diff --git a/Info.md b/Info.md index 885706f..3ea6657 100644 --- a/Info.md +++ b/Info.md @@ -37,7 +37,7 @@ These files are released under the very permissive [CC0 1.0 Universal](COPYING). # Details -Last updated on Sun Jun 2 16:14:50 UTC 2019 (2019-06-02T16:14:50+00:00). +Last updated on Sun Jun 2 16:24:13 UTC 2019 (2019-06-02T16:24:13+00:00). Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [0bddcaf9](https://github.com/SymbiFlow/prjxray/commit/0bddcaf90872d961f6aaf21848cb97c3777ff307). @@ -674,119 +674,119 @@ Results have checksums; * [`8e5baf846e629316cefb781c26c09b6a39ca509d03dd381967c3e92f429dbda3 ./kintex7/site_type_TIEOFF.json`](./kintex7/site_type_TIEOFF.json) * [`4a52214be0712e1f5e3746c304d3299fd2bfa9e578956df1d6fcd6128614da12 ./kintex7/site_type_USR_ACCESS.json`](./kintex7/site_type_USR_ACCESS.json) * [`f711f285e16aa11d4827ce8504e9413c8ccf87f9f86d108740738ae6cbb4f388 ./kintex7/site_type_XADC.json`](./kintex7/site_type_XADC.json) - * [`0bfdad62f04128ca4d469aa18b179cbd3bf78e40c6af50450c9ca85bfffd746f ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json) - * [`fd0b3b31118249e66193fa06633a58aa5d86820bed16d3f85497b886d2282845 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json) - * [`23af85ab67092eb90d6b05c3bff539499494eaecb07b5063baa2aa494063a1ec ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json) - * [`3f080d03ca1d85aa81c2bae209cb401b8dcddd6e115ea8d16d735f2b4e6fc892 ./kintex7/tile_type_BRAM_R.json`](./kintex7/tile_type_BRAM_R.json) - * [`29e4879a736ff9d43178ba3887ba47b8f1190464dabf4eef7c8fe8d8d23647c2 ./kintex7/tile_type_BRKH_BRAM.json`](./kintex7/tile_type_BRKH_BRAM.json) - * [`fccd1abee620b9dc48534d82af9c84d7e4fb9f2fbeaa0d8bbef1ddab5d2d91c5 ./kintex7/tile_type_BRKH_B_TERM_INT.json`](./kintex7/tile_type_BRKH_B_TERM_INT.json) - * [`1adbede824487b01b77eed4443ff5434c9473a067dae3c620df3ccca800951ac ./kintex7/tile_type_BRKH_CLB.json`](./kintex7/tile_type_BRKH_CLB.json) - * [`d036cb35cb1bb3237b76f2e755fd3e5902e4588b03e565e4c01ecaa6429457fa ./kintex7/tile_type_BRKH_CLK.json`](./kintex7/tile_type_BRKH_CLK.json) - * [`ec60392fdf039d697e2de0b6c856d118a52ac7fb5bc50da206802f98a8967ea6 ./kintex7/tile_type_BRKH_CMT.json`](./kintex7/tile_type_BRKH_CMT.json) - * [`721f0a9fab25908b7ae0da9b94903a8ca1cb63d42dc5119d7b143309d27156fd ./kintex7/tile_type_BRKH_DSP_L.json`](./kintex7/tile_type_BRKH_DSP_L.json) - * [`db175274054c15c1cf7093a5117628fb30f27ddd50a29eabcc894e39236f95d8 ./kintex7/tile_type_BRKH_DSP_R.json`](./kintex7/tile_type_BRKH_DSP_R.json) - * [`47d42da782610f63cf7d094ca01bdd72d632b2f7f145a942cf2ceba1dfacdc53 ./kintex7/tile_type_BRKH_GTX.json`](./kintex7/tile_type_BRKH_GTX.json) - * [`68c36646e682266cb3aecade1627160b22112d72b5859f4aae3cd32df488422a ./kintex7/tile_type_BRKH_INT.json`](./kintex7/tile_type_BRKH_INT.json) - * [`0c29262ad6e32786f23197bd603491be251278fc1a0806527e8c164a4aa269aa ./kintex7/tile_type_BRKH_TERM_INT.json`](./kintex7/tile_type_BRKH_TERM_INT.json) - * [`b3700d8432a5ea4375fab4419bba143bc79dfd137a7110117ea085d79a2dd766 ./kintex7/tile_type_B_TERM_INT.json`](./kintex7/tile_type_B_TERM_INT.json) - * [`606581f9ab6d5c8ded71371ea6806e741b0739e5e32e69c503e4ebddc9544ec9 ./kintex7/tile_type_CFG_CENTER_BOT.json`](./kintex7/tile_type_CFG_CENTER_BOT.json) - * [`820a133d2cdab23ca7c64570daa391e3329826759fa82b2d12914878676274ce ./kintex7/tile_type_CFG_CENTER_MID.json`](./kintex7/tile_type_CFG_CENTER_MID.json) - * [`cc6b420c4804236a1b2928e5c86cfa6f6143b93843e40081d14c2bfd5d5e76a8 ./kintex7/tile_type_CFG_CENTER_TOP.json`](./kintex7/tile_type_CFG_CENTER_TOP.json) - * [`0cf36c0ab629c583c01ae9efa04093e0644da71b7b0dfbc175dfcf9ed56650d5 ./kintex7/tile_type_CLBLL_L.json`](./kintex7/tile_type_CLBLL_L.json) - * [`3607f851807c3b420d21b4fe0c0b26b91db19d1384ba39d45f4c771f7251544e ./kintex7/tile_type_CLBLL_R.json`](./kintex7/tile_type_CLBLL_R.json) - * [`8f91f81d6f549d0f728dbab89baca64bae44491b1b0df30ae6ca4193b6eed951 ./kintex7/tile_type_CLBLM_L.json`](./kintex7/tile_type_CLBLM_L.json) - * [`50812dbe755a110f8e33285728a9b565d46d1e71e76e63085fc6d1dea4f4dee7 ./kintex7/tile_type_CLBLM_R.json`](./kintex7/tile_type_CLBLM_R.json) - * [`3ab28fa68486317ac22e260c8d0ac81bcccc0b214cff21b66cda2cf0974d62bb ./kintex7/tile_type_CLK_BUFG_BOT_R.json`](./kintex7/tile_type_CLK_BUFG_BOT_R.json) - * [`7e7b949435c6724c886ab674148e7a241d7761b63d8b700fbeb2b3f4105329bb ./kintex7/tile_type_CLK_BUFG_REBUF.json`](./kintex7/tile_type_CLK_BUFG_REBUF.json) - * [`b1fdae383da0691975b3836a0a66fa566165de094e4bd416d664dc32f2d010c8 ./kintex7/tile_type_CLK_BUFG_TOP_R.json`](./kintex7/tile_type_CLK_BUFG_TOP_R.json) - * [`9900c1d7c03b75bb765c57b00b20fbefd09efeccb325afba72901b941d5db0de ./kintex7/tile_type_CLK_FEED.json`](./kintex7/tile_type_CLK_FEED.json) - * [`fa0923a2169819ecc93697c7255aef24e9dbee2a3c5d8c1df3f86956e0bc8b08 ./kintex7/tile_type_CLK_HROW_BOT_R.json`](./kintex7/tile_type_CLK_HROW_BOT_R.json) - * [`71f60f081cb9718ca95f3c004034dde427a1323ae4f71f94c68f3ecb961f1d2f ./kintex7/tile_type_CLK_HROW_TOP_R.json`](./kintex7/tile_type_CLK_HROW_TOP_R.json) - * [`3d200f97f5d0608d4577dcaf9ae59c34be18f4d1406aa71815d56327fc2a3564 ./kintex7/tile_type_CLK_MTBF2.json`](./kintex7/tile_type_CLK_MTBF2.json) - * [`0163ab8305f14d439e303fc072bf980549efd65c42494e468bc2b2e0bd3ff0a6 ./kintex7/tile_type_CLK_PMV.json`](./kintex7/tile_type_CLK_PMV.json) - * [`1e08a2d1f2c7e0ec12b0eec202c3759fbfc82fab01b9d0b5d1658299d8ac5506 ./kintex7/tile_type_CLK_PMV2.json`](./kintex7/tile_type_CLK_PMV2.json) - * [`bf52b93861ca5856dab593dde196a21ab8a9522b4eb58f13fe206beaba8c78f2 ./kintex7/tile_type_CLK_PMV2_SVT.json`](./kintex7/tile_type_CLK_PMV2_SVT.json) - * [`e7123b7dbeba2ebbf4a6ae04fb87bd114548befc9bb812d7bf4bee3401aa44fa ./kintex7/tile_type_CLK_PMVIOB.json`](./kintex7/tile_type_CLK_PMVIOB.json) - * [`42236b4ea5a40883822299aef2c5eb6ef2adb30c715145a9c36c5dd9e84e102e ./kintex7/tile_type_CLK_TERM.json`](./kintex7/tile_type_CLK_TERM.json) - * [`f985c5c1c1186eb314e1bd727b4195b88f69739fcb991efbafee963310b880f9 ./kintex7/tile_type_CMT_FIFO_L.json`](./kintex7/tile_type_CMT_FIFO_L.json) - * [`2209bb569563a8f748c4f54f28a5d870d9f873d1403cefc3c433174bb68d74f2 ./kintex7/tile_type_CMT_FIFO_R.json`](./kintex7/tile_type_CMT_FIFO_R.json) - * [`a3cce946e4fc43015cc0e0d5ed2305bbf1da982807029d4a72a5f3f76cb6e756 ./kintex7/tile_type_CMT_PMV.json`](./kintex7/tile_type_CMT_PMV.json) - * [`9207ebd19f94b6a3a9d8ea08f1fe78dcf592d3b5b5f541694a23d5dc1a9163e3 ./kintex7/tile_type_CMT_PMV_L.json`](./kintex7/tile_type_CMT_PMV_L.json) - * [`63d8187207a325d174e8d509014200531f3e11236e5064c2675871ca42fbbffa ./kintex7/tile_type_CMT_TOP_L_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_B.json) - * [`129c5c28dee6d7cc79263d280a391c07b5db326124ad1e973582643d9eadff3a ./kintex7/tile_type_CMT_TOP_L_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_T.json) - * [`3c645c7e32529af66b278c8c06734bb052d1be00ff801772d28147b1e62da2ff ./kintex7/tile_type_CMT_TOP_L_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_B.json) - * [`e008d249e1f1dafa57e4ac276826c60e24b7fd29ec4e5acafd078c0604631afc ./kintex7/tile_type_CMT_TOP_L_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_T.json) - * [`5b45ef7b0d9a366440da629a02330f51b6210652842fe723369e88f31df5d732 ./kintex7/tile_type_CMT_TOP_R_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_B.json) - * [`6260182cedf2857372997d8b9a9b3d28504931d1c7ff5176d718dd44935354f0 ./kintex7/tile_type_CMT_TOP_R_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_T.json) - * [`526212df7cbe1dbc56b70ac0dc0e93823cb238fcbf0c223dd82e88fac47e329f ./kintex7/tile_type_CMT_TOP_R_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_B.json) - * [`816d810709c3f54a33774c6a9acefe472cac1e5748d306e692524007b699ee35 ./kintex7/tile_type_CMT_TOP_R_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_T.json) - * [`4ddd2c3e96995a4acf4320877f3ab6ade22d9b475eb8b2e46cb64c325b92e386 ./kintex7/tile_type_DSP_L.json`](./kintex7/tile_type_DSP_L.json) - * [`b7f2ec5fcaf13becd7a73baa9271370dd80ccc24a1dc52bbe4ec2a450aabd7ad ./kintex7/tile_type_DSP_R.json`](./kintex7/tile_type_DSP_R.json) - * [`664e29cdabfbec863560328a0833a91459c17dc70ea679128d602c805825ccd7 ./kintex7/tile_type_GTX_CHANNEL_0.json`](./kintex7/tile_type_GTX_CHANNEL_0.json) - * [`073c39fafe9d8dacb4e002d50832d5978ca20f4503434fdee83c7132cd338128 ./kintex7/tile_type_GTX_CHANNEL_1.json`](./kintex7/tile_type_GTX_CHANNEL_1.json) - * [`11692719d238fce3ad91ba0ba92a0d4216b24eb6da2f17e988f3145b08c11ddf ./kintex7/tile_type_GTX_CHANNEL_2.json`](./kintex7/tile_type_GTX_CHANNEL_2.json) - * [`06f886342ce6151e496b553027ec5930c28f972f6cfa4edf669ef46cb7958843 ./kintex7/tile_type_GTX_CHANNEL_3.json`](./kintex7/tile_type_GTX_CHANNEL_3.json) - * [`124ad9e96a57e9f949a9525366f0f2c497ef20f14e0848b465aa3215556c7825 ./kintex7/tile_type_GTX_COMMON.json`](./kintex7/tile_type_GTX_COMMON.json) - * [`b015248899232a2c9213742d7f44c597b75bb58e5f4edf03ef71119e003958d4 ./kintex7/tile_type_GTX_INT_INTERFACE.json`](./kintex7/tile_type_GTX_INT_INTERFACE.json) - * [`05eb17dc54b29fac95e4b2ac067139b528c1bc7f5cb78b672e6941a2966ec7bb ./kintex7/tile_type_HCLK_BRAM.json`](./kintex7/tile_type_HCLK_BRAM.json) - * [`307db3c561c03036e0460d24af8d435631bbacef7f81c0385f6179673d818d50 ./kintex7/tile_type_HCLK_CLB.json`](./kintex7/tile_type_HCLK_CLB.json) - * [`318c1785d2059191307e3e12efc326475b060106d048550bfd2a7a48381257d0 ./kintex7/tile_type_HCLK_CMT.json`](./kintex7/tile_type_HCLK_CMT.json) - * [`4af6db5c406dd683670c77fe2dbfcfd64b0d079e59e3082cfc4e578789cddf45 ./kintex7/tile_type_HCLK_CMT_L.json`](./kintex7/tile_type_HCLK_CMT_L.json) - * [`cbcd13d3b6a78888a73e22e1e33e56c80b5fcb23c4d1baf938b4b6daa02173f7 ./kintex7/tile_type_HCLK_DSP_L.json`](./kintex7/tile_type_HCLK_DSP_L.json) - * [`dacc707f9e2db1d6752f833cf0559536423baf915a848b3ff641373f4762793f ./kintex7/tile_type_HCLK_DSP_R.json`](./kintex7/tile_type_HCLK_DSP_R.json) - * [`c1d33fee3af7b2ba311bad50d6f8b771303ebd8241e617ec638b1fcb8d2c4ee0 ./kintex7/tile_type_HCLK_FEEDTHRU_1.json`](./kintex7/tile_type_HCLK_FEEDTHRU_1.json) - * [`0e991e5fc85e54835a7de8da8456ee1300d97d798fb12d16c521a9163500a20c ./kintex7/tile_type_HCLK_FEEDTHRU_2.json`](./kintex7/tile_type_HCLK_FEEDTHRU_2.json) - * [`1631fbdf6e3158d6e372508b55e32e3e638b270e0ca606359b4ad060f6337cea ./kintex7/tile_type_HCLK_FIFO_L.json`](./kintex7/tile_type_HCLK_FIFO_L.json) - * [`7897a72ad8df7a9561af0cd339d07b78fda2d8978771ca314edb158eb6bf21d5 ./kintex7/tile_type_HCLK_GTX.json`](./kintex7/tile_type_HCLK_GTX.json) - * [`6a66fa18fdad81ae738e61f650066415a2adc7d15b15ab87b5080faff3edb9e1 ./kintex7/tile_type_HCLK_INT_INTERFACE.json`](./kintex7/tile_type_HCLK_INT_INTERFACE.json) - * [`51fbaa9613664a08814f372c5791189ceb855720997334f55e52872cc6d4c46f ./kintex7/tile_type_HCLK_IOB.json`](./kintex7/tile_type_HCLK_IOB.json) - * [`ac2bda946bf493ddaa51c21c4cec8295317ce822692f8276725a4bc36618c0f1 ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json) - * [`5e15b63a15fd7864d838d448599718e5f82e8caafa8fd316eb19374e20c0d89c ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json) - * [`2c39172c06f58c30f92d140c6c7c060777b1b3f397a23b9cf82a41a656da82ef ./kintex7/tile_type_HCLK_L.json`](./kintex7/tile_type_HCLK_L.json) - * [`4270980b733f54a17a34b5259579fd2e42d38efeeb42518967362c599def37c2 ./kintex7/tile_type_HCLK_L_BOT_UTURN.json`](./kintex7/tile_type_HCLK_L_BOT_UTURN.json) - * [`782d62d7a78ca8282570a945739057b1801795271764120ff4f20696a36e9354 ./kintex7/tile_type_HCLK_R.json`](./kintex7/tile_type_HCLK_R.json) - * [`0bc6c1727558cc3dfe8ee21ec2f2b03e6f0f362d3948b2afed0217e1fd1b2d32 ./kintex7/tile_type_HCLK_R_BOT_UTURN.json`](./kintex7/tile_type_HCLK_R_BOT_UTURN.json) - * [`5b459ee856bd5417b0c61831120d27cebb7f5c6ae4952470bdc6dc6bad6c5b49 ./kintex7/tile_type_HCLK_TERM.json`](./kintex7/tile_type_HCLK_TERM.json) - * [`ccc33563773bbe6157c016214acd36162575086bfa661e8fa53885a58dd2d43d ./kintex7/tile_type_HCLK_TERM_GTX.json`](./kintex7/tile_type_HCLK_TERM_GTX.json) - * [`e706c7cf142b8e806283d3cf030f89e30149bad7b2f156e739e2f41247922792 ./kintex7/tile_type_HCLK_VBRK.json`](./kintex7/tile_type_HCLK_VBRK.json) - * [`acabe2c19ef9286451b67f889608af10b57c4149be795c7b9e96c700e673741a ./kintex7/tile_type_HCLK_VFRAME.json`](./kintex7/tile_type_HCLK_VFRAME.json) - * [`fe9a6b9109c94abc0860142566f1d6c292b5313f2ebe641dbd3f4d41671d05a2 ./kintex7/tile_type_INT_FEEDTHRU_1.json`](./kintex7/tile_type_INT_FEEDTHRU_1.json) - * [`1ff618718c404f469eed1fc7499db1a7bcfa90bf152b317b07511d1e070d7622 ./kintex7/tile_type_INT_FEEDTHRU_2.json`](./kintex7/tile_type_INT_FEEDTHRU_2.json) - * [`08db2bc2bc634b16af1988b445a896ffdbe75e2275647657dd44dbc9e436ec9f ./kintex7/tile_type_INT_INTERFACE_L.json`](./kintex7/tile_type_INT_INTERFACE_L.json) - * [`3f04e660e8a477ae99b5349c70d4bb420ed61c823ead17915a2900cc2210ad46 ./kintex7/tile_type_INT_INTERFACE_R.json`](./kintex7/tile_type_INT_INTERFACE_R.json) - * [`cc47a410209b8beb6140d0216de2b298547116a90f4cd7cf9674785e838f4c36 ./kintex7/tile_type_INT_L.json`](./kintex7/tile_type_INT_L.json) - * [`784502f54f667eb147924b061bc62829588d0e43673f32fd9d45113b6f740457 ./kintex7/tile_type_INT_R.json`](./kintex7/tile_type_INT_R.json) - * [`ffedd570b50dfb9fdd8d1e5065da17d53319cda7e849848ec88d352c767e2d59 ./kintex7/tile_type_IO_INT_INTERFACE_L.json`](./kintex7/tile_type_IO_INT_INTERFACE_L.json) - * [`cf049a6c528634761c6067610f50110102caadc782a33b855f4059df8ed064d9 ./kintex7/tile_type_IO_INT_INTERFACE_R.json`](./kintex7/tile_type_IO_INT_INTERFACE_R.json) - * [`cef7db2efcd92f19a0775c1833e0dd23b3dcb4d016fa8516b7e69c4a658ac630 ./kintex7/tile_type_LIOB33.json`](./kintex7/tile_type_LIOB33.json) - * [`49276f934ed32b1ec0b2eac19b67178119fbc5674d022eec1de5be08b07c4e72 ./kintex7/tile_type_LIOB33_SING.json`](./kintex7/tile_type_LIOB33_SING.json) - * [`801140f147650d8b443e46fa51793181c264bc8d92c8767bb875ae838ae4a062 ./kintex7/tile_type_LIOI3.json`](./kintex7/tile_type_LIOI3.json) - * [`c2932bc581e8b38a7373f5a9a555263ce7aa9d96ad9c4e5675c599b11d86b67b ./kintex7/tile_type_LIOI3_SING.json`](./kintex7/tile_type_LIOI3_SING.json) - * [`b69c2ea84f06bfed085b2f50e1f4dd43033dd5f34ca19e67da42d6c80317cd23 ./kintex7/tile_type_LIOI3_TBYTESRC.json`](./kintex7/tile_type_LIOI3_TBYTESRC.json) - * [`44cf5e287a63932e7b6809f4fc3245ff380ae8ad24ed9b53b8cee45b719517b6 ./kintex7/tile_type_LIOI3_TBYTETERM.json`](./kintex7/tile_type_LIOI3_TBYTETERM.json) - * [`5c6ddebe6aef58fa126d2f1121f2c415737d513b90169c393dfcbe2655251716 ./kintex7/tile_type_L_TERM_INT.json`](./kintex7/tile_type_L_TERM_INT.json) - * [`0ba8ee53d9143f34acda567dc07fe65317ced21eac6b84223de2620630c285fa ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json) - * [`ecd8853d71cb85a9234f41c12f81e22a91dc2623947c07c9ad5d6a07a1d4e9b7 ./kintex7/tile_type_MONITOR_MID_FUJI2.json`](./kintex7/tile_type_MONITOR_MID_FUJI2.json) - * [`687681f194bdd1c2642f07d0ef1e95fa1f4de557bc4ea3d098b8224e982eda69 ./kintex7/tile_type_MONITOR_TOP_FUJI2.json`](./kintex7/tile_type_MONITOR_TOP_FUJI2.json) - * [`880cdcd99af7ea01e4ee142860e0900c6c3503da3b3582837fedba1a2cafa852 ./kintex7/tile_type_NULL.json`](./kintex7/tile_type_NULL.json) - * [`a1553083f3d3f703f6fdc25b2e1b5b62e2a68d4371c4edcf3cb3aa8d8e99ec87 ./kintex7/tile_type_PCIE_BOT.json`](./kintex7/tile_type_PCIE_BOT.json) - * [`3e075fbce2e39f99504b7e799de6aa1146aafe32d545b0c7ba791d93751ac58b ./kintex7/tile_type_PCIE_INT_INTERFACE_L.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_L.json) - * [`7640289b2a0635eba0172f8e37e452a53912620fe00572cf57fe4ac4ae0db2be ./kintex7/tile_type_PCIE_INT_INTERFACE_R.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_R.json) - * [`944d9c69913b23cac150f0c80c14284d57fab43f69202a6cc63afaddce23221b ./kintex7/tile_type_PCIE_NULL.json`](./kintex7/tile_type_PCIE_NULL.json) - * [`dc29a2768d5aafea58e032f3d303e34e5e7dae896979ef2fc2fe70165b42cf3e ./kintex7/tile_type_PCIE_TOP.json`](./kintex7/tile_type_PCIE_TOP.json) - * [`0e43d927111f9707d0d2bde59253087eb358d93bed0ad3d45488d8025f45c453 ./kintex7/tile_type_RIOB18.json`](./kintex7/tile_type_RIOB18.json) - * [`143e828e00241ab782be5051c26bc83b78e87f82977e5c07d943778e4603f8f4 ./kintex7/tile_type_RIOB18_SING.json`](./kintex7/tile_type_RIOB18_SING.json) - * [`b6feb57ff8a4a680573e34cad591dd8806841c18fe6d10a13791f91c7ce947f8 ./kintex7/tile_type_RIOI.json`](./kintex7/tile_type_RIOI.json) - * [`f7782f69f88c344a504d2e8b48459cd0460835d9dcce13f229a84db8eed36b50 ./kintex7/tile_type_RIOI_SING.json`](./kintex7/tile_type_RIOI_SING.json) - * [`ceda94b5277ecf7224bcd4e1d323bb136245a547546d8b7479bee9957dfd1a5d ./kintex7/tile_type_RIOI_TBYTESRC.json`](./kintex7/tile_type_RIOI_TBYTESRC.json) - * [`3e40d2570c0019c986f4fd163cadc24f48d2557a7894af2af5994924f7a3158b ./kintex7/tile_type_RIOI_TBYTETERM.json`](./kintex7/tile_type_RIOI_TBYTETERM.json) - * [`16627ffc9c74acf89474ad03993367d2210f40d4ab07a8c71c98d9ad652f2ca8 ./kintex7/tile_type_R_TERM_INT.json`](./kintex7/tile_type_R_TERM_INT.json) - * [`fd664b568212b0479342de300f8efc07e8b521960fbb4b9abacb71336fca773b ./kintex7/tile_type_R_TERM_INT_GTX.json`](./kintex7/tile_type_R_TERM_INT_GTX.json) - * [`19503481fb531f7ddc5f92fdc7c97a817ce1cf550e128604041c771f2234b7fa ./kintex7/tile_type_TERM_CMT.json`](./kintex7/tile_type_TERM_CMT.json) - * [`f5ebbeee5575e5fbc1fb5d532f021e4ee8647de21b3874caac655d8c849a9ff3 ./kintex7/tile_type_T_TERM_INT.json`](./kintex7/tile_type_T_TERM_INT.json) - * [`dee783006fa5b5964d20457323cad59171a60397d730e9fe0840389587695727 ./kintex7/tile_type_VBRK.json`](./kintex7/tile_type_VBRK.json) - * [`04409fb1eb974ee5af7e8115bf16aacfd4bda61094c7c4644cc020762a45f6c8 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json) - * [`004efcd7f9e172780ca7b8c379ec329bcfc52f86beaa1d997f41dbef7ac4a242 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json) + * [`a8ea5587ba7e33f8038ef78e82ad9756a6554d73e71837e5c853121642976d42 ./kintex7/tile_type_BRAM_INT_INTERFACE_L.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_L.json) + * [`6b34993d29572a9fb89885dd9945986a567c294c9e229a7a2ec89158fc2c0d46 ./kintex7/tile_type_BRAM_INT_INTERFACE_R.json`](./kintex7/tile_type_BRAM_INT_INTERFACE_R.json) + * [`14d04dd5afe327a6381bf40f7956beddc81520ffab0a4cf49cd83a0e6a1454b7 ./kintex7/tile_type_BRAM_L.json`](./kintex7/tile_type_BRAM_L.json) + * [`39d9d8696e0b4d80eb005e98c819a31f25b0f3c12271bb8a176a660a1d8c8572 ./kintex7/tile_type_BRAM_R.json`](./kintex7/tile_type_BRAM_R.json) + * [`5fed21fa51d7da12161c39f1f348bdf80b08df28c01d106959e9125c2bbc2ea6 ./kintex7/tile_type_BRKH_BRAM.json`](./kintex7/tile_type_BRKH_BRAM.json) + * [`80a168dd7caa6ab7c91694aca60b15a6bdacf88cf66cdbea5fcc15483c52a448 ./kintex7/tile_type_BRKH_B_TERM_INT.json`](./kintex7/tile_type_BRKH_B_TERM_INT.json) + * [`f3c6f6f895b114fce5aa917dad371892926a80f34cac8e7a084561ad2fe22579 ./kintex7/tile_type_BRKH_CLB.json`](./kintex7/tile_type_BRKH_CLB.json) + * [`f4a1d3eac4ed9046f4b4df9d925b62080d70ac295cd492c008bdd543b5714a7f ./kintex7/tile_type_BRKH_CLK.json`](./kintex7/tile_type_BRKH_CLK.json) + * [`1a81bf9fbc72eb95ba686a6f0ebdcf5afd305ebc4c45a22d38857e83933ce3c1 ./kintex7/tile_type_BRKH_CMT.json`](./kintex7/tile_type_BRKH_CMT.json) + * [`7865b3f082f74329f8d795eda8497ab16f35436dec393ec60fb827127e6858e7 ./kintex7/tile_type_BRKH_DSP_L.json`](./kintex7/tile_type_BRKH_DSP_L.json) + * [`7b3184855f2fcaf13bc7a835b14fd35bc11c72841f2240e51703434ead3e2da3 ./kintex7/tile_type_BRKH_DSP_R.json`](./kintex7/tile_type_BRKH_DSP_R.json) + * [`d0368330d5b3fc313adaa13ee71bfd8488fd8278d19a0b8bc822ac555b314e2e ./kintex7/tile_type_BRKH_GTX.json`](./kintex7/tile_type_BRKH_GTX.json) + * [`fe71fb340a716189565a39cd184b6e391c3d6538813b59b2630d428a10e80143 ./kintex7/tile_type_BRKH_INT.json`](./kintex7/tile_type_BRKH_INT.json) + * [`8e367e3559ad9e001e3539707711c3931086344d265fddd7f9edff7d65496229 ./kintex7/tile_type_BRKH_TERM_INT.json`](./kintex7/tile_type_BRKH_TERM_INT.json) + * [`569bab17633b363bedb66f1e55da4e36edac937a6653933863ee0a95832c4ccf ./kintex7/tile_type_B_TERM_INT.json`](./kintex7/tile_type_B_TERM_INT.json) + * [`01e57f3389c31a60feef5f649d5deba442f5ae1d3c45220492fda1b02c581f15 ./kintex7/tile_type_CFG_CENTER_BOT.json`](./kintex7/tile_type_CFG_CENTER_BOT.json) + * [`6347c77d4c2cf8c51afa1846cf7d1a9ec37f7f991daa050c154e267648fc5542 ./kintex7/tile_type_CFG_CENTER_MID.json`](./kintex7/tile_type_CFG_CENTER_MID.json) + * [`2173444ec4f713e217c19fcbd57143bf39da43d0e5545e49e36bbc2db39c12ac ./kintex7/tile_type_CFG_CENTER_TOP.json`](./kintex7/tile_type_CFG_CENTER_TOP.json) + * [`80be96541d69616c67542c1bae745494a6857b913211aa3372ff778a7e722860 ./kintex7/tile_type_CLBLL_L.json`](./kintex7/tile_type_CLBLL_L.json) + * [`67932eb5bcd1fe98aec664cbeb383948733980452005537bd34c06e921bd9ea5 ./kintex7/tile_type_CLBLL_R.json`](./kintex7/tile_type_CLBLL_R.json) + * [`22e5e1c26e6f56eb7898aae4284c92296c4dc0a5d80c33d02961dc483604c701 ./kintex7/tile_type_CLBLM_L.json`](./kintex7/tile_type_CLBLM_L.json) + * [`c9a17a56a830ea1eedab1875168241168d55b853a0cdaa5aa4801b12e60ef1d3 ./kintex7/tile_type_CLBLM_R.json`](./kintex7/tile_type_CLBLM_R.json) + * [`5f780a0b8a1be7ccd688cd1ec9d55108f4a1eb89484205da93ecab2a53ea4481 ./kintex7/tile_type_CLK_BUFG_BOT_R.json`](./kintex7/tile_type_CLK_BUFG_BOT_R.json) + * [`a2670c56315bfa6d2c7b264a00bd9f94fc57707070fafa016723052c2ea6c7c7 ./kintex7/tile_type_CLK_BUFG_REBUF.json`](./kintex7/tile_type_CLK_BUFG_REBUF.json) + * [`2e4e2e43d45c9af55b2b3bb50b86cf313a15dfca42d68f12bc572b4da90d0cc2 ./kintex7/tile_type_CLK_BUFG_TOP_R.json`](./kintex7/tile_type_CLK_BUFG_TOP_R.json) + * [`4511dcbf42306a70f8413845560367a11c4ebef76732738cfe339cc7cbf7a332 ./kintex7/tile_type_CLK_FEED.json`](./kintex7/tile_type_CLK_FEED.json) + * [`7d369c12b8c05ecb9c77ec27b098091fe8defb3e092dcc768522433ae2e7ff08 ./kintex7/tile_type_CLK_HROW_BOT_R.json`](./kintex7/tile_type_CLK_HROW_BOT_R.json) + * [`b508fd42f8ae1465caa6c8f7eee76f8bc2544d2d55df6879c8af3f86e6d83ce9 ./kintex7/tile_type_CLK_HROW_TOP_R.json`](./kintex7/tile_type_CLK_HROW_TOP_R.json) + * [`0ab174146714c57d124b00d710e4b61451fd7616330659df7854542a9266cd3f ./kintex7/tile_type_CLK_MTBF2.json`](./kintex7/tile_type_CLK_MTBF2.json) + * [`7465e9e40a7564598e859620faf75bc9c230b5d41a6141c0fc58f1ea7fce7bf2 ./kintex7/tile_type_CLK_PMV.json`](./kintex7/tile_type_CLK_PMV.json) + * [`c7fa3a115807b7a7e26648bfd754df16098aeb40d835cf03355d8ff361f25872 ./kintex7/tile_type_CLK_PMV2.json`](./kintex7/tile_type_CLK_PMV2.json) + * [`b41f19caae976764c738da165f14ee36df6d6c99296fcb829e359b4dce884367 ./kintex7/tile_type_CLK_PMV2_SVT.json`](./kintex7/tile_type_CLK_PMV2_SVT.json) + * [`fbe2edf0894ee5fe23f5aec0e34dce567a2cdaa22805ac6ac1f834b52259522b ./kintex7/tile_type_CLK_PMVIOB.json`](./kintex7/tile_type_CLK_PMVIOB.json) + * [`1dfd3414cd2cd1225ae057f91a904dbac0d868e8a674066e1a0c180743524b9c ./kintex7/tile_type_CLK_TERM.json`](./kintex7/tile_type_CLK_TERM.json) + * [`b0435291b5750a18732a7f25b449918e807356a6df4d45950bc5a5a5a2a65ed2 ./kintex7/tile_type_CMT_FIFO_L.json`](./kintex7/tile_type_CMT_FIFO_L.json) + * [`949b5a4306b1cfdb66e6c6cc32a387c3bda2dc4083ffcbe2178de33194f2b201 ./kintex7/tile_type_CMT_FIFO_R.json`](./kintex7/tile_type_CMT_FIFO_R.json) + * [`386ea59114877567b21f6112c7d1926517188561980d9fb67a92aaf5351c03b0 ./kintex7/tile_type_CMT_PMV.json`](./kintex7/tile_type_CMT_PMV.json) + * [`c374c731c31670db0ad18b2de06d784fe85d37e9c68ae482cf64710e6a100bd1 ./kintex7/tile_type_CMT_PMV_L.json`](./kintex7/tile_type_CMT_PMV_L.json) + * [`e6ee3e5354b3f9988f5aeed97ec838713b2be72841e45ce2c26364269dce0dfc ./kintex7/tile_type_CMT_TOP_L_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_B.json) + * [`086e7f48c106fc528b1bd06d3b560f975cc79507b5515b7af83d0c821c9f85f9 ./kintex7/tile_type_CMT_TOP_L_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_L_LOWER_T.json) + * [`da1c4e3efcf3d0f42fca26fbed65b6c766ff1ad556e1a71c77aa5bd6229e5ac3 ./kintex7/tile_type_CMT_TOP_L_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_B.json) + * [`a3ed7b61833b696d5331393737f6e402eaae23c296f13c0a1e20ca46bc0ebec6 ./kintex7/tile_type_CMT_TOP_L_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_L_UPPER_T.json) + * [`3b9fd416da245057381ccba21d6a7dfccebb497d4d05cb9e8bd576a969f8fc30 ./kintex7/tile_type_CMT_TOP_R_LOWER_B.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_B.json) + * [`44f17bf89883d1dec8a8a2d5c019401e34c4495b9afc33fafd80738ac5f1f230 ./kintex7/tile_type_CMT_TOP_R_LOWER_T.json`](./kintex7/tile_type_CMT_TOP_R_LOWER_T.json) + * [`150c4229c18c095d67a528ebaa0db7480b0b14d37de01e0d29ba18afcdd5b7c9 ./kintex7/tile_type_CMT_TOP_R_UPPER_B.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_B.json) + * [`254a883b551b930dab29e4364aee037d58ff13f319d7cfeb4a2ba62548a7c2d2 ./kintex7/tile_type_CMT_TOP_R_UPPER_T.json`](./kintex7/tile_type_CMT_TOP_R_UPPER_T.json) + * [`df75c9242a1b4c683186356b0ea6a03cf72e92af9166a37fb395586ea4605030 ./kintex7/tile_type_DSP_L.json`](./kintex7/tile_type_DSP_L.json) + * [`bcfc5df6734b02aa8877c6e994d355cdc2984a311ac23465193cd75833e83596 ./kintex7/tile_type_DSP_R.json`](./kintex7/tile_type_DSP_R.json) + * [`52f24a994888ab0bb43cfa2fb4f0463481c531ec14d3375ec240675fb756a7d5 ./kintex7/tile_type_GTX_CHANNEL_0.json`](./kintex7/tile_type_GTX_CHANNEL_0.json) + * [`d02f4471b93133daa573201cb9b7fde66dade895e3825d9cd8ec5009c473e9fd ./kintex7/tile_type_GTX_CHANNEL_1.json`](./kintex7/tile_type_GTX_CHANNEL_1.json) + * [`686d01981414dfce32666b73668cb55f8dda65791d1794b9413bbf260b5d6cca ./kintex7/tile_type_GTX_CHANNEL_2.json`](./kintex7/tile_type_GTX_CHANNEL_2.json) + * [`e06a5c893b70cce666e65d341eaebfb35a1a527a5c2ce3d54847d0f71a5aeb23 ./kintex7/tile_type_GTX_CHANNEL_3.json`](./kintex7/tile_type_GTX_CHANNEL_3.json) + * [`180ba9d9bfc9d04acc6cd87635d14ca5ac8b5e35cb88450bd0a798bbbd93a6bb ./kintex7/tile_type_GTX_COMMON.json`](./kintex7/tile_type_GTX_COMMON.json) + * [`dbe57d834199a49251d5308ab4ca4ba608520244e07951ec61b7695fd6809879 ./kintex7/tile_type_GTX_INT_INTERFACE.json`](./kintex7/tile_type_GTX_INT_INTERFACE.json) + * [`fe27db14b76b461aa9b21f596df89860456b63da3d040bc1491cc5ebcd9e21c6 ./kintex7/tile_type_HCLK_BRAM.json`](./kintex7/tile_type_HCLK_BRAM.json) + * [`c2fac81056c91c0a8dec5b73ac5f1768f64ba6dad36c450b46577122b29605f2 ./kintex7/tile_type_HCLK_CLB.json`](./kintex7/tile_type_HCLK_CLB.json) + * [`6ad47223983ea6de90597355d91a1af11eb126b9e47c14e6fa343eb9b64e7a18 ./kintex7/tile_type_HCLK_CMT.json`](./kintex7/tile_type_HCLK_CMT.json) + * [`44a5494ba30b86162eaea1094a76f6162b6424bc77d063b109189c15eed4397d ./kintex7/tile_type_HCLK_CMT_L.json`](./kintex7/tile_type_HCLK_CMT_L.json) + * [`a3fb98d8eef8e9a390467dd179badff1b314e615ed21803aad4d7c474aade627 ./kintex7/tile_type_HCLK_DSP_L.json`](./kintex7/tile_type_HCLK_DSP_L.json) + * [`b1fe93376b654169a85a14c8f99257e694927986d967c0ef7b83c614b440daf6 ./kintex7/tile_type_HCLK_DSP_R.json`](./kintex7/tile_type_HCLK_DSP_R.json) + * [`7756e9585aa1e0eb50790b1efa4984474fe16fe01d2a2d243f42d7f36123c0ac ./kintex7/tile_type_HCLK_FEEDTHRU_1.json`](./kintex7/tile_type_HCLK_FEEDTHRU_1.json) + * [`bce1ef5bdc632645054a57fa0bc022a3f3c85717a80c1daba3eb9f777836333d ./kintex7/tile_type_HCLK_FEEDTHRU_2.json`](./kintex7/tile_type_HCLK_FEEDTHRU_2.json) + * [`20ffd03177494bd2a2c4565268c345b76802bfbdf711cf863626c104778991ba ./kintex7/tile_type_HCLK_FIFO_L.json`](./kintex7/tile_type_HCLK_FIFO_L.json) + * [`e99855672b287d989067b6a930d4fec25abb30f56bf1fcd2e8d27c25a81c57be ./kintex7/tile_type_HCLK_GTX.json`](./kintex7/tile_type_HCLK_GTX.json) + * [`979fb1ba45151227f96a4b15cc647fcfe3384e36a334cfadb0c60773b09eca78 ./kintex7/tile_type_HCLK_INT_INTERFACE.json`](./kintex7/tile_type_HCLK_INT_INTERFACE.json) + * [`a8a69a73ce318c397214da6c498c9dc6c322bc3682f39b1fb9ea109393ee70e7 ./kintex7/tile_type_HCLK_IOB.json`](./kintex7/tile_type_HCLK_IOB.json) + * [`9d428c5337a8d302fcbb34166e379032fd3f2551002234c895357c8c2f3c19ee ./kintex7/tile_type_HCLK_IOI.json`](./kintex7/tile_type_HCLK_IOI.json) + * [`34b832a8549a75febebabd9f864b3ceb94cd1452587535311a0f33588531e522 ./kintex7/tile_type_HCLK_IOI3.json`](./kintex7/tile_type_HCLK_IOI3.json) + * [`230a87c772c1e917dc721d2ef5dad9939760c9374debd22d9fe922b40790b992 ./kintex7/tile_type_HCLK_L.json`](./kintex7/tile_type_HCLK_L.json) + * [`c9e7bc163bd65a2cefc6eabee92e7b7dd74f3cc662133a3fa0c58bf69937d09c ./kintex7/tile_type_HCLK_L_BOT_UTURN.json`](./kintex7/tile_type_HCLK_L_BOT_UTURN.json) + * [`e796234bc695ae00805bc16943d199975c100991b6a15380c4656e703cbc8242 ./kintex7/tile_type_HCLK_R.json`](./kintex7/tile_type_HCLK_R.json) + * [`426f117eece10f0a55f79bd575a61806f855b9bb481ccf36117e5c3638119cd7 ./kintex7/tile_type_HCLK_R_BOT_UTURN.json`](./kintex7/tile_type_HCLK_R_BOT_UTURN.json) + * [`2df032665e26af5c97a814575440731c0d7b2bac733e1b0dcfe42d3870d9d1d7 ./kintex7/tile_type_HCLK_TERM.json`](./kintex7/tile_type_HCLK_TERM.json) + * [`4a8b6af1f3442ca519706c68ccd202e1d4d76704b24ab51fe9da12017ddfa1e8 ./kintex7/tile_type_HCLK_TERM_GTX.json`](./kintex7/tile_type_HCLK_TERM_GTX.json) + * [`4b43030e650607a9c5473a03827fdfbf990d241aa48f4093c71572ff86bf0183 ./kintex7/tile_type_HCLK_VBRK.json`](./kintex7/tile_type_HCLK_VBRK.json) + * [`8f70b2cefb458f2d3ff09123e58a891bd7ece80ae7cab637d738659799709318 ./kintex7/tile_type_HCLK_VFRAME.json`](./kintex7/tile_type_HCLK_VFRAME.json) + * [`432c6ad451ebf276da839671059c761584a6092cac75a4e14ff8f8de71bc923c ./kintex7/tile_type_INT_FEEDTHRU_1.json`](./kintex7/tile_type_INT_FEEDTHRU_1.json) + * [`938be9bbb0126fef543f27913c463e26edd5a8031067ff1a0e961e06823ae7f5 ./kintex7/tile_type_INT_FEEDTHRU_2.json`](./kintex7/tile_type_INT_FEEDTHRU_2.json) + * [`0448990cd30433c5b7dc4f311ff8f55ba1bce117f66212a692766d1581346c34 ./kintex7/tile_type_INT_INTERFACE_L.json`](./kintex7/tile_type_INT_INTERFACE_L.json) + * [`707a50230880c3ce41d5fe53fb64569b1718aab5aea3d425809949fd4fe21e69 ./kintex7/tile_type_INT_INTERFACE_R.json`](./kintex7/tile_type_INT_INTERFACE_R.json) + * [`52a016ca2953e50294dcff5f90578694dc01b2e69e27c2e5375dfe4cd8a74358 ./kintex7/tile_type_INT_L.json`](./kintex7/tile_type_INT_L.json) + * [`a87ac711c53a522cd58c1db7668daed57b86e9484f2721223d9752f9345b647d ./kintex7/tile_type_INT_R.json`](./kintex7/tile_type_INT_R.json) + * [`0de39aa85bfe03db0a31d4260cc8a58d95d3c7b61307e57482d50a88a996d979 ./kintex7/tile_type_IO_INT_INTERFACE_L.json`](./kintex7/tile_type_IO_INT_INTERFACE_L.json) + * [`7970ff931a4c236c1d84e41b6de012ccdce5ca0c934d7d77ca0f2fc7ee9461b6 ./kintex7/tile_type_IO_INT_INTERFACE_R.json`](./kintex7/tile_type_IO_INT_INTERFACE_R.json) + * [`98aa62625da0ec05ae1e812f5208019bf105e87a7931f81add1b612ae11f4512 ./kintex7/tile_type_LIOB33.json`](./kintex7/tile_type_LIOB33.json) + * [`53ea284ff8665577a52492330a3cef023465eaa840ab177120aa7dced3064c64 ./kintex7/tile_type_LIOB33_SING.json`](./kintex7/tile_type_LIOB33_SING.json) + * [`252b391e8ff0fe17d462d650a0e6054bcef2236d875bd4d9ca7f896ebbb22892 ./kintex7/tile_type_LIOI3.json`](./kintex7/tile_type_LIOI3.json) + * [`1970c750e44b80c7c2d754b8187f0fe1d3a78f02e058196b37ff300812475f27 ./kintex7/tile_type_LIOI3_SING.json`](./kintex7/tile_type_LIOI3_SING.json) + * [`f05c8ab849ee61a127623bea8c47fd976bb21bb695da7fc632bf8f51048ace88 ./kintex7/tile_type_LIOI3_TBYTESRC.json`](./kintex7/tile_type_LIOI3_TBYTESRC.json) + * [`bab0a5b81b839e3be5dc1b20986fcb4286d16c4f2bfaa9600c13edab1d12d865 ./kintex7/tile_type_LIOI3_TBYTETERM.json`](./kintex7/tile_type_LIOI3_TBYTETERM.json) + * [`003b6a50e4270b7f8f42ca73e70e7eab1213776224e4b61eed1493a722c4e2ba ./kintex7/tile_type_L_TERM_INT.json`](./kintex7/tile_type_L_TERM_INT.json) + * [`9d0e8cfbffd8025e972ce84e99471ea406cea89d999306df677540ad60344428 ./kintex7/tile_type_MONITOR_BOT_FUJI2.json`](./kintex7/tile_type_MONITOR_BOT_FUJI2.json) + * [`486f85e33e044c7a7f342f079b73ad70d22b0fcafd16b48cfeeda53412f8d1b3 ./kintex7/tile_type_MONITOR_MID_FUJI2.json`](./kintex7/tile_type_MONITOR_MID_FUJI2.json) + * [`23ab9221b032f8fd666d69220273b9a9b1ce614df194d7ec5097461760ada3e7 ./kintex7/tile_type_MONITOR_TOP_FUJI2.json`](./kintex7/tile_type_MONITOR_TOP_FUJI2.json) + * [`d430688c70e289f09318774410f2f55e53639c3544fca8a3c98d420f714b0c2f ./kintex7/tile_type_NULL.json`](./kintex7/tile_type_NULL.json) + * [`ef4278c20b438cc111717da6ba709e5f14147d37427f3c1f95b262a489e551a3 ./kintex7/tile_type_PCIE_BOT.json`](./kintex7/tile_type_PCIE_BOT.json) + * [`76afe0b2bffd363e7db29f6042fa161f210610a22eb18209b9236b8f10b56ae4 ./kintex7/tile_type_PCIE_INT_INTERFACE_L.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_L.json) + * [`87b9bf5c376e0aaf6903938e83fa398d3916ee94dfe8dc66ff4ea497821afc91 ./kintex7/tile_type_PCIE_INT_INTERFACE_R.json`](./kintex7/tile_type_PCIE_INT_INTERFACE_R.json) + * [`a246242840607ca7b8e3b45d44d7cf7fcc145fad4c973536575742c8b9bc9a42 ./kintex7/tile_type_PCIE_NULL.json`](./kintex7/tile_type_PCIE_NULL.json) + * [`e6d78d12f2b252b6bcc42c991a7ff904536f497d03a38abae25969b0fd26d3ba ./kintex7/tile_type_PCIE_TOP.json`](./kintex7/tile_type_PCIE_TOP.json) + * [`8d6974846370f048809873bb2f11160743750223880ec90e7189b6f1bd3296ad ./kintex7/tile_type_RIOB18.json`](./kintex7/tile_type_RIOB18.json) + * [`5d0021d1f204b8c1437fb9eff873f1843c1465d45fb45f0c806e6d2a16a7525a ./kintex7/tile_type_RIOB18_SING.json`](./kintex7/tile_type_RIOB18_SING.json) + * [`4b49afbc6f6bd55e6070925940fcdf19677a65760d33aab48ffd19a2faad2a0e ./kintex7/tile_type_RIOI.json`](./kintex7/tile_type_RIOI.json) + * [`1c6a969f5f6f0301ee8c1a253768f8298bcb5d05cf7723d7ad5667e8fe3475ca ./kintex7/tile_type_RIOI_SING.json`](./kintex7/tile_type_RIOI_SING.json) + * [`7a4d4f573f1c17ea2b40f971ebdff0b57266b67a5dff757357892b79fe60b8e7 ./kintex7/tile_type_RIOI_TBYTESRC.json`](./kintex7/tile_type_RIOI_TBYTESRC.json) + * [`5e119c4fa29dcbdf8c81c1af979e25e0fd8702cdd26177eaf8a13c09e5536402 ./kintex7/tile_type_RIOI_TBYTETERM.json`](./kintex7/tile_type_RIOI_TBYTETERM.json) + * [`f8636b98f24c07c250ea284be61826439e4557a3d75c8571cc3c00bc47d61f8c ./kintex7/tile_type_R_TERM_INT.json`](./kintex7/tile_type_R_TERM_INT.json) + * [`18e900373fe56da5f2ea19585effeee554c38f63437e6a5c26b00491a3952d99 ./kintex7/tile_type_R_TERM_INT_GTX.json`](./kintex7/tile_type_R_TERM_INT_GTX.json) + * [`fc909565278739a6beeb94d5bcb0780a6ec3dfa2d0f83389699974abc3d0427a ./kintex7/tile_type_TERM_CMT.json`](./kintex7/tile_type_TERM_CMT.json) + * [`372e4b47e58b79d8d6d587ee1459a576edbd7eebad7e8a49eba3e2c71cf3a536 ./kintex7/tile_type_T_TERM_INT.json`](./kintex7/tile_type_T_TERM_INT.json) + * [`9d6388021982de6d4a676c2c2fe6543029a2f44db45d290f4e827d35b91a2a6b ./kintex7/tile_type_VBRK.json`](./kintex7/tile_type_VBRK.json) + * [`5fb8795e142a7bc6955e6c50089540c890aeb3b3a6c326e6e24a6e4983d91f62 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json) + * [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json) * [`77985c4643b2984db517096deb4fc80ae992794089aea91c21b456d81fcbadd2 ./kintex7/tileconn.json`](./kintex7/tileconn.json) * [`be96cc131b66806e957bb25142ff6a47dbc06894e49cd2c4beddf7a39ee814b1 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json) * [`916a9b924454c10b835d561d80434461c5a9a2824bf85c3cdeeee5f0dedfcb24 ./kintex7/xc7k70tfbg676-2.json`](./kintex7/xc7k70tfbg676-2.json) diff --git a/kintex7/tile_type_BRAM_INT_INTERFACE_L.json b/kintex7/tile_type_BRAM_INT_INTERFACE_L.json index 67bddfd..6b985d9 100644 --- a/kintex7/tile_type_BRAM_INT_INTERFACE_L.json +++ b/kintex7/tile_type_BRAM_INT_INTERFACE_L.json @@ -2,475 +2,979 @@ "pips": { "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0" }, "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1" }, "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10" }, "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11" }, "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12" }, "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B13" }, "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B14->>INT_INTERFACE_LOGIC_OUTS_L14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B14" }, "BRAM_INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B15->>INT_INTERFACE_LOGIC_OUTS_L15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L15", 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"INT_INTERFACE_LOGIC_OUTS_L_B20", - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW4END3", - "L_INT_INTER_DQS_IOTOPHASER" - ] + "wires": { + "INT_INTERFACE_BLOCK_OUTS_L_B0": null, + "INT_INTERFACE_BLOCK_OUTS_L_B1": null, + "INT_INTERFACE_BLOCK_OUTS_L_B2": null, + "INT_INTERFACE_BLOCK_OUTS_L_B3": null, + "INT_INTERFACE_BRAM_IMUX0": null, + "INT_INTERFACE_BRAM_IMUX1": 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null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS_L0": null, + "INT_INTERFACE_LOGIC_OUTS_L1": null, + "INT_INTERFACE_LOGIC_OUTS_L10": null, + "INT_INTERFACE_LOGIC_OUTS_L11": null, + "INT_INTERFACE_LOGIC_OUTS_L12": null, + "INT_INTERFACE_LOGIC_OUTS_L13": null, + "INT_INTERFACE_LOGIC_OUTS_L14": null, + "INT_INTERFACE_LOGIC_OUTS_L15": null, + "INT_INTERFACE_LOGIC_OUTS_L16": null, + "INT_INTERFACE_LOGIC_OUTS_L17": null, + "INT_INTERFACE_LOGIC_OUTS_L18": null, + "INT_INTERFACE_LOGIC_OUTS_L19": null, + "INT_INTERFACE_LOGIC_OUTS_L2": null, + "INT_INTERFACE_LOGIC_OUTS_L20": null, + "INT_INTERFACE_LOGIC_OUTS_L21": null, + "INT_INTERFACE_LOGIC_OUTS_L22": null, + "INT_INTERFACE_LOGIC_OUTS_L23": null, + "INT_INTERFACE_LOGIC_OUTS_L3": null, + "INT_INTERFACE_LOGIC_OUTS_L4": null, + "INT_INTERFACE_LOGIC_OUTS_L5": null, + "INT_INTERFACE_LOGIC_OUTS_L6": null, + "INT_INTERFACE_LOGIC_OUTS_L7": null, + "INT_INTERFACE_LOGIC_OUTS_L8": null, + "INT_INTERFACE_LOGIC_OUTS_L9": null, + "INT_INTERFACE_LOGIC_OUTS_L_B0": null, + "INT_INTERFACE_LOGIC_OUTS_L_B1": null, + "INT_INTERFACE_LOGIC_OUTS_L_B10": null, + "INT_INTERFACE_LOGIC_OUTS_L_B11": null, + "INT_INTERFACE_LOGIC_OUTS_L_B12": null, + "INT_INTERFACE_LOGIC_OUTS_L_B13": null, + "INT_INTERFACE_LOGIC_OUTS_L_B14": null, + "INT_INTERFACE_LOGIC_OUTS_L_B15": null, + "INT_INTERFACE_LOGIC_OUTS_L_B16": null, + "INT_INTERFACE_LOGIC_OUTS_L_B17": null, + "INT_INTERFACE_LOGIC_OUTS_L_B18": null, + "INT_INTERFACE_LOGIC_OUTS_L_B19": null, + "INT_INTERFACE_LOGIC_OUTS_L_B2": null, + "INT_INTERFACE_LOGIC_OUTS_L_B20": null, + "INT_INTERFACE_LOGIC_OUTS_L_B21": null, + "INT_INTERFACE_LOGIC_OUTS_L_B22": null, + "INT_INTERFACE_LOGIC_OUTS_L_B23": null, + "INT_INTERFACE_LOGIC_OUTS_L_B3": null, + "INT_INTERFACE_LOGIC_OUTS_L_B4": null, + "INT_INTERFACE_LOGIC_OUTS_L_B5": null, + "INT_INTERFACE_LOGIC_OUTS_L_B6": null, + "INT_INTERFACE_LOGIC_OUTS_L_B7": null, + "INT_INTERFACE_LOGIC_OUTS_L_B8": null, + "INT_INTERFACE_LOGIC_OUTS_L_B9": null, + "INT_INTERFACE_MONITOR_N": null, + "INT_INTERFACE_MONITOR_P": null, + "INT_INTERFACE_NE2A0": null, + "INT_INTERFACE_NE2A1": null, + "INT_INTERFACE_NE2A2": null, + "INT_INTERFACE_NE2A3": null, + "INT_INTERFACE_NE4BEG0": null, + "INT_INTERFACE_NE4BEG1": null, + "INT_INTERFACE_NE4BEG2": null, + "INT_INTERFACE_NE4BEG3": null, + "INT_INTERFACE_NE4C0": null, + "INT_INTERFACE_NE4C1": null, + "INT_INTERFACE_NE4C2": null, + "INT_INTERFACE_NE4C3": null, + "INT_INTERFACE_NW2A0": null, + "INT_INTERFACE_NW2A1": null, + "INT_INTERFACE_NW2A2": null, + "INT_INTERFACE_NW2A3": null, + "INT_INTERFACE_NW4A0": null, + "INT_INTERFACE_NW4A1": null, + "INT_INTERFACE_NW4A2": null, + "INT_INTERFACE_NW4A3": null, + "INT_INTERFACE_NW4END0": null, + "INT_INTERFACE_NW4END1": null, + "INT_INTERFACE_NW4END2": null, + "INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_PHASER_TO_IO_ICLK": null, + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90": null, + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + "INT_INTERFACE_SW4END3": null, + "INT_INTERFACE_WL1END0": null, + "INT_INTERFACE_WL1END1": null, + "INT_INTERFACE_WL1END2": null, + "INT_INTERFACE_WL1END3": null, + "INT_INTERFACE_WR1END0": null, + "INT_INTERFACE_WR1END1": null, + "INT_INTERFACE_WR1END2": null, + "INT_INTERFACE_WR1END3": null, + "INT_INTERFACE_WW2A0": null, + "INT_INTERFACE_WW2A1": null, + "INT_INTERFACE_WW2A2": null, + "INT_INTERFACE_WW2A3": null, + "INT_INTERFACE_WW2END0": null, + "INT_INTERFACE_WW2END1": null, + "INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/kintex7/tile_type_BRAM_INT_INTERFACE_R.json b/kintex7/tile_type_BRAM_INT_INTERFACE_R.json index 6def0d9..0e41244 100644 --- a/kintex7/tile_type_BRAM_INT_INTERFACE_R.json +++ b/kintex7/tile_type_BRAM_INT_INTERFACE_R.json @@ -2,475 +2,979 @@ "pips": { "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0" }, "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1" }, "BRAM_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { "can_invert": "0", + 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"INT_INTERFACE_BYP7", - "INT_INTERFACE_CLK0", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_EE2A0", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_ER1BEG1", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_LH1", - "INT_INTERFACE_LH10", - "INT_INTERFACE_LH11", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH2", - "INT_INTERFACE_LH3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_LH5", - "INT_INTERFACE_LH6", - "INT_INTERFACE_LH7", - "INT_INTERFACE_LH8", - "INT_INTERFACE_LH9", - "INT_INTERFACE_LOGIC_OUTS0", - "INT_INTERFACE_LOGIC_OUTS1", - "INT_INTERFACE_LOGIC_OUTS10", - "INT_INTERFACE_LOGIC_OUTS11", - "INT_INTERFACE_LOGIC_OUTS12", - "INT_INTERFACE_LOGIC_OUTS13", - "INT_INTERFACE_LOGIC_OUTS14", - "INT_INTERFACE_LOGIC_OUTS15", - "INT_INTERFACE_LOGIC_OUTS16", - "INT_INTERFACE_LOGIC_OUTS17", - "INT_INTERFACE_LOGIC_OUTS18", - "INT_INTERFACE_LOGIC_OUTS19", - "INT_INTERFACE_LOGIC_OUTS2", - "INT_INTERFACE_LOGIC_OUTS20", - "INT_INTERFACE_LOGIC_OUTS21", - "INT_INTERFACE_LOGIC_OUTS22", - "INT_INTERFACE_LOGIC_OUTS23", - "INT_INTERFACE_LOGIC_OUTS3", - "INT_INTERFACE_LOGIC_OUTS4", - "INT_INTERFACE_LOGIC_OUTS5", - "INT_INTERFACE_LOGIC_OUTS6", - "INT_INTERFACE_LOGIC_OUTS7", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS9", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_LOGIC_OUTS_B1", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS_B11", - "INT_INTERFACE_LOGIC_OUTS_B12", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_LOGIC_OUTS_B14", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_LOGIC_OUTS_B18", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_LOGIC_OUTS_B2", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_LOGIC_OUTS_B21", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_LOGIC_OUTS_B23", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_LOGIC_OUTS_B4", - "INT_INTERFACE_LOGIC_OUTS_B5", - "INT_INTERFACE_LOGIC_OUTS_B6", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_LOGIC_OUTS_B9", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW4END3", - "L_INT_INTER_DQS_IOTOPHASER" - ] + "wires": { + "INT_INTERFACE_BLOCK_OUTS_B0": null, + "INT_INTERFACE_BLOCK_OUTS_B1": null, + "INT_INTERFACE_BLOCK_OUTS_B2": null, + "INT_INTERFACE_BLOCK_OUTS_B3": null, + "INT_INTERFACE_BRAM_IMUX0": null, + "INT_INTERFACE_BRAM_IMUX1": null, + "INT_INTERFACE_BRAM_IMUX10": null, + "INT_INTERFACE_BRAM_IMUX11": null, + "INT_INTERFACE_BRAM_IMUX12": null, + "INT_INTERFACE_BRAM_IMUX13": null, + "INT_INTERFACE_BRAM_IMUX14": null, + "INT_INTERFACE_BRAM_IMUX15": null, + "INT_INTERFACE_BRAM_IMUX16": null, + "INT_INTERFACE_BRAM_IMUX17": null, + "INT_INTERFACE_BRAM_IMUX18": null, + "INT_INTERFACE_BRAM_IMUX19": null, + "INT_INTERFACE_BRAM_IMUX2": null, + "INT_INTERFACE_BRAM_IMUX20": null, + "INT_INTERFACE_BRAM_IMUX21": null, + "INT_INTERFACE_BRAM_IMUX22": null, + "INT_INTERFACE_BRAM_IMUX23": null, + "INT_INTERFACE_BRAM_IMUX24": null, + "INT_INTERFACE_BRAM_IMUX25": null, + "INT_INTERFACE_BRAM_IMUX26": null, + "INT_INTERFACE_BRAM_IMUX27": null, + "INT_INTERFACE_BRAM_IMUX28": null, + "INT_INTERFACE_BRAM_IMUX29": null, + "INT_INTERFACE_BRAM_IMUX3": null, + "INT_INTERFACE_BRAM_IMUX30": null, + "INT_INTERFACE_BRAM_IMUX31": null, + "INT_INTERFACE_BRAM_IMUX32": null, + "INT_INTERFACE_BRAM_IMUX33": null, + "INT_INTERFACE_BRAM_IMUX34": null, + "INT_INTERFACE_BRAM_IMUX35": null, + "INT_INTERFACE_BRAM_IMUX36": null, + "INT_INTERFACE_BRAM_IMUX37": null, + "INT_INTERFACE_BRAM_IMUX38": null, + "INT_INTERFACE_BRAM_IMUX39": null, + "INT_INTERFACE_BRAM_IMUX4": null, + "INT_INTERFACE_BRAM_IMUX40": null, + "INT_INTERFACE_BRAM_IMUX41": null, + "INT_INTERFACE_BRAM_IMUX42": null, + "INT_INTERFACE_BRAM_IMUX43": null, + "INT_INTERFACE_BRAM_IMUX44": null, + "INT_INTERFACE_BRAM_IMUX45": null, + "INT_INTERFACE_BRAM_IMUX46": null, + "INT_INTERFACE_BRAM_IMUX47": null, + "INT_INTERFACE_BRAM_IMUX5": null, + "INT_INTERFACE_BRAM_IMUX6": null, + "INT_INTERFACE_BRAM_IMUX7": null, + "INT_INTERFACE_BRAM_IMUX8": null, + "INT_INTERFACE_BRAM_IMUX9": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX0": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX1": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX10": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX11": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX12": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX13": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX14": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX15": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX16": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX17": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX18": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX19": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX2": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX20": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX21": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX22": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX23": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX24": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX25": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX26": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX27": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX28": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX29": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX3": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX30": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX31": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX32": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX33": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX34": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX35": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX36": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX37": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX38": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX39": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX4": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX40": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX41": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX42": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX43": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX44": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX45": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX46": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX47": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX5": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX6": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX7": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX8": null, + "INT_INTERFACE_BRAM_UTURN_R_IMUX9": null, + "INT_INTERFACE_BYP0": null, + "INT_INTERFACE_BYP1": null, + "INT_INTERFACE_BYP2": null, + "INT_INTERFACE_BYP3": null, + "INT_INTERFACE_BYP4": null, + "INT_INTERFACE_BYP5": null, + "INT_INTERFACE_BYP6": null, + "INT_INTERFACE_BYP7": null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS0": null, + "INT_INTERFACE_LOGIC_OUTS1": null, + "INT_INTERFACE_LOGIC_OUTS10": null, + "INT_INTERFACE_LOGIC_OUTS11": null, + "INT_INTERFACE_LOGIC_OUTS12": null, + "INT_INTERFACE_LOGIC_OUTS13": null, + "INT_INTERFACE_LOGIC_OUTS14": null, + "INT_INTERFACE_LOGIC_OUTS15": null, + "INT_INTERFACE_LOGIC_OUTS16": null, + "INT_INTERFACE_LOGIC_OUTS17": null, + "INT_INTERFACE_LOGIC_OUTS18": null, + "INT_INTERFACE_LOGIC_OUTS19": null, + "INT_INTERFACE_LOGIC_OUTS2": null, + "INT_INTERFACE_LOGIC_OUTS20": null, + "INT_INTERFACE_LOGIC_OUTS21": null, + "INT_INTERFACE_LOGIC_OUTS22": null, + "INT_INTERFACE_LOGIC_OUTS23": null, + "INT_INTERFACE_LOGIC_OUTS3": null, + "INT_INTERFACE_LOGIC_OUTS4": null, + "INT_INTERFACE_LOGIC_OUTS5": null, + "INT_INTERFACE_LOGIC_OUTS6": null, + "INT_INTERFACE_LOGIC_OUTS7": null, + "INT_INTERFACE_LOGIC_OUTS8": null, + "INT_INTERFACE_LOGIC_OUTS9": null, + "INT_INTERFACE_LOGIC_OUTS_B0": null, + "INT_INTERFACE_LOGIC_OUTS_B1": null, + "INT_INTERFACE_LOGIC_OUTS_B10": null, + "INT_INTERFACE_LOGIC_OUTS_B11": null, + "INT_INTERFACE_LOGIC_OUTS_B12": null, + "INT_INTERFACE_LOGIC_OUTS_B13": null, + "INT_INTERFACE_LOGIC_OUTS_B14": null, + "INT_INTERFACE_LOGIC_OUTS_B15": null, + "INT_INTERFACE_LOGIC_OUTS_B16": null, + "INT_INTERFACE_LOGIC_OUTS_B17": null, + "INT_INTERFACE_LOGIC_OUTS_B18": null, + "INT_INTERFACE_LOGIC_OUTS_B19": null, + "INT_INTERFACE_LOGIC_OUTS_B2": null, + "INT_INTERFACE_LOGIC_OUTS_B20": null, + "INT_INTERFACE_LOGIC_OUTS_B21": null, + "INT_INTERFACE_LOGIC_OUTS_B22": null, + "INT_INTERFACE_LOGIC_OUTS_B23": null, + "INT_INTERFACE_LOGIC_OUTS_B3": null, + "INT_INTERFACE_LOGIC_OUTS_B4": null, + "INT_INTERFACE_LOGIC_OUTS_B5": null, + "INT_INTERFACE_LOGIC_OUTS_B6": null, + "INT_INTERFACE_LOGIC_OUTS_B7": null, + "INT_INTERFACE_LOGIC_OUTS_B8": null, + "INT_INTERFACE_LOGIC_OUTS_B9": null, + "INT_INTERFACE_MONITOR_N": null, + "INT_INTERFACE_MONITOR_P": null, + "INT_INTERFACE_NE2A0": null, + "INT_INTERFACE_NE2A1": null, + "INT_INTERFACE_NE2A2": null, + "INT_INTERFACE_NE2A3": null, + "INT_INTERFACE_NE4BEG0": null, + "INT_INTERFACE_NE4BEG1": null, + "INT_INTERFACE_NE4BEG2": null, + "INT_INTERFACE_NE4BEG3": null, + "INT_INTERFACE_NE4C0": null, + "INT_INTERFACE_NE4C1": null, + "INT_INTERFACE_NE4C2": null, + "INT_INTERFACE_NE4C3": null, + "INT_INTERFACE_NW2A0": null, + "INT_INTERFACE_NW2A1": null, + "INT_INTERFACE_NW2A2": null, + "INT_INTERFACE_NW2A3": null, + "INT_INTERFACE_NW4A0": null, + "INT_INTERFACE_NW4A1": null, + "INT_INTERFACE_NW4A2": null, + "INT_INTERFACE_NW4A3": null, + "INT_INTERFACE_NW4END0": null, + "INT_INTERFACE_NW4END1": null, + "INT_INTERFACE_NW4END2": null, + "INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_PHASER_TO_IO_ICLK": null, + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90": null, + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + "INT_INTERFACE_SW4END3": null, + "INT_INTERFACE_WL1END0": null, + "INT_INTERFACE_WL1END1": null, + "INT_INTERFACE_WL1END2": null, + "INT_INTERFACE_WL1END3": null, + "INT_INTERFACE_WR1END0": null, + "INT_INTERFACE_WR1END1": null, + "INT_INTERFACE_WR1END2": null, + "INT_INTERFACE_WR1END3": null, + "INT_INTERFACE_WW2A0": null, + "INT_INTERFACE_WW2A1": null, + "INT_INTERFACE_WW2A2": null, + "INT_INTERFACE_WW2A3": null, + "INT_INTERFACE_WW2END0": null, + "INT_INTERFACE_WW2END1": null, + "INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/kintex7/tile_type_BRAM_L.json b/kintex7/tile_type_BRAM_L.json index 35370eb..e1ba886 100644 --- a/kintex7/tile_type_BRAM_L.json +++ b/kintex7/tile_type_BRAM_L.json @@ -2,6820 +2,19714 @@ "pips": { "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO18_ADDRATIEHIGH0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_ADDRARDADDRL0" }, "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_FIFO36_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_ADDRARDADDRL0" }, "BRAM_L.BRAM_ADDRARDADDRL0->>BRAM_UTURN_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_ADDRARDADDRL0" }, "BRAM_L.BRAM_ADDRARDADDRL1->>BRAM_FIFO18_ADDRARDADDR0": { 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_L.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_0" }, "BRAM_L.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_0" }, "BRAM_L.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_CLKBWRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_1" }, "BRAM_L.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_1" }, "BRAM_L.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_CLKARDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_3" }, "BRAM_L.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKARDCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_3" }, "BRAM_L.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_4" }, "BRAM_L.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_4" }, "BRAM_L.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_0" }, "BRAM_L.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_0" }, "BRAM_L.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_1" }, "BRAM_L.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_CLKBWRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_1" }, "BRAM_L.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKARDCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_3" }, "BRAM_L.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_CLKARDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_3" }, "BRAM_L.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_4" }, "BRAM_L.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_4" }, "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTREGB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_L.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTRAMB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_L.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_L.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTREGARSTREG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_L.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_L.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_L.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTREGB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_L.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_L.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTRAMB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_L.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_L.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_L.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_L.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTREGARSTREG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_L.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN1_2" }, "BRAM_L.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN1_2" }, "BRAM_L.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN5_2" }, "BRAM_L.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN5_2" }, "BRAM_L.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_ALMOSTEMPTY" }, "BRAM_L.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_ALMOSTFULL" }, "BRAM_L.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO0" }, "BRAM_L.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO1" }, "BRAM_L.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO10" }, "BRAM_L.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO11" }, "BRAM_L.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO12" }, "BRAM_L.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO13" }, "BRAM_L.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO14" }, "BRAM_L.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO15" }, "BRAM_L.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO2" }, "BRAM_L.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO3" }, "BRAM_L.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO4" }, "BRAM_L.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO5" }, "BRAM_L.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO6" }, "BRAM_L.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO7" }, "BRAM_L.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO8" }, "BRAM_L.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO9" }, "BRAM_L.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO0" }, "BRAM_L.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO1" }, "BRAM_L.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO10" }, "BRAM_L.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO11" }, "BRAM_L.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO12" }, "BRAM_L.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO13" }, "BRAM_L.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO14" }, "BRAM_L.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO15" }, "BRAM_L.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO2" }, "BRAM_L.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO3" }, "BRAM_L.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO4" }, "BRAM_L.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO5" }, "BRAM_L.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO6" }, "BRAM_L.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO7" }, "BRAM_L.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO8" }, "BRAM_L.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO9" }, "BRAM_L.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPADOP0" }, "BRAM_L.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPADOP1" }, "BRAM_L.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPBDOP0" }, "BRAM_L.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPBDOP1" }, "BRAM_L.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_EMPTY" }, "BRAM_L.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_FULL" }, "BRAM_L.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT0" }, "BRAM_L.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT1" }, "BRAM_L.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT10" }, "BRAM_L.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT11" }, "BRAM_L.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT2" }, "BRAM_L.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT3" }, "BRAM_L.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT4" }, "BRAM_L.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT5" }, "BRAM_L.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT6" }, "BRAM_L.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT7" }, "BRAM_L.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT8" }, "BRAM_L.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT9" }, "BRAM_L.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDERR" }, "BRAM_L.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT0" }, "BRAM_L.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT1" }, "BRAM_L.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT10" }, "BRAM_L.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT11" }, "BRAM_L.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT2" }, "BRAM_L.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT3" }, "BRAM_L.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT4" }, "BRAM_L.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT5" }, "BRAM_L.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT6" }, "BRAM_L.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT7" }, "BRAM_L.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT8" }, "BRAM_L.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT9" }, "BRAM_L.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRERR" }, "BRAM_L.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ALMOSTEMPTY" }, "BRAM_L.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ALMOSTFULL" }, "BRAM_L.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_CASCADEOUTA" }, "BRAM_L.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_CASCADEOUTB" }, "BRAM_L.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DBITERR" }, "BRAM_L.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL0" }, "BRAM_L.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL1" }, "BRAM_L.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL10" }, "BRAM_L.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL11" }, "BRAM_L.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL12" }, "BRAM_L.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL13" }, "BRAM_L.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL14" }, "BRAM_L.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL15" }, "BRAM_L.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL2" }, "BRAM_L.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL3" }, "BRAM_L.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL4" }, "BRAM_L.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL5" }, "BRAM_L.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL6" }, "BRAM_L.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL7" }, "BRAM_L.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL8" }, "BRAM_L.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL9" }, "BRAM_L.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU0" }, "BRAM_L.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU1" }, "BRAM_L.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU10" }, "BRAM_L.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU11" }, "BRAM_L.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU12" }, "BRAM_L.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU13" }, "BRAM_L.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU14" }, "BRAM_L.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU15" }, "BRAM_L.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU2" }, "BRAM_L.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU3" }, "BRAM_L.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU4" }, "BRAM_L.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU5" }, "BRAM_L.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU6" }, "BRAM_L.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU7" }, "BRAM_L.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU8" }, "BRAM_L.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU9" }, "BRAM_L.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL0" }, "BRAM_L.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL1" }, "BRAM_L.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL10" }, "BRAM_L.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL11" }, "BRAM_L.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL12" }, "BRAM_L.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL13" }, "BRAM_L.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL14" }, "BRAM_L.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL15" }, "BRAM_L.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL2" }, "BRAM_L.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL3" }, "BRAM_L.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL4" }, "BRAM_L.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL5" }, "BRAM_L.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL6" }, "BRAM_L.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL7" }, "BRAM_L.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL8" }, "BRAM_L.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL9" }, "BRAM_L.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU0" }, "BRAM_L.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU1" }, "BRAM_L.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU10" }, "BRAM_L.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU11" }, "BRAM_L.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU12" }, "BRAM_L.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU13" }, "BRAM_L.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU14" }, "BRAM_L.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU15" }, "BRAM_L.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU2" }, "BRAM_L.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU3" }, "BRAM_L.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU4" }, "BRAM_L.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU5" }, "BRAM_L.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU6" }, "BRAM_L.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU7" }, "BRAM_L.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU8" }, "BRAM_L.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU9" }, "BRAM_L.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPL0" }, "BRAM_L.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPL1" }, "BRAM_L.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPU0" }, "BRAM_L.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPU1" }, "BRAM_L.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPL0" }, "BRAM_L.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPL1" }, "BRAM_L.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPU0" }, "BRAM_L.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPU1" }, "BRAM_L.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY0" }, "BRAM_L.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY1" }, "BRAM_L.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY2" }, "BRAM_L.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY3" }, "BRAM_L.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY4" }, "BRAM_L.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY5" }, "BRAM_L.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY6" }, "BRAM_L.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY7" }, "BRAM_L.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_EMPTY" }, "BRAM_L.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_FULL" }, "BRAM_L.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT0" }, "BRAM_L.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT1" }, "BRAM_L.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT10" }, "BRAM_L.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT11" }, "BRAM_L.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT12" }, "BRAM_L.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT2" }, "BRAM_L.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT3" }, "BRAM_L.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT4" }, "BRAM_L.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT5" }, "BRAM_L.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT6" }, "BRAM_L.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT7" }, "BRAM_L.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT8" }, "BRAM_L.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT9" }, "BRAM_L.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDERR" }, "BRAM_L.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_SBITERR" }, "BRAM_L.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT0" }, "BRAM_L.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT1" }, "BRAM_L.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT2" }, "BRAM_L.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT3" }, "BRAM_L.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT4" }, "BRAM_L.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT0" }, "BRAM_L.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT1" }, "BRAM_L.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT10" }, "BRAM_L.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT11" }, "BRAM_L.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT12" }, "BRAM_L.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT2" }, "BRAM_L.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT3" }, "BRAM_L.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT4" }, "BRAM_L.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT5" }, "BRAM_L.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT6" }, "BRAM_L.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT7" }, "BRAM_L.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT8" }, "BRAM_L.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT9" }, "BRAM_L.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRERR" }, "BRAM_L.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTBRAMRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX0_0" }, "BRAM_L.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_0" }, "BRAM_L.BRAM_IMUX10_1->BRAM_IMUX_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_1" }, "BRAM_L.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENARDENU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_L.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_ENARDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_L.BRAM_IMUX10_3->BRAM_IMUX_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_3" }, "BRAM_L.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_L.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_L.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_0" }, "BRAM_L.BRAM_IMUX11_1->BRAM_IMUX_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_1" }, "BRAM_L.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_L.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCEAREGCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_L.BRAM_IMUX11_3->BRAM_IMUX_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_3" }, "BRAM_L.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_L.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_L.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_0" }, "BRAM_L.BRAM_IMUX12_1->BRAM_IMUX_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_1" }, "BRAM_L.BRAM_IMUX12_2->BRAM_IMUX_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_2" }, "BRAM_L.BRAM_IMUX12_3->BRAM_IMUX_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_3" }, "BRAM_L.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_L.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_L.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_0" }, "BRAM_L.BRAM_IMUX13_1->BRAM_IMUX_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_1" }, "BRAM_L.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_L.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_L.BRAM_IMUX13_3->BRAM_IMUX_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_3" }, "BRAM_L.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_L.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_L.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_0" }, "BRAM_L.BRAM_IMUX14_1->BRAM_IMUX_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_1" }, "BRAM_L.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_L.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_L.BRAM_IMUX14_3->BRAM_IMUX_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_3" }, "BRAM_L.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_L.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_L.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_0" }, "BRAM_L.BRAM_IMUX15_1->BRAM_IMUX_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_1" }, "BRAM_L.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_L.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_L.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_L.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPADIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_L.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_L.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_L.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_0" }, "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_L.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_L.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_L.BRAM_IMUX16_3->BRAM_IMUX_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_3" }, "BRAM_L.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_L.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_L.BRAM_IMUX17_1->BRAM_IMUX_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_1" }, "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_L.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_L.BRAM_IMUX17_3->BRAM_IMUX_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_3" }, "BRAM_L.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_L.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_L.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_0" }, "BRAM_L.BRAM_IMUX18_1->BRAM_IMUX_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_1" }, "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_ENARDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_L.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENARDENL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_L.BRAM_IMUX18_3->BRAM_IMUX_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_3" }, "BRAM_L.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_L.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_L.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_0" }, "BRAM_L.BRAM_IMUX19_1->BRAM_IMUX_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_1" }, "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCEAREGCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_L.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_L.BRAM_IMUX19_3->BRAM_IMUX_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_3" }, "BRAM_L.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_L.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPBDIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_L.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_L.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_L.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_L.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_L.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_0" }, "BRAM_L.BRAM_IMUX20_1->BRAM_IMUX_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_1" }, "BRAM_L.BRAM_IMUX20_2->BRAM_IMUX_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_2" }, "BRAM_L.BRAM_IMUX20_3->BRAM_IMUX_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_3" }, "BRAM_L.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_L.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_L.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_0" }, "BRAM_L.BRAM_IMUX21_1->BRAM_IMUX_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_1" }, "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_L.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_L.BRAM_IMUX21_3->BRAM_IMUX_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_3" }, "BRAM_L.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_L.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_L.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_0" }, "BRAM_L.BRAM_IMUX22_1->BRAM_IMUX_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_1" }, "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_L.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_L.BRAM_IMUX22_3->BRAM_IMUX_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_3" }, "BRAM_L.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_L.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_L.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_0" }, "BRAM_L.BRAM_IMUX23_1->BRAM_IMUX_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_1" }, "BRAM_L.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_L.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_L.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_L.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPBDIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_L.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_L.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_L.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_L.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_L.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_L.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_L.BRAM_IMUX24_3->BRAM_IMUX_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_3" }, "BRAM_L.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_4" }, "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_L.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_L.BRAM_IMUX25_1->BRAM_IMUX_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_1" }, "BRAM_L.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_L.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_L.BRAM_IMUX25_3->BRAM_IMUX_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_3" }, "BRAM_L.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_4" }, "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_L.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_L.BRAM_IMUX26_1->BRAM_IMUX_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_1" }, "BRAM_L.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENBWRENU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_L.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_ENBWREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_L.BRAM_IMUX26_3->BRAM_IMUX_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_3" }, "BRAM_L.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_4" }, "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_L.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_L.BRAM_IMUX27_1->BRAM_IMUX_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_1" }, "BRAM_L.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_L.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_L.BRAM_IMUX27_3->BRAM_IMUX_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_3" }, "BRAM_L.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_4" }, "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_L.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_L.BRAM_IMUX28_1->BRAM_IMUX_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_1" }, "BRAM_L.BRAM_IMUX28_2->BRAM_IMUX_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_2" }, "BRAM_L.BRAM_IMUX28_3->BRAM_IMUX_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_3" }, "BRAM_L.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_4" }, "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_L.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_L.BRAM_IMUX29_1->BRAM_IMUX_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_1" }, "BRAM_L.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_L.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_L.BRAM_IMUX29_3->BRAM_IMUX_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_3" }, "BRAM_L.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_4" }, "BRAM_L.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_0" }, "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_L.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_L.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_L.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_L.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_L.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_L.BRAM_IMUX30_1->BRAM_IMUX_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_1" }, "BRAM_L.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_L.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_L.BRAM_IMUX30_3->BRAM_IMUX_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_3" }, "BRAM_L.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_4" }, "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_L.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_L.BRAM_IMUX31_1->BRAM_IMUX_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_1" }, "BRAM_L.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_INJECTDBITERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_2" }, "BRAM_L.BRAM_IMUX31_3->BRAM_IMUX_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_3" }, "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_L.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_L.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_L.BRAM_IMUX32_3->BRAM_IMUX_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_3" }, "BRAM_L.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_4" }, "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_L.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_L.BRAM_IMUX33_1->BRAM_IMUX_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_1" }, "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_L.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_L.BRAM_IMUX33_3->BRAM_IMUX_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_3" }, "BRAM_L.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_4" }, "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_L.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_L.BRAM_IMUX34_1->BRAM_IMUX_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_1" }, "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_ENBWREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_L.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENBWRENL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_L.BRAM_IMUX34_3->BRAM_IMUX_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_3" }, "BRAM_L.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_4" }, "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_L.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_L.BRAM_IMUX35_1->BRAM_IMUX_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_1" }, "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_L.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_L.BRAM_IMUX35_3->BRAM_IMUX_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_3" }, "BRAM_L.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_4" }, "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_L.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_L.BRAM_IMUX36_1->BRAM_IMUX_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_1" }, "BRAM_L.BRAM_IMUX36_2->BRAM_IMUX_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_2" }, "BRAM_L.BRAM_IMUX36_3->BRAM_IMUX_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_3" }, "BRAM_L.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_4" }, "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_L.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_L.BRAM_IMUX37_1->BRAM_IMUX_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_1" }, "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_L.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_L.BRAM_IMUX37_3->BRAM_IMUX_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_3" }, "BRAM_L.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_4" }, "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_L.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_L.BRAM_IMUX38_1->BRAM_IMUX_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_1" }, "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_L.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_L.BRAM_IMUX38_3->BRAM_IMUX_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_3" }, "BRAM_L.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_4" }, "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_L.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_L.BRAM_IMUX39_1->BRAM_IMUX_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_1" }, "BRAM_L.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_INJECTSBITERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_2" }, "BRAM_L.BRAM_IMUX39_3->BRAM_IMUX_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_3" }, "BRAM_L.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_0" }, "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_L.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPADIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_L.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_L.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_L.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPADIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_L.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_L.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_L.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_L.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_L.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, 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null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_1" }, "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_2" }, "BRAM_L.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_2" }, 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"res": "0.000" + }, "src_wire": "BRAM_IMUX41_4" }, "BRAM_L.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_0" }, "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_L.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_L.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_L.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPADIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_L.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_L.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_L.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_4" }, "BRAM_L.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_0" }, "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_L.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_L.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_L.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPBDIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_L.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_L.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_L.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_4" }, "BRAM_L.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_0" }, "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_L.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_L.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_L.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_L.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_4" }, "BRAM_L.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_0" }, "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_L.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_L.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_L.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_L.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_L.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_L.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_4" }, "BRAM_L.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_0" }, "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_L.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_L.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_L.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_L.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_4" }, "BRAM_L.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX47_0" }, "BRAM_L.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_0" }, "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_L.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPBDIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_L.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_L.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_L.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_L.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_4" }, "BRAM_L.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTFLAGIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_0" }, "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_L.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_L.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_L.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_L.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_L.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_4" }, "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_L.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_L.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_L.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_L.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_L.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_L.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_0" }, "BRAM_L.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_L.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_L.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_L.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_L.BRAM_IMUX8_3->BRAM_IMUX_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_3" }, "BRAM_L.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_L.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_L.BRAM_IMUX9_1->BRAM_IMUX_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_1" }, "BRAM_L.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_L.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_L.BRAM_IMUX9_3->BRAM_IMUX_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_3" }, "BRAM_L.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_L.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL0" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL1" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL10" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL11" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL12" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL13" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL14" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL2" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL3" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL4" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL5" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL6" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL7" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL8" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRL9" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU0" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU1" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU10" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU11" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU12" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU13" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU14" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU2" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU3" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU4" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU5" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU6" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU7" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU8" }, "BRAM_L.BRAM_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRARDADDRU9" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL0" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL1" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL10" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL11" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL12" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL13" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL14" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL15" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL2" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL3" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL4" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL5" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL6" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL7" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL8" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRL9" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU0" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU1" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU10" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU11" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU12" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU13" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU14" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU2" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU3" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU4" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU5" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU6" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU7" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU8" }, "BRAM_L.BRAM_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX_ADDRBWRADDRU9" }, "BRAM_L.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO0" }, "BRAM_L.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO1" }, "BRAM_L.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO10" }, "BRAM_L.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO11" }, "BRAM_L.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO12" }, "BRAM_L.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO13" }, "BRAM_L.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO14" }, "BRAM_L.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO15" }, "BRAM_L.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO2" }, "BRAM_L.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO3" }, "BRAM_L.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO4" }, "BRAM_L.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO5" }, "BRAM_L.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO6" }, "BRAM_L.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO7" }, "BRAM_L.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO8" }, "BRAM_L.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO9" }, "BRAM_L.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO0" }, "BRAM_L.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO1" }, "BRAM_L.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO10" }, "BRAM_L.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO11" }, "BRAM_L.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO12" }, "BRAM_L.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO13" }, "BRAM_L.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO14" }, "BRAM_L.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO15" }, "BRAM_L.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO2" }, "BRAM_L.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO3" }, "BRAM_L.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO4" }, "BRAM_L.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO5" }, "BRAM_L.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO6" }, "BRAM_L.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO7" }, "BRAM_L.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO8" }, "BRAM_L.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO9" }, "BRAM_L.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPADOP0" }, "BRAM_L.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPADOP1" }, "BRAM_L.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPBDOP0" }, "BRAM_L.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPBDOP1" } }, @@ -6824,362 +19718,3566 @@ "name": "X0Y0", "prefix": "RAMB36", "site_pins": { - "ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", - "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", - "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", - "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", - "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", - "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", - "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", - "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", - "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", - "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", - "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", - "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", - "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", - "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", - "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", - "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", - "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", - "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", - "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", - "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", - "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", - "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", - "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", - "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", - "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", - "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", - "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", - "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", - "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", - "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", - "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", - "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", - "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", - "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", - "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", - "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", - "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", - "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", - "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", - "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", - "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", - "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", - "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", - "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", - "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", - "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", - "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", - "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", - "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", - "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", - "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", - "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", - "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", - "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", - "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", - "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", - "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", - "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", - "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", - "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", - "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", - "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", - "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", - "CASCADEINA": "BRAM_FIFO36_CASCADEINA", - "CASCADEINB": "BRAM_FIFO36_CASCADEINB", - "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTA", - "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTB", - "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", - "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", - "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", - "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", - "DBITERR": "BRAM_FIFO36_DBITERR", - "DIADI0": "BRAM_FIFO36_DIADIL0", - "DIADI1": "BRAM_FIFO36_DIADIU0", - "DIADI10": "BRAM_FIFO36_DIADIL5", - "DIADI11": "BRAM_FIFO36_DIADIU5", - "DIADI12": "BRAM_FIFO36_DIADIL6", - "DIADI13": "BRAM_FIFO36_DIADIU6", - "DIADI14": "BRAM_FIFO36_DIADIL7", - "DIADI15": "BRAM_FIFO36_DIADIU7", - "DIADI16": "BRAM_FIFO36_DIADIL8", - "DIADI17": "BRAM_FIFO36_DIADIU8", - "DIADI18": "BRAM_FIFO36_DIADIL9", - "DIADI19": "BRAM_FIFO36_DIADIU9", - "DIADI2": "BRAM_FIFO36_DIADIL1", - "DIADI20": "BRAM_FIFO36_DIADIL10", - "DIADI21": "BRAM_FIFO36_DIADIU10", - "DIADI22": "BRAM_FIFO36_DIADIL11", - "DIADI23": "BRAM_FIFO36_DIADIU11", - "DIADI24": "BRAM_FIFO36_DIADIL12", - "DIADI25": "BRAM_FIFO36_DIADIU12", - "DIADI26": "BRAM_FIFO36_DIADIL13", - "DIADI27": "BRAM_FIFO36_DIADIU13", - "DIADI28": "BRAM_FIFO36_DIADIL14", - "DIADI29": "BRAM_FIFO36_DIADIU14", - "DIADI3": "BRAM_FIFO36_DIADIU1", - "DIADI30": "BRAM_FIFO36_DIADIL15", - "DIADI31": "BRAM_FIFO36_DIADIU15", - "DIADI4": "BRAM_FIFO36_DIADIL2", - "DIADI5": "BRAM_FIFO36_DIADIU2", - "DIADI6": "BRAM_FIFO36_DIADIL3", - "DIADI7": "BRAM_FIFO36_DIADIU3", - "DIADI8": "BRAM_FIFO36_DIADIL4", - "DIADI9": "BRAM_FIFO36_DIADIU4", - "DIBDI0": "BRAM_FIFO36_DIBDIL0", - "DIBDI1": "BRAM_FIFO36_DIBDIU0", - "DIBDI10": "BRAM_FIFO36_DIBDIL5", - "DIBDI11": "BRAM_FIFO36_DIBDIU5", - "DIBDI12": "BRAM_FIFO36_DIBDIL6", - "DIBDI13": "BRAM_FIFO36_DIBDIU6", - "DIBDI14": "BRAM_FIFO36_DIBDIL7", - "DIBDI15": "BRAM_FIFO36_DIBDIU7", - "DIBDI16": "BRAM_FIFO36_DIBDIL8", - "DIBDI17": "BRAM_FIFO36_DIBDIU8", - "DIBDI18": "BRAM_FIFO36_DIBDIL9", - "DIBDI19": "BRAM_FIFO36_DIBDIU9", - "DIBDI2": "BRAM_FIFO36_DIBDIL1", - "DIBDI20": "BRAM_FIFO36_DIBDIL10", - "DIBDI21": "BRAM_FIFO36_DIBDIU10", - "DIBDI22": "BRAM_FIFO36_DIBDIL11", - "DIBDI23": "BRAM_FIFO36_DIBDIU11", - "DIBDI24": "BRAM_FIFO36_DIBDIL12", - "DIBDI25": "BRAM_FIFO36_DIBDIU12", - "DIBDI26": "BRAM_FIFO36_DIBDIL13", - "DIBDI27": "BRAM_FIFO36_DIBDIU13", - "DIBDI28": "BRAM_FIFO36_DIBDIL14", - "DIBDI29": "BRAM_FIFO36_DIBDIU14", - "DIBDI3": "BRAM_FIFO36_DIBDIU1", - "DIBDI30": "BRAM_FIFO36_DIBDIL15", - "DIBDI31": "BRAM_FIFO36_DIBDIU15", - "DIBDI4": "BRAM_FIFO36_DIBDIL2", - "DIBDI5": "BRAM_FIFO36_DIBDIU2", - "DIBDI6": "BRAM_FIFO36_DIBDIL3", - "DIBDI7": "BRAM_FIFO36_DIBDIU3", - "DIBDI8": "BRAM_FIFO36_DIBDIL4", - "DIBDI9": "BRAM_FIFO36_DIBDIU4", - "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", - "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", - "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", - "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", - "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", - "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", - "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", - "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", - "DOADO0": "BRAM_FIFO36_DOADOL0", - "DOADO1": "BRAM_FIFO36_DOADOU0", - "DOADO10": "BRAM_FIFO36_DOADOL5", - "DOADO11": "BRAM_FIFO36_DOADOU5", - "DOADO12": "BRAM_FIFO36_DOADOL6", - "DOADO13": "BRAM_FIFO36_DOADOU6", - "DOADO14": "BRAM_FIFO36_DOADOL7", - "DOADO15": "BRAM_FIFO36_DOADOU7", - "DOADO16": "BRAM_FIFO36_DOADOL8", - "DOADO17": "BRAM_FIFO36_DOADOU8", - "DOADO18": "BRAM_FIFO36_DOADOL9", - "DOADO19": "BRAM_FIFO36_DOADOU9", - "DOADO2": "BRAM_FIFO36_DOADOL1", - "DOADO20": "BRAM_FIFO36_DOADOL10", - "DOADO21": "BRAM_FIFO36_DOADOU10", - "DOADO22": "BRAM_FIFO36_DOADOL11", - "DOADO23": "BRAM_FIFO36_DOADOU11", - "DOADO24": "BRAM_FIFO36_DOADOL12", - "DOADO25": "BRAM_FIFO36_DOADOU12", - "DOADO26": "BRAM_FIFO36_DOADOL13", - "DOADO27": "BRAM_FIFO36_DOADOU13", - "DOADO28": "BRAM_FIFO36_DOADOL14", - "DOADO29": "BRAM_FIFO36_DOADOU14", - "DOADO3": "BRAM_FIFO36_DOADOU1", - "DOADO30": "BRAM_FIFO36_DOADOL15", - "DOADO31": "BRAM_FIFO36_DOADOU15", - "DOADO4": "BRAM_FIFO36_DOADOL2", - "DOADO5": "BRAM_FIFO36_DOADOU2", - "DOADO6": "BRAM_FIFO36_DOADOL3", - "DOADO7": "BRAM_FIFO36_DOADOU3", - "DOADO8": "BRAM_FIFO36_DOADOL4", - "DOADO9": "BRAM_FIFO36_DOADOU4", - "DOBDO0": "BRAM_FIFO36_DOBDOL0", - "DOBDO1": "BRAM_FIFO36_DOBDOU0", - "DOBDO10": "BRAM_FIFO36_DOBDOL5", - "DOBDO11": "BRAM_FIFO36_DOBDOU5", - "DOBDO12": "BRAM_FIFO36_DOBDOL6", - "DOBDO13": "BRAM_FIFO36_DOBDOU6", - "DOBDO14": "BRAM_FIFO36_DOBDOL7", - "DOBDO15": "BRAM_FIFO36_DOBDOU7", - "DOBDO16": "BRAM_FIFO36_DOBDOL8", - "DOBDO17": "BRAM_FIFO36_DOBDOU8", - "DOBDO18": "BRAM_FIFO36_DOBDOL9", - "DOBDO19": "BRAM_FIFO36_DOBDOU9", - "DOBDO2": "BRAM_FIFO36_DOBDOL1", - "DOBDO20": "BRAM_FIFO36_DOBDOL10", - "DOBDO21": "BRAM_FIFO36_DOBDOU10", - "DOBDO22": "BRAM_FIFO36_DOBDOL11", - "DOBDO23": "BRAM_FIFO36_DOBDOU11", - "DOBDO24": "BRAM_FIFO36_DOBDOL12", - "DOBDO25": "BRAM_FIFO36_DOBDOU12", - "DOBDO26": "BRAM_FIFO36_DOBDOL13", - "DOBDO27": "BRAM_FIFO36_DOBDOU13", - "DOBDO28": "BRAM_FIFO36_DOBDOL14", - "DOBDO29": "BRAM_FIFO36_DOBDOU14", - "DOBDO3": "BRAM_FIFO36_DOBDOU1", - "DOBDO30": "BRAM_FIFO36_DOBDOL15", - "DOBDO31": "BRAM_FIFO36_DOBDOU15", - "DOBDO4": "BRAM_FIFO36_DOBDOL2", - "DOBDO5": "BRAM_FIFO36_DOBDOU2", - "DOBDO6": "BRAM_FIFO36_DOBDOL3", - "DOBDO7": "BRAM_FIFO36_DOBDOU3", - "DOBDO8": "BRAM_FIFO36_DOBDOL4", - "DOBDO9": "BRAM_FIFO36_DOBDOU4", - "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", - "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", - "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", - "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", - "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", - "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", - "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", - "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", - "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", - "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", - "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", - "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", - "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", - "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", - "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", - "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", - "EMPTY": "BRAM_FIFO36_EMPTY", - "ENARDENL": "BRAM_FIFO36_ENARDENL", - "ENARDENU": "BRAM_FIFO36_ENARDENU", - "ENBWRENL": "BRAM_FIFO36_ENBWRENL", - "ENBWRENU": "BRAM_FIFO36_ENBWRENU", - "FULL": "BRAM_FIFO36_FULL", - "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", - "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", - "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", - "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", - "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", - "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", - "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", - "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", - "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", - "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", - "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", - "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", - "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", - "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", - "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", - "RDERR": "BRAM_FIFO36_RDERR", - "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", - "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", - "REGCEBL": "BRAM_FIFO36_REGCEBL", - "REGCEBU": "BRAM_FIFO36_REGCEBU", - "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", - "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU", - "REGCLKBL": "BRAM_FIFO36_REGCLKBL", - "REGCLKBU": "BRAM_FIFO36_REGCLKBU", - "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", - "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", - "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", - "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", - "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", - "RSTREGBL": "BRAM_FIFO36_RSTREGBL", - "RSTREGBU": "BRAM_FIFO36_RSTREGBU", - "SBITERR": "BRAM_FIFO36_SBITERR", - "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", - "TSTCNT0": "BRAM_FIFO36_TSTCNT0", - "TSTCNT1": "BRAM_FIFO36_TSTCNT1", - "TSTCNT10": "BRAM_FIFO36_TSTCNT10", - "TSTCNT11": "BRAM_FIFO36_TSTCNT11", - "TSTCNT12": "BRAM_FIFO36_TSTCNT12", - "TSTCNT2": "BRAM_FIFO36_TSTCNT2", - "TSTCNT3": "BRAM_FIFO36_TSTCNT3", - "TSTCNT4": "BRAM_FIFO36_TSTCNT4", - "TSTCNT5": "BRAM_FIFO36_TSTCNT5", - "TSTCNT6": "BRAM_FIFO36_TSTCNT6", - "TSTCNT7": "BRAM_FIFO36_TSTCNT7", - "TSTCNT8": "BRAM_FIFO36_TSTCNT8", - "TSTCNT9": "BRAM_FIFO36_TSTCNT9", - "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", - "TSTIN0": "BRAM_FIFO36_TSTIN0", - "TSTIN1": "BRAM_FIFO36_TSTIN1", - "TSTIN2": "BRAM_FIFO36_TSTIN2", - "TSTIN3": "BRAM_FIFO36_TSTIN3", - "TSTIN4": "BRAM_FIFO36_TSTIN4", - "TSTOFF": "BRAM_FIFO36_TSTOFF", - "TSTOUT0": "BRAM_FIFO36_TSTOUT0", - "TSTOUT1": "BRAM_FIFO36_TSTOUT1", - "TSTOUT2": "BRAM_FIFO36_TSTOUT2", - "TSTOUT3": "BRAM_FIFO36_TSTOUT3", - "TSTOUT4": "BRAM_FIFO36_TSTOUT4", - "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", - "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", - "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", - "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", - "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", - "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", - "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", - "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", - "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", - "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", - "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", - "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", - "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", - "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", - "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", - "TSTWROS0": "BRAM_FIFO36_TSTWROS0", - "TSTWROS1": "BRAM_FIFO36_TSTWROS1", - "TSTWROS10": "BRAM_FIFO36_TSTWROS10", - "TSTWROS11": "BRAM_FIFO36_TSTWROS11", - "TSTWROS12": "BRAM_FIFO36_TSTWROS12", - "TSTWROS2": "BRAM_FIFO36_TSTWROS2", - "TSTWROS3": "BRAM_FIFO36_TSTWROS3", - "TSTWROS4": "BRAM_FIFO36_TSTWROS4", - "TSTWROS5": "BRAM_FIFO36_TSTWROS5", - "TSTWROS6": "BRAM_FIFO36_TSTWROS6", - "TSTWROS7": "BRAM_FIFO36_TSTWROS7", - "TSTWROS8": "BRAM_FIFO36_TSTWROS8", - "TSTWROS9": "BRAM_FIFO36_TSTWROS9", - "WEAL0": "BRAM_FIFO36_WEAL0", - "WEAL1": "BRAM_FIFO36_WEAL1", - "WEAL2": "BRAM_FIFO36_WEAL2", - "WEAL3": "BRAM_FIFO36_WEAL3", - "WEAU0": "BRAM_FIFO36_WEAU0", - "WEAU1": "BRAM_FIFO36_WEAU1", - "WEAU2": "BRAM_FIFO36_WEAU2", - "WEAU3": "BRAM_FIFO36_WEAU3", - "WEBWEL0": "BRAM_FIFO36_WEBWEL0", - "WEBWEL1": "BRAM_FIFO36_WEBWEL1", - "WEBWEL2": "BRAM_FIFO36_WEBWEL2", - "WEBWEL3": "BRAM_FIFO36_WEBWEL3", - "WEBWEL4": "BRAM_FIFO36_WEBWEL4", - "WEBWEL5": "BRAM_FIFO36_WEBWEL5", - "WEBWEL6": "BRAM_FIFO36_WEBWEL6", - "WEBWEL7": "BRAM_FIFO36_WEBWEL7", - "WEBWEU0": "BRAM_FIFO36_WEBWEU0", - "WEBWEU1": "BRAM_FIFO36_WEBWEU1", - "WEBWEU2": "BRAM_FIFO36_WEBWEU2", - "WEBWEU3": "BRAM_FIFO36_WEBWEU3", - "WEBWEU4": "BRAM_FIFO36_WEBWEU4", - "WEBWEU5": "BRAM_FIFO36_WEBWEU5", - "WEBWEU6": "BRAM_FIFO36_WEBWEU6", - "WEBWEU7": "BRAM_FIFO36_WEBWEU7", - "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", - "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", - "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", - "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", - "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", - "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", - "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", - "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", - "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", - "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", - "WRCOUNT7": "BRAM_FIFO36_WRCOUNT7", - "WRCOUNT8": "BRAM_FIFO36_WRCOUNT8", - "WRCOUNT9": "BRAM_FIFO36_WRCOUNT9", - "WRERR": "BRAM_FIFO36_WRERR" + "ADDRARDADDRL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL0" + }, + "ADDRARDADDRL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL1" + }, + "ADDRARDADDRL10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL10" + }, + "ADDRARDADDRL11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL11" + }, + "ADDRARDADDRL12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL12" + }, + "ADDRARDADDRL13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL13" + }, + "ADDRARDADDRL14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL14" + }, + "ADDRARDADDRL15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL15" + }, + "ADDRARDADDRL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL2" + }, + "ADDRARDADDRL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL3" + }, + "ADDRARDADDRL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL4" + }, + "ADDRARDADDRL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL5" + }, + "ADDRARDADDRL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_ADDRARDADDRL6" + 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"BRAM_FIFO36_WRCOUNT6" + }, + "WRCOUNT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT7" + }, + "WRCOUNT8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT8" + }, + "WRCOUNT9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT9" + }, + "WRERR": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRERR" + } }, "type": "RAMBFIFO36E1", "x_coord": 0, @@ -7189,164 +23287,1586 @@ "name": "X0Y0", "prefix": "RAMB18", "site_pins": { - "ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0", - "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", - "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", - "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", - "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12", - "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", - "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", - "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", - "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", - "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", - "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", - "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", - "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", - "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", - "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", - "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", - "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", - "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", - "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", - "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", - "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", - "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", - "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", - "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", - "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", - "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", - "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", - "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", - "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", - "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", - "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", - "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", - "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", - "DIADI0": "BRAM_FIFO18_DIADI0", - "DIADI1": "BRAM_FIFO18_DIADI1", - "DIADI10": "BRAM_FIFO18_DIADI10", - "DIADI11": "BRAM_FIFO18_DIADI11", - "DIADI12": "BRAM_FIFO18_DIADI12", - "DIADI13": "BRAM_FIFO18_DIADI13", - "DIADI14": "BRAM_FIFO18_DIADI14", - "DIADI15": "BRAM_FIFO18_DIADI15", - "DIADI2": "BRAM_FIFO18_DIADI2", - "DIADI3": "BRAM_FIFO18_DIADI3", - "DIADI4": "BRAM_FIFO18_DIADI4", - "DIADI5": "BRAM_FIFO18_DIADI5", - "DIADI6": "BRAM_FIFO18_DIADI6", - "DIADI7": "BRAM_FIFO18_DIADI7", - "DIADI8": "BRAM_FIFO18_DIADI8", - "DIADI9": "BRAM_FIFO18_DIADI9", - "DIBDI0": "BRAM_FIFO18_DIBDI0", - "DIBDI1": "BRAM_FIFO18_DIBDI1", - "DIBDI10": "BRAM_FIFO18_DIBDI10", - "DIBDI11": "BRAM_FIFO18_DIBDI11", - "DIBDI12": "BRAM_FIFO18_DIBDI12", - "DIBDI13": "BRAM_FIFO18_DIBDI13", - "DIBDI14": "BRAM_FIFO18_DIBDI14", - "DIBDI15": "BRAM_FIFO18_DIBDI15", - "DIBDI2": "BRAM_FIFO18_DIBDI2", - "DIBDI3": "BRAM_FIFO18_DIBDI3", - "DIBDI4": "BRAM_FIFO18_DIBDI4", - "DIBDI5": "BRAM_FIFO18_DIBDI5", - "DIBDI6": "BRAM_FIFO18_DIBDI6", - "DIBDI7": "BRAM_FIFO18_DIBDI7", - "DIBDI8": "BRAM_FIFO18_DIBDI8", - "DIBDI9": "BRAM_FIFO18_DIBDI9", - "DIPADIP0": "BRAM_FIFO18_DIPADIP0", - "DIPADIP1": "BRAM_FIFO18_DIPADIP1", - "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", - "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", - "DO0": "BRAM_FIFO18_DOADO0", - "DO1": "BRAM_FIFO18_DOADO1", - "DO10": "BRAM_FIFO18_DOADO10", - "DO11": "BRAM_FIFO18_DOADO11", - "DO12": "BRAM_FIFO18_DOADO12", - "DO13": "BRAM_FIFO18_DOADO13", - "DO14": "BRAM_FIFO18_DOADO14", - "DO15": "BRAM_FIFO18_DOADO15", - "DO16": "BRAM_FIFO18_DOBDO0", - "DO17": "BRAM_FIFO18_DOBDO1", - "DO18": "BRAM_FIFO18_DOBDO2", - "DO19": "BRAM_FIFO18_DOBDO3", - "DO2": "BRAM_FIFO18_DOADO2", - "DO20": "BRAM_FIFO18_DOBDO4", - "DO21": "BRAM_FIFO18_DOBDO5", - "DO22": "BRAM_FIFO18_DOBDO6", - "DO23": "BRAM_FIFO18_DOBDO7", - "DO24": "BRAM_FIFO18_DOBDO8", - "DO25": "BRAM_FIFO18_DOBDO9", - "DO26": "BRAM_FIFO18_DOBDO10", - "DO27": "BRAM_FIFO18_DOBDO11", - "DO28": "BRAM_FIFO18_DOBDO12", - "DO29": "BRAM_FIFO18_DOBDO13", - "DO3": "BRAM_FIFO18_DOADO3", - "DO30": "BRAM_FIFO18_DOBDO14", - "DO31": "BRAM_FIFO18_DOBDO15", - "DO4": "BRAM_FIFO18_DOADO4", - "DO5": "BRAM_FIFO18_DOADO5", - "DO6": "BRAM_FIFO18_DOADO6", - "DO7": "BRAM_FIFO18_DOADO7", - "DO8": "BRAM_FIFO18_DOADO8", - "DO9": "BRAM_FIFO18_DOADO9", - "DOP0": "BRAM_FIFO18_DOPADOP0", - "DOP1": "BRAM_FIFO18_DOPADOP1", - "DOP2": "BRAM_FIFO18_DOPBDOP0", - "DOP3": "BRAM_FIFO18_DOPBDOP1", - "EMPTY": "BRAM_FIFO18_EMPTY", - "FULL": "BRAM_FIFO18_FULL", - "RDCLK": "BRAM_FIFO18_CLKARDCLK", - "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", - "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", - "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", - "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", - "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", - "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", - "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", - "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", - "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", - "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", - "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", - "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", - "RDEN": "BRAM_FIFO18_ENARDEN", - "RDERR": "BRAM_FIFO18_RDERR", - "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", - "REGCE": "BRAM_FIFO18_REGCEAREGCE", - "REGCEB": "BRAM_FIFO18_REGCEB", - "REGCLKB": "BRAM_FIFO18_REGCLKB", - "RST": "BRAM_FIFO18_RSTRAMARSTRAM", - "RSTRAMB": "BRAM_FIFO18_RSTRAMB", - "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", - "RSTREGB": "BRAM_FIFO18_RSTREGB", - "WEA0": "BRAM_FIFO18_WEA0", - "WEA1": "BRAM_FIFO18_WEA1", - "WEA2": "BRAM_FIFO18_WEA2", - "WEA3": "BRAM_FIFO18_WEA3", - "WEBWE0": "BRAM_FIFO18_WEBWE0", - "WEBWE1": "BRAM_FIFO18_WEBWE1", - "WEBWE2": "BRAM_FIFO18_WEBWE2", - "WEBWE3": "BRAM_FIFO18_WEBWE3", - "WEBWE4": "BRAM_FIFO18_WEBWE4", - "WEBWE5": "BRAM_FIFO18_WEBWE5", - "WEBWE6": "BRAM_FIFO18_WEBWE6", - "WEBWE7": "BRAM_FIFO18_WEBWE7", - "WRCLK": "BRAM_FIFO18_CLKBWRCLK", - "WRCOUNT0": "BRAM_FIFO18_WRCOUNT0", - "WRCOUNT1": "BRAM_FIFO18_WRCOUNT1", - "WRCOUNT10": "BRAM_FIFO18_WRCOUNT10", - "WRCOUNT11": "BRAM_FIFO18_WRCOUNT11", - "WRCOUNT2": "BRAM_FIFO18_WRCOUNT2", - "WRCOUNT3": "BRAM_FIFO18_WRCOUNT3", - "WRCOUNT4": "BRAM_FIFO18_WRCOUNT4", - "WRCOUNT5": "BRAM_FIFO18_WRCOUNT5", - "WRCOUNT6": "BRAM_FIFO18_WRCOUNT6", - "WRCOUNT7": "BRAM_FIFO18_WRCOUNT7", - "WRCOUNT8": "BRAM_FIFO18_WRCOUNT8", - "WRCOUNT9": "BRAM_FIFO18_WRCOUNT9", - "WREN": "BRAM_FIFO18_ENBWREN", - "WRERR": "BRAM_FIFO18_WRERR" + "ADDRARDADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR0" + }, + "ADDRARDADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR1" + }, + "ADDRARDADDR10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR10" + }, + "ADDRARDADDR11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR11" + }, + "ADDRARDADDR12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR12" + }, + "ADDRARDADDR13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR13" + }, + "ADDRARDADDR2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR2" + }, + "ADDRARDADDR3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR3" + }, + "ADDRARDADDR4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR4" + }, + "ADDRARDADDR5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + 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"860.0625", + "wire": "BRAM_RAMB18_WRCOUNT11" + }, + "WRCOUNT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT2" + }, + "WRCOUNT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT3" + }, + "WRCOUNT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT4" + }, + "WRCOUNT5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT5" + }, + "WRCOUNT6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT6" + }, + "WRCOUNT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT7" + }, + "WRCOUNT8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT8" + }, + "WRCOUNT9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRCOUNT9" + }, + "WRERR": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_RAMB18_WRERR" + } }, "type": "RAMB18E1", "x_coord": 0, @@ -7521,2314 +26463,6136 @@ } ], "tile_type": "BRAM_L", - "wires": [ - "BRAM_ADDRARDADDRL0", - "BRAM_ADDRARDADDRL1", - "BRAM_ADDRARDADDRL10", - "BRAM_ADDRARDADDRL11", - "BRAM_ADDRARDADDRL12", - "BRAM_ADDRARDADDRL13", - "BRAM_ADDRARDADDRL14", - "BRAM_ADDRARDADDRL2", - "BRAM_ADDRARDADDRL3", - "BRAM_ADDRARDADDRL4", - "BRAM_ADDRARDADDRL5", - "BRAM_ADDRARDADDRL6", - "BRAM_ADDRARDADDRL7", - "BRAM_ADDRARDADDRL8", - "BRAM_ADDRARDADDRL9", - "BRAM_ADDRARDADDRU0", - "BRAM_ADDRARDADDRU1", - "BRAM_ADDRARDADDRU10", - "BRAM_ADDRARDADDRU11", - "BRAM_ADDRARDADDRU12", - "BRAM_ADDRARDADDRU13", - "BRAM_ADDRARDADDRU14", - "BRAM_ADDRARDADDRU2", - "BRAM_ADDRARDADDRU3", - "BRAM_ADDRARDADDRU4", - "BRAM_ADDRARDADDRU5", - "BRAM_ADDRARDADDRU6", - "BRAM_ADDRARDADDRU7", - "BRAM_ADDRARDADDRU8", - "BRAM_ADDRARDADDRU9", - "BRAM_ADDRBWRADDRL0", - "BRAM_ADDRBWRADDRL1", - "BRAM_ADDRBWRADDRL10", - "BRAM_ADDRBWRADDRL11", - "BRAM_ADDRBWRADDRL12", - "BRAM_ADDRBWRADDRL13", - "BRAM_ADDRBWRADDRL14", - "BRAM_ADDRBWRADDRL2", - "BRAM_ADDRBWRADDRL3", - "BRAM_ADDRBWRADDRL4", - "BRAM_ADDRBWRADDRL5", - "BRAM_ADDRBWRADDRL6", - "BRAM_ADDRBWRADDRL7", - "BRAM_ADDRBWRADDRL8", - "BRAM_ADDRBWRADDRL9", - "BRAM_ADDRBWRADDRU0", - "BRAM_ADDRBWRADDRU1", - "BRAM_ADDRBWRADDRU10", - "BRAM_ADDRBWRADDRU11", - "BRAM_ADDRBWRADDRU12", - "BRAM_ADDRBWRADDRU13", - "BRAM_ADDRBWRADDRU14", - "BRAM_ADDRBWRADDRU2", - "BRAM_ADDRBWRADDRU3", - "BRAM_ADDRBWRADDRU4", - "BRAM_ADDRBWRADDRU5", - "BRAM_ADDRBWRADDRU6", - "BRAM_ADDRBWRADDRU7", - "BRAM_ADDRBWRADDRU8", - "BRAM_ADDRBWRADDRU9", - "BRAM_BLOCK_OUTS_L_B0_0", - "BRAM_BLOCK_OUTS_L_B0_1", - "BRAM_BLOCK_OUTS_L_B0_2", - "BRAM_BLOCK_OUTS_L_B0_3", - "BRAM_BLOCK_OUTS_L_B0_4", - "BRAM_BLOCK_OUTS_L_B1_0", - "BRAM_BLOCK_OUTS_L_B1_1", - "BRAM_BLOCK_OUTS_L_B1_2", - "BRAM_BLOCK_OUTS_L_B1_3", - "BRAM_BLOCK_OUTS_L_B1_4", - "BRAM_BLOCK_OUTS_L_B2_0", - "BRAM_BLOCK_OUTS_L_B2_1", - "BRAM_BLOCK_OUTS_L_B2_2", - "BRAM_BLOCK_OUTS_L_B2_3", - "BRAM_BLOCK_OUTS_L_B2_4", - "BRAM_BLOCK_OUTS_L_B3_0", - "BRAM_BLOCK_OUTS_L_B3_1", - "BRAM_BLOCK_OUTS_L_B3_2", - "BRAM_BLOCK_OUTS_L_B3_3", - "BRAM_BLOCK_OUTS_L_B3_4", - "BRAM_BYP0_0", - "BRAM_BYP0_1", - "BRAM_BYP0_2", - "BRAM_BYP0_3", - "BRAM_BYP0_4", - "BRAM_BYP1_0", - "BRAM_BYP1_1", - "BRAM_BYP1_2", - "BRAM_BYP1_3", - "BRAM_BYP1_4", - "BRAM_BYP2_0", - "BRAM_BYP2_1", - "BRAM_BYP2_2", - "BRAM_BYP2_3", - "BRAM_BYP2_4", - "BRAM_BYP3_0", - "BRAM_BYP3_1", - "BRAM_BYP3_2", - "BRAM_BYP3_3", - "BRAM_BYP3_4", - "BRAM_BYP4_0", - "BRAM_BYP4_1", - "BRAM_BYP4_2", - "BRAM_BYP4_3", - "BRAM_BYP4_4", - "BRAM_BYP5_0", - "BRAM_BYP5_1", - "BRAM_BYP5_2", - "BRAM_BYP5_3", - "BRAM_BYP5_4", - "BRAM_BYP6_0", - "BRAM_BYP6_1", - "BRAM_BYP6_2", - "BRAM_BYP6_3", - "BRAM_BYP6_4", - "BRAM_BYP7_0", - "BRAM_BYP7_1", - "BRAM_BYP7_2", - "BRAM_BYP7_3", - "BRAM_BYP7_4", - "BRAM_CASCINBOT_ADDRARDADDRU0", - "BRAM_CASCINBOT_ADDRARDADDRU1", - "BRAM_CASCINBOT_ADDRARDADDRU10", - "BRAM_CASCINBOT_ADDRARDADDRU11", - "BRAM_CASCINBOT_ADDRARDADDRU12", - "BRAM_CASCINBOT_ADDRARDADDRU13", - "BRAM_CASCINBOT_ADDRARDADDRU14", - "BRAM_CASCINBOT_ADDRARDADDRU2", - "BRAM_CASCINBOT_ADDRARDADDRU3", - "BRAM_CASCINBOT_ADDRARDADDRU4", - "BRAM_CASCINBOT_ADDRARDADDRU5", - "BRAM_CASCINBOT_ADDRARDADDRU6", - "BRAM_CASCINBOT_ADDRARDADDRU7", - "BRAM_CASCINBOT_ADDRARDADDRU8", - "BRAM_CASCINBOT_ADDRARDADDRU9", - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "BRAM_CASCINBOT_ADDRBWRADDRU10", - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRAM_CASCOUT_ADDRARDADDRU0", - "BRAM_CASCOUT_ADDRARDADDRU1", - "BRAM_CASCOUT_ADDRARDADDRU10", - "BRAM_CASCOUT_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU12", - "BRAM_CASCOUT_ADDRARDADDRU13", - "BRAM_CASCOUT_ADDRARDADDRU14", - "BRAM_CASCOUT_ADDRARDADDRU2", - "BRAM_CASCOUT_ADDRARDADDRU3", - "BRAM_CASCOUT_ADDRARDADDRU4", - "BRAM_CASCOUT_ADDRARDADDRU5", - "BRAM_CASCOUT_ADDRARDADDRU6", - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRARDADDRU8", - "BRAM_CASCOUT_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU1", - "BRAM_CASCOUT_ADDRBWRADDRU10", - "BRAM_CASCOUT_ADDRBWRADDRU11", - "BRAM_CASCOUT_ADDRBWRADDRU12", - "BRAM_CASCOUT_ADDRBWRADDRU13", - "BRAM_CASCOUT_ADDRBWRADDRU14", - "BRAM_CASCOUT_ADDRBWRADDRU2", - "BRAM_CASCOUT_ADDRBWRADDRU3", - "BRAM_CASCOUT_ADDRBWRADDRU4", - "BRAM_CASCOUT_ADDRBWRADDRU5", - "BRAM_CASCOUT_ADDRBWRADDRU6", - "BRAM_CASCOUT_ADDRBWRADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU8", - "BRAM_CASCOUT_ADDRBWRADDRU9", - "BRAM_CLK0_0", - "BRAM_CLK0_1", - "BRAM_CLK0_2", - "BRAM_CLK0_3", - "BRAM_CLK0_4", - "BRAM_CLK1_0", - "BRAM_CLK1_1", - "BRAM_CLK1_2", - "BRAM_CLK1_3", - "BRAM_CLK1_4", - "BRAM_CTRL0_0", - "BRAM_CTRL0_1", - "BRAM_CTRL0_2", - "BRAM_CTRL0_3", - "BRAM_CTRL0_4", - "BRAM_CTRL1_0", - "BRAM_CTRL1_1", - "BRAM_CTRL1_2", - "BRAM_CTRL1_3", - "BRAM_CTRL1_4", - "BRAM_EE2A0_0", - "BRAM_EE2A0_1", - "BRAM_EE2A0_2", - "BRAM_EE2A0_3", - "BRAM_EE2A0_4", - "BRAM_EE2A1_0", - "BRAM_EE2A1_1", - "BRAM_EE2A1_2", - "BRAM_EE2A1_3", - "BRAM_EE2A1_4", - "BRAM_EE2A2_0", - "BRAM_EE2A2_1", - "BRAM_EE2A2_2", - "BRAM_EE2A2_3", - "BRAM_EE2A2_4", - "BRAM_EE2A3_0", - "BRAM_EE2A3_1", - "BRAM_EE2A3_2", - "BRAM_EE2A3_3", - "BRAM_EE2A3_4", - "BRAM_EE2BEG0_0", - "BRAM_EE2BEG0_1", - "BRAM_EE2BEG0_2", - "BRAM_EE2BEG0_3", - "BRAM_EE2BEG0_4", - "BRAM_EE2BEG1_0", - "BRAM_EE2BEG1_1", - "BRAM_EE2BEG1_2", - "BRAM_EE2BEG1_3", - "BRAM_EE2BEG1_4", - "BRAM_EE2BEG2_0", - "BRAM_EE2BEG2_1", - "BRAM_EE2BEG2_2", - "BRAM_EE2BEG2_3", - "BRAM_EE2BEG2_4", - "BRAM_EE2BEG3_0", - "BRAM_EE2BEG3_1", - "BRAM_EE2BEG3_2", - "BRAM_EE2BEG3_3", - "BRAM_EE2BEG3_4", - "BRAM_EE4A0_0", - "BRAM_EE4A0_1", - "BRAM_EE4A0_2", - "BRAM_EE4A0_3", - "BRAM_EE4A0_4", - "BRAM_EE4A1_0", - "BRAM_EE4A1_1", - "BRAM_EE4A1_2", - "BRAM_EE4A1_3", - "BRAM_EE4A1_4", - "BRAM_EE4A2_0", - "BRAM_EE4A2_1", - "BRAM_EE4A2_2", - "BRAM_EE4A2_3", - "BRAM_EE4A2_4", - "BRAM_EE4A3_0", - "BRAM_EE4A3_1", - "BRAM_EE4A3_2", - "BRAM_EE4A3_3", - "BRAM_EE4A3_4", - "BRAM_EE4B0_0", - "BRAM_EE4B0_1", - "BRAM_EE4B0_2", - "BRAM_EE4B0_3", - "BRAM_EE4B0_4", - "BRAM_EE4B1_0", - "BRAM_EE4B1_1", - "BRAM_EE4B1_2", - "BRAM_EE4B1_3", - "BRAM_EE4B1_4", - "BRAM_EE4B2_0", - "BRAM_EE4B2_1", - "BRAM_EE4B2_2", - "BRAM_EE4B2_3", - "BRAM_EE4B2_4", - "BRAM_EE4B3_0", - "BRAM_EE4B3_1", - "BRAM_EE4B3_2", - "BRAM_EE4B3_3", - "BRAM_EE4B3_4", - "BRAM_EE4BEG0_0", - "BRAM_EE4BEG0_1", - "BRAM_EE4BEG0_2", - "BRAM_EE4BEG0_3", - "BRAM_EE4BEG0_4", - "BRAM_EE4BEG1_0", - "BRAM_EE4BEG1_1", - "BRAM_EE4BEG1_2", - "BRAM_EE4BEG1_3", - "BRAM_EE4BEG1_4", - "BRAM_EE4BEG2_0", - "BRAM_EE4BEG2_1", - "BRAM_EE4BEG2_2", - "BRAM_EE4BEG2_3", - "BRAM_EE4BEG2_4", - "BRAM_EE4BEG3_0", - "BRAM_EE4BEG3_1", - "BRAM_EE4BEG3_2", - "BRAM_EE4BEG3_3", - "BRAM_EE4BEG3_4", - "BRAM_EE4C0_0", - "BRAM_EE4C0_1", - "BRAM_EE4C0_2", - "BRAM_EE4C0_3", - "BRAM_EE4C0_4", - "BRAM_EE4C1_0", - "BRAM_EE4C1_1", - "BRAM_EE4C1_2", - "BRAM_EE4C1_3", - "BRAM_EE4C1_4", - "BRAM_EE4C2_0", - "BRAM_EE4C2_1", - "BRAM_EE4C2_2", - "BRAM_EE4C2_3", - "BRAM_EE4C2_4", - "BRAM_EE4C3_0", - "BRAM_EE4C3_1", - "BRAM_EE4C3_2", - "BRAM_EE4C3_3", - "BRAM_EE4C3_4", - "BRAM_EL1BEG0_0", - "BRAM_EL1BEG0_1", - "BRAM_EL1BEG0_2", - "BRAM_EL1BEG0_3", - "BRAM_EL1BEG0_4", - "BRAM_EL1BEG1_0", - "BRAM_EL1BEG1_1", - "BRAM_EL1BEG1_2", - "BRAM_EL1BEG1_3", - "BRAM_EL1BEG1_4", - "BRAM_EL1BEG2_0", - "BRAM_EL1BEG2_1", - "BRAM_EL1BEG2_2", - "BRAM_EL1BEG2_3", - "BRAM_EL1BEG2_4", - "BRAM_EL1BEG3_0", - "BRAM_EL1BEG3_1", - "BRAM_EL1BEG3_2", - "BRAM_EL1BEG3_3", - "BRAM_EL1BEG3_4", - "BRAM_ER1BEG0_0", - "BRAM_ER1BEG0_1", - "BRAM_ER1BEG0_2", - "BRAM_ER1BEG0_3", - "BRAM_ER1BEG0_4", - "BRAM_ER1BEG1_0", - "BRAM_ER1BEG1_1", - "BRAM_ER1BEG1_2", - "BRAM_ER1BEG1_3", - "BRAM_ER1BEG1_4", - "BRAM_ER1BEG2_0", - "BRAM_ER1BEG2_1", - "BRAM_ER1BEG2_2", - "BRAM_ER1BEG2_3", - "BRAM_ER1BEG2_4", - "BRAM_ER1BEG3_0", - "BRAM_ER1BEG3_1", - "BRAM_ER1BEG3_2", - "BRAM_ER1BEG3_3", - "BRAM_ER1BEG3_4", - "BRAM_FAN0_0", - "BRAM_FAN0_1", - "BRAM_FAN0_2", - "BRAM_FAN0_3", - "BRAM_FAN0_4", - "BRAM_FAN1_0", - "BRAM_FAN1_1", - "BRAM_FAN1_2", - "BRAM_FAN1_3", - "BRAM_FAN1_4", - "BRAM_FAN2_0", - "BRAM_FAN2_1", - "BRAM_FAN2_2", - "BRAM_FAN2_3", - "BRAM_FAN2_4", - "BRAM_FAN3_0", - "BRAM_FAN3_1", - "BRAM_FAN3_2", - "BRAM_FAN3_3", - "BRAM_FAN3_4", - "BRAM_FAN4_0", - "BRAM_FAN4_1", - "BRAM_FAN4_2", - "BRAM_FAN4_3", - "BRAM_FAN4_4", - "BRAM_FAN5_0", - "BRAM_FAN5_1", - "BRAM_FAN5_2", - "BRAM_FAN5_3", - "BRAM_FAN5_4", - "BRAM_FAN6_0", - "BRAM_FAN6_1", - "BRAM_FAN6_2", - "BRAM_FAN6_3", - "BRAM_FAN6_4", - "BRAM_FAN7_0", - "BRAM_FAN7_1", - "BRAM_FAN7_2", - "BRAM_FAN7_3", - "BRAM_FAN7_4", - "BRAM_FIFO18_ADDRARDADDR0", - "BRAM_FIFO18_ADDRARDADDR1", - "BRAM_FIFO18_ADDRARDADDR10", - "BRAM_FIFO18_ADDRARDADDR11", - "BRAM_FIFO18_ADDRARDADDR12", - "BRAM_FIFO18_ADDRARDADDR13", - "BRAM_FIFO18_ADDRARDADDR2", - "BRAM_FIFO18_ADDRARDADDR3", - "BRAM_FIFO18_ADDRARDADDR4", - "BRAM_FIFO18_ADDRARDADDR5", - "BRAM_FIFO18_ADDRARDADDR6", - "BRAM_FIFO18_ADDRARDADDR7", - "BRAM_FIFO18_ADDRARDADDR8", - "BRAM_FIFO18_ADDRARDADDR9", - "BRAM_FIFO18_ADDRATIEHIGH0", - "BRAM_FIFO18_ADDRATIEHIGH1", - "BRAM_FIFO18_ADDRBTIEHIGH0", - "BRAM_FIFO18_ADDRBTIEHIGH1", - "BRAM_FIFO18_ADDRBWRADDR0", - "BRAM_FIFO18_ADDRBWRADDR1", - "BRAM_FIFO18_ADDRBWRADDR10", - "BRAM_FIFO18_ADDRBWRADDR11", - "BRAM_FIFO18_ADDRBWRADDR12", - "BRAM_FIFO18_ADDRBWRADDR13", - "BRAM_FIFO18_ADDRBWRADDR2", - "BRAM_FIFO18_ADDRBWRADDR3", - "BRAM_FIFO18_ADDRBWRADDR4", - "BRAM_FIFO18_ADDRBWRADDR5", - "BRAM_FIFO18_ADDRBWRADDR6", - "BRAM_FIFO18_ADDRBWRADDR7", - "BRAM_FIFO18_ADDRBWRADDR8", - "BRAM_FIFO18_ADDRBWRADDR9", - "BRAM_FIFO18_ALMOSTEMPTY", - "BRAM_FIFO18_ALMOSTFULL", - "BRAM_FIFO18_CLKARDCLK", - "BRAM_FIFO18_CLKBWRCLK", - "BRAM_FIFO18_DIADI0", - "BRAM_FIFO18_DIADI1", - "BRAM_FIFO18_DIADI10", - "BRAM_FIFO18_DIADI11", - "BRAM_FIFO18_DIADI12", - "BRAM_FIFO18_DIADI13", - "BRAM_FIFO18_DIADI14", - "BRAM_FIFO18_DIADI15", - "BRAM_FIFO18_DIADI2", - "BRAM_FIFO18_DIADI3", - "BRAM_FIFO18_DIADI4", - "BRAM_FIFO18_DIADI5", - "BRAM_FIFO18_DIADI6", - "BRAM_FIFO18_DIADI7", - "BRAM_FIFO18_DIADI8", - "BRAM_FIFO18_DIADI9", - "BRAM_FIFO18_DIBDI0", - "BRAM_FIFO18_DIBDI1", - "BRAM_FIFO18_DIBDI10", - "BRAM_FIFO18_DIBDI11", - "BRAM_FIFO18_DIBDI12", - "BRAM_FIFO18_DIBDI13", - "BRAM_FIFO18_DIBDI14", - "BRAM_FIFO18_DIBDI15", - "BRAM_FIFO18_DIBDI2", - "BRAM_FIFO18_DIBDI3", - "BRAM_FIFO18_DIBDI4", - "BRAM_FIFO18_DIBDI5", - "BRAM_FIFO18_DIBDI6", - "BRAM_FIFO18_DIBDI7", - "BRAM_FIFO18_DIBDI8", - "BRAM_FIFO18_DIBDI9", - "BRAM_FIFO18_DIPADIP0", - "BRAM_FIFO18_DIPADIP1", - "BRAM_FIFO18_DIPBDIP0", - "BRAM_FIFO18_DIPBDIP1", - "BRAM_FIFO18_DOADO0", - "BRAM_FIFO18_DOADO1", - "BRAM_FIFO18_DOADO10", - "BRAM_FIFO18_DOADO11", - "BRAM_FIFO18_DOADO12", - "BRAM_FIFO18_DOADO13", - "BRAM_FIFO18_DOADO14", - "BRAM_FIFO18_DOADO15", - "BRAM_FIFO18_DOADO2", - "BRAM_FIFO18_DOADO3", - "BRAM_FIFO18_DOADO4", - "BRAM_FIFO18_DOADO5", - "BRAM_FIFO18_DOADO6", - "BRAM_FIFO18_DOADO7", - "BRAM_FIFO18_DOADO8", - "BRAM_FIFO18_DOADO9", - "BRAM_FIFO18_DOBDO0", - "BRAM_FIFO18_DOBDO1", - "BRAM_FIFO18_DOBDO10", - "BRAM_FIFO18_DOBDO11", - "BRAM_FIFO18_DOBDO12", - "BRAM_FIFO18_DOBDO13", - "BRAM_FIFO18_DOBDO14", - "BRAM_FIFO18_DOBDO15", - "BRAM_FIFO18_DOBDO2", - "BRAM_FIFO18_DOBDO3", - "BRAM_FIFO18_DOBDO4", - "BRAM_FIFO18_DOBDO5", - "BRAM_FIFO18_DOBDO6", - "BRAM_FIFO18_DOBDO7", - "BRAM_FIFO18_DOBDO8", - "BRAM_FIFO18_DOBDO9", - "BRAM_FIFO18_DOPADOP0", - "BRAM_FIFO18_DOPADOP1", - "BRAM_FIFO18_DOPBDOP0", - "BRAM_FIFO18_DOPBDOP1", - "BRAM_FIFO18_EMPTY", - "BRAM_FIFO18_ENARDEN", - "BRAM_FIFO18_ENBWREN", - "BRAM_FIFO18_FULL", - "BRAM_FIFO18_RDCOUNT0", - "BRAM_FIFO18_RDCOUNT1", - "BRAM_FIFO18_RDCOUNT10", - "BRAM_FIFO18_RDCOUNT11", - "BRAM_FIFO18_RDCOUNT2", - "BRAM_FIFO18_RDCOUNT3", - "BRAM_FIFO18_RDCOUNT4", - "BRAM_FIFO18_RDCOUNT5", - "BRAM_FIFO18_RDCOUNT6", - "BRAM_FIFO18_RDCOUNT7", - "BRAM_FIFO18_RDCOUNT8", - "BRAM_FIFO18_RDCOUNT9", - "BRAM_FIFO18_RDERR", - "BRAM_FIFO18_REGCEAREGCE", - "BRAM_FIFO18_REGCEB", - "BRAM_FIFO18_REGCLKARDRCLK", - "BRAM_FIFO18_REGCLKB", - "BRAM_FIFO18_RSTRAMARSTRAM", - "BRAM_FIFO18_RSTRAMB", - "BRAM_FIFO18_RSTREGARSTREG", - "BRAM_FIFO18_RSTREGB", - "BRAM_FIFO18_WEA0", - "BRAM_FIFO18_WEA1", - "BRAM_FIFO18_WEA2", - "BRAM_FIFO18_WEA3", - "BRAM_FIFO18_WEBWE0", - "BRAM_FIFO18_WEBWE1", - "BRAM_FIFO18_WEBWE2", - "BRAM_FIFO18_WEBWE3", - "BRAM_FIFO18_WEBWE4", - "BRAM_FIFO18_WEBWE5", - "BRAM_FIFO18_WEBWE6", - "BRAM_FIFO18_WEBWE7", - "BRAM_FIFO18_WRCOUNT0", - "BRAM_FIFO18_WRCOUNT1", - "BRAM_FIFO18_WRCOUNT10", - "BRAM_FIFO18_WRCOUNT11", - "BRAM_FIFO18_WRCOUNT2", - "BRAM_FIFO18_WRCOUNT3", - "BRAM_FIFO18_WRCOUNT4", - "BRAM_FIFO18_WRCOUNT5", - "BRAM_FIFO18_WRCOUNT6", - "BRAM_FIFO18_WRCOUNT7", - "BRAM_FIFO18_WRCOUNT8", - "BRAM_FIFO18_WRCOUNT9", - "BRAM_FIFO18_WRERR", - "BRAM_FIFO36_ADDRARDADDRL0", - "BRAM_FIFO36_ADDRARDADDRL1", - "BRAM_FIFO36_ADDRARDADDRL10", - "BRAM_FIFO36_ADDRARDADDRL11", - "BRAM_FIFO36_ADDRARDADDRL12", - "BRAM_FIFO36_ADDRARDADDRL13", - "BRAM_FIFO36_ADDRARDADDRL14", - "BRAM_FIFO36_ADDRARDADDRL15", - "BRAM_FIFO36_ADDRARDADDRL2", - "BRAM_FIFO36_ADDRARDADDRL3", - "BRAM_FIFO36_ADDRARDADDRL4", - "BRAM_FIFO36_ADDRARDADDRL5", - "BRAM_FIFO36_ADDRARDADDRL6", - "BRAM_FIFO36_ADDRARDADDRL7", - "BRAM_FIFO36_ADDRARDADDRL8", - "BRAM_FIFO36_ADDRARDADDRL9", - "BRAM_FIFO36_ADDRARDADDRU0", - "BRAM_FIFO36_ADDRARDADDRU1", - "BRAM_FIFO36_ADDRARDADDRU10", - "BRAM_FIFO36_ADDRARDADDRU11", - "BRAM_FIFO36_ADDRARDADDRU12", - "BRAM_FIFO36_ADDRARDADDRU13", - "BRAM_FIFO36_ADDRARDADDRU14", - "BRAM_FIFO36_ADDRARDADDRU2", - "BRAM_FIFO36_ADDRARDADDRU3", - "BRAM_FIFO36_ADDRARDADDRU4", - "BRAM_FIFO36_ADDRARDADDRU5", - "BRAM_FIFO36_ADDRARDADDRU6", - "BRAM_FIFO36_ADDRARDADDRU7", - "BRAM_FIFO36_ADDRARDADDRU8", - "BRAM_FIFO36_ADDRARDADDRU9", - "BRAM_FIFO36_ADDRBWRADDRL0", - "BRAM_FIFO36_ADDRBWRADDRL1", - "BRAM_FIFO36_ADDRBWRADDRL10", - "BRAM_FIFO36_ADDRBWRADDRL11", - "BRAM_FIFO36_ADDRBWRADDRL12", - "BRAM_FIFO36_ADDRBWRADDRL13", - "BRAM_FIFO36_ADDRBWRADDRL14", - "BRAM_FIFO36_ADDRBWRADDRL15", - "BRAM_FIFO36_ADDRBWRADDRL2", - "BRAM_FIFO36_ADDRBWRADDRL3", - "BRAM_FIFO36_ADDRBWRADDRL4", - "BRAM_FIFO36_ADDRBWRADDRL5", - "BRAM_FIFO36_ADDRBWRADDRL6", - "BRAM_FIFO36_ADDRBWRADDRL7", - "BRAM_FIFO36_ADDRBWRADDRL8", - "BRAM_FIFO36_ADDRBWRADDRL9", - "BRAM_FIFO36_ADDRBWRADDRU0", - "BRAM_FIFO36_ADDRBWRADDRU1", - "BRAM_FIFO36_ADDRBWRADDRU10", - "BRAM_FIFO36_ADDRBWRADDRU11", - "BRAM_FIFO36_ADDRBWRADDRU12", - "BRAM_FIFO36_ADDRBWRADDRU13", - "BRAM_FIFO36_ADDRBWRADDRU14", - "BRAM_FIFO36_ADDRBWRADDRU2", - "BRAM_FIFO36_ADDRBWRADDRU3", - "BRAM_FIFO36_ADDRBWRADDRU4", - "BRAM_FIFO36_ADDRBWRADDRU5", - "BRAM_FIFO36_ADDRBWRADDRU6", - "BRAM_FIFO36_ADDRBWRADDRU7", - "BRAM_FIFO36_ADDRBWRADDRU8", - "BRAM_FIFO36_ADDRBWRADDRU9", - "BRAM_FIFO36_ALMOSTEMPTY", - "BRAM_FIFO36_ALMOSTFULL", - "BRAM_FIFO36_CASCADEINA", - "BRAM_FIFO36_CASCADEINB", - "BRAM_FIFO36_CASCADEOUTA", - "BRAM_FIFO36_CASCADEOUTA_1", - "BRAM_FIFO36_CASCADEOUTB", - "BRAM_FIFO36_CASCADEOUTB_1", - "BRAM_FIFO36_CLKARDCLKL", - "BRAM_FIFO36_CLKARDCLKU", - "BRAM_FIFO36_CLKBWRCLKL", - "BRAM_FIFO36_CLKBWRCLKU", - "BRAM_FIFO36_DBITERR", - "BRAM_FIFO36_DIADIL0", - "BRAM_FIFO36_DIADIL1", - "BRAM_FIFO36_DIADIL10", - "BRAM_FIFO36_DIADIL11", - "BRAM_FIFO36_DIADIL12", - "BRAM_FIFO36_DIADIL13", - "BRAM_FIFO36_DIADIL14", - "BRAM_FIFO36_DIADIL15", - "BRAM_FIFO36_DIADIL2", - "BRAM_FIFO36_DIADIL3", - "BRAM_FIFO36_DIADIL4", - "BRAM_FIFO36_DIADIL5", - "BRAM_FIFO36_DIADIL6", - "BRAM_FIFO36_DIADIL7", - "BRAM_FIFO36_DIADIL8", - "BRAM_FIFO36_DIADIL9", - "BRAM_FIFO36_DIADIU0", - "BRAM_FIFO36_DIADIU1", - "BRAM_FIFO36_DIADIU10", - "BRAM_FIFO36_DIADIU11", - "BRAM_FIFO36_DIADIU12", - "BRAM_FIFO36_DIADIU13", - "BRAM_FIFO36_DIADIU14", - "BRAM_FIFO36_DIADIU15", - "BRAM_FIFO36_DIADIU2", - "BRAM_FIFO36_DIADIU3", - "BRAM_FIFO36_DIADIU4", - "BRAM_FIFO36_DIADIU5", - "BRAM_FIFO36_DIADIU6", - "BRAM_FIFO36_DIADIU7", - "BRAM_FIFO36_DIADIU8", - "BRAM_FIFO36_DIADIU9", - "BRAM_FIFO36_DIBDIL0", - "BRAM_FIFO36_DIBDIL1", - "BRAM_FIFO36_DIBDIL10", - "BRAM_FIFO36_DIBDIL11", - "BRAM_FIFO36_DIBDIL12", - "BRAM_FIFO36_DIBDIL13", - "BRAM_FIFO36_DIBDIL14", - "BRAM_FIFO36_DIBDIL15", - "BRAM_FIFO36_DIBDIL2", - "BRAM_FIFO36_DIBDIL3", - "BRAM_FIFO36_DIBDIL4", - "BRAM_FIFO36_DIBDIL5", - "BRAM_FIFO36_DIBDIL6", - "BRAM_FIFO36_DIBDIL7", - "BRAM_FIFO36_DIBDIL8", - "BRAM_FIFO36_DIBDIL9", - "BRAM_FIFO36_DIBDIU0", - "BRAM_FIFO36_DIBDIU1", - "BRAM_FIFO36_DIBDIU10", - "BRAM_FIFO36_DIBDIU11", - "BRAM_FIFO36_DIBDIU12", - "BRAM_FIFO36_DIBDIU13", - "BRAM_FIFO36_DIBDIU14", - "BRAM_FIFO36_DIBDIU15", - "BRAM_FIFO36_DIBDIU2", - "BRAM_FIFO36_DIBDIU3", - "BRAM_FIFO36_DIBDIU4", - "BRAM_FIFO36_DIBDIU5", - "BRAM_FIFO36_DIBDIU6", - "BRAM_FIFO36_DIBDIU7", - "BRAM_FIFO36_DIBDIU8", - "BRAM_FIFO36_DIBDIU9", - "BRAM_FIFO36_DIPADIPL0", - "BRAM_FIFO36_DIPADIPL1", - "BRAM_FIFO36_DIPADIPU0", - "BRAM_FIFO36_DIPADIPU1", - "BRAM_FIFO36_DIPBDIPL0", - "BRAM_FIFO36_DIPBDIPL1", - "BRAM_FIFO36_DIPBDIPU0", - "BRAM_FIFO36_DIPBDIPU1", - "BRAM_FIFO36_DOADOL0", - "BRAM_FIFO36_DOADOL1", - "BRAM_FIFO36_DOADOL10", - "BRAM_FIFO36_DOADOL11", - "BRAM_FIFO36_DOADOL12", - "BRAM_FIFO36_DOADOL13", - "BRAM_FIFO36_DOADOL14", - "BRAM_FIFO36_DOADOL15", - "BRAM_FIFO36_DOADOL2", - "BRAM_FIFO36_DOADOL3", - "BRAM_FIFO36_DOADOL4", - "BRAM_FIFO36_DOADOL5", - "BRAM_FIFO36_DOADOL6", - "BRAM_FIFO36_DOADOL7", - "BRAM_FIFO36_DOADOL8", - "BRAM_FIFO36_DOADOL9", - "BRAM_FIFO36_DOADOU0", - "BRAM_FIFO36_DOADOU1", - "BRAM_FIFO36_DOADOU10", - "BRAM_FIFO36_DOADOU11", - "BRAM_FIFO36_DOADOU12", - "BRAM_FIFO36_DOADOU13", - "BRAM_FIFO36_DOADOU14", - "BRAM_FIFO36_DOADOU15", - "BRAM_FIFO36_DOADOU2", - "BRAM_FIFO36_DOADOU3", - "BRAM_FIFO36_DOADOU4", - "BRAM_FIFO36_DOADOU5", - "BRAM_FIFO36_DOADOU6", - "BRAM_FIFO36_DOADOU7", - "BRAM_FIFO36_DOADOU8", - "BRAM_FIFO36_DOADOU9", - "BRAM_FIFO36_DOBDOL0", - "BRAM_FIFO36_DOBDOL1", - "BRAM_FIFO36_DOBDOL10", - "BRAM_FIFO36_DOBDOL11", - "BRAM_FIFO36_DOBDOL12", - "BRAM_FIFO36_DOBDOL13", - "BRAM_FIFO36_DOBDOL14", - "BRAM_FIFO36_DOBDOL15", - "BRAM_FIFO36_DOBDOL2", - "BRAM_FIFO36_DOBDOL3", - "BRAM_FIFO36_DOBDOL4", - "BRAM_FIFO36_DOBDOL5", - "BRAM_FIFO36_DOBDOL6", - "BRAM_FIFO36_DOBDOL7", - "BRAM_FIFO36_DOBDOL8", - "BRAM_FIFO36_DOBDOL9", - "BRAM_FIFO36_DOBDOU0", - "BRAM_FIFO36_DOBDOU1", - "BRAM_FIFO36_DOBDOU10", - "BRAM_FIFO36_DOBDOU11", - "BRAM_FIFO36_DOBDOU12", - "BRAM_FIFO36_DOBDOU13", - "BRAM_FIFO36_DOBDOU14", - "BRAM_FIFO36_DOBDOU15", - "BRAM_FIFO36_DOBDOU2", - "BRAM_FIFO36_DOBDOU3", - "BRAM_FIFO36_DOBDOU4", - "BRAM_FIFO36_DOBDOU5", - "BRAM_FIFO36_DOBDOU6", - "BRAM_FIFO36_DOBDOU7", - "BRAM_FIFO36_DOBDOU8", - "BRAM_FIFO36_DOBDOU9", - "BRAM_FIFO36_DOPADOPL0", - "BRAM_FIFO36_DOPADOPL1", - "BRAM_FIFO36_DOPADOPU0", - "BRAM_FIFO36_DOPADOPU1", - "BRAM_FIFO36_DOPBDOPL0", - "BRAM_FIFO36_DOPBDOPL1", - "BRAM_FIFO36_DOPBDOPU0", - "BRAM_FIFO36_DOPBDOPU1", - "BRAM_FIFO36_ECCPARITY0", - "BRAM_FIFO36_ECCPARITY1", - "BRAM_FIFO36_ECCPARITY2", - "BRAM_FIFO36_ECCPARITY3", - "BRAM_FIFO36_ECCPARITY4", - "BRAM_FIFO36_ECCPARITY5", - "BRAM_FIFO36_ECCPARITY6", - "BRAM_FIFO36_ECCPARITY7", - "BRAM_FIFO36_EMPTY", - "BRAM_FIFO36_ENARDENL", - "BRAM_FIFO36_ENARDENU", - "BRAM_FIFO36_ENBWRENL", - "BRAM_FIFO36_ENBWRENU", - "BRAM_FIFO36_FULL", - "BRAM_FIFO36_INJECTDBITERR", - "BRAM_FIFO36_INJECTSBITERR", - "BRAM_FIFO36_RDCOUNT0", - "BRAM_FIFO36_RDCOUNT1", - "BRAM_FIFO36_RDCOUNT10", - "BRAM_FIFO36_RDCOUNT11", - "BRAM_FIFO36_RDCOUNT12", - "BRAM_FIFO36_RDCOUNT2", - "BRAM_FIFO36_RDCOUNT3", - "BRAM_FIFO36_RDCOUNT4", - "BRAM_FIFO36_RDCOUNT5", - "BRAM_FIFO36_RDCOUNT6", - "BRAM_FIFO36_RDCOUNT7", - "BRAM_FIFO36_RDCOUNT8", - "BRAM_FIFO36_RDCOUNT9", - "BRAM_FIFO36_RDERR", - "BRAM_FIFO36_REGCEAREGCEL", - "BRAM_FIFO36_REGCEAREGCEU", - "BRAM_FIFO36_REGCEBL", - "BRAM_FIFO36_REGCEBU", - "BRAM_FIFO36_REGCLKARDRCLKL", - "BRAM_FIFO36_REGCLKARDRCLKU", - "BRAM_FIFO36_REGCLKBL", - "BRAM_FIFO36_REGCLKBU", - "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "BRAM_FIFO36_RSTRAMARSTRAMU", - "BRAM_FIFO36_RSTRAMBL", - "BRAM_FIFO36_RSTRAMBU", - "BRAM_FIFO36_RSTREGARSTREGL", - "BRAM_FIFO36_RSTREGARSTREGU", - "BRAM_FIFO36_RSTREGBL", - "BRAM_FIFO36_RSTREGBU", - "BRAM_FIFO36_SBITERR", - "BRAM_FIFO36_TSTBRAMRST", - "BRAM_FIFO36_TSTCNT0", - "BRAM_FIFO36_TSTCNT1", - "BRAM_FIFO36_TSTCNT10", - "BRAM_FIFO36_TSTCNT11", - "BRAM_FIFO36_TSTCNT12", - "BRAM_FIFO36_TSTCNT2", - "BRAM_FIFO36_TSTCNT3", - "BRAM_FIFO36_TSTCNT4", - "BRAM_FIFO36_TSTCNT5", - "BRAM_FIFO36_TSTCNT6", - "BRAM_FIFO36_TSTCNT7", - "BRAM_FIFO36_TSTCNT8", - "BRAM_FIFO36_TSTCNT9", - "BRAM_FIFO36_TSTFLAGIN", - "BRAM_FIFO36_TSTIN0", - "BRAM_FIFO36_TSTIN1", - "BRAM_FIFO36_TSTIN2", - "BRAM_FIFO36_TSTIN3", - "BRAM_FIFO36_TSTIN4", - "BRAM_FIFO36_TSTOFF", - "BRAM_FIFO36_TSTOUT0", - "BRAM_FIFO36_TSTOUT1", - "BRAM_FIFO36_TSTOUT2", - "BRAM_FIFO36_TSTOUT3", - "BRAM_FIFO36_TSTOUT4", - "BRAM_FIFO36_TSTRDCNTOFF", - "BRAM_FIFO36_TSTRDOS0", - "BRAM_FIFO36_TSTRDOS1", - "BRAM_FIFO36_TSTRDOS10", - "BRAM_FIFO36_TSTRDOS11", - "BRAM_FIFO36_TSTRDOS12", - "BRAM_FIFO36_TSTRDOS2", - "BRAM_FIFO36_TSTRDOS3", - "BRAM_FIFO36_TSTRDOS4", - "BRAM_FIFO36_TSTRDOS5", - "BRAM_FIFO36_TSTRDOS6", - "BRAM_FIFO36_TSTRDOS7", - "BRAM_FIFO36_TSTRDOS8", - "BRAM_FIFO36_TSTRDOS9", - "BRAM_FIFO36_TSTWRCNTOFF", - "BRAM_FIFO36_TSTWROS0", - "BRAM_FIFO36_TSTWROS1", - "BRAM_FIFO36_TSTWROS10", - "BRAM_FIFO36_TSTWROS11", - "BRAM_FIFO36_TSTWROS12", - "BRAM_FIFO36_TSTWROS2", - "BRAM_FIFO36_TSTWROS3", - "BRAM_FIFO36_TSTWROS4", - "BRAM_FIFO36_TSTWROS5", - "BRAM_FIFO36_TSTWROS6", - "BRAM_FIFO36_TSTWROS7", - "BRAM_FIFO36_TSTWROS8", - "BRAM_FIFO36_TSTWROS9", - "BRAM_FIFO36_WEAL0", - "BRAM_FIFO36_WEAL1", - "BRAM_FIFO36_WEAL2", - "BRAM_FIFO36_WEAL3", - "BRAM_FIFO36_WEAU0", - "BRAM_FIFO36_WEAU1", - "BRAM_FIFO36_WEAU2", - "BRAM_FIFO36_WEAU3", - "BRAM_FIFO36_WEBWEL0", - "BRAM_FIFO36_WEBWEL1", - "BRAM_FIFO36_WEBWEL2", - "BRAM_FIFO36_WEBWEL3", - "BRAM_FIFO36_WEBWEL4", - "BRAM_FIFO36_WEBWEL5", - "BRAM_FIFO36_WEBWEL6", - "BRAM_FIFO36_WEBWEL7", - "BRAM_FIFO36_WEBWEU0", - "BRAM_FIFO36_WEBWEU1", - "BRAM_FIFO36_WEBWEU2", - "BRAM_FIFO36_WEBWEU3", - "BRAM_FIFO36_WEBWEU4", - "BRAM_FIFO36_WEBWEU5", - "BRAM_FIFO36_WEBWEU6", - "BRAM_FIFO36_WEBWEU7", - "BRAM_FIFO36_WRCOUNT0", - "BRAM_FIFO36_WRCOUNT1", - "BRAM_FIFO36_WRCOUNT10", - "BRAM_FIFO36_WRCOUNT11", - "BRAM_FIFO36_WRCOUNT12", - "BRAM_FIFO36_WRCOUNT2", - "BRAM_FIFO36_WRCOUNT3", - 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"BRAM_IMUX_ADDRARDADDRL3", - "BRAM_IMUX_ADDRARDADDRL4", - "BRAM_IMUX_ADDRARDADDRL5", - "BRAM_IMUX_ADDRARDADDRL6", - "BRAM_IMUX_ADDRARDADDRL7", - "BRAM_IMUX_ADDRARDADDRL8", - "BRAM_IMUX_ADDRARDADDRL9", - "BRAM_IMUX_ADDRARDADDRU0", - "BRAM_IMUX_ADDRARDADDRU1", - "BRAM_IMUX_ADDRARDADDRU10", - "BRAM_IMUX_ADDRARDADDRU11", - "BRAM_IMUX_ADDRARDADDRU12", - "BRAM_IMUX_ADDRARDADDRU13", - "BRAM_IMUX_ADDRARDADDRU14", - "BRAM_IMUX_ADDRARDADDRU2", - "BRAM_IMUX_ADDRARDADDRU3", - "BRAM_IMUX_ADDRARDADDRU4", - "BRAM_IMUX_ADDRARDADDRU5", - "BRAM_IMUX_ADDRARDADDRU6", - "BRAM_IMUX_ADDRARDADDRU7", - "BRAM_IMUX_ADDRARDADDRU8", - "BRAM_IMUX_ADDRARDADDRU9", - "BRAM_IMUX_ADDRBWRADDRL0", - "BRAM_IMUX_ADDRBWRADDRL1", - "BRAM_IMUX_ADDRBWRADDRL10", - "BRAM_IMUX_ADDRBWRADDRL11", - "BRAM_IMUX_ADDRBWRADDRL12", - "BRAM_IMUX_ADDRBWRADDRL13", - "BRAM_IMUX_ADDRBWRADDRL14", - "BRAM_IMUX_ADDRBWRADDRL15", - "BRAM_IMUX_ADDRBWRADDRL2", - "BRAM_IMUX_ADDRBWRADDRL3", - "BRAM_IMUX_ADDRBWRADDRL4", - "BRAM_IMUX_ADDRBWRADDRL5", - "BRAM_IMUX_ADDRBWRADDRL6", - "BRAM_IMUX_ADDRBWRADDRL7", - "BRAM_IMUX_ADDRBWRADDRL8", - "BRAM_IMUX_ADDRBWRADDRL9", - "BRAM_IMUX_ADDRBWRADDRU0", - "BRAM_IMUX_ADDRBWRADDRU1", - "BRAM_IMUX_ADDRBWRADDRU10", - "BRAM_IMUX_ADDRBWRADDRU11", - "BRAM_IMUX_ADDRBWRADDRU12", - "BRAM_IMUX_ADDRBWRADDRU13", - "BRAM_IMUX_ADDRBWRADDRU14", - "BRAM_IMUX_ADDRBWRADDRU2", - "BRAM_IMUX_ADDRBWRADDRU3", - "BRAM_IMUX_ADDRBWRADDRU4", - "BRAM_IMUX_ADDRBWRADDRU5", - "BRAM_IMUX_ADDRBWRADDRU6", - "BRAM_IMUX_ADDRBWRADDRU7", - "BRAM_IMUX_ADDRBWRADDRU8", - "BRAM_IMUX_ADDRBWRADDRU9", - "BRAM_LH10_0", - "BRAM_LH10_1", - "BRAM_LH10_2", - "BRAM_LH10_3", - "BRAM_LH10_4", - "BRAM_LH11_0", - "BRAM_LH11_1", - "BRAM_LH11_2", - "BRAM_LH11_3", - "BRAM_LH11_4", - "BRAM_LH12_0", - "BRAM_LH12_1", - "BRAM_LH12_2", - "BRAM_LH12_3", - "BRAM_LH12_4", - "BRAM_LH1_0", - "BRAM_LH1_1", - "BRAM_LH1_2", - "BRAM_LH1_3", - "BRAM_LH1_4", - "BRAM_LH2_0", - "BRAM_LH2_1", - "BRAM_LH2_2", - "BRAM_LH2_3", - "BRAM_LH2_4", - "BRAM_LH3_0", - "BRAM_LH3_1", - "BRAM_LH3_2", - "BRAM_LH3_3", - "BRAM_LH3_4", - "BRAM_LH4_0", - "BRAM_LH4_1", - "BRAM_LH4_2", - "BRAM_LH4_3", - "BRAM_LH4_4", - "BRAM_LH5_0", - "BRAM_LH5_1", - "BRAM_LH5_2", - "BRAM_LH5_3", - "BRAM_LH5_4", - "BRAM_LH6_0", - "BRAM_LH6_1", - "BRAM_LH6_2", - "BRAM_LH6_3", - "BRAM_LH6_4", - "BRAM_LH7_0", - "BRAM_LH7_1", - "BRAM_LH7_2", - "BRAM_LH7_3", - "BRAM_LH7_4", - "BRAM_LH8_0", - "BRAM_LH8_1", - "BRAM_LH8_2", - "BRAM_LH8_3", - "BRAM_LH8_4", - "BRAM_LH9_0", - "BRAM_LH9_1", - "BRAM_LH9_2", - "BRAM_LH9_3", - "BRAM_LH9_4", - "BRAM_LOGIC_OUTS_B0_0", - "BRAM_LOGIC_OUTS_B0_1", - "BRAM_LOGIC_OUTS_B0_2", - "BRAM_LOGIC_OUTS_B0_3", - "BRAM_LOGIC_OUTS_B0_4", - "BRAM_LOGIC_OUTS_B10_0", - "BRAM_LOGIC_OUTS_B10_1", - "BRAM_LOGIC_OUTS_B10_2", - "BRAM_LOGIC_OUTS_B10_3", - "BRAM_LOGIC_OUTS_B10_4", - "BRAM_LOGIC_OUTS_B11_0", - "BRAM_LOGIC_OUTS_B11_1", - "BRAM_LOGIC_OUTS_B11_2", - "BRAM_LOGIC_OUTS_B11_3", - "BRAM_LOGIC_OUTS_B11_4", - "BRAM_LOGIC_OUTS_B12_0", - "BRAM_LOGIC_OUTS_B12_1", - "BRAM_LOGIC_OUTS_B12_2", - "BRAM_LOGIC_OUTS_B12_3", - "BRAM_LOGIC_OUTS_B12_4", - "BRAM_LOGIC_OUTS_B13_0", - "BRAM_LOGIC_OUTS_B13_1", - "BRAM_LOGIC_OUTS_B13_2", - "BRAM_LOGIC_OUTS_B13_3", - "BRAM_LOGIC_OUTS_B13_4", - "BRAM_LOGIC_OUTS_B14_0", - "BRAM_LOGIC_OUTS_B14_1", - "BRAM_LOGIC_OUTS_B14_2", - "BRAM_LOGIC_OUTS_B14_3", - "BRAM_LOGIC_OUTS_B14_4", - "BRAM_LOGIC_OUTS_B15_0", - "BRAM_LOGIC_OUTS_B15_1", - "BRAM_LOGIC_OUTS_B15_2", - "BRAM_LOGIC_OUTS_B15_3", - "BRAM_LOGIC_OUTS_B15_4", - "BRAM_LOGIC_OUTS_B16_0", - "BRAM_LOGIC_OUTS_B16_1", - "BRAM_LOGIC_OUTS_B16_2", - "BRAM_LOGIC_OUTS_B16_3", - "BRAM_LOGIC_OUTS_B16_4", - "BRAM_LOGIC_OUTS_B17_0", - "BRAM_LOGIC_OUTS_B17_1", - "BRAM_LOGIC_OUTS_B17_2", - "BRAM_LOGIC_OUTS_B17_3", - "BRAM_LOGIC_OUTS_B17_4", - "BRAM_LOGIC_OUTS_B18_0", - "BRAM_LOGIC_OUTS_B18_1", - "BRAM_LOGIC_OUTS_B18_2", - "BRAM_LOGIC_OUTS_B18_3", - "BRAM_LOGIC_OUTS_B18_4", - "BRAM_LOGIC_OUTS_B19_0", - "BRAM_LOGIC_OUTS_B19_1", - "BRAM_LOGIC_OUTS_B19_2", - "BRAM_LOGIC_OUTS_B19_3", - "BRAM_LOGIC_OUTS_B19_4", - "BRAM_LOGIC_OUTS_B1_0", - "BRAM_LOGIC_OUTS_B1_1", - "BRAM_LOGIC_OUTS_B1_2", - "BRAM_LOGIC_OUTS_B1_3", - "BRAM_LOGIC_OUTS_B1_4", - "BRAM_LOGIC_OUTS_B20_0", - "BRAM_LOGIC_OUTS_B20_1", - "BRAM_LOGIC_OUTS_B20_2", - "BRAM_LOGIC_OUTS_B20_3", - "BRAM_LOGIC_OUTS_B20_4", - "BRAM_LOGIC_OUTS_B21_0", - "BRAM_LOGIC_OUTS_B21_1", - "BRAM_LOGIC_OUTS_B21_2", - "BRAM_LOGIC_OUTS_B21_3", - "BRAM_LOGIC_OUTS_B21_4", - "BRAM_LOGIC_OUTS_B22_0", - "BRAM_LOGIC_OUTS_B22_1", - "BRAM_LOGIC_OUTS_B22_2", - "BRAM_LOGIC_OUTS_B22_3", - "BRAM_LOGIC_OUTS_B22_4", - "BRAM_LOGIC_OUTS_B23_0", - "BRAM_LOGIC_OUTS_B23_1", - "BRAM_LOGIC_OUTS_B23_2", - "BRAM_LOGIC_OUTS_B23_3", - "BRAM_LOGIC_OUTS_B23_4", - "BRAM_LOGIC_OUTS_B2_0", - "BRAM_LOGIC_OUTS_B2_1", - "BRAM_LOGIC_OUTS_B2_2", - "BRAM_LOGIC_OUTS_B2_3", - "BRAM_LOGIC_OUTS_B2_4", - "BRAM_LOGIC_OUTS_B3_0", - "BRAM_LOGIC_OUTS_B3_1", - "BRAM_LOGIC_OUTS_B3_2", - "BRAM_LOGIC_OUTS_B3_3", - "BRAM_LOGIC_OUTS_B3_4", - "BRAM_LOGIC_OUTS_B4_0", - "BRAM_LOGIC_OUTS_B4_1", - "BRAM_LOGIC_OUTS_B4_2", - "BRAM_LOGIC_OUTS_B4_3", - "BRAM_LOGIC_OUTS_B4_4", - "BRAM_LOGIC_OUTS_B5_0", - "BRAM_LOGIC_OUTS_B5_1", - "BRAM_LOGIC_OUTS_B5_2", - "BRAM_LOGIC_OUTS_B5_3", - "BRAM_LOGIC_OUTS_B5_4", - "BRAM_LOGIC_OUTS_B6_0", - "BRAM_LOGIC_OUTS_B6_1", - "BRAM_LOGIC_OUTS_B6_2", - "BRAM_LOGIC_OUTS_B6_3", - "BRAM_LOGIC_OUTS_B6_4", - "BRAM_LOGIC_OUTS_B7_0", - "BRAM_LOGIC_OUTS_B7_1", - "BRAM_LOGIC_OUTS_B7_2", - "BRAM_LOGIC_OUTS_B7_3", - "BRAM_LOGIC_OUTS_B7_4", - "BRAM_LOGIC_OUTS_B8_0", - "BRAM_LOGIC_OUTS_B8_1", - "BRAM_LOGIC_OUTS_B8_2", - "BRAM_LOGIC_OUTS_B8_3", - "BRAM_LOGIC_OUTS_B8_4", - "BRAM_LOGIC_OUTS_B9_0", - "BRAM_LOGIC_OUTS_B9_1", - "BRAM_LOGIC_OUTS_B9_2", - "BRAM_LOGIC_OUTS_B9_3", - "BRAM_LOGIC_OUTS_B9_4", - "BRAM_MONITOR_N_0", - "BRAM_MONITOR_N_1", - "BRAM_MONITOR_N_2", - "BRAM_MONITOR_N_3", - "BRAM_MONITOR_N_4", - "BRAM_MONITOR_P_0", - "BRAM_MONITOR_P_1", - "BRAM_MONITOR_P_2", - "BRAM_MONITOR_P_3", - "BRAM_MONITOR_P_4", - "BRAM_NE2A0_0", - "BRAM_NE2A0_1", - "BRAM_NE2A0_2", - "BRAM_NE2A0_3", - "BRAM_NE2A0_4", - "BRAM_NE2A1_0", - "BRAM_NE2A1_1", - "BRAM_NE2A1_2", - "BRAM_NE2A1_3", - "BRAM_NE2A1_4", - "BRAM_NE2A2_0", - "BRAM_NE2A2_1", - "BRAM_NE2A2_2", - "BRAM_NE2A2_3", - "BRAM_NE2A2_4", - "BRAM_NE2A3_0", - "BRAM_NE2A3_1", - "BRAM_NE2A3_2", - "BRAM_NE2A3_3", - "BRAM_NE2A3_4", - "BRAM_NE4BEG0_0", - "BRAM_NE4BEG0_1", - "BRAM_NE4BEG0_2", - "BRAM_NE4BEG0_3", - "BRAM_NE4BEG0_4", - "BRAM_NE4BEG1_0", - "BRAM_NE4BEG1_1", - "BRAM_NE4BEG1_2", - "BRAM_NE4BEG1_3", - "BRAM_NE4BEG1_4", - "BRAM_NE4BEG2_0", - "BRAM_NE4BEG2_1", - "BRAM_NE4BEG2_2", - "BRAM_NE4BEG2_3", - "BRAM_NE4BEG2_4", - "BRAM_NE4BEG3_0", - "BRAM_NE4BEG3_1", - "BRAM_NE4BEG3_2", - "BRAM_NE4BEG3_3", - "BRAM_NE4BEG3_4", - "BRAM_NE4C0_0", - "BRAM_NE4C0_1", - "BRAM_NE4C0_2", - "BRAM_NE4C0_3", - "BRAM_NE4C0_4", - "BRAM_NE4C1_0", - "BRAM_NE4C1_1", - "BRAM_NE4C1_2", - "BRAM_NE4C1_3", - "BRAM_NE4C1_4", - "BRAM_NE4C2_0", - "BRAM_NE4C2_1", - "BRAM_NE4C2_2", - "BRAM_NE4C2_3", - "BRAM_NE4C2_4", - "BRAM_NE4C3_0", - "BRAM_NE4C3_1", - "BRAM_NE4C3_2", - "BRAM_NE4C3_3", - "BRAM_NE4C3_4", - "BRAM_NW2A0_0", - "BRAM_NW2A0_1", - "BRAM_NW2A0_2", - "BRAM_NW2A0_3", - "BRAM_NW2A0_4", - "BRAM_NW2A1_0", - "BRAM_NW2A1_1", - "BRAM_NW2A1_2", - "BRAM_NW2A1_3", - "BRAM_NW2A1_4", - "BRAM_NW2A2_0", - "BRAM_NW2A2_1", - "BRAM_NW2A2_2", - "BRAM_NW2A2_3", - "BRAM_NW2A2_4", - "BRAM_NW2A3_0", - "BRAM_NW2A3_1", - "BRAM_NW2A3_2", - "BRAM_NW2A3_3", - "BRAM_NW2A3_4", - "BRAM_NW4A0_0", - "BRAM_NW4A0_1", - "BRAM_NW4A0_2", - "BRAM_NW4A0_3", - "BRAM_NW4A0_4", - "BRAM_NW4A1_0", - "BRAM_NW4A1_1", - "BRAM_NW4A1_2", - "BRAM_NW4A1_3", - "BRAM_NW4A1_4", - "BRAM_NW4A2_0", - "BRAM_NW4A2_1", - "BRAM_NW4A2_2", - "BRAM_NW4A2_3", - "BRAM_NW4A2_4", - "BRAM_NW4A3_0", - "BRAM_NW4A3_1", - "BRAM_NW4A3_2", - "BRAM_NW4A3_3", - "BRAM_NW4A3_4", - "BRAM_NW4END0_0", - "BRAM_NW4END0_1", - "BRAM_NW4END0_2", - "BRAM_NW4END0_3", - "BRAM_NW4END0_4", - "BRAM_NW4END1_0", - "BRAM_NW4END1_1", - "BRAM_NW4END1_2", - "BRAM_NW4END1_3", - "BRAM_NW4END1_4", - "BRAM_NW4END2_0", - "BRAM_NW4END2_1", - "BRAM_NW4END2_2", - "BRAM_NW4END2_3", - "BRAM_NW4END2_4", - "BRAM_NW4END3_0", - "BRAM_NW4END3_1", - "BRAM_NW4END3_2", - "BRAM_NW4END3_3", - "BRAM_NW4END3_4", - "BRAM_PMVBRAM_O", - "BRAM_PMVBRAM_ODIV2", - "BRAM_PMVBRAM_ODIV2_1", - "BRAM_PMVBRAM_ODIV4", - "BRAM_PMVBRAM_O_1", - "BRAM_PMVBRAM_O_2", - "BRAM_PMVBRAM_SELECT1", - "BRAM_PMVBRAM_SELECT2", - "BRAM_PMVBRAM_SELECT3", - "BRAM_PMVBRAM_SELECT4", - "BRAM_RAMB18_ADDRARDADDR0", - "BRAM_RAMB18_ADDRARDADDR1", - "BRAM_RAMB18_ADDRARDADDR10", - "BRAM_RAMB18_ADDRARDADDR11", - "BRAM_RAMB18_ADDRARDADDR12", - "BRAM_RAMB18_ADDRARDADDR13", - "BRAM_RAMB18_ADDRARDADDR2", - "BRAM_RAMB18_ADDRARDADDR3", - "BRAM_RAMB18_ADDRARDADDR4", - "BRAM_RAMB18_ADDRARDADDR5", - "BRAM_RAMB18_ADDRARDADDR6", - "BRAM_RAMB18_ADDRARDADDR7", - "BRAM_RAMB18_ADDRARDADDR8", - "BRAM_RAMB18_ADDRARDADDR9", - "BRAM_RAMB18_ADDRATIEHIGH0", - "BRAM_RAMB18_ADDRATIEHIGH1", - "BRAM_RAMB18_ADDRBTIEHIGH0", - "BRAM_RAMB18_ADDRBTIEHIGH1", - "BRAM_RAMB18_ADDRBWRADDR0", - "BRAM_RAMB18_ADDRBWRADDR1", - "BRAM_RAMB18_ADDRBWRADDR10", - "BRAM_RAMB18_ADDRBWRADDR11", - "BRAM_RAMB18_ADDRBWRADDR12", - "BRAM_RAMB18_ADDRBWRADDR13", - "BRAM_RAMB18_ADDRBWRADDR2", - "BRAM_RAMB18_ADDRBWRADDR3", - "BRAM_RAMB18_ADDRBWRADDR4", - "BRAM_RAMB18_ADDRBWRADDR5", - "BRAM_RAMB18_ADDRBWRADDR6", - "BRAM_RAMB18_ADDRBWRADDR7", - "BRAM_RAMB18_ADDRBWRADDR8", - "BRAM_RAMB18_ADDRBWRADDR9", - "BRAM_RAMB18_ALMOSTEMPTY", - "BRAM_RAMB18_ALMOSTFULL", - "BRAM_RAMB18_CLKARDCLK", - "BRAM_RAMB18_CLKBWRCLK", - "BRAM_RAMB18_DIADI0", - "BRAM_RAMB18_DIADI1", - "BRAM_RAMB18_DIADI10", - "BRAM_RAMB18_DIADI11", - "BRAM_RAMB18_DIADI12", - "BRAM_RAMB18_DIADI13", - "BRAM_RAMB18_DIADI14", - "BRAM_RAMB18_DIADI15", - "BRAM_RAMB18_DIADI2", - "BRAM_RAMB18_DIADI3", - "BRAM_RAMB18_DIADI4", - "BRAM_RAMB18_DIADI5", - "BRAM_RAMB18_DIADI6", - "BRAM_RAMB18_DIADI7", - "BRAM_RAMB18_DIADI8", - "BRAM_RAMB18_DIADI9", - "BRAM_RAMB18_DIBDI0", - "BRAM_RAMB18_DIBDI1", - "BRAM_RAMB18_DIBDI10", - "BRAM_RAMB18_DIBDI11", - "BRAM_RAMB18_DIBDI12", - "BRAM_RAMB18_DIBDI13", - "BRAM_RAMB18_DIBDI14", - "BRAM_RAMB18_DIBDI15", - "BRAM_RAMB18_DIBDI2", - "BRAM_RAMB18_DIBDI3", - "BRAM_RAMB18_DIBDI4", - "BRAM_RAMB18_DIBDI5", - "BRAM_RAMB18_DIBDI6", - "BRAM_RAMB18_DIBDI7", - "BRAM_RAMB18_DIBDI8", - "BRAM_RAMB18_DIBDI9", - "BRAM_RAMB18_DIPADIP0", - "BRAM_RAMB18_DIPADIP1", - "BRAM_RAMB18_DIPBDIP0", - "BRAM_RAMB18_DIPBDIP1", - "BRAM_RAMB18_DOADO0", - "BRAM_RAMB18_DOADO1", - "BRAM_RAMB18_DOADO10", - "BRAM_RAMB18_DOADO11", - "BRAM_RAMB18_DOADO12", - "BRAM_RAMB18_DOADO13", - "BRAM_RAMB18_DOADO14", - "BRAM_RAMB18_DOADO15", - "BRAM_RAMB18_DOADO2", - "BRAM_RAMB18_DOADO3", - "BRAM_RAMB18_DOADO4", - "BRAM_RAMB18_DOADO5", - "BRAM_RAMB18_DOADO6", - "BRAM_RAMB18_DOADO7", - "BRAM_RAMB18_DOADO8", - "BRAM_RAMB18_DOADO9", - "BRAM_RAMB18_DOBDO0", - "BRAM_RAMB18_DOBDO1", - "BRAM_RAMB18_DOBDO10", - "BRAM_RAMB18_DOBDO11", - "BRAM_RAMB18_DOBDO12", - "BRAM_RAMB18_DOBDO13", - "BRAM_RAMB18_DOBDO14", - "BRAM_RAMB18_DOBDO15", - "BRAM_RAMB18_DOBDO2", - "BRAM_RAMB18_DOBDO3", - "BRAM_RAMB18_DOBDO4", - "BRAM_RAMB18_DOBDO5", - "BRAM_RAMB18_DOBDO6", - "BRAM_RAMB18_DOBDO7", - "BRAM_RAMB18_DOBDO8", - "BRAM_RAMB18_DOBDO9", - "BRAM_RAMB18_DOPADOP0", - "BRAM_RAMB18_DOPADOP1", - "BRAM_RAMB18_DOPBDOP0", - "BRAM_RAMB18_DOPBDOP1", - "BRAM_RAMB18_EMPTY", - "BRAM_RAMB18_ENARDEN", - "BRAM_RAMB18_ENBWREN", - "BRAM_RAMB18_FULL", - "BRAM_RAMB18_RDCOUNT0", - "BRAM_RAMB18_RDCOUNT1", - "BRAM_RAMB18_RDCOUNT10", - "BRAM_RAMB18_RDCOUNT11", - "BRAM_RAMB18_RDCOUNT2", - "BRAM_RAMB18_RDCOUNT3", - "BRAM_RAMB18_RDCOUNT4", - "BRAM_RAMB18_RDCOUNT5", - "BRAM_RAMB18_RDCOUNT6", - "BRAM_RAMB18_RDCOUNT7", - "BRAM_RAMB18_RDCOUNT8", - "BRAM_RAMB18_RDCOUNT9", - "BRAM_RAMB18_RDERR", - "BRAM_RAMB18_REGCEAREGCE", - "BRAM_RAMB18_REGCEB", - "BRAM_RAMB18_REGCLKARDRCLK", - "BRAM_RAMB18_REGCLKB", - "BRAM_RAMB18_RSTRAMARSTRAM", - "BRAM_RAMB18_RSTRAMB", - "BRAM_RAMB18_RSTREGARSTREG", - "BRAM_RAMB18_RSTREGB", - "BRAM_RAMB18_WEA0", - "BRAM_RAMB18_WEA1", - "BRAM_RAMB18_WEA2", - "BRAM_RAMB18_WEA3", - "BRAM_RAMB18_WEBWE0", - "BRAM_RAMB18_WEBWE1", - "BRAM_RAMB18_WEBWE2", - "BRAM_RAMB18_WEBWE3", - "BRAM_RAMB18_WEBWE4", - "BRAM_RAMB18_WEBWE5", - "BRAM_RAMB18_WEBWE6", - "BRAM_RAMB18_WEBWE7", - "BRAM_RAMB18_WRCOUNT0", - "BRAM_RAMB18_WRCOUNT1", - "BRAM_RAMB18_WRCOUNT10", - "BRAM_RAMB18_WRCOUNT11", - "BRAM_RAMB18_WRCOUNT2", - "BRAM_RAMB18_WRCOUNT3", - "BRAM_RAMB18_WRCOUNT4", - "BRAM_RAMB18_WRCOUNT5", - "BRAM_RAMB18_WRCOUNT6", - "BRAM_RAMB18_WRCOUNT7", - "BRAM_RAMB18_WRCOUNT8", - "BRAM_RAMB18_WRCOUNT9", - "BRAM_RAMB18_WRERR", - "BRAM_SE2A0_0", - "BRAM_SE2A0_1", - "BRAM_SE2A0_2", - "BRAM_SE2A0_3", - "BRAM_SE2A0_4", - "BRAM_SE2A1_0", - "BRAM_SE2A1_1", - "BRAM_SE2A1_2", - "BRAM_SE2A1_3", - "BRAM_SE2A1_4", - "BRAM_SE2A2_0", - "BRAM_SE2A2_1", - "BRAM_SE2A2_2", - "BRAM_SE2A2_3", - "BRAM_SE2A2_4", - "BRAM_SE2A3_0", - "BRAM_SE2A3_1", - "BRAM_SE2A3_2", - "BRAM_SE2A3_3", - "BRAM_SE2A3_4", - "BRAM_SE4BEG0_0", - "BRAM_SE4BEG0_1", - "BRAM_SE4BEG0_2", - "BRAM_SE4BEG0_3", - "BRAM_SE4BEG0_4", - "BRAM_SE4BEG1_0", - "BRAM_SE4BEG1_1", - "BRAM_SE4BEG1_2", - "BRAM_SE4BEG1_3", - "BRAM_SE4BEG1_4", - "BRAM_SE4BEG2_0", - "BRAM_SE4BEG2_1", - "BRAM_SE4BEG2_2", - "BRAM_SE4BEG2_3", - "BRAM_SE4BEG2_4", - "BRAM_SE4BEG3_0", - "BRAM_SE4BEG3_1", - "BRAM_SE4BEG3_2", - "BRAM_SE4BEG3_3", - "BRAM_SE4BEG3_4", - "BRAM_SE4C0_0", - "BRAM_SE4C0_1", - "BRAM_SE4C0_2", - "BRAM_SE4C0_3", - "BRAM_SE4C0_4", - "BRAM_SE4C1_0", - "BRAM_SE4C1_1", - "BRAM_SE4C1_2", - "BRAM_SE4C1_3", - "BRAM_SE4C1_4", - "BRAM_SE4C2_0", - "BRAM_SE4C2_1", - "BRAM_SE4C2_2", - "BRAM_SE4C2_3", - "BRAM_SE4C2_4", - "BRAM_SE4C3_0", - "BRAM_SE4C3_1", - "BRAM_SE4C3_2", - "BRAM_SE4C3_3", - "BRAM_SE4C3_4", - "BRAM_SW2A0_0", - "BRAM_SW2A0_1", - "BRAM_SW2A0_2", - "BRAM_SW2A0_3", - "BRAM_SW2A0_4", - "BRAM_SW2A1_0", - "BRAM_SW2A1_1", - "BRAM_SW2A1_2", - "BRAM_SW2A1_3", - "BRAM_SW2A1_4", - "BRAM_SW2A2_0", - "BRAM_SW2A2_1", - "BRAM_SW2A2_2", - "BRAM_SW2A2_3", - "BRAM_SW2A2_4", - "BRAM_SW2A3_0", - "BRAM_SW2A3_1", - "BRAM_SW2A3_2", - "BRAM_SW2A3_3", - "BRAM_SW2A3_4", - "BRAM_SW4A0_0", - "BRAM_SW4A0_1", - "BRAM_SW4A0_2", - "BRAM_SW4A0_3", - "BRAM_SW4A0_4", - "BRAM_SW4A1_0", - "BRAM_SW4A1_1", - "BRAM_SW4A1_2", - "BRAM_SW4A1_3", - "BRAM_SW4A1_4", - "BRAM_SW4A2_0", - "BRAM_SW4A2_1", - "BRAM_SW4A2_2", - "BRAM_SW4A2_3", - "BRAM_SW4A2_4", - "BRAM_SW4A3_0", - "BRAM_SW4A3_1", - "BRAM_SW4A3_2", - "BRAM_SW4A3_3", - "BRAM_SW4A3_4", - "BRAM_SW4END0_0", - "BRAM_SW4END0_1", - "BRAM_SW4END0_2", - "BRAM_SW4END0_3", - "BRAM_SW4END0_4", - "BRAM_SW4END1_0", - "BRAM_SW4END1_1", - "BRAM_SW4END1_2", - "BRAM_SW4END1_3", - "BRAM_SW4END1_4", - "BRAM_SW4END2_0", - "BRAM_SW4END2_1", - "BRAM_SW4END2_2", - "BRAM_SW4END2_3", - "BRAM_SW4END2_4", - "BRAM_SW4END3_0", - "BRAM_SW4END3_1", - "BRAM_SW4END3_2", - "BRAM_SW4END3_3", - "BRAM_SW4END3_4", - "BRAM_UTURN_ADDRARDADDRL0", - "BRAM_UTURN_ADDRARDADDRL1", - "BRAM_UTURN_ADDRARDADDRL10", - "BRAM_UTURN_ADDRARDADDRL11", - "BRAM_UTURN_ADDRARDADDRL12", - "BRAM_UTURN_ADDRARDADDRL13", - "BRAM_UTURN_ADDRARDADDRL14", - "BRAM_UTURN_ADDRARDADDRL15", - "BRAM_UTURN_ADDRARDADDRL2", - "BRAM_UTURN_ADDRARDADDRL3", - "BRAM_UTURN_ADDRARDADDRL4", - "BRAM_UTURN_ADDRARDADDRL5", - "BRAM_UTURN_ADDRARDADDRL6", - "BRAM_UTURN_ADDRARDADDRL7", - "BRAM_UTURN_ADDRARDADDRL8", - "BRAM_UTURN_ADDRARDADDRL9", - "BRAM_UTURN_ADDRARDADDRU0", - "BRAM_UTURN_ADDRARDADDRU1", - "BRAM_UTURN_ADDRARDADDRU10", - "BRAM_UTURN_ADDRARDADDRU11", - "BRAM_UTURN_ADDRARDADDRU12", - "BRAM_UTURN_ADDRARDADDRU13", - "BRAM_UTURN_ADDRARDADDRU14", - "BRAM_UTURN_ADDRARDADDRU2", - "BRAM_UTURN_ADDRARDADDRU3", - "BRAM_UTURN_ADDRARDADDRU4", - "BRAM_UTURN_ADDRARDADDRU5", - "BRAM_UTURN_ADDRARDADDRU6", - "BRAM_UTURN_ADDRARDADDRU7", - "BRAM_UTURN_ADDRARDADDRU8", - "BRAM_UTURN_ADDRARDADDRU9", - "BRAM_UTURN_ADDRBWRADDRL0", - "BRAM_UTURN_ADDRBWRADDRL1", - "BRAM_UTURN_ADDRBWRADDRL10", - "BRAM_UTURN_ADDRBWRADDRL11", - "BRAM_UTURN_ADDRBWRADDRL12", - "BRAM_UTURN_ADDRBWRADDRL13", - "BRAM_UTURN_ADDRBWRADDRL14", - "BRAM_UTURN_ADDRBWRADDRL15", - "BRAM_UTURN_ADDRBWRADDRL2", - "BRAM_UTURN_ADDRBWRADDRL3", - "BRAM_UTURN_ADDRBWRADDRL4", - "BRAM_UTURN_ADDRBWRADDRL5", - "BRAM_UTURN_ADDRBWRADDRL6", - "BRAM_UTURN_ADDRBWRADDRL7", - "BRAM_UTURN_ADDRBWRADDRL8", - "BRAM_UTURN_ADDRBWRADDRL9", - "BRAM_UTURN_ADDRBWRADDRU0", - "BRAM_UTURN_ADDRBWRADDRU1", - "BRAM_UTURN_ADDRBWRADDRU10", - "BRAM_UTURN_ADDRBWRADDRU11", - "BRAM_UTURN_ADDRBWRADDRU12", - "BRAM_UTURN_ADDRBWRADDRU13", - "BRAM_UTURN_ADDRBWRADDRU14", - "BRAM_UTURN_ADDRBWRADDRU2", - "BRAM_UTURN_ADDRBWRADDRU3", - "BRAM_UTURN_ADDRBWRADDRU4", - "BRAM_UTURN_ADDRBWRADDRU5", - "BRAM_UTURN_ADDRBWRADDRU6", - "BRAM_UTURN_ADDRBWRADDRU7", - "BRAM_UTURN_ADDRBWRADDRU8", - "BRAM_UTURN_ADDRBWRADDRU9", - "BRAM_WL1END0_0", - "BRAM_WL1END0_1", - "BRAM_WL1END0_2", - "BRAM_WL1END0_3", - "BRAM_WL1END0_4", - "BRAM_WL1END1_0", - "BRAM_WL1END1_1", - "BRAM_WL1END1_2", - "BRAM_WL1END1_3", - "BRAM_WL1END1_4", - "BRAM_WL1END2_0", - "BRAM_WL1END2_1", - "BRAM_WL1END2_2", - "BRAM_WL1END2_3", - "BRAM_WL1END2_4", - "BRAM_WL1END3_0", - "BRAM_WL1END3_1", - "BRAM_WL1END3_2", - "BRAM_WL1END3_3", - "BRAM_WL1END3_4", - "BRAM_WR1END0_0", - "BRAM_WR1END0_1", - "BRAM_WR1END0_2", - "BRAM_WR1END0_3", - "BRAM_WR1END0_4", - "BRAM_WR1END1_0", - "BRAM_WR1END1_1", - "BRAM_WR1END1_2", - "BRAM_WR1END1_3", - "BRAM_WR1END1_4", - "BRAM_WR1END2_0", - "BRAM_WR1END2_1", - "BRAM_WR1END2_2", - "BRAM_WR1END2_3", - "BRAM_WR1END2_4", - "BRAM_WR1END3_0", - "BRAM_WR1END3_1", - "BRAM_WR1END3_2", - "BRAM_WR1END3_3", - "BRAM_WR1END3_4", - "BRAM_WW2A0_0", - "BRAM_WW2A0_1", - "BRAM_WW2A0_2", - "BRAM_WW2A0_3", - "BRAM_WW2A0_4", - "BRAM_WW2A1_0", - "BRAM_WW2A1_1", - "BRAM_WW2A1_2", - "BRAM_WW2A1_3", - "BRAM_WW2A1_4", - "BRAM_WW2A2_0", - "BRAM_WW2A2_1", - "BRAM_WW2A2_2", - "BRAM_WW2A2_3", - "BRAM_WW2A2_4", - "BRAM_WW2A3_0", - "BRAM_WW2A3_1", - "BRAM_WW2A3_2", - "BRAM_WW2A3_3", - "BRAM_WW2A3_4", - "BRAM_WW2END0_0", - "BRAM_WW2END0_1", - "BRAM_WW2END0_2", - "BRAM_WW2END0_3", - "BRAM_WW2END0_4", - "BRAM_WW2END1_0", - "BRAM_WW2END1_1", - "BRAM_WW2END1_2", - "BRAM_WW2END1_3", - "BRAM_WW2END1_4", - "BRAM_WW2END2_0", - "BRAM_WW2END2_1", - "BRAM_WW2END2_2", - "BRAM_WW2END2_3", - "BRAM_WW2END2_4", - "BRAM_WW2END3_0", - "BRAM_WW2END3_1", - "BRAM_WW2END3_2", - "BRAM_WW2END3_3", - "BRAM_WW2END3_4", - "BRAM_WW4A0_0", - "BRAM_WW4A0_1", - "BRAM_WW4A0_2", - "BRAM_WW4A0_3", - "BRAM_WW4A0_4", - "BRAM_WW4A1_0", - "BRAM_WW4A1_1", - "BRAM_WW4A1_2", - "BRAM_WW4A1_3", - "BRAM_WW4A1_4", - "BRAM_WW4A2_0", - "BRAM_WW4A2_1", - "BRAM_WW4A2_2", - "BRAM_WW4A2_3", - "BRAM_WW4A2_4", - "BRAM_WW4A3_0", - "BRAM_WW4A3_1", - "BRAM_WW4A3_2", - "BRAM_WW4A3_3", - "BRAM_WW4A3_4", - "BRAM_WW4B0_0", - "BRAM_WW4B0_1", - "BRAM_WW4B0_2", - "BRAM_WW4B0_3", - "BRAM_WW4B0_4", - "BRAM_WW4B1_0", - "BRAM_WW4B1_1", - "BRAM_WW4B1_2", - "BRAM_WW4B1_3", - "BRAM_WW4B1_4", - "BRAM_WW4B2_0", - "BRAM_WW4B2_1", - "BRAM_WW4B2_2", - "BRAM_WW4B2_3", - "BRAM_WW4B2_4", - "BRAM_WW4B3_0", - "BRAM_WW4B3_1", - "BRAM_WW4B3_2", - "BRAM_WW4B3_3", - "BRAM_WW4B3_4", - "BRAM_WW4C0_0", - "BRAM_WW4C0_1", - "BRAM_WW4C0_2", - "BRAM_WW4C0_3", - "BRAM_WW4C0_4", - "BRAM_WW4C1_0", - "BRAM_WW4C1_1", - "BRAM_WW4C1_2", - "BRAM_WW4C1_3", - "BRAM_WW4C1_4", - "BRAM_WW4C2_0", - "BRAM_WW4C2_1", - "BRAM_WW4C2_2", - "BRAM_WW4C2_3", - "BRAM_WW4C2_4", - "BRAM_WW4C3_0", - "BRAM_WW4C3_1", - "BRAM_WW4C3_2", - "BRAM_WW4C3_3", - "BRAM_WW4C3_4", - "BRAM_WW4END0_0", - "BRAM_WW4END0_1", - "BRAM_WW4END0_2", - "BRAM_WW4END0_3", - "BRAM_WW4END0_4", - "BRAM_WW4END1_0", - "BRAM_WW4END1_1", - "BRAM_WW4END1_2", - "BRAM_WW4END1_3", - "BRAM_WW4END1_4", - "BRAM_WW4END2_0", - "BRAM_WW4END2_1", - "BRAM_WW4END2_2", - "BRAM_WW4END2_3", - "BRAM_WW4END2_4", - "BRAM_WW4END3_0", - "BRAM_WW4END3_1", - "BRAM_WW4END3_2", - "BRAM_WW4END3_3", - "BRAM_WW4END3_4" - ] + "wires": { + "BRAM_ADDRARDADDRL0": null, + "BRAM_ADDRARDADDRL1": null, + "BRAM_ADDRARDADDRL10": null, + "BRAM_ADDRARDADDRL11": null, + "BRAM_ADDRARDADDRL12": null, + "BRAM_ADDRARDADDRL13": null, + "BRAM_ADDRARDADDRL14": null, + "BRAM_ADDRARDADDRL2": null, + "BRAM_ADDRARDADDRL3": null, + "BRAM_ADDRARDADDRL4": null, + "BRAM_ADDRARDADDRL5": null, + "BRAM_ADDRARDADDRL6": null, + "BRAM_ADDRARDADDRL7": null, + "BRAM_ADDRARDADDRL8": null, + "BRAM_ADDRARDADDRL9": null, + "BRAM_ADDRARDADDRU0": null, + "BRAM_ADDRARDADDRU1": null, + "BRAM_ADDRARDADDRU10": null, + "BRAM_ADDRARDADDRU11": null, + "BRAM_ADDRARDADDRU12": null, + "BRAM_ADDRARDADDRU13": null, + "BRAM_ADDRARDADDRU14": null, + "BRAM_ADDRARDADDRU2": null, + "BRAM_ADDRARDADDRU3": null, + "BRAM_ADDRARDADDRU4": null, + "BRAM_ADDRARDADDRU5": null, + "BRAM_ADDRARDADDRU6": null, + "BRAM_ADDRARDADDRU7": null, + "BRAM_ADDRARDADDRU8": null, + "BRAM_ADDRARDADDRU9": null, + "BRAM_ADDRBWRADDRL0": null, + "BRAM_ADDRBWRADDRL1": null, + "BRAM_ADDRBWRADDRL10": null, + "BRAM_ADDRBWRADDRL11": null, + "BRAM_ADDRBWRADDRL12": null, + "BRAM_ADDRBWRADDRL13": null, + "BRAM_ADDRBWRADDRL14": null, + "BRAM_ADDRBWRADDRL2": null, + "BRAM_ADDRBWRADDRL3": null, + "BRAM_ADDRBWRADDRL4": null, + "BRAM_ADDRBWRADDRL5": null, + "BRAM_ADDRBWRADDRL6": null, + "BRAM_ADDRBWRADDRL7": null, + "BRAM_ADDRBWRADDRL8": null, + "BRAM_ADDRBWRADDRL9": null, + "BRAM_ADDRBWRADDRU0": null, + "BRAM_ADDRBWRADDRU1": null, + "BRAM_ADDRBWRADDRU10": null, + "BRAM_ADDRBWRADDRU11": null, + "BRAM_ADDRBWRADDRU12": null, + "BRAM_ADDRBWRADDRU13": null, + "BRAM_ADDRBWRADDRU14": null, + "BRAM_ADDRBWRADDRU2": null, + "BRAM_ADDRBWRADDRU3": null, + "BRAM_ADDRBWRADDRU4": null, + "BRAM_ADDRBWRADDRU5": null, + "BRAM_ADDRBWRADDRU6": null, + "BRAM_ADDRBWRADDRU7": null, + "BRAM_ADDRBWRADDRU8": null, + "BRAM_ADDRBWRADDRU9": null, + "BRAM_BLOCK_OUTS_L_B0_0": null, + "BRAM_BLOCK_OUTS_L_B0_1": null, + "BRAM_BLOCK_OUTS_L_B0_2": null, + "BRAM_BLOCK_OUTS_L_B0_3": null, + "BRAM_BLOCK_OUTS_L_B0_4": null, + "BRAM_BLOCK_OUTS_L_B1_0": null, + "BRAM_BLOCK_OUTS_L_B1_1": null, + "BRAM_BLOCK_OUTS_L_B1_2": null, + "BRAM_BLOCK_OUTS_L_B1_3": null, + "BRAM_BLOCK_OUTS_L_B1_4": null, + "BRAM_BLOCK_OUTS_L_B2_0": null, + "BRAM_BLOCK_OUTS_L_B2_1": null, + "BRAM_BLOCK_OUTS_L_B2_2": null, + "BRAM_BLOCK_OUTS_L_B2_3": null, + "BRAM_BLOCK_OUTS_L_B2_4": null, + "BRAM_BLOCK_OUTS_L_B3_0": null, + "BRAM_BLOCK_OUTS_L_B3_1": null, + "BRAM_BLOCK_OUTS_L_B3_2": null, + "BRAM_BLOCK_OUTS_L_B3_3": null, + "BRAM_BLOCK_OUTS_L_B3_4": null, + "BRAM_BYP0_0": null, + "BRAM_BYP0_1": null, + "BRAM_BYP0_2": null, + "BRAM_BYP0_3": null, + "BRAM_BYP0_4": null, + "BRAM_BYP1_0": null, + "BRAM_BYP1_1": null, + "BRAM_BYP1_2": null, + "BRAM_BYP1_3": null, + "BRAM_BYP1_4": null, + "BRAM_BYP2_0": null, + "BRAM_BYP2_1": null, + "BRAM_BYP2_2": null, + "BRAM_BYP2_3": null, + "BRAM_BYP2_4": null, + "BRAM_BYP3_0": null, + "BRAM_BYP3_1": null, + "BRAM_BYP3_2": null, + "BRAM_BYP3_3": null, + "BRAM_BYP3_4": null, + "BRAM_BYP4_0": null, + "BRAM_BYP4_1": null, + "BRAM_BYP4_2": null, + "BRAM_BYP4_3": null, + "BRAM_BYP4_4": null, + "BRAM_BYP5_0": null, + "BRAM_BYP5_1": null, + "BRAM_BYP5_2": null, + "BRAM_BYP5_3": null, + "BRAM_BYP5_4": null, + "BRAM_BYP6_0": null, + "BRAM_BYP6_1": null, + "BRAM_BYP6_2": null, + "BRAM_BYP6_3": null, + "BRAM_BYP6_4": null, + "BRAM_BYP7_0": null, + "BRAM_BYP7_1": null, + "BRAM_BYP7_2": null, + "BRAM_BYP7_3": null, + "BRAM_BYP7_4": null, + "BRAM_CASCINBOT_ADDRARDADDRU0": null, + "BRAM_CASCINBOT_ADDRARDADDRU1": null, + "BRAM_CASCINBOT_ADDRARDADDRU10": null, + "BRAM_CASCINBOT_ADDRARDADDRU11": null, + "BRAM_CASCINBOT_ADDRARDADDRU12": null, + "BRAM_CASCINBOT_ADDRARDADDRU13": null, + "BRAM_CASCINBOT_ADDRARDADDRU14": null, + "BRAM_CASCINBOT_ADDRARDADDRU2": null, + "BRAM_CASCINBOT_ADDRARDADDRU3": null, + "BRAM_CASCINBOT_ADDRARDADDRU4": null, + "BRAM_CASCINBOT_ADDRARDADDRU5": null, + "BRAM_CASCINBOT_ADDRARDADDRU6": null, + "BRAM_CASCINBOT_ADDRARDADDRU7": null, + "BRAM_CASCINBOT_ADDRARDADDRU8": null, + "BRAM_CASCINBOT_ADDRARDADDRU9": null, + "BRAM_CASCINBOT_ADDRBWRADDRU0": null, + "BRAM_CASCINBOT_ADDRBWRADDRU1": null, + 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"0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_ADDRBWRADDRU9" }, "BRAM_R.BRAM_BYP3_2->BRAM_FIFO18_WEBWE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_BYP3_2" }, "BRAM_R.BRAM_BYP3_2->BRAM_FIFO36_WEBWEL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_BYP3_2" }, "BRAM_R.BRAM_BYP6_2->BRAM_FIFO18_WEBWE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_BYP6_2" }, "BRAM_R.BRAM_BYP6_2->BRAM_FIFO36_WEBWEL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_BYP6_2" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU0" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU1" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU10" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU11" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU12" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU13" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU14" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU2" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU3" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU4" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU5" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU6" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU7" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU8" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_R.BRAM_CASCINBOT_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRARDADDRU9" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU0" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU1" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU10" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU11" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU12" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU13" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU14" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU2" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU3" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU4" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU5" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU6" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU7" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU8" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_R.BRAM_CASCINBOT_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINBOT_ADDRBWRADDRU9" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU0" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU1" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU10" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU11" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU12" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU13" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU14" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU2" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU3" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU4" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU5" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU6" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU7" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU8" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_R.BRAM_CASCINTOP_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRARDADDRU9" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU0" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU1" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU10" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU11" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU12" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU13" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU14" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU2" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU3" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU4" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU5" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU6" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU7" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU8" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_R.BRAM_CASCINTOP_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CASCINTOP_ADDRBWRADDRU9" }, "BRAM_R.BRAM_CLK0_0->BRAM_FIFO18_REGCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_0" }, "BRAM_R.BRAM_CLK0_0->BRAM_FIFO36_REGCLKBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_0" }, "BRAM_R.BRAM_CLK0_1->BRAM_FIFO18_CLKBWRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_CLKBWRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_1" }, "BRAM_R.BRAM_CLK0_1->BRAM_FIFO36_CLKBWRCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_1" }, "BRAM_R.BRAM_CLK0_3->BRAM_FIFO18_CLKARDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_CLKARDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_3" }, "BRAM_R.BRAM_CLK0_3->BRAM_FIFO36_CLKARDCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKARDCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_3" }, "BRAM_R.BRAM_CLK0_4->BRAM_FIFO18_REGCLKARDRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCLKARDRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_4" }, "BRAM_R.BRAM_CLK0_4->BRAM_FIFO36_REGCLKARDRCLKL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK0_4" }, "BRAM_R.BRAM_CLK1_0->BRAM_FIFO36_REGCLKBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_0" }, "BRAM_R.BRAM_CLK1_0->BRAM_RAMB18_REGCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_0" }, "BRAM_R.BRAM_CLK1_1->BRAM_FIFO36_CLKBWRCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKBWRCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_1" }, "BRAM_R.BRAM_CLK1_1->BRAM_RAMB18_CLKBWRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_CLKBWRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_1" }, "BRAM_R.BRAM_CLK1_3->BRAM_FIFO36_CLKARDCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CLKARDCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_3" }, "BRAM_R.BRAM_CLK1_3->BRAM_RAMB18_CLKARDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_CLKARDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_3" }, "BRAM_R.BRAM_CLK1_4->BRAM_FIFO36_REGCLKARDRCLKU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCLKARDRCLKU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_4" }, "BRAM_R.BRAM_CLK1_4->BRAM_RAMB18_REGCLKARDRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCLKARDRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CLK1_4" }, "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO18_RSTREGB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTREGB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_R.BRAM_CTRL0_0->BRAM_FIFO36_RSTREGBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_0" }, "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO18_RSTRAMB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTRAMB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_R.BRAM_CTRL0_1->BRAM_FIFO36_RSTRAMBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_1" }, "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO18_RSTRAMARSTRAM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTRAMARSTRAM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_R.BRAM_CTRL0_3->BRAM_FIFO36_RSTRAMARSTRAMLRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMLRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_3" }, "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO18_RSTREGARSTREG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_RSTREGARSTREG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_R.BRAM_CTRL0_4->BRAM_FIFO36_RSTREGARSTREGL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL0_4" }, "BRAM_R.BRAM_CTRL1_0->BRAM_FIFO36_RSTREGBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_R.BRAM_CTRL1_0->BRAM_RAMB18_RSTREGB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTREGB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_0" }, "BRAM_R.BRAM_CTRL1_1->BRAM_FIFO36_RSTRAMBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_R.BRAM_CTRL1_1->BRAM_RAMB18_RSTRAMB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTRAMB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_1" }, "BRAM_R.BRAM_CTRL1_3->BRAM_FIFO36_RSTRAMARSTRAMU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTRAMARSTRAMU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_R.BRAM_CTRL1_3->BRAM_RAMB18_RSTRAMARSTRAM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTRAMARSTRAM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_3" }, "BRAM_R.BRAM_CTRL1_4->BRAM_FIFO36_RSTREGARSTREGU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_RSTREGARSTREGU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_R.BRAM_CTRL1_4->BRAM_RAMB18_RSTREGARSTREG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_RSTREGARSTREG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_CTRL1_4" }, "BRAM_R.BRAM_FAN1_2->BRAM_FIFO36_WEBWEU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN1_2" }, "BRAM_R.BRAM_FAN1_2->BRAM_RAMB18_WEBWE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN1_2" }, "BRAM_R.BRAM_FAN5_2->BRAM_FIFO36_WEBWEU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN5_2" }, "BRAM_R.BRAM_FAN5_2->BRAM_RAMB18_WEBWE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FAN5_2" }, "BRAM_R.BRAM_FIFO18_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_ALMOSTEMPTY" }, "BRAM_R.BRAM_FIFO18_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_ALMOSTFULL" }, "BRAM_R.BRAM_FIFO18_DOADO0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO0" }, "BRAM_R.BRAM_FIFO18_DOADO1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO1" }, "BRAM_R.BRAM_FIFO18_DOADO10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO10" }, "BRAM_R.BRAM_FIFO18_DOADO11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO11" }, "BRAM_R.BRAM_FIFO18_DOADO12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO12" }, "BRAM_R.BRAM_FIFO18_DOADO13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO13" }, "BRAM_R.BRAM_FIFO18_DOADO14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO14" }, "BRAM_R.BRAM_FIFO18_DOADO15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO15" }, "BRAM_R.BRAM_FIFO18_DOADO2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO2" }, "BRAM_R.BRAM_FIFO18_DOADO3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO3" }, "BRAM_R.BRAM_FIFO18_DOADO4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO4" }, "BRAM_R.BRAM_FIFO18_DOADO5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO5" }, "BRAM_R.BRAM_FIFO18_DOADO6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO6" }, "BRAM_R.BRAM_FIFO18_DOADO7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO7" }, "BRAM_R.BRAM_FIFO18_DOADO8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO8" }, "BRAM_R.BRAM_FIFO18_DOADO9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOADO9" }, "BRAM_R.BRAM_FIFO18_DOBDO0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO0" }, "BRAM_R.BRAM_FIFO18_DOBDO1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO1" }, "BRAM_R.BRAM_FIFO18_DOBDO10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO10" }, "BRAM_R.BRAM_FIFO18_DOBDO11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO11" }, "BRAM_R.BRAM_FIFO18_DOBDO12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO12" }, "BRAM_R.BRAM_FIFO18_DOBDO13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO13" }, "BRAM_R.BRAM_FIFO18_DOBDO14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO14" }, "BRAM_R.BRAM_FIFO18_DOBDO15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO15" }, "BRAM_R.BRAM_FIFO18_DOBDO2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO2" }, "BRAM_R.BRAM_FIFO18_DOBDO3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO3" }, "BRAM_R.BRAM_FIFO18_DOBDO4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO4" }, "BRAM_R.BRAM_FIFO18_DOBDO5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO5" }, "BRAM_R.BRAM_FIFO18_DOBDO6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO6" }, "BRAM_R.BRAM_FIFO18_DOBDO7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO7" }, "BRAM_R.BRAM_FIFO18_DOBDO8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO8" }, "BRAM_R.BRAM_FIFO18_DOBDO9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOBDO9" }, "BRAM_R.BRAM_FIFO18_DOPADOP0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPADOP0" }, "BRAM_R.BRAM_FIFO18_DOPADOP1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPADOP1" }, "BRAM_R.BRAM_FIFO18_DOPBDOP0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPBDOP0" }, "BRAM_R.BRAM_FIFO18_DOPBDOP1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_DOPBDOP1" }, "BRAM_R.BRAM_FIFO18_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_EMPTY" }, "BRAM_R.BRAM_FIFO18_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_FULL" }, "BRAM_R.BRAM_FIFO18_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT0" }, "BRAM_R.BRAM_FIFO18_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT1" }, "BRAM_R.BRAM_FIFO18_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT10" }, "BRAM_R.BRAM_FIFO18_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT11" }, "BRAM_R.BRAM_FIFO18_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT2" }, "BRAM_R.BRAM_FIFO18_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT3" }, "BRAM_R.BRAM_FIFO18_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT4" }, "BRAM_R.BRAM_FIFO18_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT5" }, "BRAM_R.BRAM_FIFO18_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT6" }, "BRAM_R.BRAM_FIFO18_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT7" }, "BRAM_R.BRAM_FIFO18_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT8" }, "BRAM_R.BRAM_FIFO18_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDCOUNT9" }, "BRAM_R.BRAM_FIFO18_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_RDERR" }, "BRAM_R.BRAM_FIFO18_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT0" }, "BRAM_R.BRAM_FIFO18_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT1" }, "BRAM_R.BRAM_FIFO18_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT10" }, "BRAM_R.BRAM_FIFO18_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT11" }, "BRAM_R.BRAM_FIFO18_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT2" }, "BRAM_R.BRAM_FIFO18_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT3" }, "BRAM_R.BRAM_FIFO18_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT4" }, "BRAM_R.BRAM_FIFO18_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT5" }, "BRAM_R.BRAM_FIFO18_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT6" }, "BRAM_R.BRAM_FIFO18_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT7" }, "BRAM_R.BRAM_FIFO18_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT8" }, "BRAM_R.BRAM_FIFO18_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRCOUNT9" }, "BRAM_R.BRAM_FIFO18_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO18_WRERR" }, "BRAM_R.BRAM_FIFO36_ALMOSTEMPTY->BRAM_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ALMOSTEMPTY" }, "BRAM_R.BRAM_FIFO36_ALMOSTFULL->BRAM_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ALMOSTFULL" }, "BRAM_R.BRAM_FIFO36_CASCADEOUTA->BRAM_FIFO36_CASCADEOUTA_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CASCADEOUTA_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_CASCADEOUTA" }, "BRAM_R.BRAM_FIFO36_CASCADEOUTB->BRAM_FIFO36_CASCADEOUTB_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_CASCADEOUTB_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_CASCADEOUTB" }, "BRAM_R.BRAM_FIFO36_DBITERR->BRAM_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DBITERR" }, "BRAM_R.BRAM_FIFO36_DOADOL0->BRAM_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL0" }, "BRAM_R.BRAM_FIFO36_DOADOL1->BRAM_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL1" }, "BRAM_R.BRAM_FIFO36_DOADOL10->BRAM_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL10" }, "BRAM_R.BRAM_FIFO36_DOADOL11->BRAM_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL11" }, "BRAM_R.BRAM_FIFO36_DOADOL12->BRAM_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL12" }, "BRAM_R.BRAM_FIFO36_DOADOL13->BRAM_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL13" }, "BRAM_R.BRAM_FIFO36_DOADOL14->BRAM_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL14" }, "BRAM_R.BRAM_FIFO36_DOADOL15->BRAM_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL15" }, "BRAM_R.BRAM_FIFO36_DOADOL2->BRAM_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL2" }, "BRAM_R.BRAM_FIFO36_DOADOL3->BRAM_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL3" }, "BRAM_R.BRAM_FIFO36_DOADOL4->BRAM_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL4" }, "BRAM_R.BRAM_FIFO36_DOADOL5->BRAM_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL5" }, "BRAM_R.BRAM_FIFO36_DOADOL6->BRAM_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL6" }, "BRAM_R.BRAM_FIFO36_DOADOL7->BRAM_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL7" }, "BRAM_R.BRAM_FIFO36_DOADOL8->BRAM_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL8" }, "BRAM_R.BRAM_FIFO36_DOADOL9->BRAM_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOL9" }, "BRAM_R.BRAM_FIFO36_DOADOU0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU0" }, "BRAM_R.BRAM_FIFO36_DOADOU1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU1" }, "BRAM_R.BRAM_FIFO36_DOADOU10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU10" }, "BRAM_R.BRAM_FIFO36_DOADOU11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU11" }, "BRAM_R.BRAM_FIFO36_DOADOU12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU12" }, "BRAM_R.BRAM_FIFO36_DOADOU13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU13" }, "BRAM_R.BRAM_FIFO36_DOADOU14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU14" }, "BRAM_R.BRAM_FIFO36_DOADOU15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU15" }, "BRAM_R.BRAM_FIFO36_DOADOU2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU2" }, "BRAM_R.BRAM_FIFO36_DOADOU3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU3" }, "BRAM_R.BRAM_FIFO36_DOADOU4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU4" }, "BRAM_R.BRAM_FIFO36_DOADOU5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU5" }, "BRAM_R.BRAM_FIFO36_DOADOU6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU6" }, "BRAM_R.BRAM_FIFO36_DOADOU7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU7" }, "BRAM_R.BRAM_FIFO36_DOADOU8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU8" }, "BRAM_R.BRAM_FIFO36_DOADOU9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOADOU9" }, "BRAM_R.BRAM_FIFO36_DOBDOL0->BRAM_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL0" }, "BRAM_R.BRAM_FIFO36_DOBDOL1->BRAM_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL1" }, "BRAM_R.BRAM_FIFO36_DOBDOL10->BRAM_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL10" }, "BRAM_R.BRAM_FIFO36_DOBDOL11->BRAM_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL11" }, "BRAM_R.BRAM_FIFO36_DOBDOL12->BRAM_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL12" }, "BRAM_R.BRAM_FIFO36_DOBDOL13->BRAM_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL13" }, "BRAM_R.BRAM_FIFO36_DOBDOL14->BRAM_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL14" }, "BRAM_R.BRAM_FIFO36_DOBDOL15->BRAM_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL15" }, "BRAM_R.BRAM_FIFO36_DOBDOL2->BRAM_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL2" }, "BRAM_R.BRAM_FIFO36_DOBDOL3->BRAM_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL3" }, "BRAM_R.BRAM_FIFO36_DOBDOL4->BRAM_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL4" }, "BRAM_R.BRAM_FIFO36_DOBDOL5->BRAM_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL5" }, "BRAM_R.BRAM_FIFO36_DOBDOL6->BRAM_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL6" }, "BRAM_R.BRAM_FIFO36_DOBDOL7->BRAM_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL7" }, "BRAM_R.BRAM_FIFO36_DOBDOL8->BRAM_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL8" }, "BRAM_R.BRAM_FIFO36_DOBDOL9->BRAM_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOL9" }, "BRAM_R.BRAM_FIFO36_DOBDOU0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU0" }, "BRAM_R.BRAM_FIFO36_DOBDOU1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU1" }, "BRAM_R.BRAM_FIFO36_DOBDOU10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU10" }, "BRAM_R.BRAM_FIFO36_DOBDOU11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU11" }, "BRAM_R.BRAM_FIFO36_DOBDOU12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU12" }, "BRAM_R.BRAM_FIFO36_DOBDOU13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU13" }, "BRAM_R.BRAM_FIFO36_DOBDOU14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU14" }, "BRAM_R.BRAM_FIFO36_DOBDOU15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU15" }, "BRAM_R.BRAM_FIFO36_DOBDOU2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU2" }, "BRAM_R.BRAM_FIFO36_DOBDOU3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU3" }, "BRAM_R.BRAM_FIFO36_DOBDOU4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU4" }, "BRAM_R.BRAM_FIFO36_DOBDOU5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU5" }, "BRAM_R.BRAM_FIFO36_DOBDOU6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU6" }, "BRAM_R.BRAM_FIFO36_DOBDOU7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU7" }, "BRAM_R.BRAM_FIFO36_DOBDOU8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU8" }, "BRAM_R.BRAM_FIFO36_DOBDOU9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOBDOU9" }, "BRAM_R.BRAM_FIFO36_DOPADOPL0->BRAM_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPL0" }, "BRAM_R.BRAM_FIFO36_DOPADOPL1->BRAM_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPL1" }, "BRAM_R.BRAM_FIFO36_DOPADOPU0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPU0" }, "BRAM_R.BRAM_FIFO36_DOPADOPU1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPADOPU1" }, "BRAM_R.BRAM_FIFO36_DOPBDOPL0->BRAM_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPL0" }, "BRAM_R.BRAM_FIFO36_DOPBDOPL1->BRAM_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPL1" }, "BRAM_R.BRAM_FIFO36_DOPBDOPU0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPU0" }, "BRAM_R.BRAM_FIFO36_DOPBDOPU1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_DOPBDOPU1" }, "BRAM_R.BRAM_FIFO36_ECCPARITY0->BRAM_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY0" }, "BRAM_R.BRAM_FIFO36_ECCPARITY1->BRAM_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY1" }, "BRAM_R.BRAM_FIFO36_ECCPARITY2->BRAM_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY2" }, "BRAM_R.BRAM_FIFO36_ECCPARITY3->BRAM_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY3" }, "BRAM_R.BRAM_FIFO36_ECCPARITY4->BRAM_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY4" }, "BRAM_R.BRAM_FIFO36_ECCPARITY5->BRAM_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY5" }, "BRAM_R.BRAM_FIFO36_ECCPARITY6->BRAM_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY6" }, "BRAM_R.BRAM_FIFO36_ECCPARITY7->BRAM_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_ECCPARITY7" }, "BRAM_R.BRAM_FIFO36_EMPTY->BRAM_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_EMPTY" }, "BRAM_R.BRAM_FIFO36_FULL->BRAM_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_FULL" }, "BRAM_R.BRAM_FIFO36_RDCOUNT0->BRAM_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT0" }, "BRAM_R.BRAM_FIFO36_RDCOUNT1->BRAM_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT1" }, "BRAM_R.BRAM_FIFO36_RDCOUNT10->BRAM_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT10" }, "BRAM_R.BRAM_FIFO36_RDCOUNT11->BRAM_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT11" }, "BRAM_R.BRAM_FIFO36_RDCOUNT12->BRAM_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT12" }, "BRAM_R.BRAM_FIFO36_RDCOUNT2->BRAM_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT2" }, "BRAM_R.BRAM_FIFO36_RDCOUNT3->BRAM_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT3" }, "BRAM_R.BRAM_FIFO36_RDCOUNT4->BRAM_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT4" }, "BRAM_R.BRAM_FIFO36_RDCOUNT5->BRAM_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT5" }, "BRAM_R.BRAM_FIFO36_RDCOUNT6->BRAM_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT6" }, "BRAM_R.BRAM_FIFO36_RDCOUNT7->BRAM_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT7" }, "BRAM_R.BRAM_FIFO36_RDCOUNT8->BRAM_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT8" }, "BRAM_R.BRAM_FIFO36_RDCOUNT9->BRAM_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDCOUNT9" }, "BRAM_R.BRAM_FIFO36_RDERR->BRAM_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_RDERR" }, "BRAM_R.BRAM_FIFO36_SBITERR->BRAM_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_SBITERR" }, "BRAM_R.BRAM_FIFO36_TSTOUT0->BRAM_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT0" }, "BRAM_R.BRAM_FIFO36_TSTOUT1->BRAM_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT1" }, "BRAM_R.BRAM_FIFO36_TSTOUT2->BRAM_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT2" }, "BRAM_R.BRAM_FIFO36_TSTOUT3->BRAM_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT3" }, "BRAM_R.BRAM_FIFO36_TSTOUT4->BRAM_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_TSTOUT4" }, "BRAM_R.BRAM_FIFO36_WRCOUNT0->BRAM_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT0" }, "BRAM_R.BRAM_FIFO36_WRCOUNT1->BRAM_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT1" }, "BRAM_R.BRAM_FIFO36_WRCOUNT10->BRAM_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT10" }, "BRAM_R.BRAM_FIFO36_WRCOUNT11->BRAM_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT11" }, "BRAM_R.BRAM_FIFO36_WRCOUNT12->BRAM_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT12" }, "BRAM_R.BRAM_FIFO36_WRCOUNT2->BRAM_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT2" }, "BRAM_R.BRAM_FIFO36_WRCOUNT3->BRAM_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT3" }, "BRAM_R.BRAM_FIFO36_WRCOUNT4->BRAM_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT4" }, "BRAM_R.BRAM_FIFO36_WRCOUNT5->BRAM_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT5" }, "BRAM_R.BRAM_FIFO36_WRCOUNT6->BRAM_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT6" }, "BRAM_R.BRAM_FIFO36_WRCOUNT7->BRAM_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT7" }, "BRAM_R.BRAM_FIFO36_WRCOUNT8->BRAM_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT8" }, "BRAM_R.BRAM_FIFO36_WRCOUNT9->BRAM_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRCOUNT9" }, "BRAM_R.BRAM_FIFO36_WRERR->BRAM_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_FIFO36_WRERR" }, "BRAM_R.BRAM_IMUX0_0->BRAM_FIFO36_TSTBRAMRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTBRAMRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX0_0" }, "BRAM_R.BRAM_IMUX10_0->BRAM_FIFO36_TSTCNT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_0" }, "BRAM_R.BRAM_IMUX10_1->BRAM_R_IMUX_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_1" }, "BRAM_R.BRAM_IMUX10_2->BRAM_FIFO36_ENARDENU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENARDENU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_R.BRAM_IMUX10_2->BRAM_RAMB18_ENARDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_ENARDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_2" }, "BRAM_R.BRAM_IMUX10_3->BRAM_R_IMUX_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_3" }, "BRAM_R.BRAM_IMUX10_4->BRAM_FIFO36_DIADIU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_R.BRAM_IMUX10_4->BRAM_RAMB18_DIADI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX10_4" }, "BRAM_R.BRAM_IMUX11_0->BRAM_FIFO36_TSTCNT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_0" }, "BRAM_R.BRAM_IMUX11_1->BRAM_R_IMUX_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_1" }, "BRAM_R.BRAM_IMUX11_2->BRAM_FIFO36_REGCEAREGCEU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_R.BRAM_IMUX11_2->BRAM_RAMB18_REGCEAREGCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCEAREGCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_2" }, "BRAM_R.BRAM_IMUX11_3->BRAM_R_IMUX_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_3" }, "BRAM_R.BRAM_IMUX11_4->BRAM_FIFO36_DIADIU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_R.BRAM_IMUX11_4->BRAM_RAMB18_DIADI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX11_4" }, "BRAM_R.BRAM_IMUX12_0->BRAM_FIFO36_TSTCNT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_0" }, "BRAM_R.BRAM_IMUX12_1->BRAM_R_IMUX_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_1" }, "BRAM_R.BRAM_IMUX12_2->BRAM_R_IMUX_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_2" }, "BRAM_R.BRAM_IMUX12_3->BRAM_R_IMUX_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_3" }, "BRAM_R.BRAM_IMUX12_4->BRAM_FIFO36_DIADIU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_R.BRAM_IMUX12_4->BRAM_RAMB18_DIADI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX12_4" }, "BRAM_R.BRAM_IMUX13_0->BRAM_FIFO36_TSTCNT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_0" }, "BRAM_R.BRAM_IMUX13_1->BRAM_R_IMUX_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_1" }, "BRAM_R.BRAM_IMUX13_2->BRAM_FIFO36_WEBWEU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_R.BRAM_IMUX13_2->BRAM_RAMB18_WEBWE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_2" }, "BRAM_R.BRAM_IMUX13_3->BRAM_R_IMUX_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_3" }, "BRAM_R.BRAM_IMUX13_4->BRAM_FIFO36_DIADIU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_R.BRAM_IMUX13_4->BRAM_RAMB18_DIADI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX13_4" }, "BRAM_R.BRAM_IMUX14_0->BRAM_FIFO36_TSTCNT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_0" }, "BRAM_R.BRAM_IMUX14_1->BRAM_R_IMUX_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_1" }, "BRAM_R.BRAM_IMUX14_2->BRAM_FIFO36_WEBWEU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_R.BRAM_IMUX14_2->BRAM_RAMB18_WEBWE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_2" }, "BRAM_R.BRAM_IMUX14_3->BRAM_R_IMUX_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_3" }, "BRAM_R.BRAM_IMUX14_4->BRAM_FIFO36_DIADIU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_R.BRAM_IMUX14_4->BRAM_RAMB18_DIADI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX14_4" }, "BRAM_R.BRAM_IMUX15_0->BRAM_FIFO36_TSTCNT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_0" }, "BRAM_R.BRAM_IMUX15_1->BRAM_R_IMUX_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_1" }, "BRAM_R.BRAM_IMUX15_2->BRAM_FIFO36_DIADIU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_R.BRAM_IMUX15_2->BRAM_RAMB18_DIADI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_2" }, "BRAM_R.BRAM_IMUX15_3->BRAM_FIFO36_DIPADIPU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_R.BRAM_IMUX15_3->BRAM_RAMB18_DIPADIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPADIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_3" }, "BRAM_R.BRAM_IMUX15_4->BRAM_FIFO36_DIADIU15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_R.BRAM_IMUX15_4->BRAM_RAMB18_DIADI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX15_4" }, "BRAM_R.BRAM_IMUX16_0->BRAM_FIFO36_TSTIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_0" }, "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO18_DIADI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_R.BRAM_IMUX16_1->BRAM_FIFO36_DIADIL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_1" }, "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO18_WEA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_R.BRAM_IMUX16_2->BRAM_FIFO36_WEAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_2" }, "BRAM_R.BRAM_IMUX16_3->BRAM_R_IMUX_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_3" }, "BRAM_R.BRAM_IMUX16_4->BRAM_FIFO36_DIBDIU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_R.BRAM_IMUX16_4->BRAM_RAMB18_DIBDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX16_4" }, "BRAM_R.BRAM_IMUX17_1->BRAM_R_IMUX_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_1" }, "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO18_WEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_R.BRAM_IMUX17_2->BRAM_FIFO36_WEAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_2" }, "BRAM_R.BRAM_IMUX17_3->BRAM_R_IMUX_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_3" }, "BRAM_R.BRAM_IMUX17_4->BRAM_FIFO36_DIBDIU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_R.BRAM_IMUX17_4->BRAM_RAMB18_DIBDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX17_4" }, "BRAM_R.BRAM_IMUX18_0->BRAM_FIFO36_TSTRDOS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_0" }, "BRAM_R.BRAM_IMUX18_1->BRAM_R_IMUX_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_1" }, "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO18_ENARDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_ENARDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_R.BRAM_IMUX18_2->BRAM_FIFO36_ENARDENL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENARDENL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_2" }, "BRAM_R.BRAM_IMUX18_3->BRAM_R_IMUX_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_3" }, "BRAM_R.BRAM_IMUX18_4->BRAM_FIFO36_DIBDIU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_R.BRAM_IMUX18_4->BRAM_RAMB18_DIBDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX18_4" }, "BRAM_R.BRAM_IMUX19_0->BRAM_FIFO36_TSTRDOS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_0" }, "BRAM_R.BRAM_IMUX19_1->BRAM_R_IMUX_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_1" }, "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO18_REGCEAREGCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCEAREGCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_R.BRAM_IMUX19_2->BRAM_FIFO36_REGCEAREGCEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEAREGCEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_2" }, "BRAM_R.BRAM_IMUX19_3->BRAM_R_IMUX_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_3" }, "BRAM_R.BRAM_IMUX19_4->BRAM_FIFO36_DIBDIU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_R.BRAM_IMUX19_4->BRAM_RAMB18_DIBDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX19_4" }, "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO18_DIPBDIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPBDIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_R.BRAM_IMUX1_1->BRAM_FIFO36_DIPBDIPL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_1" }, "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO18_DIBDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_R.BRAM_IMUX1_2->BRAM_FIFO36_DIBDIL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_2" }, "BRAM_R.BRAM_IMUX1_3->BRAM_FIFO36_DIBDIU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_R.BRAM_IMUX1_3->BRAM_RAMB18_DIBDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX1_3" }, "BRAM_R.BRAM_IMUX20_0->BRAM_FIFO36_TSTRDOS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_0" }, "BRAM_R.BRAM_IMUX20_1->BRAM_R_IMUX_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_1" }, "BRAM_R.BRAM_IMUX20_2->BRAM_R_IMUX_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_2" }, "BRAM_R.BRAM_IMUX20_3->BRAM_R_IMUX_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_3" }, "BRAM_R.BRAM_IMUX20_4->BRAM_FIFO36_DIBDIU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_R.BRAM_IMUX20_4->BRAM_RAMB18_DIBDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX20_4" }, "BRAM_R.BRAM_IMUX21_0->BRAM_FIFO36_TSTRDOS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_0" }, "BRAM_R.BRAM_IMUX21_1->BRAM_R_IMUX_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_1" }, "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO18_WEBWE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_R.BRAM_IMUX21_2->BRAM_FIFO36_WEBWEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_2" }, "BRAM_R.BRAM_IMUX21_3->BRAM_R_IMUX_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_3" }, "BRAM_R.BRAM_IMUX21_4->BRAM_FIFO36_DIBDIU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_R.BRAM_IMUX21_4->BRAM_RAMB18_DIBDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX21_4" }, "BRAM_R.BRAM_IMUX22_0->BRAM_FIFO36_TSTRDOS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_0" }, "BRAM_R.BRAM_IMUX22_1->BRAM_R_IMUX_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_1" }, "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO18_WEBWE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_R.BRAM_IMUX22_2->BRAM_FIFO36_WEBWEL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_2" }, "BRAM_R.BRAM_IMUX22_3->BRAM_R_IMUX_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_3" }, "BRAM_R.BRAM_IMUX22_4->BRAM_FIFO36_DIBDIU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_R.BRAM_IMUX22_4->BRAM_RAMB18_DIBDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX22_4" }, "BRAM_R.BRAM_IMUX23_0->BRAM_FIFO36_TSTRDOS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_0" }, "BRAM_R.BRAM_IMUX23_1->BRAM_R_IMUX_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_1" }, "BRAM_R.BRAM_IMUX23_2->BRAM_FIFO36_DIBDIU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_R.BRAM_IMUX23_2->BRAM_RAMB18_DIBDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_2" }, "BRAM_R.BRAM_IMUX23_3->BRAM_FIFO36_DIPBDIPU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_R.BRAM_IMUX23_3->BRAM_RAMB18_DIPBDIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPBDIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_3" }, "BRAM_R.BRAM_IMUX23_4->BRAM_FIFO36_DIBDIU15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_R.BRAM_IMUX23_4->BRAM_RAMB18_DIBDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX23_4" }, "BRAM_R.BRAM_IMUX24_1->BRAM_FIFO36_DIBDIU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_R.BRAM_IMUX24_1->BRAM_RAMB18_DIBDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_1" }, "BRAM_R.BRAM_IMUX24_2->BRAM_FIFO36_WEAU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_R.BRAM_IMUX24_2->BRAM_RAMB18_WEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_2" }, "BRAM_R.BRAM_IMUX24_3->BRAM_R_IMUX_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_3" }, "BRAM_R.BRAM_IMUX24_4->BRAM_FIFO36_TSTCNT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX24_4" }, "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO18_DIADI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_R.BRAM_IMUX25_0->BRAM_FIFO36_DIADIL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_0" }, "BRAM_R.BRAM_IMUX25_1->BRAM_R_IMUX_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_1" }, "BRAM_R.BRAM_IMUX25_2->BRAM_FIFO36_WEAU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_R.BRAM_IMUX25_2->BRAM_RAMB18_WEA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_2" }, "BRAM_R.BRAM_IMUX25_3->BRAM_R_IMUX_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_3" }, "BRAM_R.BRAM_IMUX25_4->BRAM_FIFO36_TSTCNT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX25_4" }, "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO18_DIADI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_R.BRAM_IMUX26_0->BRAM_FIFO36_DIADIL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_0" }, "BRAM_R.BRAM_IMUX26_1->BRAM_R_IMUX_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_1" }, "BRAM_R.BRAM_IMUX26_2->BRAM_FIFO36_ENBWRENU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENBWRENU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_R.BRAM_IMUX26_2->BRAM_RAMB18_ENBWREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_ENBWREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_2" }, "BRAM_R.BRAM_IMUX26_3->BRAM_R_IMUX_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_3" }, "BRAM_R.BRAM_IMUX26_4->BRAM_FIFO36_TSTCNT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX26_4" }, "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO18_DIADI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_R.BRAM_IMUX27_0->BRAM_FIFO36_DIADIL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_0" }, "BRAM_R.BRAM_IMUX27_1->BRAM_R_IMUX_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_1" }, "BRAM_R.BRAM_IMUX27_2->BRAM_FIFO36_REGCEBU": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEBU", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_R.BRAM_IMUX27_2->BRAM_RAMB18_REGCEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_REGCEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_2" }, "BRAM_R.BRAM_IMUX27_3->BRAM_R_IMUX_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_3" }, "BRAM_R.BRAM_IMUX27_4->BRAM_FIFO36_TSTCNT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX27_4" }, "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO18_DIADI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_R.BRAM_IMUX28_0->BRAM_FIFO36_DIADIL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_0" }, "BRAM_R.BRAM_IMUX28_1->BRAM_R_IMUX_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_1" }, "BRAM_R.BRAM_IMUX28_2->BRAM_R_IMUX_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_2" }, "BRAM_R.BRAM_IMUX28_3->BRAM_R_IMUX_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_3" }, "BRAM_R.BRAM_IMUX28_4->BRAM_FIFO36_TSTCNT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX28_4" }, "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO18_DIADI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_R.BRAM_IMUX29_0->BRAM_FIFO36_DIADIL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_0" }, "BRAM_R.BRAM_IMUX29_1->BRAM_R_IMUX_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_1" }, "BRAM_R.BRAM_IMUX29_2->BRAM_FIFO36_WEBWEU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_R.BRAM_IMUX29_2->BRAM_RAMB18_WEBWE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_2" }, "BRAM_R.BRAM_IMUX29_3->BRAM_R_IMUX_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_3" }, "BRAM_R.BRAM_IMUX29_4->BRAM_FIFO36_TSTCNT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX29_4" }, "BRAM_R.BRAM_IMUX2_0->BRAM_FIFO36_TSTRDCNTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDCNTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_0" }, "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO18_DIBDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_R.BRAM_IMUX2_1->BRAM_FIFO36_DIBDIL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_1" }, "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO18_DIBDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_R.BRAM_IMUX2_2->BRAM_FIFO36_DIBDIL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_2" }, "BRAM_R.BRAM_IMUX2_3->BRAM_FIFO36_DIBDIU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_R.BRAM_IMUX2_3->BRAM_RAMB18_DIBDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX2_3" }, "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO18_DIADI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_R.BRAM_IMUX30_0->BRAM_FIFO36_DIADIL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_0" }, "BRAM_R.BRAM_IMUX30_1->BRAM_R_IMUX_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_1" }, "BRAM_R.BRAM_IMUX30_2->BRAM_FIFO36_WEBWEU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_R.BRAM_IMUX30_2->BRAM_RAMB18_WEBWE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_2" }, "BRAM_R.BRAM_IMUX30_3->BRAM_R_IMUX_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_3" }, "BRAM_R.BRAM_IMUX30_4->BRAM_FIFO36_TSTCNT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTCNT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX30_4" }, "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO18_DIADI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_R.BRAM_IMUX31_0->BRAM_FIFO36_DIADIL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_0" }, "BRAM_R.BRAM_IMUX31_1->BRAM_R_IMUX_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_1" }, "BRAM_R.BRAM_IMUX31_2->BRAM_FIFO36_INJECTDBITERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_INJECTDBITERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_2" }, "BRAM_R.BRAM_IMUX31_3->BRAM_IMUX_R_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_R_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX31_3" }, "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO18_DIBDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_R.BRAM_IMUX32_1->BRAM_FIFO36_DIBDIL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_1" }, "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO18_WEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_R.BRAM_IMUX32_2->BRAM_FIFO36_WEAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_2" }, "BRAM_R.BRAM_IMUX32_3->BRAM_R_IMUX_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_3" }, "BRAM_R.BRAM_IMUX32_4->BRAM_FIFO36_TSTRDOS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX32_4" }, "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO18_DIBDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_R.BRAM_IMUX33_0->BRAM_FIFO36_DIBDIL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_0" }, "BRAM_R.BRAM_IMUX33_1->BRAM_R_IMUX_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_1" }, "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO18_WEA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_R.BRAM_IMUX33_2->BRAM_FIFO36_WEAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_2" }, "BRAM_R.BRAM_IMUX33_3->BRAM_R_IMUX_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_3" }, "BRAM_R.BRAM_IMUX33_4->BRAM_FIFO36_TSTRDOS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX33_4" }, "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO18_DIBDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_R.BRAM_IMUX34_0->BRAM_FIFO36_DIBDIL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_0" }, "BRAM_R.BRAM_IMUX34_1->BRAM_R_IMUX_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_1" }, "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO18_ENBWREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_ENBWREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_R.BRAM_IMUX34_2->BRAM_FIFO36_ENBWRENL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_ENBWRENL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_2" }, "BRAM_R.BRAM_IMUX34_3->BRAM_R_IMUX_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_3" }, "BRAM_R.BRAM_IMUX34_4->BRAM_FIFO36_TSTRDOS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX34_4" }, "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO18_DIBDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_R.BRAM_IMUX35_0->BRAM_FIFO36_DIBDIL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_0" }, "BRAM_R.BRAM_IMUX35_1->BRAM_R_IMUX_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_1" }, "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO18_REGCEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_REGCEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_R.BRAM_IMUX35_2->BRAM_FIFO36_REGCEBL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_REGCEBL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_2" }, "BRAM_R.BRAM_IMUX35_3->BRAM_R_IMUX_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_3" }, "BRAM_R.BRAM_IMUX35_4->BRAM_FIFO36_TSTRDOS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX35_4" }, "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO18_DIBDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_R.BRAM_IMUX36_0->BRAM_FIFO36_DIBDIL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_0" }, "BRAM_R.BRAM_IMUX36_1->BRAM_R_IMUX_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_1" }, "BRAM_R.BRAM_IMUX36_2->BRAM_R_IMUX_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_2" }, "BRAM_R.BRAM_IMUX36_3->BRAM_R_IMUX_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_3" }, "BRAM_R.BRAM_IMUX36_4->BRAM_FIFO36_TSTRDOS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX36_4" }, "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO18_DIBDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_R.BRAM_IMUX37_0->BRAM_FIFO36_DIBDIL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_0" }, "BRAM_R.BRAM_IMUX37_1->BRAM_R_IMUX_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_1" }, "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO18_WEBWE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_R.BRAM_IMUX37_2->BRAM_FIFO36_WEBWEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_2" }, "BRAM_R.BRAM_IMUX37_3->BRAM_R_IMUX_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_3" }, "BRAM_R.BRAM_IMUX37_4->BRAM_FIFO36_TSTRDOS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX37_4" }, "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO18_DIBDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_R.BRAM_IMUX38_0->BRAM_FIFO36_DIBDIL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_0" }, "BRAM_R.BRAM_IMUX38_1->BRAM_R_IMUX_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_1" }, "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO18_WEBWE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_R.BRAM_IMUX38_2->BRAM_FIFO36_WEBWEL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_2" }, "BRAM_R.BRAM_IMUX38_3->BRAM_R_IMUX_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_3" }, "BRAM_R.BRAM_IMUX38_4->BRAM_FIFO36_TSTRDOS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTRDOS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX38_4" }, "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO18_DIBDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_R.BRAM_IMUX39_0->BRAM_FIFO36_DIBDIL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_0" }, "BRAM_R.BRAM_IMUX39_1->BRAM_R_IMUX_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_1" }, "BRAM_R.BRAM_IMUX39_2->BRAM_FIFO36_INJECTSBITERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_INJECTSBITERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_2" }, "BRAM_R.BRAM_IMUX39_3->BRAM_IMUX_R_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_IMUX_R_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX39_3" }, "BRAM_R.BRAM_IMUX3_0->BRAM_FIFO36_TSTWRCNTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWRCNTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_0" }, "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO18_DIBDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_R.BRAM_IMUX3_1->BRAM_FIFO36_DIBDIL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_1" }, "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO18_DIPADIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPADIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_R.BRAM_IMUX3_2->BRAM_FIFO36_DIPADIPL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_2" }, "BRAM_R.BRAM_IMUX3_3->BRAM_FIFO36_DIBDIU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_R.BRAM_IMUX3_3->BRAM_RAMB18_DIBDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX3_3" }, "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO18_DIPADIP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPADIP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_R.BRAM_IMUX40_1->BRAM_FIFO36_DIPADIPL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_1" }, "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO18_DIADI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_R.BRAM_IMUX40_2->BRAM_FIFO36_DIADIL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_2" }, "BRAM_R.BRAM_IMUX40_3->BRAM_FIFO36_DIADIU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_R.BRAM_IMUX40_3->BRAM_RAMB18_DIADI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_3" }, "BRAM_R.BRAM_IMUX40_4->BRAM_FIFO36_TSTWROS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX40_4" }, "BRAM_R.BRAM_IMUX41_0->BRAM_FIFO36_TSTIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_0" }, "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO18_DIADI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_1" }, "BRAM_R.BRAM_IMUX41_1->BRAM_FIFO36_DIADIL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_1" }, "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO18_DIADI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_2" }, "BRAM_R.BRAM_IMUX41_2->BRAM_FIFO36_DIADIL15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_2" }, "BRAM_R.BRAM_IMUX41_3->BRAM_FIFO36_DIADIU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_3" }, "BRAM_R.BRAM_IMUX41_3->BRAM_RAMB18_DIADI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_3" }, "BRAM_R.BRAM_IMUX41_4->BRAM_FIFO36_TSTWROS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX41_4" }, "BRAM_R.BRAM_IMUX42_0->BRAM_FIFO36_TSTWROS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_0" }, "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO18_DIADI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_R.BRAM_IMUX42_1->BRAM_FIFO36_DIADIL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_1" }, "BRAM_R.BRAM_IMUX42_2->BRAM_FIFO36_DIPADIPU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPADIPU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_R.BRAM_IMUX42_2->BRAM_RAMB18_DIPADIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPADIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_2" }, "BRAM_R.BRAM_IMUX42_3->BRAM_FIFO36_DIADIU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_R.BRAM_IMUX42_3->BRAM_RAMB18_DIADI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_3" }, "BRAM_R.BRAM_IMUX42_4->BRAM_FIFO36_TSTWROS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX42_4" }, "BRAM_R.BRAM_IMUX43_0->BRAM_FIFO36_TSTWROS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_0" }, "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO18_DIADI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_R.BRAM_IMUX43_1->BRAM_FIFO36_DIADIL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_1" }, "BRAM_R.BRAM_IMUX43_2->BRAM_FIFO36_DIPBDIPU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_R.BRAM_IMUX43_2->BRAM_RAMB18_DIPBDIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIPBDIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_2" }, "BRAM_R.BRAM_IMUX43_3->BRAM_FIFO36_DIADIU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_R.BRAM_IMUX43_3->BRAM_RAMB18_DIADI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_3" }, "BRAM_R.BRAM_IMUX43_4->BRAM_FIFO36_TSTWROS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX43_4" }, "BRAM_R.BRAM_IMUX44_0->BRAM_FIFO36_TSTWROS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_0" }, "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO18_DIADI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_R.BRAM_IMUX44_1->BRAM_FIFO36_DIADIL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_1" }, "BRAM_R.BRAM_IMUX44_3->BRAM_FIFO36_DIADIU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_R.BRAM_IMUX44_3->BRAM_RAMB18_DIADI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_3" }, "BRAM_R.BRAM_IMUX44_4->BRAM_FIFO36_TSTWROS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX44_4" }, "BRAM_R.BRAM_IMUX45_0->BRAM_FIFO36_TSTWROS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_0" }, "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO18_DIADI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_R.BRAM_IMUX45_1->BRAM_FIFO36_DIADIL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_1" }, "BRAM_R.BRAM_IMUX45_2->BRAM_FIFO36_WEBWEU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_R.BRAM_IMUX45_2->BRAM_RAMB18_WEBWE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_2" }, "BRAM_R.BRAM_IMUX45_3->BRAM_FIFO36_DIADIU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_R.BRAM_IMUX45_3->BRAM_RAMB18_DIADI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_3" }, "BRAM_R.BRAM_IMUX45_4->BRAM_FIFO36_TSTWROS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX45_4" }, "BRAM_R.BRAM_IMUX46_0->BRAM_FIFO36_TSTWROS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_0" }, "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO18_DIADI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIADI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_R.BRAM_IMUX46_1->BRAM_FIFO36_DIADIL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_1" }, "BRAM_R.BRAM_IMUX46_2->BRAM_FIFO36_WEBWEU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_R.BRAM_IMUX46_2->BRAM_RAMB18_WEBWE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEBWE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_2" }, "BRAM_R.BRAM_IMUX46_4->BRAM_FIFO36_TSTWROS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX46_4" }, "BRAM_R.BRAM_IMUX47_0->BRAM_FIFO36_TSTWROS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTWROS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX47_0" }, "BRAM_R.BRAM_IMUX4_0->BRAM_FIFO36_TSTOFF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTOFF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_0" }, "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO18_DIBDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_R.BRAM_IMUX4_1->BRAM_FIFO36_DIBDIL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_1" }, "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO18_DIPBDIP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIPBDIP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_R.BRAM_IMUX4_2->BRAM_FIFO36_DIPBDIPL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIPBDIPL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_2" }, "BRAM_R.BRAM_IMUX4_3->BRAM_FIFO36_DIBDIU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_R.BRAM_IMUX4_3->BRAM_RAMB18_DIBDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_3" }, "BRAM_R.BRAM_IMUX4_4->BRAM_FIFO36_TSTIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX4_4" }, "BRAM_R.BRAM_IMUX5_0->BRAM_FIFO36_TSTFLAGIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTFLAGIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_0" }, "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO18_DIBDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_R.BRAM_IMUX5_1->BRAM_FIFO36_DIBDIL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_1" }, "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO18_WEBWE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_R.BRAM_IMUX5_2->BRAM_FIFO36_WEBWEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_2" }, "BRAM_R.BRAM_IMUX5_3->BRAM_FIFO36_DIBDIU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_R.BRAM_IMUX5_3->BRAM_RAMB18_DIBDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_3" }, "BRAM_R.BRAM_IMUX5_4->BRAM_FIFO36_TSTIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX5_4" }, "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO18_DIBDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_R.BRAM_IMUX6_1->BRAM_FIFO36_DIBDIL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_1" }, "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO18_WEBWE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_WEBWE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_R.BRAM_IMUX6_2->BRAM_FIFO36_WEBWEL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEBWEL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_2" }, "BRAM_R.BRAM_IMUX6_3->BRAM_FIFO36_DIBDIU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_R.BRAM_IMUX6_3->BRAM_RAMB18_DIBDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIBDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX6_3" }, "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO18_DIBDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO18_DIBDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_R.BRAM_IMUX7_1->BRAM_FIFO36_DIBDIL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIBDIL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX7_1" }, "BRAM_R.BRAM_IMUX8_0->BRAM_FIFO36_TSTIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_TSTIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_0" }, "BRAM_R.BRAM_IMUX8_1->BRAM_FIFO36_DIADIU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_R.BRAM_IMUX8_1->BRAM_RAMB18_DIADI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_1" }, "BRAM_R.BRAM_IMUX8_2->BRAM_FIFO36_WEAU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_R.BRAM_IMUX8_2->BRAM_RAMB18_WEA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_2" }, "BRAM_R.BRAM_IMUX8_3->BRAM_R_IMUX_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_3" }, "BRAM_R.BRAM_IMUX8_4->BRAM_FIFO36_DIADIU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_R.BRAM_IMUX8_4->BRAM_RAMB18_DIADI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX8_4" }, "BRAM_R.BRAM_IMUX9_1->BRAM_R_IMUX_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_1" }, "BRAM_R.BRAM_IMUX9_2->BRAM_FIFO36_WEAU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_WEAU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_R.BRAM_IMUX9_2->BRAM_RAMB18_WEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_WEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_2" }, "BRAM_R.BRAM_IMUX9_3->BRAM_R_IMUX_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_R_IMUX_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_3" }, "BRAM_R.BRAM_IMUX9_4->BRAM_FIFO36_DIADIU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_FIFO36_DIADIU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_R.BRAM_IMUX9_4->BRAM_RAMB18_DIADI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_RAMB18_DIADI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_IMUX9_4" }, "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO18_ADDRATIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO18_ADDRATIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_FIFO36_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO36_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_RAMB18_ADDRATIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_RAMB18_ADDRATIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRARDADDRL15->>BRAM_UTURN_ADDRARDADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRARDADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_IMUX_R_ADDRARDADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO18_ADDRBTIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO18_ADDRBTIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_FIFO36_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_FIFO36_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_RAMB18_ADDRBTIEHIGH1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "dst_wire": "BRAM_RAMB18_ADDRBTIEHIGH1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.046", + "0.069", + "0.084" + ], + "in_cap": "0.000", + "res": "615.157125" + }, "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15" }, "BRAM_R.BRAM_IMUX_R_ADDRBWRADDRL15->>BRAM_UTURN_ADDRBWRADDRL15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "BRAM_UTURN_ADDRBWRADDRL15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "BRAM_IMUX_R_ADDRBWRADDRL15" }, "BRAM_R.BRAM_RAMB18_DOADO0->BRAM_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO0" }, "BRAM_R.BRAM_RAMB18_DOADO1->BRAM_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO1" }, "BRAM_R.BRAM_RAMB18_DOADO10->BRAM_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO10" }, "BRAM_R.BRAM_RAMB18_DOADO11->BRAM_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO11" }, "BRAM_R.BRAM_RAMB18_DOADO12->BRAM_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO12" }, "BRAM_R.BRAM_RAMB18_DOADO13->BRAM_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO13" }, "BRAM_R.BRAM_RAMB18_DOADO14->BRAM_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO14" }, "BRAM_R.BRAM_RAMB18_DOADO15->BRAM_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO15" }, "BRAM_R.BRAM_RAMB18_DOADO2->BRAM_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO2" }, "BRAM_R.BRAM_RAMB18_DOADO3->BRAM_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO3" }, "BRAM_R.BRAM_RAMB18_DOADO4->BRAM_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO4" }, "BRAM_R.BRAM_RAMB18_DOADO5->BRAM_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO5" }, "BRAM_R.BRAM_RAMB18_DOADO6->BRAM_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO6" }, "BRAM_R.BRAM_RAMB18_DOADO7->BRAM_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO7" }, "BRAM_R.BRAM_RAMB18_DOADO8->BRAM_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO8" }, "BRAM_R.BRAM_RAMB18_DOADO9->BRAM_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOADO9" }, "BRAM_R.BRAM_RAMB18_DOBDO0->BRAM_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO0" }, "BRAM_R.BRAM_RAMB18_DOBDO1->BRAM_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO1" }, "BRAM_R.BRAM_RAMB18_DOBDO10->BRAM_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO10" }, "BRAM_R.BRAM_RAMB18_DOBDO11->BRAM_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO11" }, "BRAM_R.BRAM_RAMB18_DOBDO12->BRAM_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO12" }, "BRAM_R.BRAM_RAMB18_DOBDO13->BRAM_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO13" }, "BRAM_R.BRAM_RAMB18_DOBDO14->BRAM_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO14" }, "BRAM_R.BRAM_RAMB18_DOBDO15->BRAM_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO15" }, "BRAM_R.BRAM_RAMB18_DOBDO2->BRAM_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO2" }, "BRAM_R.BRAM_RAMB18_DOBDO3->BRAM_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO3" }, "BRAM_R.BRAM_RAMB18_DOBDO4->BRAM_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO4" }, "BRAM_R.BRAM_RAMB18_DOBDO5->BRAM_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO5" }, "BRAM_R.BRAM_RAMB18_DOBDO6->BRAM_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO6" }, "BRAM_R.BRAM_RAMB18_DOBDO7->BRAM_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO7" }, "BRAM_R.BRAM_RAMB18_DOBDO8->BRAM_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO8" }, "BRAM_R.BRAM_RAMB18_DOBDO9->BRAM_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOBDO9" }, "BRAM_R.BRAM_RAMB18_DOPADOP0->BRAM_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPADOP0" }, "BRAM_R.BRAM_RAMB18_DOPADOP1->BRAM_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPADOP1" }, "BRAM_R.BRAM_RAMB18_DOPBDOP0->BRAM_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPBDOP0" }, "BRAM_R.BRAM_RAMB18_DOPBDOP1->BRAM_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_RAMB18_DOPBDOP1" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL0->BRAM_ADDRARDADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL0" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL1->BRAM_ADDRARDADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL1" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL10->BRAM_ADDRARDADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL10" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL11->BRAM_ADDRARDADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL11" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL12->BRAM_ADDRARDADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL12" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL13->BRAM_ADDRARDADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL13" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL14->BRAM_ADDRARDADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL14" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL2->BRAM_ADDRARDADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL2" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL3->BRAM_ADDRARDADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL3" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL4->BRAM_ADDRARDADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL4" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL5->BRAM_ADDRARDADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL5" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL6->BRAM_ADDRARDADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL6" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL7->BRAM_ADDRARDADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL7" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL8->BRAM_ADDRARDADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL8" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRL9->BRAM_ADDRARDADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRL9" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU0->BRAM_ADDRARDADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU0" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU1->BRAM_ADDRARDADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU1" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU10->BRAM_ADDRARDADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU10" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU11->BRAM_ADDRARDADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU11" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU12->BRAM_ADDRARDADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU12" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU13->BRAM_ADDRARDADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU13" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU14->BRAM_ADDRARDADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU14" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU2->BRAM_ADDRARDADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU2" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU3->BRAM_ADDRARDADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU3" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU4->BRAM_ADDRARDADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU4" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU5->BRAM_ADDRARDADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU5" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU6->BRAM_ADDRARDADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU6" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU7->BRAM_ADDRARDADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU7" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU8->BRAM_ADDRARDADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU8" }, "BRAM_R.BRAM_R_IMUX_ADDRARDADDRU9->BRAM_ADDRARDADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRARDADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRARDADDRU9" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL0->BRAM_ADDRBWRADDRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL0" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL1->BRAM_ADDRBWRADDRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL1" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL10->BRAM_ADDRBWRADDRL10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL10" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL11->BRAM_ADDRBWRADDRL11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL11" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL12->BRAM_ADDRBWRADDRL12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL12" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL13->BRAM_ADDRBWRADDRL13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL13" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL14->BRAM_ADDRBWRADDRL14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL14" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL2->BRAM_ADDRBWRADDRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL2" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL3->BRAM_ADDRBWRADDRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL3" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL4->BRAM_ADDRBWRADDRL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL4" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL5->BRAM_ADDRBWRADDRL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL5" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL6->BRAM_ADDRBWRADDRL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL6" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL7->BRAM_ADDRBWRADDRL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL7" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL8->BRAM_ADDRBWRADDRL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL8" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRL9->BRAM_ADDRBWRADDRL9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRL9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRL9" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU0->BRAM_ADDRBWRADDRU0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU0" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU1->BRAM_ADDRBWRADDRU1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU1" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU10->BRAM_ADDRBWRADDRU10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU10" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU11->BRAM_ADDRBWRADDRU11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU11" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU12->BRAM_ADDRBWRADDRU12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU12" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU13->BRAM_ADDRBWRADDRU13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU13" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU14->BRAM_ADDRBWRADDRU14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU14" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU2->BRAM_ADDRBWRADDRU2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU2" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU3->BRAM_ADDRBWRADDRU3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU3" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU4->BRAM_ADDRBWRADDRU4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU4" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU5->BRAM_ADDRBWRADDRU5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU5" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU6->BRAM_ADDRBWRADDRU6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU6" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU7->BRAM_ADDRBWRADDRU7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU7" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU8->BRAM_ADDRBWRADDRU8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU8" }, "BRAM_R.BRAM_R_IMUX_ADDRBWRADDRU9->BRAM_ADDRBWRADDRU9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRAM_ADDRBWRADDRU9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRAM_R_IMUX_ADDRBWRADDRU9" } }, @@ -6824,164 +19718,1586 @@ "name": "X0Y0", "prefix": "RAMB18", "site_pins": { - "ADDRARDADDR0": "BRAM_FIFO18_ADDRARDADDR0", - "ADDRARDADDR1": "BRAM_FIFO18_ADDRARDADDR1", - "ADDRARDADDR10": "BRAM_FIFO18_ADDRARDADDR10", - "ADDRARDADDR11": "BRAM_FIFO18_ADDRARDADDR11", - "ADDRARDADDR12": "BRAM_FIFO18_ADDRARDADDR12", - "ADDRARDADDR13": "BRAM_FIFO18_ADDRARDADDR13", - "ADDRARDADDR2": "BRAM_FIFO18_ADDRARDADDR2", - "ADDRARDADDR3": "BRAM_FIFO18_ADDRARDADDR3", - "ADDRARDADDR4": "BRAM_FIFO18_ADDRARDADDR4", - "ADDRARDADDR5": "BRAM_FIFO18_ADDRARDADDR5", - "ADDRARDADDR6": "BRAM_FIFO18_ADDRARDADDR6", - "ADDRARDADDR7": "BRAM_FIFO18_ADDRARDADDR7", - "ADDRARDADDR8": "BRAM_FIFO18_ADDRARDADDR8", - "ADDRARDADDR9": "BRAM_FIFO18_ADDRARDADDR9", - "ADDRATIEHIGH0": "BRAM_FIFO18_ADDRATIEHIGH0", - "ADDRATIEHIGH1": "BRAM_FIFO18_ADDRATIEHIGH1", - "ADDRBTIEHIGH0": "BRAM_FIFO18_ADDRBTIEHIGH0", - "ADDRBTIEHIGH1": "BRAM_FIFO18_ADDRBTIEHIGH1", - "ADDRBWRADDR0": "BRAM_FIFO18_ADDRBWRADDR0", - "ADDRBWRADDR1": "BRAM_FIFO18_ADDRBWRADDR1", - "ADDRBWRADDR10": "BRAM_FIFO18_ADDRBWRADDR10", - "ADDRBWRADDR11": "BRAM_FIFO18_ADDRBWRADDR11", - "ADDRBWRADDR12": "BRAM_FIFO18_ADDRBWRADDR12", - "ADDRBWRADDR13": "BRAM_FIFO18_ADDRBWRADDR13", - "ADDRBWRADDR2": "BRAM_FIFO18_ADDRBWRADDR2", - "ADDRBWRADDR3": "BRAM_FIFO18_ADDRBWRADDR3", - "ADDRBWRADDR4": "BRAM_FIFO18_ADDRBWRADDR4", - "ADDRBWRADDR5": "BRAM_FIFO18_ADDRBWRADDR5", - "ADDRBWRADDR6": "BRAM_FIFO18_ADDRBWRADDR6", - "ADDRBWRADDR7": "BRAM_FIFO18_ADDRBWRADDR7", - "ADDRBWRADDR8": "BRAM_FIFO18_ADDRBWRADDR8", - "ADDRBWRADDR9": "BRAM_FIFO18_ADDRBWRADDR9", - "ALMOSTEMPTY": "BRAM_FIFO18_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_FIFO18_ALMOSTFULL", - "DIADI0": "BRAM_FIFO18_DIADI0", - "DIADI1": "BRAM_FIFO18_DIADI1", - "DIADI10": "BRAM_FIFO18_DIADI10", - "DIADI11": "BRAM_FIFO18_DIADI11", - "DIADI12": "BRAM_FIFO18_DIADI12", - "DIADI13": "BRAM_FIFO18_DIADI13", - "DIADI14": "BRAM_FIFO18_DIADI14", - "DIADI15": "BRAM_FIFO18_DIADI15", - "DIADI2": "BRAM_FIFO18_DIADI2", - "DIADI3": "BRAM_FIFO18_DIADI3", - "DIADI4": "BRAM_FIFO18_DIADI4", - "DIADI5": "BRAM_FIFO18_DIADI5", - "DIADI6": "BRAM_FIFO18_DIADI6", - "DIADI7": "BRAM_FIFO18_DIADI7", - "DIADI8": "BRAM_FIFO18_DIADI8", - "DIADI9": "BRAM_FIFO18_DIADI9", - "DIBDI0": "BRAM_FIFO18_DIBDI0", - "DIBDI1": "BRAM_FIFO18_DIBDI1", - "DIBDI10": "BRAM_FIFO18_DIBDI10", - "DIBDI11": "BRAM_FIFO18_DIBDI11", - "DIBDI12": "BRAM_FIFO18_DIBDI12", - "DIBDI13": "BRAM_FIFO18_DIBDI13", - "DIBDI14": "BRAM_FIFO18_DIBDI14", - "DIBDI15": "BRAM_FIFO18_DIBDI15", - "DIBDI2": "BRAM_FIFO18_DIBDI2", - "DIBDI3": "BRAM_FIFO18_DIBDI3", - "DIBDI4": "BRAM_FIFO18_DIBDI4", - "DIBDI5": "BRAM_FIFO18_DIBDI5", - "DIBDI6": "BRAM_FIFO18_DIBDI6", - "DIBDI7": "BRAM_FIFO18_DIBDI7", - "DIBDI8": "BRAM_FIFO18_DIBDI8", - "DIBDI9": "BRAM_FIFO18_DIBDI9", - "DIPADIP0": "BRAM_FIFO18_DIPADIP0", - "DIPADIP1": "BRAM_FIFO18_DIPADIP1", - "DIPBDIP0": "BRAM_FIFO18_DIPBDIP0", - "DIPBDIP1": "BRAM_FIFO18_DIPBDIP1", - "DO0": "BRAM_FIFO18_DOADO0", - "DO1": "BRAM_FIFO18_DOADO1", - "DO10": "BRAM_FIFO18_DOADO10", - "DO11": "BRAM_FIFO18_DOADO11", - "DO12": "BRAM_FIFO18_DOADO12", - "DO13": "BRAM_FIFO18_DOADO13", - "DO14": "BRAM_FIFO18_DOADO14", - "DO15": "BRAM_FIFO18_DOADO15", - "DO16": "BRAM_FIFO18_DOBDO0", - "DO17": "BRAM_FIFO18_DOBDO1", - "DO18": "BRAM_FIFO18_DOBDO2", - "DO19": "BRAM_FIFO18_DOBDO3", - "DO2": "BRAM_FIFO18_DOADO2", - "DO20": "BRAM_FIFO18_DOBDO4", - "DO21": "BRAM_FIFO18_DOBDO5", - "DO22": "BRAM_FIFO18_DOBDO6", - "DO23": "BRAM_FIFO18_DOBDO7", - "DO24": "BRAM_FIFO18_DOBDO8", - "DO25": "BRAM_FIFO18_DOBDO9", - "DO26": "BRAM_FIFO18_DOBDO10", - "DO27": "BRAM_FIFO18_DOBDO11", - "DO28": "BRAM_FIFO18_DOBDO12", - "DO29": "BRAM_FIFO18_DOBDO13", - "DO3": "BRAM_FIFO18_DOADO3", - "DO30": "BRAM_FIFO18_DOBDO14", - "DO31": "BRAM_FIFO18_DOBDO15", - "DO4": "BRAM_FIFO18_DOADO4", - "DO5": "BRAM_FIFO18_DOADO5", - "DO6": "BRAM_FIFO18_DOADO6", - "DO7": "BRAM_FIFO18_DOADO7", - "DO8": "BRAM_FIFO18_DOADO8", - "DO9": "BRAM_FIFO18_DOADO9", - "DOP0": "BRAM_FIFO18_DOPADOP0", - "DOP1": "BRAM_FIFO18_DOPADOP1", - "DOP2": "BRAM_FIFO18_DOPBDOP0", - "DOP3": "BRAM_FIFO18_DOPBDOP1", - "EMPTY": "BRAM_FIFO18_EMPTY", - "FULL": "BRAM_FIFO18_FULL", - "RDCLK": "BRAM_FIFO18_CLKARDCLK", - "RDCOUNT0": "BRAM_FIFO18_RDCOUNT0", - "RDCOUNT1": "BRAM_FIFO18_RDCOUNT1", - "RDCOUNT10": "BRAM_FIFO18_RDCOUNT10", - "RDCOUNT11": "BRAM_FIFO18_RDCOUNT11", - "RDCOUNT2": "BRAM_FIFO18_RDCOUNT2", - "RDCOUNT3": "BRAM_FIFO18_RDCOUNT3", - "RDCOUNT4": "BRAM_FIFO18_RDCOUNT4", - "RDCOUNT5": "BRAM_FIFO18_RDCOUNT5", - "RDCOUNT6": "BRAM_FIFO18_RDCOUNT6", - "RDCOUNT7": "BRAM_FIFO18_RDCOUNT7", - "RDCOUNT8": "BRAM_FIFO18_RDCOUNT8", - "RDCOUNT9": "BRAM_FIFO18_RDCOUNT9", - "RDEN": "BRAM_FIFO18_ENARDEN", - "RDERR": "BRAM_FIFO18_RDERR", - "RDRCLK": "BRAM_FIFO18_REGCLKARDRCLK", - "REGCE": "BRAM_FIFO18_REGCEAREGCE", - "REGCEB": "BRAM_FIFO18_REGCEB", - "REGCLKB": "BRAM_FIFO18_REGCLKB", - "RST": "BRAM_FIFO18_RSTRAMARSTRAM", - "RSTRAMB": "BRAM_FIFO18_RSTRAMB", - "RSTREG": "BRAM_FIFO18_RSTREGARSTREG", - "RSTREGB": "BRAM_FIFO18_RSTREGB", - "WEA0": "BRAM_FIFO18_WEA0", - "WEA1": "BRAM_FIFO18_WEA1", - "WEA2": "BRAM_FIFO18_WEA2", - "WEA3": "BRAM_FIFO18_WEA3", - "WEBWE0": "BRAM_FIFO18_WEBWE0", - "WEBWE1": "BRAM_FIFO18_WEBWE1", - "WEBWE2": "BRAM_FIFO18_WEBWE2", - "WEBWE3": "BRAM_FIFO18_WEBWE3", - "WEBWE4": "BRAM_FIFO18_WEBWE4", - "WEBWE5": "BRAM_FIFO18_WEBWE5", - "WEBWE6": "BRAM_FIFO18_WEBWE6", - "WEBWE7": "BRAM_FIFO18_WEBWE7", - "WRCLK": "BRAM_FIFO18_CLKBWRCLK", - "WRCOUNT0": "BRAM_FIFO18_WRCOUNT0", - "WRCOUNT1": "BRAM_FIFO18_WRCOUNT1", - "WRCOUNT10": "BRAM_FIFO18_WRCOUNT10", - "WRCOUNT11": "BRAM_FIFO18_WRCOUNT11", - "WRCOUNT2": "BRAM_FIFO18_WRCOUNT2", - "WRCOUNT3": "BRAM_FIFO18_WRCOUNT3", - "WRCOUNT4": "BRAM_FIFO18_WRCOUNT4", - "WRCOUNT5": "BRAM_FIFO18_WRCOUNT5", - "WRCOUNT6": "BRAM_FIFO18_WRCOUNT6", - "WRCOUNT7": "BRAM_FIFO18_WRCOUNT7", - "WRCOUNT8": "BRAM_FIFO18_WRCOUNT8", - "WRCOUNT9": "BRAM_FIFO18_WRCOUNT9", - "WREN": "BRAM_FIFO18_ENBWREN", - "WRERR": "BRAM_FIFO18_WRERR" + "ADDRARDADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR0" + }, + "ADDRARDADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR1" + }, + "ADDRARDADDR10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR10" + }, + "ADDRARDADDR11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR11" + }, + "ADDRARDADDR12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR12" + }, + "ADDRARDADDR13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR13" + }, + "ADDRARDADDR2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR2" + }, + "ADDRARDADDR3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR3" + }, + "ADDRARDADDR4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR4" + }, + "ADDRARDADDR5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR5" + }, + "ADDRARDADDR6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR6" + }, + "ADDRARDADDR7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR7" + }, + "ADDRARDADDR8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR8" + }, + "ADDRARDADDR9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRARDADDR9" + }, + "ADDRATIEHIGH0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRATIEHIGH0" + }, + "ADDRATIEHIGH1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRATIEHIGH1" + }, + "ADDRBTIEHIGH0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBTIEHIGH0" + }, + "ADDRBTIEHIGH1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBTIEHIGH1" + }, + "ADDRBWRADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR0" + }, + "ADDRBWRADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR1" + }, + "ADDRBWRADDR10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR10" + }, + "ADDRBWRADDR11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR11" + }, + "ADDRBWRADDR12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR12" + }, + "ADDRBWRADDR13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR13" + }, + "ADDRBWRADDR2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR2" + }, + "ADDRBWRADDR3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR3" + }, + "ADDRBWRADDR4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR4" + }, + "ADDRBWRADDR5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR5" + }, + "ADDRBWRADDR6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR6" + }, + "ADDRBWRADDR7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR7" + }, + "ADDRBWRADDR8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR8" + }, + "ADDRBWRADDR9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_ADDRBWRADDR9" + }, + "ALMOSTEMPTY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "855.9375", + "wire": "BRAM_FIFO18_ALMOSTEMPTY" + }, + "ALMOSTFULL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "855.9375", + "wire": "BRAM_FIFO18_ALMOSTFULL" + }, + "DIADI0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI0" + }, + "DIADI1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI1" + }, + "DIADI10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI10" + }, + "DIADI11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI11" + }, + "DIADI12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI12" + }, + "DIADI13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI13" + }, + "DIADI14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI14" + }, + "DIADI15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI15" + }, + "DIADI2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI2" + }, + "DIADI3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI3" + }, + "DIADI4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI4" + }, + "DIADI5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI5" + }, + "DIADI6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI6" + }, + "DIADI7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO18_DIADI7" + }, + "DIADI8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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"BRAM_RAMB18_ADDRBWRADDR9", - "ALMOSTEMPTY": "BRAM_RAMB18_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_RAMB18_ALMOSTFULL", - "CLKARDCLK": "BRAM_RAMB18_CLKARDCLK", - "CLKBWRCLK": "BRAM_RAMB18_CLKBWRCLK", - "DIADI0": "BRAM_RAMB18_DIADI0", - "DIADI1": "BRAM_RAMB18_DIADI1", - "DIADI10": "BRAM_RAMB18_DIADI10", - "DIADI11": "BRAM_RAMB18_DIADI11", - "DIADI12": "BRAM_RAMB18_DIADI12", - "DIADI13": "BRAM_RAMB18_DIADI13", - "DIADI14": "BRAM_RAMB18_DIADI14", - "DIADI15": "BRAM_RAMB18_DIADI15", - "DIADI2": "BRAM_RAMB18_DIADI2", - "DIADI3": "BRAM_RAMB18_DIADI3", - "DIADI4": "BRAM_RAMB18_DIADI4", - "DIADI5": "BRAM_RAMB18_DIADI5", - "DIADI6": "BRAM_RAMB18_DIADI6", - "DIADI7": "BRAM_RAMB18_DIADI7", - "DIADI8": "BRAM_RAMB18_DIADI8", - "DIADI9": "BRAM_RAMB18_DIADI9", - "DIBDI0": "BRAM_RAMB18_DIBDI0", - "DIBDI1": "BRAM_RAMB18_DIBDI1", - "DIBDI10": "BRAM_RAMB18_DIBDI10", - "DIBDI11": "BRAM_RAMB18_DIBDI11", - "DIBDI12": "BRAM_RAMB18_DIBDI12", - "DIBDI13": "BRAM_RAMB18_DIBDI13", - "DIBDI14": "BRAM_RAMB18_DIBDI14", - "DIBDI15": "BRAM_RAMB18_DIBDI15", - "DIBDI2": "BRAM_RAMB18_DIBDI2", - "DIBDI3": "BRAM_RAMB18_DIBDI3", - "DIBDI4": "BRAM_RAMB18_DIBDI4", - "DIBDI5": "BRAM_RAMB18_DIBDI5", - "DIBDI6": "BRAM_RAMB18_DIBDI6", - "DIBDI7": "BRAM_RAMB18_DIBDI7", - "DIBDI8": "BRAM_RAMB18_DIBDI8", - "DIBDI9": "BRAM_RAMB18_DIBDI9", - "DIPADIP0": "BRAM_RAMB18_DIPADIP0", - "DIPADIP1": "BRAM_RAMB18_DIPADIP1", - "DIPBDIP0": "BRAM_RAMB18_DIPBDIP0", - "DIPBDIP1": "BRAM_RAMB18_DIPBDIP1", - "DOADO0": "BRAM_RAMB18_DOADO0", - "DOADO1": "BRAM_RAMB18_DOADO1", - "DOADO10": "BRAM_RAMB18_DOADO10", - "DOADO11": "BRAM_RAMB18_DOADO11", - "DOADO12": "BRAM_RAMB18_DOADO12", - "DOADO13": "BRAM_RAMB18_DOADO13", - "DOADO14": "BRAM_RAMB18_DOADO14", - "DOADO15": "BRAM_RAMB18_DOADO15", - "DOADO2": "BRAM_RAMB18_DOADO2", - "DOADO3": "BRAM_RAMB18_DOADO3", - "DOADO4": "BRAM_RAMB18_DOADO4", - "DOADO5": "BRAM_RAMB18_DOADO5", - "DOADO6": "BRAM_RAMB18_DOADO6", - "DOADO7": "BRAM_RAMB18_DOADO7", - "DOADO8": "BRAM_RAMB18_DOADO8", - "DOADO9": "BRAM_RAMB18_DOADO9", - "DOBDO0": "BRAM_RAMB18_DOBDO0", - "DOBDO1": "BRAM_RAMB18_DOBDO1", - "DOBDO10": "BRAM_RAMB18_DOBDO10", - "DOBDO11": "BRAM_RAMB18_DOBDO11", - "DOBDO12": "BRAM_RAMB18_DOBDO12", - "DOBDO13": "BRAM_RAMB18_DOBDO13", - "DOBDO14": "BRAM_RAMB18_DOBDO14", - "DOBDO15": "BRAM_RAMB18_DOBDO15", - "DOBDO2": "BRAM_RAMB18_DOBDO2", - "DOBDO3": "BRAM_RAMB18_DOBDO3", - "DOBDO4": "BRAM_RAMB18_DOBDO4", - "DOBDO5": "BRAM_RAMB18_DOBDO5", - "DOBDO6": "BRAM_RAMB18_DOBDO6", - "DOBDO7": "BRAM_RAMB18_DOBDO7", - "DOBDO8": "BRAM_RAMB18_DOBDO8", - "DOBDO9": "BRAM_RAMB18_DOBDO9", - "DOPADOP0": "BRAM_RAMB18_DOPADOP0", - "DOPADOP1": "BRAM_RAMB18_DOPADOP1", - "DOPBDOP0": "BRAM_RAMB18_DOPBDOP0", - "DOPBDOP1": "BRAM_RAMB18_DOPBDOP1", - "EMPTY": "BRAM_RAMB18_EMPTY", - "ENARDEN": "BRAM_RAMB18_ENARDEN", - "ENBWREN": "BRAM_RAMB18_ENBWREN", - "FULL": "BRAM_RAMB18_FULL", - "RDCOUNT0": "BRAM_RAMB18_RDCOUNT0", - "RDCOUNT1": "BRAM_RAMB18_RDCOUNT1", - "RDCOUNT10": "BRAM_RAMB18_RDCOUNT10", - "RDCOUNT11": "BRAM_RAMB18_RDCOUNT11", - "RDCOUNT2": "BRAM_RAMB18_RDCOUNT2", - "RDCOUNT3": "BRAM_RAMB18_RDCOUNT3", - "RDCOUNT4": "BRAM_RAMB18_RDCOUNT4", - "RDCOUNT5": "BRAM_RAMB18_RDCOUNT5", - "RDCOUNT6": "BRAM_RAMB18_RDCOUNT6", - "RDCOUNT7": "BRAM_RAMB18_RDCOUNT7", - "RDCOUNT8": "BRAM_RAMB18_RDCOUNT8", - "RDCOUNT9": "BRAM_RAMB18_RDCOUNT9", - "RDERR": "BRAM_RAMB18_RDERR", - "REGCEAREGCE": "BRAM_RAMB18_REGCEAREGCE", - "REGCEB": "BRAM_RAMB18_REGCEB", - "REGCLKARDRCLK": "BRAM_RAMB18_REGCLKARDRCLK", - "REGCLKB": "BRAM_RAMB18_REGCLKB", - "RSTRAMARSTRAM": "BRAM_RAMB18_RSTRAMARSTRAM", - "RSTRAMB": "BRAM_RAMB18_RSTRAMB", - "RSTREGARSTREG": "BRAM_RAMB18_RSTREGARSTREG", - "RSTREGB": "BRAM_RAMB18_RSTREGB", - "WEA0": "BRAM_RAMB18_WEA0", - "WEA1": "BRAM_RAMB18_WEA1", - "WEA2": "BRAM_RAMB18_WEA2", - "WEA3": "BRAM_RAMB18_WEA3", - "WEBWE0": "BRAM_RAMB18_WEBWE0", - "WEBWE1": "BRAM_RAMB18_WEBWE1", - "WEBWE2": "BRAM_RAMB18_WEBWE2", - "WEBWE3": "BRAM_RAMB18_WEBWE3", - "WEBWE4": "BRAM_RAMB18_WEBWE4", - "WEBWE5": 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"ADDRARDADDRL0": "BRAM_FIFO36_ADDRARDADDRL0", - "ADDRARDADDRL1": "BRAM_FIFO36_ADDRARDADDRL1", - "ADDRARDADDRL10": "BRAM_FIFO36_ADDRARDADDRL10", - "ADDRARDADDRL11": "BRAM_FIFO36_ADDRARDADDRL11", - "ADDRARDADDRL12": "BRAM_FIFO36_ADDRARDADDRL12", - "ADDRARDADDRL13": "BRAM_FIFO36_ADDRARDADDRL13", - "ADDRARDADDRL14": "BRAM_FIFO36_ADDRARDADDRL14", - "ADDRARDADDRL15": "BRAM_FIFO36_ADDRARDADDRL15", - "ADDRARDADDRL2": "BRAM_FIFO36_ADDRARDADDRL2", - "ADDRARDADDRL3": "BRAM_FIFO36_ADDRARDADDRL3", - "ADDRARDADDRL4": "BRAM_FIFO36_ADDRARDADDRL4", - "ADDRARDADDRL5": "BRAM_FIFO36_ADDRARDADDRL5", - "ADDRARDADDRL6": "BRAM_FIFO36_ADDRARDADDRL6", - "ADDRARDADDRL7": "BRAM_FIFO36_ADDRARDADDRL7", - "ADDRARDADDRL8": "BRAM_FIFO36_ADDRARDADDRL8", - "ADDRARDADDRL9": "BRAM_FIFO36_ADDRARDADDRL9", - "ADDRARDADDRU0": "BRAM_FIFO36_ADDRARDADDRU0", - "ADDRARDADDRU1": "BRAM_FIFO36_ADDRARDADDRU1", - "ADDRARDADDRU10": "BRAM_FIFO36_ADDRARDADDRU10", - "ADDRARDADDRU11": "BRAM_FIFO36_ADDRARDADDRU11", - "ADDRARDADDRU12": "BRAM_FIFO36_ADDRARDADDRU12", - "ADDRARDADDRU13": "BRAM_FIFO36_ADDRARDADDRU13", - "ADDRARDADDRU14": "BRAM_FIFO36_ADDRARDADDRU14", - "ADDRARDADDRU2": "BRAM_FIFO36_ADDRARDADDRU2", - "ADDRARDADDRU3": "BRAM_FIFO36_ADDRARDADDRU3", - "ADDRARDADDRU4": "BRAM_FIFO36_ADDRARDADDRU4", - "ADDRARDADDRU5": "BRAM_FIFO36_ADDRARDADDRU5", - "ADDRARDADDRU6": "BRAM_FIFO36_ADDRARDADDRU6", - "ADDRARDADDRU7": "BRAM_FIFO36_ADDRARDADDRU7", - "ADDRARDADDRU8": "BRAM_FIFO36_ADDRARDADDRU8", - "ADDRARDADDRU9": "BRAM_FIFO36_ADDRARDADDRU9", - "ADDRBWRADDRL0": "BRAM_FIFO36_ADDRBWRADDRL0", - "ADDRBWRADDRL1": "BRAM_FIFO36_ADDRBWRADDRL1", - "ADDRBWRADDRL10": "BRAM_FIFO36_ADDRBWRADDRL10", - "ADDRBWRADDRL11": "BRAM_FIFO36_ADDRBWRADDRL11", - "ADDRBWRADDRL12": "BRAM_FIFO36_ADDRBWRADDRL12", - "ADDRBWRADDRL13": "BRAM_FIFO36_ADDRBWRADDRL13", - "ADDRBWRADDRL14": "BRAM_FIFO36_ADDRBWRADDRL14", - "ADDRBWRADDRL15": "BRAM_FIFO36_ADDRBWRADDRL15", - "ADDRBWRADDRL2": "BRAM_FIFO36_ADDRBWRADDRL2", - "ADDRBWRADDRL3": "BRAM_FIFO36_ADDRBWRADDRL3", - "ADDRBWRADDRL4": "BRAM_FIFO36_ADDRBWRADDRL4", - "ADDRBWRADDRL5": "BRAM_FIFO36_ADDRBWRADDRL5", - "ADDRBWRADDRL6": "BRAM_FIFO36_ADDRBWRADDRL6", - "ADDRBWRADDRL7": "BRAM_FIFO36_ADDRBWRADDRL7", - "ADDRBWRADDRL8": "BRAM_FIFO36_ADDRBWRADDRL8", - "ADDRBWRADDRL9": "BRAM_FIFO36_ADDRBWRADDRL9", - "ADDRBWRADDRU0": "BRAM_FIFO36_ADDRBWRADDRU0", - "ADDRBWRADDRU1": "BRAM_FIFO36_ADDRBWRADDRU1", - "ADDRBWRADDRU10": "BRAM_FIFO36_ADDRBWRADDRU10", - "ADDRBWRADDRU11": "BRAM_FIFO36_ADDRBWRADDRU11", - "ADDRBWRADDRU12": "BRAM_FIFO36_ADDRBWRADDRU12", - "ADDRBWRADDRU13": "BRAM_FIFO36_ADDRBWRADDRU13", - "ADDRBWRADDRU14": "BRAM_FIFO36_ADDRBWRADDRU14", - "ADDRBWRADDRU2": "BRAM_FIFO36_ADDRBWRADDRU2", - "ADDRBWRADDRU3": "BRAM_FIFO36_ADDRBWRADDRU3", - "ADDRBWRADDRU4": "BRAM_FIFO36_ADDRBWRADDRU4", - "ADDRBWRADDRU5": "BRAM_FIFO36_ADDRBWRADDRU5", - "ADDRBWRADDRU6": "BRAM_FIFO36_ADDRBWRADDRU6", - "ADDRBWRADDRU7": "BRAM_FIFO36_ADDRBWRADDRU7", - "ADDRBWRADDRU8": "BRAM_FIFO36_ADDRBWRADDRU8", - "ADDRBWRADDRU9": "BRAM_FIFO36_ADDRBWRADDRU9", - "ALMOSTEMPTY": "BRAM_FIFO36_ALMOSTEMPTY", - "ALMOSTFULL": "BRAM_FIFO36_ALMOSTFULL", - "CASCADEINA": "BRAM_FIFO36_CASCADEINB", - "CASCADEINB": "BRAM_FIFO36_CASCADEINA", - "CASCADEOUTA": "BRAM_FIFO36_CASCADEOUTB", - "CASCADEOUTB": "BRAM_FIFO36_CASCADEOUTA", - "CLKARDCLKL": "BRAM_FIFO36_CLKARDCLKL", - "CLKARDCLKU": "BRAM_FIFO36_CLKARDCLKU", - "CLKBWRCLKL": "BRAM_FIFO36_CLKBWRCLKL", - "CLKBWRCLKU": "BRAM_FIFO36_CLKBWRCLKU", - "DBITERR": "BRAM_FIFO36_DBITERR", - "DIADI0": "BRAM_FIFO36_DIADIL0", - "DIADI1": "BRAM_FIFO36_DIADIU0", - "DIADI10": "BRAM_FIFO36_DIADIL5", - "DIADI11": "BRAM_FIFO36_DIADIU5", - "DIADI12": "BRAM_FIFO36_DIADIL6", - "DIADI13": "BRAM_FIFO36_DIADIU6", - "DIADI14": "BRAM_FIFO36_DIADIL7", - "DIADI15": "BRAM_FIFO36_DIADIU7", - "DIADI16": "BRAM_FIFO36_DIADIL8", - "DIADI17": "BRAM_FIFO36_DIADIU8", - "DIADI18": "BRAM_FIFO36_DIADIL9", - "DIADI19": "BRAM_FIFO36_DIADIU9", - "DIADI2": "BRAM_FIFO36_DIADIL1", - "DIADI20": "BRAM_FIFO36_DIADIL10", - "DIADI21": "BRAM_FIFO36_DIADIU10", - "DIADI22": "BRAM_FIFO36_DIADIL11", - "DIADI23": "BRAM_FIFO36_DIADIU11", - "DIADI24": "BRAM_FIFO36_DIADIL12", - "DIADI25": "BRAM_FIFO36_DIADIU12", - "DIADI26": "BRAM_FIFO36_DIADIL13", - "DIADI27": "BRAM_FIFO36_DIADIU13", - "DIADI28": "BRAM_FIFO36_DIADIL14", - "DIADI29": "BRAM_FIFO36_DIADIU14", - "DIADI3": "BRAM_FIFO36_DIADIU1", - "DIADI30": "BRAM_FIFO36_DIADIL15", - "DIADI31": "BRAM_FIFO36_DIADIU15", - "DIADI4": "BRAM_FIFO36_DIADIL2", - "DIADI5": "BRAM_FIFO36_DIADIU2", - "DIADI6": "BRAM_FIFO36_DIADIL3", - "DIADI7": "BRAM_FIFO36_DIADIU3", - "DIADI8": "BRAM_FIFO36_DIADIL4", - "DIADI9": "BRAM_FIFO36_DIADIU4", - "DIBDI0": "BRAM_FIFO36_DIBDIL0", - "DIBDI1": "BRAM_FIFO36_DIBDIU0", - "DIBDI10": "BRAM_FIFO36_DIBDIL5", - "DIBDI11": "BRAM_FIFO36_DIBDIU5", - "DIBDI12": "BRAM_FIFO36_DIBDIL6", - "DIBDI13": "BRAM_FIFO36_DIBDIU6", - "DIBDI14": "BRAM_FIFO36_DIBDIL7", - "DIBDI15": "BRAM_FIFO36_DIBDIU7", - "DIBDI16": "BRAM_FIFO36_DIBDIL8", - "DIBDI17": "BRAM_FIFO36_DIBDIU8", - "DIBDI18": "BRAM_FIFO36_DIBDIL9", - "DIBDI19": "BRAM_FIFO36_DIBDIU9", - "DIBDI2": "BRAM_FIFO36_DIBDIL1", - "DIBDI20": "BRAM_FIFO36_DIBDIL10", - "DIBDI21": "BRAM_FIFO36_DIBDIU10", - "DIBDI22": "BRAM_FIFO36_DIBDIL11", - "DIBDI23": "BRAM_FIFO36_DIBDIU11", - "DIBDI24": "BRAM_FIFO36_DIBDIL12", - "DIBDI25": "BRAM_FIFO36_DIBDIU12", - "DIBDI26": "BRAM_FIFO36_DIBDIL13", - "DIBDI27": "BRAM_FIFO36_DIBDIU13", - "DIBDI28": "BRAM_FIFO36_DIBDIL14", - "DIBDI29": "BRAM_FIFO36_DIBDIU14", - "DIBDI3": "BRAM_FIFO36_DIBDIU1", - "DIBDI30": "BRAM_FIFO36_DIBDIL15", - "DIBDI31": "BRAM_FIFO36_DIBDIU15", - "DIBDI4": "BRAM_FIFO36_DIBDIL2", - "DIBDI5": "BRAM_FIFO36_DIBDIU2", - "DIBDI6": "BRAM_FIFO36_DIBDIL3", - "DIBDI7": "BRAM_FIFO36_DIBDIU3", - "DIBDI8": "BRAM_FIFO36_DIBDIL4", - "DIBDI9": "BRAM_FIFO36_DIBDIU4", - "DIPADIP0": "BRAM_FIFO36_DIPADIPL0", - "DIPADIP1": "BRAM_FIFO36_DIPADIPU0", - "DIPADIP2": "BRAM_FIFO36_DIPADIPL1", - "DIPADIP3": "BRAM_FIFO36_DIPADIPU1", - "DIPBDIP0": "BRAM_FIFO36_DIPBDIPL0", - "DIPBDIP1": "BRAM_FIFO36_DIPBDIPU0", - "DIPBDIP2": "BRAM_FIFO36_DIPBDIPL1", - "DIPBDIP3": "BRAM_FIFO36_DIPBDIPU1", - "DOADO0": "BRAM_FIFO36_DOADOL0", - "DOADO1": "BRAM_FIFO36_DOADOU0", - "DOADO10": "BRAM_FIFO36_DOADOL5", - "DOADO11": "BRAM_FIFO36_DOADOU5", - "DOADO12": "BRAM_FIFO36_DOADOL6", - "DOADO13": "BRAM_FIFO36_DOADOU6", - "DOADO14": "BRAM_FIFO36_DOADOL7", - "DOADO15": "BRAM_FIFO36_DOADOU7", - "DOADO16": "BRAM_FIFO36_DOADOL8", - "DOADO17": "BRAM_FIFO36_DOADOU8", - "DOADO18": "BRAM_FIFO36_DOADOL9", - "DOADO19": "BRAM_FIFO36_DOADOU9", - "DOADO2": "BRAM_FIFO36_DOADOL1", - "DOADO20": "BRAM_FIFO36_DOADOL10", - "DOADO21": "BRAM_FIFO36_DOADOU10", - "DOADO22": "BRAM_FIFO36_DOADOL11", - "DOADO23": "BRAM_FIFO36_DOADOU11", - "DOADO24": "BRAM_FIFO36_DOADOL12", - "DOADO25": "BRAM_FIFO36_DOADOU12", - "DOADO26": "BRAM_FIFO36_DOADOL13", - "DOADO27": "BRAM_FIFO36_DOADOU13", - "DOADO28": "BRAM_FIFO36_DOADOL14", - "DOADO29": "BRAM_FIFO36_DOADOU14", - "DOADO3": "BRAM_FIFO36_DOADOU1", - "DOADO30": "BRAM_FIFO36_DOADOL15", - "DOADO31": "BRAM_FIFO36_DOADOU15", - "DOADO4": "BRAM_FIFO36_DOADOL2", - "DOADO5": "BRAM_FIFO36_DOADOU2", - "DOADO6": "BRAM_FIFO36_DOADOL3", - "DOADO7": "BRAM_FIFO36_DOADOU3", - "DOADO8": "BRAM_FIFO36_DOADOL4", - "DOADO9": "BRAM_FIFO36_DOADOU4", - "DOBDO0": "BRAM_FIFO36_DOBDOL0", - "DOBDO1": "BRAM_FIFO36_DOBDOU0", - "DOBDO10": "BRAM_FIFO36_DOBDOL5", - "DOBDO11": "BRAM_FIFO36_DOBDOU5", - "DOBDO12": "BRAM_FIFO36_DOBDOL6", - "DOBDO13": "BRAM_FIFO36_DOBDOU6", - "DOBDO14": "BRAM_FIFO36_DOBDOL7", - "DOBDO15": "BRAM_FIFO36_DOBDOU7", - "DOBDO16": "BRAM_FIFO36_DOBDOL8", - "DOBDO17": "BRAM_FIFO36_DOBDOU8", - "DOBDO18": "BRAM_FIFO36_DOBDOL9", - "DOBDO19": "BRAM_FIFO36_DOBDOU9", - "DOBDO2": "BRAM_FIFO36_DOBDOL1", - "DOBDO20": "BRAM_FIFO36_DOBDOL10", - "DOBDO21": "BRAM_FIFO36_DOBDOU10", - "DOBDO22": "BRAM_FIFO36_DOBDOL11", - "DOBDO23": "BRAM_FIFO36_DOBDOU11", - "DOBDO24": "BRAM_FIFO36_DOBDOL12", - "DOBDO25": "BRAM_FIFO36_DOBDOU12", - "DOBDO26": "BRAM_FIFO36_DOBDOL13", - "DOBDO27": "BRAM_FIFO36_DOBDOU13", - "DOBDO28": "BRAM_FIFO36_DOBDOL14", - "DOBDO29": "BRAM_FIFO36_DOBDOU14", - "DOBDO3": "BRAM_FIFO36_DOBDOU1", - "DOBDO30": "BRAM_FIFO36_DOBDOL15", - "DOBDO31": "BRAM_FIFO36_DOBDOU15", - "DOBDO4": "BRAM_FIFO36_DOBDOL2", - "DOBDO5": "BRAM_FIFO36_DOBDOU2", - "DOBDO6": "BRAM_FIFO36_DOBDOL3", - "DOBDO7": "BRAM_FIFO36_DOBDOU3", - "DOBDO8": "BRAM_FIFO36_DOBDOL4", - "DOBDO9": "BRAM_FIFO36_DOBDOU4", - "DOPADOP0": "BRAM_FIFO36_DOPADOPL0", - "DOPADOP1": "BRAM_FIFO36_DOPADOPU0", - "DOPADOP2": "BRAM_FIFO36_DOPADOPL1", - "DOPADOP3": "BRAM_FIFO36_DOPADOPU1", - "DOPBDOP0": "BRAM_FIFO36_DOPBDOPL0", - "DOPBDOP1": "BRAM_FIFO36_DOPBDOPU0", - "DOPBDOP2": "BRAM_FIFO36_DOPBDOPL1", - "DOPBDOP3": "BRAM_FIFO36_DOPBDOPU1", - "ECCPARITY0": "BRAM_FIFO36_ECCPARITY0", - "ECCPARITY1": "BRAM_FIFO36_ECCPARITY1", - "ECCPARITY2": "BRAM_FIFO36_ECCPARITY2", - "ECCPARITY3": "BRAM_FIFO36_ECCPARITY3", - "ECCPARITY4": "BRAM_FIFO36_ECCPARITY4", - "ECCPARITY5": "BRAM_FIFO36_ECCPARITY5", - "ECCPARITY6": "BRAM_FIFO36_ECCPARITY6", - "ECCPARITY7": "BRAM_FIFO36_ECCPARITY7", - "EMPTY": "BRAM_FIFO36_EMPTY", - "ENARDENL": "BRAM_FIFO36_ENARDENL", - "ENARDENU": "BRAM_FIFO36_ENARDENU", - "ENBWRENL": "BRAM_FIFO36_ENBWRENL", - "ENBWRENU": "BRAM_FIFO36_ENBWRENU", - "FULL": "BRAM_FIFO36_FULL", - "INJECTDBITERR": "BRAM_FIFO36_INJECTDBITERR", - "INJECTSBITERR": "BRAM_FIFO36_INJECTSBITERR", - "RDCOUNT0": "BRAM_FIFO36_RDCOUNT0", - "RDCOUNT1": "BRAM_FIFO36_RDCOUNT1", - "RDCOUNT10": "BRAM_FIFO36_RDCOUNT10", - "RDCOUNT11": "BRAM_FIFO36_RDCOUNT11", - "RDCOUNT12": "BRAM_FIFO36_RDCOUNT12", - "RDCOUNT2": "BRAM_FIFO36_RDCOUNT2", - "RDCOUNT3": "BRAM_FIFO36_RDCOUNT3", - "RDCOUNT4": "BRAM_FIFO36_RDCOUNT4", - "RDCOUNT5": "BRAM_FIFO36_RDCOUNT5", - "RDCOUNT6": "BRAM_FIFO36_RDCOUNT6", - "RDCOUNT7": "BRAM_FIFO36_RDCOUNT7", - "RDCOUNT8": "BRAM_FIFO36_RDCOUNT8", - "RDCOUNT9": "BRAM_FIFO36_RDCOUNT9", - "RDERR": "BRAM_FIFO36_RDERR", - "REGCEAREGCEL": "BRAM_FIFO36_REGCEAREGCEL", - "REGCEAREGCEU": "BRAM_FIFO36_REGCEAREGCEU", - "REGCEBL": "BRAM_FIFO36_REGCEBL", - "REGCEBU": "BRAM_FIFO36_REGCEBU", - "REGCLKARDRCLKL": "BRAM_FIFO36_REGCLKARDRCLKL", - "REGCLKARDRCLKU": "BRAM_FIFO36_REGCLKARDRCLKU", - "REGCLKBL": "BRAM_FIFO36_REGCLKBL", - "REGCLKBU": "BRAM_FIFO36_REGCLKBU", - "RSTRAMARSTRAMLRST": "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "RSTRAMARSTRAMU": "BRAM_FIFO36_RSTRAMARSTRAMU", - "RSTRAMBL": "BRAM_FIFO36_RSTRAMBL", - "RSTRAMBU": "BRAM_FIFO36_RSTRAMBU", - "RSTREGARSTREGL": "BRAM_FIFO36_RSTREGARSTREGL", - "RSTREGARSTREGU": "BRAM_FIFO36_RSTREGARSTREGU", - "RSTREGBL": "BRAM_FIFO36_RSTREGBL", - "RSTREGBU": "BRAM_FIFO36_RSTREGBU", - "SBITERR": "BRAM_FIFO36_SBITERR", - "TSTBRAMRST": "BRAM_FIFO36_TSTBRAMRST", - "TSTCNT0": "BRAM_FIFO36_TSTCNT0", - "TSTCNT1": "BRAM_FIFO36_TSTCNT1", - "TSTCNT10": "BRAM_FIFO36_TSTCNT10", - "TSTCNT11": "BRAM_FIFO36_TSTCNT11", - "TSTCNT12": "BRAM_FIFO36_TSTCNT12", - "TSTCNT2": "BRAM_FIFO36_TSTCNT2", - "TSTCNT3": "BRAM_FIFO36_TSTCNT3", - "TSTCNT4": "BRAM_FIFO36_TSTCNT4", - "TSTCNT5": "BRAM_FIFO36_TSTCNT5", - "TSTCNT6": "BRAM_FIFO36_TSTCNT6", - "TSTCNT7": "BRAM_FIFO36_TSTCNT7", - "TSTCNT8": "BRAM_FIFO36_TSTCNT8", - "TSTCNT9": "BRAM_FIFO36_TSTCNT9", - "TSTFLAGIN": "BRAM_FIFO36_TSTFLAGIN", - "TSTIN0": "BRAM_FIFO36_TSTIN0", - "TSTIN1": "BRAM_FIFO36_TSTIN1", - "TSTIN2": "BRAM_FIFO36_TSTIN2", - "TSTIN3": "BRAM_FIFO36_TSTIN3", - "TSTIN4": "BRAM_FIFO36_TSTIN4", - "TSTOFF": "BRAM_FIFO36_TSTOFF", - "TSTOUT0": "BRAM_FIFO36_TSTOUT0", - "TSTOUT1": "BRAM_FIFO36_TSTOUT1", - "TSTOUT2": "BRAM_FIFO36_TSTOUT2", - "TSTOUT3": "BRAM_FIFO36_TSTOUT3", - "TSTOUT4": "BRAM_FIFO36_TSTOUT4", - "TSTRDCNTOFF": "BRAM_FIFO36_TSTRDCNTOFF", - "TSTRDOS0": "BRAM_FIFO36_TSTRDOS0", - "TSTRDOS1": "BRAM_FIFO36_TSTRDOS1", - "TSTRDOS10": "BRAM_FIFO36_TSTRDOS10", - "TSTRDOS11": "BRAM_FIFO36_TSTRDOS11", - "TSTRDOS12": "BRAM_FIFO36_TSTRDOS12", - "TSTRDOS2": "BRAM_FIFO36_TSTRDOS2", - "TSTRDOS3": "BRAM_FIFO36_TSTRDOS3", - "TSTRDOS4": "BRAM_FIFO36_TSTRDOS4", - "TSTRDOS5": "BRAM_FIFO36_TSTRDOS5", - "TSTRDOS6": "BRAM_FIFO36_TSTRDOS6", - "TSTRDOS7": "BRAM_FIFO36_TSTRDOS7", - "TSTRDOS8": "BRAM_FIFO36_TSTRDOS8", - "TSTRDOS9": "BRAM_FIFO36_TSTRDOS9", - "TSTWRCNTOFF": "BRAM_FIFO36_TSTWRCNTOFF", - "TSTWROS0": "BRAM_FIFO36_TSTWROS0", - "TSTWROS1": "BRAM_FIFO36_TSTWROS1", - "TSTWROS10": "BRAM_FIFO36_TSTWROS10", - "TSTWROS11": "BRAM_FIFO36_TSTWROS11", - "TSTWROS12": "BRAM_FIFO36_TSTWROS12", - "TSTWROS2": "BRAM_FIFO36_TSTWROS2", - "TSTWROS3": "BRAM_FIFO36_TSTWROS3", - "TSTWROS4": "BRAM_FIFO36_TSTWROS4", - "TSTWROS5": "BRAM_FIFO36_TSTWROS5", - "TSTWROS6": "BRAM_FIFO36_TSTWROS6", - "TSTWROS7": "BRAM_FIFO36_TSTWROS7", - "TSTWROS8": "BRAM_FIFO36_TSTWROS8", - "TSTWROS9": "BRAM_FIFO36_TSTWROS9", - "WEAL0": "BRAM_FIFO36_WEAL0", - "WEAL1": "BRAM_FIFO36_WEAL1", - "WEAL2": "BRAM_FIFO36_WEAL2", - "WEAL3": "BRAM_FIFO36_WEAL3", - "WEAU0": "BRAM_FIFO36_WEAU0", - "WEAU1": "BRAM_FIFO36_WEAU1", - "WEAU2": "BRAM_FIFO36_WEAU2", - "WEAU3": "BRAM_FIFO36_WEAU3", - "WEBWEL0": "BRAM_FIFO36_WEBWEL0", - "WEBWEL1": "BRAM_FIFO36_WEBWEL1", - "WEBWEL2": "BRAM_FIFO36_WEBWEL2", - "WEBWEL3": "BRAM_FIFO36_WEBWEL3", - "WEBWEL4": "BRAM_FIFO36_WEBWEL4", - "WEBWEL5": "BRAM_FIFO36_WEBWEL5", - "WEBWEL6": "BRAM_FIFO36_WEBWEL6", - "WEBWEL7": "BRAM_FIFO36_WEBWEL7", - "WEBWEU0": "BRAM_FIFO36_WEBWEU0", - "WEBWEU1": "BRAM_FIFO36_WEBWEU1", - "WEBWEU2": "BRAM_FIFO36_WEBWEU2", - "WEBWEU3": "BRAM_FIFO36_WEBWEU3", - "WEBWEU4": "BRAM_FIFO36_WEBWEU4", - "WEBWEU5": "BRAM_FIFO36_WEBWEU5", - "WEBWEU6": "BRAM_FIFO36_WEBWEU6", - "WEBWEU7": "BRAM_FIFO36_WEBWEU7", - "WRCOUNT0": "BRAM_FIFO36_WRCOUNT0", - "WRCOUNT1": "BRAM_FIFO36_WRCOUNT1", - "WRCOUNT10": "BRAM_FIFO36_WRCOUNT10", - "WRCOUNT11": "BRAM_FIFO36_WRCOUNT11", - "WRCOUNT12": "BRAM_FIFO36_WRCOUNT12", - "WRCOUNT2": "BRAM_FIFO36_WRCOUNT2", - "WRCOUNT3": "BRAM_FIFO36_WRCOUNT3", - "WRCOUNT4": "BRAM_FIFO36_WRCOUNT4", - "WRCOUNT5": "BRAM_FIFO36_WRCOUNT5", - "WRCOUNT6": "BRAM_FIFO36_WRCOUNT6", - "WRCOUNT7": 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"0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_TSTWROS6" + }, + "TSTWROS7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_TSTWROS7" + }, + "TSTWROS8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_TSTWROS8" + }, + "TSTWROS9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_TSTWROS9" + }, + "WEAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEAL0" + }, + "WEAL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEAL1" + }, + "WEAL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEAL2" + }, + "WEAL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEAL3" + }, + "WEAU0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEAU0" + }, + "WEAU1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEAU1" + }, + "WEAU2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEAU2" + }, + "WEAU3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEAU3" + }, + "WEBWEL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEL0" + }, + "WEBWEL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEL1" + }, + "WEBWEL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEL2" + }, + "WEBWEL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEL3" + }, + "WEBWEL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEL4" + }, + "WEBWEL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEL5" + }, + "WEBWEL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEL6" + }, + "WEBWEL7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEL7" + }, + "WEBWEU0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEU0" + }, + "WEBWEU1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEU1" + }, + "WEBWEU2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEU2" + }, + "WEBWEU3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEU3" + }, + "WEBWEU4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEU4" + }, + "WEBWEU5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEU5" + }, + "WEBWEU6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEU6" + }, + "WEBWEU7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "BRAM_FIFO36_WEBWEU7" + }, + "WRCOUNT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT0" + }, + "WRCOUNT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT1" + }, + "WRCOUNT10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT10" + }, + "WRCOUNT11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT11" + }, + "WRCOUNT12": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT12" + }, + "WRCOUNT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT2" + }, + "WRCOUNT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT3" + }, + "WRCOUNT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT4" + }, + "WRCOUNT5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT5" + }, + "WRCOUNT6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT6" + }, + "WRCOUNT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT7" + }, + "WRCOUNT8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT8" + }, + "WRCOUNT9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRCOUNT9" + }, + "WRERR": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "860.0625", + "wire": "BRAM_FIFO36_WRERR" + } }, "type": "RAMBFIFO36E1", "x_coord": 0, @@ -7521,2314 +26463,6136 @@ } ], "tile_type": "BRAM_R", - "wires": [ - "BRAM_ADDRARDADDRL0", - "BRAM_ADDRARDADDRL1", - "BRAM_ADDRARDADDRL10", - "BRAM_ADDRARDADDRL11", - "BRAM_ADDRARDADDRL12", - "BRAM_ADDRARDADDRL13", - "BRAM_ADDRARDADDRL14", - "BRAM_ADDRARDADDRL2", - "BRAM_ADDRARDADDRL3", - "BRAM_ADDRARDADDRL4", - "BRAM_ADDRARDADDRL5", - "BRAM_ADDRARDADDRL6", - "BRAM_ADDRARDADDRL7", - "BRAM_ADDRARDADDRL8", - "BRAM_ADDRARDADDRL9", - "BRAM_ADDRARDADDRU0", - "BRAM_ADDRARDADDRU1", - "BRAM_ADDRARDADDRU10", - "BRAM_ADDRARDADDRU11", - "BRAM_ADDRARDADDRU12", - "BRAM_ADDRARDADDRU13", - "BRAM_ADDRARDADDRU14", - "BRAM_ADDRARDADDRU2", - "BRAM_ADDRARDADDRU3", - "BRAM_ADDRARDADDRU4", - "BRAM_ADDRARDADDRU5", - "BRAM_ADDRARDADDRU6", - "BRAM_ADDRARDADDRU7", - "BRAM_ADDRARDADDRU8", - "BRAM_ADDRARDADDRU9", - "BRAM_ADDRBWRADDRL0", - "BRAM_ADDRBWRADDRL1", - "BRAM_ADDRBWRADDRL10", - "BRAM_ADDRBWRADDRL11", - "BRAM_ADDRBWRADDRL12", - "BRAM_ADDRBWRADDRL13", - "BRAM_ADDRBWRADDRL14", - "BRAM_ADDRBWRADDRL2", - "BRAM_ADDRBWRADDRL3", - "BRAM_ADDRBWRADDRL4", - "BRAM_ADDRBWRADDRL5", - "BRAM_ADDRBWRADDRL6", - "BRAM_ADDRBWRADDRL7", - "BRAM_ADDRBWRADDRL8", - "BRAM_ADDRBWRADDRL9", - "BRAM_ADDRBWRADDRU0", - "BRAM_ADDRBWRADDRU1", - "BRAM_ADDRBWRADDRU10", - "BRAM_ADDRBWRADDRU11", - "BRAM_ADDRBWRADDRU12", - "BRAM_ADDRBWRADDRU13", - "BRAM_ADDRBWRADDRU14", - "BRAM_ADDRBWRADDRU2", - "BRAM_ADDRBWRADDRU3", - "BRAM_ADDRBWRADDRU4", - "BRAM_ADDRBWRADDRU5", - "BRAM_ADDRBWRADDRU6", - "BRAM_ADDRBWRADDRU7", - "BRAM_ADDRBWRADDRU8", - "BRAM_ADDRBWRADDRU9", - "BRAM_BLOCK_OUTS_L_B0_0", - "BRAM_BLOCK_OUTS_L_B0_1", - "BRAM_BLOCK_OUTS_L_B0_2", - "BRAM_BLOCK_OUTS_L_B0_3", - "BRAM_BLOCK_OUTS_L_B0_4", - "BRAM_BLOCK_OUTS_L_B1_0", - "BRAM_BLOCK_OUTS_L_B1_1", - "BRAM_BLOCK_OUTS_L_B1_2", - "BRAM_BLOCK_OUTS_L_B1_3", - "BRAM_BLOCK_OUTS_L_B1_4", - "BRAM_BLOCK_OUTS_L_B2_0", - "BRAM_BLOCK_OUTS_L_B2_1", - "BRAM_BLOCK_OUTS_L_B2_2", - "BRAM_BLOCK_OUTS_L_B2_3", - "BRAM_BLOCK_OUTS_L_B2_4", - "BRAM_BLOCK_OUTS_L_B3_0", - "BRAM_BLOCK_OUTS_L_B3_1", - "BRAM_BLOCK_OUTS_L_B3_2", - "BRAM_BLOCK_OUTS_L_B3_3", - "BRAM_BLOCK_OUTS_L_B3_4", - "BRAM_BYP0_0", - "BRAM_BYP0_1", - "BRAM_BYP0_2", - "BRAM_BYP0_3", - "BRAM_BYP0_4", - "BRAM_BYP1_0", - "BRAM_BYP1_1", - "BRAM_BYP1_2", - "BRAM_BYP1_3", - "BRAM_BYP1_4", - "BRAM_BYP2_0", - "BRAM_BYP2_1", - "BRAM_BYP2_2", - "BRAM_BYP2_3", - "BRAM_BYP2_4", - "BRAM_BYP3_0", - "BRAM_BYP3_1", - "BRAM_BYP3_2", - "BRAM_BYP3_3", - "BRAM_BYP3_4", - "BRAM_BYP4_0", - "BRAM_BYP4_1", - "BRAM_BYP4_2", - "BRAM_BYP4_3", - "BRAM_BYP4_4", - "BRAM_BYP5_0", - "BRAM_BYP5_1", - "BRAM_BYP5_2", - "BRAM_BYP5_3", - "BRAM_BYP5_4", - "BRAM_BYP6_0", - "BRAM_BYP6_1", - "BRAM_BYP6_2", - "BRAM_BYP6_3", - "BRAM_BYP6_4", - "BRAM_BYP7_0", - "BRAM_BYP7_1", - "BRAM_BYP7_2", - "BRAM_BYP7_3", - "BRAM_BYP7_4", - "BRAM_CASCINBOT_ADDRARDADDRU0", - "BRAM_CASCINBOT_ADDRARDADDRU1", - "BRAM_CASCINBOT_ADDRARDADDRU10", - "BRAM_CASCINBOT_ADDRARDADDRU11", - "BRAM_CASCINBOT_ADDRARDADDRU12", - "BRAM_CASCINBOT_ADDRARDADDRU13", - "BRAM_CASCINBOT_ADDRARDADDRU14", - "BRAM_CASCINBOT_ADDRARDADDRU2", - "BRAM_CASCINBOT_ADDRARDADDRU3", - "BRAM_CASCINBOT_ADDRARDADDRU4", - "BRAM_CASCINBOT_ADDRARDADDRU5", - "BRAM_CASCINBOT_ADDRARDADDRU6", - "BRAM_CASCINBOT_ADDRARDADDRU7", - "BRAM_CASCINBOT_ADDRARDADDRU8", - "BRAM_CASCINBOT_ADDRARDADDRU9", - "BRAM_CASCINBOT_ADDRBWRADDRU0", - "BRAM_CASCINBOT_ADDRBWRADDRU1", - "BRAM_CASCINBOT_ADDRBWRADDRU10", - "BRAM_CASCINBOT_ADDRBWRADDRU11", - "BRAM_CASCINBOT_ADDRBWRADDRU12", - "BRAM_CASCINBOT_ADDRBWRADDRU13", - "BRAM_CASCINBOT_ADDRBWRADDRU14", - "BRAM_CASCINBOT_ADDRBWRADDRU2", - "BRAM_CASCINBOT_ADDRBWRADDRU3", - "BRAM_CASCINBOT_ADDRBWRADDRU4", - "BRAM_CASCINBOT_ADDRBWRADDRU5", - "BRAM_CASCINBOT_ADDRBWRADDRU6", - "BRAM_CASCINBOT_ADDRBWRADDRU7", - "BRAM_CASCINBOT_ADDRBWRADDRU8", - "BRAM_CASCINBOT_ADDRBWRADDRU9", - "BRAM_CASCINTOP_ADDRARDADDRU0", - "BRAM_CASCINTOP_ADDRARDADDRU1", - "BRAM_CASCINTOP_ADDRARDADDRU10", - "BRAM_CASCINTOP_ADDRARDADDRU11", - "BRAM_CASCINTOP_ADDRARDADDRU12", - "BRAM_CASCINTOP_ADDRARDADDRU13", - "BRAM_CASCINTOP_ADDRARDADDRU14", - "BRAM_CASCINTOP_ADDRARDADDRU2", - "BRAM_CASCINTOP_ADDRARDADDRU3", - "BRAM_CASCINTOP_ADDRARDADDRU4", - "BRAM_CASCINTOP_ADDRARDADDRU5", - "BRAM_CASCINTOP_ADDRARDADDRU6", - "BRAM_CASCINTOP_ADDRARDADDRU7", - "BRAM_CASCINTOP_ADDRARDADDRU8", - "BRAM_CASCINTOP_ADDRARDADDRU9", - "BRAM_CASCINTOP_ADDRBWRADDRU0", - "BRAM_CASCINTOP_ADDRBWRADDRU1", - "BRAM_CASCINTOP_ADDRBWRADDRU10", - "BRAM_CASCINTOP_ADDRBWRADDRU11", - "BRAM_CASCINTOP_ADDRBWRADDRU12", - "BRAM_CASCINTOP_ADDRBWRADDRU13", - "BRAM_CASCINTOP_ADDRBWRADDRU14", - "BRAM_CASCINTOP_ADDRBWRADDRU2", - "BRAM_CASCINTOP_ADDRBWRADDRU3", - "BRAM_CASCINTOP_ADDRBWRADDRU4", - "BRAM_CASCINTOP_ADDRBWRADDRU5", - "BRAM_CASCINTOP_ADDRBWRADDRU6", - "BRAM_CASCINTOP_ADDRBWRADDRU7", - "BRAM_CASCINTOP_ADDRBWRADDRU8", - "BRAM_CASCINTOP_ADDRBWRADDRU9", - "BRAM_CASCOUT_ADDRARDADDRU0", - "BRAM_CASCOUT_ADDRARDADDRU1", - "BRAM_CASCOUT_ADDRARDADDRU10", - "BRAM_CASCOUT_ADDRARDADDRU11", - "BRAM_CASCOUT_ADDRARDADDRU12", - "BRAM_CASCOUT_ADDRARDADDRU13", - "BRAM_CASCOUT_ADDRARDADDRU14", - "BRAM_CASCOUT_ADDRARDADDRU2", - "BRAM_CASCOUT_ADDRARDADDRU3", - "BRAM_CASCOUT_ADDRARDADDRU4", - "BRAM_CASCOUT_ADDRARDADDRU5", - "BRAM_CASCOUT_ADDRARDADDRU6", - "BRAM_CASCOUT_ADDRARDADDRU7", - "BRAM_CASCOUT_ADDRARDADDRU8", - "BRAM_CASCOUT_ADDRARDADDRU9", - "BRAM_CASCOUT_ADDRBWRADDRU0", - "BRAM_CASCOUT_ADDRBWRADDRU1", - "BRAM_CASCOUT_ADDRBWRADDRU10", - "BRAM_CASCOUT_ADDRBWRADDRU11", - "BRAM_CASCOUT_ADDRBWRADDRU12", - "BRAM_CASCOUT_ADDRBWRADDRU13", - "BRAM_CASCOUT_ADDRBWRADDRU14", - "BRAM_CASCOUT_ADDRBWRADDRU2", - "BRAM_CASCOUT_ADDRBWRADDRU3", - "BRAM_CASCOUT_ADDRBWRADDRU4", - "BRAM_CASCOUT_ADDRBWRADDRU5", - "BRAM_CASCOUT_ADDRBWRADDRU6", - "BRAM_CASCOUT_ADDRBWRADDRU7", - "BRAM_CASCOUT_ADDRBWRADDRU8", - "BRAM_CASCOUT_ADDRBWRADDRU9", - "BRAM_CLK0_0", - "BRAM_CLK0_1", - "BRAM_CLK0_2", - "BRAM_CLK0_3", - "BRAM_CLK0_4", - "BRAM_CLK1_0", - "BRAM_CLK1_1", - "BRAM_CLK1_2", - "BRAM_CLK1_3", - "BRAM_CLK1_4", - "BRAM_CTRL0_0", - "BRAM_CTRL0_1", - "BRAM_CTRL0_2", - "BRAM_CTRL0_3", - "BRAM_CTRL0_4", - "BRAM_CTRL1_0", - "BRAM_CTRL1_1", - "BRAM_CTRL1_2", - "BRAM_CTRL1_3", - "BRAM_CTRL1_4", - "BRAM_EE2A0_0", - "BRAM_EE2A0_1", - "BRAM_EE2A0_2", - "BRAM_EE2A0_3", - "BRAM_EE2A0_4", - "BRAM_EE2A1_0", - "BRAM_EE2A1_1", - "BRAM_EE2A1_2", - "BRAM_EE2A1_3", - "BRAM_EE2A1_4", - "BRAM_EE2A2_0", - "BRAM_EE2A2_1", - "BRAM_EE2A2_2", - "BRAM_EE2A2_3", - "BRAM_EE2A2_4", - "BRAM_EE2A3_0", - "BRAM_EE2A3_1", - "BRAM_EE2A3_2", - "BRAM_EE2A3_3", - "BRAM_EE2A3_4", - "BRAM_EE2BEG0_0", - "BRAM_EE2BEG0_1", - "BRAM_EE2BEG0_2", - "BRAM_EE2BEG0_3", - "BRAM_EE2BEG0_4", - "BRAM_EE2BEG1_0", - "BRAM_EE2BEG1_1", - "BRAM_EE2BEG1_2", - "BRAM_EE2BEG1_3", - "BRAM_EE2BEG1_4", - "BRAM_EE2BEG2_0", - "BRAM_EE2BEG2_1", - "BRAM_EE2BEG2_2", - "BRAM_EE2BEG2_3", - "BRAM_EE2BEG2_4", - "BRAM_EE2BEG3_0", - "BRAM_EE2BEG3_1", - "BRAM_EE2BEG3_2", - "BRAM_EE2BEG3_3", - "BRAM_EE2BEG3_4", - "BRAM_EE4A0_0", - "BRAM_EE4A0_1", - "BRAM_EE4A0_2", - "BRAM_EE4A0_3", - "BRAM_EE4A0_4", - "BRAM_EE4A1_0", - "BRAM_EE4A1_1", - "BRAM_EE4A1_2", - "BRAM_EE4A1_3", - "BRAM_EE4A1_4", - "BRAM_EE4A2_0", - "BRAM_EE4A2_1", - "BRAM_EE4A2_2", - "BRAM_EE4A2_3", - "BRAM_EE4A2_4", - "BRAM_EE4A3_0", - "BRAM_EE4A3_1", - "BRAM_EE4A3_2", - "BRAM_EE4A3_3", - "BRAM_EE4A3_4", - "BRAM_EE4B0_0", - "BRAM_EE4B0_1", - "BRAM_EE4B0_2", - "BRAM_EE4B0_3", - "BRAM_EE4B0_4", - "BRAM_EE4B1_0", - "BRAM_EE4B1_1", - "BRAM_EE4B1_2", - "BRAM_EE4B1_3", - "BRAM_EE4B1_4", - "BRAM_EE4B2_0", - "BRAM_EE4B2_1", - "BRAM_EE4B2_2", - "BRAM_EE4B2_3", - "BRAM_EE4B2_4", - "BRAM_EE4B3_0", - "BRAM_EE4B3_1", - "BRAM_EE4B3_2", - "BRAM_EE4B3_3", - "BRAM_EE4B3_4", - "BRAM_EE4BEG0_0", - "BRAM_EE4BEG0_1", - "BRAM_EE4BEG0_2", - "BRAM_EE4BEG0_3", - "BRAM_EE4BEG0_4", - "BRAM_EE4BEG1_0", - "BRAM_EE4BEG1_1", - "BRAM_EE4BEG1_2", - "BRAM_EE4BEG1_3", - "BRAM_EE4BEG1_4", - "BRAM_EE4BEG2_0", - "BRAM_EE4BEG2_1", - "BRAM_EE4BEG2_2", - "BRAM_EE4BEG2_3", - "BRAM_EE4BEG2_4", - "BRAM_EE4BEG3_0", - "BRAM_EE4BEG3_1", - "BRAM_EE4BEG3_2", - "BRAM_EE4BEG3_3", - "BRAM_EE4BEG3_4", - "BRAM_EE4C0_0", - "BRAM_EE4C0_1", - "BRAM_EE4C0_2", - "BRAM_EE4C0_3", - "BRAM_EE4C0_4", - "BRAM_EE4C1_0", - "BRAM_EE4C1_1", - "BRAM_EE4C1_2", - "BRAM_EE4C1_3", - "BRAM_EE4C1_4", - "BRAM_EE4C2_0", - "BRAM_EE4C2_1", - "BRAM_EE4C2_2", - "BRAM_EE4C2_3", - "BRAM_EE4C2_4", - "BRAM_EE4C3_0", - "BRAM_EE4C3_1", - "BRAM_EE4C3_2", - "BRAM_EE4C3_3", - "BRAM_EE4C3_4", - "BRAM_EL1BEG0_0", - "BRAM_EL1BEG0_1", - "BRAM_EL1BEG0_2", - "BRAM_EL1BEG0_3", - "BRAM_EL1BEG0_4", - "BRAM_EL1BEG1_0", - "BRAM_EL1BEG1_1", - "BRAM_EL1BEG1_2", - "BRAM_EL1BEG1_3", - "BRAM_EL1BEG1_4", - "BRAM_EL1BEG2_0", - "BRAM_EL1BEG2_1", - "BRAM_EL1BEG2_2", - "BRAM_EL1BEG2_3", - "BRAM_EL1BEG2_4", - "BRAM_EL1BEG3_0", - "BRAM_EL1BEG3_1", - "BRAM_EL1BEG3_2", - "BRAM_EL1BEG3_3", - "BRAM_EL1BEG3_4", - "BRAM_ER1BEG0_0", - "BRAM_ER1BEG0_1", - "BRAM_ER1BEG0_2", - "BRAM_ER1BEG0_3", - "BRAM_ER1BEG0_4", - "BRAM_ER1BEG1_0", - "BRAM_ER1BEG1_1", - "BRAM_ER1BEG1_2", - "BRAM_ER1BEG1_3", - "BRAM_ER1BEG1_4", - "BRAM_ER1BEG2_0", - "BRAM_ER1BEG2_1", - "BRAM_ER1BEG2_2", - "BRAM_ER1BEG2_3", - "BRAM_ER1BEG2_4", - "BRAM_ER1BEG3_0", - "BRAM_ER1BEG3_1", - "BRAM_ER1BEG3_2", - "BRAM_ER1BEG3_3", - "BRAM_ER1BEG3_4", - "BRAM_FAN0_0", - "BRAM_FAN0_1", - "BRAM_FAN0_2", - "BRAM_FAN0_3", - "BRAM_FAN0_4", - "BRAM_FAN1_0", - "BRAM_FAN1_1", - "BRAM_FAN1_2", - "BRAM_FAN1_3", - "BRAM_FAN1_4", - "BRAM_FAN2_0", - "BRAM_FAN2_1", - "BRAM_FAN2_2", - "BRAM_FAN2_3", - "BRAM_FAN2_4", - "BRAM_FAN3_0", - "BRAM_FAN3_1", - "BRAM_FAN3_2", - "BRAM_FAN3_3", - "BRAM_FAN3_4", - "BRAM_FAN4_0", - "BRAM_FAN4_1", - "BRAM_FAN4_2", - "BRAM_FAN4_3", - "BRAM_FAN4_4", - "BRAM_FAN5_0", - "BRAM_FAN5_1", - "BRAM_FAN5_2", - "BRAM_FAN5_3", - "BRAM_FAN5_4", - "BRAM_FAN6_0", - "BRAM_FAN6_1", - "BRAM_FAN6_2", - "BRAM_FAN6_3", - "BRAM_FAN6_4", - "BRAM_FAN7_0", - "BRAM_FAN7_1", - "BRAM_FAN7_2", - "BRAM_FAN7_3", - "BRAM_FAN7_4", - "BRAM_FIFO18_ADDRARDADDR0", - "BRAM_FIFO18_ADDRARDADDR1", - "BRAM_FIFO18_ADDRARDADDR10", - "BRAM_FIFO18_ADDRARDADDR11", - "BRAM_FIFO18_ADDRARDADDR12", - "BRAM_FIFO18_ADDRARDADDR13", - "BRAM_FIFO18_ADDRARDADDR2", - "BRAM_FIFO18_ADDRARDADDR3", - "BRAM_FIFO18_ADDRARDADDR4", - "BRAM_FIFO18_ADDRARDADDR5", - "BRAM_FIFO18_ADDRARDADDR6", - "BRAM_FIFO18_ADDRARDADDR7", - "BRAM_FIFO18_ADDRARDADDR8", - "BRAM_FIFO18_ADDRARDADDR9", - "BRAM_FIFO18_ADDRATIEHIGH0", - "BRAM_FIFO18_ADDRATIEHIGH1", - "BRAM_FIFO18_ADDRBTIEHIGH0", - "BRAM_FIFO18_ADDRBTIEHIGH1", - "BRAM_FIFO18_ADDRBWRADDR0", - "BRAM_FIFO18_ADDRBWRADDR1", - "BRAM_FIFO18_ADDRBWRADDR10", - "BRAM_FIFO18_ADDRBWRADDR11", - "BRAM_FIFO18_ADDRBWRADDR12", - "BRAM_FIFO18_ADDRBWRADDR13", - "BRAM_FIFO18_ADDRBWRADDR2", - "BRAM_FIFO18_ADDRBWRADDR3", - "BRAM_FIFO18_ADDRBWRADDR4", - "BRAM_FIFO18_ADDRBWRADDR5", - "BRAM_FIFO18_ADDRBWRADDR6", - "BRAM_FIFO18_ADDRBWRADDR7", - "BRAM_FIFO18_ADDRBWRADDR8", - "BRAM_FIFO18_ADDRBWRADDR9", - "BRAM_FIFO18_ALMOSTEMPTY", - "BRAM_FIFO18_ALMOSTFULL", - "BRAM_FIFO18_CLKARDCLK", - "BRAM_FIFO18_CLKBWRCLK", - "BRAM_FIFO18_DIADI0", - "BRAM_FIFO18_DIADI1", - "BRAM_FIFO18_DIADI10", - "BRAM_FIFO18_DIADI11", - "BRAM_FIFO18_DIADI12", - "BRAM_FIFO18_DIADI13", - "BRAM_FIFO18_DIADI14", - "BRAM_FIFO18_DIADI15", - "BRAM_FIFO18_DIADI2", - "BRAM_FIFO18_DIADI3", - "BRAM_FIFO18_DIADI4", - "BRAM_FIFO18_DIADI5", - "BRAM_FIFO18_DIADI6", - "BRAM_FIFO18_DIADI7", - "BRAM_FIFO18_DIADI8", - "BRAM_FIFO18_DIADI9", - "BRAM_FIFO18_DIBDI0", - "BRAM_FIFO18_DIBDI1", - "BRAM_FIFO18_DIBDI10", - "BRAM_FIFO18_DIBDI11", - "BRAM_FIFO18_DIBDI12", - "BRAM_FIFO18_DIBDI13", - "BRAM_FIFO18_DIBDI14", - "BRAM_FIFO18_DIBDI15", - "BRAM_FIFO18_DIBDI2", - "BRAM_FIFO18_DIBDI3", - "BRAM_FIFO18_DIBDI4", - "BRAM_FIFO18_DIBDI5", - "BRAM_FIFO18_DIBDI6", - "BRAM_FIFO18_DIBDI7", - "BRAM_FIFO18_DIBDI8", - "BRAM_FIFO18_DIBDI9", - "BRAM_FIFO18_DIPADIP0", - "BRAM_FIFO18_DIPADIP1", - "BRAM_FIFO18_DIPBDIP0", - "BRAM_FIFO18_DIPBDIP1", - "BRAM_FIFO18_DOADO0", - "BRAM_FIFO18_DOADO1", - "BRAM_FIFO18_DOADO10", - "BRAM_FIFO18_DOADO11", - "BRAM_FIFO18_DOADO12", - "BRAM_FIFO18_DOADO13", - "BRAM_FIFO18_DOADO14", - "BRAM_FIFO18_DOADO15", - "BRAM_FIFO18_DOADO2", - "BRAM_FIFO18_DOADO3", - "BRAM_FIFO18_DOADO4", - "BRAM_FIFO18_DOADO5", - "BRAM_FIFO18_DOADO6", - "BRAM_FIFO18_DOADO7", - "BRAM_FIFO18_DOADO8", - "BRAM_FIFO18_DOADO9", - "BRAM_FIFO18_DOBDO0", - "BRAM_FIFO18_DOBDO1", - "BRAM_FIFO18_DOBDO10", - "BRAM_FIFO18_DOBDO11", - "BRAM_FIFO18_DOBDO12", - "BRAM_FIFO18_DOBDO13", - "BRAM_FIFO18_DOBDO14", - "BRAM_FIFO18_DOBDO15", - "BRAM_FIFO18_DOBDO2", - "BRAM_FIFO18_DOBDO3", - "BRAM_FIFO18_DOBDO4", - "BRAM_FIFO18_DOBDO5", - "BRAM_FIFO18_DOBDO6", - "BRAM_FIFO18_DOBDO7", - "BRAM_FIFO18_DOBDO8", - "BRAM_FIFO18_DOBDO9", - "BRAM_FIFO18_DOPADOP0", - "BRAM_FIFO18_DOPADOP1", - "BRAM_FIFO18_DOPBDOP0", - "BRAM_FIFO18_DOPBDOP1", - "BRAM_FIFO18_EMPTY", - "BRAM_FIFO18_ENARDEN", - "BRAM_FIFO18_ENBWREN", - "BRAM_FIFO18_FULL", - "BRAM_FIFO18_RDCOUNT0", - "BRAM_FIFO18_RDCOUNT1", - "BRAM_FIFO18_RDCOUNT10", - "BRAM_FIFO18_RDCOUNT11", - "BRAM_FIFO18_RDCOUNT2", - "BRAM_FIFO18_RDCOUNT3", - "BRAM_FIFO18_RDCOUNT4", - "BRAM_FIFO18_RDCOUNT5", - "BRAM_FIFO18_RDCOUNT6", - "BRAM_FIFO18_RDCOUNT7", - "BRAM_FIFO18_RDCOUNT8", - "BRAM_FIFO18_RDCOUNT9", - "BRAM_FIFO18_RDERR", - "BRAM_FIFO18_REGCEAREGCE", - "BRAM_FIFO18_REGCEB", - "BRAM_FIFO18_REGCLKARDRCLK", - "BRAM_FIFO18_REGCLKB", - "BRAM_FIFO18_RSTRAMARSTRAM", - "BRAM_FIFO18_RSTRAMB", - "BRAM_FIFO18_RSTREGARSTREG", - "BRAM_FIFO18_RSTREGB", - "BRAM_FIFO18_WEA0", - "BRAM_FIFO18_WEA1", - "BRAM_FIFO18_WEA2", - "BRAM_FIFO18_WEA3", - "BRAM_FIFO18_WEBWE0", - "BRAM_FIFO18_WEBWE1", - "BRAM_FIFO18_WEBWE2", - "BRAM_FIFO18_WEBWE3", - "BRAM_FIFO18_WEBWE4", - "BRAM_FIFO18_WEBWE5", - "BRAM_FIFO18_WEBWE6", - "BRAM_FIFO18_WEBWE7", - "BRAM_FIFO18_WRCOUNT0", - "BRAM_FIFO18_WRCOUNT1", - "BRAM_FIFO18_WRCOUNT10", - "BRAM_FIFO18_WRCOUNT11", - "BRAM_FIFO18_WRCOUNT2", - "BRAM_FIFO18_WRCOUNT3", - "BRAM_FIFO18_WRCOUNT4", - "BRAM_FIFO18_WRCOUNT5", - "BRAM_FIFO18_WRCOUNT6", - "BRAM_FIFO18_WRCOUNT7", - "BRAM_FIFO18_WRCOUNT8", - "BRAM_FIFO18_WRCOUNT9", - "BRAM_FIFO18_WRERR", - "BRAM_FIFO36_ADDRARDADDRL0", - "BRAM_FIFO36_ADDRARDADDRL1", - "BRAM_FIFO36_ADDRARDADDRL10", - "BRAM_FIFO36_ADDRARDADDRL11", - "BRAM_FIFO36_ADDRARDADDRL12", - "BRAM_FIFO36_ADDRARDADDRL13", - "BRAM_FIFO36_ADDRARDADDRL14", - "BRAM_FIFO36_ADDRARDADDRL15", - "BRAM_FIFO36_ADDRARDADDRL2", - "BRAM_FIFO36_ADDRARDADDRL3", - "BRAM_FIFO36_ADDRARDADDRL4", - "BRAM_FIFO36_ADDRARDADDRL5", - "BRAM_FIFO36_ADDRARDADDRL6", - "BRAM_FIFO36_ADDRARDADDRL7", - "BRAM_FIFO36_ADDRARDADDRL8", - "BRAM_FIFO36_ADDRARDADDRL9", - "BRAM_FIFO36_ADDRARDADDRU0", - "BRAM_FIFO36_ADDRARDADDRU1", - "BRAM_FIFO36_ADDRARDADDRU10", - "BRAM_FIFO36_ADDRARDADDRU11", - "BRAM_FIFO36_ADDRARDADDRU12", - "BRAM_FIFO36_ADDRARDADDRU13", - "BRAM_FIFO36_ADDRARDADDRU14", - "BRAM_FIFO36_ADDRARDADDRU2", - "BRAM_FIFO36_ADDRARDADDRU3", - "BRAM_FIFO36_ADDRARDADDRU4", - "BRAM_FIFO36_ADDRARDADDRU5", - "BRAM_FIFO36_ADDRARDADDRU6", - "BRAM_FIFO36_ADDRARDADDRU7", - "BRAM_FIFO36_ADDRARDADDRU8", - "BRAM_FIFO36_ADDRARDADDRU9", - "BRAM_FIFO36_ADDRBWRADDRL0", - "BRAM_FIFO36_ADDRBWRADDRL1", - "BRAM_FIFO36_ADDRBWRADDRL10", - "BRAM_FIFO36_ADDRBWRADDRL11", - "BRAM_FIFO36_ADDRBWRADDRL12", - "BRAM_FIFO36_ADDRBWRADDRL13", - "BRAM_FIFO36_ADDRBWRADDRL14", - "BRAM_FIFO36_ADDRBWRADDRL15", - "BRAM_FIFO36_ADDRBWRADDRL2", - "BRAM_FIFO36_ADDRBWRADDRL3", - "BRAM_FIFO36_ADDRBWRADDRL4", - "BRAM_FIFO36_ADDRBWRADDRL5", - "BRAM_FIFO36_ADDRBWRADDRL6", - "BRAM_FIFO36_ADDRBWRADDRL7", - "BRAM_FIFO36_ADDRBWRADDRL8", - "BRAM_FIFO36_ADDRBWRADDRL9", - "BRAM_FIFO36_ADDRBWRADDRU0", - "BRAM_FIFO36_ADDRBWRADDRU1", - "BRAM_FIFO36_ADDRBWRADDRU10", - "BRAM_FIFO36_ADDRBWRADDRU11", - "BRAM_FIFO36_ADDRBWRADDRU12", - "BRAM_FIFO36_ADDRBWRADDRU13", - "BRAM_FIFO36_ADDRBWRADDRU14", - "BRAM_FIFO36_ADDRBWRADDRU2", - "BRAM_FIFO36_ADDRBWRADDRU3", - "BRAM_FIFO36_ADDRBWRADDRU4", - "BRAM_FIFO36_ADDRBWRADDRU5", - "BRAM_FIFO36_ADDRBWRADDRU6", - "BRAM_FIFO36_ADDRBWRADDRU7", - "BRAM_FIFO36_ADDRBWRADDRU8", - "BRAM_FIFO36_ADDRBWRADDRU9", - "BRAM_FIFO36_ALMOSTEMPTY", - "BRAM_FIFO36_ALMOSTFULL", - "BRAM_FIFO36_CASCADEINA", - "BRAM_FIFO36_CASCADEINB", - "BRAM_FIFO36_CASCADEOUTA", - "BRAM_FIFO36_CASCADEOUTA_1", - "BRAM_FIFO36_CASCADEOUTB", - "BRAM_FIFO36_CASCADEOUTB_1", - "BRAM_FIFO36_CLKARDCLKL", - "BRAM_FIFO36_CLKARDCLKU", - "BRAM_FIFO36_CLKBWRCLKL", - "BRAM_FIFO36_CLKBWRCLKU", - "BRAM_FIFO36_DBITERR", - "BRAM_FIFO36_DIADIL0", - "BRAM_FIFO36_DIADIL1", - "BRAM_FIFO36_DIADIL10", - "BRAM_FIFO36_DIADIL11", - "BRAM_FIFO36_DIADIL12", - "BRAM_FIFO36_DIADIL13", - "BRAM_FIFO36_DIADIL14", - "BRAM_FIFO36_DIADIL15", - "BRAM_FIFO36_DIADIL2", - "BRAM_FIFO36_DIADIL3", - "BRAM_FIFO36_DIADIL4", - "BRAM_FIFO36_DIADIL5", - "BRAM_FIFO36_DIADIL6", - "BRAM_FIFO36_DIADIL7", - "BRAM_FIFO36_DIADIL8", - "BRAM_FIFO36_DIADIL9", - "BRAM_FIFO36_DIADIU0", - "BRAM_FIFO36_DIADIU1", - "BRAM_FIFO36_DIADIU10", - "BRAM_FIFO36_DIADIU11", - "BRAM_FIFO36_DIADIU12", - "BRAM_FIFO36_DIADIU13", - "BRAM_FIFO36_DIADIU14", - "BRAM_FIFO36_DIADIU15", - "BRAM_FIFO36_DIADIU2", - "BRAM_FIFO36_DIADIU3", - "BRAM_FIFO36_DIADIU4", - "BRAM_FIFO36_DIADIU5", - "BRAM_FIFO36_DIADIU6", - "BRAM_FIFO36_DIADIU7", - "BRAM_FIFO36_DIADIU8", - "BRAM_FIFO36_DIADIU9", - "BRAM_FIFO36_DIBDIL0", - "BRAM_FIFO36_DIBDIL1", - "BRAM_FIFO36_DIBDIL10", - "BRAM_FIFO36_DIBDIL11", - "BRAM_FIFO36_DIBDIL12", - "BRAM_FIFO36_DIBDIL13", - "BRAM_FIFO36_DIBDIL14", - "BRAM_FIFO36_DIBDIL15", - "BRAM_FIFO36_DIBDIL2", - "BRAM_FIFO36_DIBDIL3", - "BRAM_FIFO36_DIBDIL4", - "BRAM_FIFO36_DIBDIL5", - "BRAM_FIFO36_DIBDIL6", - "BRAM_FIFO36_DIBDIL7", - "BRAM_FIFO36_DIBDIL8", - "BRAM_FIFO36_DIBDIL9", - "BRAM_FIFO36_DIBDIU0", - "BRAM_FIFO36_DIBDIU1", - "BRAM_FIFO36_DIBDIU10", - "BRAM_FIFO36_DIBDIU11", - "BRAM_FIFO36_DIBDIU12", - "BRAM_FIFO36_DIBDIU13", - "BRAM_FIFO36_DIBDIU14", - "BRAM_FIFO36_DIBDIU15", - "BRAM_FIFO36_DIBDIU2", - "BRAM_FIFO36_DIBDIU3", - "BRAM_FIFO36_DIBDIU4", - "BRAM_FIFO36_DIBDIU5", - "BRAM_FIFO36_DIBDIU6", - "BRAM_FIFO36_DIBDIU7", - "BRAM_FIFO36_DIBDIU8", - "BRAM_FIFO36_DIBDIU9", - "BRAM_FIFO36_DIPADIPL0", - "BRAM_FIFO36_DIPADIPL1", - "BRAM_FIFO36_DIPADIPU0", - "BRAM_FIFO36_DIPADIPU1", - "BRAM_FIFO36_DIPBDIPL0", - "BRAM_FIFO36_DIPBDIPL1", - "BRAM_FIFO36_DIPBDIPU0", - "BRAM_FIFO36_DIPBDIPU1", - "BRAM_FIFO36_DOADOL0", - "BRAM_FIFO36_DOADOL1", - "BRAM_FIFO36_DOADOL10", - "BRAM_FIFO36_DOADOL11", - "BRAM_FIFO36_DOADOL12", - "BRAM_FIFO36_DOADOL13", - "BRAM_FIFO36_DOADOL14", - "BRAM_FIFO36_DOADOL15", - "BRAM_FIFO36_DOADOL2", - "BRAM_FIFO36_DOADOL3", - "BRAM_FIFO36_DOADOL4", - "BRAM_FIFO36_DOADOL5", - "BRAM_FIFO36_DOADOL6", - "BRAM_FIFO36_DOADOL7", - "BRAM_FIFO36_DOADOL8", - "BRAM_FIFO36_DOADOL9", - "BRAM_FIFO36_DOADOU0", - "BRAM_FIFO36_DOADOU1", - "BRAM_FIFO36_DOADOU10", - "BRAM_FIFO36_DOADOU11", - "BRAM_FIFO36_DOADOU12", - "BRAM_FIFO36_DOADOU13", - "BRAM_FIFO36_DOADOU14", - "BRAM_FIFO36_DOADOU15", - "BRAM_FIFO36_DOADOU2", - "BRAM_FIFO36_DOADOU3", - "BRAM_FIFO36_DOADOU4", - "BRAM_FIFO36_DOADOU5", - "BRAM_FIFO36_DOADOU6", - "BRAM_FIFO36_DOADOU7", - "BRAM_FIFO36_DOADOU8", - "BRAM_FIFO36_DOADOU9", - "BRAM_FIFO36_DOBDOL0", - "BRAM_FIFO36_DOBDOL1", - "BRAM_FIFO36_DOBDOL10", - "BRAM_FIFO36_DOBDOL11", - "BRAM_FIFO36_DOBDOL12", - "BRAM_FIFO36_DOBDOL13", - "BRAM_FIFO36_DOBDOL14", - "BRAM_FIFO36_DOBDOL15", - "BRAM_FIFO36_DOBDOL2", - "BRAM_FIFO36_DOBDOL3", - "BRAM_FIFO36_DOBDOL4", - "BRAM_FIFO36_DOBDOL5", - "BRAM_FIFO36_DOBDOL6", - "BRAM_FIFO36_DOBDOL7", - "BRAM_FIFO36_DOBDOL8", - "BRAM_FIFO36_DOBDOL9", - "BRAM_FIFO36_DOBDOU0", - "BRAM_FIFO36_DOBDOU1", - "BRAM_FIFO36_DOBDOU10", - "BRAM_FIFO36_DOBDOU11", - "BRAM_FIFO36_DOBDOU12", - "BRAM_FIFO36_DOBDOU13", - "BRAM_FIFO36_DOBDOU14", - "BRAM_FIFO36_DOBDOU15", - "BRAM_FIFO36_DOBDOU2", - "BRAM_FIFO36_DOBDOU3", - "BRAM_FIFO36_DOBDOU4", - "BRAM_FIFO36_DOBDOU5", - "BRAM_FIFO36_DOBDOU6", - "BRAM_FIFO36_DOBDOU7", - "BRAM_FIFO36_DOBDOU8", - "BRAM_FIFO36_DOBDOU9", - "BRAM_FIFO36_DOPADOPL0", - "BRAM_FIFO36_DOPADOPL1", - "BRAM_FIFO36_DOPADOPU0", - "BRAM_FIFO36_DOPADOPU1", - "BRAM_FIFO36_DOPBDOPL0", - "BRAM_FIFO36_DOPBDOPL1", - "BRAM_FIFO36_DOPBDOPU0", - "BRAM_FIFO36_DOPBDOPU1", - "BRAM_FIFO36_ECCPARITY0", - "BRAM_FIFO36_ECCPARITY1", - "BRAM_FIFO36_ECCPARITY2", - "BRAM_FIFO36_ECCPARITY3", - "BRAM_FIFO36_ECCPARITY4", - "BRAM_FIFO36_ECCPARITY5", - "BRAM_FIFO36_ECCPARITY6", - "BRAM_FIFO36_ECCPARITY7", - "BRAM_FIFO36_EMPTY", - "BRAM_FIFO36_ENARDENL", - "BRAM_FIFO36_ENARDENU", - "BRAM_FIFO36_ENBWRENL", - "BRAM_FIFO36_ENBWRENU", - "BRAM_FIFO36_FULL", - "BRAM_FIFO36_INJECTDBITERR", - "BRAM_FIFO36_INJECTSBITERR", - "BRAM_FIFO36_RDCOUNT0", - "BRAM_FIFO36_RDCOUNT1", - "BRAM_FIFO36_RDCOUNT10", - "BRAM_FIFO36_RDCOUNT11", - "BRAM_FIFO36_RDCOUNT12", - "BRAM_FIFO36_RDCOUNT2", - "BRAM_FIFO36_RDCOUNT3", - "BRAM_FIFO36_RDCOUNT4", - "BRAM_FIFO36_RDCOUNT5", - "BRAM_FIFO36_RDCOUNT6", - "BRAM_FIFO36_RDCOUNT7", - "BRAM_FIFO36_RDCOUNT8", - "BRAM_FIFO36_RDCOUNT9", - "BRAM_FIFO36_RDERR", - "BRAM_FIFO36_REGCEAREGCEL", - "BRAM_FIFO36_REGCEAREGCEU", - "BRAM_FIFO36_REGCEBL", - "BRAM_FIFO36_REGCEBU", - "BRAM_FIFO36_REGCLKARDRCLKL", - "BRAM_FIFO36_REGCLKARDRCLKU", - "BRAM_FIFO36_REGCLKBL", - "BRAM_FIFO36_REGCLKBU", - "BRAM_FIFO36_RSTRAMARSTRAMLRST", - "BRAM_FIFO36_RSTRAMARSTRAMU", - "BRAM_FIFO36_RSTRAMBL", - "BRAM_FIFO36_RSTRAMBU", - "BRAM_FIFO36_RSTREGARSTREGL", - "BRAM_FIFO36_RSTREGARSTREGU", - "BRAM_FIFO36_RSTREGBL", - "BRAM_FIFO36_RSTREGBU", - "BRAM_FIFO36_SBITERR", - "BRAM_FIFO36_TSTBRAMRST", - "BRAM_FIFO36_TSTCNT0", - "BRAM_FIFO36_TSTCNT1", - "BRAM_FIFO36_TSTCNT10", - "BRAM_FIFO36_TSTCNT11", - "BRAM_FIFO36_TSTCNT12", - "BRAM_FIFO36_TSTCNT2", - "BRAM_FIFO36_TSTCNT3", - "BRAM_FIFO36_TSTCNT4", - "BRAM_FIFO36_TSTCNT5", - "BRAM_FIFO36_TSTCNT6", - "BRAM_FIFO36_TSTCNT7", - "BRAM_FIFO36_TSTCNT8", - "BRAM_FIFO36_TSTCNT9", - "BRAM_FIFO36_TSTFLAGIN", - "BRAM_FIFO36_TSTIN0", - "BRAM_FIFO36_TSTIN1", - "BRAM_FIFO36_TSTIN2", - "BRAM_FIFO36_TSTIN3", - "BRAM_FIFO36_TSTIN4", - "BRAM_FIFO36_TSTOFF", - "BRAM_FIFO36_TSTOUT0", - "BRAM_FIFO36_TSTOUT1", - "BRAM_FIFO36_TSTOUT2", - "BRAM_FIFO36_TSTOUT3", - "BRAM_FIFO36_TSTOUT4", - "BRAM_FIFO36_TSTRDCNTOFF", - "BRAM_FIFO36_TSTRDOS0", - "BRAM_FIFO36_TSTRDOS1", - "BRAM_FIFO36_TSTRDOS10", - "BRAM_FIFO36_TSTRDOS11", - "BRAM_FIFO36_TSTRDOS12", - "BRAM_FIFO36_TSTRDOS2", - "BRAM_FIFO36_TSTRDOS3", - "BRAM_FIFO36_TSTRDOS4", - "BRAM_FIFO36_TSTRDOS5", - "BRAM_FIFO36_TSTRDOS6", - "BRAM_FIFO36_TSTRDOS7", - "BRAM_FIFO36_TSTRDOS8", - "BRAM_FIFO36_TSTRDOS9", - "BRAM_FIFO36_TSTWRCNTOFF", - "BRAM_FIFO36_TSTWROS0", - "BRAM_FIFO36_TSTWROS1", - "BRAM_FIFO36_TSTWROS10", - "BRAM_FIFO36_TSTWROS11", - "BRAM_FIFO36_TSTWROS12", - "BRAM_FIFO36_TSTWROS2", - "BRAM_FIFO36_TSTWROS3", - "BRAM_FIFO36_TSTWROS4", - "BRAM_FIFO36_TSTWROS5", - "BRAM_FIFO36_TSTWROS6", - "BRAM_FIFO36_TSTWROS7", - "BRAM_FIFO36_TSTWROS8", - "BRAM_FIFO36_TSTWROS9", - "BRAM_FIFO36_WEAL0", - "BRAM_FIFO36_WEAL1", - "BRAM_FIFO36_WEAL2", - "BRAM_FIFO36_WEAL3", - "BRAM_FIFO36_WEAU0", - "BRAM_FIFO36_WEAU1", - "BRAM_FIFO36_WEAU2", - "BRAM_FIFO36_WEAU3", - "BRAM_FIFO36_WEBWEL0", - "BRAM_FIFO36_WEBWEL1", - "BRAM_FIFO36_WEBWEL2", - "BRAM_FIFO36_WEBWEL3", - "BRAM_FIFO36_WEBWEL4", - "BRAM_FIFO36_WEBWEL5", - "BRAM_FIFO36_WEBWEL6", - "BRAM_FIFO36_WEBWEL7", - "BRAM_FIFO36_WEBWEU0", - "BRAM_FIFO36_WEBWEU1", - "BRAM_FIFO36_WEBWEU2", - "BRAM_FIFO36_WEBWEU3", - "BRAM_FIFO36_WEBWEU4", - "BRAM_FIFO36_WEBWEU5", - "BRAM_FIFO36_WEBWEU6", - "BRAM_FIFO36_WEBWEU7", - "BRAM_FIFO36_WRCOUNT0", - "BRAM_FIFO36_WRCOUNT1", - "BRAM_FIFO36_WRCOUNT10", - "BRAM_FIFO36_WRCOUNT11", - "BRAM_FIFO36_WRCOUNT12", - "BRAM_FIFO36_WRCOUNT2", - "BRAM_FIFO36_WRCOUNT3", - "BRAM_FIFO36_WRCOUNT4", - "BRAM_FIFO36_WRCOUNT5", - "BRAM_FIFO36_WRCOUNT6", - "BRAM_FIFO36_WRCOUNT7", - "BRAM_FIFO36_WRCOUNT8", - "BRAM_FIFO36_WRCOUNT9", - "BRAM_FIFO36_WRERR", - "BRAM_IMUX0_0", - "BRAM_IMUX0_1", - "BRAM_IMUX0_2", - "BRAM_IMUX0_3", - "BRAM_IMUX0_4", - "BRAM_IMUX0_UTURN_0", - "BRAM_IMUX0_UTURN_1", - "BRAM_IMUX0_UTURN_2", - "BRAM_IMUX0_UTURN_3", - "BRAM_IMUX0_UTURN_4", - "BRAM_IMUX10_0", - "BRAM_IMUX10_1", - "BRAM_IMUX10_2", - "BRAM_IMUX10_3", - "BRAM_IMUX10_4", - "BRAM_IMUX10_UTURN_0", - "BRAM_IMUX10_UTURN_1", - "BRAM_IMUX10_UTURN_2", - "BRAM_IMUX10_UTURN_3", - "BRAM_IMUX10_UTURN_4", - "BRAM_IMUX11_0", - "BRAM_IMUX11_1", - "BRAM_IMUX11_2", - "BRAM_IMUX11_3", - "BRAM_IMUX11_4", - "BRAM_IMUX11_UTURN_0", - "BRAM_IMUX11_UTURN_1", - "BRAM_IMUX11_UTURN_2", - "BRAM_IMUX11_UTURN_3", - "BRAM_IMUX11_UTURN_4", - "BRAM_IMUX12_0", - "BRAM_IMUX12_1", - "BRAM_IMUX12_2", - "BRAM_IMUX12_3", - "BRAM_IMUX12_4", - "BRAM_IMUX12_UTURN_0", - "BRAM_IMUX12_UTURN_1", - "BRAM_IMUX12_UTURN_2", - "BRAM_IMUX12_UTURN_3", - "BRAM_IMUX12_UTURN_4", - "BRAM_IMUX13_0", - "BRAM_IMUX13_1", - "BRAM_IMUX13_2", - "BRAM_IMUX13_3", - "BRAM_IMUX13_4", - "BRAM_IMUX13_UTURN_0", - "BRAM_IMUX13_UTURN_1", - "BRAM_IMUX13_UTURN_2", - "BRAM_IMUX13_UTURN_3", - "BRAM_IMUX13_UTURN_4", - "BRAM_IMUX14_0", - "BRAM_IMUX14_1", - "BRAM_IMUX14_2", - "BRAM_IMUX14_3", - "BRAM_IMUX14_4", - "BRAM_IMUX14_UTURN_0", - "BRAM_IMUX14_UTURN_1", - "BRAM_IMUX14_UTURN_2", - "BRAM_IMUX14_UTURN_3", - "BRAM_IMUX14_UTURN_4", - "BRAM_IMUX15_0", - "BRAM_IMUX15_1", - "BRAM_IMUX15_2", - "BRAM_IMUX15_3", - "BRAM_IMUX15_4", - "BRAM_IMUX15_UTURN_0", - "BRAM_IMUX15_UTURN_1", - "BRAM_IMUX15_UTURN_2", - "BRAM_IMUX15_UTURN_3", - "BRAM_IMUX15_UTURN_4", - "BRAM_IMUX16_0", - "BRAM_IMUX16_1", - "BRAM_IMUX16_2", - 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"BRAM_NW4A0_3", - "BRAM_NW4A0_4", - "BRAM_NW4A1_0", - "BRAM_NW4A1_1", - "BRAM_NW4A1_2", - "BRAM_NW4A1_3", - "BRAM_NW4A1_4", - "BRAM_NW4A2_0", - "BRAM_NW4A2_1", - "BRAM_NW4A2_2", - "BRAM_NW4A2_3", - "BRAM_NW4A2_4", - "BRAM_NW4A3_0", - "BRAM_NW4A3_1", - "BRAM_NW4A3_2", - "BRAM_NW4A3_3", - "BRAM_NW4A3_4", - "BRAM_NW4END0_0", - "BRAM_NW4END0_1", - "BRAM_NW4END0_2", - "BRAM_NW4END0_3", - "BRAM_NW4END0_4", - "BRAM_NW4END1_0", - "BRAM_NW4END1_1", - "BRAM_NW4END1_2", - "BRAM_NW4END1_3", - "BRAM_NW4END1_4", - "BRAM_NW4END2_0", - "BRAM_NW4END2_1", - "BRAM_NW4END2_2", - "BRAM_NW4END2_3", - "BRAM_NW4END2_4", - "BRAM_NW4END3_0", - "BRAM_NW4END3_1", - "BRAM_NW4END3_2", - "BRAM_NW4END3_3", - "BRAM_NW4END3_4", - "BRAM_PMVBRAM_O", - "BRAM_PMVBRAM_ODIV2", - "BRAM_PMVBRAM_ODIV2_1", - "BRAM_PMVBRAM_ODIV4", - "BRAM_PMVBRAM_O_1", - "BRAM_PMVBRAM_O_2", - "BRAM_PMVBRAM_SELECT1", - "BRAM_PMVBRAM_SELECT2", - "BRAM_PMVBRAM_SELECT3", - "BRAM_PMVBRAM_SELECT4", - "BRAM_RAMB18_ADDRARDADDR0", - "BRAM_RAMB18_ADDRARDADDR1", - "BRAM_RAMB18_ADDRARDADDR10", - "BRAM_RAMB18_ADDRARDADDR11", - "BRAM_RAMB18_ADDRARDADDR12", - "BRAM_RAMB18_ADDRARDADDR13", - "BRAM_RAMB18_ADDRARDADDR2", - "BRAM_RAMB18_ADDRARDADDR3", - "BRAM_RAMB18_ADDRARDADDR4", - "BRAM_RAMB18_ADDRARDADDR5", - "BRAM_RAMB18_ADDRARDADDR6", - "BRAM_RAMB18_ADDRARDADDR7", - "BRAM_RAMB18_ADDRARDADDR8", - "BRAM_RAMB18_ADDRARDADDR9", - "BRAM_RAMB18_ADDRATIEHIGH0", - "BRAM_RAMB18_ADDRATIEHIGH1", - "BRAM_RAMB18_ADDRBTIEHIGH0", - "BRAM_RAMB18_ADDRBTIEHIGH1", - "BRAM_RAMB18_ADDRBWRADDR0", - "BRAM_RAMB18_ADDRBWRADDR1", - "BRAM_RAMB18_ADDRBWRADDR10", - "BRAM_RAMB18_ADDRBWRADDR11", - "BRAM_RAMB18_ADDRBWRADDR12", - "BRAM_RAMB18_ADDRBWRADDR13", - "BRAM_RAMB18_ADDRBWRADDR2", - "BRAM_RAMB18_ADDRBWRADDR3", - "BRAM_RAMB18_ADDRBWRADDR4", - "BRAM_RAMB18_ADDRBWRADDR5", - "BRAM_RAMB18_ADDRBWRADDR6", - "BRAM_RAMB18_ADDRBWRADDR7", - "BRAM_RAMB18_ADDRBWRADDR8", - "BRAM_RAMB18_ADDRBWRADDR9", - "BRAM_RAMB18_ALMOSTEMPTY", - "BRAM_RAMB18_ALMOSTFULL", - "BRAM_RAMB18_CLKARDCLK", - "BRAM_RAMB18_CLKBWRCLK", - "BRAM_RAMB18_DIADI0", - "BRAM_RAMB18_DIADI1", - "BRAM_RAMB18_DIADI10", - "BRAM_RAMB18_DIADI11", - "BRAM_RAMB18_DIADI12", - "BRAM_RAMB18_DIADI13", - "BRAM_RAMB18_DIADI14", - "BRAM_RAMB18_DIADI15", - "BRAM_RAMB18_DIADI2", - "BRAM_RAMB18_DIADI3", - "BRAM_RAMB18_DIADI4", - "BRAM_RAMB18_DIADI5", - "BRAM_RAMB18_DIADI6", - "BRAM_RAMB18_DIADI7", - "BRAM_RAMB18_DIADI8", - "BRAM_RAMB18_DIADI9", - "BRAM_RAMB18_DIBDI0", - "BRAM_RAMB18_DIBDI1", - "BRAM_RAMB18_DIBDI10", - "BRAM_RAMB18_DIBDI11", - "BRAM_RAMB18_DIBDI12", - "BRAM_RAMB18_DIBDI13", - "BRAM_RAMB18_DIBDI14", - "BRAM_RAMB18_DIBDI15", - "BRAM_RAMB18_DIBDI2", - "BRAM_RAMB18_DIBDI3", - "BRAM_RAMB18_DIBDI4", - "BRAM_RAMB18_DIBDI5", - "BRAM_RAMB18_DIBDI6", - "BRAM_RAMB18_DIBDI7", - "BRAM_RAMB18_DIBDI8", - "BRAM_RAMB18_DIBDI9", - "BRAM_RAMB18_DIPADIP0", - "BRAM_RAMB18_DIPADIP1", - "BRAM_RAMB18_DIPBDIP0", - "BRAM_RAMB18_DIPBDIP1", - "BRAM_RAMB18_DOADO0", - "BRAM_RAMB18_DOADO1", - "BRAM_RAMB18_DOADO10", - "BRAM_RAMB18_DOADO11", - "BRAM_RAMB18_DOADO12", - "BRAM_RAMB18_DOADO13", - "BRAM_RAMB18_DOADO14", - "BRAM_RAMB18_DOADO15", - "BRAM_RAMB18_DOADO2", - "BRAM_RAMB18_DOADO3", - "BRAM_RAMB18_DOADO4", - "BRAM_RAMB18_DOADO5", - "BRAM_RAMB18_DOADO6", - "BRAM_RAMB18_DOADO7", - "BRAM_RAMB18_DOADO8", - "BRAM_RAMB18_DOADO9", - "BRAM_RAMB18_DOBDO0", - "BRAM_RAMB18_DOBDO1", - "BRAM_RAMB18_DOBDO10", - "BRAM_RAMB18_DOBDO11", - "BRAM_RAMB18_DOBDO12", - "BRAM_RAMB18_DOBDO13", - "BRAM_RAMB18_DOBDO14", - "BRAM_RAMB18_DOBDO15", - "BRAM_RAMB18_DOBDO2", - "BRAM_RAMB18_DOBDO3", - "BRAM_RAMB18_DOBDO4", - "BRAM_RAMB18_DOBDO5", - "BRAM_RAMB18_DOBDO6", - "BRAM_RAMB18_DOBDO7", - "BRAM_RAMB18_DOBDO8", - "BRAM_RAMB18_DOBDO9", - "BRAM_RAMB18_DOPADOP0", - "BRAM_RAMB18_DOPADOP1", - "BRAM_RAMB18_DOPBDOP0", - "BRAM_RAMB18_DOPBDOP1", - "BRAM_RAMB18_EMPTY", - "BRAM_RAMB18_ENARDEN", - "BRAM_RAMB18_ENBWREN", - "BRAM_RAMB18_FULL", - "BRAM_RAMB18_RDCOUNT0", - "BRAM_RAMB18_RDCOUNT1", - "BRAM_RAMB18_RDCOUNT10", - "BRAM_RAMB18_RDCOUNT11", - "BRAM_RAMB18_RDCOUNT2", - "BRAM_RAMB18_RDCOUNT3", - "BRAM_RAMB18_RDCOUNT4", - "BRAM_RAMB18_RDCOUNT5", - "BRAM_RAMB18_RDCOUNT6", - "BRAM_RAMB18_RDCOUNT7", - "BRAM_RAMB18_RDCOUNT8", - "BRAM_RAMB18_RDCOUNT9", - "BRAM_RAMB18_RDERR", - "BRAM_RAMB18_REGCEAREGCE", - "BRAM_RAMB18_REGCEB", - "BRAM_RAMB18_REGCLKARDRCLK", - "BRAM_RAMB18_REGCLKB", - "BRAM_RAMB18_RSTRAMARSTRAM", - "BRAM_RAMB18_RSTRAMB", - "BRAM_RAMB18_RSTREGARSTREG", - "BRAM_RAMB18_RSTREGB", - "BRAM_RAMB18_WEA0", - "BRAM_RAMB18_WEA1", - "BRAM_RAMB18_WEA2", - "BRAM_RAMB18_WEA3", - "BRAM_RAMB18_WEBWE0", - "BRAM_RAMB18_WEBWE1", - "BRAM_RAMB18_WEBWE2", - "BRAM_RAMB18_WEBWE3", - "BRAM_RAMB18_WEBWE4", - "BRAM_RAMB18_WEBWE5", - "BRAM_RAMB18_WEBWE6", - "BRAM_RAMB18_WEBWE7", - "BRAM_RAMB18_WRCOUNT0", - "BRAM_RAMB18_WRCOUNT1", - "BRAM_RAMB18_WRCOUNT10", - "BRAM_RAMB18_WRCOUNT11", - "BRAM_RAMB18_WRCOUNT2", - "BRAM_RAMB18_WRCOUNT3", - "BRAM_RAMB18_WRCOUNT4", - "BRAM_RAMB18_WRCOUNT5", - "BRAM_RAMB18_WRCOUNT6", - "BRAM_RAMB18_WRCOUNT7", - "BRAM_RAMB18_WRCOUNT8", - "BRAM_RAMB18_WRCOUNT9", - "BRAM_RAMB18_WRERR", - "BRAM_R_IMUX_ADDRARDADDRL0", - "BRAM_R_IMUX_ADDRARDADDRL1", - "BRAM_R_IMUX_ADDRARDADDRL10", - "BRAM_R_IMUX_ADDRARDADDRL11", - "BRAM_R_IMUX_ADDRARDADDRL12", - "BRAM_R_IMUX_ADDRARDADDRL13", - "BRAM_R_IMUX_ADDRARDADDRL14", - "BRAM_R_IMUX_ADDRARDADDRL2", - "BRAM_R_IMUX_ADDRARDADDRL3", - "BRAM_R_IMUX_ADDRARDADDRL4", - "BRAM_R_IMUX_ADDRARDADDRL5", - "BRAM_R_IMUX_ADDRARDADDRL6", - "BRAM_R_IMUX_ADDRARDADDRL7", - "BRAM_R_IMUX_ADDRARDADDRL8", - "BRAM_R_IMUX_ADDRARDADDRL9", - "BRAM_R_IMUX_ADDRARDADDRU0", - "BRAM_R_IMUX_ADDRARDADDRU1", - "BRAM_R_IMUX_ADDRARDADDRU10", - "BRAM_R_IMUX_ADDRARDADDRU11", - "BRAM_R_IMUX_ADDRARDADDRU12", - "BRAM_R_IMUX_ADDRARDADDRU13", - "BRAM_R_IMUX_ADDRARDADDRU14", - "BRAM_R_IMUX_ADDRARDADDRU2", - "BRAM_R_IMUX_ADDRARDADDRU3", - "BRAM_R_IMUX_ADDRARDADDRU4", - "BRAM_R_IMUX_ADDRARDADDRU5", - "BRAM_R_IMUX_ADDRARDADDRU6", - "BRAM_R_IMUX_ADDRARDADDRU7", - "BRAM_R_IMUX_ADDRARDADDRU8", - "BRAM_R_IMUX_ADDRARDADDRU9", - "BRAM_R_IMUX_ADDRBWRADDRL0", - "BRAM_R_IMUX_ADDRBWRADDRL1", - "BRAM_R_IMUX_ADDRBWRADDRL10", - "BRAM_R_IMUX_ADDRBWRADDRL11", - "BRAM_R_IMUX_ADDRBWRADDRL12", - "BRAM_R_IMUX_ADDRBWRADDRL13", - "BRAM_R_IMUX_ADDRBWRADDRL14", - "BRAM_R_IMUX_ADDRBWRADDRL2", - "BRAM_R_IMUX_ADDRBWRADDRL3", - "BRAM_R_IMUX_ADDRBWRADDRL4", - "BRAM_R_IMUX_ADDRBWRADDRL5", - "BRAM_R_IMUX_ADDRBWRADDRL6", - "BRAM_R_IMUX_ADDRBWRADDRL7", - "BRAM_R_IMUX_ADDRBWRADDRL8", - "BRAM_R_IMUX_ADDRBWRADDRL9", - "BRAM_R_IMUX_ADDRBWRADDRU0", - "BRAM_R_IMUX_ADDRBWRADDRU1", - "BRAM_R_IMUX_ADDRBWRADDRU10", - "BRAM_R_IMUX_ADDRBWRADDRU11", - "BRAM_R_IMUX_ADDRBWRADDRU12", - "BRAM_R_IMUX_ADDRBWRADDRU13", - "BRAM_R_IMUX_ADDRBWRADDRU14", - "BRAM_R_IMUX_ADDRBWRADDRU2", - "BRAM_R_IMUX_ADDRBWRADDRU3", - "BRAM_R_IMUX_ADDRBWRADDRU4", - "BRAM_R_IMUX_ADDRBWRADDRU5", - "BRAM_R_IMUX_ADDRBWRADDRU6", - "BRAM_R_IMUX_ADDRBWRADDRU7", - "BRAM_R_IMUX_ADDRBWRADDRU8", - "BRAM_R_IMUX_ADDRBWRADDRU9", - "BRAM_SE2A0_0", - "BRAM_SE2A0_1", - "BRAM_SE2A0_2", - "BRAM_SE2A0_3", - "BRAM_SE2A0_4", - "BRAM_SE2A1_0", - "BRAM_SE2A1_1", - "BRAM_SE2A1_2", - "BRAM_SE2A1_3", - "BRAM_SE2A1_4", - "BRAM_SE2A2_0", - "BRAM_SE2A2_1", - "BRAM_SE2A2_2", - "BRAM_SE2A2_3", - "BRAM_SE2A2_4", - "BRAM_SE2A3_0", - "BRAM_SE2A3_1", - "BRAM_SE2A3_2", - "BRAM_SE2A3_3", - "BRAM_SE2A3_4", - "BRAM_SE4BEG0_0", - "BRAM_SE4BEG0_1", - "BRAM_SE4BEG0_2", - "BRAM_SE4BEG0_3", - "BRAM_SE4BEG0_4", - "BRAM_SE4BEG1_0", - "BRAM_SE4BEG1_1", - "BRAM_SE4BEG1_2", - "BRAM_SE4BEG1_3", - "BRAM_SE4BEG1_4", - "BRAM_SE4BEG2_0", - "BRAM_SE4BEG2_1", - "BRAM_SE4BEG2_2", - "BRAM_SE4BEG2_3", - "BRAM_SE4BEG2_4", - "BRAM_SE4BEG3_0", - "BRAM_SE4BEG3_1", - "BRAM_SE4BEG3_2", - "BRAM_SE4BEG3_3", - "BRAM_SE4BEG3_4", - "BRAM_SE4C0_0", - "BRAM_SE4C0_1", - "BRAM_SE4C0_2", - "BRAM_SE4C0_3", - "BRAM_SE4C0_4", - "BRAM_SE4C1_0", - "BRAM_SE4C1_1", - "BRAM_SE4C1_2", - "BRAM_SE4C1_3", - "BRAM_SE4C1_4", - "BRAM_SE4C2_0", - "BRAM_SE4C2_1", - "BRAM_SE4C2_2", - "BRAM_SE4C2_3", - "BRAM_SE4C2_4", - "BRAM_SE4C3_0", - "BRAM_SE4C3_1", - "BRAM_SE4C3_2", - "BRAM_SE4C3_3", - "BRAM_SE4C3_4", - "BRAM_SW2A0_0", - "BRAM_SW2A0_1", - "BRAM_SW2A0_2", - "BRAM_SW2A0_3", - "BRAM_SW2A0_4", - "BRAM_SW2A1_0", - "BRAM_SW2A1_1", - "BRAM_SW2A1_2", - "BRAM_SW2A1_3", - "BRAM_SW2A1_4", - "BRAM_SW2A2_0", - "BRAM_SW2A2_1", - "BRAM_SW2A2_2", - "BRAM_SW2A2_3", - "BRAM_SW2A2_4", - "BRAM_SW2A3_0", - "BRAM_SW2A3_1", - "BRAM_SW2A3_2", - "BRAM_SW2A3_3", - "BRAM_SW2A3_4", - "BRAM_SW4A0_0", - "BRAM_SW4A0_1", - "BRAM_SW4A0_2", - "BRAM_SW4A0_3", - "BRAM_SW4A0_4", - "BRAM_SW4A1_0", - "BRAM_SW4A1_1", - "BRAM_SW4A1_2", - "BRAM_SW4A1_3", - "BRAM_SW4A1_4", - "BRAM_SW4A2_0", - "BRAM_SW4A2_1", - "BRAM_SW4A2_2", - "BRAM_SW4A2_3", - "BRAM_SW4A2_4", - "BRAM_SW4A3_0", - "BRAM_SW4A3_1", - "BRAM_SW4A3_2", - "BRAM_SW4A3_3", - "BRAM_SW4A3_4", - "BRAM_SW4END0_0", - "BRAM_SW4END0_1", - "BRAM_SW4END0_2", - "BRAM_SW4END0_3", - "BRAM_SW4END0_4", - "BRAM_SW4END1_0", - "BRAM_SW4END1_1", - "BRAM_SW4END1_2", - "BRAM_SW4END1_3", - "BRAM_SW4END1_4", - "BRAM_SW4END2_0", - "BRAM_SW4END2_1", - "BRAM_SW4END2_2", - "BRAM_SW4END2_3", - "BRAM_SW4END2_4", - "BRAM_SW4END3_0", - "BRAM_SW4END3_1", - "BRAM_SW4END3_2", - "BRAM_SW4END3_3", - "BRAM_SW4END3_4", - "BRAM_UTURN_ADDRARDADDRL0", - "BRAM_UTURN_ADDRARDADDRL1", - "BRAM_UTURN_ADDRARDADDRL10", - "BRAM_UTURN_ADDRARDADDRL11", - "BRAM_UTURN_ADDRARDADDRL12", - "BRAM_UTURN_ADDRARDADDRL13", - "BRAM_UTURN_ADDRARDADDRL14", - "BRAM_UTURN_ADDRARDADDRL15", - "BRAM_UTURN_ADDRARDADDRL2", - "BRAM_UTURN_ADDRARDADDRL3", - "BRAM_UTURN_ADDRARDADDRL4", - "BRAM_UTURN_ADDRARDADDRL5", - "BRAM_UTURN_ADDRARDADDRL6", - "BRAM_UTURN_ADDRARDADDRL7", - "BRAM_UTURN_ADDRARDADDRL8", - "BRAM_UTURN_ADDRARDADDRL9", - "BRAM_UTURN_ADDRARDADDRU0", - "BRAM_UTURN_ADDRARDADDRU1", - "BRAM_UTURN_ADDRARDADDRU10", - "BRAM_UTURN_ADDRARDADDRU11", - "BRAM_UTURN_ADDRARDADDRU12", - "BRAM_UTURN_ADDRARDADDRU13", - "BRAM_UTURN_ADDRARDADDRU14", - "BRAM_UTURN_ADDRARDADDRU2", - "BRAM_UTURN_ADDRARDADDRU3", - "BRAM_UTURN_ADDRARDADDRU4", - "BRAM_UTURN_ADDRARDADDRU5", - "BRAM_UTURN_ADDRARDADDRU6", - "BRAM_UTURN_ADDRARDADDRU7", - "BRAM_UTURN_ADDRARDADDRU8", - "BRAM_UTURN_ADDRARDADDRU9", - "BRAM_UTURN_ADDRBWRADDRL0", - "BRAM_UTURN_ADDRBWRADDRL1", - "BRAM_UTURN_ADDRBWRADDRL10", - "BRAM_UTURN_ADDRBWRADDRL11", - "BRAM_UTURN_ADDRBWRADDRL12", - "BRAM_UTURN_ADDRBWRADDRL13", - "BRAM_UTURN_ADDRBWRADDRL14", - "BRAM_UTURN_ADDRBWRADDRL15", - "BRAM_UTURN_ADDRBWRADDRL2", - "BRAM_UTURN_ADDRBWRADDRL3", - "BRAM_UTURN_ADDRBWRADDRL4", - "BRAM_UTURN_ADDRBWRADDRL5", - "BRAM_UTURN_ADDRBWRADDRL6", - "BRAM_UTURN_ADDRBWRADDRL7", - "BRAM_UTURN_ADDRBWRADDRL8", - "BRAM_UTURN_ADDRBWRADDRL9", - "BRAM_UTURN_ADDRBWRADDRU0", - "BRAM_UTURN_ADDRBWRADDRU1", - "BRAM_UTURN_ADDRBWRADDRU10", - "BRAM_UTURN_ADDRBWRADDRU11", - "BRAM_UTURN_ADDRBWRADDRU12", - "BRAM_UTURN_ADDRBWRADDRU13", - "BRAM_UTURN_ADDRBWRADDRU14", - "BRAM_UTURN_ADDRBWRADDRU2", - "BRAM_UTURN_ADDRBWRADDRU3", - "BRAM_UTURN_ADDRBWRADDRU4", - "BRAM_UTURN_ADDRBWRADDRU5", - "BRAM_UTURN_ADDRBWRADDRU6", - "BRAM_UTURN_ADDRBWRADDRU7", - "BRAM_UTURN_ADDRBWRADDRU8", - "BRAM_UTURN_ADDRBWRADDRU9", - "BRAM_WL1END0_0", - "BRAM_WL1END0_1", - "BRAM_WL1END0_2", - "BRAM_WL1END0_3", - "BRAM_WL1END0_4", - "BRAM_WL1END1_0", - "BRAM_WL1END1_1", - "BRAM_WL1END1_2", - "BRAM_WL1END1_3", - "BRAM_WL1END1_4", - "BRAM_WL1END2_0", - "BRAM_WL1END2_1", - "BRAM_WL1END2_2", - "BRAM_WL1END2_3", - "BRAM_WL1END2_4", - "BRAM_WL1END3_0", - "BRAM_WL1END3_1", - "BRAM_WL1END3_2", - "BRAM_WL1END3_3", - "BRAM_WL1END3_4", - "BRAM_WR1END0_0", - "BRAM_WR1END0_1", - "BRAM_WR1END0_2", - "BRAM_WR1END0_3", - "BRAM_WR1END0_4", - "BRAM_WR1END1_0", - "BRAM_WR1END1_1", - "BRAM_WR1END1_2", - "BRAM_WR1END1_3", - "BRAM_WR1END1_4", - "BRAM_WR1END2_0", - "BRAM_WR1END2_1", - "BRAM_WR1END2_2", - "BRAM_WR1END2_3", - "BRAM_WR1END2_4", - "BRAM_WR1END3_0", - "BRAM_WR1END3_1", - "BRAM_WR1END3_2", - "BRAM_WR1END3_3", - "BRAM_WR1END3_4", - "BRAM_WW2A0_0", - "BRAM_WW2A0_1", - "BRAM_WW2A0_2", - "BRAM_WW2A0_3", - "BRAM_WW2A0_4", - "BRAM_WW2A1_0", - "BRAM_WW2A1_1", - "BRAM_WW2A1_2", - "BRAM_WW2A1_3", - "BRAM_WW2A1_4", - "BRAM_WW2A2_0", - "BRAM_WW2A2_1", - "BRAM_WW2A2_2", - "BRAM_WW2A2_3", - "BRAM_WW2A2_4", - "BRAM_WW2A3_0", - "BRAM_WW2A3_1", - "BRAM_WW2A3_2", - "BRAM_WW2A3_3", - "BRAM_WW2A3_4", - "BRAM_WW2END0_0", - "BRAM_WW2END0_1", - "BRAM_WW2END0_2", - "BRAM_WW2END0_3", - "BRAM_WW2END0_4", - "BRAM_WW2END1_0", - "BRAM_WW2END1_1", - "BRAM_WW2END1_2", - "BRAM_WW2END1_3", - "BRAM_WW2END1_4", - "BRAM_WW2END2_0", - "BRAM_WW2END2_1", - "BRAM_WW2END2_2", - "BRAM_WW2END2_3", - "BRAM_WW2END2_4", - "BRAM_WW2END3_0", - "BRAM_WW2END3_1", - "BRAM_WW2END3_2", - "BRAM_WW2END3_3", - "BRAM_WW2END3_4", - "BRAM_WW4A0_0", - "BRAM_WW4A0_1", - "BRAM_WW4A0_2", - "BRAM_WW4A0_3", - "BRAM_WW4A0_4", - "BRAM_WW4A1_0", - "BRAM_WW4A1_1", - "BRAM_WW4A1_2", - "BRAM_WW4A1_3", - "BRAM_WW4A1_4", - "BRAM_WW4A2_0", - "BRAM_WW4A2_1", - "BRAM_WW4A2_2", - "BRAM_WW4A2_3", - "BRAM_WW4A2_4", - "BRAM_WW4A3_0", - "BRAM_WW4A3_1", - "BRAM_WW4A3_2", - "BRAM_WW4A3_3", - "BRAM_WW4A3_4", - "BRAM_WW4B0_0", - "BRAM_WW4B0_1", - "BRAM_WW4B0_2", - "BRAM_WW4B0_3", - "BRAM_WW4B0_4", - "BRAM_WW4B1_0", - "BRAM_WW4B1_1", - "BRAM_WW4B1_2", - "BRAM_WW4B1_3", - "BRAM_WW4B1_4", - "BRAM_WW4B2_0", - "BRAM_WW4B2_1", - "BRAM_WW4B2_2", - "BRAM_WW4B2_3", - "BRAM_WW4B2_4", - "BRAM_WW4B3_0", - "BRAM_WW4B3_1", - "BRAM_WW4B3_2", - "BRAM_WW4B3_3", - "BRAM_WW4B3_4", - "BRAM_WW4C0_0", - "BRAM_WW4C0_1", - "BRAM_WW4C0_2", - "BRAM_WW4C0_3", - "BRAM_WW4C0_4", - "BRAM_WW4C1_0", - "BRAM_WW4C1_1", - "BRAM_WW4C1_2", - "BRAM_WW4C1_3", - "BRAM_WW4C1_4", - "BRAM_WW4C2_0", - "BRAM_WW4C2_1", - "BRAM_WW4C2_2", - "BRAM_WW4C2_3", - "BRAM_WW4C2_4", - "BRAM_WW4C3_0", - "BRAM_WW4C3_1", - "BRAM_WW4C3_2", - "BRAM_WW4C3_3", - "BRAM_WW4C3_4", - "BRAM_WW4END0_0", - "BRAM_WW4END0_1", - "BRAM_WW4END0_2", - "BRAM_WW4END0_3", - "BRAM_WW4END0_4", - "BRAM_WW4END1_0", - "BRAM_WW4END1_1", - "BRAM_WW4END1_2", - "BRAM_WW4END1_3", - "BRAM_WW4END1_4", - "BRAM_WW4END2_0", - "BRAM_WW4END2_1", - "BRAM_WW4END2_2", - "BRAM_WW4END2_3", - "BRAM_WW4END2_4", - "BRAM_WW4END3_0", - "BRAM_WW4END3_1", - "BRAM_WW4END3_2", - "BRAM_WW4END3_3", - "BRAM_WW4END3_4" - ] + "wires": { + "BRAM_ADDRARDADDRL0": null, + "BRAM_ADDRARDADDRL1": null, + "BRAM_ADDRARDADDRL10": null, + "BRAM_ADDRARDADDRL11": null, + "BRAM_ADDRARDADDRL12": null, + "BRAM_ADDRARDADDRL13": null, + "BRAM_ADDRARDADDRL14": null, + "BRAM_ADDRARDADDRL2": null, + "BRAM_ADDRARDADDRL3": null, + "BRAM_ADDRARDADDRL4": null, + "BRAM_ADDRARDADDRL5": null, + "BRAM_ADDRARDADDRL6": null, + "BRAM_ADDRARDADDRL7": null, + "BRAM_ADDRARDADDRL8": null, + "BRAM_ADDRARDADDRL9": null, + "BRAM_ADDRARDADDRU0": null, + "BRAM_ADDRARDADDRU1": null, + "BRAM_ADDRARDADDRU10": null, + "BRAM_ADDRARDADDRU11": null, + "BRAM_ADDRARDADDRU12": null, + "BRAM_ADDRARDADDRU13": null, + "BRAM_ADDRARDADDRU14": null, + "BRAM_ADDRARDADDRU2": null, + "BRAM_ADDRARDADDRU3": null, + "BRAM_ADDRARDADDRU4": null, + "BRAM_ADDRARDADDRU5": null, + "BRAM_ADDRARDADDRU6": null, + "BRAM_ADDRARDADDRU7": null, + "BRAM_ADDRARDADDRU8": null, + "BRAM_ADDRARDADDRU9": null, + "BRAM_ADDRBWRADDRL0": null, + "BRAM_ADDRBWRADDRL1": null, + "BRAM_ADDRBWRADDRL10": null, + "BRAM_ADDRBWRADDRL11": null, + "BRAM_ADDRBWRADDRL12": null, + "BRAM_ADDRBWRADDRL13": null, + "BRAM_ADDRBWRADDRL14": null, + "BRAM_ADDRBWRADDRL2": null, + "BRAM_ADDRBWRADDRL3": null, + "BRAM_ADDRBWRADDRL4": null, + "BRAM_ADDRBWRADDRL5": null, + "BRAM_ADDRBWRADDRL6": null, + "BRAM_ADDRBWRADDRL7": null, + "BRAM_ADDRBWRADDRL8": null, + "BRAM_ADDRBWRADDRL9": null, + "BRAM_ADDRBWRADDRU0": null, + "BRAM_ADDRBWRADDRU1": null, + "BRAM_ADDRBWRADDRU10": null, + "BRAM_ADDRBWRADDRU11": null, + "BRAM_ADDRBWRADDRU12": null, + "BRAM_ADDRBWRADDRU13": null, + "BRAM_ADDRBWRADDRU14": null, + "BRAM_ADDRBWRADDRU2": null, + "BRAM_ADDRBWRADDRU3": null, + "BRAM_ADDRBWRADDRU4": null, + "BRAM_ADDRBWRADDRU5": null, + "BRAM_ADDRBWRADDRU6": null, + "BRAM_ADDRBWRADDRU7": null, + "BRAM_ADDRBWRADDRU8": null, + "BRAM_ADDRBWRADDRU9": null, + "BRAM_BLOCK_OUTS_L_B0_0": null, + "BRAM_BLOCK_OUTS_L_B0_1": null, + "BRAM_BLOCK_OUTS_L_B0_2": null, + "BRAM_BLOCK_OUTS_L_B0_3": null, + "BRAM_BLOCK_OUTS_L_B0_4": null, + "BRAM_BLOCK_OUTS_L_B1_0": null, + "BRAM_BLOCK_OUTS_L_B1_1": null, + "BRAM_BLOCK_OUTS_L_B1_2": null, + "BRAM_BLOCK_OUTS_L_B1_3": null, + "BRAM_BLOCK_OUTS_L_B1_4": null, + "BRAM_BLOCK_OUTS_L_B2_0": null, + "BRAM_BLOCK_OUTS_L_B2_1": null, + "BRAM_BLOCK_OUTS_L_B2_2": null, + "BRAM_BLOCK_OUTS_L_B2_3": null, + "BRAM_BLOCK_OUTS_L_B2_4": null, + "BRAM_BLOCK_OUTS_L_B3_0": null, + "BRAM_BLOCK_OUTS_L_B3_1": null, + "BRAM_BLOCK_OUTS_L_B3_2": null, + "BRAM_BLOCK_OUTS_L_B3_3": null, + "BRAM_BLOCK_OUTS_L_B3_4": null, + "BRAM_BYP0_0": null, + "BRAM_BYP0_1": null, + "BRAM_BYP0_2": null, + "BRAM_BYP0_3": null, + "BRAM_BYP0_4": null, + "BRAM_BYP1_0": null, + "BRAM_BYP1_1": null, + "BRAM_BYP1_2": null, + "BRAM_BYP1_3": null, + "BRAM_BYP1_4": null, + "BRAM_BYP2_0": null, + "BRAM_BYP2_1": null, + "BRAM_BYP2_2": null, + "BRAM_BYP2_3": null, + "BRAM_BYP2_4": null, + "BRAM_BYP3_0": null, + "BRAM_BYP3_1": null, + "BRAM_BYP3_2": null, + "BRAM_BYP3_3": null, + "BRAM_BYP3_4": null, + "BRAM_BYP4_0": null, + "BRAM_BYP4_1": null, + "BRAM_BYP4_2": null, + "BRAM_BYP4_3": null, + "BRAM_BYP4_4": null, + "BRAM_BYP5_0": null, + "BRAM_BYP5_1": null, + "BRAM_BYP5_2": null, + "BRAM_BYP5_3": null, + "BRAM_BYP5_4": null, + "BRAM_BYP6_0": null, + "BRAM_BYP6_1": null, + "BRAM_BYP6_2": null, + "BRAM_BYP6_3": null, + "BRAM_BYP6_4": null, + "BRAM_BYP7_0": null, + "BRAM_BYP7_1": null, + "BRAM_BYP7_2": null, + "BRAM_BYP7_3": null, + "BRAM_BYP7_4": null, + "BRAM_CASCINBOT_ADDRARDADDRU0": null, + "BRAM_CASCINBOT_ADDRARDADDRU1": null, + "BRAM_CASCINBOT_ADDRARDADDRU10": null, + "BRAM_CASCINBOT_ADDRARDADDRU11": null, + "BRAM_CASCINBOT_ADDRARDADDRU12": null, + "BRAM_CASCINBOT_ADDRARDADDRU13": null, + "BRAM_CASCINBOT_ADDRARDADDRU14": null, + "BRAM_CASCINBOT_ADDRARDADDRU2": null, + "BRAM_CASCINBOT_ADDRARDADDRU3": null, + "BRAM_CASCINBOT_ADDRARDADDRU4": null, + "BRAM_CASCINBOT_ADDRARDADDRU5": null, + "BRAM_CASCINBOT_ADDRARDADDRU6": null, + "BRAM_CASCINBOT_ADDRARDADDRU7": null, + "BRAM_CASCINBOT_ADDRARDADDRU8": null, + "BRAM_CASCINBOT_ADDRARDADDRU9": null, + "BRAM_CASCINBOT_ADDRBWRADDRU0": null, + "BRAM_CASCINBOT_ADDRBWRADDRU1": null, + "BRAM_CASCINBOT_ADDRBWRADDRU10": null, + "BRAM_CASCINBOT_ADDRBWRADDRU11": null, + "BRAM_CASCINBOT_ADDRBWRADDRU12": null, + "BRAM_CASCINBOT_ADDRBWRADDRU13": null, + "BRAM_CASCINBOT_ADDRBWRADDRU14": null, + "BRAM_CASCINBOT_ADDRBWRADDRU2": null, + "BRAM_CASCINBOT_ADDRBWRADDRU3": null, + "BRAM_CASCINBOT_ADDRBWRADDRU4": null, + "BRAM_CASCINBOT_ADDRBWRADDRU5": null, + "BRAM_CASCINBOT_ADDRBWRADDRU6": null, + "BRAM_CASCINBOT_ADDRBWRADDRU7": null, + "BRAM_CASCINBOT_ADDRBWRADDRU8": null, + "BRAM_CASCINBOT_ADDRBWRADDRU9": null, + "BRAM_CASCINTOP_ADDRARDADDRU0": null, + "BRAM_CASCINTOP_ADDRARDADDRU1": null, + "BRAM_CASCINTOP_ADDRARDADDRU10": null, + "BRAM_CASCINTOP_ADDRARDADDRU11": null, + "BRAM_CASCINTOP_ADDRARDADDRU12": null, + "BRAM_CASCINTOP_ADDRARDADDRU13": null, + "BRAM_CASCINTOP_ADDRARDADDRU14": null, + "BRAM_CASCINTOP_ADDRARDADDRU2": null, + "BRAM_CASCINTOP_ADDRARDADDRU3": null, + "BRAM_CASCINTOP_ADDRARDADDRU4": null, + "BRAM_CASCINTOP_ADDRARDADDRU5": null, + "BRAM_CASCINTOP_ADDRARDADDRU6": null, + "BRAM_CASCINTOP_ADDRARDADDRU7": null, + "BRAM_CASCINTOP_ADDRARDADDRU8": null, + "BRAM_CASCINTOP_ADDRARDADDRU9": null, + "BRAM_CASCINTOP_ADDRBWRADDRU0": null, + "BRAM_CASCINTOP_ADDRBWRADDRU1": null, + "BRAM_CASCINTOP_ADDRBWRADDRU10": null, + "BRAM_CASCINTOP_ADDRBWRADDRU11": null, + "BRAM_CASCINTOP_ADDRBWRADDRU12": null, + "BRAM_CASCINTOP_ADDRBWRADDRU13": null, + "BRAM_CASCINTOP_ADDRBWRADDRU14": null, + "BRAM_CASCINTOP_ADDRBWRADDRU2": null, + "BRAM_CASCINTOP_ADDRBWRADDRU3": null, + "BRAM_CASCINTOP_ADDRBWRADDRU4": null, + "BRAM_CASCINTOP_ADDRBWRADDRU5": null, + "BRAM_CASCINTOP_ADDRBWRADDRU6": null, + "BRAM_CASCINTOP_ADDRBWRADDRU7": null, + "BRAM_CASCINTOP_ADDRBWRADDRU8": null, + "BRAM_CASCINTOP_ADDRBWRADDRU9": null, + "BRAM_CASCOUT_ADDRARDADDRU0": null, + "BRAM_CASCOUT_ADDRARDADDRU1": null, + "BRAM_CASCOUT_ADDRARDADDRU10": null, + "BRAM_CASCOUT_ADDRARDADDRU11": null, + "BRAM_CASCOUT_ADDRARDADDRU12": null, + "BRAM_CASCOUT_ADDRARDADDRU13": null, + "BRAM_CASCOUT_ADDRARDADDRU14": null, + "BRAM_CASCOUT_ADDRARDADDRU2": null, + "BRAM_CASCOUT_ADDRARDADDRU3": null, + "BRAM_CASCOUT_ADDRARDADDRU4": null, + "BRAM_CASCOUT_ADDRARDADDRU5": null, + "BRAM_CASCOUT_ADDRARDADDRU6": null, + "BRAM_CASCOUT_ADDRARDADDRU7": null, + "BRAM_CASCOUT_ADDRARDADDRU8": null, + "BRAM_CASCOUT_ADDRARDADDRU9": null, + "BRAM_CASCOUT_ADDRBWRADDRU0": null, + "BRAM_CASCOUT_ADDRBWRADDRU1": null, + "BRAM_CASCOUT_ADDRBWRADDRU10": null, + "BRAM_CASCOUT_ADDRBWRADDRU11": null, + "BRAM_CASCOUT_ADDRBWRADDRU12": null, + "BRAM_CASCOUT_ADDRBWRADDRU13": null, + "BRAM_CASCOUT_ADDRBWRADDRU14": null, + "BRAM_CASCOUT_ADDRBWRADDRU2": null, + "BRAM_CASCOUT_ADDRBWRADDRU3": null, + "BRAM_CASCOUT_ADDRBWRADDRU4": null, + "BRAM_CASCOUT_ADDRBWRADDRU5": null, + "BRAM_CASCOUT_ADDRBWRADDRU6": null, + "BRAM_CASCOUT_ADDRBWRADDRU7": null, + "BRAM_CASCOUT_ADDRBWRADDRU8": null, + "BRAM_CASCOUT_ADDRBWRADDRU9": null, + "BRAM_CLK0_0": null, + "BRAM_CLK0_1": null, + "BRAM_CLK0_2": null, + "BRAM_CLK0_3": null, + "BRAM_CLK0_4": null, + "BRAM_CLK1_0": null, + "BRAM_CLK1_1": null, + "BRAM_CLK1_2": null, + "BRAM_CLK1_3": null, + "BRAM_CLK1_4": null, + "BRAM_CTRL0_0": null, + "BRAM_CTRL0_1": null, + "BRAM_CTRL0_2": null, + "BRAM_CTRL0_3": null, + "BRAM_CTRL0_4": null, + "BRAM_CTRL1_0": null, + "BRAM_CTRL1_1": null, + "BRAM_CTRL1_2": null, + "BRAM_CTRL1_3": null, + "BRAM_CTRL1_4": null, + "BRAM_EE2A0_0": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A0_1": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A0_2": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A0_3": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A0_4": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A1_0": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A1_1": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A1_2": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A1_3": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A1_4": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A2_0": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A2_1": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A2_2": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A2_3": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A2_4": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A3_0": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A3_1": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A3_2": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A3_3": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2A3_4": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG0_0": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG0_1": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG0_2": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG0_3": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG0_4": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG1_0": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG1_1": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG1_2": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG1_3": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG1_4": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG2_0": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG2_1": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG2_2": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG2_3": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG2_4": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG3_0": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG3_1": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG3_2": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG3_3": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE2BEG3_4": { + "cap": "67.000", + "res": "268.920" + }, + "BRAM_EE4A0_0": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A0_1": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A0_2": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A0_3": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A0_4": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A1_0": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A1_1": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A1_2": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A1_3": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A1_4": { + "cap": "68.000", + "res": "268.920" + }, + "BRAM_EE4A2_0": { + "cap": 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a/kintex7/tile_type_BRKH_BRAM.json b/kintex7/tile_type_BRKH_BRAM.json index 0314f62..be8ea32 100644 --- a/kintex7/tile_type_BRKH_BRAM.json +++ b/kintex7/tile_type_BRKH_BRAM.json @@ -2,70 +2,70 @@ "pips": {}, "sites": [], "tile_type": "BRKH_BRAM", - "wires": [ - "BRKH_BRAM_CASCADEA_L", - "BRKH_BRAM_CASCADEA_R", - "BRKH_BRAM_CASCADEB_L", - "BRKH_BRAM_CASCADEB_R", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8", - "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8", - "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8", - "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9" - ] + "wires": { + "BRKH_BRAM_CASCADEA_L": null, + "BRKH_BRAM_CASCADEA_R": null, + "BRKH_BRAM_CASCADEB_L": null, + "BRKH_BRAM_CASCADEB_R": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU0": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU1": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU10": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU11": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU12": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU13": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU14": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU2": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU3": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU4": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU5": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU6": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU7": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU8": null, + "BRKH_BRAM_CASCIN_L_ADDRARDADDRU9": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU0": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU1": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU10": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU11": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU12": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU13": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU14": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU2": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU3": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU4": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU5": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU6": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU7": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU8": null, + "BRKH_BRAM_CASCIN_L_ADDRBWRADDRU9": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU0": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU1": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU10": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU11": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU12": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU13": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU14": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU2": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU3": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU4": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU5": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU6": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU7": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU8": null, + "BRKH_BRAM_CASCOUT_L_ADDRARDADDRU9": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU0": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU1": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU10": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU11": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU12": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU13": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU14": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU2": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU3": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU4": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU5": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU6": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU7": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU8": null, + "BRKH_BRAM_CASCOUT_L_ADDRBWRADDRU9": null + } } diff --git a/kintex7/tile_type_BRKH_B_TERM_INT.json b/kintex7/tile_type_BRKH_B_TERM_INT.json index b319f4c..0b8feb1 100644 --- a/kintex7/tile_type_BRKH_B_TERM_INT.json +++ b/kintex7/tile_type_BRKH_B_TERM_INT.json @@ -2,124 +2,214 @@ "pips": {}, "sites": [], "tile_type": "BRKH_B_TERM_INT", - "wires": [ - "B_TERM_UTURN_INT_ER1BEG0", - "B_TERM_UTURN_INT_ER1END_N3_3", - "B_TERM_UTURN_INT_FAN_BOUNCE0", - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "B_TERM_UTURN_INT_LV18", - "B_TERM_UTURN_INT_LV2", - "B_TERM_UTURN_INT_LV3", - "B_TERM_UTURN_INT_LV4", - "B_TERM_UTURN_INT_LV5", - "B_TERM_UTURN_INT_LV6", - "B_TERM_UTURN_INT_LV7", - "B_TERM_UTURN_INT_LV8", - "B_TERM_UTURN_INT_LV9", - "B_TERM_UTURN_INT_LVB0", - "B_TERM_UTURN_INT_LVB1", - "B_TERM_UTURN_INT_LVB2", - "B_TERM_UTURN_INT_LVB3", - "B_TERM_UTURN_INT_LVB4", - "B_TERM_UTURN_INT_LVB5", - "B_TERM_UTURN_INT_LVB_L0", - "B_TERM_UTURN_INT_LVB_L1", - "B_TERM_UTURN_INT_LVB_L2", - "B_TERM_UTURN_INT_LVB_L3", - "B_TERM_UTURN_INT_LVB_L4", - "B_TERM_UTURN_INT_LVB_L5", - "B_TERM_UTURN_INT_LV_L18", - "B_TERM_UTURN_INT_LV_L2", - "B_TERM_UTURN_INT_LV_L3", - "B_TERM_UTURN_INT_LV_L4", - "B_TERM_UTURN_INT_LV_L5", - "B_TERM_UTURN_INT_LV_L6", - "B_TERM_UTURN_INT_LV_L7", - "B_TERM_UTURN_INT_LV_L8", - "B_TERM_UTURN_INT_LV_L9", - "B_TERM_UTURN_INT_SE2BEG0", - "B_TERM_UTURN_INT_SE2BEG1", - "B_TERM_UTURN_INT_SE2BEG2", - "B_TERM_UTURN_INT_SE2BEG3", - "B_TERM_UTURN_INT_SE6A0", - "B_TERM_UTURN_INT_SE6A1", - "B_TERM_UTURN_INT_SE6A2", - "B_TERM_UTURN_INT_SE6A3", - "B_TERM_UTURN_INT_SE6B0", - "B_TERM_UTURN_INT_SE6B1", - "B_TERM_UTURN_INT_SE6B2", - "B_TERM_UTURN_INT_SE6B3", - "B_TERM_UTURN_INT_SE6C0", - "B_TERM_UTURN_INT_SE6C1", - "B_TERM_UTURN_INT_SE6C2", - "B_TERM_UTURN_INT_SE6C3", - "B_TERM_UTURN_INT_SE6D0", - "B_TERM_UTURN_INT_SE6D1", - "B_TERM_UTURN_INT_SE6D2", - "B_TERM_UTURN_INT_SE6D3", - "B_TERM_UTURN_INT_SL1BEG0", - "B_TERM_UTURN_INT_SL1BEG1", - "B_TERM_UTURN_INT_SL1BEG2", - "B_TERM_UTURN_INT_SL1BEG3", - "B_TERM_UTURN_INT_SR1BEG1", - "B_TERM_UTURN_INT_SR1BEG2", - "B_TERM_UTURN_INT_SR1BEG3", - "B_TERM_UTURN_INT_SS2A0", - "B_TERM_UTURN_INT_SS2A1", - "B_TERM_UTURN_INT_SS2A2", - "B_TERM_UTURN_INT_SS2A3", - "B_TERM_UTURN_INT_SS2BEG0", - "B_TERM_UTURN_INT_SS2BEG1", - "B_TERM_UTURN_INT_SS2BEG2", - "B_TERM_UTURN_INT_SS2BEG3", - "B_TERM_UTURN_INT_SS6A0", - "B_TERM_UTURN_INT_SS6A1", - "B_TERM_UTURN_INT_SS6A2", - "B_TERM_UTURN_INT_SS6A3", - "B_TERM_UTURN_INT_SS6B0", - "B_TERM_UTURN_INT_SS6B1", - "B_TERM_UTURN_INT_SS6B2", - "B_TERM_UTURN_INT_SS6B3", - "B_TERM_UTURN_INT_SS6BEG0", - "B_TERM_UTURN_INT_SS6BEG1", - "B_TERM_UTURN_INT_SS6BEG2", - "B_TERM_UTURN_INT_SS6BEG3", - "B_TERM_UTURN_INT_SS6C0", - "B_TERM_UTURN_INT_SS6C1", - "B_TERM_UTURN_INT_SS6C2", - "B_TERM_UTURN_INT_SS6C3", - "B_TERM_UTURN_INT_SS6D0", - "B_TERM_UTURN_INT_SS6D1", - "B_TERM_UTURN_INT_SS6D2", - "B_TERM_UTURN_INT_SS6D3", - "B_TERM_UTURN_INT_SS6E0", - "B_TERM_UTURN_INT_SS6E1", - "B_TERM_UTURN_INT_SS6E2", - "B_TERM_UTURN_INT_SS6E3", - "B_TERM_UTURN_INT_SW2BEG0", - "B_TERM_UTURN_INT_SW2BEG1", - "B_TERM_UTURN_INT_SW2BEG2", - "B_TERM_UTURN_INT_SW2BEG3", - "B_TERM_UTURN_INT_SW6A0", - "B_TERM_UTURN_INT_SW6A1", - "B_TERM_UTURN_INT_SW6A2", - "B_TERM_UTURN_INT_SW6A3", - "B_TERM_UTURN_INT_SW6B0", - "B_TERM_UTURN_INT_SW6B1", - "B_TERM_UTURN_INT_SW6B2", - "B_TERM_UTURN_INT_SW6B3", - "B_TERM_UTURN_INT_SW6C0", - "B_TERM_UTURN_INT_SW6C1", - "B_TERM_UTURN_INT_SW6C2", - "B_TERM_UTURN_INT_SW6C3", - "B_TERM_UTURN_INT_SW6D0", - "B_TERM_UTURN_INT_SW6D1", - "B_TERM_UTURN_INT_SW6D2", - "B_TERM_UTURN_INT_SW6D3", - "B_TERM_UTURN_INT_SW6END_N0_3", - "B_TERM_UTURN_INT_WR1BEG0", - "B_TERM_UTURN_INT_WR1END0" - ] + "wires": { + "B_TERM_UTURN_INT_ER1BEG0": null, + "B_TERM_UTURN_INT_ER1END_N3_3": null, + "B_TERM_UTURN_INT_FAN_BOUNCE0": null, + "B_TERM_UTURN_INT_FAN_BOUNCE2": null, + "B_TERM_UTURN_INT_FAN_BOUNCE4": null, + "B_TERM_UTURN_INT_FAN_BOUNCE6": null, + "B_TERM_UTURN_INT_LV18": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB0": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L0": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L1": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L18": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L6": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L7": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L8": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L9": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_SE2BEG0": null, + "B_TERM_UTURN_INT_SE2BEG1": null, + "B_TERM_UTURN_INT_SE2BEG2": null, + "B_TERM_UTURN_INT_SE2BEG3": null, + "B_TERM_UTURN_INT_SE6A0": null, + "B_TERM_UTURN_INT_SE6A1": null, + "B_TERM_UTURN_INT_SE6A2": null, + "B_TERM_UTURN_INT_SE6A3": null, + "B_TERM_UTURN_INT_SE6B0": null, + "B_TERM_UTURN_INT_SE6B1": null, + "B_TERM_UTURN_INT_SE6B2": null, + "B_TERM_UTURN_INT_SE6B3": null, + "B_TERM_UTURN_INT_SE6C0": null, + "B_TERM_UTURN_INT_SE6C1": null, + "B_TERM_UTURN_INT_SE6C2": null, + "B_TERM_UTURN_INT_SE6C3": null, + "B_TERM_UTURN_INT_SE6D0": null, + "B_TERM_UTURN_INT_SE6D1": null, + "B_TERM_UTURN_INT_SE6D2": null, + "B_TERM_UTURN_INT_SE6D3": null, + "B_TERM_UTURN_INT_SL1BEG0": null, + "B_TERM_UTURN_INT_SL1BEG1": null, + "B_TERM_UTURN_INT_SL1BEG2": null, + "B_TERM_UTURN_INT_SL1BEG3": null, + "B_TERM_UTURN_INT_SR1BEG1": null, + "B_TERM_UTURN_INT_SR1BEG2": null, + "B_TERM_UTURN_INT_SR1BEG3": null, + "B_TERM_UTURN_INT_SS2A0": null, + "B_TERM_UTURN_INT_SS2A1": null, + "B_TERM_UTURN_INT_SS2A2": null, + "B_TERM_UTURN_INT_SS2A3": null, + "B_TERM_UTURN_INT_SS2BEG0": null, + "B_TERM_UTURN_INT_SS2BEG1": null, + "B_TERM_UTURN_INT_SS2BEG2": null, + "B_TERM_UTURN_INT_SS2BEG3": null, + "B_TERM_UTURN_INT_SS6A0": null, + "B_TERM_UTURN_INT_SS6A1": null, + "B_TERM_UTURN_INT_SS6A2": null, + "B_TERM_UTURN_INT_SS6A3": null, + "B_TERM_UTURN_INT_SS6B0": null, + "B_TERM_UTURN_INT_SS6B1": null, + "B_TERM_UTURN_INT_SS6B2": null, + "B_TERM_UTURN_INT_SS6B3": null, + "B_TERM_UTURN_INT_SS6BEG0": null, + "B_TERM_UTURN_INT_SS6BEG1": null, + "B_TERM_UTURN_INT_SS6BEG2": null, + "B_TERM_UTURN_INT_SS6BEG3": null, + "B_TERM_UTURN_INT_SS6C0": null, + "B_TERM_UTURN_INT_SS6C1": null, + "B_TERM_UTURN_INT_SS6C2": null, + "B_TERM_UTURN_INT_SS6C3": null, + "B_TERM_UTURN_INT_SS6D0": null, + "B_TERM_UTURN_INT_SS6D1": null, + "B_TERM_UTURN_INT_SS6D2": null, + "B_TERM_UTURN_INT_SS6D3": null, + "B_TERM_UTURN_INT_SS6E0": null, + "B_TERM_UTURN_INT_SS6E1": null, + "B_TERM_UTURN_INT_SS6E2": null, + "B_TERM_UTURN_INT_SS6E3": null, + "B_TERM_UTURN_INT_SW2BEG0": null, + "B_TERM_UTURN_INT_SW2BEG1": null, + "B_TERM_UTURN_INT_SW2BEG2": null, + "B_TERM_UTURN_INT_SW2BEG3": null, + "B_TERM_UTURN_INT_SW6A0": null, + "B_TERM_UTURN_INT_SW6A1": null, + "B_TERM_UTURN_INT_SW6A2": null, + "B_TERM_UTURN_INT_SW6A3": null, + "B_TERM_UTURN_INT_SW6B0": null, + "B_TERM_UTURN_INT_SW6B1": null, + "B_TERM_UTURN_INT_SW6B2": null, + "B_TERM_UTURN_INT_SW6B3": null, + "B_TERM_UTURN_INT_SW6C0": null, + "B_TERM_UTURN_INT_SW6C1": null, + "B_TERM_UTURN_INT_SW6C2": null, + "B_TERM_UTURN_INT_SW6C3": null, + "B_TERM_UTURN_INT_SW6D0": null, + "B_TERM_UTURN_INT_SW6D1": null, + "B_TERM_UTURN_INT_SW6D2": null, + "B_TERM_UTURN_INT_SW6D3": null, + "B_TERM_UTURN_INT_SW6END_N0_3": null, + "B_TERM_UTURN_INT_WR1BEG0": null, + "B_TERM_UTURN_INT_WR1END0": null + } } diff --git a/kintex7/tile_type_BRKH_CLB.json b/kintex7/tile_type_BRKH_CLB.json index 272811f..a128285 100644 --- a/kintex7/tile_type_BRKH_CLB.json +++ b/kintex7/tile_type_BRKH_CLB.json @@ -2,10 +2,22 @@ "pips": {}, "sites": [], "tile_type": "BRKH_CLB", - "wires": [ - "BRKH_CLB_COUT0_L", - "BRKH_CLB_COUT0_R", - "BRKH_CLB_COUT1_L", - "BRKH_CLB_COUT1_R" - ] + "wires": { + "BRKH_CLB_COUT0_L": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_CLB_COUT0_R": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_CLB_COUT1_L": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_CLB_COUT1_R": { + "cap": "1.000", + "res": "0.000" + } + } } diff --git a/kintex7/tile_type_BRKH_CLK.json b/kintex7/tile_type_BRKH_CLK.json index 1d51dea..bae9469 100644 --- a/kintex7/tile_type_BRKH_CLK.json +++ b/kintex7/tile_type_BRKH_CLK.json @@ -2,134 +2,134 @@ "pips": {}, "sites": [], "tile_type": "BRKH_CLK", - "wires": [ - "BRKH_CLK_CK_BUFG_CASC0", - "BRKH_CLK_CK_BUFG_CASC1", - "BRKH_CLK_CK_BUFG_CASC10", - "BRKH_CLK_CK_BUFG_CASC11", - "BRKH_CLK_CK_BUFG_CASC12", - "BRKH_CLK_CK_BUFG_CASC13", - "BRKH_CLK_CK_BUFG_CASC14", - "BRKH_CLK_CK_BUFG_CASC15", - "BRKH_CLK_CK_BUFG_CASC16", - "BRKH_CLK_CK_BUFG_CASC17", - "BRKH_CLK_CK_BUFG_CASC18", - "BRKH_CLK_CK_BUFG_CASC19", - "BRKH_CLK_CK_BUFG_CASC2", - "BRKH_CLK_CK_BUFG_CASC20", - "BRKH_CLK_CK_BUFG_CASC21", - "BRKH_CLK_CK_BUFG_CASC22", - "BRKH_CLK_CK_BUFG_CASC23", - "BRKH_CLK_CK_BUFG_CASC24", - "BRKH_CLK_CK_BUFG_CASC25", - "BRKH_CLK_CK_BUFG_CASC26", - "BRKH_CLK_CK_BUFG_CASC27", - "BRKH_CLK_CK_BUFG_CASC28", - "BRKH_CLK_CK_BUFG_CASC29", - "BRKH_CLK_CK_BUFG_CASC3", - "BRKH_CLK_CK_BUFG_CASC30", - "BRKH_CLK_CK_BUFG_CASC31", - "BRKH_CLK_CK_BUFG_CASC4", - "BRKH_CLK_CK_BUFG_CASC5", - "BRKH_CLK_CK_BUFG_CASC6", - "BRKH_CLK_CK_BUFG_CASC7", - "BRKH_CLK_CK_BUFG_CASC8", - "BRKH_CLK_CK_BUFG_CASC9", - "BRKH_CLK_CK_GCLK0", - "BRKH_CLK_CK_GCLK1", - "BRKH_CLK_CK_GCLK10", - "BRKH_CLK_CK_GCLK11", - "BRKH_CLK_CK_GCLK12", - "BRKH_CLK_CK_GCLK13", - "BRKH_CLK_CK_GCLK14", - "BRKH_CLK_CK_GCLK15", - "BRKH_CLK_CK_GCLK16", - "BRKH_CLK_CK_GCLK17", - "BRKH_CLK_CK_GCLK18", - "BRKH_CLK_CK_GCLK19", - "BRKH_CLK_CK_GCLK2", - "BRKH_CLK_CK_GCLK20", - "BRKH_CLK_CK_GCLK21", - "BRKH_CLK_CK_GCLK22", - "BRKH_CLK_CK_GCLK23", - "BRKH_CLK_CK_GCLK24", - "BRKH_CLK_CK_GCLK25", - "BRKH_CLK_CK_GCLK26", - "BRKH_CLK_CK_GCLK27", - "BRKH_CLK_CK_GCLK28", - "BRKH_CLK_CK_GCLK29", - "BRKH_CLK_CK_GCLK3", - "BRKH_CLK_CK_GCLK30", - "BRKH_CLK_CK_GCLK31", - "BRKH_CLK_CK_GCLK4", - "BRKH_CLK_CK_GCLK5", - "BRKH_CLK_CK_GCLK6", - "BRKH_CLK_CK_GCLK7", - "BRKH_CLK_CK_GCLK8", - "BRKH_CLK_CK_GCLK9", - "BRKH_CLK_R_CK_BUFG_CASC0", - "BRKH_CLK_R_CK_BUFG_CASC1", - "BRKH_CLK_R_CK_BUFG_CASC10", - "BRKH_CLK_R_CK_BUFG_CASC11", - "BRKH_CLK_R_CK_BUFG_CASC12", - "BRKH_CLK_R_CK_BUFG_CASC13", - "BRKH_CLK_R_CK_BUFG_CASC14", - "BRKH_CLK_R_CK_BUFG_CASC15", - "BRKH_CLK_R_CK_BUFG_CASC16", - "BRKH_CLK_R_CK_BUFG_CASC17", - "BRKH_CLK_R_CK_BUFG_CASC18", - "BRKH_CLK_R_CK_BUFG_CASC19", - "BRKH_CLK_R_CK_BUFG_CASC2", - "BRKH_CLK_R_CK_BUFG_CASC20", - "BRKH_CLK_R_CK_BUFG_CASC21", - "BRKH_CLK_R_CK_BUFG_CASC22", - "BRKH_CLK_R_CK_BUFG_CASC23", - "BRKH_CLK_R_CK_BUFG_CASC24", - "BRKH_CLK_R_CK_BUFG_CASC25", - "BRKH_CLK_R_CK_BUFG_CASC26", - "BRKH_CLK_R_CK_BUFG_CASC27", - "BRKH_CLK_R_CK_BUFG_CASC28", - "BRKH_CLK_R_CK_BUFG_CASC29", - "BRKH_CLK_R_CK_BUFG_CASC3", - "BRKH_CLK_R_CK_BUFG_CASC30", - "BRKH_CLK_R_CK_BUFG_CASC31", - "BRKH_CLK_R_CK_BUFG_CASC4", - "BRKH_CLK_R_CK_BUFG_CASC5", - "BRKH_CLK_R_CK_BUFG_CASC6", - "BRKH_CLK_R_CK_BUFG_CASC7", - "BRKH_CLK_R_CK_BUFG_CASC8", - "BRKH_CLK_R_CK_BUFG_CASC9", - "BRKH_CLK_R_CK_GCLK0", - "BRKH_CLK_R_CK_GCLK1", - "BRKH_CLK_R_CK_GCLK10", - "BRKH_CLK_R_CK_GCLK11", - "BRKH_CLK_R_CK_GCLK12", - "BRKH_CLK_R_CK_GCLK13", - "BRKH_CLK_R_CK_GCLK14", - "BRKH_CLK_R_CK_GCLK15", - "BRKH_CLK_R_CK_GCLK16", - "BRKH_CLK_R_CK_GCLK17", - "BRKH_CLK_R_CK_GCLK18", - "BRKH_CLK_R_CK_GCLK19", - "BRKH_CLK_R_CK_GCLK2", - "BRKH_CLK_R_CK_GCLK20", - "BRKH_CLK_R_CK_GCLK21", - "BRKH_CLK_R_CK_GCLK22", - "BRKH_CLK_R_CK_GCLK23", - "BRKH_CLK_R_CK_GCLK24", - "BRKH_CLK_R_CK_GCLK25", - "BRKH_CLK_R_CK_GCLK26", - "BRKH_CLK_R_CK_GCLK27", - "BRKH_CLK_R_CK_GCLK28", - "BRKH_CLK_R_CK_GCLK29", - "BRKH_CLK_R_CK_GCLK3", - "BRKH_CLK_R_CK_GCLK30", - "BRKH_CLK_R_CK_GCLK31", - "BRKH_CLK_R_CK_GCLK4", - "BRKH_CLK_R_CK_GCLK5", - "BRKH_CLK_R_CK_GCLK6", - "BRKH_CLK_R_CK_GCLK7", - "BRKH_CLK_R_CK_GCLK8", - "BRKH_CLK_R_CK_GCLK9" - ] + "wires": { + "BRKH_CLK_CK_BUFG_CASC0": null, + "BRKH_CLK_CK_BUFG_CASC1": null, + "BRKH_CLK_CK_BUFG_CASC10": null, + "BRKH_CLK_CK_BUFG_CASC11": null, + "BRKH_CLK_CK_BUFG_CASC12": null, + "BRKH_CLK_CK_BUFG_CASC13": null, + "BRKH_CLK_CK_BUFG_CASC14": null, + "BRKH_CLK_CK_BUFG_CASC15": null, + "BRKH_CLK_CK_BUFG_CASC16": null, + "BRKH_CLK_CK_BUFG_CASC17": null, + "BRKH_CLK_CK_BUFG_CASC18": null, + "BRKH_CLK_CK_BUFG_CASC19": null, + "BRKH_CLK_CK_BUFG_CASC2": null, + "BRKH_CLK_CK_BUFG_CASC20": null, + "BRKH_CLK_CK_BUFG_CASC21": null, + "BRKH_CLK_CK_BUFG_CASC22": null, + "BRKH_CLK_CK_BUFG_CASC23": null, + "BRKH_CLK_CK_BUFG_CASC24": null, + "BRKH_CLK_CK_BUFG_CASC25": null, + "BRKH_CLK_CK_BUFG_CASC26": null, + "BRKH_CLK_CK_BUFG_CASC27": null, + "BRKH_CLK_CK_BUFG_CASC28": null, + "BRKH_CLK_CK_BUFG_CASC29": null, + "BRKH_CLK_CK_BUFG_CASC3": null, + "BRKH_CLK_CK_BUFG_CASC30": null, + "BRKH_CLK_CK_BUFG_CASC31": null, + "BRKH_CLK_CK_BUFG_CASC4": null, + "BRKH_CLK_CK_BUFG_CASC5": null, + "BRKH_CLK_CK_BUFG_CASC6": null, + "BRKH_CLK_CK_BUFG_CASC7": null, + "BRKH_CLK_CK_BUFG_CASC8": null, + "BRKH_CLK_CK_BUFG_CASC9": null, + "BRKH_CLK_CK_GCLK0": null, + "BRKH_CLK_CK_GCLK1": null, + "BRKH_CLK_CK_GCLK10": null, + "BRKH_CLK_CK_GCLK11": null, + "BRKH_CLK_CK_GCLK12": null, + "BRKH_CLK_CK_GCLK13": null, + "BRKH_CLK_CK_GCLK14": null, + "BRKH_CLK_CK_GCLK15": null, + "BRKH_CLK_CK_GCLK16": null, + "BRKH_CLK_CK_GCLK17": null, + "BRKH_CLK_CK_GCLK18": null, + "BRKH_CLK_CK_GCLK19": null, + "BRKH_CLK_CK_GCLK2": null, + "BRKH_CLK_CK_GCLK20": null, + "BRKH_CLK_CK_GCLK21": null, + "BRKH_CLK_CK_GCLK22": null, + "BRKH_CLK_CK_GCLK23": null, + "BRKH_CLK_CK_GCLK24": null, + "BRKH_CLK_CK_GCLK25": null, + "BRKH_CLK_CK_GCLK26": null, + "BRKH_CLK_CK_GCLK27": null, + "BRKH_CLK_CK_GCLK28": null, + "BRKH_CLK_CK_GCLK29": null, + "BRKH_CLK_CK_GCLK3": null, + "BRKH_CLK_CK_GCLK30": null, + "BRKH_CLK_CK_GCLK31": null, + "BRKH_CLK_CK_GCLK4": null, + "BRKH_CLK_CK_GCLK5": null, + "BRKH_CLK_CK_GCLK6": null, + "BRKH_CLK_CK_GCLK7": null, + "BRKH_CLK_CK_GCLK8": null, + "BRKH_CLK_CK_GCLK9": null, + "BRKH_CLK_R_CK_BUFG_CASC0": null, + "BRKH_CLK_R_CK_BUFG_CASC1": null, + "BRKH_CLK_R_CK_BUFG_CASC10": null, + "BRKH_CLK_R_CK_BUFG_CASC11": null, + "BRKH_CLK_R_CK_BUFG_CASC12": null, + "BRKH_CLK_R_CK_BUFG_CASC13": null, + "BRKH_CLK_R_CK_BUFG_CASC14": null, + "BRKH_CLK_R_CK_BUFG_CASC15": null, + "BRKH_CLK_R_CK_BUFG_CASC16": null, + "BRKH_CLK_R_CK_BUFG_CASC17": null, + "BRKH_CLK_R_CK_BUFG_CASC18": null, + "BRKH_CLK_R_CK_BUFG_CASC19": null, + "BRKH_CLK_R_CK_BUFG_CASC2": null, + "BRKH_CLK_R_CK_BUFG_CASC20": null, + "BRKH_CLK_R_CK_BUFG_CASC21": null, + "BRKH_CLK_R_CK_BUFG_CASC22": null, + "BRKH_CLK_R_CK_BUFG_CASC23": null, + "BRKH_CLK_R_CK_BUFG_CASC24": null, + "BRKH_CLK_R_CK_BUFG_CASC25": null, + "BRKH_CLK_R_CK_BUFG_CASC26": null, + "BRKH_CLK_R_CK_BUFG_CASC27": null, + "BRKH_CLK_R_CK_BUFG_CASC28": null, + "BRKH_CLK_R_CK_BUFG_CASC29": null, + "BRKH_CLK_R_CK_BUFG_CASC3": null, + "BRKH_CLK_R_CK_BUFG_CASC30": null, + "BRKH_CLK_R_CK_BUFG_CASC31": null, + "BRKH_CLK_R_CK_BUFG_CASC4": null, + "BRKH_CLK_R_CK_BUFG_CASC5": null, + "BRKH_CLK_R_CK_BUFG_CASC6": null, + "BRKH_CLK_R_CK_BUFG_CASC7": null, + "BRKH_CLK_R_CK_BUFG_CASC8": null, + "BRKH_CLK_R_CK_BUFG_CASC9": null, + "BRKH_CLK_R_CK_GCLK0": null, + "BRKH_CLK_R_CK_GCLK1": null, + "BRKH_CLK_R_CK_GCLK10": null, + "BRKH_CLK_R_CK_GCLK11": null, + "BRKH_CLK_R_CK_GCLK12": null, + "BRKH_CLK_R_CK_GCLK13": null, + "BRKH_CLK_R_CK_GCLK14": null, + "BRKH_CLK_R_CK_GCLK15": null, + "BRKH_CLK_R_CK_GCLK16": null, + "BRKH_CLK_R_CK_GCLK17": null, + "BRKH_CLK_R_CK_GCLK18": null, + "BRKH_CLK_R_CK_GCLK19": null, + "BRKH_CLK_R_CK_GCLK2": null, + "BRKH_CLK_R_CK_GCLK20": null, + "BRKH_CLK_R_CK_GCLK21": null, + "BRKH_CLK_R_CK_GCLK22": null, + "BRKH_CLK_R_CK_GCLK23": null, + "BRKH_CLK_R_CK_GCLK24": null, + "BRKH_CLK_R_CK_GCLK25": null, + "BRKH_CLK_R_CK_GCLK26": null, + "BRKH_CLK_R_CK_GCLK27": null, + "BRKH_CLK_R_CK_GCLK28": null, + "BRKH_CLK_R_CK_GCLK29": null, + "BRKH_CLK_R_CK_GCLK3": null, + "BRKH_CLK_R_CK_GCLK30": null, + "BRKH_CLK_R_CK_GCLK31": null, + "BRKH_CLK_R_CK_GCLK4": null, + "BRKH_CLK_R_CK_GCLK5": null, + "BRKH_CLK_R_CK_GCLK6": null, + "BRKH_CLK_R_CK_GCLK7": null, + "BRKH_CLK_R_CK_GCLK8": null, + "BRKH_CLK_R_CK_GCLK9": null + } } diff --git a/kintex7/tile_type_BRKH_CMT.json b/kintex7/tile_type_BRKH_CMT.json index 6c4fd76..ef7cb17 100644 --- a/kintex7/tile_type_BRKH_CMT.json +++ b/kintex7/tile_type_BRKH_CMT.json @@ -2,15 +2,15 @@ "pips": {}, "sites": [], "tile_type": "BRKH_CMT", - "wires": [ - "BRKH_CMT_FREQ_REF_NS0", - "BRKH_CMT_FREQ_REF_NS1", - "BRKH_CMT_FREQ_REF_NS2", - "BRKH_CMT_FREQ_REF_NS3", - "BRKH_CMT_PHASEREF0", - "BRKH_CMT_PHASEREF1", - "BRKH_CMT_PHASEREF_BELOW0", - "BRKH_CMT_PHASEREF_BELOW1", - "BRKH_CMT_PHYCTRL_SYNC_BB" - ] + "wires": { + "BRKH_CMT_FREQ_REF_NS0": null, + "BRKH_CMT_FREQ_REF_NS1": null, + "BRKH_CMT_FREQ_REF_NS2": null, + "BRKH_CMT_FREQ_REF_NS3": null, + "BRKH_CMT_PHASEREF0": null, + "BRKH_CMT_PHASEREF1": null, + "BRKH_CMT_PHASEREF_BELOW0": null, + "BRKH_CMT_PHASEREF_BELOW1": null, + "BRKH_CMT_PHYCTRL_SYNC_BB": null + } } diff --git a/kintex7/tile_type_BRKH_DSP_L.json b/kintex7/tile_type_BRKH_DSP_L.json index c975252..edfe4f3 100644 --- a/kintex7/tile_type_BRKH_DSP_L.json +++ b/kintex7/tile_type_BRKH_DSP_L.json @@ -2,104 +2,104 @@ "pips": {}, "sites": [], "tile_type": "BRKH_DSP_L", - "wires": [ - "BRKH_DSP_ACIN0", - "BRKH_DSP_ACIN1", - "BRKH_DSP_ACIN10", - "BRKH_DSP_ACIN11", - "BRKH_DSP_ACIN12", - "BRKH_DSP_ACIN13", - "BRKH_DSP_ACIN14", - "BRKH_DSP_ACIN15", - "BRKH_DSP_ACIN16", - "BRKH_DSP_ACIN17", - "BRKH_DSP_ACIN18", - "BRKH_DSP_ACIN19", - "BRKH_DSP_ACIN2", - "BRKH_DSP_ACIN20", - "BRKH_DSP_ACIN21", - "BRKH_DSP_ACIN22", - "BRKH_DSP_ACIN23", - "BRKH_DSP_ACIN24", - "BRKH_DSP_ACIN25", - "BRKH_DSP_ACIN26", - "BRKH_DSP_ACIN27", - "BRKH_DSP_ACIN28", - "BRKH_DSP_ACIN29", - "BRKH_DSP_ACIN3", - "BRKH_DSP_ACIN4", - "BRKH_DSP_ACIN5", - "BRKH_DSP_ACIN6", - "BRKH_DSP_ACIN7", - "BRKH_DSP_ACIN8", - "BRKH_DSP_ACIN9", - "BRKH_DSP_BCIN0", - "BRKH_DSP_BCIN1", - "BRKH_DSP_BCIN10", - "BRKH_DSP_BCIN11", - "BRKH_DSP_BCIN12", - "BRKH_DSP_BCIN13", - "BRKH_DSP_BCIN14", - "BRKH_DSP_BCIN15", - "BRKH_DSP_BCIN16", - "BRKH_DSP_BCIN17", - "BRKH_DSP_BCIN2", - "BRKH_DSP_BCIN3", - "BRKH_DSP_BCIN4", - "BRKH_DSP_BCIN5", - "BRKH_DSP_BCIN6", - "BRKH_DSP_BCIN7", - "BRKH_DSP_BCIN8", - "BRKH_DSP_BCIN9", - "BRKH_DSP_CARRYCASCIN", - "BRKH_DSP_MULTSIGNIN", - "BRKH_DSP_PCIN0", - "BRKH_DSP_PCIN1", - "BRKH_DSP_PCIN10", - "BRKH_DSP_PCIN11", - "BRKH_DSP_PCIN12", - "BRKH_DSP_PCIN13", - "BRKH_DSP_PCIN14", - "BRKH_DSP_PCIN15", - "BRKH_DSP_PCIN16", - "BRKH_DSP_PCIN17", - "BRKH_DSP_PCIN18", - "BRKH_DSP_PCIN19", - "BRKH_DSP_PCIN2", - "BRKH_DSP_PCIN20", - "BRKH_DSP_PCIN21", - "BRKH_DSP_PCIN22", - "BRKH_DSP_PCIN23", - "BRKH_DSP_PCIN24", - "BRKH_DSP_PCIN25", - "BRKH_DSP_PCIN26", - "BRKH_DSP_PCIN27", - "BRKH_DSP_PCIN28", - "BRKH_DSP_PCIN29", - "BRKH_DSP_PCIN3", - "BRKH_DSP_PCIN30", - "BRKH_DSP_PCIN31", - "BRKH_DSP_PCIN32", - "BRKH_DSP_PCIN33", - "BRKH_DSP_PCIN34", - "BRKH_DSP_PCIN35", - "BRKH_DSP_PCIN36", - "BRKH_DSP_PCIN37", - "BRKH_DSP_PCIN38", - "BRKH_DSP_PCIN39", - "BRKH_DSP_PCIN4", - "BRKH_DSP_PCIN40", - "BRKH_DSP_PCIN41", - "BRKH_DSP_PCIN42", - "BRKH_DSP_PCIN43", - "BRKH_DSP_PCIN44", - "BRKH_DSP_PCIN45", - "BRKH_DSP_PCIN46", - "BRKH_DSP_PCIN47", - "BRKH_DSP_PCIN5", - "BRKH_DSP_PCIN6", - "BRKH_DSP_PCIN7", - "BRKH_DSP_PCIN8", - "BRKH_DSP_PCIN9" - ] + "wires": { + "BRKH_DSP_ACIN0": null, + "BRKH_DSP_ACIN1": null, + "BRKH_DSP_ACIN10": null, + "BRKH_DSP_ACIN11": null, + "BRKH_DSP_ACIN12": null, + "BRKH_DSP_ACIN13": null, + "BRKH_DSP_ACIN14": null, + "BRKH_DSP_ACIN15": null, + "BRKH_DSP_ACIN16": null, + "BRKH_DSP_ACIN17": null, + "BRKH_DSP_ACIN18": null, + "BRKH_DSP_ACIN19": null, + "BRKH_DSP_ACIN2": null, + "BRKH_DSP_ACIN20": null, + "BRKH_DSP_ACIN21": null, + "BRKH_DSP_ACIN22": null, + "BRKH_DSP_ACIN23": null, + "BRKH_DSP_ACIN24": null, + "BRKH_DSP_ACIN25": null, + "BRKH_DSP_ACIN26": null, + "BRKH_DSP_ACIN27": null, + "BRKH_DSP_ACIN28": null, + "BRKH_DSP_ACIN29": null, + "BRKH_DSP_ACIN3": null, + "BRKH_DSP_ACIN4": null, + "BRKH_DSP_ACIN5": null, + "BRKH_DSP_ACIN6": null, + "BRKH_DSP_ACIN7": null, + "BRKH_DSP_ACIN8": null, + "BRKH_DSP_ACIN9": null, + "BRKH_DSP_BCIN0": null, + "BRKH_DSP_BCIN1": null, + "BRKH_DSP_BCIN10": null, + "BRKH_DSP_BCIN11": null, + "BRKH_DSP_BCIN12": null, + "BRKH_DSP_BCIN13": null, + "BRKH_DSP_BCIN14": null, + "BRKH_DSP_BCIN15": null, + "BRKH_DSP_BCIN16": null, + "BRKH_DSP_BCIN17": null, + "BRKH_DSP_BCIN2": null, + "BRKH_DSP_BCIN3": null, + "BRKH_DSP_BCIN4": null, + "BRKH_DSP_BCIN5": null, + "BRKH_DSP_BCIN6": null, + "BRKH_DSP_BCIN7": null, + "BRKH_DSP_BCIN8": null, + "BRKH_DSP_BCIN9": null, + "BRKH_DSP_CARRYCASCIN": null, + "BRKH_DSP_MULTSIGNIN": null, + "BRKH_DSP_PCIN0": null, + "BRKH_DSP_PCIN1": null, + "BRKH_DSP_PCIN10": null, + "BRKH_DSP_PCIN11": null, + "BRKH_DSP_PCIN12": null, + "BRKH_DSP_PCIN13": null, + "BRKH_DSP_PCIN14": null, + "BRKH_DSP_PCIN15": null, + "BRKH_DSP_PCIN16": null, + "BRKH_DSP_PCIN17": null, + "BRKH_DSP_PCIN18": null, + "BRKH_DSP_PCIN19": null, + "BRKH_DSP_PCIN2": null, + "BRKH_DSP_PCIN20": null, + "BRKH_DSP_PCIN21": null, + "BRKH_DSP_PCIN22": null, + "BRKH_DSP_PCIN23": null, + "BRKH_DSP_PCIN24": null, + "BRKH_DSP_PCIN25": null, + "BRKH_DSP_PCIN26": null, + "BRKH_DSP_PCIN27": null, + "BRKH_DSP_PCIN28": null, + "BRKH_DSP_PCIN29": null, + "BRKH_DSP_PCIN3": null, + "BRKH_DSP_PCIN30": null, + "BRKH_DSP_PCIN31": null, + "BRKH_DSP_PCIN32": null, + "BRKH_DSP_PCIN33": null, + "BRKH_DSP_PCIN34": null, + "BRKH_DSP_PCIN35": null, + "BRKH_DSP_PCIN36": null, + "BRKH_DSP_PCIN37": null, + "BRKH_DSP_PCIN38": null, + "BRKH_DSP_PCIN39": null, + "BRKH_DSP_PCIN4": null, + "BRKH_DSP_PCIN40": null, + "BRKH_DSP_PCIN41": null, + "BRKH_DSP_PCIN42": null, + "BRKH_DSP_PCIN43": null, + "BRKH_DSP_PCIN44": null, + "BRKH_DSP_PCIN45": null, + "BRKH_DSP_PCIN46": null, + "BRKH_DSP_PCIN47": null, + "BRKH_DSP_PCIN5": null, + "BRKH_DSP_PCIN6": null, + "BRKH_DSP_PCIN7": null, + "BRKH_DSP_PCIN8": null, + "BRKH_DSP_PCIN9": null + } } diff --git a/kintex7/tile_type_BRKH_DSP_R.json b/kintex7/tile_type_BRKH_DSP_R.json index b7ac207..42d27f4 100644 --- a/kintex7/tile_type_BRKH_DSP_R.json +++ b/kintex7/tile_type_BRKH_DSP_R.json @@ -2,104 +2,104 @@ "pips": {}, "sites": [], "tile_type": "BRKH_DSP_R", - "wires": [ - "BRKH_DSP_ACIN0", - "BRKH_DSP_ACIN1", - "BRKH_DSP_ACIN10", - "BRKH_DSP_ACIN11", - "BRKH_DSP_ACIN12", - "BRKH_DSP_ACIN13", - "BRKH_DSP_ACIN14", - "BRKH_DSP_ACIN15", - "BRKH_DSP_ACIN16", - "BRKH_DSP_ACIN17", - "BRKH_DSP_ACIN18", - "BRKH_DSP_ACIN19", - "BRKH_DSP_ACIN2", - "BRKH_DSP_ACIN20", - "BRKH_DSP_ACIN21", - "BRKH_DSP_ACIN22", - "BRKH_DSP_ACIN23", - "BRKH_DSP_ACIN24", - "BRKH_DSP_ACIN25", - "BRKH_DSP_ACIN26", - "BRKH_DSP_ACIN27", - "BRKH_DSP_ACIN28", - "BRKH_DSP_ACIN29", - "BRKH_DSP_ACIN3", - "BRKH_DSP_ACIN4", - "BRKH_DSP_ACIN5", - "BRKH_DSP_ACIN6", - "BRKH_DSP_ACIN7", - "BRKH_DSP_ACIN8", - "BRKH_DSP_ACIN9", - "BRKH_DSP_BCIN0", - "BRKH_DSP_BCIN1", - "BRKH_DSP_BCIN10", - "BRKH_DSP_BCIN11", - "BRKH_DSP_BCIN12", - "BRKH_DSP_BCIN13", - "BRKH_DSP_BCIN14", - "BRKH_DSP_BCIN15", - "BRKH_DSP_BCIN16", - "BRKH_DSP_BCIN17", - "BRKH_DSP_BCIN2", - "BRKH_DSP_BCIN3", - "BRKH_DSP_BCIN4", - "BRKH_DSP_BCIN5", - "BRKH_DSP_BCIN6", - "BRKH_DSP_BCIN7", - "BRKH_DSP_BCIN8", - "BRKH_DSP_BCIN9", - "BRKH_DSP_CARRYCASCIN", - "BRKH_DSP_MULTSIGNIN", - "BRKH_DSP_PCIN0", - "BRKH_DSP_PCIN1", - "BRKH_DSP_PCIN10", - "BRKH_DSP_PCIN11", - "BRKH_DSP_PCIN12", - "BRKH_DSP_PCIN13", - "BRKH_DSP_PCIN14", - "BRKH_DSP_PCIN15", - "BRKH_DSP_PCIN16", - "BRKH_DSP_PCIN17", - "BRKH_DSP_PCIN18", - "BRKH_DSP_PCIN19", - "BRKH_DSP_PCIN2", - "BRKH_DSP_PCIN20", - "BRKH_DSP_PCIN21", - "BRKH_DSP_PCIN22", - "BRKH_DSP_PCIN23", - "BRKH_DSP_PCIN24", - "BRKH_DSP_PCIN25", - "BRKH_DSP_PCIN26", - "BRKH_DSP_PCIN27", - "BRKH_DSP_PCIN28", - "BRKH_DSP_PCIN29", - "BRKH_DSP_PCIN3", - "BRKH_DSP_PCIN30", - "BRKH_DSP_PCIN31", - "BRKH_DSP_PCIN32", - "BRKH_DSP_PCIN33", - "BRKH_DSP_PCIN34", - "BRKH_DSP_PCIN35", - "BRKH_DSP_PCIN36", - "BRKH_DSP_PCIN37", - "BRKH_DSP_PCIN38", - "BRKH_DSP_PCIN39", - "BRKH_DSP_PCIN4", - "BRKH_DSP_PCIN40", - "BRKH_DSP_PCIN41", - "BRKH_DSP_PCIN42", - "BRKH_DSP_PCIN43", - "BRKH_DSP_PCIN44", - "BRKH_DSP_PCIN45", - "BRKH_DSP_PCIN46", - "BRKH_DSP_PCIN47", - "BRKH_DSP_PCIN5", - "BRKH_DSP_PCIN6", - "BRKH_DSP_PCIN7", - "BRKH_DSP_PCIN8", - "BRKH_DSP_PCIN9" - ] + "wires": { + "BRKH_DSP_ACIN0": null, + "BRKH_DSP_ACIN1": null, + "BRKH_DSP_ACIN10": null, + "BRKH_DSP_ACIN11": null, + "BRKH_DSP_ACIN12": null, + "BRKH_DSP_ACIN13": null, + "BRKH_DSP_ACIN14": null, + "BRKH_DSP_ACIN15": null, + "BRKH_DSP_ACIN16": null, + "BRKH_DSP_ACIN17": null, + "BRKH_DSP_ACIN18": null, + "BRKH_DSP_ACIN19": null, + "BRKH_DSP_ACIN2": null, + "BRKH_DSP_ACIN20": null, + "BRKH_DSP_ACIN21": null, + "BRKH_DSP_ACIN22": null, + "BRKH_DSP_ACIN23": null, + "BRKH_DSP_ACIN24": null, + "BRKH_DSP_ACIN25": null, + "BRKH_DSP_ACIN26": null, + "BRKH_DSP_ACIN27": null, + "BRKH_DSP_ACIN28": null, + "BRKH_DSP_ACIN29": null, + "BRKH_DSP_ACIN3": null, + "BRKH_DSP_ACIN4": null, + "BRKH_DSP_ACIN5": null, + "BRKH_DSP_ACIN6": null, + "BRKH_DSP_ACIN7": null, + "BRKH_DSP_ACIN8": null, + "BRKH_DSP_ACIN9": null, + "BRKH_DSP_BCIN0": null, + "BRKH_DSP_BCIN1": null, + "BRKH_DSP_BCIN10": null, + "BRKH_DSP_BCIN11": null, + "BRKH_DSP_BCIN12": null, + "BRKH_DSP_BCIN13": null, + "BRKH_DSP_BCIN14": null, + "BRKH_DSP_BCIN15": null, + "BRKH_DSP_BCIN16": null, + "BRKH_DSP_BCIN17": null, + "BRKH_DSP_BCIN2": null, + "BRKH_DSP_BCIN3": null, + "BRKH_DSP_BCIN4": null, + "BRKH_DSP_BCIN5": null, + "BRKH_DSP_BCIN6": null, + "BRKH_DSP_BCIN7": null, + "BRKH_DSP_BCIN8": null, + "BRKH_DSP_BCIN9": null, + "BRKH_DSP_CARRYCASCIN": null, + "BRKH_DSP_MULTSIGNIN": null, + "BRKH_DSP_PCIN0": null, + "BRKH_DSP_PCIN1": null, + "BRKH_DSP_PCIN10": null, + "BRKH_DSP_PCIN11": null, + "BRKH_DSP_PCIN12": null, + "BRKH_DSP_PCIN13": null, + "BRKH_DSP_PCIN14": null, + "BRKH_DSP_PCIN15": null, + "BRKH_DSP_PCIN16": null, + "BRKH_DSP_PCIN17": null, + "BRKH_DSP_PCIN18": null, + "BRKH_DSP_PCIN19": null, + "BRKH_DSP_PCIN2": null, + "BRKH_DSP_PCIN20": null, + "BRKH_DSP_PCIN21": null, + "BRKH_DSP_PCIN22": null, + "BRKH_DSP_PCIN23": null, + "BRKH_DSP_PCIN24": null, + "BRKH_DSP_PCIN25": null, + "BRKH_DSP_PCIN26": null, + "BRKH_DSP_PCIN27": null, + "BRKH_DSP_PCIN28": null, + "BRKH_DSP_PCIN29": null, + "BRKH_DSP_PCIN3": null, + "BRKH_DSP_PCIN30": null, + "BRKH_DSP_PCIN31": null, + "BRKH_DSP_PCIN32": null, + "BRKH_DSP_PCIN33": null, + "BRKH_DSP_PCIN34": null, + "BRKH_DSP_PCIN35": null, + "BRKH_DSP_PCIN36": null, + "BRKH_DSP_PCIN37": null, + "BRKH_DSP_PCIN38": null, + "BRKH_DSP_PCIN39": null, + "BRKH_DSP_PCIN4": null, + "BRKH_DSP_PCIN40": null, + "BRKH_DSP_PCIN41": null, + "BRKH_DSP_PCIN42": null, + "BRKH_DSP_PCIN43": null, + "BRKH_DSP_PCIN44": null, + "BRKH_DSP_PCIN45": null, + "BRKH_DSP_PCIN46": null, + "BRKH_DSP_PCIN47": null, + "BRKH_DSP_PCIN5": null, + "BRKH_DSP_PCIN6": null, + "BRKH_DSP_PCIN7": null, + "BRKH_DSP_PCIN8": null, + "BRKH_DSP_PCIN9": null + } } diff --git a/kintex7/tile_type_BRKH_GTX.json b/kintex7/tile_type_BRKH_GTX.json index b271f6b..0df3514 100644 --- a/kintex7/tile_type_BRKH_GTX.json +++ b/kintex7/tile_type_BRKH_GTX.json @@ -2,103 +2,235 @@ "pips": { "BRKH_GTX.BRKH_GTX_NORTHREFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_NORTHREFCLK0_LOWER" }, "BRKH_GTX.BRKH_GTX_NORTHREFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_NORTHREFCLK1_LOWER" }, "BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_REFCLK0_LOWER" }, "BRKH_GTX.BRKH_GTX_REFCLK0_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_REFCLK0_LOWER" }, "BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_REFCLK0_UPPER" }, "BRKH_GTX.BRKH_GTX_REFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_REFCLK0_UPPER" }, "BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK0_UPPER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_NORTHREFCLK0_UPPER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_REFCLK1_LOWER" }, "BRKH_GTX.BRKH_GTX_REFCLK1_LOWER->BRKH_GTX_NORTHREFCLK1_UPPER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_NORTHREFCLK1_UPPER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_REFCLK1_LOWER" }, "BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_REFCLK1_UPPER" }, "BRKH_GTX.BRKH_GTX_REFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_REFCLK1_UPPER" }, "BRKH_GTX.BRKH_GTX_SOUTHREFCLK0_UPPER->BRKH_GTX_SOUTHREFCLK0_LOWER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_SOUTHREFCLK0_LOWER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_SOUTHREFCLK0_UPPER" }, "BRKH_GTX.BRKH_GTX_SOUTHREFCLK1_UPPER->BRKH_GTX_SOUTHREFCLK1_LOWER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "BRKH_GTX_SOUTHREFCLK1_LOWER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "BRKH_GTX_SOUTHREFCLK1_UPPER" } }, "sites": [], "tile_type": "BRKH_GTX", - "wires": [ - "BRKH_GTX_NORTHREFCLK0_LOWER", - "BRKH_GTX_NORTHREFCLK0_UPPER", - "BRKH_GTX_NORTHREFCLK1_LOWER", - "BRKH_GTX_NORTHREFCLK1_UPPER", - "BRKH_GTX_REFCLK0_LOWER", - "BRKH_GTX_REFCLK0_UPPER", - "BRKH_GTX_REFCLK1_LOWER", - "BRKH_GTX_REFCLK1_UPPER", - "BRKH_GTX_SOUTHREFCLK0_LOWER", - "BRKH_GTX_SOUTHREFCLK0_UPPER", - "BRKH_GTX_SOUTHREFCLK1_LOWER", - "BRKH_GTX_SOUTHREFCLK1_UPPER" - ] + "wires": { + "BRKH_GTX_NORTHREFCLK0_LOWER": null, + "BRKH_GTX_NORTHREFCLK0_UPPER": null, + "BRKH_GTX_NORTHREFCLK1_LOWER": null, + "BRKH_GTX_NORTHREFCLK1_UPPER": null, + "BRKH_GTX_REFCLK0_LOWER": null, + "BRKH_GTX_REFCLK0_UPPER": null, + "BRKH_GTX_REFCLK1_LOWER": null, + "BRKH_GTX_REFCLK1_UPPER": null, + "BRKH_GTX_SOUTHREFCLK0_LOWER": null, + "BRKH_GTX_SOUTHREFCLK0_UPPER": null, + "BRKH_GTX_SOUTHREFCLK1_LOWER": null, + "BRKH_GTX_SOUTHREFCLK1_UPPER": null + } } diff --git a/kintex7/tile_type_BRKH_INT.json b/kintex7/tile_type_BRKH_INT.json index 124110a..cac3112 100644 --- a/kintex7/tile_type_BRKH_INT.json +++ b/kintex7/tile_type_BRKH_INT.json @@ -2,366 +2,1353 @@ "pips": { "BRKH_INT.BRKH_INT_NL1BEG0->>BRKH_INT_NL1BEG0_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NL1BEG0_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "src_wire": "BRKH_INT_NL1BEG0" }, "BRKH_INT.BRKH_INT_NL1BEG1->>BRKH_INT_NL1BEG1_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NL1BEG1_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "src_wire": "BRKH_INT_NL1BEG1" }, "BRKH_INT.BRKH_INT_NL1BEG2->>BRKH_INT_NL1BEG2_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NL1BEG2_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "src_wire": "BRKH_INT_NL1BEG2" }, "BRKH_INT.BRKH_INT_NR1BEG0->>BRKH_INT_NR1BEG0_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NR1BEG0_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "src_wire": "BRKH_INT_NR1BEG0" }, "BRKH_INT.BRKH_INT_NR1BEG1->>BRKH_INT_NR1BEG1_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NR1BEG1_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "src_wire": "BRKH_INT_NR1BEG1" }, "BRKH_INT.BRKH_INT_NR1BEG2->>BRKH_INT_NR1BEG2_SLOW": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "dst_wire": "BRKH_INT_NR1BEG2_SLOW", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, 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"in_cap": "2.222", + "res": "424.875" + }, "dst_wire": "BRKH_INT_SR1END2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "src_wire": "BRKH_INT_SR1END2_SLOW" }, "BRKH_INT.BRKH_INT_SR1END3_SLOW->>BRKH_INT_SR1END3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "dst_wire": "BRKH_INT_SR1END3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.181", + "0.206", + "0.233" + ], + "in_cap": "2.222", + "res": "424.875" + }, "src_wire": "BRKH_INT_SR1END3_SLOW" } }, "sites": [], "tile_type": "BRKH_INT", - "wires": [ - "BRKH_INT_BYP_BOUNCE2", - "BRKH_INT_BYP_BOUNCE3", - "BRKH_INT_BYP_BOUNCE6", - "BRKH_INT_BYP_BOUNCE7", - "BRKH_INT_EL1BEG3", - "BRKH_INT_EL1END_S3_0", - "BRKH_INT_ER1BEG_S0", - "BRKH_INT_ER1END3", - "BRKH_INT_FAN_BOUNCE_S3_0", - "BRKH_INT_FAN_BOUNCE_S3_2", - "BRKH_INT_FAN_BOUNCE_S3_4", - "BRKH_INT_FAN_BOUNCE_S3_6", - "BRKH_INT_LV0", - "BRKH_INT_LV1", - "BRKH_INT_LV10", - "BRKH_INT_LV11", - "BRKH_INT_LV12", - "BRKH_INT_LV13", - "BRKH_INT_LV14", - "BRKH_INT_LV15", - "BRKH_INT_LV16", - "BRKH_INT_LV17", - "BRKH_INT_LV2", - "BRKH_INT_LV3", - "BRKH_INT_LV4", - "BRKH_INT_LV5", - "BRKH_INT_LV6", - "BRKH_INT_LV7", - "BRKH_INT_LV8", - "BRKH_INT_LV9", - "BRKH_INT_LVB1", - "BRKH_INT_LVB10", - "BRKH_INT_LVB11", - "BRKH_INT_LVB12", - "BRKH_INT_LVB2", - "BRKH_INT_LVB3", - "BRKH_INT_LVB4", - "BRKH_INT_LVB5", - "BRKH_INT_LVB6", - "BRKH_INT_LVB7", - "BRKH_INT_LVB8", - "BRKH_INT_LVB9", - "BRKH_INT_LVB_L1", - "BRKH_INT_LVB_L10", - "BRKH_INT_LVB_L11", - "BRKH_INT_LVB_L12", - "BRKH_INT_LVB_L2", - "BRKH_INT_LVB_L3", - "BRKH_INT_LVB_L4", - "BRKH_INT_LVB_L5", - "BRKH_INT_LVB_L6", - "BRKH_INT_LVB_L7", - "BRKH_INT_LVB_L8", - "BRKH_INT_LVB_L9", - "BRKH_INT_L_LV0", - "BRKH_INT_L_LV1", - "BRKH_INT_L_LV10", - "BRKH_INT_L_LV11", - "BRKH_INT_L_LV12", - "BRKH_INT_L_LV13", - "BRKH_INT_L_LV14", - "BRKH_INT_L_LV15", - "BRKH_INT_L_LV16", - "BRKH_INT_L_LV17", - "BRKH_INT_L_LV2", - "BRKH_INT_L_LV3", - "BRKH_INT_L_LV4", - "BRKH_INT_L_LV5", - "BRKH_INT_L_LV6", - "BRKH_INT_L_LV7", - "BRKH_INT_L_LV8", - "BRKH_INT_L_LV9", - "BRKH_INT_NE2BEG0", - "BRKH_INT_NE2BEG1", - "BRKH_INT_NE2BEG2", - "BRKH_INT_NE2BEG3", - "BRKH_INT_NE2END_S3_0", - "BRKH_INT_NE6A0", - "BRKH_INT_NE6A1", - "BRKH_INT_NE6A2", - "BRKH_INT_NE6A3", - "BRKH_INT_NE6B0", - "BRKH_INT_NE6B1", - "BRKH_INT_NE6B2", - "BRKH_INT_NE6B3", - "BRKH_INT_NE6C0", - "BRKH_INT_NE6C1", - "BRKH_INT_NE6C2", - "BRKH_INT_NE6C3", - "BRKH_INT_NE6D0", - "BRKH_INT_NE6D1", - "BRKH_INT_NE6D2", - "BRKH_INT_NE6D3", - "BRKH_INT_NL1BEG0", - "BRKH_INT_NL1BEG0_SLOW", - "BRKH_INT_NL1BEG1", - "BRKH_INT_NL1BEG1_SLOW", - "BRKH_INT_NL1BEG2", - "BRKH_INT_NL1BEG2_SLOW", - "BRKH_INT_NL1END_S3_0", - "BRKH_INT_NN2A0", - "BRKH_INT_NN2A1", - "BRKH_INT_NN2A2", - "BRKH_INT_NN2A3", - "BRKH_INT_NN2BEG0", - "BRKH_INT_NN2BEG1", - "BRKH_INT_NN2BEG2", - "BRKH_INT_NN2BEG3", - "BRKH_INT_NN2END_S2_0", - "BRKH_INT_NN6A0", - "BRKH_INT_NN6A1", - "BRKH_INT_NN6A2", - "BRKH_INT_NN6A3", - "BRKH_INT_NN6B0", - "BRKH_INT_NN6B1", - "BRKH_INT_NN6B2", - "BRKH_INT_NN6B3", - "BRKH_INT_NN6BEG0", - "BRKH_INT_NN6BEG1", - "BRKH_INT_NN6BEG2", - "BRKH_INT_NN6BEG3", - "BRKH_INT_NN6C0", - "BRKH_INT_NN6C1", - "BRKH_INT_NN6C2", - "BRKH_INT_NN6C3", - "BRKH_INT_NN6D0", - "BRKH_INT_NN6D1", - "BRKH_INT_NN6D2", - "BRKH_INT_NN6D3", - "BRKH_INT_NN6E0", - "BRKH_INT_NN6E1", - "BRKH_INT_NN6E2", - "BRKH_INT_NN6E3", - "BRKH_INT_NN6END_S1_0", - "BRKH_INT_NR1BEG0", - "BRKH_INT_NR1BEG0_SLOW", - "BRKH_INT_NR1BEG1", - "BRKH_INT_NR1BEG1_SLOW", - "BRKH_INT_NR1BEG2", - "BRKH_INT_NR1BEG2_SLOW", - "BRKH_INT_NR1BEG3", - "BRKH_INT_NR1BEG3_SLOW", - "BRKH_INT_NW2BEG0", - "BRKH_INT_NW2BEG1", - "BRKH_INT_NW2BEG2", - "BRKH_INT_NW2BEG3", - "BRKH_INT_NW2END_S0_0", - "BRKH_INT_NW6A0", - "BRKH_INT_NW6A1", - "BRKH_INT_NW6A2", - "BRKH_INT_NW6A3", - "BRKH_INT_NW6B0", - "BRKH_INT_NW6B1", - "BRKH_INT_NW6B2", - "BRKH_INT_NW6B3", - "BRKH_INT_NW6C0", - "BRKH_INT_NW6C1", - "BRKH_INT_NW6C2", - "BRKH_INT_NW6C3", - "BRKH_INT_NW6D0", - "BRKH_INT_NW6D1", - "BRKH_INT_NW6D2", - "BRKH_INT_NW6D3", - "BRKH_INT_NW6END_S0_0", - "BRKH_INT_SE2A0", - "BRKH_INT_SE2A1", - "BRKH_INT_SE2A2", - "BRKH_INT_SE2A3", - "BRKH_INT_SE6B0", - "BRKH_INT_SE6B1", - "BRKH_INT_SE6B2", - "BRKH_INT_SE6B3", - "BRKH_INT_SE6C0", - "BRKH_INT_SE6C1", - "BRKH_INT_SE6C2", - "BRKH_INT_SE6C3", - "BRKH_INT_SE6D0", - "BRKH_INT_SE6D1", - "BRKH_INT_SE6D2", - "BRKH_INT_SE6D3", - "BRKH_INT_SE6E0", - "BRKH_INT_SE6E1", - "BRKH_INT_SE6E2", - "BRKH_INT_SE6E3", - "BRKH_INT_SL1END0", - "BRKH_INT_SL1END0_SLOW", - "BRKH_INT_SL1END1", - "BRKH_INT_SL1END1_SLOW", - "BRKH_INT_SL1END2", - "BRKH_INT_SL1END2_SLOW", - "BRKH_INT_SL1END3", - "BRKH_INT_SL1END3_SLOW", - "BRKH_INT_SR1END1", - "BRKH_INT_SR1END1_SLOW", - "BRKH_INT_SR1END2", - "BRKH_INT_SR1END2_SLOW", - "BRKH_INT_SR1END3", - "BRKH_INT_SR1END3_SLOW", - "BRKH_INT_SR1END_N3_3", - "BRKH_INT_SS2A0", - "BRKH_INT_SS2A1", - "BRKH_INT_SS2A2", - "BRKH_INT_SS2A3", - "BRKH_INT_SS2END0", - "BRKH_INT_SS2END1", - "BRKH_INT_SS2END2", - "BRKH_INT_SS2END3", - "BRKH_INT_SS2END_N0_3", - "BRKH_INT_SS6A0", - "BRKH_INT_SS6A1", - "BRKH_INT_SS6A2", - "BRKH_INT_SS6A3", - "BRKH_INT_SS6B0", - "BRKH_INT_SS6B1", - "BRKH_INT_SS6B2", - "BRKH_INT_SS6B3", - "BRKH_INT_SS6C0", - "BRKH_INT_SS6C1", - "BRKH_INT_SS6C2", - "BRKH_INT_SS6C3", - "BRKH_INT_SS6D0", - "BRKH_INT_SS6D1", - "BRKH_INT_SS6D2", - "BRKH_INT_SS6D3", - "BRKH_INT_SS6E0", - "BRKH_INT_SS6E1", - "BRKH_INT_SS6E2", - "BRKH_INT_SS6E3", - "BRKH_INT_SS6END0", - "BRKH_INT_SS6END1", - "BRKH_INT_SS6END2", - "BRKH_INT_SS6END3", - "BRKH_INT_SS6END_N0_3", - "BRKH_INT_SW2A0", - "BRKH_INT_SW2A1", - "BRKH_INT_SW2A2", - "BRKH_INT_SW2A3", - "BRKH_INT_SW2END3", - "BRKH_INT_SW6B0", - "BRKH_INT_SW6B1", - "BRKH_INT_SW6B2", - "BRKH_INT_SW6B3", - "BRKH_INT_SW6C0", - "BRKH_INT_SW6C1", - "BRKH_INT_SW6C2", - "BRKH_INT_SW6C3", - "BRKH_INT_SW6D0", - "BRKH_INT_SW6D1", - "BRKH_INT_SW6D2", - "BRKH_INT_SW6D3", - "BRKH_INT_SW6E0", - "BRKH_INT_SW6E1", - "BRKH_INT_SW6E2", - "BRKH_INT_SW6E3", - "BRKH_INT_SW6END3", - "BRKH_INT_WL1BEG3", - "BRKH_INT_WL1END3", - "BRKH_INT_WR1BEG_S0", - "BRKH_INT_WR1END_S1_0", - "BRKH_INT_WW2END3", - "BRKH_INT_WW4END_S0_0" - ] + "wires": { + "BRKH_INT_BYP_BOUNCE2": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_BYP_BOUNCE3": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_BYP_BOUNCE6": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_BYP_BOUNCE7": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_EL1BEG3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_EL1END_S3_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_ER1BEG_S0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_ER1END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_FAN_BOUNCE_S3_0": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_FAN_BOUNCE_S3_2": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_FAN_BOUNCE_S3_4": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_FAN_BOUNCE_S3_6": { + "cap": "1.000", + "res": "0.000" + }, + "BRKH_INT_LV0": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV1": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV10": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV11": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV12": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV13": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV14": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV15": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV16": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV17": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "BRKH_INT_LV4": { + "cap": "13.000", + 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"cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6C3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6D0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6D1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6E0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6E1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6E2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6E3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NN6END_S1_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NR1BEG0": null, + "BRKH_INT_NR1BEG0_SLOW": null, + "BRKH_INT_NR1BEG1": null, + "BRKH_INT_NR1BEG1_SLOW": null, + "BRKH_INT_NR1BEG2": null, + "BRKH_INT_NR1BEG2_SLOW": null, + "BRKH_INT_NR1BEG3": null, + "BRKH_INT_NR1BEG3_SLOW": null, + "BRKH_INT_NW2BEG0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW2BEG1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW2BEG2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW2BEG3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW2END_S0_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6B0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6B1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6B2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6B3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6C0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6C1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6C2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6C3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6D0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6D1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_NW6END_S0_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE2A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE2A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE2A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE2A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6B0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6B1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6B2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6B3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6C0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6C1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6C2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6C3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6D0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6D1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6E0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6E1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6E2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SE6E3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SL1END0": null, + "BRKH_INT_SL1END0_SLOW": null, + "BRKH_INT_SL1END1": null, + "BRKH_INT_SL1END1_SLOW": null, + "BRKH_INT_SL1END2": null, + "BRKH_INT_SL1END2_SLOW": null, + "BRKH_INT_SL1END3": null, + "BRKH_INT_SL1END3_SLOW": null, + "BRKH_INT_SR1END1": null, + "BRKH_INT_SR1END1_SLOW": null, + "BRKH_INT_SR1END2": null, + "BRKH_INT_SR1END2_SLOW": null, + "BRKH_INT_SR1END3": null, + "BRKH_INT_SR1END3_SLOW": null, + "BRKH_INT_SR1END_N3_3": null, + "BRKH_INT_SS2A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS2END_N0_3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6B0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6B1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6B2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6B3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6C0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6C1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6C2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6C3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6D0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6D1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6E0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6E1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6E2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6E3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SS6END_N0_3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2A0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2A1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2A2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2A3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW2END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6B0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6B1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6B2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6B3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6C0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6C1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6C2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6C3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6D0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6D1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6D2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6D3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6E0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6E1": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6E2": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6E3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_SW6END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WL1BEG3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WL1END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WR1BEG_S0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WR1END_S1_0": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WW2END3": { + "cap": "1.000", + "res": "5.230" + }, + "BRKH_INT_WW4END_S0_0": { + "cap": "1.000", + "res": "5.230" + } + } } diff --git a/kintex7/tile_type_BRKH_TERM_INT.json b/kintex7/tile_type_BRKH_TERM_INT.json index 1329a6c..54cd852 100644 --- a/kintex7/tile_type_BRKH_TERM_INT.json +++ b/kintex7/tile_type_BRKH_TERM_INT.json @@ -2,123 +2,213 @@ "pips": {}, "sites": [], "tile_type": "BRKH_TERM_INT", - "wires": [ - "T_TERM_INT_UTURN_LV_R16", - "T_TERM_INT_UTURN_LV_R17", - "T_TERM_INT_UTURN_LV_R2", - "T_TERM_INT_UTURN_LV_R3", - "T_TERM_INT_UTURN_LV_R4", - "T_TERM_INT_UTURN_LV_R5", - "T_TERM_INT_UTURN_LV_R6", - "T_TERM_INT_UTURN_LV_R7", - "T_TERM_INT_UTURN_LV_R9", - "T_TERM_UTURN_INT_ER1BEG_S0", - "T_TERM_UTURN_INT_ER1END3", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "T_TERM_UTURN_INT_LVB0", - "T_TERM_UTURN_INT_LVB1", - "T_TERM_UTURN_INT_LVB2", - "T_TERM_UTURN_INT_LVB3", - "T_TERM_UTURN_INT_LVB4", - "T_TERM_UTURN_INT_LVB5", - "T_TERM_UTURN_INT_LVB_L0", - "T_TERM_UTURN_INT_LVB_L1", - "T_TERM_UTURN_INT_LVB_L2", - "T_TERM_UTURN_INT_LVB_L3", - "T_TERM_UTURN_INT_LVB_L4", - "T_TERM_UTURN_INT_LVB_L5", - "T_TERM_UTURN_INT_LV_L16", - "T_TERM_UTURN_INT_LV_L17", - "T_TERM_UTURN_INT_LV_L2", - "T_TERM_UTURN_INT_LV_L3", - "T_TERM_UTURN_INT_LV_L4", - "T_TERM_UTURN_INT_LV_L5", - "T_TERM_UTURN_INT_LV_L6", - "T_TERM_UTURN_INT_LV_L7", - "T_TERM_UTURN_INT_LV_L9", - "T_TERM_UTURN_INT_SE2A0", - "T_TERM_UTURN_INT_SE2A1", - "T_TERM_UTURN_INT_SE2A2", - "T_TERM_UTURN_INT_SE2A3", - "T_TERM_UTURN_INT_SE6B0", - "T_TERM_UTURN_INT_SE6B1", - "T_TERM_UTURN_INT_SE6B2", - "T_TERM_UTURN_INT_SE6B3", - "T_TERM_UTURN_INT_SE6C0", - "T_TERM_UTURN_INT_SE6C1", - "T_TERM_UTURN_INT_SE6C2", - "T_TERM_UTURN_INT_SE6C3", - "T_TERM_UTURN_INT_SE6D0", - "T_TERM_UTURN_INT_SE6D1", - "T_TERM_UTURN_INT_SE6D2", - "T_TERM_UTURN_INT_SE6D3", - "T_TERM_UTURN_INT_SE6E0", - "T_TERM_UTURN_INT_SE6E1", - "T_TERM_UTURN_INT_SE6E2", - "T_TERM_UTURN_INT_SE6E3", - "T_TERM_UTURN_INT_SL1END0_SLOW", - "T_TERM_UTURN_INT_SL1END1_SLOW", - "T_TERM_UTURN_INT_SL1END2_SLOW", - "T_TERM_UTURN_INT_SL1END3_SLOW", - "T_TERM_UTURN_INT_SR1END1_SLOW", - "T_TERM_UTURN_INT_SR1END2_SLOW", - "T_TERM_UTURN_INT_SR1END3_SLOW", - "T_TERM_UTURN_INT_SS2A0", - "T_TERM_UTURN_INT_SS2A1", - "T_TERM_UTURN_INT_SS2A2", - "T_TERM_UTURN_INT_SS2A3", - "T_TERM_UTURN_INT_SS2END0", - "T_TERM_UTURN_INT_SS2END1", - "T_TERM_UTURN_INT_SS2END2", - "T_TERM_UTURN_INT_SS2END3", - "T_TERM_UTURN_INT_SS6A0", - "T_TERM_UTURN_INT_SS6A1", - "T_TERM_UTURN_INT_SS6A2", - "T_TERM_UTURN_INT_SS6A3", - "T_TERM_UTURN_INT_SS6B0", - "T_TERM_UTURN_INT_SS6B1", - "T_TERM_UTURN_INT_SS6B2", - "T_TERM_UTURN_INT_SS6B3", - "T_TERM_UTURN_INT_SS6C0", - "T_TERM_UTURN_INT_SS6C1", - "T_TERM_UTURN_INT_SS6C2", - "T_TERM_UTURN_INT_SS6C3", - "T_TERM_UTURN_INT_SS6D0", - "T_TERM_UTURN_INT_SS6D1", - "T_TERM_UTURN_INT_SS6D2", - "T_TERM_UTURN_INT_SS6D3", - "T_TERM_UTURN_INT_SS6E0", - "T_TERM_UTURN_INT_SS6E1", - "T_TERM_UTURN_INT_SS6E2", - "T_TERM_UTURN_INT_SS6E3", - "T_TERM_UTURN_INT_SS6END0", - "T_TERM_UTURN_INT_SS6END1", - "T_TERM_UTURN_INT_SS6END2", - "T_TERM_UTURN_INT_SS6END3", - "T_TERM_UTURN_INT_SW2A0", - "T_TERM_UTURN_INT_SW2A1", - "T_TERM_UTURN_INT_SW2A2", - "T_TERM_UTURN_INT_SW2A3", - "T_TERM_UTURN_INT_SW6B0", - "T_TERM_UTURN_INT_SW6B1", - "T_TERM_UTURN_INT_SW6B2", - "T_TERM_UTURN_INT_SW6B3", - "T_TERM_UTURN_INT_SW6C0", - "T_TERM_UTURN_INT_SW6C1", - "T_TERM_UTURN_INT_SW6C2", - "T_TERM_UTURN_INT_SW6C3", - "T_TERM_UTURN_INT_SW6D0", - "T_TERM_UTURN_INT_SW6D1", - "T_TERM_UTURN_INT_SW6D2", - "T_TERM_UTURN_INT_SW6D3", - "T_TERM_UTURN_INT_SW6E0", - "T_TERM_UTURN_INT_SW6E1", - "T_TERM_UTURN_INT_SW6E2", - "T_TERM_UTURN_INT_SW6E3", - "T_TERM_UTURN_INT_WR1BEG_S0", - "T_TERM_UTURN_INT_WR1END_S1_0" - ] + "wires": { + "T_TERM_INT_UTURN_LV_R16": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R17": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R2": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R3": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R4": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R5": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R6": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R7": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_INT_UTURN_LV_R9": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_ER1BEG_S0": null, + "T_TERM_UTURN_INT_ER1END3": null, + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0": null, + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2": null, + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4": null, + "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6": null, + "T_TERM_UTURN_INT_LVB0": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB_L0": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB_L1": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB_L2": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB_L3": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB_L4": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LVB_L5": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LV_L16": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LV_L17": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LV_L2": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LV_L3": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LV_L4": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LV_L5": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LV_L6": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LV_L7": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_LV_L9": { + "cap": "13.000", + "res": "2.800" + }, + "T_TERM_UTURN_INT_SE2A0": null, + "T_TERM_UTURN_INT_SE2A1": null, + "T_TERM_UTURN_INT_SE2A2": null, + "T_TERM_UTURN_INT_SE2A3": null, + "T_TERM_UTURN_INT_SE6B0": null, + "T_TERM_UTURN_INT_SE6B1": null, + "T_TERM_UTURN_INT_SE6B2": null, + "T_TERM_UTURN_INT_SE6B3": null, + "T_TERM_UTURN_INT_SE6C0": null, + "T_TERM_UTURN_INT_SE6C1": null, + "T_TERM_UTURN_INT_SE6C2": null, + "T_TERM_UTURN_INT_SE6C3": null, + "T_TERM_UTURN_INT_SE6D0": null, + "T_TERM_UTURN_INT_SE6D1": null, + "T_TERM_UTURN_INT_SE6D2": null, + "T_TERM_UTURN_INT_SE6D3": null, + "T_TERM_UTURN_INT_SE6E0": null, + "T_TERM_UTURN_INT_SE6E1": null, + "T_TERM_UTURN_INT_SE6E2": null, + "T_TERM_UTURN_INT_SE6E3": null, + "T_TERM_UTURN_INT_SL1END0_SLOW": null, + "T_TERM_UTURN_INT_SL1END1_SLOW": null, + "T_TERM_UTURN_INT_SL1END2_SLOW": null, + "T_TERM_UTURN_INT_SL1END3_SLOW": null, + "T_TERM_UTURN_INT_SR1END1_SLOW": null, + "T_TERM_UTURN_INT_SR1END2_SLOW": null, + "T_TERM_UTURN_INT_SR1END3_SLOW": null, + "T_TERM_UTURN_INT_SS2A0": null, + "T_TERM_UTURN_INT_SS2A1": null, + "T_TERM_UTURN_INT_SS2A2": null, + "T_TERM_UTURN_INT_SS2A3": null, + "T_TERM_UTURN_INT_SS2END0": null, + "T_TERM_UTURN_INT_SS2END1": null, + "T_TERM_UTURN_INT_SS2END2": null, + "T_TERM_UTURN_INT_SS2END3": null, + "T_TERM_UTURN_INT_SS6A0": null, + "T_TERM_UTURN_INT_SS6A1": null, + "T_TERM_UTURN_INT_SS6A2": null, + "T_TERM_UTURN_INT_SS6A3": null, + "T_TERM_UTURN_INT_SS6B0": null, + "T_TERM_UTURN_INT_SS6B1": null, + "T_TERM_UTURN_INT_SS6B2": null, + "T_TERM_UTURN_INT_SS6B3": null, + "T_TERM_UTURN_INT_SS6C0": null, + "T_TERM_UTURN_INT_SS6C1": null, + "T_TERM_UTURN_INT_SS6C2": null, + "T_TERM_UTURN_INT_SS6C3": null, + "T_TERM_UTURN_INT_SS6D0": null, + "T_TERM_UTURN_INT_SS6D1": null, + "T_TERM_UTURN_INT_SS6D2": null, + "T_TERM_UTURN_INT_SS6D3": null, + "T_TERM_UTURN_INT_SS6E0": null, + "T_TERM_UTURN_INT_SS6E1": null, + "T_TERM_UTURN_INT_SS6E2": null, + "T_TERM_UTURN_INT_SS6E3": null, + "T_TERM_UTURN_INT_SS6END0": null, + "T_TERM_UTURN_INT_SS6END1": null, + "T_TERM_UTURN_INT_SS6END2": null, + "T_TERM_UTURN_INT_SS6END3": null, + "T_TERM_UTURN_INT_SW2A0": null, + "T_TERM_UTURN_INT_SW2A1": null, + "T_TERM_UTURN_INT_SW2A2": null, + "T_TERM_UTURN_INT_SW2A3": null, + "T_TERM_UTURN_INT_SW6B0": null, + "T_TERM_UTURN_INT_SW6B1": null, + "T_TERM_UTURN_INT_SW6B2": null, + "T_TERM_UTURN_INT_SW6B3": null, + "T_TERM_UTURN_INT_SW6C0": null, + "T_TERM_UTURN_INT_SW6C1": null, + "T_TERM_UTURN_INT_SW6C2": null, + "T_TERM_UTURN_INT_SW6C3": null, + "T_TERM_UTURN_INT_SW6D0": null, + "T_TERM_UTURN_INT_SW6D1": null, + "T_TERM_UTURN_INT_SW6D2": null, + "T_TERM_UTURN_INT_SW6D3": null, + "T_TERM_UTURN_INT_SW6E0": null, + "T_TERM_UTURN_INT_SW6E1": null, + "T_TERM_UTURN_INT_SW6E2": null, + "T_TERM_UTURN_INT_SW6E3": null, + "T_TERM_UTURN_INT_WR1BEG_S0": null, + "T_TERM_UTURN_INT_WR1END_S1_0": null + } } diff --git a/kintex7/tile_type_B_TERM_INT.json b/kintex7/tile_type_B_TERM_INT.json index 8ce2278..73bd2de 100644 --- a/kintex7/tile_type_B_TERM_INT.json +++ b/kintex7/tile_type_B_TERM_INT.json @@ -2,124 +2,214 @@ "pips": {}, "sites": [], "tile_type": "B_TERM_INT", - "wires": [ - "B_TERM_UTURN_INT_ER1BEG0", - "B_TERM_UTURN_INT_ER1END_N3_3", - "B_TERM_UTURN_INT_FAN_BOUNCE0", - "B_TERM_UTURN_INT_FAN_BOUNCE2", - "B_TERM_UTURN_INT_FAN_BOUNCE4", - "B_TERM_UTURN_INT_FAN_BOUNCE6", - "B_TERM_UTURN_INT_LV18", - "B_TERM_UTURN_INT_LV2", - "B_TERM_UTURN_INT_LV3", - "B_TERM_UTURN_INT_LV4", - "B_TERM_UTURN_INT_LV5", - "B_TERM_UTURN_INT_LV6", - "B_TERM_UTURN_INT_LV7", - "B_TERM_UTURN_INT_LV8", - "B_TERM_UTURN_INT_LV9", - "B_TERM_UTURN_INT_LVB0", - "B_TERM_UTURN_INT_LVB1", - "B_TERM_UTURN_INT_LVB2", - "B_TERM_UTURN_INT_LVB3", - "B_TERM_UTURN_INT_LVB4", - "B_TERM_UTURN_INT_LVB5", - "B_TERM_UTURN_INT_LVB_L0", - "B_TERM_UTURN_INT_LVB_L1", - "B_TERM_UTURN_INT_LVB_L2", - "B_TERM_UTURN_INT_LVB_L3", - "B_TERM_UTURN_INT_LVB_L4", - "B_TERM_UTURN_INT_LVB_L5", - "B_TERM_UTURN_INT_LV_L18", - "B_TERM_UTURN_INT_LV_L2", - "B_TERM_UTURN_INT_LV_L3", - "B_TERM_UTURN_INT_LV_L4", - "B_TERM_UTURN_INT_LV_L5", - "B_TERM_UTURN_INT_LV_L6", - "B_TERM_UTURN_INT_LV_L7", - "B_TERM_UTURN_INT_LV_L8", - "B_TERM_UTURN_INT_LV_L9", - "B_TERM_UTURN_INT_SE2BEG0", - "B_TERM_UTURN_INT_SE2BEG1", - "B_TERM_UTURN_INT_SE2BEG2", - "B_TERM_UTURN_INT_SE2BEG3", - "B_TERM_UTURN_INT_SE6A0", - "B_TERM_UTURN_INT_SE6A1", - "B_TERM_UTURN_INT_SE6A2", - "B_TERM_UTURN_INT_SE6A3", - "B_TERM_UTURN_INT_SE6B0", - "B_TERM_UTURN_INT_SE6B1", - "B_TERM_UTURN_INT_SE6B2", - "B_TERM_UTURN_INT_SE6B3", - "B_TERM_UTURN_INT_SE6C0", - "B_TERM_UTURN_INT_SE6C1", - "B_TERM_UTURN_INT_SE6C2", - "B_TERM_UTURN_INT_SE6C3", - "B_TERM_UTURN_INT_SE6D0", - "B_TERM_UTURN_INT_SE6D1", - "B_TERM_UTURN_INT_SE6D2", - "B_TERM_UTURN_INT_SE6D3", - "B_TERM_UTURN_INT_SL1BEG0", - "B_TERM_UTURN_INT_SL1BEG1", - "B_TERM_UTURN_INT_SL1BEG2", - "B_TERM_UTURN_INT_SL1BEG3", - "B_TERM_UTURN_INT_SR1BEG1", - "B_TERM_UTURN_INT_SR1BEG2", - "B_TERM_UTURN_INT_SR1BEG3", - "B_TERM_UTURN_INT_SS2A0", - "B_TERM_UTURN_INT_SS2A1", - "B_TERM_UTURN_INT_SS2A2", - "B_TERM_UTURN_INT_SS2A3", - "B_TERM_UTURN_INT_SS2BEG0", - "B_TERM_UTURN_INT_SS2BEG1", - "B_TERM_UTURN_INT_SS2BEG2", - "B_TERM_UTURN_INT_SS2BEG3", - "B_TERM_UTURN_INT_SS6A0", - "B_TERM_UTURN_INT_SS6A1", - "B_TERM_UTURN_INT_SS6A2", - "B_TERM_UTURN_INT_SS6A3", - "B_TERM_UTURN_INT_SS6B0", - "B_TERM_UTURN_INT_SS6B1", - "B_TERM_UTURN_INT_SS6B2", - "B_TERM_UTURN_INT_SS6B3", - "B_TERM_UTURN_INT_SS6BEG0", - "B_TERM_UTURN_INT_SS6BEG1", - "B_TERM_UTURN_INT_SS6BEG2", - "B_TERM_UTURN_INT_SS6BEG3", - "B_TERM_UTURN_INT_SS6C0", - "B_TERM_UTURN_INT_SS6C1", - "B_TERM_UTURN_INT_SS6C2", - "B_TERM_UTURN_INT_SS6C3", - "B_TERM_UTURN_INT_SS6D0", - "B_TERM_UTURN_INT_SS6D1", - "B_TERM_UTURN_INT_SS6D2", - "B_TERM_UTURN_INT_SS6D3", - "B_TERM_UTURN_INT_SS6E0", - "B_TERM_UTURN_INT_SS6E1", - "B_TERM_UTURN_INT_SS6E2", - "B_TERM_UTURN_INT_SS6E3", - "B_TERM_UTURN_INT_SW2BEG0", - "B_TERM_UTURN_INT_SW2BEG1", - "B_TERM_UTURN_INT_SW2BEG2", - "B_TERM_UTURN_INT_SW2BEG3", - "B_TERM_UTURN_INT_SW6A0", - "B_TERM_UTURN_INT_SW6A1", - "B_TERM_UTURN_INT_SW6A2", - "B_TERM_UTURN_INT_SW6A3", - "B_TERM_UTURN_INT_SW6B0", - "B_TERM_UTURN_INT_SW6B1", - "B_TERM_UTURN_INT_SW6B2", - "B_TERM_UTURN_INT_SW6B3", - "B_TERM_UTURN_INT_SW6C0", - "B_TERM_UTURN_INT_SW6C1", - "B_TERM_UTURN_INT_SW6C2", - "B_TERM_UTURN_INT_SW6C3", - "B_TERM_UTURN_INT_SW6D0", - "B_TERM_UTURN_INT_SW6D1", - "B_TERM_UTURN_INT_SW6D2", - "B_TERM_UTURN_INT_SW6D3", - "B_TERM_UTURN_INT_SW6END_N0_3", - "B_TERM_UTURN_INT_WR1BEG0", - "B_TERM_UTURN_INT_WR1END0" - ] + "wires": { + "B_TERM_UTURN_INT_ER1BEG0": null, + "B_TERM_UTURN_INT_ER1END_N3_3": null, + "B_TERM_UTURN_INT_FAN_BOUNCE0": null, + "B_TERM_UTURN_INT_FAN_BOUNCE2": null, + "B_TERM_UTURN_INT_FAN_BOUNCE4": null, + "B_TERM_UTURN_INT_FAN_BOUNCE6": null, + "B_TERM_UTURN_INT_LV18": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB0": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L0": { + "cap": "13.000", + "res": "2.800" + }, + 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"B_TERM_UTURN_INT_SE2BEG0": null, + "B_TERM_UTURN_INT_SE2BEG1": null, + "B_TERM_UTURN_INT_SE2BEG2": null, + "B_TERM_UTURN_INT_SE2BEG3": null, + "B_TERM_UTURN_INT_SE6A0": null, + "B_TERM_UTURN_INT_SE6A1": null, + "B_TERM_UTURN_INT_SE6A2": null, + "B_TERM_UTURN_INT_SE6A3": null, + "B_TERM_UTURN_INT_SE6B0": null, + "B_TERM_UTURN_INT_SE6B1": null, + "B_TERM_UTURN_INT_SE6B2": null, + "B_TERM_UTURN_INT_SE6B3": null, + "B_TERM_UTURN_INT_SE6C0": null, + "B_TERM_UTURN_INT_SE6C1": null, + "B_TERM_UTURN_INT_SE6C2": null, + "B_TERM_UTURN_INT_SE6C3": null, + "B_TERM_UTURN_INT_SE6D0": null, + "B_TERM_UTURN_INT_SE6D1": null, + "B_TERM_UTURN_INT_SE6D2": null, + "B_TERM_UTURN_INT_SE6D3": null, + "B_TERM_UTURN_INT_SL1BEG0": null, + "B_TERM_UTURN_INT_SL1BEG1": null, + "B_TERM_UTURN_INT_SL1BEG2": null, + "B_TERM_UTURN_INT_SL1BEG3": null, + "B_TERM_UTURN_INT_SR1BEG1": null, + "B_TERM_UTURN_INT_SR1BEG2": null, + "B_TERM_UTURN_INT_SR1BEG3": null, + "B_TERM_UTURN_INT_SS2A0": null, + "B_TERM_UTURN_INT_SS2A1": null, + "B_TERM_UTURN_INT_SS2A2": null, + "B_TERM_UTURN_INT_SS2A3": null, + "B_TERM_UTURN_INT_SS2BEG0": null, + "B_TERM_UTURN_INT_SS2BEG1": null, + "B_TERM_UTURN_INT_SS2BEG2": null, + "B_TERM_UTURN_INT_SS2BEG3": null, + "B_TERM_UTURN_INT_SS6A0": null, + "B_TERM_UTURN_INT_SS6A1": null, + "B_TERM_UTURN_INT_SS6A2": null, + "B_TERM_UTURN_INT_SS6A3": null, + "B_TERM_UTURN_INT_SS6B0": null, + "B_TERM_UTURN_INT_SS6B1": null, + "B_TERM_UTURN_INT_SS6B2": null, + "B_TERM_UTURN_INT_SS6B3": null, + "B_TERM_UTURN_INT_SS6BEG0": null, + "B_TERM_UTURN_INT_SS6BEG1": null, + "B_TERM_UTURN_INT_SS6BEG2": null, + "B_TERM_UTURN_INT_SS6BEG3": null, + "B_TERM_UTURN_INT_SS6C0": null, + "B_TERM_UTURN_INT_SS6C1": null, + "B_TERM_UTURN_INT_SS6C2": null, + "B_TERM_UTURN_INT_SS6C3": null, + "B_TERM_UTURN_INT_SS6D0": null, + "B_TERM_UTURN_INT_SS6D1": null, + "B_TERM_UTURN_INT_SS6D2": null, + "B_TERM_UTURN_INT_SS6D3": null, + "B_TERM_UTURN_INT_SS6E0": null, + "B_TERM_UTURN_INT_SS6E1": null, + "B_TERM_UTURN_INT_SS6E2": null, + "B_TERM_UTURN_INT_SS6E3": null, + "B_TERM_UTURN_INT_SW2BEG0": null, + "B_TERM_UTURN_INT_SW2BEG1": null, + "B_TERM_UTURN_INT_SW2BEG2": null, + "B_TERM_UTURN_INT_SW2BEG3": null, + "B_TERM_UTURN_INT_SW6A0": null, + "B_TERM_UTURN_INT_SW6A1": null, + "B_TERM_UTURN_INT_SW6A2": null, + "B_TERM_UTURN_INT_SW6A3": null, + "B_TERM_UTURN_INT_SW6B0": null, + "B_TERM_UTURN_INT_SW6B1": null, + "B_TERM_UTURN_INT_SW6B2": null, + "B_TERM_UTURN_INT_SW6B3": null, + "B_TERM_UTURN_INT_SW6C0": null, + "B_TERM_UTURN_INT_SW6C1": null, + "B_TERM_UTURN_INT_SW6C2": null, + "B_TERM_UTURN_INT_SW6C3": null, + "B_TERM_UTURN_INT_SW6D0": null, + "B_TERM_UTURN_INT_SW6D1": null, + "B_TERM_UTURN_INT_SW6D2": null, + "B_TERM_UTURN_INT_SW6D3": null, + "B_TERM_UTURN_INT_SW6END_N0_3": null, + "B_TERM_UTURN_INT_WR1BEG0": null, + "B_TERM_UTURN_INT_WR1END0": null + } } diff --git a/kintex7/tile_type_CFG_CENTER_BOT.json b/kintex7/tile_type_CFG_CENTER_BOT.json index 0fe8bfe..f560437 100644 --- a/kintex7/tile_type_CFG_CENTER_BOT.json +++ b/kintex7/tile_type_CFG_CENTER_BOT.json @@ -2,4512 +2,16895 @@ "pips": { "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA10->CFG_CENTER_LOGIC_OUTS_B21_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA10" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA11->CFG_CENTER_LOGIC_OUTS_B22_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA11" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA12->CFG_CENTER_LOGIC_OUTS_B23_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA12" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA13->CFG_CENTER_LOGIC_OUTS_B10_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA13" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA14->CFG_CENTER_LOGIC_OUTS_B11_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA14" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA2->CFG_CENTER_LOGIC_OUTS_B13_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA2" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA3->CFG_CENTER_LOGIC_OUTS_B14_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA3" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA4->CFG_CENTER_LOGIC_OUTS_B15_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA4" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA5->CFG_CENTER_LOGIC_OUTS_B16_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA5" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA6->CFG_CENTER_LOGIC_OUTS_B17_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA6" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA7->CFG_CENTER_LOGIC_OUTS_B18_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA7" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA8->CFG_CENTER_LOGIC_OUTS_B19_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA8" }, "CFG_CENTER_BOT.CFG_CENTER_BOT_USR_ACCESS_DATA9->CFG_CENTER_LOGIC_OUTS_B20_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BOT_USR_ACCESS_DATA9" } }, "sites": [], "tile_type": "CFG_CENTER_BOT", - "wires": [ - "CFG_CENTER_BLOCK_OUTS_B0_0", - "CFG_CENTER_BLOCK_OUTS_B0_1", - "CFG_CENTER_BLOCK_OUTS_B0_10", - "CFG_CENTER_BLOCK_OUTS_B0_11", - "CFG_CENTER_BLOCK_OUTS_B0_12", - "CFG_CENTER_BLOCK_OUTS_B0_13", - "CFG_CENTER_BLOCK_OUTS_B0_14", - "CFG_CENTER_BLOCK_OUTS_B0_15", - "CFG_CENTER_BLOCK_OUTS_B0_16", - "CFG_CENTER_BLOCK_OUTS_B0_17", - "CFG_CENTER_BLOCK_OUTS_B0_18", - "CFG_CENTER_BLOCK_OUTS_B0_19", - "CFG_CENTER_BLOCK_OUTS_B0_2", - "CFG_CENTER_BLOCK_OUTS_B0_3", - "CFG_CENTER_BLOCK_OUTS_B0_4", - "CFG_CENTER_BLOCK_OUTS_B0_5", - "CFG_CENTER_BLOCK_OUTS_B0_6", - "CFG_CENTER_BLOCK_OUTS_B0_7", - "CFG_CENTER_BLOCK_OUTS_B0_8", - "CFG_CENTER_BLOCK_OUTS_B0_9", - "CFG_CENTER_BLOCK_OUTS_B1_0", - "CFG_CENTER_BLOCK_OUTS_B1_1", - "CFG_CENTER_BLOCK_OUTS_B1_10", - "CFG_CENTER_BLOCK_OUTS_B1_11", - "CFG_CENTER_BLOCK_OUTS_B1_12", - "CFG_CENTER_BLOCK_OUTS_B1_13", - "CFG_CENTER_BLOCK_OUTS_B1_14", - "CFG_CENTER_BLOCK_OUTS_B1_15", - "CFG_CENTER_BLOCK_OUTS_B1_16", - "CFG_CENTER_BLOCK_OUTS_B1_17", - "CFG_CENTER_BLOCK_OUTS_B1_18", - "CFG_CENTER_BLOCK_OUTS_B1_19", - "CFG_CENTER_BLOCK_OUTS_B1_2", - "CFG_CENTER_BLOCK_OUTS_B1_3", - "CFG_CENTER_BLOCK_OUTS_B1_4", - "CFG_CENTER_BLOCK_OUTS_B1_5", - "CFG_CENTER_BLOCK_OUTS_B1_6", - "CFG_CENTER_BLOCK_OUTS_B1_7", - "CFG_CENTER_BLOCK_OUTS_B1_8", - "CFG_CENTER_BLOCK_OUTS_B1_9", - "CFG_CENTER_BLOCK_OUTS_B2_0", - "CFG_CENTER_BLOCK_OUTS_B2_1", - "CFG_CENTER_BLOCK_OUTS_B2_10", - "CFG_CENTER_BLOCK_OUTS_B2_11", - "CFG_CENTER_BLOCK_OUTS_B2_12", - "CFG_CENTER_BLOCK_OUTS_B2_13", - "CFG_CENTER_BLOCK_OUTS_B2_14", - "CFG_CENTER_BLOCK_OUTS_B2_15", - "CFG_CENTER_BLOCK_OUTS_B2_16", - "CFG_CENTER_BLOCK_OUTS_B2_17", - "CFG_CENTER_BLOCK_OUTS_B2_18", - "CFG_CENTER_BLOCK_OUTS_B2_19", - "CFG_CENTER_BLOCK_OUTS_B2_2", - "CFG_CENTER_BLOCK_OUTS_B2_3", - "CFG_CENTER_BLOCK_OUTS_B2_4", - "CFG_CENTER_BLOCK_OUTS_B2_5", - "CFG_CENTER_BLOCK_OUTS_B2_6", - "CFG_CENTER_BLOCK_OUTS_B2_7", - "CFG_CENTER_BLOCK_OUTS_B2_8", - "CFG_CENTER_BLOCK_OUTS_B2_9", - "CFG_CENTER_BLOCK_OUTS_B3_0", - "CFG_CENTER_BLOCK_OUTS_B3_1", - "CFG_CENTER_BLOCK_OUTS_B3_10", - "CFG_CENTER_BLOCK_OUTS_B3_11", - "CFG_CENTER_BLOCK_OUTS_B3_12", - "CFG_CENTER_BLOCK_OUTS_B3_13", - "CFG_CENTER_BLOCK_OUTS_B3_14", - "CFG_CENTER_BLOCK_OUTS_B3_15", - "CFG_CENTER_BLOCK_OUTS_B3_16", - "CFG_CENTER_BLOCK_OUTS_B3_17", - "CFG_CENTER_BLOCK_OUTS_B3_18", - "CFG_CENTER_BLOCK_OUTS_B3_19", - "CFG_CENTER_BLOCK_OUTS_B3_2", - "CFG_CENTER_BLOCK_OUTS_B3_3", - "CFG_CENTER_BLOCK_OUTS_B3_4", - "CFG_CENTER_BLOCK_OUTS_B3_5", - "CFG_CENTER_BLOCK_OUTS_B3_6", - "CFG_CENTER_BLOCK_OUTS_B3_7", - "CFG_CENTER_BLOCK_OUTS_B3_8", - "CFG_CENTER_BLOCK_OUTS_B3_9", - "CFG_CENTER_BOT_CFG_IO_ACCESS_VGGCOMPOUT", - "CFG_CENTER_BOT_USR_ACCESS_DATA10", - "CFG_CENTER_BOT_USR_ACCESS_DATA11", - "CFG_CENTER_BOT_USR_ACCESS_DATA12", - "CFG_CENTER_BOT_USR_ACCESS_DATA13", - "CFG_CENTER_BOT_USR_ACCESS_DATA14", - "CFG_CENTER_BOT_USR_ACCESS_DATA2", - "CFG_CENTER_BOT_USR_ACCESS_DATA3", - "CFG_CENTER_BOT_USR_ACCESS_DATA4", - "CFG_CENTER_BOT_USR_ACCESS_DATA5", - "CFG_CENTER_BOT_USR_ACCESS_DATA6", - "CFG_CENTER_BOT_USR_ACCESS_DATA7", - "CFG_CENTER_BOT_USR_ACCESS_DATA8", - "CFG_CENTER_BOT_USR_ACCESS_DATA9", - "CFG_CENTER_BYP0_0", - "CFG_CENTER_BYP0_1", - "CFG_CENTER_BYP0_10", - "CFG_CENTER_BYP0_11", - "CFG_CENTER_BYP0_12", - "CFG_CENTER_BYP0_13", - "CFG_CENTER_BYP0_14", - "CFG_CENTER_BYP0_15", - "CFG_CENTER_BYP0_16", - "CFG_CENTER_BYP0_17", - "CFG_CENTER_BYP0_18", - "CFG_CENTER_BYP0_19", - "CFG_CENTER_BYP0_2", - "CFG_CENTER_BYP0_3", - "CFG_CENTER_BYP0_4", - "CFG_CENTER_BYP0_5", - "CFG_CENTER_BYP0_6", - "CFG_CENTER_BYP0_7", - "CFG_CENTER_BYP0_8", - "CFG_CENTER_BYP0_9", - "CFG_CENTER_BYP1_0", - "CFG_CENTER_BYP1_1", - "CFG_CENTER_BYP1_10", - "CFG_CENTER_BYP1_11", - "CFG_CENTER_BYP1_12", - "CFG_CENTER_BYP1_13", - "CFG_CENTER_BYP1_14", - "CFG_CENTER_BYP1_15", - "CFG_CENTER_BYP1_16", - "CFG_CENTER_BYP1_17", - "CFG_CENTER_BYP1_18", - "CFG_CENTER_BYP1_19", - "CFG_CENTER_BYP1_2", - "CFG_CENTER_BYP1_3", - "CFG_CENTER_BYP1_4", - "CFG_CENTER_BYP1_5", - "CFG_CENTER_BYP1_6", - "CFG_CENTER_BYP1_7", - "CFG_CENTER_BYP1_8", - "CFG_CENTER_BYP1_9", - "CFG_CENTER_BYP2_0", - "CFG_CENTER_BYP2_1", - "CFG_CENTER_BYP2_10", - "CFG_CENTER_BYP2_11", - "CFG_CENTER_BYP2_12", - "CFG_CENTER_BYP2_13", - "CFG_CENTER_BYP2_14", - "CFG_CENTER_BYP2_15", - "CFG_CENTER_BYP2_16", - "CFG_CENTER_BYP2_17", - "CFG_CENTER_BYP2_18", - "CFG_CENTER_BYP2_19", - "CFG_CENTER_BYP2_2", - "CFG_CENTER_BYP2_3", - "CFG_CENTER_BYP2_4", - "CFG_CENTER_BYP2_5", - "CFG_CENTER_BYP2_6", - "CFG_CENTER_BYP2_7", - "CFG_CENTER_BYP2_8", - "CFG_CENTER_BYP2_9", - "CFG_CENTER_BYP3_0", - "CFG_CENTER_BYP3_1", - "CFG_CENTER_BYP3_10", - "CFG_CENTER_BYP3_11", - "CFG_CENTER_BYP3_12", - "CFG_CENTER_BYP3_13", - "CFG_CENTER_BYP3_14", - "CFG_CENTER_BYP3_15", - "CFG_CENTER_BYP3_16", - "CFG_CENTER_BYP3_17", - "CFG_CENTER_BYP3_18", - "CFG_CENTER_BYP3_19", - "CFG_CENTER_BYP3_2", - "CFG_CENTER_BYP3_3", - "CFG_CENTER_BYP3_4", - "CFG_CENTER_BYP3_5", - "CFG_CENTER_BYP3_6", - "CFG_CENTER_BYP3_7", - "CFG_CENTER_BYP3_8", - "CFG_CENTER_BYP3_9", - "CFG_CENTER_BYP4_0", - "CFG_CENTER_BYP4_1", - "CFG_CENTER_BYP4_10", - "CFG_CENTER_BYP4_11", - "CFG_CENTER_BYP4_12", - "CFG_CENTER_BYP4_13", - "CFG_CENTER_BYP4_14", - "CFG_CENTER_BYP4_15", - "CFG_CENTER_BYP4_16", - "CFG_CENTER_BYP4_17", - "CFG_CENTER_BYP4_18", - "CFG_CENTER_BYP4_19", - "CFG_CENTER_BYP4_2", - "CFG_CENTER_BYP4_3", - "CFG_CENTER_BYP4_4", - "CFG_CENTER_BYP4_5", - "CFG_CENTER_BYP4_6", - "CFG_CENTER_BYP4_7", - "CFG_CENTER_BYP4_8", - "CFG_CENTER_BYP4_9", - "CFG_CENTER_BYP5_0", - "CFG_CENTER_BYP5_1", - "CFG_CENTER_BYP5_10", - "CFG_CENTER_BYP5_11", - "CFG_CENTER_BYP5_12", - "CFG_CENTER_BYP5_13", - "CFG_CENTER_BYP5_14", - "CFG_CENTER_BYP5_15", - "CFG_CENTER_BYP5_16", - "CFG_CENTER_BYP5_17", - "CFG_CENTER_BYP5_18", - "CFG_CENTER_BYP5_19", - "CFG_CENTER_BYP5_2", - "CFG_CENTER_BYP5_3", - "CFG_CENTER_BYP5_4", - "CFG_CENTER_BYP5_5", - "CFG_CENTER_BYP5_6", - "CFG_CENTER_BYP5_7", - "CFG_CENTER_BYP5_8", - "CFG_CENTER_BYP5_9", - "CFG_CENTER_BYP6_0", - "CFG_CENTER_BYP6_1", - "CFG_CENTER_BYP6_10", - "CFG_CENTER_BYP6_11", - "CFG_CENTER_BYP6_12", - "CFG_CENTER_BYP6_13", - "CFG_CENTER_BYP6_14", - "CFG_CENTER_BYP6_15", - "CFG_CENTER_BYP6_16", - "CFG_CENTER_BYP6_17", - "CFG_CENTER_BYP6_18", - "CFG_CENTER_BYP6_19", - "CFG_CENTER_BYP6_2", - "CFG_CENTER_BYP6_3", - "CFG_CENTER_BYP6_4", - "CFG_CENTER_BYP6_5", - "CFG_CENTER_BYP6_6", - "CFG_CENTER_BYP6_7", - "CFG_CENTER_BYP6_8", - "CFG_CENTER_BYP6_9", - "CFG_CENTER_BYP7_0", - "CFG_CENTER_BYP7_1", - "CFG_CENTER_BYP7_10", - "CFG_CENTER_BYP7_11", - "CFG_CENTER_BYP7_12", - "CFG_CENTER_BYP7_13", - "CFG_CENTER_BYP7_14", - "CFG_CENTER_BYP7_15", - "CFG_CENTER_BYP7_16", - "CFG_CENTER_BYP7_17", - "CFG_CENTER_BYP7_18", - "CFG_CENTER_BYP7_19", - "CFG_CENTER_BYP7_2", - "CFG_CENTER_BYP7_3", - "CFG_CENTER_BYP7_4", - "CFG_CENTER_BYP7_5", - "CFG_CENTER_BYP7_6", - "CFG_CENTER_BYP7_7", - "CFG_CENTER_BYP7_8", - "CFG_CENTER_BYP7_9", - "CFG_CENTER_CLK0_0", - "CFG_CENTER_CLK0_1", - "CFG_CENTER_CLK0_10", - "CFG_CENTER_CLK0_11", - "CFG_CENTER_CLK0_12", - "CFG_CENTER_CLK0_13", - "CFG_CENTER_CLK0_14", - "CFG_CENTER_CLK0_15", - "CFG_CENTER_CLK0_16", - "CFG_CENTER_CLK0_17", - "CFG_CENTER_CLK0_18", - "CFG_CENTER_CLK0_19", - "CFG_CENTER_CLK0_2", - "CFG_CENTER_CLK0_3", - "CFG_CENTER_CLK0_4", - "CFG_CENTER_CLK0_5", - "CFG_CENTER_CLK0_6", - "CFG_CENTER_CLK0_7", - "CFG_CENTER_CLK0_8", - "CFG_CENTER_CLK0_9", - "CFG_CENTER_CLK1_0", - "CFG_CENTER_CLK1_1", - "CFG_CENTER_CLK1_10", - "CFG_CENTER_CLK1_11", - "CFG_CENTER_CLK1_12", - "CFG_CENTER_CLK1_13", - "CFG_CENTER_CLK1_14", - "CFG_CENTER_CLK1_15", - "CFG_CENTER_CLK1_16", - "CFG_CENTER_CLK1_17", - "CFG_CENTER_CLK1_18", - "CFG_CENTER_CLK1_19", - "CFG_CENTER_CLK1_2", - "CFG_CENTER_CLK1_3", - "CFG_CENTER_CLK1_4", - "CFG_CENTER_CLK1_5", - "CFG_CENTER_CLK1_6", - "CFG_CENTER_CLK1_7", - "CFG_CENTER_CLK1_8", - "CFG_CENTER_CLK1_9", - "CFG_CENTER_CTRL0_0", - "CFG_CENTER_CTRL0_1", - "CFG_CENTER_CTRL0_10", - "CFG_CENTER_CTRL0_11", - "CFG_CENTER_CTRL0_12", - "CFG_CENTER_CTRL0_13", - "CFG_CENTER_CTRL0_14", - "CFG_CENTER_CTRL0_15", - "CFG_CENTER_CTRL0_16", - "CFG_CENTER_CTRL0_17", - "CFG_CENTER_CTRL0_18", - "CFG_CENTER_CTRL0_19", - "CFG_CENTER_CTRL0_2", - "CFG_CENTER_CTRL0_3", - "CFG_CENTER_CTRL0_4", - "CFG_CENTER_CTRL0_5", - "CFG_CENTER_CTRL0_6", - "CFG_CENTER_CTRL0_7", - "CFG_CENTER_CTRL0_8", - "CFG_CENTER_CTRL0_9", - "CFG_CENTER_CTRL1_0", - "CFG_CENTER_CTRL1_1", - "CFG_CENTER_CTRL1_10", - "CFG_CENTER_CTRL1_11", - "CFG_CENTER_CTRL1_12", - "CFG_CENTER_CTRL1_13", - "CFG_CENTER_CTRL1_14", - "CFG_CENTER_CTRL1_15", - "CFG_CENTER_CTRL1_16", - "CFG_CENTER_CTRL1_17", - "CFG_CENTER_CTRL1_18", - "CFG_CENTER_CTRL1_19", - "CFG_CENTER_CTRL1_2", - "CFG_CENTER_CTRL1_3", - "CFG_CENTER_CTRL1_4", - "CFG_CENTER_CTRL1_5", - "CFG_CENTER_CTRL1_6", - "CFG_CENTER_CTRL1_7", - "CFG_CENTER_CTRL1_8", - "CFG_CENTER_CTRL1_9", - "CFG_CENTER_EE2A0_0", - "CFG_CENTER_EE2A0_1", - "CFG_CENTER_EE2A0_10", - "CFG_CENTER_EE2A0_11", - "CFG_CENTER_EE2A0_12", - "CFG_CENTER_EE2A0_13", - "CFG_CENTER_EE2A0_14", - "CFG_CENTER_EE2A0_15", - "CFG_CENTER_EE2A0_16", - "CFG_CENTER_EE2A0_17", - "CFG_CENTER_EE2A0_18", - "CFG_CENTER_EE2A0_19", - "CFG_CENTER_EE2A0_2", - "CFG_CENTER_EE2A0_3", - "CFG_CENTER_EE2A0_4", - "CFG_CENTER_EE2A0_5", - "CFG_CENTER_EE2A0_6", - "CFG_CENTER_EE2A0_7", - "CFG_CENTER_EE2A0_8", - "CFG_CENTER_EE2A0_9", - "CFG_CENTER_EE2A1_0", - "CFG_CENTER_EE2A1_1", - "CFG_CENTER_EE2A1_10", - "CFG_CENTER_EE2A1_11", - "CFG_CENTER_EE2A1_12", - "CFG_CENTER_EE2A1_13", - "CFG_CENTER_EE2A1_14", - "CFG_CENTER_EE2A1_15", - "CFG_CENTER_EE2A1_16", - "CFG_CENTER_EE2A1_17", - "CFG_CENTER_EE2A1_18", - "CFG_CENTER_EE2A1_19", - "CFG_CENTER_EE2A1_2", - "CFG_CENTER_EE2A1_3", - "CFG_CENTER_EE2A1_4", - "CFG_CENTER_EE2A1_5", - "CFG_CENTER_EE2A1_6", - "CFG_CENTER_EE2A1_7", - "CFG_CENTER_EE2A1_8", - "CFG_CENTER_EE2A1_9", - "CFG_CENTER_EE2A2_0", - "CFG_CENTER_EE2A2_1", - "CFG_CENTER_EE2A2_10", - "CFG_CENTER_EE2A2_11", - "CFG_CENTER_EE2A2_12", - "CFG_CENTER_EE2A2_13", - "CFG_CENTER_EE2A2_14", - "CFG_CENTER_EE2A2_15", - "CFG_CENTER_EE2A2_16", - "CFG_CENTER_EE2A2_17", - "CFG_CENTER_EE2A2_18", - "CFG_CENTER_EE2A2_19", - "CFG_CENTER_EE2A2_2", - "CFG_CENTER_EE2A2_3", - "CFG_CENTER_EE2A2_4", - "CFG_CENTER_EE2A2_5", - "CFG_CENTER_EE2A2_6", - "CFG_CENTER_EE2A2_7", - "CFG_CENTER_EE2A2_8", - "CFG_CENTER_EE2A2_9", - "CFG_CENTER_EE2A3_0", - "CFG_CENTER_EE2A3_1", - "CFG_CENTER_EE2A3_10", - "CFG_CENTER_EE2A3_11", - "CFG_CENTER_EE2A3_12", - "CFG_CENTER_EE2A3_13", - "CFG_CENTER_EE2A3_14", - "CFG_CENTER_EE2A3_15", - "CFG_CENTER_EE2A3_16", - "CFG_CENTER_EE2A3_17", - "CFG_CENTER_EE2A3_18", - "CFG_CENTER_EE2A3_19", - "CFG_CENTER_EE2A3_2", - "CFG_CENTER_EE2A3_3", - "CFG_CENTER_EE2A3_4", - "CFG_CENTER_EE2A3_5", - "CFG_CENTER_EE2A3_6", - "CFG_CENTER_EE2A3_7", - "CFG_CENTER_EE2A3_8", - "CFG_CENTER_EE2A3_9", - "CFG_CENTER_EE2BEG0_0", - "CFG_CENTER_EE2BEG0_1", - "CFG_CENTER_EE2BEG0_10", - "CFG_CENTER_EE2BEG0_11", - "CFG_CENTER_EE2BEG0_12", - "CFG_CENTER_EE2BEG0_13", - "CFG_CENTER_EE2BEG0_14", - "CFG_CENTER_EE2BEG0_15", - "CFG_CENTER_EE2BEG0_16", - "CFG_CENTER_EE2BEG0_17", - "CFG_CENTER_EE2BEG0_18", - "CFG_CENTER_EE2BEG0_19", - "CFG_CENTER_EE2BEG0_2", - "CFG_CENTER_EE2BEG0_3", - "CFG_CENTER_EE2BEG0_4", - "CFG_CENTER_EE2BEG0_5", - "CFG_CENTER_EE2BEG0_6", - "CFG_CENTER_EE2BEG0_7", - "CFG_CENTER_EE2BEG0_8", - "CFG_CENTER_EE2BEG0_9", - "CFG_CENTER_EE2BEG1_0", - "CFG_CENTER_EE2BEG1_1", - "CFG_CENTER_EE2BEG1_10", - "CFG_CENTER_EE2BEG1_11", - "CFG_CENTER_EE2BEG1_12", - "CFG_CENTER_EE2BEG1_13", - "CFG_CENTER_EE2BEG1_14", - "CFG_CENTER_EE2BEG1_15", - "CFG_CENTER_EE2BEG1_16", - "CFG_CENTER_EE2BEG1_17", - "CFG_CENTER_EE2BEG1_18", - "CFG_CENTER_EE2BEG1_19", - "CFG_CENTER_EE2BEG1_2", - "CFG_CENTER_EE2BEG1_3", - "CFG_CENTER_EE2BEG1_4", - "CFG_CENTER_EE2BEG1_5", - "CFG_CENTER_EE2BEG1_6", - "CFG_CENTER_EE2BEG1_7", - "CFG_CENTER_EE2BEG1_8", - "CFG_CENTER_EE2BEG1_9", - "CFG_CENTER_EE2BEG2_0", - "CFG_CENTER_EE2BEG2_1", - "CFG_CENTER_EE2BEG2_10", - "CFG_CENTER_EE2BEG2_11", - "CFG_CENTER_EE2BEG2_12", - "CFG_CENTER_EE2BEG2_13", - "CFG_CENTER_EE2BEG2_14", - "CFG_CENTER_EE2BEG2_15", - "CFG_CENTER_EE2BEG2_16", - "CFG_CENTER_EE2BEG2_17", - "CFG_CENTER_EE2BEG2_18", - "CFG_CENTER_EE2BEG2_19", - "CFG_CENTER_EE2BEG2_2", - "CFG_CENTER_EE2BEG2_3", - "CFG_CENTER_EE2BEG2_4", - "CFG_CENTER_EE2BEG2_5", - "CFG_CENTER_EE2BEG2_6", - "CFG_CENTER_EE2BEG2_7", - "CFG_CENTER_EE2BEG2_8", - "CFG_CENTER_EE2BEG2_9", - "CFG_CENTER_EE2BEG3_0", - "CFG_CENTER_EE2BEG3_1", - "CFG_CENTER_EE2BEG3_10", - "CFG_CENTER_EE2BEG3_11", - "CFG_CENTER_EE2BEG3_12", - "CFG_CENTER_EE2BEG3_13", - "CFG_CENTER_EE2BEG3_14", - "CFG_CENTER_EE2BEG3_15", - "CFG_CENTER_EE2BEG3_16", - "CFG_CENTER_EE2BEG3_17", - "CFG_CENTER_EE2BEG3_18", - "CFG_CENTER_EE2BEG3_19", - "CFG_CENTER_EE2BEG3_2", - "CFG_CENTER_EE2BEG3_3", - "CFG_CENTER_EE2BEG3_4", - "CFG_CENTER_EE2BEG3_5", - "CFG_CENTER_EE2BEG3_6", - "CFG_CENTER_EE2BEG3_7", - "CFG_CENTER_EE2BEG3_8", - "CFG_CENTER_EE2BEG3_9", - "CFG_CENTER_EE4A0_0", - "CFG_CENTER_EE4A0_1", - "CFG_CENTER_EE4A0_10", - "CFG_CENTER_EE4A0_11", - "CFG_CENTER_EE4A0_12", - "CFG_CENTER_EE4A0_13", - "CFG_CENTER_EE4A0_14", - "CFG_CENTER_EE4A0_15", - "CFG_CENTER_EE4A0_16", - "CFG_CENTER_EE4A0_17", - "CFG_CENTER_EE4A0_18", - "CFG_CENTER_EE4A0_19", - "CFG_CENTER_EE4A0_2", - "CFG_CENTER_EE4A0_3", - "CFG_CENTER_EE4A0_4", - "CFG_CENTER_EE4A0_5", - "CFG_CENTER_EE4A0_6", - "CFG_CENTER_EE4A0_7", - "CFG_CENTER_EE4A0_8", - "CFG_CENTER_EE4A0_9", - "CFG_CENTER_EE4A1_0", - "CFG_CENTER_EE4A1_1", - "CFG_CENTER_EE4A1_10", - "CFG_CENTER_EE4A1_11", - "CFG_CENTER_EE4A1_12", - "CFG_CENTER_EE4A1_13", - "CFG_CENTER_EE4A1_14", - "CFG_CENTER_EE4A1_15", - "CFG_CENTER_EE4A1_16", - "CFG_CENTER_EE4A1_17", - "CFG_CENTER_EE4A1_18", - "CFG_CENTER_EE4A1_19", - "CFG_CENTER_EE4A1_2", - "CFG_CENTER_EE4A1_3", - "CFG_CENTER_EE4A1_4", - "CFG_CENTER_EE4A1_5", - "CFG_CENTER_EE4A1_6", - "CFG_CENTER_EE4A1_7", - "CFG_CENTER_EE4A1_8", - "CFG_CENTER_EE4A1_9", - "CFG_CENTER_EE4A2_0", - "CFG_CENTER_EE4A2_1", - "CFG_CENTER_EE4A2_10", - "CFG_CENTER_EE4A2_11", - "CFG_CENTER_EE4A2_12", - "CFG_CENTER_EE4A2_13", - "CFG_CENTER_EE4A2_14", - "CFG_CENTER_EE4A2_15", - "CFG_CENTER_EE4A2_16", - "CFG_CENTER_EE4A2_17", - "CFG_CENTER_EE4A2_18", - "CFG_CENTER_EE4A2_19", - "CFG_CENTER_EE4A2_2", - "CFG_CENTER_EE4A2_3", - "CFG_CENTER_EE4A2_4", - "CFG_CENTER_EE4A2_5", - "CFG_CENTER_EE4A2_6", - "CFG_CENTER_EE4A2_7", - "CFG_CENTER_EE4A2_8", - "CFG_CENTER_EE4A2_9", - "CFG_CENTER_EE4A3_0", - "CFG_CENTER_EE4A3_1", - "CFG_CENTER_EE4A3_10", - "CFG_CENTER_EE4A3_11", - "CFG_CENTER_EE4A3_12", - "CFG_CENTER_EE4A3_13", - "CFG_CENTER_EE4A3_14", - "CFG_CENTER_EE4A3_15", - "CFG_CENTER_EE4A3_16", - "CFG_CENTER_EE4A3_17", - "CFG_CENTER_EE4A3_18", - "CFG_CENTER_EE4A3_19", - "CFG_CENTER_EE4A3_2", - "CFG_CENTER_EE4A3_3", - "CFG_CENTER_EE4A3_4", - "CFG_CENTER_EE4A3_5", - "CFG_CENTER_EE4A3_6", - "CFG_CENTER_EE4A3_7", - "CFG_CENTER_EE4A3_8", - "CFG_CENTER_EE4A3_9", - "CFG_CENTER_EE4B0_0", - "CFG_CENTER_EE4B0_1", - "CFG_CENTER_EE4B0_10", - "CFG_CENTER_EE4B0_11", - "CFG_CENTER_EE4B0_12", - "CFG_CENTER_EE4B0_13", - "CFG_CENTER_EE4B0_14", - "CFG_CENTER_EE4B0_15", - "CFG_CENTER_EE4B0_16", - "CFG_CENTER_EE4B0_17", - "CFG_CENTER_EE4B0_18", - "CFG_CENTER_EE4B0_19", - "CFG_CENTER_EE4B0_2", - "CFG_CENTER_EE4B0_3", - "CFG_CENTER_EE4B0_4", - "CFG_CENTER_EE4B0_5", - "CFG_CENTER_EE4B0_6", - "CFG_CENTER_EE4B0_7", - "CFG_CENTER_EE4B0_8", - "CFG_CENTER_EE4B0_9", - "CFG_CENTER_EE4B1_0", - "CFG_CENTER_EE4B1_1", - "CFG_CENTER_EE4B1_10", - "CFG_CENTER_EE4B1_11", - "CFG_CENTER_EE4B1_12", - "CFG_CENTER_EE4B1_13", - "CFG_CENTER_EE4B1_14", - "CFG_CENTER_EE4B1_15", - "CFG_CENTER_EE4B1_16", - "CFG_CENTER_EE4B1_17", - "CFG_CENTER_EE4B1_18", - "CFG_CENTER_EE4B1_19", - "CFG_CENTER_EE4B1_2", - "CFG_CENTER_EE4B1_3", - "CFG_CENTER_EE4B1_4", - "CFG_CENTER_EE4B1_5", - "CFG_CENTER_EE4B1_6", - "CFG_CENTER_EE4B1_7", - "CFG_CENTER_EE4B1_8", - "CFG_CENTER_EE4B1_9", - "CFG_CENTER_EE4B2_0", - "CFG_CENTER_EE4B2_1", - "CFG_CENTER_EE4B2_10", - "CFG_CENTER_EE4B2_11", - "CFG_CENTER_EE4B2_12", - "CFG_CENTER_EE4B2_13", - "CFG_CENTER_EE4B2_14", - "CFG_CENTER_EE4B2_15", - "CFG_CENTER_EE4B2_16", - "CFG_CENTER_EE4B2_17", - "CFG_CENTER_EE4B2_18", - "CFG_CENTER_EE4B2_19", - "CFG_CENTER_EE4B2_2", - "CFG_CENTER_EE4B2_3", - "CFG_CENTER_EE4B2_4", - "CFG_CENTER_EE4B2_5", - "CFG_CENTER_EE4B2_6", - "CFG_CENTER_EE4B2_7", - "CFG_CENTER_EE4B2_8", - "CFG_CENTER_EE4B2_9", - "CFG_CENTER_EE4B3_0", - "CFG_CENTER_EE4B3_1", - "CFG_CENTER_EE4B3_10", - "CFG_CENTER_EE4B3_11", - "CFG_CENTER_EE4B3_12", - "CFG_CENTER_EE4B3_13", - "CFG_CENTER_EE4B3_14", - "CFG_CENTER_EE4B3_15", - "CFG_CENTER_EE4B3_16", - "CFG_CENTER_EE4B3_17", - "CFG_CENTER_EE4B3_18", - "CFG_CENTER_EE4B3_19", - "CFG_CENTER_EE4B3_2", - "CFG_CENTER_EE4B3_3", - "CFG_CENTER_EE4B3_4", - "CFG_CENTER_EE4B3_5", - "CFG_CENTER_EE4B3_6", - "CFG_CENTER_EE4B3_7", - "CFG_CENTER_EE4B3_8", - "CFG_CENTER_EE4B3_9", - "CFG_CENTER_EE4BEG0_0", - "CFG_CENTER_EE4BEG0_1", - "CFG_CENTER_EE4BEG0_10", - "CFG_CENTER_EE4BEG0_11", - "CFG_CENTER_EE4BEG0_12", - "CFG_CENTER_EE4BEG0_13", - "CFG_CENTER_EE4BEG0_14", - "CFG_CENTER_EE4BEG0_15", - "CFG_CENTER_EE4BEG0_16", - "CFG_CENTER_EE4BEG0_17", - "CFG_CENTER_EE4BEG0_18", - "CFG_CENTER_EE4BEG0_19", - "CFG_CENTER_EE4BEG0_2", - "CFG_CENTER_EE4BEG0_3", - "CFG_CENTER_EE4BEG0_4", - "CFG_CENTER_EE4BEG0_5", - "CFG_CENTER_EE4BEG0_6", - "CFG_CENTER_EE4BEG0_7", - "CFG_CENTER_EE4BEG0_8", - "CFG_CENTER_EE4BEG0_9", - "CFG_CENTER_EE4BEG1_0", - "CFG_CENTER_EE4BEG1_1", - "CFG_CENTER_EE4BEG1_10", - "CFG_CENTER_EE4BEG1_11", - "CFG_CENTER_EE4BEG1_12", - "CFG_CENTER_EE4BEG1_13", - "CFG_CENTER_EE4BEG1_14", - "CFG_CENTER_EE4BEG1_15", - "CFG_CENTER_EE4BEG1_16", - "CFG_CENTER_EE4BEG1_17", - "CFG_CENTER_EE4BEG1_18", - "CFG_CENTER_EE4BEG1_19", - "CFG_CENTER_EE4BEG1_2", - "CFG_CENTER_EE4BEG1_3", - "CFG_CENTER_EE4BEG1_4", - "CFG_CENTER_EE4BEG1_5", - "CFG_CENTER_EE4BEG1_6", - "CFG_CENTER_EE4BEG1_7", - "CFG_CENTER_EE4BEG1_8", - "CFG_CENTER_EE4BEG1_9", - "CFG_CENTER_EE4BEG2_0", - "CFG_CENTER_EE4BEG2_1", - "CFG_CENTER_EE4BEG2_10", - "CFG_CENTER_EE4BEG2_11", - "CFG_CENTER_EE4BEG2_12", - "CFG_CENTER_EE4BEG2_13", - "CFG_CENTER_EE4BEG2_14", - "CFG_CENTER_EE4BEG2_15", - "CFG_CENTER_EE4BEG2_16", - "CFG_CENTER_EE4BEG2_17", - "CFG_CENTER_EE4BEG2_18", - "CFG_CENTER_EE4BEG2_19", - "CFG_CENTER_EE4BEG2_2", - "CFG_CENTER_EE4BEG2_3", - "CFG_CENTER_EE4BEG2_4", - "CFG_CENTER_EE4BEG2_5", - "CFG_CENTER_EE4BEG2_6", - "CFG_CENTER_EE4BEG2_7", - "CFG_CENTER_EE4BEG2_8", - "CFG_CENTER_EE4BEG2_9", - "CFG_CENTER_EE4BEG3_0", - "CFG_CENTER_EE4BEG3_1", - "CFG_CENTER_EE4BEG3_10", - "CFG_CENTER_EE4BEG3_11", - "CFG_CENTER_EE4BEG3_12", - "CFG_CENTER_EE4BEG3_13", - "CFG_CENTER_EE4BEG3_14", - "CFG_CENTER_EE4BEG3_15", - "CFG_CENTER_EE4BEG3_16", - "CFG_CENTER_EE4BEG3_17", - "CFG_CENTER_EE4BEG3_18", - "CFG_CENTER_EE4BEG3_19", - "CFG_CENTER_EE4BEG3_2", - "CFG_CENTER_EE4BEG3_3", - "CFG_CENTER_EE4BEG3_4", - "CFG_CENTER_EE4BEG3_5", - "CFG_CENTER_EE4BEG3_6", - "CFG_CENTER_EE4BEG3_7", - "CFG_CENTER_EE4BEG3_8", - "CFG_CENTER_EE4BEG3_9", - "CFG_CENTER_EE4C0_0", - "CFG_CENTER_EE4C0_1", - "CFG_CENTER_EE4C0_10", - "CFG_CENTER_EE4C0_11", - "CFG_CENTER_EE4C0_12", - "CFG_CENTER_EE4C0_13", - "CFG_CENTER_EE4C0_14", - "CFG_CENTER_EE4C0_15", - "CFG_CENTER_EE4C0_16", - "CFG_CENTER_EE4C0_17", - "CFG_CENTER_EE4C0_18", - "CFG_CENTER_EE4C0_19", - "CFG_CENTER_EE4C0_2", - "CFG_CENTER_EE4C0_3", - "CFG_CENTER_EE4C0_4", - "CFG_CENTER_EE4C0_5", - "CFG_CENTER_EE4C0_6", - "CFG_CENTER_EE4C0_7", - "CFG_CENTER_EE4C0_8", - "CFG_CENTER_EE4C0_9", - "CFG_CENTER_EE4C1_0", - "CFG_CENTER_EE4C1_1", - "CFG_CENTER_EE4C1_10", - "CFG_CENTER_EE4C1_11", - "CFG_CENTER_EE4C1_12", - "CFG_CENTER_EE4C1_13", - "CFG_CENTER_EE4C1_14", - "CFG_CENTER_EE4C1_15", - "CFG_CENTER_EE4C1_16", - "CFG_CENTER_EE4C1_17", - "CFG_CENTER_EE4C1_18", - "CFG_CENTER_EE4C1_19", - "CFG_CENTER_EE4C1_2", - "CFG_CENTER_EE4C1_3", - "CFG_CENTER_EE4C1_4", - "CFG_CENTER_EE4C1_5", - "CFG_CENTER_EE4C1_6", - "CFG_CENTER_EE4C1_7", - "CFG_CENTER_EE4C1_8", - "CFG_CENTER_EE4C1_9", - "CFG_CENTER_EE4C2_0", - "CFG_CENTER_EE4C2_1", - "CFG_CENTER_EE4C2_10", - "CFG_CENTER_EE4C2_11", - "CFG_CENTER_EE4C2_12", - "CFG_CENTER_EE4C2_13", - "CFG_CENTER_EE4C2_14", - "CFG_CENTER_EE4C2_15", - "CFG_CENTER_EE4C2_16", - "CFG_CENTER_EE4C2_17", - "CFG_CENTER_EE4C2_18", - "CFG_CENTER_EE4C2_19", - "CFG_CENTER_EE4C2_2", - "CFG_CENTER_EE4C2_3", - "CFG_CENTER_EE4C2_4", - "CFG_CENTER_EE4C2_5", - "CFG_CENTER_EE4C2_6", - "CFG_CENTER_EE4C2_7", - "CFG_CENTER_EE4C2_8", - "CFG_CENTER_EE4C2_9", - "CFG_CENTER_EE4C3_0", - "CFG_CENTER_EE4C3_1", - "CFG_CENTER_EE4C3_10", - "CFG_CENTER_EE4C3_11", - "CFG_CENTER_EE4C3_12", - "CFG_CENTER_EE4C3_13", - "CFG_CENTER_EE4C3_14", - "CFG_CENTER_EE4C3_15", - "CFG_CENTER_EE4C3_16", - "CFG_CENTER_EE4C3_17", - "CFG_CENTER_EE4C3_18", - "CFG_CENTER_EE4C3_19", - "CFG_CENTER_EE4C3_2", - "CFG_CENTER_EE4C3_3", - "CFG_CENTER_EE4C3_4", - "CFG_CENTER_EE4C3_5", - "CFG_CENTER_EE4C3_6", - "CFG_CENTER_EE4C3_7", - "CFG_CENTER_EE4C3_8", - "CFG_CENTER_EE4C3_9", - "CFG_CENTER_EL1BEG0_0", - "CFG_CENTER_EL1BEG0_1", - "CFG_CENTER_EL1BEG0_10", - "CFG_CENTER_EL1BEG0_11", - "CFG_CENTER_EL1BEG0_12", - "CFG_CENTER_EL1BEG0_13", - "CFG_CENTER_EL1BEG0_14", - "CFG_CENTER_EL1BEG0_15", - "CFG_CENTER_EL1BEG0_16", - "CFG_CENTER_EL1BEG0_17", - "CFG_CENTER_EL1BEG0_18", - "CFG_CENTER_EL1BEG0_19", - "CFG_CENTER_EL1BEG0_2", - "CFG_CENTER_EL1BEG0_3", - "CFG_CENTER_EL1BEG0_4", - "CFG_CENTER_EL1BEG0_5", - "CFG_CENTER_EL1BEG0_6", - "CFG_CENTER_EL1BEG0_7", - "CFG_CENTER_EL1BEG0_8", - "CFG_CENTER_EL1BEG0_9", - "CFG_CENTER_EL1BEG1_0", - "CFG_CENTER_EL1BEG1_1", - "CFG_CENTER_EL1BEG1_10", - "CFG_CENTER_EL1BEG1_11", - "CFG_CENTER_EL1BEG1_12", - "CFG_CENTER_EL1BEG1_13", - "CFG_CENTER_EL1BEG1_14", - "CFG_CENTER_EL1BEG1_15", - "CFG_CENTER_EL1BEG1_16", - "CFG_CENTER_EL1BEG1_17", - "CFG_CENTER_EL1BEG1_18", - "CFG_CENTER_EL1BEG1_19", - "CFG_CENTER_EL1BEG1_2", - "CFG_CENTER_EL1BEG1_3", - "CFG_CENTER_EL1BEG1_4", - "CFG_CENTER_EL1BEG1_5", - "CFG_CENTER_EL1BEG1_6", - "CFG_CENTER_EL1BEG1_7", - "CFG_CENTER_EL1BEG1_8", - "CFG_CENTER_EL1BEG1_9", - "CFG_CENTER_EL1BEG2_0", - "CFG_CENTER_EL1BEG2_1", - "CFG_CENTER_EL1BEG2_10", - "CFG_CENTER_EL1BEG2_11", - "CFG_CENTER_EL1BEG2_12", - "CFG_CENTER_EL1BEG2_13", - "CFG_CENTER_EL1BEG2_14", - "CFG_CENTER_EL1BEG2_15", - "CFG_CENTER_EL1BEG2_16", - "CFG_CENTER_EL1BEG2_17", - "CFG_CENTER_EL1BEG2_18", - "CFG_CENTER_EL1BEG2_19", - "CFG_CENTER_EL1BEG2_2", - "CFG_CENTER_EL1BEG2_3", - "CFG_CENTER_EL1BEG2_4", - "CFG_CENTER_EL1BEG2_5", - "CFG_CENTER_EL1BEG2_6", - "CFG_CENTER_EL1BEG2_7", - "CFG_CENTER_EL1BEG2_8", - "CFG_CENTER_EL1BEG2_9", - "CFG_CENTER_EL1BEG3_0", - "CFG_CENTER_EL1BEG3_1", - "CFG_CENTER_EL1BEG3_10", - "CFG_CENTER_EL1BEG3_11", - "CFG_CENTER_EL1BEG3_12", - "CFG_CENTER_EL1BEG3_13", - "CFG_CENTER_EL1BEG3_14", - "CFG_CENTER_EL1BEG3_15", - "CFG_CENTER_EL1BEG3_16", - "CFG_CENTER_EL1BEG3_17", - "CFG_CENTER_EL1BEG3_18", - "CFG_CENTER_EL1BEG3_19", - "CFG_CENTER_EL1BEG3_2", - "CFG_CENTER_EL1BEG3_3", - "CFG_CENTER_EL1BEG3_4", - "CFG_CENTER_EL1BEG3_5", - "CFG_CENTER_EL1BEG3_6", - "CFG_CENTER_EL1BEG3_7", - "CFG_CENTER_EL1BEG3_8", - "CFG_CENTER_EL1BEG3_9", - "CFG_CENTER_ER1BEG0_0", - "CFG_CENTER_ER1BEG0_1", - "CFG_CENTER_ER1BEG0_10", - "CFG_CENTER_ER1BEG0_11", - "CFG_CENTER_ER1BEG0_12", - "CFG_CENTER_ER1BEG0_13", - "CFG_CENTER_ER1BEG0_14", - "CFG_CENTER_ER1BEG0_15", - "CFG_CENTER_ER1BEG0_16", - "CFG_CENTER_ER1BEG0_17", - "CFG_CENTER_ER1BEG0_18", - "CFG_CENTER_ER1BEG0_19", - "CFG_CENTER_ER1BEG0_2", - "CFG_CENTER_ER1BEG0_3", - "CFG_CENTER_ER1BEG0_4", - "CFG_CENTER_ER1BEG0_5", - "CFG_CENTER_ER1BEG0_6", - "CFG_CENTER_ER1BEG0_7", - "CFG_CENTER_ER1BEG0_8", - "CFG_CENTER_ER1BEG0_9", - "CFG_CENTER_ER1BEG1_0", - "CFG_CENTER_ER1BEG1_1", - "CFG_CENTER_ER1BEG1_10", - "CFG_CENTER_ER1BEG1_11", - "CFG_CENTER_ER1BEG1_12", - "CFG_CENTER_ER1BEG1_13", - "CFG_CENTER_ER1BEG1_14", - "CFG_CENTER_ER1BEG1_15", - "CFG_CENTER_ER1BEG1_16", - "CFG_CENTER_ER1BEG1_17", - "CFG_CENTER_ER1BEG1_18", - "CFG_CENTER_ER1BEG1_19", - "CFG_CENTER_ER1BEG1_2", - "CFG_CENTER_ER1BEG1_3", - "CFG_CENTER_ER1BEG1_4", - "CFG_CENTER_ER1BEG1_5", - "CFG_CENTER_ER1BEG1_6", - "CFG_CENTER_ER1BEG1_7", - "CFG_CENTER_ER1BEG1_8", - "CFG_CENTER_ER1BEG1_9", - "CFG_CENTER_ER1BEG2_0", - "CFG_CENTER_ER1BEG2_1", - "CFG_CENTER_ER1BEG2_10", - "CFG_CENTER_ER1BEG2_11", - "CFG_CENTER_ER1BEG2_12", - "CFG_CENTER_ER1BEG2_13", - "CFG_CENTER_ER1BEG2_14", - "CFG_CENTER_ER1BEG2_15", - "CFG_CENTER_ER1BEG2_16", - "CFG_CENTER_ER1BEG2_17", - "CFG_CENTER_ER1BEG2_18", - "CFG_CENTER_ER1BEG2_19", - "CFG_CENTER_ER1BEG2_2", - "CFG_CENTER_ER1BEG2_3", - "CFG_CENTER_ER1BEG2_4", - "CFG_CENTER_ER1BEG2_5", - "CFG_CENTER_ER1BEG2_6", - "CFG_CENTER_ER1BEG2_7", - "CFG_CENTER_ER1BEG2_8", - "CFG_CENTER_ER1BEG2_9", - "CFG_CENTER_ER1BEG3_0", - "CFG_CENTER_ER1BEG3_1", - "CFG_CENTER_ER1BEG3_10", - "CFG_CENTER_ER1BEG3_11", - "CFG_CENTER_ER1BEG3_12", - "CFG_CENTER_ER1BEG3_13", - "CFG_CENTER_ER1BEG3_14", - "CFG_CENTER_ER1BEG3_15", - "CFG_CENTER_ER1BEG3_16", - "CFG_CENTER_ER1BEG3_17", - "CFG_CENTER_ER1BEG3_18", - "CFG_CENTER_ER1BEG3_19", - "CFG_CENTER_ER1BEG3_2", - "CFG_CENTER_ER1BEG3_3", - "CFG_CENTER_ER1BEG3_4", - "CFG_CENTER_ER1BEG3_5", - "CFG_CENTER_ER1BEG3_6", - "CFG_CENTER_ER1BEG3_7", - "CFG_CENTER_ER1BEG3_8", - "CFG_CENTER_ER1BEG3_9", - "CFG_CENTER_FAN0_0", - "CFG_CENTER_FAN0_1", - "CFG_CENTER_FAN0_10", - "CFG_CENTER_FAN0_11", - "CFG_CENTER_FAN0_12", - "CFG_CENTER_FAN0_13", - "CFG_CENTER_FAN0_14", - "CFG_CENTER_FAN0_15", - "CFG_CENTER_FAN0_16", - "CFG_CENTER_FAN0_17", - "CFG_CENTER_FAN0_18", - "CFG_CENTER_FAN0_19", - "CFG_CENTER_FAN0_2", - "CFG_CENTER_FAN0_3", - "CFG_CENTER_FAN0_4", - "CFG_CENTER_FAN0_5", - "CFG_CENTER_FAN0_6", - "CFG_CENTER_FAN0_7", - "CFG_CENTER_FAN0_8", - "CFG_CENTER_FAN0_9", - "CFG_CENTER_FAN1_0", - "CFG_CENTER_FAN1_1", - "CFG_CENTER_FAN1_10", - "CFG_CENTER_FAN1_11", - "CFG_CENTER_FAN1_12", - "CFG_CENTER_FAN1_13", - "CFG_CENTER_FAN1_14", - "CFG_CENTER_FAN1_15", - "CFG_CENTER_FAN1_16", - "CFG_CENTER_FAN1_17", - "CFG_CENTER_FAN1_18", - "CFG_CENTER_FAN1_19", - "CFG_CENTER_FAN1_2", - "CFG_CENTER_FAN1_3", - "CFG_CENTER_FAN1_4", - "CFG_CENTER_FAN1_5", - "CFG_CENTER_FAN1_6", - "CFG_CENTER_FAN1_7", - "CFG_CENTER_FAN1_8", - "CFG_CENTER_FAN1_9", - "CFG_CENTER_FAN2_0", - "CFG_CENTER_FAN2_1", - "CFG_CENTER_FAN2_10", - "CFG_CENTER_FAN2_11", - "CFG_CENTER_FAN2_12", - "CFG_CENTER_FAN2_13", - "CFG_CENTER_FAN2_14", - "CFG_CENTER_FAN2_15", - "CFG_CENTER_FAN2_16", - "CFG_CENTER_FAN2_17", - "CFG_CENTER_FAN2_18", - "CFG_CENTER_FAN2_19", - "CFG_CENTER_FAN2_2", - "CFG_CENTER_FAN2_3", - "CFG_CENTER_FAN2_4", - "CFG_CENTER_FAN2_5", - "CFG_CENTER_FAN2_6", - "CFG_CENTER_FAN2_7", - "CFG_CENTER_FAN2_8", - "CFG_CENTER_FAN2_9", - "CFG_CENTER_FAN3_0", - "CFG_CENTER_FAN3_1", - "CFG_CENTER_FAN3_10", - "CFG_CENTER_FAN3_11", - "CFG_CENTER_FAN3_12", - "CFG_CENTER_FAN3_13", - "CFG_CENTER_FAN3_14", - "CFG_CENTER_FAN3_15", - "CFG_CENTER_FAN3_16", - "CFG_CENTER_FAN3_17", - "CFG_CENTER_FAN3_18", - "CFG_CENTER_FAN3_19", - "CFG_CENTER_FAN3_2", - "CFG_CENTER_FAN3_3", - "CFG_CENTER_FAN3_4", - "CFG_CENTER_FAN3_5", - "CFG_CENTER_FAN3_6", - "CFG_CENTER_FAN3_7", - "CFG_CENTER_FAN3_8", - "CFG_CENTER_FAN3_9", - "CFG_CENTER_FAN4_0", - "CFG_CENTER_FAN4_1", - "CFG_CENTER_FAN4_10", - "CFG_CENTER_FAN4_11", - "CFG_CENTER_FAN4_12", - "CFG_CENTER_FAN4_13", - "CFG_CENTER_FAN4_14", - "CFG_CENTER_FAN4_15", - "CFG_CENTER_FAN4_16", - "CFG_CENTER_FAN4_17", - "CFG_CENTER_FAN4_18", - "CFG_CENTER_FAN4_19", - "CFG_CENTER_FAN4_2", - "CFG_CENTER_FAN4_3", - "CFG_CENTER_FAN4_4", - "CFG_CENTER_FAN4_5", - "CFG_CENTER_FAN4_6", - "CFG_CENTER_FAN4_7", - "CFG_CENTER_FAN4_8", - "CFG_CENTER_FAN4_9", - "CFG_CENTER_FAN5_0", - "CFG_CENTER_FAN5_1", - "CFG_CENTER_FAN5_10", - "CFG_CENTER_FAN5_11", - "CFG_CENTER_FAN5_12", - "CFG_CENTER_FAN5_13", - "CFG_CENTER_FAN5_14", - "CFG_CENTER_FAN5_15", - "CFG_CENTER_FAN5_16", - "CFG_CENTER_FAN5_17", - "CFG_CENTER_FAN5_18", - "CFG_CENTER_FAN5_19", - "CFG_CENTER_FAN5_2", - "CFG_CENTER_FAN5_3", - "CFG_CENTER_FAN5_4", - "CFG_CENTER_FAN5_5", - "CFG_CENTER_FAN5_6", - "CFG_CENTER_FAN5_7", - "CFG_CENTER_FAN5_8", - "CFG_CENTER_FAN5_9", - "CFG_CENTER_FAN6_0", - "CFG_CENTER_FAN6_1", - "CFG_CENTER_FAN6_10", - "CFG_CENTER_FAN6_11", - "CFG_CENTER_FAN6_12", - "CFG_CENTER_FAN6_13", - "CFG_CENTER_FAN6_14", - "CFG_CENTER_FAN6_15", - "CFG_CENTER_FAN6_16", - "CFG_CENTER_FAN6_17", - "CFG_CENTER_FAN6_18", - "CFG_CENTER_FAN6_19", - "CFG_CENTER_FAN6_2", - "CFG_CENTER_FAN6_3", - "CFG_CENTER_FAN6_4", - "CFG_CENTER_FAN6_5", - "CFG_CENTER_FAN6_6", - "CFG_CENTER_FAN6_7", - "CFG_CENTER_FAN6_8", - "CFG_CENTER_FAN6_9", - "CFG_CENTER_FAN7_0", - "CFG_CENTER_FAN7_1", - "CFG_CENTER_FAN7_10", - "CFG_CENTER_FAN7_11", - "CFG_CENTER_FAN7_12", - "CFG_CENTER_FAN7_13", - "CFG_CENTER_FAN7_14", - "CFG_CENTER_FAN7_15", - "CFG_CENTER_FAN7_16", - "CFG_CENTER_FAN7_17", - "CFG_CENTER_FAN7_18", - "CFG_CENTER_FAN7_19", - "CFG_CENTER_FAN7_2", - "CFG_CENTER_FAN7_3", - "CFG_CENTER_FAN7_4", - "CFG_CENTER_FAN7_5", - "CFG_CENTER_FAN7_6", - "CFG_CENTER_FAN7_7", - "CFG_CENTER_FAN7_8", - "CFG_CENTER_FAN7_9", - "CFG_CENTER_IMUX0_0", - "CFG_CENTER_IMUX0_1", - "CFG_CENTER_IMUX0_10", - "CFG_CENTER_IMUX0_11", - "CFG_CENTER_IMUX0_12", - "CFG_CENTER_IMUX0_13", - "CFG_CENTER_IMUX0_14", - "CFG_CENTER_IMUX0_15", - "CFG_CENTER_IMUX0_16", - "CFG_CENTER_IMUX0_17", - "CFG_CENTER_IMUX0_18", - "CFG_CENTER_IMUX0_19", - "CFG_CENTER_IMUX0_2", - "CFG_CENTER_IMUX0_3", - "CFG_CENTER_IMUX0_4", - "CFG_CENTER_IMUX0_5", - "CFG_CENTER_IMUX0_6", - "CFG_CENTER_IMUX0_7", - "CFG_CENTER_IMUX0_8", - "CFG_CENTER_IMUX0_9", - "CFG_CENTER_IMUX10_0", - "CFG_CENTER_IMUX10_1", - "CFG_CENTER_IMUX10_10", - "CFG_CENTER_IMUX10_11", - "CFG_CENTER_IMUX10_12", - "CFG_CENTER_IMUX10_13", - "CFG_CENTER_IMUX10_14", - "CFG_CENTER_IMUX10_15", - "CFG_CENTER_IMUX10_16", - "CFG_CENTER_IMUX10_17", - "CFG_CENTER_IMUX10_18", - "CFG_CENTER_IMUX10_19", - "CFG_CENTER_IMUX10_2", - "CFG_CENTER_IMUX10_3", - "CFG_CENTER_IMUX10_4", - "CFG_CENTER_IMUX10_5", - "CFG_CENTER_IMUX10_6", - "CFG_CENTER_IMUX10_7", - "CFG_CENTER_IMUX10_8", - "CFG_CENTER_IMUX10_9", - "CFG_CENTER_IMUX11_0", - "CFG_CENTER_IMUX11_1", - "CFG_CENTER_IMUX11_10", - "CFG_CENTER_IMUX11_11", - "CFG_CENTER_IMUX11_12", - "CFG_CENTER_IMUX11_13", - "CFG_CENTER_IMUX11_14", - "CFG_CENTER_IMUX11_15", - "CFG_CENTER_IMUX11_16", - "CFG_CENTER_IMUX11_17", - "CFG_CENTER_IMUX11_18", - "CFG_CENTER_IMUX11_19", - "CFG_CENTER_IMUX11_2", - "CFG_CENTER_IMUX11_3", - "CFG_CENTER_IMUX11_4", - "CFG_CENTER_IMUX11_5", - "CFG_CENTER_IMUX11_6", - "CFG_CENTER_IMUX11_7", - "CFG_CENTER_IMUX11_8", - "CFG_CENTER_IMUX11_9", - "CFG_CENTER_IMUX12_0", - "CFG_CENTER_IMUX12_1", - "CFG_CENTER_IMUX12_10", - "CFG_CENTER_IMUX12_11", - "CFG_CENTER_IMUX12_12", - "CFG_CENTER_IMUX12_13", - "CFG_CENTER_IMUX12_14", - "CFG_CENTER_IMUX12_15", - "CFG_CENTER_IMUX12_16", - "CFG_CENTER_IMUX12_17", - "CFG_CENTER_IMUX12_18", - "CFG_CENTER_IMUX12_19", - "CFG_CENTER_IMUX12_2", - "CFG_CENTER_IMUX12_3", - "CFG_CENTER_IMUX12_4", - "CFG_CENTER_IMUX12_5", - "CFG_CENTER_IMUX12_6", - "CFG_CENTER_IMUX12_7", - "CFG_CENTER_IMUX12_8", - "CFG_CENTER_IMUX12_9", - "CFG_CENTER_IMUX13_0", - "CFG_CENTER_IMUX13_1", - "CFG_CENTER_IMUX13_10", - "CFG_CENTER_IMUX13_11", - "CFG_CENTER_IMUX13_12", - "CFG_CENTER_IMUX13_13", - "CFG_CENTER_IMUX13_14", - "CFG_CENTER_IMUX13_15", - "CFG_CENTER_IMUX13_16", - "CFG_CENTER_IMUX13_17", - "CFG_CENTER_IMUX13_18", - "CFG_CENTER_IMUX13_19", - "CFG_CENTER_IMUX13_2", - "CFG_CENTER_IMUX13_3", - "CFG_CENTER_IMUX13_4", - "CFG_CENTER_IMUX13_5", - "CFG_CENTER_IMUX13_6", - "CFG_CENTER_IMUX13_7", - "CFG_CENTER_IMUX13_8", - "CFG_CENTER_IMUX13_9", - "CFG_CENTER_IMUX14_0", - "CFG_CENTER_IMUX14_1", - "CFG_CENTER_IMUX14_10", - "CFG_CENTER_IMUX14_11", - "CFG_CENTER_IMUX14_12", - "CFG_CENTER_IMUX14_13", - "CFG_CENTER_IMUX14_14", - "CFG_CENTER_IMUX14_15", - "CFG_CENTER_IMUX14_16", - "CFG_CENTER_IMUX14_17", - "CFG_CENTER_IMUX14_18", - "CFG_CENTER_IMUX14_19", - "CFG_CENTER_IMUX14_2", - "CFG_CENTER_IMUX14_3", - "CFG_CENTER_IMUX14_4", - "CFG_CENTER_IMUX14_5", - "CFG_CENTER_IMUX14_6", - "CFG_CENTER_IMUX14_7", - "CFG_CENTER_IMUX14_8", - "CFG_CENTER_IMUX14_9", - "CFG_CENTER_IMUX15_0", - "CFG_CENTER_IMUX15_1", - "CFG_CENTER_IMUX15_10", - "CFG_CENTER_IMUX15_11", - "CFG_CENTER_IMUX15_12", - "CFG_CENTER_IMUX15_13", - "CFG_CENTER_IMUX15_14", - "CFG_CENTER_IMUX15_15", - "CFG_CENTER_IMUX15_16", - "CFG_CENTER_IMUX15_17", - "CFG_CENTER_IMUX15_18", - "CFG_CENTER_IMUX15_19", - "CFG_CENTER_IMUX15_2", - "CFG_CENTER_IMUX15_3", - "CFG_CENTER_IMUX15_4", - "CFG_CENTER_IMUX15_5", - "CFG_CENTER_IMUX15_6", - "CFG_CENTER_IMUX15_7", - "CFG_CENTER_IMUX15_8", - "CFG_CENTER_IMUX15_9", - "CFG_CENTER_IMUX16_0", - "CFG_CENTER_IMUX16_1", - "CFG_CENTER_IMUX16_10", - "CFG_CENTER_IMUX16_11", - "CFG_CENTER_IMUX16_12", - "CFG_CENTER_IMUX16_13", - "CFG_CENTER_IMUX16_14", - "CFG_CENTER_IMUX16_15", - "CFG_CENTER_IMUX16_16", - "CFG_CENTER_IMUX16_17", - "CFG_CENTER_IMUX16_18", - "CFG_CENTER_IMUX16_19", - "CFG_CENTER_IMUX16_2", - "CFG_CENTER_IMUX16_3", - "CFG_CENTER_IMUX16_4", - "CFG_CENTER_IMUX16_5", - "CFG_CENTER_IMUX16_6", - "CFG_CENTER_IMUX16_7", - "CFG_CENTER_IMUX16_8", - "CFG_CENTER_IMUX16_9", - "CFG_CENTER_IMUX17_0", - "CFG_CENTER_IMUX17_1", - "CFG_CENTER_IMUX17_10", - "CFG_CENTER_IMUX17_11", - "CFG_CENTER_IMUX17_12", - "CFG_CENTER_IMUX17_13", - "CFG_CENTER_IMUX17_14", - "CFG_CENTER_IMUX17_15", - "CFG_CENTER_IMUX17_16", - "CFG_CENTER_IMUX17_17", - "CFG_CENTER_IMUX17_18", - "CFG_CENTER_IMUX17_19", - "CFG_CENTER_IMUX17_2", - "CFG_CENTER_IMUX17_3", - "CFG_CENTER_IMUX17_4", - "CFG_CENTER_IMUX17_5", - "CFG_CENTER_IMUX17_6", - "CFG_CENTER_IMUX17_7", - "CFG_CENTER_IMUX17_8", - "CFG_CENTER_IMUX17_9", - "CFG_CENTER_IMUX18_0", - "CFG_CENTER_IMUX18_1", - "CFG_CENTER_IMUX18_10", - "CFG_CENTER_IMUX18_11", - "CFG_CENTER_IMUX18_12", - "CFG_CENTER_IMUX18_13", - "CFG_CENTER_IMUX18_14", - "CFG_CENTER_IMUX18_15", - "CFG_CENTER_IMUX18_16", - "CFG_CENTER_IMUX18_17", - "CFG_CENTER_IMUX18_18", - "CFG_CENTER_IMUX18_19", - "CFG_CENTER_IMUX18_2", - "CFG_CENTER_IMUX18_3", - "CFG_CENTER_IMUX18_4", - "CFG_CENTER_IMUX18_5", - "CFG_CENTER_IMUX18_6", - "CFG_CENTER_IMUX18_7", - "CFG_CENTER_IMUX18_8", - "CFG_CENTER_IMUX18_9", - "CFG_CENTER_IMUX19_0", - "CFG_CENTER_IMUX19_1", - "CFG_CENTER_IMUX19_10", - "CFG_CENTER_IMUX19_11", - "CFG_CENTER_IMUX19_12", - "CFG_CENTER_IMUX19_13", - "CFG_CENTER_IMUX19_14", - "CFG_CENTER_IMUX19_15", - "CFG_CENTER_IMUX19_16", - "CFG_CENTER_IMUX19_17", - "CFG_CENTER_IMUX19_18", - "CFG_CENTER_IMUX19_19", - "CFG_CENTER_IMUX19_2", - "CFG_CENTER_IMUX19_3", - "CFG_CENTER_IMUX19_4", - "CFG_CENTER_IMUX19_5", - "CFG_CENTER_IMUX19_6", - "CFG_CENTER_IMUX19_7", - "CFG_CENTER_IMUX19_8", - "CFG_CENTER_IMUX19_9", - "CFG_CENTER_IMUX1_0", - "CFG_CENTER_IMUX1_1", - "CFG_CENTER_IMUX1_10", - "CFG_CENTER_IMUX1_11", - "CFG_CENTER_IMUX1_12", - "CFG_CENTER_IMUX1_13", - "CFG_CENTER_IMUX1_14", - "CFG_CENTER_IMUX1_15", - "CFG_CENTER_IMUX1_16", - "CFG_CENTER_IMUX1_17", - "CFG_CENTER_IMUX1_18", - "CFG_CENTER_IMUX1_19", - "CFG_CENTER_IMUX1_2", - "CFG_CENTER_IMUX1_3", - "CFG_CENTER_IMUX1_4", - "CFG_CENTER_IMUX1_5", - "CFG_CENTER_IMUX1_6", - "CFG_CENTER_IMUX1_7", - "CFG_CENTER_IMUX1_8", - "CFG_CENTER_IMUX1_9", - "CFG_CENTER_IMUX20_0", - "CFG_CENTER_IMUX20_1", - "CFG_CENTER_IMUX20_10", - "CFG_CENTER_IMUX20_11", - "CFG_CENTER_IMUX20_12", - "CFG_CENTER_IMUX20_13", - "CFG_CENTER_IMUX20_14", - "CFG_CENTER_IMUX20_15", - "CFG_CENTER_IMUX20_16", - "CFG_CENTER_IMUX20_17", - "CFG_CENTER_IMUX20_18", - "CFG_CENTER_IMUX20_19", - "CFG_CENTER_IMUX20_2", - "CFG_CENTER_IMUX20_3", - "CFG_CENTER_IMUX20_4", - "CFG_CENTER_IMUX20_5", - "CFG_CENTER_IMUX20_6", - "CFG_CENTER_IMUX20_7", - "CFG_CENTER_IMUX20_8", - "CFG_CENTER_IMUX20_9", - "CFG_CENTER_IMUX21_0", - "CFG_CENTER_IMUX21_1", - "CFG_CENTER_IMUX21_10", - "CFG_CENTER_IMUX21_11", - "CFG_CENTER_IMUX21_12", - "CFG_CENTER_IMUX21_13", - "CFG_CENTER_IMUX21_14", - "CFG_CENTER_IMUX21_15", - "CFG_CENTER_IMUX21_16", - "CFG_CENTER_IMUX21_17", - "CFG_CENTER_IMUX21_18", - "CFG_CENTER_IMUX21_19", - "CFG_CENTER_IMUX21_2", - "CFG_CENTER_IMUX21_3", - "CFG_CENTER_IMUX21_4", - "CFG_CENTER_IMUX21_5", - "CFG_CENTER_IMUX21_6", - "CFG_CENTER_IMUX21_7", - "CFG_CENTER_IMUX21_8", - "CFG_CENTER_IMUX21_9", - "CFG_CENTER_IMUX22_0", - "CFG_CENTER_IMUX22_1", - "CFG_CENTER_IMUX22_10", - "CFG_CENTER_IMUX22_11", - "CFG_CENTER_IMUX22_12", - "CFG_CENTER_IMUX22_13", - "CFG_CENTER_IMUX22_14", - "CFG_CENTER_IMUX22_15", - "CFG_CENTER_IMUX22_16", - "CFG_CENTER_IMUX22_17", - "CFG_CENTER_IMUX22_18", - "CFG_CENTER_IMUX22_19", - "CFG_CENTER_IMUX22_2", - "CFG_CENTER_IMUX22_3", - "CFG_CENTER_IMUX22_4", - "CFG_CENTER_IMUX22_5", - "CFG_CENTER_IMUX22_6", - "CFG_CENTER_IMUX22_7", - "CFG_CENTER_IMUX22_8", - "CFG_CENTER_IMUX22_9", - "CFG_CENTER_IMUX23_0", - "CFG_CENTER_IMUX23_1", - "CFG_CENTER_IMUX23_10", - "CFG_CENTER_IMUX23_11", - "CFG_CENTER_IMUX23_12", - "CFG_CENTER_IMUX23_13", - "CFG_CENTER_IMUX23_14", - "CFG_CENTER_IMUX23_15", - "CFG_CENTER_IMUX23_16", - "CFG_CENTER_IMUX23_17", - "CFG_CENTER_IMUX23_18", - "CFG_CENTER_IMUX23_19", - "CFG_CENTER_IMUX23_2", - "CFG_CENTER_IMUX23_3", - "CFG_CENTER_IMUX23_4", - "CFG_CENTER_IMUX23_5", - "CFG_CENTER_IMUX23_6", - "CFG_CENTER_IMUX23_7", - "CFG_CENTER_IMUX23_8", - "CFG_CENTER_IMUX23_9", - "CFG_CENTER_IMUX24_0", - "CFG_CENTER_IMUX24_1", - "CFG_CENTER_IMUX24_10", - "CFG_CENTER_IMUX24_11", - "CFG_CENTER_IMUX24_12", - "CFG_CENTER_IMUX24_13", - "CFG_CENTER_IMUX24_14", - "CFG_CENTER_IMUX24_15", - "CFG_CENTER_IMUX24_16", - "CFG_CENTER_IMUX24_17", - "CFG_CENTER_IMUX24_18", - "CFG_CENTER_IMUX24_19", - "CFG_CENTER_IMUX24_2", - "CFG_CENTER_IMUX24_3", - "CFG_CENTER_IMUX24_4", - "CFG_CENTER_IMUX24_5", - "CFG_CENTER_IMUX24_6", - "CFG_CENTER_IMUX24_7", - "CFG_CENTER_IMUX24_8", - "CFG_CENTER_IMUX24_9", - "CFG_CENTER_IMUX25_0", - "CFG_CENTER_IMUX25_1", - "CFG_CENTER_IMUX25_10", - "CFG_CENTER_IMUX25_11", - "CFG_CENTER_IMUX25_12", - "CFG_CENTER_IMUX25_13", - "CFG_CENTER_IMUX25_14", - "CFG_CENTER_IMUX25_15", - "CFG_CENTER_IMUX25_16", - "CFG_CENTER_IMUX25_17", - "CFG_CENTER_IMUX25_18", - "CFG_CENTER_IMUX25_19", - "CFG_CENTER_IMUX25_2", - "CFG_CENTER_IMUX25_3", - "CFG_CENTER_IMUX25_4", - "CFG_CENTER_IMUX25_5", - "CFG_CENTER_IMUX25_6", - "CFG_CENTER_IMUX25_7", - "CFG_CENTER_IMUX25_8", - "CFG_CENTER_IMUX25_9", - "CFG_CENTER_IMUX26_0", - "CFG_CENTER_IMUX26_1", - "CFG_CENTER_IMUX26_10", - "CFG_CENTER_IMUX26_11", - "CFG_CENTER_IMUX26_12", - "CFG_CENTER_IMUX26_13", - "CFG_CENTER_IMUX26_14", - "CFG_CENTER_IMUX26_15", - "CFG_CENTER_IMUX26_16", - "CFG_CENTER_IMUX26_17", - "CFG_CENTER_IMUX26_18", - "CFG_CENTER_IMUX26_19", - "CFG_CENTER_IMUX26_2", - "CFG_CENTER_IMUX26_3", - "CFG_CENTER_IMUX26_4", - "CFG_CENTER_IMUX26_5", - "CFG_CENTER_IMUX26_6", - "CFG_CENTER_IMUX26_7", - "CFG_CENTER_IMUX26_8", - "CFG_CENTER_IMUX26_9", - "CFG_CENTER_IMUX27_0", - "CFG_CENTER_IMUX27_1", - "CFG_CENTER_IMUX27_10", - "CFG_CENTER_IMUX27_11", - "CFG_CENTER_IMUX27_12", - "CFG_CENTER_IMUX27_13", - "CFG_CENTER_IMUX27_14", - "CFG_CENTER_IMUX27_15", - "CFG_CENTER_IMUX27_16", - "CFG_CENTER_IMUX27_17", - "CFG_CENTER_IMUX27_18", - "CFG_CENTER_IMUX27_19", - "CFG_CENTER_IMUX27_2", - "CFG_CENTER_IMUX27_3", - "CFG_CENTER_IMUX27_4", - "CFG_CENTER_IMUX27_5", - "CFG_CENTER_IMUX27_6", - "CFG_CENTER_IMUX27_7", - "CFG_CENTER_IMUX27_8", - "CFG_CENTER_IMUX27_9", - "CFG_CENTER_IMUX28_0", - "CFG_CENTER_IMUX28_1", - "CFG_CENTER_IMUX28_10", - "CFG_CENTER_IMUX28_11", - "CFG_CENTER_IMUX28_12", - "CFG_CENTER_IMUX28_13", - "CFG_CENTER_IMUX28_14", - "CFG_CENTER_IMUX28_15", - "CFG_CENTER_IMUX28_16", - "CFG_CENTER_IMUX28_17", - "CFG_CENTER_IMUX28_18", - "CFG_CENTER_IMUX28_19", - "CFG_CENTER_IMUX28_2", - "CFG_CENTER_IMUX28_3", - "CFG_CENTER_IMUX28_4", - "CFG_CENTER_IMUX28_5", - "CFG_CENTER_IMUX28_6", - "CFG_CENTER_IMUX28_7", - "CFG_CENTER_IMUX28_8", - "CFG_CENTER_IMUX28_9", - "CFG_CENTER_IMUX29_0", - "CFG_CENTER_IMUX29_1", - "CFG_CENTER_IMUX29_10", - "CFG_CENTER_IMUX29_11", - "CFG_CENTER_IMUX29_12", - "CFG_CENTER_IMUX29_13", - "CFG_CENTER_IMUX29_14", - "CFG_CENTER_IMUX29_15", - "CFG_CENTER_IMUX29_16", - "CFG_CENTER_IMUX29_17", - "CFG_CENTER_IMUX29_18", - "CFG_CENTER_IMUX29_19", - "CFG_CENTER_IMUX29_2", - "CFG_CENTER_IMUX29_3", - "CFG_CENTER_IMUX29_4", - "CFG_CENTER_IMUX29_5", - "CFG_CENTER_IMUX29_6", - "CFG_CENTER_IMUX29_7", - "CFG_CENTER_IMUX29_8", - "CFG_CENTER_IMUX29_9", - "CFG_CENTER_IMUX2_0", - "CFG_CENTER_IMUX2_1", - "CFG_CENTER_IMUX2_10", - "CFG_CENTER_IMUX2_11", - "CFG_CENTER_IMUX2_12", - "CFG_CENTER_IMUX2_13", - "CFG_CENTER_IMUX2_14", - "CFG_CENTER_IMUX2_15", - "CFG_CENTER_IMUX2_16", - "CFG_CENTER_IMUX2_17", - "CFG_CENTER_IMUX2_18", - "CFG_CENTER_IMUX2_19", - "CFG_CENTER_IMUX2_2", - "CFG_CENTER_IMUX2_3", - "CFG_CENTER_IMUX2_4", - "CFG_CENTER_IMUX2_5", - "CFG_CENTER_IMUX2_6", - "CFG_CENTER_IMUX2_7", - "CFG_CENTER_IMUX2_8", - "CFG_CENTER_IMUX2_9", - "CFG_CENTER_IMUX30_0", - "CFG_CENTER_IMUX30_1", - "CFG_CENTER_IMUX30_10", - "CFG_CENTER_IMUX30_11", - "CFG_CENTER_IMUX30_12", - "CFG_CENTER_IMUX30_13", - "CFG_CENTER_IMUX30_14", - "CFG_CENTER_IMUX30_15", - "CFG_CENTER_IMUX30_16", - "CFG_CENTER_IMUX30_17", - "CFG_CENTER_IMUX30_18", - "CFG_CENTER_IMUX30_19", - "CFG_CENTER_IMUX30_2", - "CFG_CENTER_IMUX30_3", - "CFG_CENTER_IMUX30_4", - "CFG_CENTER_IMUX30_5", - "CFG_CENTER_IMUX30_6", - "CFG_CENTER_IMUX30_7", - "CFG_CENTER_IMUX30_8", - "CFG_CENTER_IMUX30_9", - "CFG_CENTER_IMUX31_0", - "CFG_CENTER_IMUX31_1", - "CFG_CENTER_IMUX31_10", - "CFG_CENTER_IMUX31_11", - "CFG_CENTER_IMUX31_12", - "CFG_CENTER_IMUX31_13", - "CFG_CENTER_IMUX31_14", - "CFG_CENTER_IMUX31_15", - "CFG_CENTER_IMUX31_16", - "CFG_CENTER_IMUX31_17", - "CFG_CENTER_IMUX31_18", - "CFG_CENTER_IMUX31_19", - "CFG_CENTER_IMUX31_2", - "CFG_CENTER_IMUX31_3", - "CFG_CENTER_IMUX31_4", - "CFG_CENTER_IMUX31_5", - "CFG_CENTER_IMUX31_6", - "CFG_CENTER_IMUX31_7", - "CFG_CENTER_IMUX31_8", - "CFG_CENTER_IMUX31_9", - "CFG_CENTER_IMUX32_0", - "CFG_CENTER_IMUX32_1", - "CFG_CENTER_IMUX32_10", - "CFG_CENTER_IMUX32_11", - "CFG_CENTER_IMUX32_12", - "CFG_CENTER_IMUX32_13", - "CFG_CENTER_IMUX32_14", - "CFG_CENTER_IMUX32_15", - "CFG_CENTER_IMUX32_16", - "CFG_CENTER_IMUX32_17", - "CFG_CENTER_IMUX32_18", - "CFG_CENTER_IMUX32_19", - "CFG_CENTER_IMUX32_2", - "CFG_CENTER_IMUX32_3", - "CFG_CENTER_IMUX32_4", - "CFG_CENTER_IMUX32_5", - "CFG_CENTER_IMUX32_6", - "CFG_CENTER_IMUX32_7", - "CFG_CENTER_IMUX32_8", - "CFG_CENTER_IMUX32_9", - "CFG_CENTER_IMUX33_0", - "CFG_CENTER_IMUX33_1", - "CFG_CENTER_IMUX33_10", - "CFG_CENTER_IMUX33_11", - "CFG_CENTER_IMUX33_12", - "CFG_CENTER_IMUX33_13", - "CFG_CENTER_IMUX33_14", - "CFG_CENTER_IMUX33_15", - "CFG_CENTER_IMUX33_16", - "CFG_CENTER_IMUX33_17", - "CFG_CENTER_IMUX33_18", - "CFG_CENTER_IMUX33_19", - "CFG_CENTER_IMUX33_2", - "CFG_CENTER_IMUX33_3", - "CFG_CENTER_IMUX33_4", - "CFG_CENTER_IMUX33_5", - "CFG_CENTER_IMUX33_6", - "CFG_CENTER_IMUX33_7", - "CFG_CENTER_IMUX33_8", - "CFG_CENTER_IMUX33_9", - "CFG_CENTER_IMUX34_0", - "CFG_CENTER_IMUX34_1", - "CFG_CENTER_IMUX34_10", - "CFG_CENTER_IMUX34_11", - "CFG_CENTER_IMUX34_12", - "CFG_CENTER_IMUX34_13", - "CFG_CENTER_IMUX34_14", - "CFG_CENTER_IMUX34_15", - "CFG_CENTER_IMUX34_16", - "CFG_CENTER_IMUX34_17", - "CFG_CENTER_IMUX34_18", - "CFG_CENTER_IMUX34_19", - "CFG_CENTER_IMUX34_2", - "CFG_CENTER_IMUX34_3", - "CFG_CENTER_IMUX34_4", - "CFG_CENTER_IMUX34_5", - "CFG_CENTER_IMUX34_6", - "CFG_CENTER_IMUX34_7", - "CFG_CENTER_IMUX34_8", - "CFG_CENTER_IMUX34_9", - "CFG_CENTER_IMUX35_0", - "CFG_CENTER_IMUX35_1", - "CFG_CENTER_IMUX35_10", - "CFG_CENTER_IMUX35_11", - "CFG_CENTER_IMUX35_12", - "CFG_CENTER_IMUX35_13", - "CFG_CENTER_IMUX35_14", - "CFG_CENTER_IMUX35_15", - "CFG_CENTER_IMUX35_16", - "CFG_CENTER_IMUX35_17", - "CFG_CENTER_IMUX35_18", - "CFG_CENTER_IMUX35_19", - "CFG_CENTER_IMUX35_2", - "CFG_CENTER_IMUX35_3", - "CFG_CENTER_IMUX35_4", - "CFG_CENTER_IMUX35_5", - "CFG_CENTER_IMUX35_6", - "CFG_CENTER_IMUX35_7", - "CFG_CENTER_IMUX35_8", - "CFG_CENTER_IMUX35_9", - "CFG_CENTER_IMUX36_0", - "CFG_CENTER_IMUX36_1", - "CFG_CENTER_IMUX36_10", - "CFG_CENTER_IMUX36_11", - "CFG_CENTER_IMUX36_12", - "CFG_CENTER_IMUX36_13", - "CFG_CENTER_IMUX36_14", - "CFG_CENTER_IMUX36_15", - "CFG_CENTER_IMUX36_16", - "CFG_CENTER_IMUX36_17", - "CFG_CENTER_IMUX36_18", - "CFG_CENTER_IMUX36_19", - "CFG_CENTER_IMUX36_2", - "CFG_CENTER_IMUX36_3", - "CFG_CENTER_IMUX36_4", - "CFG_CENTER_IMUX36_5", - "CFG_CENTER_IMUX36_6", - "CFG_CENTER_IMUX36_7", - "CFG_CENTER_IMUX36_8", - "CFG_CENTER_IMUX36_9", - "CFG_CENTER_IMUX37_0", - "CFG_CENTER_IMUX37_1", - "CFG_CENTER_IMUX37_10", - "CFG_CENTER_IMUX37_11", - "CFG_CENTER_IMUX37_12", - "CFG_CENTER_IMUX37_13", - "CFG_CENTER_IMUX37_14", - "CFG_CENTER_IMUX37_15", - "CFG_CENTER_IMUX37_16", - "CFG_CENTER_IMUX37_17", - "CFG_CENTER_IMUX37_18", - "CFG_CENTER_IMUX37_19", - "CFG_CENTER_IMUX37_2", - "CFG_CENTER_IMUX37_3", - "CFG_CENTER_IMUX37_4", - "CFG_CENTER_IMUX37_5", - "CFG_CENTER_IMUX37_6", - "CFG_CENTER_IMUX37_7", - "CFG_CENTER_IMUX37_8", - "CFG_CENTER_IMUX37_9", - "CFG_CENTER_IMUX38_0", - "CFG_CENTER_IMUX38_1", - "CFG_CENTER_IMUX38_10", - "CFG_CENTER_IMUX38_11", - "CFG_CENTER_IMUX38_12", - "CFG_CENTER_IMUX38_13", - "CFG_CENTER_IMUX38_14", - "CFG_CENTER_IMUX38_15", - "CFG_CENTER_IMUX38_16", - "CFG_CENTER_IMUX38_17", - "CFG_CENTER_IMUX38_18", - "CFG_CENTER_IMUX38_19", - "CFG_CENTER_IMUX38_2", - "CFG_CENTER_IMUX38_3", - "CFG_CENTER_IMUX38_4", - "CFG_CENTER_IMUX38_5", - "CFG_CENTER_IMUX38_6", - "CFG_CENTER_IMUX38_7", - "CFG_CENTER_IMUX38_8", - "CFG_CENTER_IMUX38_9", - "CFG_CENTER_IMUX39_0", - "CFG_CENTER_IMUX39_1", - "CFG_CENTER_IMUX39_10", - "CFG_CENTER_IMUX39_11", - "CFG_CENTER_IMUX39_12", - "CFG_CENTER_IMUX39_13", - "CFG_CENTER_IMUX39_14", - "CFG_CENTER_IMUX39_15", - "CFG_CENTER_IMUX39_16", - "CFG_CENTER_IMUX39_17", - "CFG_CENTER_IMUX39_18", - "CFG_CENTER_IMUX39_19", - "CFG_CENTER_IMUX39_2", - "CFG_CENTER_IMUX39_3", - "CFG_CENTER_IMUX39_4", - "CFG_CENTER_IMUX39_5", - "CFG_CENTER_IMUX39_6", - "CFG_CENTER_IMUX39_7", - "CFG_CENTER_IMUX39_8", - "CFG_CENTER_IMUX39_9", - "CFG_CENTER_IMUX3_0", - "CFG_CENTER_IMUX3_1", - "CFG_CENTER_IMUX3_10", - "CFG_CENTER_IMUX3_11", - "CFG_CENTER_IMUX3_12", - "CFG_CENTER_IMUX3_13", - "CFG_CENTER_IMUX3_14", - "CFG_CENTER_IMUX3_15", - "CFG_CENTER_IMUX3_16", - "CFG_CENTER_IMUX3_17", - "CFG_CENTER_IMUX3_18", - "CFG_CENTER_IMUX3_19", - "CFG_CENTER_IMUX3_2", - "CFG_CENTER_IMUX3_3", - "CFG_CENTER_IMUX3_4", - "CFG_CENTER_IMUX3_5", - "CFG_CENTER_IMUX3_6", - "CFG_CENTER_IMUX3_7", - "CFG_CENTER_IMUX3_8", - "CFG_CENTER_IMUX3_9", - "CFG_CENTER_IMUX40_0", - "CFG_CENTER_IMUX40_1", - "CFG_CENTER_IMUX40_10", - "CFG_CENTER_IMUX40_11", - "CFG_CENTER_IMUX40_12", - "CFG_CENTER_IMUX40_13", - "CFG_CENTER_IMUX40_14", - "CFG_CENTER_IMUX40_15", - "CFG_CENTER_IMUX40_16", - "CFG_CENTER_IMUX40_17", - "CFG_CENTER_IMUX40_18", - "CFG_CENTER_IMUX40_19", - "CFG_CENTER_IMUX40_2", - "CFG_CENTER_IMUX40_3", - "CFG_CENTER_IMUX40_4", - "CFG_CENTER_IMUX40_5", - "CFG_CENTER_IMUX40_6", - "CFG_CENTER_IMUX40_7", - "CFG_CENTER_IMUX40_8", - "CFG_CENTER_IMUX40_9", - "CFG_CENTER_IMUX41_0", - "CFG_CENTER_IMUX41_1", - "CFG_CENTER_IMUX41_10", - "CFG_CENTER_IMUX41_11", - "CFG_CENTER_IMUX41_12", - "CFG_CENTER_IMUX41_13", - "CFG_CENTER_IMUX41_14", - "CFG_CENTER_IMUX41_15", - "CFG_CENTER_IMUX41_16", - "CFG_CENTER_IMUX41_17", - "CFG_CENTER_IMUX41_18", - "CFG_CENTER_IMUX41_19", - "CFG_CENTER_IMUX41_2", - "CFG_CENTER_IMUX41_3", - "CFG_CENTER_IMUX41_4", - "CFG_CENTER_IMUX41_5", - "CFG_CENTER_IMUX41_6", - "CFG_CENTER_IMUX41_7", - "CFG_CENTER_IMUX41_8", - "CFG_CENTER_IMUX41_9", - "CFG_CENTER_IMUX42_0", - "CFG_CENTER_IMUX42_1", - "CFG_CENTER_IMUX42_10", - "CFG_CENTER_IMUX42_11", - "CFG_CENTER_IMUX42_12", - "CFG_CENTER_IMUX42_13", - "CFG_CENTER_IMUX42_14", - "CFG_CENTER_IMUX42_15", - "CFG_CENTER_IMUX42_16", - "CFG_CENTER_IMUX42_17", - "CFG_CENTER_IMUX42_18", - "CFG_CENTER_IMUX42_19", - "CFG_CENTER_IMUX42_2", - "CFG_CENTER_IMUX42_3", - "CFG_CENTER_IMUX42_4", - "CFG_CENTER_IMUX42_5", - "CFG_CENTER_IMUX42_6", - "CFG_CENTER_IMUX42_7", - "CFG_CENTER_IMUX42_8", - "CFG_CENTER_IMUX42_9", - "CFG_CENTER_IMUX43_0", - "CFG_CENTER_IMUX43_1", - "CFG_CENTER_IMUX43_10", - "CFG_CENTER_IMUX43_11", - "CFG_CENTER_IMUX43_12", - "CFG_CENTER_IMUX43_13", - "CFG_CENTER_IMUX43_14", - "CFG_CENTER_IMUX43_15", - "CFG_CENTER_IMUX43_16", - "CFG_CENTER_IMUX43_17", - "CFG_CENTER_IMUX43_18", - "CFG_CENTER_IMUX43_19", - "CFG_CENTER_IMUX43_2", - "CFG_CENTER_IMUX43_3", - "CFG_CENTER_IMUX43_4", - "CFG_CENTER_IMUX43_5", - "CFG_CENTER_IMUX43_6", - "CFG_CENTER_IMUX43_7", - "CFG_CENTER_IMUX43_8", - "CFG_CENTER_IMUX43_9", - "CFG_CENTER_IMUX44_0", - "CFG_CENTER_IMUX44_1", - "CFG_CENTER_IMUX44_10", - "CFG_CENTER_IMUX44_11", - "CFG_CENTER_IMUX44_12", - "CFG_CENTER_IMUX44_13", - "CFG_CENTER_IMUX44_14", - "CFG_CENTER_IMUX44_15", - "CFG_CENTER_IMUX44_16", - "CFG_CENTER_IMUX44_17", - "CFG_CENTER_IMUX44_18", - "CFG_CENTER_IMUX44_19", - "CFG_CENTER_IMUX44_2", - "CFG_CENTER_IMUX44_3", - "CFG_CENTER_IMUX44_4", - "CFG_CENTER_IMUX44_5", - "CFG_CENTER_IMUX44_6", - "CFG_CENTER_IMUX44_7", - "CFG_CENTER_IMUX44_8", - "CFG_CENTER_IMUX44_9", - "CFG_CENTER_IMUX45_0", - "CFG_CENTER_IMUX45_1", - "CFG_CENTER_IMUX45_10", - "CFG_CENTER_IMUX45_11", - "CFG_CENTER_IMUX45_12", - "CFG_CENTER_IMUX45_13", - "CFG_CENTER_IMUX45_14", - "CFG_CENTER_IMUX45_15", - "CFG_CENTER_IMUX45_16", - "CFG_CENTER_IMUX45_17", - "CFG_CENTER_IMUX45_18", - "CFG_CENTER_IMUX45_19", - "CFG_CENTER_IMUX45_2", - "CFG_CENTER_IMUX45_3", - "CFG_CENTER_IMUX45_4", - "CFG_CENTER_IMUX45_5", - "CFG_CENTER_IMUX45_6", - "CFG_CENTER_IMUX45_7", - "CFG_CENTER_IMUX45_8", - "CFG_CENTER_IMUX45_9", - "CFG_CENTER_IMUX46_0", - "CFG_CENTER_IMUX46_1", - "CFG_CENTER_IMUX46_10", - "CFG_CENTER_IMUX46_11", - "CFG_CENTER_IMUX46_12", - "CFG_CENTER_IMUX46_13", - "CFG_CENTER_IMUX46_14", - "CFG_CENTER_IMUX46_15", - "CFG_CENTER_IMUX46_16", - "CFG_CENTER_IMUX46_17", - "CFG_CENTER_IMUX46_18", - "CFG_CENTER_IMUX46_19", - "CFG_CENTER_IMUX46_2", - "CFG_CENTER_IMUX46_3", - "CFG_CENTER_IMUX46_4", - "CFG_CENTER_IMUX46_5", - "CFG_CENTER_IMUX46_6", - "CFG_CENTER_IMUX46_7", - "CFG_CENTER_IMUX46_8", - "CFG_CENTER_IMUX46_9", - "CFG_CENTER_IMUX47_0", - "CFG_CENTER_IMUX47_1", - "CFG_CENTER_IMUX47_10", - "CFG_CENTER_IMUX47_11", - "CFG_CENTER_IMUX47_12", - "CFG_CENTER_IMUX47_13", - "CFG_CENTER_IMUX47_14", - "CFG_CENTER_IMUX47_15", - "CFG_CENTER_IMUX47_16", - "CFG_CENTER_IMUX47_17", - "CFG_CENTER_IMUX47_18", - "CFG_CENTER_IMUX47_19", - "CFG_CENTER_IMUX47_2", - "CFG_CENTER_IMUX47_3", - "CFG_CENTER_IMUX47_4", - "CFG_CENTER_IMUX47_5", - "CFG_CENTER_IMUX47_6", - "CFG_CENTER_IMUX47_7", - "CFG_CENTER_IMUX47_8", - "CFG_CENTER_IMUX47_9", - "CFG_CENTER_IMUX4_0", - "CFG_CENTER_IMUX4_1", - "CFG_CENTER_IMUX4_10", - "CFG_CENTER_IMUX4_11", - "CFG_CENTER_IMUX4_12", - "CFG_CENTER_IMUX4_13", - "CFG_CENTER_IMUX4_14", - "CFG_CENTER_IMUX4_15", - "CFG_CENTER_IMUX4_16", - "CFG_CENTER_IMUX4_17", - "CFG_CENTER_IMUX4_18", - "CFG_CENTER_IMUX4_19", - "CFG_CENTER_IMUX4_2", - "CFG_CENTER_IMUX4_3", - "CFG_CENTER_IMUX4_4", - "CFG_CENTER_IMUX4_5", - "CFG_CENTER_IMUX4_6", - "CFG_CENTER_IMUX4_7", - "CFG_CENTER_IMUX4_8", - "CFG_CENTER_IMUX4_9", - "CFG_CENTER_IMUX5_0", - "CFG_CENTER_IMUX5_1", - "CFG_CENTER_IMUX5_10", - "CFG_CENTER_IMUX5_11", - "CFG_CENTER_IMUX5_12", - "CFG_CENTER_IMUX5_13", - "CFG_CENTER_IMUX5_14", - "CFG_CENTER_IMUX5_15", - "CFG_CENTER_IMUX5_16", - "CFG_CENTER_IMUX5_17", - "CFG_CENTER_IMUX5_18", - "CFG_CENTER_IMUX5_19", - "CFG_CENTER_IMUX5_2", - "CFG_CENTER_IMUX5_3", - "CFG_CENTER_IMUX5_4", - "CFG_CENTER_IMUX5_5", - "CFG_CENTER_IMUX5_6", - "CFG_CENTER_IMUX5_7", - "CFG_CENTER_IMUX5_8", - "CFG_CENTER_IMUX5_9", - "CFG_CENTER_IMUX6_0", - "CFG_CENTER_IMUX6_1", - "CFG_CENTER_IMUX6_10", - "CFG_CENTER_IMUX6_11", - "CFG_CENTER_IMUX6_12", - "CFG_CENTER_IMUX6_13", - "CFG_CENTER_IMUX6_14", - "CFG_CENTER_IMUX6_15", - "CFG_CENTER_IMUX6_16", - "CFG_CENTER_IMUX6_17", - "CFG_CENTER_IMUX6_18", - "CFG_CENTER_IMUX6_19", - "CFG_CENTER_IMUX6_2", - "CFG_CENTER_IMUX6_3", - "CFG_CENTER_IMUX6_4", - "CFG_CENTER_IMUX6_5", - "CFG_CENTER_IMUX6_6", - "CFG_CENTER_IMUX6_7", - "CFG_CENTER_IMUX6_8", - "CFG_CENTER_IMUX6_9", - "CFG_CENTER_IMUX7_0", - "CFG_CENTER_IMUX7_1", - "CFG_CENTER_IMUX7_10", - "CFG_CENTER_IMUX7_11", - "CFG_CENTER_IMUX7_12", - "CFG_CENTER_IMUX7_13", - "CFG_CENTER_IMUX7_14", - "CFG_CENTER_IMUX7_15", - "CFG_CENTER_IMUX7_16", - "CFG_CENTER_IMUX7_17", - "CFG_CENTER_IMUX7_18", - "CFG_CENTER_IMUX7_19", - "CFG_CENTER_IMUX7_2", - "CFG_CENTER_IMUX7_3", - "CFG_CENTER_IMUX7_4", - "CFG_CENTER_IMUX7_5", - "CFG_CENTER_IMUX7_6", - "CFG_CENTER_IMUX7_7", - "CFG_CENTER_IMUX7_8", - "CFG_CENTER_IMUX7_9", - "CFG_CENTER_IMUX8_0", - "CFG_CENTER_IMUX8_1", - "CFG_CENTER_IMUX8_10", - "CFG_CENTER_IMUX8_11", - "CFG_CENTER_IMUX8_12", - "CFG_CENTER_IMUX8_13", - "CFG_CENTER_IMUX8_14", - "CFG_CENTER_IMUX8_15", - "CFG_CENTER_IMUX8_16", - "CFG_CENTER_IMUX8_17", - "CFG_CENTER_IMUX8_18", - "CFG_CENTER_IMUX8_19", - "CFG_CENTER_IMUX8_2", - "CFG_CENTER_IMUX8_3", - "CFG_CENTER_IMUX8_4", - "CFG_CENTER_IMUX8_5", - "CFG_CENTER_IMUX8_6", - "CFG_CENTER_IMUX8_7", - "CFG_CENTER_IMUX8_8", - "CFG_CENTER_IMUX8_9", - "CFG_CENTER_IMUX9_0", - "CFG_CENTER_IMUX9_1", - "CFG_CENTER_IMUX9_10", - "CFG_CENTER_IMUX9_11", - "CFG_CENTER_IMUX9_12", - "CFG_CENTER_IMUX9_13", - "CFG_CENTER_IMUX9_14", - "CFG_CENTER_IMUX9_15", - "CFG_CENTER_IMUX9_16", - "CFG_CENTER_IMUX9_17", - "CFG_CENTER_IMUX9_18", - "CFG_CENTER_IMUX9_19", - "CFG_CENTER_IMUX9_2", - "CFG_CENTER_IMUX9_3", - "CFG_CENTER_IMUX9_4", - "CFG_CENTER_IMUX9_5", - "CFG_CENTER_IMUX9_6", - "CFG_CENTER_IMUX9_7", - "CFG_CENTER_IMUX9_8", - "CFG_CENTER_IMUX9_9", - "CFG_CENTER_LH10_0", - "CFG_CENTER_LH10_1", - "CFG_CENTER_LH10_10", - "CFG_CENTER_LH10_11", - "CFG_CENTER_LH10_12", - "CFG_CENTER_LH10_13", - "CFG_CENTER_LH10_14", - "CFG_CENTER_LH10_15", - "CFG_CENTER_LH10_16", - "CFG_CENTER_LH10_17", - "CFG_CENTER_LH10_18", - "CFG_CENTER_LH10_19", - "CFG_CENTER_LH10_2", - "CFG_CENTER_LH10_3", - "CFG_CENTER_LH10_4", - "CFG_CENTER_LH10_5", - "CFG_CENTER_LH10_6", - "CFG_CENTER_LH10_7", - "CFG_CENTER_LH10_8", - "CFG_CENTER_LH10_9", - "CFG_CENTER_LH11_0", - "CFG_CENTER_LH11_1", - "CFG_CENTER_LH11_10", - "CFG_CENTER_LH11_11", - "CFG_CENTER_LH11_12", - "CFG_CENTER_LH11_13", - "CFG_CENTER_LH11_14", - "CFG_CENTER_LH11_15", - "CFG_CENTER_LH11_16", - "CFG_CENTER_LH11_17", - "CFG_CENTER_LH11_18", - "CFG_CENTER_LH11_19", - "CFG_CENTER_LH11_2", - "CFG_CENTER_LH11_3", - "CFG_CENTER_LH11_4", - "CFG_CENTER_LH11_5", - "CFG_CENTER_LH11_6", - "CFG_CENTER_LH11_7", - "CFG_CENTER_LH11_8", - "CFG_CENTER_LH11_9", - "CFG_CENTER_LH12_0", - "CFG_CENTER_LH12_1", - "CFG_CENTER_LH12_10", - "CFG_CENTER_LH12_11", - "CFG_CENTER_LH12_12", - "CFG_CENTER_LH12_13", - "CFG_CENTER_LH12_14", - "CFG_CENTER_LH12_15", - "CFG_CENTER_LH12_16", - "CFG_CENTER_LH12_17", - "CFG_CENTER_LH12_18", - "CFG_CENTER_LH12_19", - "CFG_CENTER_LH12_2", - "CFG_CENTER_LH12_3", - "CFG_CENTER_LH12_4", - "CFG_CENTER_LH12_5", - "CFG_CENTER_LH12_6", - "CFG_CENTER_LH12_7", - "CFG_CENTER_LH12_8", - "CFG_CENTER_LH12_9", - "CFG_CENTER_LH1_0", - "CFG_CENTER_LH1_1", - "CFG_CENTER_LH1_10", - "CFG_CENTER_LH1_11", - "CFG_CENTER_LH1_12", - "CFG_CENTER_LH1_13", - "CFG_CENTER_LH1_14", - "CFG_CENTER_LH1_15", - "CFG_CENTER_LH1_16", - "CFG_CENTER_LH1_17", - "CFG_CENTER_LH1_18", - "CFG_CENTER_LH1_19", - "CFG_CENTER_LH1_2", - "CFG_CENTER_LH1_3", - "CFG_CENTER_LH1_4", - "CFG_CENTER_LH1_5", - "CFG_CENTER_LH1_6", - "CFG_CENTER_LH1_7", - "CFG_CENTER_LH1_8", - "CFG_CENTER_LH1_9", - "CFG_CENTER_LH2_0", - "CFG_CENTER_LH2_1", - "CFG_CENTER_LH2_10", - "CFG_CENTER_LH2_11", - "CFG_CENTER_LH2_12", - "CFG_CENTER_LH2_13", - "CFG_CENTER_LH2_14", - "CFG_CENTER_LH2_15", - "CFG_CENTER_LH2_16", - "CFG_CENTER_LH2_17", - "CFG_CENTER_LH2_18", - "CFG_CENTER_LH2_19", - "CFG_CENTER_LH2_2", - "CFG_CENTER_LH2_3", - "CFG_CENTER_LH2_4", - "CFG_CENTER_LH2_5", - "CFG_CENTER_LH2_6", - "CFG_CENTER_LH2_7", - "CFG_CENTER_LH2_8", - "CFG_CENTER_LH2_9", - "CFG_CENTER_LH3_0", - "CFG_CENTER_LH3_1", - "CFG_CENTER_LH3_10", - "CFG_CENTER_LH3_11", - "CFG_CENTER_LH3_12", - "CFG_CENTER_LH3_13", - "CFG_CENTER_LH3_14", - "CFG_CENTER_LH3_15", - "CFG_CENTER_LH3_16", - "CFG_CENTER_LH3_17", - "CFG_CENTER_LH3_18", - "CFG_CENTER_LH3_19", - "CFG_CENTER_LH3_2", - "CFG_CENTER_LH3_3", - "CFG_CENTER_LH3_4", - "CFG_CENTER_LH3_5", - "CFG_CENTER_LH3_6", - "CFG_CENTER_LH3_7", - "CFG_CENTER_LH3_8", - "CFG_CENTER_LH3_9", - "CFG_CENTER_LH4_0", - "CFG_CENTER_LH4_1", - "CFG_CENTER_LH4_10", - "CFG_CENTER_LH4_11", - "CFG_CENTER_LH4_12", - "CFG_CENTER_LH4_13", - "CFG_CENTER_LH4_14", - "CFG_CENTER_LH4_15", - "CFG_CENTER_LH4_16", - "CFG_CENTER_LH4_17", - "CFG_CENTER_LH4_18", - "CFG_CENTER_LH4_19", - "CFG_CENTER_LH4_2", - "CFG_CENTER_LH4_3", - "CFG_CENTER_LH4_4", - "CFG_CENTER_LH4_5", - "CFG_CENTER_LH4_6", - "CFG_CENTER_LH4_7", - "CFG_CENTER_LH4_8", - "CFG_CENTER_LH4_9", - "CFG_CENTER_LH5_0", - "CFG_CENTER_LH5_1", - "CFG_CENTER_LH5_10", - "CFG_CENTER_LH5_11", - "CFG_CENTER_LH5_12", - "CFG_CENTER_LH5_13", - "CFG_CENTER_LH5_14", - "CFG_CENTER_LH5_15", - "CFG_CENTER_LH5_16", - "CFG_CENTER_LH5_17", - "CFG_CENTER_LH5_18", - "CFG_CENTER_LH5_19", - "CFG_CENTER_LH5_2", - "CFG_CENTER_LH5_3", - "CFG_CENTER_LH5_4", - "CFG_CENTER_LH5_5", - "CFG_CENTER_LH5_6", - "CFG_CENTER_LH5_7", - "CFG_CENTER_LH5_8", - "CFG_CENTER_LH5_9", - "CFG_CENTER_LH6_0", - "CFG_CENTER_LH6_1", - "CFG_CENTER_LH6_10", - "CFG_CENTER_LH6_11", - "CFG_CENTER_LH6_12", - "CFG_CENTER_LH6_13", - "CFG_CENTER_LH6_14", - "CFG_CENTER_LH6_15", - "CFG_CENTER_LH6_16", - "CFG_CENTER_LH6_17", - "CFG_CENTER_LH6_18", - "CFG_CENTER_LH6_19", - "CFG_CENTER_LH6_2", - "CFG_CENTER_LH6_3", - "CFG_CENTER_LH6_4", - "CFG_CENTER_LH6_5", - "CFG_CENTER_LH6_6", - "CFG_CENTER_LH6_7", - "CFG_CENTER_LH6_8", - "CFG_CENTER_LH6_9", - "CFG_CENTER_LH7_0", - "CFG_CENTER_LH7_1", - "CFG_CENTER_LH7_10", - "CFG_CENTER_LH7_11", - "CFG_CENTER_LH7_12", - "CFG_CENTER_LH7_13", - "CFG_CENTER_LH7_14", - "CFG_CENTER_LH7_15", - "CFG_CENTER_LH7_16", - "CFG_CENTER_LH7_17", - "CFG_CENTER_LH7_18", - "CFG_CENTER_LH7_19", - "CFG_CENTER_LH7_2", - "CFG_CENTER_LH7_3", - "CFG_CENTER_LH7_4", - "CFG_CENTER_LH7_5", - "CFG_CENTER_LH7_6", - "CFG_CENTER_LH7_7", - "CFG_CENTER_LH7_8", - "CFG_CENTER_LH7_9", - "CFG_CENTER_LH8_0", - "CFG_CENTER_LH8_1", - "CFG_CENTER_LH8_10", - "CFG_CENTER_LH8_11", - "CFG_CENTER_LH8_12", - "CFG_CENTER_LH8_13", - "CFG_CENTER_LH8_14", - "CFG_CENTER_LH8_15", - "CFG_CENTER_LH8_16", - "CFG_CENTER_LH8_17", - "CFG_CENTER_LH8_18", - "CFG_CENTER_LH8_19", - "CFG_CENTER_LH8_2", - "CFG_CENTER_LH8_3", - "CFG_CENTER_LH8_4", - "CFG_CENTER_LH8_5", - "CFG_CENTER_LH8_6", - "CFG_CENTER_LH8_7", - "CFG_CENTER_LH8_8", - "CFG_CENTER_LH8_9", - "CFG_CENTER_LH9_0", - "CFG_CENTER_LH9_1", - "CFG_CENTER_LH9_10", - "CFG_CENTER_LH9_11", - "CFG_CENTER_LH9_12", - "CFG_CENTER_LH9_13", - "CFG_CENTER_LH9_14", - "CFG_CENTER_LH9_15", - "CFG_CENTER_LH9_16", - "CFG_CENTER_LH9_17", - "CFG_CENTER_LH9_18", - "CFG_CENTER_LH9_19", - "CFG_CENTER_LH9_2", - "CFG_CENTER_LH9_3", - "CFG_CENTER_LH9_4", - "CFG_CENTER_LH9_5", - "CFG_CENTER_LH9_6", - "CFG_CENTER_LH9_7", - "CFG_CENTER_LH9_8", - "CFG_CENTER_LH9_9", - "CFG_CENTER_LOGIC_OUTS_B0_0", - "CFG_CENTER_LOGIC_OUTS_B0_1", - "CFG_CENTER_LOGIC_OUTS_B0_10", - "CFG_CENTER_LOGIC_OUTS_B0_11", - "CFG_CENTER_LOGIC_OUTS_B0_12", - "CFG_CENTER_LOGIC_OUTS_B0_13", - "CFG_CENTER_LOGIC_OUTS_B0_14", - "CFG_CENTER_LOGIC_OUTS_B0_15", - "CFG_CENTER_LOGIC_OUTS_B0_16", - "CFG_CENTER_LOGIC_OUTS_B0_17", - "CFG_CENTER_LOGIC_OUTS_B0_18", - "CFG_CENTER_LOGIC_OUTS_B0_19", - "CFG_CENTER_LOGIC_OUTS_B0_2", - "CFG_CENTER_LOGIC_OUTS_B0_3", - "CFG_CENTER_LOGIC_OUTS_B0_4", - "CFG_CENTER_LOGIC_OUTS_B0_5", - "CFG_CENTER_LOGIC_OUTS_B0_6", - "CFG_CENTER_LOGIC_OUTS_B0_7", - "CFG_CENTER_LOGIC_OUTS_B0_8", - "CFG_CENTER_LOGIC_OUTS_B0_9", - "CFG_CENTER_LOGIC_OUTS_B10_0", - "CFG_CENTER_LOGIC_OUTS_B10_1", - "CFG_CENTER_LOGIC_OUTS_B10_10", - "CFG_CENTER_LOGIC_OUTS_B10_11", - "CFG_CENTER_LOGIC_OUTS_B10_12", - "CFG_CENTER_LOGIC_OUTS_B10_13", - "CFG_CENTER_LOGIC_OUTS_B10_14", - "CFG_CENTER_LOGIC_OUTS_B10_15", - "CFG_CENTER_LOGIC_OUTS_B10_16", - "CFG_CENTER_LOGIC_OUTS_B10_17", - "CFG_CENTER_LOGIC_OUTS_B10_18", - "CFG_CENTER_LOGIC_OUTS_B10_19", - "CFG_CENTER_LOGIC_OUTS_B10_2", - "CFG_CENTER_LOGIC_OUTS_B10_3", - "CFG_CENTER_LOGIC_OUTS_B10_4", - "CFG_CENTER_LOGIC_OUTS_B10_5", - "CFG_CENTER_LOGIC_OUTS_B10_6", - "CFG_CENTER_LOGIC_OUTS_B10_7", - "CFG_CENTER_LOGIC_OUTS_B10_8", - "CFG_CENTER_LOGIC_OUTS_B10_9", - "CFG_CENTER_LOGIC_OUTS_B11_0", - "CFG_CENTER_LOGIC_OUTS_B11_1", - "CFG_CENTER_LOGIC_OUTS_B11_10", - "CFG_CENTER_LOGIC_OUTS_B11_11", - "CFG_CENTER_LOGIC_OUTS_B11_12", - "CFG_CENTER_LOGIC_OUTS_B11_13", - "CFG_CENTER_LOGIC_OUTS_B11_14", - "CFG_CENTER_LOGIC_OUTS_B11_15", - "CFG_CENTER_LOGIC_OUTS_B11_16", - "CFG_CENTER_LOGIC_OUTS_B11_17", - "CFG_CENTER_LOGIC_OUTS_B11_18", - "CFG_CENTER_LOGIC_OUTS_B11_19", - "CFG_CENTER_LOGIC_OUTS_B11_2", - "CFG_CENTER_LOGIC_OUTS_B11_3", - "CFG_CENTER_LOGIC_OUTS_B11_4", - "CFG_CENTER_LOGIC_OUTS_B11_5", - "CFG_CENTER_LOGIC_OUTS_B11_6", - "CFG_CENTER_LOGIC_OUTS_B11_7", - "CFG_CENTER_LOGIC_OUTS_B11_8", - "CFG_CENTER_LOGIC_OUTS_B11_9", - "CFG_CENTER_LOGIC_OUTS_B12_0", - "CFG_CENTER_LOGIC_OUTS_B12_1", - "CFG_CENTER_LOGIC_OUTS_B12_10", - "CFG_CENTER_LOGIC_OUTS_B12_11", - "CFG_CENTER_LOGIC_OUTS_B12_12", - "CFG_CENTER_LOGIC_OUTS_B12_13", - "CFG_CENTER_LOGIC_OUTS_B12_14", - "CFG_CENTER_LOGIC_OUTS_B12_15", - "CFG_CENTER_LOGIC_OUTS_B12_16", - "CFG_CENTER_LOGIC_OUTS_B12_17", - "CFG_CENTER_LOGIC_OUTS_B12_18", - "CFG_CENTER_LOGIC_OUTS_B12_19", - "CFG_CENTER_LOGIC_OUTS_B12_2", - "CFG_CENTER_LOGIC_OUTS_B12_3", - "CFG_CENTER_LOGIC_OUTS_B12_4", - "CFG_CENTER_LOGIC_OUTS_B12_5", - "CFG_CENTER_LOGIC_OUTS_B12_6", - "CFG_CENTER_LOGIC_OUTS_B12_7", - "CFG_CENTER_LOGIC_OUTS_B12_8", - "CFG_CENTER_LOGIC_OUTS_B12_9", - "CFG_CENTER_LOGIC_OUTS_B13_0", - "CFG_CENTER_LOGIC_OUTS_B13_1", - "CFG_CENTER_LOGIC_OUTS_B13_10", - "CFG_CENTER_LOGIC_OUTS_B13_11", - "CFG_CENTER_LOGIC_OUTS_B13_12", - "CFG_CENTER_LOGIC_OUTS_B13_13", - "CFG_CENTER_LOGIC_OUTS_B13_14", - "CFG_CENTER_LOGIC_OUTS_B13_15", - "CFG_CENTER_LOGIC_OUTS_B13_16", - "CFG_CENTER_LOGIC_OUTS_B13_17", - "CFG_CENTER_LOGIC_OUTS_B13_18", - "CFG_CENTER_LOGIC_OUTS_B13_19", - "CFG_CENTER_LOGIC_OUTS_B13_2", - "CFG_CENTER_LOGIC_OUTS_B13_3", - "CFG_CENTER_LOGIC_OUTS_B13_4", - "CFG_CENTER_LOGIC_OUTS_B13_5", - "CFG_CENTER_LOGIC_OUTS_B13_6", - "CFG_CENTER_LOGIC_OUTS_B13_7", - "CFG_CENTER_LOGIC_OUTS_B13_8", - "CFG_CENTER_LOGIC_OUTS_B13_9", - "CFG_CENTER_LOGIC_OUTS_B14_0", - "CFG_CENTER_LOGIC_OUTS_B14_1", - "CFG_CENTER_LOGIC_OUTS_B14_10", - "CFG_CENTER_LOGIC_OUTS_B14_11", - "CFG_CENTER_LOGIC_OUTS_B14_12", - "CFG_CENTER_LOGIC_OUTS_B14_13", - "CFG_CENTER_LOGIC_OUTS_B14_14", - "CFG_CENTER_LOGIC_OUTS_B14_15", - "CFG_CENTER_LOGIC_OUTS_B14_16", - "CFG_CENTER_LOGIC_OUTS_B14_17", - "CFG_CENTER_LOGIC_OUTS_B14_18", - "CFG_CENTER_LOGIC_OUTS_B14_19", - "CFG_CENTER_LOGIC_OUTS_B14_2", - "CFG_CENTER_LOGIC_OUTS_B14_3", - "CFG_CENTER_LOGIC_OUTS_B14_4", - "CFG_CENTER_LOGIC_OUTS_B14_5", - "CFG_CENTER_LOGIC_OUTS_B14_6", - "CFG_CENTER_LOGIC_OUTS_B14_7", - "CFG_CENTER_LOGIC_OUTS_B14_8", - "CFG_CENTER_LOGIC_OUTS_B14_9", - "CFG_CENTER_LOGIC_OUTS_B15_0", - "CFG_CENTER_LOGIC_OUTS_B15_1", - "CFG_CENTER_LOGIC_OUTS_B15_10", - "CFG_CENTER_LOGIC_OUTS_B15_11", - "CFG_CENTER_LOGIC_OUTS_B15_12", - "CFG_CENTER_LOGIC_OUTS_B15_13", - "CFG_CENTER_LOGIC_OUTS_B15_14", - "CFG_CENTER_LOGIC_OUTS_B15_15", - "CFG_CENTER_LOGIC_OUTS_B15_16", - "CFG_CENTER_LOGIC_OUTS_B15_17", - "CFG_CENTER_LOGIC_OUTS_B15_18", - "CFG_CENTER_LOGIC_OUTS_B15_19", - "CFG_CENTER_LOGIC_OUTS_B15_2", - "CFG_CENTER_LOGIC_OUTS_B15_3", - "CFG_CENTER_LOGIC_OUTS_B15_4", - "CFG_CENTER_LOGIC_OUTS_B15_5", - "CFG_CENTER_LOGIC_OUTS_B15_6", - "CFG_CENTER_LOGIC_OUTS_B15_7", - "CFG_CENTER_LOGIC_OUTS_B15_8", - "CFG_CENTER_LOGIC_OUTS_B15_9", - "CFG_CENTER_LOGIC_OUTS_B16_0", - "CFG_CENTER_LOGIC_OUTS_B16_1", - "CFG_CENTER_LOGIC_OUTS_B16_10", - "CFG_CENTER_LOGIC_OUTS_B16_11", - "CFG_CENTER_LOGIC_OUTS_B16_12", - "CFG_CENTER_LOGIC_OUTS_B16_13", - "CFG_CENTER_LOGIC_OUTS_B16_14", - "CFG_CENTER_LOGIC_OUTS_B16_15", - "CFG_CENTER_LOGIC_OUTS_B16_16", - "CFG_CENTER_LOGIC_OUTS_B16_17", - "CFG_CENTER_LOGIC_OUTS_B16_18", - "CFG_CENTER_LOGIC_OUTS_B16_19", - "CFG_CENTER_LOGIC_OUTS_B16_2", - "CFG_CENTER_LOGIC_OUTS_B16_3", - "CFG_CENTER_LOGIC_OUTS_B16_4", - "CFG_CENTER_LOGIC_OUTS_B16_5", - "CFG_CENTER_LOGIC_OUTS_B16_6", - "CFG_CENTER_LOGIC_OUTS_B16_7", - "CFG_CENTER_LOGIC_OUTS_B16_8", - "CFG_CENTER_LOGIC_OUTS_B16_9", - "CFG_CENTER_LOGIC_OUTS_B17_0", - "CFG_CENTER_LOGIC_OUTS_B17_1", - "CFG_CENTER_LOGIC_OUTS_B17_10", - "CFG_CENTER_LOGIC_OUTS_B17_11", - "CFG_CENTER_LOGIC_OUTS_B17_12", - "CFG_CENTER_LOGIC_OUTS_B17_13", - "CFG_CENTER_LOGIC_OUTS_B17_14", - "CFG_CENTER_LOGIC_OUTS_B17_15", - "CFG_CENTER_LOGIC_OUTS_B17_16", - "CFG_CENTER_LOGIC_OUTS_B17_17", - "CFG_CENTER_LOGIC_OUTS_B17_18", - "CFG_CENTER_LOGIC_OUTS_B17_19", - "CFG_CENTER_LOGIC_OUTS_B17_2", - "CFG_CENTER_LOGIC_OUTS_B17_3", - "CFG_CENTER_LOGIC_OUTS_B17_4", - "CFG_CENTER_LOGIC_OUTS_B17_5", - "CFG_CENTER_LOGIC_OUTS_B17_6", - "CFG_CENTER_LOGIC_OUTS_B17_7", - "CFG_CENTER_LOGIC_OUTS_B17_8", - "CFG_CENTER_LOGIC_OUTS_B17_9", - "CFG_CENTER_LOGIC_OUTS_B18_0", - "CFG_CENTER_LOGIC_OUTS_B18_1", - "CFG_CENTER_LOGIC_OUTS_B18_10", - "CFG_CENTER_LOGIC_OUTS_B18_11", - "CFG_CENTER_LOGIC_OUTS_B18_12", - "CFG_CENTER_LOGIC_OUTS_B18_13", - "CFG_CENTER_LOGIC_OUTS_B18_14", - "CFG_CENTER_LOGIC_OUTS_B18_15", - "CFG_CENTER_LOGIC_OUTS_B18_16", - "CFG_CENTER_LOGIC_OUTS_B18_17", - "CFG_CENTER_LOGIC_OUTS_B18_18", - "CFG_CENTER_LOGIC_OUTS_B18_19", - "CFG_CENTER_LOGIC_OUTS_B18_2", - "CFG_CENTER_LOGIC_OUTS_B18_3", - "CFG_CENTER_LOGIC_OUTS_B18_4", - "CFG_CENTER_LOGIC_OUTS_B18_5", - "CFG_CENTER_LOGIC_OUTS_B18_6", - "CFG_CENTER_LOGIC_OUTS_B18_7", - "CFG_CENTER_LOGIC_OUTS_B18_8", - "CFG_CENTER_LOGIC_OUTS_B18_9", - "CFG_CENTER_LOGIC_OUTS_B19_0", - "CFG_CENTER_LOGIC_OUTS_B19_1", - "CFG_CENTER_LOGIC_OUTS_B19_10", - "CFG_CENTER_LOGIC_OUTS_B19_11", - "CFG_CENTER_LOGIC_OUTS_B19_12", - "CFG_CENTER_LOGIC_OUTS_B19_13", - "CFG_CENTER_LOGIC_OUTS_B19_14", - "CFG_CENTER_LOGIC_OUTS_B19_15", - "CFG_CENTER_LOGIC_OUTS_B19_16", - "CFG_CENTER_LOGIC_OUTS_B19_17", - "CFG_CENTER_LOGIC_OUTS_B19_18", - "CFG_CENTER_LOGIC_OUTS_B19_19", - "CFG_CENTER_LOGIC_OUTS_B19_2", - "CFG_CENTER_LOGIC_OUTS_B19_3", - "CFG_CENTER_LOGIC_OUTS_B19_4", - "CFG_CENTER_LOGIC_OUTS_B19_5", - "CFG_CENTER_LOGIC_OUTS_B19_6", - "CFG_CENTER_LOGIC_OUTS_B19_7", - "CFG_CENTER_LOGIC_OUTS_B19_8", - "CFG_CENTER_LOGIC_OUTS_B19_9", - "CFG_CENTER_LOGIC_OUTS_B1_0", - "CFG_CENTER_LOGIC_OUTS_B1_1", - "CFG_CENTER_LOGIC_OUTS_B1_10", - "CFG_CENTER_LOGIC_OUTS_B1_11", - "CFG_CENTER_LOGIC_OUTS_B1_12", - "CFG_CENTER_LOGIC_OUTS_B1_13", - "CFG_CENTER_LOGIC_OUTS_B1_14", - "CFG_CENTER_LOGIC_OUTS_B1_15", - "CFG_CENTER_LOGIC_OUTS_B1_16", - "CFG_CENTER_LOGIC_OUTS_B1_17", - "CFG_CENTER_LOGIC_OUTS_B1_18", - "CFG_CENTER_LOGIC_OUTS_B1_19", - "CFG_CENTER_LOGIC_OUTS_B1_2", - "CFG_CENTER_LOGIC_OUTS_B1_3", - "CFG_CENTER_LOGIC_OUTS_B1_4", - "CFG_CENTER_LOGIC_OUTS_B1_5", - "CFG_CENTER_LOGIC_OUTS_B1_6", - "CFG_CENTER_LOGIC_OUTS_B1_7", - "CFG_CENTER_LOGIC_OUTS_B1_8", - "CFG_CENTER_LOGIC_OUTS_B1_9", - "CFG_CENTER_LOGIC_OUTS_B20_0", - "CFG_CENTER_LOGIC_OUTS_B20_1", - "CFG_CENTER_LOGIC_OUTS_B20_10", - "CFG_CENTER_LOGIC_OUTS_B20_11", - "CFG_CENTER_LOGIC_OUTS_B20_12", - "CFG_CENTER_LOGIC_OUTS_B20_13", - "CFG_CENTER_LOGIC_OUTS_B20_14", - "CFG_CENTER_LOGIC_OUTS_B20_15", - "CFG_CENTER_LOGIC_OUTS_B20_16", - "CFG_CENTER_LOGIC_OUTS_B20_17", - "CFG_CENTER_LOGIC_OUTS_B20_18", - "CFG_CENTER_LOGIC_OUTS_B20_19", - "CFG_CENTER_LOGIC_OUTS_B20_2", - "CFG_CENTER_LOGIC_OUTS_B20_3", - "CFG_CENTER_LOGIC_OUTS_B20_4", - "CFG_CENTER_LOGIC_OUTS_B20_5", - "CFG_CENTER_LOGIC_OUTS_B20_6", - "CFG_CENTER_LOGIC_OUTS_B20_7", - "CFG_CENTER_LOGIC_OUTS_B20_8", - "CFG_CENTER_LOGIC_OUTS_B20_9", - "CFG_CENTER_LOGIC_OUTS_B21_0", - "CFG_CENTER_LOGIC_OUTS_B21_1", - "CFG_CENTER_LOGIC_OUTS_B21_10", - "CFG_CENTER_LOGIC_OUTS_B21_11", - "CFG_CENTER_LOGIC_OUTS_B21_12", - "CFG_CENTER_LOGIC_OUTS_B21_13", - "CFG_CENTER_LOGIC_OUTS_B21_14", - "CFG_CENTER_LOGIC_OUTS_B21_15", - "CFG_CENTER_LOGIC_OUTS_B21_16", - "CFG_CENTER_LOGIC_OUTS_B21_17", - "CFG_CENTER_LOGIC_OUTS_B21_18", - "CFG_CENTER_LOGIC_OUTS_B21_19", - "CFG_CENTER_LOGIC_OUTS_B21_2", - "CFG_CENTER_LOGIC_OUTS_B21_3", - "CFG_CENTER_LOGIC_OUTS_B21_4", - "CFG_CENTER_LOGIC_OUTS_B21_5", - "CFG_CENTER_LOGIC_OUTS_B21_6", - "CFG_CENTER_LOGIC_OUTS_B21_7", - "CFG_CENTER_LOGIC_OUTS_B21_8", - "CFG_CENTER_LOGIC_OUTS_B21_9", - "CFG_CENTER_LOGIC_OUTS_B22_0", - "CFG_CENTER_LOGIC_OUTS_B22_1", - "CFG_CENTER_LOGIC_OUTS_B22_10", - "CFG_CENTER_LOGIC_OUTS_B22_11", - "CFG_CENTER_LOGIC_OUTS_B22_12", - "CFG_CENTER_LOGIC_OUTS_B22_13", - "CFG_CENTER_LOGIC_OUTS_B22_14", - "CFG_CENTER_LOGIC_OUTS_B22_15", - "CFG_CENTER_LOGIC_OUTS_B22_16", - "CFG_CENTER_LOGIC_OUTS_B22_17", - "CFG_CENTER_LOGIC_OUTS_B22_18", - "CFG_CENTER_LOGIC_OUTS_B22_19", - "CFG_CENTER_LOGIC_OUTS_B22_2", - "CFG_CENTER_LOGIC_OUTS_B22_3", - "CFG_CENTER_LOGIC_OUTS_B22_4", - "CFG_CENTER_LOGIC_OUTS_B22_5", - "CFG_CENTER_LOGIC_OUTS_B22_6", - "CFG_CENTER_LOGIC_OUTS_B22_7", - "CFG_CENTER_LOGIC_OUTS_B22_8", - "CFG_CENTER_LOGIC_OUTS_B22_9", - "CFG_CENTER_LOGIC_OUTS_B23_0", - "CFG_CENTER_LOGIC_OUTS_B23_1", - "CFG_CENTER_LOGIC_OUTS_B23_10", - "CFG_CENTER_LOGIC_OUTS_B23_11", - "CFG_CENTER_LOGIC_OUTS_B23_12", - "CFG_CENTER_LOGIC_OUTS_B23_13", - "CFG_CENTER_LOGIC_OUTS_B23_14", - "CFG_CENTER_LOGIC_OUTS_B23_15", - "CFG_CENTER_LOGIC_OUTS_B23_16", - "CFG_CENTER_LOGIC_OUTS_B23_17", - "CFG_CENTER_LOGIC_OUTS_B23_18", - "CFG_CENTER_LOGIC_OUTS_B23_19", - "CFG_CENTER_LOGIC_OUTS_B23_2", - "CFG_CENTER_LOGIC_OUTS_B23_3", - "CFG_CENTER_LOGIC_OUTS_B23_4", - "CFG_CENTER_LOGIC_OUTS_B23_5", - "CFG_CENTER_LOGIC_OUTS_B23_6", - "CFG_CENTER_LOGIC_OUTS_B23_7", - "CFG_CENTER_LOGIC_OUTS_B23_8", - "CFG_CENTER_LOGIC_OUTS_B23_9", - "CFG_CENTER_LOGIC_OUTS_B2_0", - "CFG_CENTER_LOGIC_OUTS_B2_1", - "CFG_CENTER_LOGIC_OUTS_B2_10", - "CFG_CENTER_LOGIC_OUTS_B2_11", - "CFG_CENTER_LOGIC_OUTS_B2_12", - "CFG_CENTER_LOGIC_OUTS_B2_13", - "CFG_CENTER_LOGIC_OUTS_B2_14", - "CFG_CENTER_LOGIC_OUTS_B2_15", - "CFG_CENTER_LOGIC_OUTS_B2_16", - "CFG_CENTER_LOGIC_OUTS_B2_17", - "CFG_CENTER_LOGIC_OUTS_B2_18", - "CFG_CENTER_LOGIC_OUTS_B2_19", - "CFG_CENTER_LOGIC_OUTS_B2_2", - "CFG_CENTER_LOGIC_OUTS_B2_3", - "CFG_CENTER_LOGIC_OUTS_B2_4", - "CFG_CENTER_LOGIC_OUTS_B2_5", - "CFG_CENTER_LOGIC_OUTS_B2_6", - "CFG_CENTER_LOGIC_OUTS_B2_7", - "CFG_CENTER_LOGIC_OUTS_B2_8", - "CFG_CENTER_LOGIC_OUTS_B2_9", - "CFG_CENTER_LOGIC_OUTS_B3_0", - "CFG_CENTER_LOGIC_OUTS_B3_1", - "CFG_CENTER_LOGIC_OUTS_B3_10", - "CFG_CENTER_LOGIC_OUTS_B3_11", - "CFG_CENTER_LOGIC_OUTS_B3_12", - "CFG_CENTER_LOGIC_OUTS_B3_13", - "CFG_CENTER_LOGIC_OUTS_B3_14", - "CFG_CENTER_LOGIC_OUTS_B3_15", - "CFG_CENTER_LOGIC_OUTS_B3_16", - "CFG_CENTER_LOGIC_OUTS_B3_17", - "CFG_CENTER_LOGIC_OUTS_B3_18", - "CFG_CENTER_LOGIC_OUTS_B3_19", - "CFG_CENTER_LOGIC_OUTS_B3_2", - "CFG_CENTER_LOGIC_OUTS_B3_3", - "CFG_CENTER_LOGIC_OUTS_B3_4", - "CFG_CENTER_LOGIC_OUTS_B3_5", - "CFG_CENTER_LOGIC_OUTS_B3_6", - "CFG_CENTER_LOGIC_OUTS_B3_7", - "CFG_CENTER_LOGIC_OUTS_B3_8", - "CFG_CENTER_LOGIC_OUTS_B3_9", - "CFG_CENTER_LOGIC_OUTS_B4_0", - "CFG_CENTER_LOGIC_OUTS_B4_1", - "CFG_CENTER_LOGIC_OUTS_B4_10", - "CFG_CENTER_LOGIC_OUTS_B4_11", - "CFG_CENTER_LOGIC_OUTS_B4_12", - "CFG_CENTER_LOGIC_OUTS_B4_13", - "CFG_CENTER_LOGIC_OUTS_B4_14", - "CFG_CENTER_LOGIC_OUTS_B4_15", - "CFG_CENTER_LOGIC_OUTS_B4_16", - "CFG_CENTER_LOGIC_OUTS_B4_17", - "CFG_CENTER_LOGIC_OUTS_B4_18", - "CFG_CENTER_LOGIC_OUTS_B4_19", - "CFG_CENTER_LOGIC_OUTS_B4_2", - "CFG_CENTER_LOGIC_OUTS_B4_3", - "CFG_CENTER_LOGIC_OUTS_B4_4", - "CFG_CENTER_LOGIC_OUTS_B4_5", - "CFG_CENTER_LOGIC_OUTS_B4_6", - "CFG_CENTER_LOGIC_OUTS_B4_7", - "CFG_CENTER_LOGIC_OUTS_B4_8", - "CFG_CENTER_LOGIC_OUTS_B4_9", - "CFG_CENTER_LOGIC_OUTS_B5_0", - "CFG_CENTER_LOGIC_OUTS_B5_1", - "CFG_CENTER_LOGIC_OUTS_B5_10", - "CFG_CENTER_LOGIC_OUTS_B5_11", - "CFG_CENTER_LOGIC_OUTS_B5_12", - "CFG_CENTER_LOGIC_OUTS_B5_13", - "CFG_CENTER_LOGIC_OUTS_B5_14", - "CFG_CENTER_LOGIC_OUTS_B5_15", - "CFG_CENTER_LOGIC_OUTS_B5_16", - "CFG_CENTER_LOGIC_OUTS_B5_17", - "CFG_CENTER_LOGIC_OUTS_B5_18", - "CFG_CENTER_LOGIC_OUTS_B5_19", - "CFG_CENTER_LOGIC_OUTS_B5_2", - "CFG_CENTER_LOGIC_OUTS_B5_3", - "CFG_CENTER_LOGIC_OUTS_B5_4", - "CFG_CENTER_LOGIC_OUTS_B5_5", - "CFG_CENTER_LOGIC_OUTS_B5_6", - "CFG_CENTER_LOGIC_OUTS_B5_7", - "CFG_CENTER_LOGIC_OUTS_B5_8", - "CFG_CENTER_LOGIC_OUTS_B5_9", - "CFG_CENTER_LOGIC_OUTS_B6_0", - "CFG_CENTER_LOGIC_OUTS_B6_1", - "CFG_CENTER_LOGIC_OUTS_B6_10", - "CFG_CENTER_LOGIC_OUTS_B6_11", - "CFG_CENTER_LOGIC_OUTS_B6_12", - "CFG_CENTER_LOGIC_OUTS_B6_13", - "CFG_CENTER_LOGIC_OUTS_B6_14", - "CFG_CENTER_LOGIC_OUTS_B6_15", - "CFG_CENTER_LOGIC_OUTS_B6_16", - "CFG_CENTER_LOGIC_OUTS_B6_17", - "CFG_CENTER_LOGIC_OUTS_B6_18", - "CFG_CENTER_LOGIC_OUTS_B6_19", - "CFG_CENTER_LOGIC_OUTS_B6_2", - "CFG_CENTER_LOGIC_OUTS_B6_3", - "CFG_CENTER_LOGIC_OUTS_B6_4", - "CFG_CENTER_LOGIC_OUTS_B6_5", - "CFG_CENTER_LOGIC_OUTS_B6_6", - "CFG_CENTER_LOGIC_OUTS_B6_7", - "CFG_CENTER_LOGIC_OUTS_B6_8", - "CFG_CENTER_LOGIC_OUTS_B6_9", - "CFG_CENTER_LOGIC_OUTS_B7_0", - "CFG_CENTER_LOGIC_OUTS_B7_1", - "CFG_CENTER_LOGIC_OUTS_B7_10", - "CFG_CENTER_LOGIC_OUTS_B7_11", - "CFG_CENTER_LOGIC_OUTS_B7_12", - "CFG_CENTER_LOGIC_OUTS_B7_13", - "CFG_CENTER_LOGIC_OUTS_B7_14", - "CFG_CENTER_LOGIC_OUTS_B7_15", - "CFG_CENTER_LOGIC_OUTS_B7_16", - "CFG_CENTER_LOGIC_OUTS_B7_17", - "CFG_CENTER_LOGIC_OUTS_B7_18", - "CFG_CENTER_LOGIC_OUTS_B7_19", - "CFG_CENTER_LOGIC_OUTS_B7_2", - "CFG_CENTER_LOGIC_OUTS_B7_3", - "CFG_CENTER_LOGIC_OUTS_B7_4", - "CFG_CENTER_LOGIC_OUTS_B7_5", - "CFG_CENTER_LOGIC_OUTS_B7_6", - "CFG_CENTER_LOGIC_OUTS_B7_7", - "CFG_CENTER_LOGIC_OUTS_B7_8", - "CFG_CENTER_LOGIC_OUTS_B7_9", - "CFG_CENTER_LOGIC_OUTS_B8_0", - "CFG_CENTER_LOGIC_OUTS_B8_1", - "CFG_CENTER_LOGIC_OUTS_B8_10", - "CFG_CENTER_LOGIC_OUTS_B8_11", - "CFG_CENTER_LOGIC_OUTS_B8_12", - "CFG_CENTER_LOGIC_OUTS_B8_13", - "CFG_CENTER_LOGIC_OUTS_B8_14", - "CFG_CENTER_LOGIC_OUTS_B8_15", - "CFG_CENTER_LOGIC_OUTS_B8_16", - "CFG_CENTER_LOGIC_OUTS_B8_17", - "CFG_CENTER_LOGIC_OUTS_B8_18", - "CFG_CENTER_LOGIC_OUTS_B8_19", - "CFG_CENTER_LOGIC_OUTS_B8_2", - "CFG_CENTER_LOGIC_OUTS_B8_3", - "CFG_CENTER_LOGIC_OUTS_B8_4", - "CFG_CENTER_LOGIC_OUTS_B8_5", - "CFG_CENTER_LOGIC_OUTS_B8_6", - "CFG_CENTER_LOGIC_OUTS_B8_7", - "CFG_CENTER_LOGIC_OUTS_B8_8", - "CFG_CENTER_LOGIC_OUTS_B8_9", - "CFG_CENTER_LOGIC_OUTS_B9_0", - "CFG_CENTER_LOGIC_OUTS_B9_1", - "CFG_CENTER_LOGIC_OUTS_B9_10", - "CFG_CENTER_LOGIC_OUTS_B9_11", - "CFG_CENTER_LOGIC_OUTS_B9_12", - "CFG_CENTER_LOGIC_OUTS_B9_13", - "CFG_CENTER_LOGIC_OUTS_B9_14", - "CFG_CENTER_LOGIC_OUTS_B9_15", - "CFG_CENTER_LOGIC_OUTS_B9_16", - "CFG_CENTER_LOGIC_OUTS_B9_17", - "CFG_CENTER_LOGIC_OUTS_B9_18", - "CFG_CENTER_LOGIC_OUTS_B9_19", - "CFG_CENTER_LOGIC_OUTS_B9_2", - "CFG_CENTER_LOGIC_OUTS_B9_3", - "CFG_CENTER_LOGIC_OUTS_B9_4", - "CFG_CENTER_LOGIC_OUTS_B9_5", - "CFG_CENTER_LOGIC_OUTS_B9_6", - "CFG_CENTER_LOGIC_OUTS_B9_7", - "CFG_CENTER_LOGIC_OUTS_B9_8", - "CFG_CENTER_LOGIC_OUTS_B9_9", - "CFG_CENTER_NE2A0_0", - "CFG_CENTER_NE2A0_1", - "CFG_CENTER_NE2A0_10", - "CFG_CENTER_NE2A0_11", - "CFG_CENTER_NE2A0_12", - "CFG_CENTER_NE2A0_13", - "CFG_CENTER_NE2A0_14", - "CFG_CENTER_NE2A0_15", - "CFG_CENTER_NE2A0_16", - "CFG_CENTER_NE2A0_17", - "CFG_CENTER_NE2A0_18", - "CFG_CENTER_NE2A0_19", - "CFG_CENTER_NE2A0_2", - "CFG_CENTER_NE2A0_3", - "CFG_CENTER_NE2A0_4", - "CFG_CENTER_NE2A0_5", - "CFG_CENTER_NE2A0_6", - "CFG_CENTER_NE2A0_7", - "CFG_CENTER_NE2A0_8", - "CFG_CENTER_NE2A0_9", - "CFG_CENTER_NE2A1_0", - "CFG_CENTER_NE2A1_1", - "CFG_CENTER_NE2A1_10", - "CFG_CENTER_NE2A1_11", - "CFG_CENTER_NE2A1_12", - "CFG_CENTER_NE2A1_13", - "CFG_CENTER_NE2A1_14", - "CFG_CENTER_NE2A1_15", - "CFG_CENTER_NE2A1_16", - "CFG_CENTER_NE2A1_17", - "CFG_CENTER_NE2A1_18", - "CFG_CENTER_NE2A1_19", - "CFG_CENTER_NE2A1_2", - "CFG_CENTER_NE2A1_3", - "CFG_CENTER_NE2A1_4", - "CFG_CENTER_NE2A1_5", - "CFG_CENTER_NE2A1_6", - "CFG_CENTER_NE2A1_7", - "CFG_CENTER_NE2A1_8", - "CFG_CENTER_NE2A1_9", - "CFG_CENTER_NE2A2_0", - "CFG_CENTER_NE2A2_1", - "CFG_CENTER_NE2A2_10", - "CFG_CENTER_NE2A2_11", - "CFG_CENTER_NE2A2_12", - "CFG_CENTER_NE2A2_13", - "CFG_CENTER_NE2A2_14", - "CFG_CENTER_NE2A2_15", - "CFG_CENTER_NE2A2_16", - "CFG_CENTER_NE2A2_17", - "CFG_CENTER_NE2A2_18", - "CFG_CENTER_NE2A2_19", - "CFG_CENTER_NE2A2_2", - "CFG_CENTER_NE2A2_3", - "CFG_CENTER_NE2A2_4", - "CFG_CENTER_NE2A2_5", - "CFG_CENTER_NE2A2_6", - "CFG_CENTER_NE2A2_7", - "CFG_CENTER_NE2A2_8", - "CFG_CENTER_NE2A2_9", - "CFG_CENTER_NE2A3_0", - "CFG_CENTER_NE2A3_1", - "CFG_CENTER_NE2A3_10", - "CFG_CENTER_NE2A3_11", - "CFG_CENTER_NE2A3_12", - "CFG_CENTER_NE2A3_13", - "CFG_CENTER_NE2A3_14", - "CFG_CENTER_NE2A3_15", - "CFG_CENTER_NE2A3_16", - "CFG_CENTER_NE2A3_17", - "CFG_CENTER_NE2A3_18", - "CFG_CENTER_NE2A3_19", - "CFG_CENTER_NE2A3_2", - "CFG_CENTER_NE2A3_3", - "CFG_CENTER_NE2A3_4", - "CFG_CENTER_NE2A3_5", - "CFG_CENTER_NE2A3_6", - "CFG_CENTER_NE2A3_7", - "CFG_CENTER_NE2A3_8", - "CFG_CENTER_NE2A3_9", - "CFG_CENTER_NE4BEG0_0", - "CFG_CENTER_NE4BEG0_1", - "CFG_CENTER_NE4BEG0_10", - "CFG_CENTER_NE4BEG0_11", - "CFG_CENTER_NE4BEG0_12", - "CFG_CENTER_NE4BEG0_13", - "CFG_CENTER_NE4BEG0_14", - "CFG_CENTER_NE4BEG0_15", - "CFG_CENTER_NE4BEG0_16", - "CFG_CENTER_NE4BEG0_17", - "CFG_CENTER_NE4BEG0_18", - "CFG_CENTER_NE4BEG0_19", - "CFG_CENTER_NE4BEG0_2", - "CFG_CENTER_NE4BEG0_3", - "CFG_CENTER_NE4BEG0_4", - "CFG_CENTER_NE4BEG0_5", - "CFG_CENTER_NE4BEG0_6", - "CFG_CENTER_NE4BEG0_7", - "CFG_CENTER_NE4BEG0_8", - "CFG_CENTER_NE4BEG0_9", - "CFG_CENTER_NE4BEG1_0", - "CFG_CENTER_NE4BEG1_1", - "CFG_CENTER_NE4BEG1_10", - "CFG_CENTER_NE4BEG1_11", - "CFG_CENTER_NE4BEG1_12", - "CFG_CENTER_NE4BEG1_13", - "CFG_CENTER_NE4BEG1_14", - "CFG_CENTER_NE4BEG1_15", - "CFG_CENTER_NE4BEG1_16", - "CFG_CENTER_NE4BEG1_17", - "CFG_CENTER_NE4BEG1_18", - "CFG_CENTER_NE4BEG1_19", - "CFG_CENTER_NE4BEG1_2", - "CFG_CENTER_NE4BEG1_3", - "CFG_CENTER_NE4BEG1_4", - "CFG_CENTER_NE4BEG1_5", - "CFG_CENTER_NE4BEG1_6", - "CFG_CENTER_NE4BEG1_7", - "CFG_CENTER_NE4BEG1_8", - "CFG_CENTER_NE4BEG1_9", - "CFG_CENTER_NE4BEG2_0", - "CFG_CENTER_NE4BEG2_1", - "CFG_CENTER_NE4BEG2_10", - "CFG_CENTER_NE4BEG2_11", - "CFG_CENTER_NE4BEG2_12", - "CFG_CENTER_NE4BEG2_13", - "CFG_CENTER_NE4BEG2_14", - "CFG_CENTER_NE4BEG2_15", - "CFG_CENTER_NE4BEG2_16", - "CFG_CENTER_NE4BEG2_17", - "CFG_CENTER_NE4BEG2_18", - "CFG_CENTER_NE4BEG2_19", - "CFG_CENTER_NE4BEG2_2", - "CFG_CENTER_NE4BEG2_3", - "CFG_CENTER_NE4BEG2_4", - "CFG_CENTER_NE4BEG2_5", - "CFG_CENTER_NE4BEG2_6", - "CFG_CENTER_NE4BEG2_7", - "CFG_CENTER_NE4BEG2_8", - "CFG_CENTER_NE4BEG2_9", - "CFG_CENTER_NE4BEG3_0", - "CFG_CENTER_NE4BEG3_1", - "CFG_CENTER_NE4BEG3_10", - "CFG_CENTER_NE4BEG3_11", - "CFG_CENTER_NE4BEG3_12", - "CFG_CENTER_NE4BEG3_13", - "CFG_CENTER_NE4BEG3_14", - "CFG_CENTER_NE4BEG3_15", - "CFG_CENTER_NE4BEG3_16", - "CFG_CENTER_NE4BEG3_17", - "CFG_CENTER_NE4BEG3_18", - "CFG_CENTER_NE4BEG3_19", - "CFG_CENTER_NE4BEG3_2", - "CFG_CENTER_NE4BEG3_3", - "CFG_CENTER_NE4BEG3_4", - "CFG_CENTER_NE4BEG3_5", - "CFG_CENTER_NE4BEG3_6", - "CFG_CENTER_NE4BEG3_7", - "CFG_CENTER_NE4BEG3_8", - "CFG_CENTER_NE4BEG3_9", - "CFG_CENTER_NE4C0_0", - "CFG_CENTER_NE4C0_1", - "CFG_CENTER_NE4C0_10", - "CFG_CENTER_NE4C0_11", - "CFG_CENTER_NE4C0_12", - "CFG_CENTER_NE4C0_13", - "CFG_CENTER_NE4C0_14", - "CFG_CENTER_NE4C0_15", - "CFG_CENTER_NE4C0_16", - "CFG_CENTER_NE4C0_17", - "CFG_CENTER_NE4C0_18", - "CFG_CENTER_NE4C0_19", - "CFG_CENTER_NE4C0_2", - "CFG_CENTER_NE4C0_3", - "CFG_CENTER_NE4C0_4", - "CFG_CENTER_NE4C0_5", - "CFG_CENTER_NE4C0_6", - "CFG_CENTER_NE4C0_7", - "CFG_CENTER_NE4C0_8", - "CFG_CENTER_NE4C0_9", - "CFG_CENTER_NE4C1_0", - "CFG_CENTER_NE4C1_1", - "CFG_CENTER_NE4C1_10", - "CFG_CENTER_NE4C1_11", - "CFG_CENTER_NE4C1_12", - "CFG_CENTER_NE4C1_13", - "CFG_CENTER_NE4C1_14", - "CFG_CENTER_NE4C1_15", - "CFG_CENTER_NE4C1_16", - "CFG_CENTER_NE4C1_17", - "CFG_CENTER_NE4C1_18", - "CFG_CENTER_NE4C1_19", - "CFG_CENTER_NE4C1_2", - "CFG_CENTER_NE4C1_3", - "CFG_CENTER_NE4C1_4", - "CFG_CENTER_NE4C1_5", - "CFG_CENTER_NE4C1_6", - "CFG_CENTER_NE4C1_7", - "CFG_CENTER_NE4C1_8", - "CFG_CENTER_NE4C1_9", - "CFG_CENTER_NE4C2_0", - "CFG_CENTER_NE4C2_1", - "CFG_CENTER_NE4C2_10", - "CFG_CENTER_NE4C2_11", - "CFG_CENTER_NE4C2_12", - "CFG_CENTER_NE4C2_13", - "CFG_CENTER_NE4C2_14", - "CFG_CENTER_NE4C2_15", - "CFG_CENTER_NE4C2_16", - "CFG_CENTER_NE4C2_17", - "CFG_CENTER_NE4C2_18", - "CFG_CENTER_NE4C2_19", - "CFG_CENTER_NE4C2_2", - "CFG_CENTER_NE4C2_3", - "CFG_CENTER_NE4C2_4", - "CFG_CENTER_NE4C2_5", - "CFG_CENTER_NE4C2_6", - "CFG_CENTER_NE4C2_7", - "CFG_CENTER_NE4C2_8", - "CFG_CENTER_NE4C2_9", - "CFG_CENTER_NE4C3_0", - "CFG_CENTER_NE4C3_1", - "CFG_CENTER_NE4C3_10", - "CFG_CENTER_NE4C3_11", - "CFG_CENTER_NE4C3_12", - "CFG_CENTER_NE4C3_13", - "CFG_CENTER_NE4C3_14", - "CFG_CENTER_NE4C3_15", - "CFG_CENTER_NE4C3_16", - "CFG_CENTER_NE4C3_17", - "CFG_CENTER_NE4C3_18", - "CFG_CENTER_NE4C3_19", - "CFG_CENTER_NE4C3_2", - "CFG_CENTER_NE4C3_3", - "CFG_CENTER_NE4C3_4", - "CFG_CENTER_NE4C3_5", - "CFG_CENTER_NE4C3_6", - "CFG_CENTER_NE4C3_7", - "CFG_CENTER_NE4C3_8", - "CFG_CENTER_NE4C3_9", - "CFG_CENTER_NW2A0_0", - "CFG_CENTER_NW2A0_1", - "CFG_CENTER_NW2A0_10", - "CFG_CENTER_NW2A0_11", - "CFG_CENTER_NW2A0_12", - "CFG_CENTER_NW2A0_13", - "CFG_CENTER_NW2A0_14", - "CFG_CENTER_NW2A0_15", - "CFG_CENTER_NW2A0_16", - "CFG_CENTER_NW2A0_17", - "CFG_CENTER_NW2A0_18", - "CFG_CENTER_NW2A0_19", - "CFG_CENTER_NW2A0_2", - "CFG_CENTER_NW2A0_3", - "CFG_CENTER_NW2A0_4", - "CFG_CENTER_NW2A0_5", - "CFG_CENTER_NW2A0_6", - "CFG_CENTER_NW2A0_7", - "CFG_CENTER_NW2A0_8", - "CFG_CENTER_NW2A0_9", - "CFG_CENTER_NW2A1_0", - "CFG_CENTER_NW2A1_1", - "CFG_CENTER_NW2A1_10", - "CFG_CENTER_NW2A1_11", - "CFG_CENTER_NW2A1_12", - "CFG_CENTER_NW2A1_13", - "CFG_CENTER_NW2A1_14", - "CFG_CENTER_NW2A1_15", - "CFG_CENTER_NW2A1_16", - "CFG_CENTER_NW2A1_17", - "CFG_CENTER_NW2A1_18", - "CFG_CENTER_NW2A1_19", - "CFG_CENTER_NW2A1_2", - "CFG_CENTER_NW2A1_3", - "CFG_CENTER_NW2A1_4", - "CFG_CENTER_NW2A1_5", - "CFG_CENTER_NW2A1_6", - "CFG_CENTER_NW2A1_7", - "CFG_CENTER_NW2A1_8", - "CFG_CENTER_NW2A1_9", - "CFG_CENTER_NW2A2_0", - "CFG_CENTER_NW2A2_1", - "CFG_CENTER_NW2A2_10", - "CFG_CENTER_NW2A2_11", - "CFG_CENTER_NW2A2_12", - "CFG_CENTER_NW2A2_13", - "CFG_CENTER_NW2A2_14", - "CFG_CENTER_NW2A2_15", - "CFG_CENTER_NW2A2_16", - "CFG_CENTER_NW2A2_17", - "CFG_CENTER_NW2A2_18", - "CFG_CENTER_NW2A2_19", - "CFG_CENTER_NW2A2_2", - "CFG_CENTER_NW2A2_3", - "CFG_CENTER_NW2A2_4", - "CFG_CENTER_NW2A2_5", - "CFG_CENTER_NW2A2_6", - "CFG_CENTER_NW2A2_7", - "CFG_CENTER_NW2A2_8", - "CFG_CENTER_NW2A2_9", - "CFG_CENTER_NW2A3_0", - "CFG_CENTER_NW2A3_1", - "CFG_CENTER_NW2A3_10", - "CFG_CENTER_NW2A3_11", - "CFG_CENTER_NW2A3_12", - "CFG_CENTER_NW2A3_13", - "CFG_CENTER_NW2A3_14", - "CFG_CENTER_NW2A3_15", - "CFG_CENTER_NW2A3_16", - "CFG_CENTER_NW2A3_17", - "CFG_CENTER_NW2A3_18", - "CFG_CENTER_NW2A3_19", - "CFG_CENTER_NW2A3_2", - "CFG_CENTER_NW2A3_3", - "CFG_CENTER_NW2A3_4", - "CFG_CENTER_NW2A3_5", - "CFG_CENTER_NW2A3_6", - "CFG_CENTER_NW2A3_7", - "CFG_CENTER_NW2A3_8", - "CFG_CENTER_NW2A3_9", - "CFG_CENTER_NW4A0_0", - "CFG_CENTER_NW4A0_1", - "CFG_CENTER_NW4A0_10", - "CFG_CENTER_NW4A0_11", - "CFG_CENTER_NW4A0_12", - "CFG_CENTER_NW4A0_13", - "CFG_CENTER_NW4A0_14", - "CFG_CENTER_NW4A0_15", - "CFG_CENTER_NW4A0_16", - "CFG_CENTER_NW4A0_17", - "CFG_CENTER_NW4A0_18", - "CFG_CENTER_NW4A0_19", - "CFG_CENTER_NW4A0_2", - "CFG_CENTER_NW4A0_3", - "CFG_CENTER_NW4A0_4", - "CFG_CENTER_NW4A0_5", - "CFG_CENTER_NW4A0_6", - "CFG_CENTER_NW4A0_7", - "CFG_CENTER_NW4A0_8", - "CFG_CENTER_NW4A0_9", - "CFG_CENTER_NW4A1_0", - "CFG_CENTER_NW4A1_1", - "CFG_CENTER_NW4A1_10", - "CFG_CENTER_NW4A1_11", - "CFG_CENTER_NW4A1_12", - "CFG_CENTER_NW4A1_13", - "CFG_CENTER_NW4A1_14", - "CFG_CENTER_NW4A1_15", - "CFG_CENTER_NW4A1_16", - "CFG_CENTER_NW4A1_17", - "CFG_CENTER_NW4A1_18", - "CFG_CENTER_NW4A1_19", - "CFG_CENTER_NW4A1_2", - "CFG_CENTER_NW4A1_3", - "CFG_CENTER_NW4A1_4", - "CFG_CENTER_NW4A1_5", - "CFG_CENTER_NW4A1_6", - "CFG_CENTER_NW4A1_7", - "CFG_CENTER_NW4A1_8", - "CFG_CENTER_NW4A1_9", - "CFG_CENTER_NW4A2_0", - "CFG_CENTER_NW4A2_1", - "CFG_CENTER_NW4A2_10", - "CFG_CENTER_NW4A2_11", - "CFG_CENTER_NW4A2_12", - "CFG_CENTER_NW4A2_13", - "CFG_CENTER_NW4A2_14", - "CFG_CENTER_NW4A2_15", - "CFG_CENTER_NW4A2_16", - "CFG_CENTER_NW4A2_17", - "CFG_CENTER_NW4A2_18", - "CFG_CENTER_NW4A2_19", - "CFG_CENTER_NW4A2_2", - "CFG_CENTER_NW4A2_3", - "CFG_CENTER_NW4A2_4", - "CFG_CENTER_NW4A2_5", - "CFG_CENTER_NW4A2_6", - "CFG_CENTER_NW4A2_7", - "CFG_CENTER_NW4A2_8", - "CFG_CENTER_NW4A2_9", - "CFG_CENTER_NW4A3_0", - "CFG_CENTER_NW4A3_1", - "CFG_CENTER_NW4A3_10", - "CFG_CENTER_NW4A3_11", - "CFG_CENTER_NW4A3_12", - "CFG_CENTER_NW4A3_13", - "CFG_CENTER_NW4A3_14", - "CFG_CENTER_NW4A3_15", - "CFG_CENTER_NW4A3_16", - "CFG_CENTER_NW4A3_17", - "CFG_CENTER_NW4A3_18", - "CFG_CENTER_NW4A3_19", - "CFG_CENTER_NW4A3_2", - "CFG_CENTER_NW4A3_3", - "CFG_CENTER_NW4A3_4", - "CFG_CENTER_NW4A3_5", - "CFG_CENTER_NW4A3_6", - "CFG_CENTER_NW4A3_7", - "CFG_CENTER_NW4A3_8", - "CFG_CENTER_NW4A3_9", - "CFG_CENTER_NW4END0_0", - "CFG_CENTER_NW4END0_1", - "CFG_CENTER_NW4END0_10", - "CFG_CENTER_NW4END0_11", - "CFG_CENTER_NW4END0_12", - "CFG_CENTER_NW4END0_13", - "CFG_CENTER_NW4END0_14", - "CFG_CENTER_NW4END0_15", - "CFG_CENTER_NW4END0_16", - "CFG_CENTER_NW4END0_17", - "CFG_CENTER_NW4END0_18", - "CFG_CENTER_NW4END0_19", - "CFG_CENTER_NW4END0_2", - "CFG_CENTER_NW4END0_3", - "CFG_CENTER_NW4END0_4", - "CFG_CENTER_NW4END0_5", - "CFG_CENTER_NW4END0_6", - "CFG_CENTER_NW4END0_7", - "CFG_CENTER_NW4END0_8", - "CFG_CENTER_NW4END0_9", - "CFG_CENTER_NW4END1_0", - "CFG_CENTER_NW4END1_1", - "CFG_CENTER_NW4END1_10", - "CFG_CENTER_NW4END1_11", - "CFG_CENTER_NW4END1_12", - "CFG_CENTER_NW4END1_13", - "CFG_CENTER_NW4END1_14", - "CFG_CENTER_NW4END1_15", - "CFG_CENTER_NW4END1_16", - "CFG_CENTER_NW4END1_17", - "CFG_CENTER_NW4END1_18", - "CFG_CENTER_NW4END1_19", - "CFG_CENTER_NW4END1_2", - "CFG_CENTER_NW4END1_3", - "CFG_CENTER_NW4END1_4", - "CFG_CENTER_NW4END1_5", - "CFG_CENTER_NW4END1_6", - "CFG_CENTER_NW4END1_7", - "CFG_CENTER_NW4END1_8", - "CFG_CENTER_NW4END1_9", - "CFG_CENTER_NW4END2_0", - "CFG_CENTER_NW4END2_1", - "CFG_CENTER_NW4END2_10", - "CFG_CENTER_NW4END2_11", - "CFG_CENTER_NW4END2_12", - "CFG_CENTER_NW4END2_13", - "CFG_CENTER_NW4END2_14", - "CFG_CENTER_NW4END2_15", - "CFG_CENTER_NW4END2_16", - "CFG_CENTER_NW4END2_17", - "CFG_CENTER_NW4END2_18", - "CFG_CENTER_NW4END2_19", - "CFG_CENTER_NW4END2_2", - "CFG_CENTER_NW4END2_3", - "CFG_CENTER_NW4END2_4", - "CFG_CENTER_NW4END2_5", - "CFG_CENTER_NW4END2_6", - "CFG_CENTER_NW4END2_7", - "CFG_CENTER_NW4END2_8", - "CFG_CENTER_NW4END2_9", - "CFG_CENTER_NW4END3_0", - "CFG_CENTER_NW4END3_1", - "CFG_CENTER_NW4END3_10", - "CFG_CENTER_NW4END3_11", - "CFG_CENTER_NW4END3_12", - "CFG_CENTER_NW4END3_13", - "CFG_CENTER_NW4END3_14", - "CFG_CENTER_NW4END3_15", - "CFG_CENTER_NW4END3_16", - "CFG_CENTER_NW4END3_17", - "CFG_CENTER_NW4END3_18", - "CFG_CENTER_NW4END3_19", - "CFG_CENTER_NW4END3_2", - "CFG_CENTER_NW4END3_3", - "CFG_CENTER_NW4END3_4", - "CFG_CENTER_NW4END3_5", - "CFG_CENTER_NW4END3_6", - "CFG_CENTER_NW4END3_7", - "CFG_CENTER_NW4END3_8", - "CFG_CENTER_NW4END3_9", - "CFG_CENTER_SE2A0_0", - "CFG_CENTER_SE2A0_1", - "CFG_CENTER_SE2A0_10", - "CFG_CENTER_SE2A0_11", - "CFG_CENTER_SE2A0_12", - "CFG_CENTER_SE2A0_13", - "CFG_CENTER_SE2A0_14", - "CFG_CENTER_SE2A0_15", - "CFG_CENTER_SE2A0_16", - "CFG_CENTER_SE2A0_17", - "CFG_CENTER_SE2A0_18", - "CFG_CENTER_SE2A0_19", - "CFG_CENTER_SE2A0_2", - "CFG_CENTER_SE2A0_3", - "CFG_CENTER_SE2A0_4", - "CFG_CENTER_SE2A0_5", - "CFG_CENTER_SE2A0_6", - "CFG_CENTER_SE2A0_7", - "CFG_CENTER_SE2A0_8", - "CFG_CENTER_SE2A0_9", - "CFG_CENTER_SE2A1_0", - "CFG_CENTER_SE2A1_1", - "CFG_CENTER_SE2A1_10", - "CFG_CENTER_SE2A1_11", - "CFG_CENTER_SE2A1_12", - "CFG_CENTER_SE2A1_13", - "CFG_CENTER_SE2A1_14", - "CFG_CENTER_SE2A1_15", - "CFG_CENTER_SE2A1_16", - "CFG_CENTER_SE2A1_17", - "CFG_CENTER_SE2A1_18", - "CFG_CENTER_SE2A1_19", - "CFG_CENTER_SE2A1_2", - "CFG_CENTER_SE2A1_3", - "CFG_CENTER_SE2A1_4", - "CFG_CENTER_SE2A1_5", - "CFG_CENTER_SE2A1_6", - "CFG_CENTER_SE2A1_7", - "CFG_CENTER_SE2A1_8", - "CFG_CENTER_SE2A1_9", - "CFG_CENTER_SE2A2_0", - "CFG_CENTER_SE2A2_1", - "CFG_CENTER_SE2A2_10", - "CFG_CENTER_SE2A2_11", - "CFG_CENTER_SE2A2_12", - "CFG_CENTER_SE2A2_13", - "CFG_CENTER_SE2A2_14", - "CFG_CENTER_SE2A2_15", - "CFG_CENTER_SE2A2_16", - "CFG_CENTER_SE2A2_17", - "CFG_CENTER_SE2A2_18", - "CFG_CENTER_SE2A2_19", - "CFG_CENTER_SE2A2_2", - "CFG_CENTER_SE2A2_3", - "CFG_CENTER_SE2A2_4", - "CFG_CENTER_SE2A2_5", - "CFG_CENTER_SE2A2_6", - "CFG_CENTER_SE2A2_7", - "CFG_CENTER_SE2A2_8", - "CFG_CENTER_SE2A2_9", - "CFG_CENTER_SE2A3_0", - "CFG_CENTER_SE2A3_1", - "CFG_CENTER_SE2A3_10", - "CFG_CENTER_SE2A3_11", - "CFG_CENTER_SE2A3_12", - "CFG_CENTER_SE2A3_13", - "CFG_CENTER_SE2A3_14", - "CFG_CENTER_SE2A3_15", - "CFG_CENTER_SE2A3_16", - "CFG_CENTER_SE2A3_17", - "CFG_CENTER_SE2A3_18", - "CFG_CENTER_SE2A3_19", - "CFG_CENTER_SE2A3_2", - "CFG_CENTER_SE2A3_3", - "CFG_CENTER_SE2A3_4", - "CFG_CENTER_SE2A3_5", - "CFG_CENTER_SE2A3_6", - "CFG_CENTER_SE2A3_7", - "CFG_CENTER_SE2A3_8", - "CFG_CENTER_SE2A3_9", - "CFG_CENTER_SE4BEG0_0", - "CFG_CENTER_SE4BEG0_1", - "CFG_CENTER_SE4BEG0_10", - "CFG_CENTER_SE4BEG0_11", - "CFG_CENTER_SE4BEG0_12", - "CFG_CENTER_SE4BEG0_13", - "CFG_CENTER_SE4BEG0_14", - "CFG_CENTER_SE4BEG0_15", - "CFG_CENTER_SE4BEG0_16", - "CFG_CENTER_SE4BEG0_17", - "CFG_CENTER_SE4BEG0_18", - "CFG_CENTER_SE4BEG0_19", - "CFG_CENTER_SE4BEG0_2", - "CFG_CENTER_SE4BEG0_3", - "CFG_CENTER_SE4BEG0_4", - "CFG_CENTER_SE4BEG0_5", - "CFG_CENTER_SE4BEG0_6", - "CFG_CENTER_SE4BEG0_7", - "CFG_CENTER_SE4BEG0_8", - "CFG_CENTER_SE4BEG0_9", - "CFG_CENTER_SE4BEG1_0", - "CFG_CENTER_SE4BEG1_1", - "CFG_CENTER_SE4BEG1_10", - "CFG_CENTER_SE4BEG1_11", - "CFG_CENTER_SE4BEG1_12", - "CFG_CENTER_SE4BEG1_13", - "CFG_CENTER_SE4BEG1_14", - "CFG_CENTER_SE4BEG1_15", - "CFG_CENTER_SE4BEG1_16", - "CFG_CENTER_SE4BEG1_17", - "CFG_CENTER_SE4BEG1_18", - "CFG_CENTER_SE4BEG1_19", - "CFG_CENTER_SE4BEG1_2", - "CFG_CENTER_SE4BEG1_3", - "CFG_CENTER_SE4BEG1_4", - "CFG_CENTER_SE4BEG1_5", - "CFG_CENTER_SE4BEG1_6", - "CFG_CENTER_SE4BEG1_7", - "CFG_CENTER_SE4BEG1_8", - "CFG_CENTER_SE4BEG1_9", - "CFG_CENTER_SE4BEG2_0", - "CFG_CENTER_SE4BEG2_1", - "CFG_CENTER_SE4BEG2_10", - "CFG_CENTER_SE4BEG2_11", - "CFG_CENTER_SE4BEG2_12", - "CFG_CENTER_SE4BEG2_13", - "CFG_CENTER_SE4BEG2_14", - "CFG_CENTER_SE4BEG2_15", - "CFG_CENTER_SE4BEG2_16", - "CFG_CENTER_SE4BEG2_17", - "CFG_CENTER_SE4BEG2_18", - "CFG_CENTER_SE4BEG2_19", - "CFG_CENTER_SE4BEG2_2", - "CFG_CENTER_SE4BEG2_3", - "CFG_CENTER_SE4BEG2_4", - "CFG_CENTER_SE4BEG2_5", - "CFG_CENTER_SE4BEG2_6", - "CFG_CENTER_SE4BEG2_7", - "CFG_CENTER_SE4BEG2_8", - "CFG_CENTER_SE4BEG2_9", - "CFG_CENTER_SE4BEG3_0", - "CFG_CENTER_SE4BEG3_1", - "CFG_CENTER_SE4BEG3_10", - "CFG_CENTER_SE4BEG3_11", - "CFG_CENTER_SE4BEG3_12", - "CFG_CENTER_SE4BEG3_13", - "CFG_CENTER_SE4BEG3_14", - "CFG_CENTER_SE4BEG3_15", - "CFG_CENTER_SE4BEG3_16", - "CFG_CENTER_SE4BEG3_17", - "CFG_CENTER_SE4BEG3_18", - "CFG_CENTER_SE4BEG3_19", - "CFG_CENTER_SE4BEG3_2", - "CFG_CENTER_SE4BEG3_3", - "CFG_CENTER_SE4BEG3_4", - "CFG_CENTER_SE4BEG3_5", - "CFG_CENTER_SE4BEG3_6", - "CFG_CENTER_SE4BEG3_7", - "CFG_CENTER_SE4BEG3_8", - "CFG_CENTER_SE4BEG3_9", - "CFG_CENTER_SE4C0_0", - "CFG_CENTER_SE4C0_1", - "CFG_CENTER_SE4C0_10", - "CFG_CENTER_SE4C0_11", - "CFG_CENTER_SE4C0_12", - "CFG_CENTER_SE4C0_13", - "CFG_CENTER_SE4C0_14", - "CFG_CENTER_SE4C0_15", - "CFG_CENTER_SE4C0_16", - "CFG_CENTER_SE4C0_17", - "CFG_CENTER_SE4C0_18", - "CFG_CENTER_SE4C0_19", - "CFG_CENTER_SE4C0_2", - "CFG_CENTER_SE4C0_3", - "CFG_CENTER_SE4C0_4", - "CFG_CENTER_SE4C0_5", - "CFG_CENTER_SE4C0_6", - "CFG_CENTER_SE4C0_7", - "CFG_CENTER_SE4C0_8", - "CFG_CENTER_SE4C0_9", - "CFG_CENTER_SE4C1_0", - "CFG_CENTER_SE4C1_1", - "CFG_CENTER_SE4C1_10", - "CFG_CENTER_SE4C1_11", - "CFG_CENTER_SE4C1_12", - "CFG_CENTER_SE4C1_13", - "CFG_CENTER_SE4C1_14", - "CFG_CENTER_SE4C1_15", - "CFG_CENTER_SE4C1_16", - "CFG_CENTER_SE4C1_17", - "CFG_CENTER_SE4C1_18", - "CFG_CENTER_SE4C1_19", - "CFG_CENTER_SE4C1_2", - "CFG_CENTER_SE4C1_3", - "CFG_CENTER_SE4C1_4", - "CFG_CENTER_SE4C1_5", - "CFG_CENTER_SE4C1_6", - "CFG_CENTER_SE4C1_7", - "CFG_CENTER_SE4C1_8", - "CFG_CENTER_SE4C1_9", - "CFG_CENTER_SE4C2_0", - "CFG_CENTER_SE4C2_1", - "CFG_CENTER_SE4C2_10", - "CFG_CENTER_SE4C2_11", - "CFG_CENTER_SE4C2_12", - "CFG_CENTER_SE4C2_13", - "CFG_CENTER_SE4C2_14", - "CFG_CENTER_SE4C2_15", - "CFG_CENTER_SE4C2_16", - "CFG_CENTER_SE4C2_17", - "CFG_CENTER_SE4C2_18", - "CFG_CENTER_SE4C2_19", - "CFG_CENTER_SE4C2_2", - "CFG_CENTER_SE4C2_3", - "CFG_CENTER_SE4C2_4", - "CFG_CENTER_SE4C2_5", - "CFG_CENTER_SE4C2_6", - "CFG_CENTER_SE4C2_7", - "CFG_CENTER_SE4C2_8", - "CFG_CENTER_SE4C2_9", - "CFG_CENTER_SE4C3_0", - "CFG_CENTER_SE4C3_1", - "CFG_CENTER_SE4C3_10", - "CFG_CENTER_SE4C3_11", - "CFG_CENTER_SE4C3_12", - "CFG_CENTER_SE4C3_13", - "CFG_CENTER_SE4C3_14", - "CFG_CENTER_SE4C3_15", - "CFG_CENTER_SE4C3_16", - "CFG_CENTER_SE4C3_17", - "CFG_CENTER_SE4C3_18", - "CFG_CENTER_SE4C3_19", - "CFG_CENTER_SE4C3_2", - "CFG_CENTER_SE4C3_3", - "CFG_CENTER_SE4C3_4", - "CFG_CENTER_SE4C3_5", - "CFG_CENTER_SE4C3_6", - "CFG_CENTER_SE4C3_7", - "CFG_CENTER_SE4C3_8", - "CFG_CENTER_SE4C3_9", - "CFG_CENTER_SW2A0_0", - "CFG_CENTER_SW2A0_1", - "CFG_CENTER_SW2A0_10", - "CFG_CENTER_SW2A0_11", - "CFG_CENTER_SW2A0_12", - "CFG_CENTER_SW2A0_13", - "CFG_CENTER_SW2A0_14", - "CFG_CENTER_SW2A0_15", - "CFG_CENTER_SW2A0_16", - "CFG_CENTER_SW2A0_17", - "CFG_CENTER_SW2A0_18", - "CFG_CENTER_SW2A0_19", - "CFG_CENTER_SW2A0_2", - "CFG_CENTER_SW2A0_3", - "CFG_CENTER_SW2A0_4", - "CFG_CENTER_SW2A0_5", - "CFG_CENTER_SW2A0_6", - "CFG_CENTER_SW2A0_7", - "CFG_CENTER_SW2A0_8", - "CFG_CENTER_SW2A0_9", - "CFG_CENTER_SW2A1_0", - "CFG_CENTER_SW2A1_1", - "CFG_CENTER_SW2A1_10", - "CFG_CENTER_SW2A1_11", - "CFG_CENTER_SW2A1_12", - "CFG_CENTER_SW2A1_13", - "CFG_CENTER_SW2A1_14", - "CFG_CENTER_SW2A1_15", - "CFG_CENTER_SW2A1_16", - "CFG_CENTER_SW2A1_17", - "CFG_CENTER_SW2A1_18", - "CFG_CENTER_SW2A1_19", - "CFG_CENTER_SW2A1_2", - "CFG_CENTER_SW2A1_3", - "CFG_CENTER_SW2A1_4", - "CFG_CENTER_SW2A1_5", - "CFG_CENTER_SW2A1_6", - "CFG_CENTER_SW2A1_7", - "CFG_CENTER_SW2A1_8", - "CFG_CENTER_SW2A1_9", - "CFG_CENTER_SW2A2_0", - "CFG_CENTER_SW2A2_1", - "CFG_CENTER_SW2A2_10", - "CFG_CENTER_SW2A2_11", - "CFG_CENTER_SW2A2_12", - "CFG_CENTER_SW2A2_13", - "CFG_CENTER_SW2A2_14", - "CFG_CENTER_SW2A2_15", - "CFG_CENTER_SW2A2_16", - "CFG_CENTER_SW2A2_17", - "CFG_CENTER_SW2A2_18", - "CFG_CENTER_SW2A2_19", - "CFG_CENTER_SW2A2_2", - "CFG_CENTER_SW2A2_3", - "CFG_CENTER_SW2A2_4", - "CFG_CENTER_SW2A2_5", - "CFG_CENTER_SW2A2_6", - "CFG_CENTER_SW2A2_7", - "CFG_CENTER_SW2A2_8", - "CFG_CENTER_SW2A2_9", - "CFG_CENTER_SW2A3_0", - "CFG_CENTER_SW2A3_1", - "CFG_CENTER_SW2A3_10", - "CFG_CENTER_SW2A3_11", - "CFG_CENTER_SW2A3_12", - "CFG_CENTER_SW2A3_13", - "CFG_CENTER_SW2A3_14", - "CFG_CENTER_SW2A3_15", - "CFG_CENTER_SW2A3_16", - "CFG_CENTER_SW2A3_17", - "CFG_CENTER_SW2A3_18", - "CFG_CENTER_SW2A3_19", - "CFG_CENTER_SW2A3_2", - "CFG_CENTER_SW2A3_3", - "CFG_CENTER_SW2A3_4", - "CFG_CENTER_SW2A3_5", - "CFG_CENTER_SW2A3_6", - "CFG_CENTER_SW2A3_7", - "CFG_CENTER_SW2A3_8", - "CFG_CENTER_SW2A3_9", - "CFG_CENTER_SW4A0_0", - "CFG_CENTER_SW4A0_1", - "CFG_CENTER_SW4A0_10", - "CFG_CENTER_SW4A0_11", - "CFG_CENTER_SW4A0_12", - "CFG_CENTER_SW4A0_13", - "CFG_CENTER_SW4A0_14", - "CFG_CENTER_SW4A0_15", - "CFG_CENTER_SW4A0_16", - "CFG_CENTER_SW4A0_17", - "CFG_CENTER_SW4A0_18", - "CFG_CENTER_SW4A0_19", - "CFG_CENTER_SW4A0_2", - "CFG_CENTER_SW4A0_3", - "CFG_CENTER_SW4A0_4", - "CFG_CENTER_SW4A0_5", - "CFG_CENTER_SW4A0_6", - "CFG_CENTER_SW4A0_7", - "CFG_CENTER_SW4A0_8", - "CFG_CENTER_SW4A0_9", - "CFG_CENTER_SW4A1_0", - "CFG_CENTER_SW4A1_1", - "CFG_CENTER_SW4A1_10", - "CFG_CENTER_SW4A1_11", - "CFG_CENTER_SW4A1_12", - "CFG_CENTER_SW4A1_13", - "CFG_CENTER_SW4A1_14", - "CFG_CENTER_SW4A1_15", - "CFG_CENTER_SW4A1_16", - "CFG_CENTER_SW4A1_17", - "CFG_CENTER_SW4A1_18", - "CFG_CENTER_SW4A1_19", - "CFG_CENTER_SW4A1_2", - "CFG_CENTER_SW4A1_3", - "CFG_CENTER_SW4A1_4", - "CFG_CENTER_SW4A1_5", - "CFG_CENTER_SW4A1_6", - "CFG_CENTER_SW4A1_7", - "CFG_CENTER_SW4A1_8", - "CFG_CENTER_SW4A1_9", - "CFG_CENTER_SW4A2_0", - "CFG_CENTER_SW4A2_1", - "CFG_CENTER_SW4A2_10", - "CFG_CENTER_SW4A2_11", - "CFG_CENTER_SW4A2_12", - "CFG_CENTER_SW4A2_13", - "CFG_CENTER_SW4A2_14", - "CFG_CENTER_SW4A2_15", - "CFG_CENTER_SW4A2_16", - "CFG_CENTER_SW4A2_17", - "CFG_CENTER_SW4A2_18", - "CFG_CENTER_SW4A2_19", - "CFG_CENTER_SW4A2_2", - "CFG_CENTER_SW4A2_3", - "CFG_CENTER_SW4A2_4", - "CFG_CENTER_SW4A2_5", - "CFG_CENTER_SW4A2_6", - "CFG_CENTER_SW4A2_7", - "CFG_CENTER_SW4A2_8", - "CFG_CENTER_SW4A2_9", - "CFG_CENTER_SW4A3_0", - "CFG_CENTER_SW4A3_1", - "CFG_CENTER_SW4A3_10", - "CFG_CENTER_SW4A3_11", - "CFG_CENTER_SW4A3_12", - "CFG_CENTER_SW4A3_13", - "CFG_CENTER_SW4A3_14", - "CFG_CENTER_SW4A3_15", - "CFG_CENTER_SW4A3_16", - "CFG_CENTER_SW4A3_17", - "CFG_CENTER_SW4A3_18", - "CFG_CENTER_SW4A3_19", - "CFG_CENTER_SW4A3_2", - "CFG_CENTER_SW4A3_3", - "CFG_CENTER_SW4A3_4", - "CFG_CENTER_SW4A3_5", - "CFG_CENTER_SW4A3_6", - "CFG_CENTER_SW4A3_7", - "CFG_CENTER_SW4A3_8", - "CFG_CENTER_SW4A3_9", - "CFG_CENTER_SW4END0_0", - "CFG_CENTER_SW4END0_1", - "CFG_CENTER_SW4END0_10", - "CFG_CENTER_SW4END0_11", - "CFG_CENTER_SW4END0_12", - "CFG_CENTER_SW4END0_13", - "CFG_CENTER_SW4END0_14", - "CFG_CENTER_SW4END0_15", - "CFG_CENTER_SW4END0_16", - "CFG_CENTER_SW4END0_17", - "CFG_CENTER_SW4END0_18", - "CFG_CENTER_SW4END0_19", - "CFG_CENTER_SW4END0_2", - "CFG_CENTER_SW4END0_3", - "CFG_CENTER_SW4END0_4", - "CFG_CENTER_SW4END0_5", - "CFG_CENTER_SW4END0_6", - "CFG_CENTER_SW4END0_7", - "CFG_CENTER_SW4END0_8", - "CFG_CENTER_SW4END0_9", - "CFG_CENTER_SW4END1_0", - "CFG_CENTER_SW4END1_1", - "CFG_CENTER_SW4END1_10", - "CFG_CENTER_SW4END1_11", - "CFG_CENTER_SW4END1_12", - "CFG_CENTER_SW4END1_13", - "CFG_CENTER_SW4END1_14", - "CFG_CENTER_SW4END1_15", - "CFG_CENTER_SW4END1_16", - "CFG_CENTER_SW4END1_17", - "CFG_CENTER_SW4END1_18", - "CFG_CENTER_SW4END1_19", - "CFG_CENTER_SW4END1_2", - "CFG_CENTER_SW4END1_3", - "CFG_CENTER_SW4END1_4", - "CFG_CENTER_SW4END1_5", - "CFG_CENTER_SW4END1_6", - "CFG_CENTER_SW4END1_7", - "CFG_CENTER_SW4END1_8", - "CFG_CENTER_SW4END1_9", - "CFG_CENTER_SW4END2_0", - "CFG_CENTER_SW4END2_1", - "CFG_CENTER_SW4END2_10", - "CFG_CENTER_SW4END2_11", - "CFG_CENTER_SW4END2_12", - "CFG_CENTER_SW4END2_13", - "CFG_CENTER_SW4END2_14", - "CFG_CENTER_SW4END2_15", - "CFG_CENTER_SW4END2_16", - "CFG_CENTER_SW4END2_17", - "CFG_CENTER_SW4END2_18", - "CFG_CENTER_SW4END2_19", - "CFG_CENTER_SW4END2_2", - "CFG_CENTER_SW4END2_3", - "CFG_CENTER_SW4END2_4", - "CFG_CENTER_SW4END2_5", - "CFG_CENTER_SW4END2_6", - "CFG_CENTER_SW4END2_7", - "CFG_CENTER_SW4END2_8", - "CFG_CENTER_SW4END2_9", - "CFG_CENTER_SW4END3_0", - "CFG_CENTER_SW4END3_1", - "CFG_CENTER_SW4END3_10", - "CFG_CENTER_SW4END3_11", - "CFG_CENTER_SW4END3_12", - "CFG_CENTER_SW4END3_13", - "CFG_CENTER_SW4END3_14", - "CFG_CENTER_SW4END3_15", - "CFG_CENTER_SW4END3_16", - "CFG_CENTER_SW4END3_17", - "CFG_CENTER_SW4END3_18", - "CFG_CENTER_SW4END3_19", - "CFG_CENTER_SW4END3_2", - "CFG_CENTER_SW4END3_3", - "CFG_CENTER_SW4END3_4", - "CFG_CENTER_SW4END3_5", - "CFG_CENTER_SW4END3_6", - "CFG_CENTER_SW4END3_7", - "CFG_CENTER_SW4END3_8", - "CFG_CENTER_SW4END3_9", - "CFG_CENTER_WL1END0_0", - "CFG_CENTER_WL1END0_1", - "CFG_CENTER_WL1END0_10", - "CFG_CENTER_WL1END0_11", - "CFG_CENTER_WL1END0_12", - "CFG_CENTER_WL1END0_13", - "CFG_CENTER_WL1END0_14", - "CFG_CENTER_WL1END0_15", - "CFG_CENTER_WL1END0_16", - "CFG_CENTER_WL1END0_17", - "CFG_CENTER_WL1END0_18", - "CFG_CENTER_WL1END0_19", - "CFG_CENTER_WL1END0_2", - "CFG_CENTER_WL1END0_3", - "CFG_CENTER_WL1END0_4", - "CFG_CENTER_WL1END0_5", - "CFG_CENTER_WL1END0_6", - "CFG_CENTER_WL1END0_7", - "CFG_CENTER_WL1END0_8", - "CFG_CENTER_WL1END0_9", - "CFG_CENTER_WL1END1_0", - "CFG_CENTER_WL1END1_1", - "CFG_CENTER_WL1END1_10", - "CFG_CENTER_WL1END1_11", - "CFG_CENTER_WL1END1_12", - "CFG_CENTER_WL1END1_13", - "CFG_CENTER_WL1END1_14", - "CFG_CENTER_WL1END1_15", - "CFG_CENTER_WL1END1_16", - "CFG_CENTER_WL1END1_17", - "CFG_CENTER_WL1END1_18", - "CFG_CENTER_WL1END1_19", - "CFG_CENTER_WL1END1_2", - "CFG_CENTER_WL1END1_3", - "CFG_CENTER_WL1END1_4", - "CFG_CENTER_WL1END1_5", - "CFG_CENTER_WL1END1_6", - "CFG_CENTER_WL1END1_7", - "CFG_CENTER_WL1END1_8", - "CFG_CENTER_WL1END1_9", - "CFG_CENTER_WL1END2_0", - "CFG_CENTER_WL1END2_1", - "CFG_CENTER_WL1END2_10", - "CFG_CENTER_WL1END2_11", - "CFG_CENTER_WL1END2_12", - "CFG_CENTER_WL1END2_13", - "CFG_CENTER_WL1END2_14", - "CFG_CENTER_WL1END2_15", - "CFG_CENTER_WL1END2_16", - "CFG_CENTER_WL1END2_17", - "CFG_CENTER_WL1END2_18", - "CFG_CENTER_WL1END2_19", - "CFG_CENTER_WL1END2_2", - "CFG_CENTER_WL1END2_3", - "CFG_CENTER_WL1END2_4", - "CFG_CENTER_WL1END2_5", - "CFG_CENTER_WL1END2_6", - "CFG_CENTER_WL1END2_7", - "CFG_CENTER_WL1END2_8", - "CFG_CENTER_WL1END2_9", - "CFG_CENTER_WL1END3_0", - "CFG_CENTER_WL1END3_1", - "CFG_CENTER_WL1END3_10", - "CFG_CENTER_WL1END3_11", - "CFG_CENTER_WL1END3_12", - "CFG_CENTER_WL1END3_13", - "CFG_CENTER_WL1END3_14", - "CFG_CENTER_WL1END3_15", - "CFG_CENTER_WL1END3_16", - "CFG_CENTER_WL1END3_17", - "CFG_CENTER_WL1END3_18", - "CFG_CENTER_WL1END3_19", - "CFG_CENTER_WL1END3_2", - "CFG_CENTER_WL1END3_3", - "CFG_CENTER_WL1END3_4", - "CFG_CENTER_WL1END3_5", - "CFG_CENTER_WL1END3_6", - "CFG_CENTER_WL1END3_7", - "CFG_CENTER_WL1END3_8", - "CFG_CENTER_WL1END3_9", - "CFG_CENTER_WR1END0_0", - "CFG_CENTER_WR1END0_1", - "CFG_CENTER_WR1END0_10", - "CFG_CENTER_WR1END0_11", - "CFG_CENTER_WR1END0_12", - "CFG_CENTER_WR1END0_13", - "CFG_CENTER_WR1END0_14", - "CFG_CENTER_WR1END0_15", - "CFG_CENTER_WR1END0_16", - "CFG_CENTER_WR1END0_17", - "CFG_CENTER_WR1END0_18", - "CFG_CENTER_WR1END0_19", - "CFG_CENTER_WR1END0_2", - "CFG_CENTER_WR1END0_3", - "CFG_CENTER_WR1END0_4", - "CFG_CENTER_WR1END0_5", - "CFG_CENTER_WR1END0_6", - "CFG_CENTER_WR1END0_7", - "CFG_CENTER_WR1END0_8", - "CFG_CENTER_WR1END0_9", - "CFG_CENTER_WR1END1_0", - "CFG_CENTER_WR1END1_1", - "CFG_CENTER_WR1END1_10", - "CFG_CENTER_WR1END1_11", - "CFG_CENTER_WR1END1_12", - "CFG_CENTER_WR1END1_13", - "CFG_CENTER_WR1END1_14", - "CFG_CENTER_WR1END1_15", - "CFG_CENTER_WR1END1_16", - "CFG_CENTER_WR1END1_17", - "CFG_CENTER_WR1END1_18", - "CFG_CENTER_WR1END1_19", - "CFG_CENTER_WR1END1_2", - "CFG_CENTER_WR1END1_3", - "CFG_CENTER_WR1END1_4", - "CFG_CENTER_WR1END1_5", - "CFG_CENTER_WR1END1_6", - "CFG_CENTER_WR1END1_7", - "CFG_CENTER_WR1END1_8", - "CFG_CENTER_WR1END1_9", - "CFG_CENTER_WR1END2_0", - "CFG_CENTER_WR1END2_1", - "CFG_CENTER_WR1END2_10", - "CFG_CENTER_WR1END2_11", - "CFG_CENTER_WR1END2_12", - "CFG_CENTER_WR1END2_13", - "CFG_CENTER_WR1END2_14", - "CFG_CENTER_WR1END2_15", - "CFG_CENTER_WR1END2_16", - "CFG_CENTER_WR1END2_17", - "CFG_CENTER_WR1END2_18", - "CFG_CENTER_WR1END2_19", - "CFG_CENTER_WR1END2_2", - "CFG_CENTER_WR1END2_3", - "CFG_CENTER_WR1END2_4", - "CFG_CENTER_WR1END2_5", - "CFG_CENTER_WR1END2_6", - "CFG_CENTER_WR1END2_7", - "CFG_CENTER_WR1END2_8", - "CFG_CENTER_WR1END2_9", - "CFG_CENTER_WR1END3_0", - "CFG_CENTER_WR1END3_1", - "CFG_CENTER_WR1END3_10", - "CFG_CENTER_WR1END3_11", - "CFG_CENTER_WR1END3_12", - "CFG_CENTER_WR1END3_13", - "CFG_CENTER_WR1END3_14", - "CFG_CENTER_WR1END3_15", - "CFG_CENTER_WR1END3_16", - "CFG_CENTER_WR1END3_17", - "CFG_CENTER_WR1END3_18", - "CFG_CENTER_WR1END3_19", - "CFG_CENTER_WR1END3_2", - "CFG_CENTER_WR1END3_3", - "CFG_CENTER_WR1END3_4", - "CFG_CENTER_WR1END3_5", - "CFG_CENTER_WR1END3_6", - "CFG_CENTER_WR1END3_7", - "CFG_CENTER_WR1END3_8", - "CFG_CENTER_WR1END3_9", - "CFG_CENTER_WW2A0_0", - "CFG_CENTER_WW2A0_1", - "CFG_CENTER_WW2A0_10", - "CFG_CENTER_WW2A0_11", - "CFG_CENTER_WW2A0_12", - "CFG_CENTER_WW2A0_13", - "CFG_CENTER_WW2A0_14", - "CFG_CENTER_WW2A0_15", - "CFG_CENTER_WW2A0_16", - "CFG_CENTER_WW2A0_17", - "CFG_CENTER_WW2A0_18", - "CFG_CENTER_WW2A0_19", - "CFG_CENTER_WW2A0_2", - "CFG_CENTER_WW2A0_3", - "CFG_CENTER_WW2A0_4", - "CFG_CENTER_WW2A0_5", - "CFG_CENTER_WW2A0_6", - "CFG_CENTER_WW2A0_7", - "CFG_CENTER_WW2A0_8", - "CFG_CENTER_WW2A0_9", - "CFG_CENTER_WW2A1_0", - "CFG_CENTER_WW2A1_1", - "CFG_CENTER_WW2A1_10", - "CFG_CENTER_WW2A1_11", - "CFG_CENTER_WW2A1_12", - "CFG_CENTER_WW2A1_13", - "CFG_CENTER_WW2A1_14", - "CFG_CENTER_WW2A1_15", - "CFG_CENTER_WW2A1_16", - "CFG_CENTER_WW2A1_17", - "CFG_CENTER_WW2A1_18", - "CFG_CENTER_WW2A1_19", - "CFG_CENTER_WW2A1_2", - "CFG_CENTER_WW2A1_3", - "CFG_CENTER_WW2A1_4", - "CFG_CENTER_WW2A1_5", - "CFG_CENTER_WW2A1_6", - "CFG_CENTER_WW2A1_7", - "CFG_CENTER_WW2A1_8", - "CFG_CENTER_WW2A1_9", - "CFG_CENTER_WW2A2_0", - "CFG_CENTER_WW2A2_1", - "CFG_CENTER_WW2A2_10", - "CFG_CENTER_WW2A2_11", - "CFG_CENTER_WW2A2_12", - "CFG_CENTER_WW2A2_13", - "CFG_CENTER_WW2A2_14", - "CFG_CENTER_WW2A2_15", - "CFG_CENTER_WW2A2_16", - "CFG_CENTER_WW2A2_17", - "CFG_CENTER_WW2A2_18", - "CFG_CENTER_WW2A2_19", - "CFG_CENTER_WW2A2_2", - "CFG_CENTER_WW2A2_3", - "CFG_CENTER_WW2A2_4", - "CFG_CENTER_WW2A2_5", - "CFG_CENTER_WW2A2_6", - "CFG_CENTER_WW2A2_7", - "CFG_CENTER_WW2A2_8", - "CFG_CENTER_WW2A2_9", - "CFG_CENTER_WW2A3_0", - "CFG_CENTER_WW2A3_1", - "CFG_CENTER_WW2A3_10", - "CFG_CENTER_WW2A3_11", - "CFG_CENTER_WW2A3_12", - "CFG_CENTER_WW2A3_13", - "CFG_CENTER_WW2A3_14", - "CFG_CENTER_WW2A3_15", - "CFG_CENTER_WW2A3_16", - "CFG_CENTER_WW2A3_17", - "CFG_CENTER_WW2A3_18", - "CFG_CENTER_WW2A3_19", - "CFG_CENTER_WW2A3_2", - "CFG_CENTER_WW2A3_3", - "CFG_CENTER_WW2A3_4", - "CFG_CENTER_WW2A3_5", - "CFG_CENTER_WW2A3_6", - "CFG_CENTER_WW2A3_7", - "CFG_CENTER_WW2A3_8", - "CFG_CENTER_WW2A3_9", - "CFG_CENTER_WW2END0_0", - "CFG_CENTER_WW2END0_1", - "CFG_CENTER_WW2END0_10", - "CFG_CENTER_WW2END0_11", - "CFG_CENTER_WW2END0_12", - "CFG_CENTER_WW2END0_13", - "CFG_CENTER_WW2END0_14", - "CFG_CENTER_WW2END0_15", - "CFG_CENTER_WW2END0_16", - "CFG_CENTER_WW2END0_17", - "CFG_CENTER_WW2END0_18", - "CFG_CENTER_WW2END0_19", - "CFG_CENTER_WW2END0_2", - "CFG_CENTER_WW2END0_3", - "CFG_CENTER_WW2END0_4", - "CFG_CENTER_WW2END0_5", - "CFG_CENTER_WW2END0_6", - "CFG_CENTER_WW2END0_7", - "CFG_CENTER_WW2END0_8", - "CFG_CENTER_WW2END0_9", - "CFG_CENTER_WW2END1_0", - "CFG_CENTER_WW2END1_1", - "CFG_CENTER_WW2END1_10", - "CFG_CENTER_WW2END1_11", - "CFG_CENTER_WW2END1_12", - "CFG_CENTER_WW2END1_13", - "CFG_CENTER_WW2END1_14", - "CFG_CENTER_WW2END1_15", - "CFG_CENTER_WW2END1_16", - "CFG_CENTER_WW2END1_17", - "CFG_CENTER_WW2END1_18", - "CFG_CENTER_WW2END1_19", - "CFG_CENTER_WW2END1_2", - "CFG_CENTER_WW2END1_3", - "CFG_CENTER_WW2END1_4", - "CFG_CENTER_WW2END1_5", - "CFG_CENTER_WW2END1_6", - "CFG_CENTER_WW2END1_7", - "CFG_CENTER_WW2END1_8", - "CFG_CENTER_WW2END1_9", - "CFG_CENTER_WW2END2_0", - "CFG_CENTER_WW2END2_1", - "CFG_CENTER_WW2END2_10", - "CFG_CENTER_WW2END2_11", - "CFG_CENTER_WW2END2_12", - "CFG_CENTER_WW2END2_13", - "CFG_CENTER_WW2END2_14", - "CFG_CENTER_WW2END2_15", - "CFG_CENTER_WW2END2_16", - "CFG_CENTER_WW2END2_17", - "CFG_CENTER_WW2END2_18", - "CFG_CENTER_WW2END2_19", - "CFG_CENTER_WW2END2_2", - "CFG_CENTER_WW2END2_3", - "CFG_CENTER_WW2END2_4", - "CFG_CENTER_WW2END2_5", - "CFG_CENTER_WW2END2_6", - "CFG_CENTER_WW2END2_7", - "CFG_CENTER_WW2END2_8", - "CFG_CENTER_WW2END2_9", - "CFG_CENTER_WW2END3_0", - "CFG_CENTER_WW2END3_1", - "CFG_CENTER_WW2END3_10", - "CFG_CENTER_WW2END3_11", - "CFG_CENTER_WW2END3_12", - "CFG_CENTER_WW2END3_13", - "CFG_CENTER_WW2END3_14", - "CFG_CENTER_WW2END3_15", - "CFG_CENTER_WW2END3_16", - "CFG_CENTER_WW2END3_17", - "CFG_CENTER_WW2END3_18", - "CFG_CENTER_WW2END3_19", - "CFG_CENTER_WW2END3_2", - "CFG_CENTER_WW2END3_3", - "CFG_CENTER_WW2END3_4", - "CFG_CENTER_WW2END3_5", - "CFG_CENTER_WW2END3_6", - "CFG_CENTER_WW2END3_7", - "CFG_CENTER_WW2END3_8", - "CFG_CENTER_WW2END3_9", - "CFG_CENTER_WW4A0_0", - "CFG_CENTER_WW4A0_1", - "CFG_CENTER_WW4A0_10", - "CFG_CENTER_WW4A0_11", - "CFG_CENTER_WW4A0_12", - "CFG_CENTER_WW4A0_13", - "CFG_CENTER_WW4A0_14", - "CFG_CENTER_WW4A0_15", - "CFG_CENTER_WW4A0_16", - "CFG_CENTER_WW4A0_17", - "CFG_CENTER_WW4A0_18", - "CFG_CENTER_WW4A0_19", - "CFG_CENTER_WW4A0_2", - "CFG_CENTER_WW4A0_3", - "CFG_CENTER_WW4A0_4", - "CFG_CENTER_WW4A0_5", - "CFG_CENTER_WW4A0_6", - "CFG_CENTER_WW4A0_7", - "CFG_CENTER_WW4A0_8", - "CFG_CENTER_WW4A0_9", - "CFG_CENTER_WW4A1_0", - "CFG_CENTER_WW4A1_1", - "CFG_CENTER_WW4A1_10", - "CFG_CENTER_WW4A1_11", - "CFG_CENTER_WW4A1_12", - "CFG_CENTER_WW4A1_13", - "CFG_CENTER_WW4A1_14", - "CFG_CENTER_WW4A1_15", - "CFG_CENTER_WW4A1_16", - "CFG_CENTER_WW4A1_17", - "CFG_CENTER_WW4A1_18", - "CFG_CENTER_WW4A1_19", - "CFG_CENTER_WW4A1_2", - "CFG_CENTER_WW4A1_3", - "CFG_CENTER_WW4A1_4", - "CFG_CENTER_WW4A1_5", - "CFG_CENTER_WW4A1_6", - "CFG_CENTER_WW4A1_7", - "CFG_CENTER_WW4A1_8", - "CFG_CENTER_WW4A1_9", - "CFG_CENTER_WW4A2_0", - "CFG_CENTER_WW4A2_1", - "CFG_CENTER_WW4A2_10", - "CFG_CENTER_WW4A2_11", - "CFG_CENTER_WW4A2_12", - "CFG_CENTER_WW4A2_13", - "CFG_CENTER_WW4A2_14", - "CFG_CENTER_WW4A2_15", - "CFG_CENTER_WW4A2_16", - "CFG_CENTER_WW4A2_17", - "CFG_CENTER_WW4A2_18", - "CFG_CENTER_WW4A2_19", - "CFG_CENTER_WW4A2_2", - "CFG_CENTER_WW4A2_3", - "CFG_CENTER_WW4A2_4", - "CFG_CENTER_WW4A2_5", - "CFG_CENTER_WW4A2_6", - "CFG_CENTER_WW4A2_7", - "CFG_CENTER_WW4A2_8", - "CFG_CENTER_WW4A2_9", - "CFG_CENTER_WW4A3_0", - "CFG_CENTER_WW4A3_1", - "CFG_CENTER_WW4A3_10", - "CFG_CENTER_WW4A3_11", - "CFG_CENTER_WW4A3_12", - "CFG_CENTER_WW4A3_13", - "CFG_CENTER_WW4A3_14", - "CFG_CENTER_WW4A3_15", - "CFG_CENTER_WW4A3_16", - "CFG_CENTER_WW4A3_17", - "CFG_CENTER_WW4A3_18", - "CFG_CENTER_WW4A3_19", - "CFG_CENTER_WW4A3_2", - "CFG_CENTER_WW4A3_3", - "CFG_CENTER_WW4A3_4", - "CFG_CENTER_WW4A3_5", - "CFG_CENTER_WW4A3_6", - "CFG_CENTER_WW4A3_7", - "CFG_CENTER_WW4A3_8", - "CFG_CENTER_WW4A3_9", - "CFG_CENTER_WW4B0_0", - "CFG_CENTER_WW4B0_1", - "CFG_CENTER_WW4B0_10", - "CFG_CENTER_WW4B0_11", - "CFG_CENTER_WW4B0_12", - "CFG_CENTER_WW4B0_13", - "CFG_CENTER_WW4B0_14", - "CFG_CENTER_WW4B0_15", - "CFG_CENTER_WW4B0_16", - "CFG_CENTER_WW4B0_17", - "CFG_CENTER_WW4B0_18", - "CFG_CENTER_WW4B0_19", - "CFG_CENTER_WW4B0_2", - "CFG_CENTER_WW4B0_3", - "CFG_CENTER_WW4B0_4", - "CFG_CENTER_WW4B0_5", - "CFG_CENTER_WW4B0_6", - "CFG_CENTER_WW4B0_7", - "CFG_CENTER_WW4B0_8", - "CFG_CENTER_WW4B0_9", - "CFG_CENTER_WW4B1_0", - "CFG_CENTER_WW4B1_1", - "CFG_CENTER_WW4B1_10", - "CFG_CENTER_WW4B1_11", - "CFG_CENTER_WW4B1_12", - "CFG_CENTER_WW4B1_13", - "CFG_CENTER_WW4B1_14", - "CFG_CENTER_WW4B1_15", - "CFG_CENTER_WW4B1_16", - "CFG_CENTER_WW4B1_17", - "CFG_CENTER_WW4B1_18", - "CFG_CENTER_WW4B1_19", - "CFG_CENTER_WW4B1_2", - "CFG_CENTER_WW4B1_3", - "CFG_CENTER_WW4B1_4", - "CFG_CENTER_WW4B1_5", - "CFG_CENTER_WW4B1_6", - "CFG_CENTER_WW4B1_7", - "CFG_CENTER_WW4B1_8", - "CFG_CENTER_WW4B1_9", - "CFG_CENTER_WW4B2_0", - "CFG_CENTER_WW4B2_1", - "CFG_CENTER_WW4B2_10", - "CFG_CENTER_WW4B2_11", - "CFG_CENTER_WW4B2_12", - "CFG_CENTER_WW4B2_13", - "CFG_CENTER_WW4B2_14", - "CFG_CENTER_WW4B2_15", - "CFG_CENTER_WW4B2_16", - "CFG_CENTER_WW4B2_17", - "CFG_CENTER_WW4B2_18", - "CFG_CENTER_WW4B2_19", - "CFG_CENTER_WW4B2_2", - "CFG_CENTER_WW4B2_3", - "CFG_CENTER_WW4B2_4", - "CFG_CENTER_WW4B2_5", - "CFG_CENTER_WW4B2_6", - "CFG_CENTER_WW4B2_7", - "CFG_CENTER_WW4B2_8", - "CFG_CENTER_WW4B2_9", - "CFG_CENTER_WW4B3_0", - "CFG_CENTER_WW4B3_1", - "CFG_CENTER_WW4B3_10", - "CFG_CENTER_WW4B3_11", - "CFG_CENTER_WW4B3_12", - "CFG_CENTER_WW4B3_13", - "CFG_CENTER_WW4B3_14", - "CFG_CENTER_WW4B3_15", - "CFG_CENTER_WW4B3_16", - "CFG_CENTER_WW4B3_17", - "CFG_CENTER_WW4B3_18", - "CFG_CENTER_WW4B3_19", - "CFG_CENTER_WW4B3_2", - "CFG_CENTER_WW4B3_3", - "CFG_CENTER_WW4B3_4", - "CFG_CENTER_WW4B3_5", - "CFG_CENTER_WW4B3_6", - "CFG_CENTER_WW4B3_7", - "CFG_CENTER_WW4B3_8", - "CFG_CENTER_WW4B3_9", - "CFG_CENTER_WW4C0_0", - "CFG_CENTER_WW4C0_1", - "CFG_CENTER_WW4C0_10", - "CFG_CENTER_WW4C0_11", - "CFG_CENTER_WW4C0_12", - "CFG_CENTER_WW4C0_13", - "CFG_CENTER_WW4C0_14", - "CFG_CENTER_WW4C0_15", - "CFG_CENTER_WW4C0_16", - "CFG_CENTER_WW4C0_17", - "CFG_CENTER_WW4C0_18", - "CFG_CENTER_WW4C0_19", - "CFG_CENTER_WW4C0_2", - "CFG_CENTER_WW4C0_3", - "CFG_CENTER_WW4C0_4", - "CFG_CENTER_WW4C0_5", - "CFG_CENTER_WW4C0_6", - "CFG_CENTER_WW4C0_7", - "CFG_CENTER_WW4C0_8", - "CFG_CENTER_WW4C0_9", - "CFG_CENTER_WW4C1_0", - "CFG_CENTER_WW4C1_1", - "CFG_CENTER_WW4C1_10", - "CFG_CENTER_WW4C1_11", - "CFG_CENTER_WW4C1_12", - "CFG_CENTER_WW4C1_13", - "CFG_CENTER_WW4C1_14", - "CFG_CENTER_WW4C1_15", - "CFG_CENTER_WW4C1_16", - "CFG_CENTER_WW4C1_17", - "CFG_CENTER_WW4C1_18", - "CFG_CENTER_WW4C1_19", - "CFG_CENTER_WW4C1_2", - "CFG_CENTER_WW4C1_3", - "CFG_CENTER_WW4C1_4", - "CFG_CENTER_WW4C1_5", - "CFG_CENTER_WW4C1_6", - "CFG_CENTER_WW4C1_7", - "CFG_CENTER_WW4C1_8", - "CFG_CENTER_WW4C1_9", - "CFG_CENTER_WW4C2_0", - "CFG_CENTER_WW4C2_1", - "CFG_CENTER_WW4C2_10", - "CFG_CENTER_WW4C2_11", - "CFG_CENTER_WW4C2_12", - "CFG_CENTER_WW4C2_13", - "CFG_CENTER_WW4C2_14", - "CFG_CENTER_WW4C2_15", - "CFG_CENTER_WW4C2_16", - "CFG_CENTER_WW4C2_17", - "CFG_CENTER_WW4C2_18", - "CFG_CENTER_WW4C2_19", - "CFG_CENTER_WW4C2_2", - "CFG_CENTER_WW4C2_3", - "CFG_CENTER_WW4C2_4", - "CFG_CENTER_WW4C2_5", - "CFG_CENTER_WW4C2_6", - "CFG_CENTER_WW4C2_7", - "CFG_CENTER_WW4C2_8", - "CFG_CENTER_WW4C2_9", - "CFG_CENTER_WW4C3_0", - "CFG_CENTER_WW4C3_1", - "CFG_CENTER_WW4C3_10", - "CFG_CENTER_WW4C3_11", - "CFG_CENTER_WW4C3_12", - "CFG_CENTER_WW4C3_13", - "CFG_CENTER_WW4C3_14", - "CFG_CENTER_WW4C3_15", - "CFG_CENTER_WW4C3_16", - "CFG_CENTER_WW4C3_17", - "CFG_CENTER_WW4C3_18", - "CFG_CENTER_WW4C3_19", - "CFG_CENTER_WW4C3_2", - "CFG_CENTER_WW4C3_3", - "CFG_CENTER_WW4C3_4", - "CFG_CENTER_WW4C3_5", - "CFG_CENTER_WW4C3_6", - "CFG_CENTER_WW4C3_7", - "CFG_CENTER_WW4C3_8", - "CFG_CENTER_WW4C3_9", - "CFG_CENTER_WW4END0_0", - "CFG_CENTER_WW4END0_1", - "CFG_CENTER_WW4END0_10", - "CFG_CENTER_WW4END0_11", - "CFG_CENTER_WW4END0_12", - "CFG_CENTER_WW4END0_13", - "CFG_CENTER_WW4END0_14", - "CFG_CENTER_WW4END0_15", - "CFG_CENTER_WW4END0_16", - "CFG_CENTER_WW4END0_17", - "CFG_CENTER_WW4END0_18", - "CFG_CENTER_WW4END0_19", - "CFG_CENTER_WW4END0_2", - "CFG_CENTER_WW4END0_3", - "CFG_CENTER_WW4END0_4", - "CFG_CENTER_WW4END0_5", - "CFG_CENTER_WW4END0_6", - "CFG_CENTER_WW4END0_7", - "CFG_CENTER_WW4END0_8", - "CFG_CENTER_WW4END0_9", - "CFG_CENTER_WW4END1_0", - "CFG_CENTER_WW4END1_1", - "CFG_CENTER_WW4END1_10", - "CFG_CENTER_WW4END1_11", - "CFG_CENTER_WW4END1_12", - "CFG_CENTER_WW4END1_13", - "CFG_CENTER_WW4END1_14", - "CFG_CENTER_WW4END1_15", - "CFG_CENTER_WW4END1_16", - "CFG_CENTER_WW4END1_17", - "CFG_CENTER_WW4END1_18", - "CFG_CENTER_WW4END1_19", - "CFG_CENTER_WW4END1_2", - "CFG_CENTER_WW4END1_3", - "CFG_CENTER_WW4END1_4", - "CFG_CENTER_WW4END1_5", - "CFG_CENTER_WW4END1_6", - "CFG_CENTER_WW4END1_7", - "CFG_CENTER_WW4END1_8", - "CFG_CENTER_WW4END1_9", - "CFG_CENTER_WW4END2_0", - "CFG_CENTER_WW4END2_1", - "CFG_CENTER_WW4END2_10", - "CFG_CENTER_WW4END2_11", - "CFG_CENTER_WW4END2_12", - "CFG_CENTER_WW4END2_13", - "CFG_CENTER_WW4END2_14", - "CFG_CENTER_WW4END2_15", - "CFG_CENTER_WW4END2_16", - "CFG_CENTER_WW4END2_17", - "CFG_CENTER_WW4END2_18", - "CFG_CENTER_WW4END2_19", - "CFG_CENTER_WW4END2_2", - "CFG_CENTER_WW4END2_3", - "CFG_CENTER_WW4END2_4", - "CFG_CENTER_WW4END2_5", - "CFG_CENTER_WW4END2_6", - "CFG_CENTER_WW4END2_7", - "CFG_CENTER_WW4END2_8", - "CFG_CENTER_WW4END2_9", - "CFG_CENTER_WW4END3_0", - "CFG_CENTER_WW4END3_1", - "CFG_CENTER_WW4END3_10", - "CFG_CENTER_WW4END3_11", - "CFG_CENTER_WW4END3_12", - "CFG_CENTER_WW4END3_13", - "CFG_CENTER_WW4END3_14", - "CFG_CENTER_WW4END3_15", - "CFG_CENTER_WW4END3_16", - "CFG_CENTER_WW4END3_17", - "CFG_CENTER_WW4END3_18", - "CFG_CENTER_WW4END3_19", - "CFG_CENTER_WW4END3_2", - "CFG_CENTER_WW4END3_3", - "CFG_CENTER_WW4END3_4", - "CFG_CENTER_WW4END3_5", - "CFG_CENTER_WW4END3_6", - "CFG_CENTER_WW4END3_7", - "CFG_CENTER_WW4END3_8", - "CFG_CENTER_WW4END3_9" - ] + "wires": { + "CFG_CENTER_BLOCK_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_5": { + "cap": "1.111", + "res": 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"CFG_CENTER_BLOCK_OUTS_B2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BOT_CFG_IO_ACCESS_VGGCOMPOUT": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA10": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA11": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA12": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA13": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA14": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA2": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA3": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA4": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA5": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA6": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA7": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA8": null, + "CFG_CENTER_BOT_USR_ACCESS_DATA9": null, + "CFG_CENTER_BYP0_0": null, + "CFG_CENTER_BYP0_1": null, + "CFG_CENTER_BYP0_10": null, + "CFG_CENTER_BYP0_11": null, + "CFG_CENTER_BYP0_12": null, + "CFG_CENTER_BYP0_13": null, + "CFG_CENTER_BYP0_14": null, + "CFG_CENTER_BYP0_15": null, + "CFG_CENTER_BYP0_16": null, + "CFG_CENTER_BYP0_17": null, + "CFG_CENTER_BYP0_18": null, + "CFG_CENTER_BYP0_19": null, + "CFG_CENTER_BYP0_2": null, + "CFG_CENTER_BYP0_3": null, + "CFG_CENTER_BYP0_4": null, + "CFG_CENTER_BYP0_5": null, + "CFG_CENTER_BYP0_6": null, + "CFG_CENTER_BYP0_7": null, + "CFG_CENTER_BYP0_8": null, + "CFG_CENTER_BYP0_9": null, + "CFG_CENTER_BYP1_0": null, + "CFG_CENTER_BYP1_1": null, + "CFG_CENTER_BYP1_10": null, + "CFG_CENTER_BYP1_11": null, + "CFG_CENTER_BYP1_12": null, + "CFG_CENTER_BYP1_13": null, + "CFG_CENTER_BYP1_14": null, + "CFG_CENTER_BYP1_15": null, + "CFG_CENTER_BYP1_16": null, + "CFG_CENTER_BYP1_17": null, + "CFG_CENTER_BYP1_18": null, + "CFG_CENTER_BYP1_19": null, + "CFG_CENTER_BYP1_2": null, + "CFG_CENTER_BYP1_3": null, + "CFG_CENTER_BYP1_4": null, + "CFG_CENTER_BYP1_5": null, + "CFG_CENTER_BYP1_6": null, + "CFG_CENTER_BYP1_7": null, + "CFG_CENTER_BYP1_8": null, + "CFG_CENTER_BYP1_9": null, + "CFG_CENTER_BYP2_0": null, + "CFG_CENTER_BYP2_1": null, + "CFG_CENTER_BYP2_10": null, + "CFG_CENTER_BYP2_11": null, + "CFG_CENTER_BYP2_12": null, + "CFG_CENTER_BYP2_13": null, + "CFG_CENTER_BYP2_14": null, + "CFG_CENTER_BYP2_15": null, + "CFG_CENTER_BYP2_16": null, + "CFG_CENTER_BYP2_17": null, + "CFG_CENTER_BYP2_18": null, + "CFG_CENTER_BYP2_19": null, + "CFG_CENTER_BYP2_2": null, + "CFG_CENTER_BYP2_3": null, + "CFG_CENTER_BYP2_4": null, + "CFG_CENTER_BYP2_5": null, + "CFG_CENTER_BYP2_6": null, + "CFG_CENTER_BYP2_7": null, + "CFG_CENTER_BYP2_8": null, + "CFG_CENTER_BYP2_9": null, + "CFG_CENTER_BYP3_0": null, + "CFG_CENTER_BYP3_1": null, + "CFG_CENTER_BYP3_10": null, + "CFG_CENTER_BYP3_11": null, + "CFG_CENTER_BYP3_12": null, + "CFG_CENTER_BYP3_13": null, + "CFG_CENTER_BYP3_14": null, + "CFG_CENTER_BYP3_15": null, + "CFG_CENTER_BYP3_16": null, + "CFG_CENTER_BYP3_17": null, + "CFG_CENTER_BYP3_18": null, + "CFG_CENTER_BYP3_19": null, + "CFG_CENTER_BYP3_2": null, + "CFG_CENTER_BYP3_3": null, + "CFG_CENTER_BYP3_4": null, + "CFG_CENTER_BYP3_5": null, + "CFG_CENTER_BYP3_6": null, + "CFG_CENTER_BYP3_7": null, + "CFG_CENTER_BYP3_8": null, + "CFG_CENTER_BYP3_9": null, + "CFG_CENTER_BYP4_0": null, + "CFG_CENTER_BYP4_1": null, + "CFG_CENTER_BYP4_10": null, + "CFG_CENTER_BYP4_11": null, + "CFG_CENTER_BYP4_12": null, + "CFG_CENTER_BYP4_13": null, + "CFG_CENTER_BYP4_14": null, + "CFG_CENTER_BYP4_15": null, + "CFG_CENTER_BYP4_16": null, + "CFG_CENTER_BYP4_17": null, + "CFG_CENTER_BYP4_18": null, + "CFG_CENTER_BYP4_19": null, + "CFG_CENTER_BYP4_2": null, + "CFG_CENTER_BYP4_3": null, + "CFG_CENTER_BYP4_4": null, + "CFG_CENTER_BYP4_5": null, + "CFG_CENTER_BYP4_6": null, + "CFG_CENTER_BYP4_7": null, + "CFG_CENTER_BYP4_8": null, + "CFG_CENTER_BYP4_9": null, + "CFG_CENTER_BYP5_0": null, + "CFG_CENTER_BYP5_1": null, + "CFG_CENTER_BYP5_10": null, + "CFG_CENTER_BYP5_11": null, + "CFG_CENTER_BYP5_12": null, + "CFG_CENTER_BYP5_13": null, + "CFG_CENTER_BYP5_14": null, + "CFG_CENTER_BYP5_15": null, + "CFG_CENTER_BYP5_16": null, + "CFG_CENTER_BYP5_17": null, + "CFG_CENTER_BYP5_18": null, + "CFG_CENTER_BYP5_19": null, + "CFG_CENTER_BYP5_2": null, + "CFG_CENTER_BYP5_3": null, + "CFG_CENTER_BYP5_4": null, + "CFG_CENTER_BYP5_5": null, + "CFG_CENTER_BYP5_6": null, + "CFG_CENTER_BYP5_7": null, + "CFG_CENTER_BYP5_8": null, + "CFG_CENTER_BYP5_9": null, + "CFG_CENTER_BYP6_0": null, + "CFG_CENTER_BYP6_1": null, + "CFG_CENTER_BYP6_10": null, + "CFG_CENTER_BYP6_11": null, + "CFG_CENTER_BYP6_12": null, + "CFG_CENTER_BYP6_13": null, + "CFG_CENTER_BYP6_14": null, + "CFG_CENTER_BYP6_15": null, + "CFG_CENTER_BYP6_16": null, + "CFG_CENTER_BYP6_17": null, + "CFG_CENTER_BYP6_18": null, + "CFG_CENTER_BYP6_19": null, + "CFG_CENTER_BYP6_2": null, + "CFG_CENTER_BYP6_3": null, + "CFG_CENTER_BYP6_4": null, + "CFG_CENTER_BYP6_5": null, + "CFG_CENTER_BYP6_6": null, + "CFG_CENTER_BYP6_7": null, + "CFG_CENTER_BYP6_8": null, + "CFG_CENTER_BYP6_9": null, + "CFG_CENTER_BYP7_0": null, + "CFG_CENTER_BYP7_1": null, + "CFG_CENTER_BYP7_10": null, + "CFG_CENTER_BYP7_11": null, + "CFG_CENTER_BYP7_12": null, + "CFG_CENTER_BYP7_13": null, + "CFG_CENTER_BYP7_14": null, + "CFG_CENTER_BYP7_15": null, + "CFG_CENTER_BYP7_16": null, + "CFG_CENTER_BYP7_17": null, + "CFG_CENTER_BYP7_18": null, + "CFG_CENTER_BYP7_19": null, + "CFG_CENTER_BYP7_2": null, + "CFG_CENTER_BYP7_3": null, + "CFG_CENTER_BYP7_4": null, + "CFG_CENTER_BYP7_5": null, + "CFG_CENTER_BYP7_6": null, + "CFG_CENTER_BYP7_7": null, + "CFG_CENTER_BYP7_8": null, + "CFG_CENTER_BYP7_9": null, + "CFG_CENTER_CLK0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_EE2A0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_4": { 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"325.400" + }, + "CFG_CENTER_EE2A1_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A2_7": { + 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"res": "325.400" + }, + "CFG_CENTER_EE2A3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2BEG1_3": { + "cap": "99.000", + "res": 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null, + "CFG_CENTER_FAN4_3": null, + "CFG_CENTER_FAN4_4": null, + "CFG_CENTER_FAN4_5": null, + "CFG_CENTER_FAN4_6": null, + "CFG_CENTER_FAN4_7": null, + "CFG_CENTER_FAN4_8": null, + "CFG_CENTER_FAN4_9": null, + "CFG_CENTER_FAN5_0": null, + "CFG_CENTER_FAN5_1": null, + "CFG_CENTER_FAN5_10": null, + "CFG_CENTER_FAN5_11": null, + "CFG_CENTER_FAN5_12": null, + "CFG_CENTER_FAN5_13": null, + "CFG_CENTER_FAN5_14": null, + "CFG_CENTER_FAN5_15": null, + "CFG_CENTER_FAN5_16": null, + "CFG_CENTER_FAN5_17": null, + "CFG_CENTER_FAN5_18": null, + "CFG_CENTER_FAN5_19": null, + "CFG_CENTER_FAN5_2": null, + "CFG_CENTER_FAN5_3": null, + "CFG_CENTER_FAN5_4": null, + "CFG_CENTER_FAN5_5": null, + "CFG_CENTER_FAN5_6": null, + "CFG_CENTER_FAN5_7": null, + "CFG_CENTER_FAN5_8": null, + "CFG_CENTER_FAN5_9": null, + "CFG_CENTER_FAN6_0": null, + "CFG_CENTER_FAN6_1": null, + "CFG_CENTER_FAN6_10": null, + "CFG_CENTER_FAN6_11": null, + "CFG_CENTER_FAN6_12": null, + "CFG_CENTER_FAN6_13": null, + "CFG_CENTER_FAN6_14": null, + "CFG_CENTER_FAN6_15": null, + "CFG_CENTER_FAN6_16": null, + "CFG_CENTER_FAN6_17": null, + "CFG_CENTER_FAN6_18": null, + "CFG_CENTER_FAN6_19": null, + "CFG_CENTER_FAN6_2": null, + "CFG_CENTER_FAN6_3": null, + "CFG_CENTER_FAN6_4": null, + "CFG_CENTER_FAN6_5": null, + "CFG_CENTER_FAN6_6": null, + "CFG_CENTER_FAN6_7": null, + "CFG_CENTER_FAN6_8": null, + "CFG_CENTER_FAN6_9": null, + "CFG_CENTER_FAN7_0": null, + "CFG_CENTER_FAN7_1": null, + "CFG_CENTER_FAN7_10": null, + "CFG_CENTER_FAN7_11": null, + "CFG_CENTER_FAN7_12": null, + "CFG_CENTER_FAN7_13": null, + "CFG_CENTER_FAN7_14": null, + "CFG_CENTER_FAN7_15": null, + "CFG_CENTER_FAN7_16": null, + "CFG_CENTER_FAN7_17": null, + "CFG_CENTER_FAN7_18": null, + "CFG_CENTER_FAN7_19": null, + "CFG_CENTER_FAN7_2": null, + "CFG_CENTER_FAN7_3": null, + "CFG_CENTER_FAN7_4": null, + "CFG_CENTER_FAN7_5": null, + "CFG_CENTER_FAN7_6": null, + "CFG_CENTER_FAN7_7": null, + "CFG_CENTER_FAN7_8": null, + "CFG_CENTER_FAN7_9": null, + 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"CFG_CENTER_IMUX0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_17": { + "cap": "1.111", + "res": "0.000" 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"res": "0.000" + }, + "CFG_CENTER_IMUX11_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_14": { 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"CFG_CENTER_IMUX22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_18": { + "cap": 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"0.000" + }, + "CFG_CENTER_IMUX25_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_12": { 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"0.000" + }, + "CFG_CENTER_IMUX28_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_16": { + "cap": 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+ "res": "0.000" + }, + "CFG_CENTER_IMUX32_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_7": { + 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+ "res": "0.000" + }, + "CFG_CENTER_IMUX35_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_6": { + 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"res": "0.000" + }, + "CFG_CENTER_IMUX40_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_16": { + "cap": "1.111", + "res": "0.000" + }, + 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"1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_2": { + "cap": "1.111", + "res": "0.000" + }, + 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"0.000" + }, + "CFG_CENTER_IMUX44_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_19": { + "cap": "1.111", + "res": "0.000" + }, + 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"res": "0.000" + }, + "CFG_CENTER_IMUX4_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LH10_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LOGIC_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_19": { + "cap": "1.111", + "res": "0.000" + }, + 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"CFG_CENTER_LOGIC_OUTS_B21_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_9": { 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"0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_9": { 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+ "CFG_CENTER_SW4END3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW2A0_14": { + "cap": "99.000", + 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}, + "CFG_CENTER_WW4END0_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_9": { + "cap": "99.000", + "res": "325.400" + } + } } diff --git a/kintex7/tile_type_CFG_CENTER_MID.json b/kintex7/tile_type_CFG_CENTER_MID.json index 6206124..cdec6a9 100644 --- a/kintex7/tile_type_CFG_CENTER_MID.json +++ b/kintex7/tile_type_CFG_CENTER_MID.json @@ -2,1997 +2,5132 @@ "pips": { "CFG_CENTER_MID.CFG_CENTER_BSCAN1_CAPTURE->CFG_CENTER_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_CAPTURE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_DRCK->CFG_CENTER_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_DRCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RESET->CFG_CENTER_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_RESET" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_RUNTEST->CFG_CENTER_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_RUNTEST" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SEL->CFG_CENTER_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_SEL" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_SHIFT->CFG_CENTER_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_SHIFT" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TCK->CFG_CENTER_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_TCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TDI->CFG_CENTER_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_TDI" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_TMS->CFG_CENTER_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_TMS" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN1_UPDATE->CFG_CENTER_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN1_UPDATE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_CAPTURE->CFG_CENTER_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_CAPTURE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_DRCK->CFG_CENTER_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_DRCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RESET->CFG_CENTER_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_RESET" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_RUNTEST->CFG_CENTER_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_RUNTEST" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SEL->CFG_CENTER_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_SEL" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_SHIFT->CFG_CENTER_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_SHIFT" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TCK->CFG_CENTER_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_TCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TDI->CFG_CENTER_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_TDI" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_TMS->CFG_CENTER_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_TMS" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN2_UPDATE->CFG_CENTER_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN2_UPDATE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_CAPTURE->CFG_CENTER_LOGIC_OUTS_B11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_CAPTURE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_DRCK->CFG_CENTER_LOGIC_OUTS_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_DRCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RESET->CFG_CENTER_LOGIC_OUTS_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_RESET" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_RUNTEST->CFG_CENTER_LOGIC_OUTS_B13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_RUNTEST" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SEL->CFG_CENTER_LOGIC_OUTS_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_SEL" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_SHIFT->CFG_CENTER_LOGIC_OUTS_B21_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_SHIFT" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TCK->CFG_CENTER_LOGIC_OUTS_B19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_TCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TDI->CFG_CENTER_LOGIC_OUTS_B17_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_TDI" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_TMS->CFG_CENTER_LOGIC_OUTS_B15_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_TMS" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN3_UPDATE->CFG_CENTER_LOGIC_OUTS_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN3_UPDATE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_CAPTURE->CFG_CENTER_LOGIC_OUTS_B12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_CAPTURE" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_DRCK->CFG_CENTER_LOGIC_OUTS_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_DRCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RESET->CFG_CENTER_LOGIC_OUTS_B21_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_RESET" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_RUNTEST->CFG_CENTER_LOGIC_OUTS_B14_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_RUNTEST" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SEL->CFG_CENTER_LOGIC_OUTS_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_SEL" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_SHIFT->CFG_CENTER_LOGIC_OUTS_B22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_SHIFT" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TCK->CFG_CENTER_LOGIC_OUTS_B20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_TCK" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TDI->CFG_CENTER_LOGIC_OUTS_B18_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_TDI" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_TMS->CFG_CENTER_LOGIC_OUTS_B16_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_TMS" }, "CFG_CENTER_MID.CFG_CENTER_BSCAN4_UPDATE->CFG_CENTER_LOGIC_OUTS_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_BSCAN4_UPDATE" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_5->CFG_CENTER_STARTUP_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_5" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_6->CFG_CENTER_ICAP0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_6" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_7->CFG_CENTER_STARTUP_USRCCLKO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_USRCCLKO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_7" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_8->CFG_CENTER_MID_DNA_PORT_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_DNA_PORT_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_8" }, "CFG_CENTER_MID.CFG_CENTER_CLK1_9->CFG_CENTER_CAPTURE_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_CAPTURE_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_9" }, "CFG_CENTER_MID.CFG_CENTER_DCIRESET_LOCKED->CFG_CENTER_LOGIC_OUTS_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_DCIRESET_LOCKED" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_CRCERROR->CFG_CENTER_LOGIC_OUTS_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_CRCERROR" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERROR->CFG_CENTER_LOGIC_OUTS_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_ECCERROR" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_ECCERRORSINGLE->CFG_CENTER_LOGIC_OUTS_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR0->CFG_CENTER_LOGIC_OUTS_B10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR0" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR1->CFG_CENTER_LOGIC_OUTS_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR1" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR10->CFG_CENTER_LOGIC_OUTS_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR10" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR11->CFG_CENTER_LOGIC_OUTS_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR11" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR12->CFG_CENTER_LOGIC_OUTS_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR12" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR13->CFG_CENTER_LOGIC_OUTS_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR13" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR14->CFG_CENTER_LOGIC_OUTS_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR14" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR15->CFG_CENTER_LOGIC_OUTS_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR15" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR16->CFG_CENTER_LOGIC_OUTS_B10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR16" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR17->CFG_CENTER_LOGIC_OUTS_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR17" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR18->CFG_CENTER_LOGIC_OUTS_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR18" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR19->CFG_CENTER_LOGIC_OUTS_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR19" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR2->CFG_CENTER_LOGIC_OUTS_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR2" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR20->CFG_CENTER_LOGIC_OUTS_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR20" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR21->CFG_CENTER_LOGIC_OUTS_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR21" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR22->CFG_CENTER_LOGIC_OUTS_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR22" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR23->CFG_CENTER_LOGIC_OUTS_B17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR23" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR24->CFG_CENTER_LOGIC_OUTS_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR24" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR25->CFG_CENTER_LOGIC_OUTS_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR25" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR3->CFG_CENTER_LOGIC_OUTS_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR3" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR4->CFG_CENTER_LOGIC_OUTS_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR4" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR5->CFG_CENTER_LOGIC_OUTS_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR5" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR6->CFG_CENTER_LOGIC_OUTS_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR6" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR7->CFG_CENTER_LOGIC_OUTS_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR7" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR8->CFG_CENTER_LOGIC_OUTS_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR8" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_FAR9->CFG_CENTER_LOGIC_OUTS_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_FAR9" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT0->CFG_CENTER_LOGIC_OUTS_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT0" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT1->CFG_CENTER_LOGIC_OUTS_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT1" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT2->CFG_CENTER_LOGIC_OUTS_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT2" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT3->CFG_CENTER_LOGIC_OUTS_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT3" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNBIT4->CFG_CENTER_LOGIC_OUTS_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNBIT4" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME0->CFG_CENTER_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME0" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME1->CFG_CENTER_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME1" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME10->CFG_CENTER_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME10" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME11->CFG_CENTER_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME11" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME12->CFG_CENTER_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME12" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME2->CFG_CENTER_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME2" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME3->CFG_CENTER_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME3" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME4->CFG_CENTER_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME4" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME5->CFG_CENTER_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME5" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME6->CFG_CENTER_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME6" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME7->CFG_CENTER_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME7" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME8->CFG_CENTER_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME8" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROME9->CFG_CENTER_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROME9" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNDROMEVALID->CFG_CENTER_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD0->CFG_CENTER_LOGIC_OUTS_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD0" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD1->CFG_CENTER_LOGIC_OUTS_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD1" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD2->CFG_CENTER_LOGIC_OUTS_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD2" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD3->CFG_CENTER_LOGIC_OUTS_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD3" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD4->CFG_CENTER_LOGIC_OUTS_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD4" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD5->CFG_CENTER_LOGIC_OUTS_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD5" }, "CFG_CENTER_MID.CFG_CENTER_FRAME_ECC_SYNWORD6->CFG_CENTER_LOGIC_OUTS_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_FRAME_ECC_SYNWORD6" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O0->CFG_CENTER_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O0" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O1->CFG_CENTER_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O1" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O10->CFG_CENTER_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O10" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O11->CFG_CENTER_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O11" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O12->CFG_CENTER_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O12" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O13->CFG_CENTER_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O13" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O14->CFG_CENTER_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O14" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O15->CFG_CENTER_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O15" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O16->CFG_CENTER_LOGIC_OUTS_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O16" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O17->CFG_CENTER_LOGIC_OUTS_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O17" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O18->CFG_CENTER_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O18" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O19->CFG_CENTER_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O19" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O2->CFG_CENTER_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O2" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O20->CFG_CENTER_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O20" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O21->CFG_CENTER_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O21" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O22->CFG_CENTER_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O22" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O23->CFG_CENTER_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O23" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O24->CFG_CENTER_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O24" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O25->CFG_CENTER_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O25" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O26->CFG_CENTER_LOGIC_OUTS_B10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O26" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O27->CFG_CENTER_LOGIC_OUTS_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O27" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O28->CFG_CENTER_LOGIC_OUTS_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O28" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O29->CFG_CENTER_LOGIC_OUTS_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O29" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O3->CFG_CENTER_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O3" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O30->CFG_CENTER_LOGIC_OUTS_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O30" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O31->CFG_CENTER_LOGIC_OUTS_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O31" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O4->CFG_CENTER_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O4" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O5->CFG_CENTER_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O5" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O6->CFG_CENTER_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O6" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O7->CFG_CENTER_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O7" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O8->CFG_CENTER_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O8" }, "CFG_CENTER_MID.CFG_CENTER_ICAP0_O9->CFG_CENTER_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP0_O9" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O0->CFG_CENTER_LOGIC_OUTS_B23_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O0" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O1->CFG_CENTER_LOGIC_OUTS_B12_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O1" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O10->CFG_CENTER_LOGIC_OUTS_B21_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O10" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O11->CFG_CENTER_LOGIC_OUTS_B22_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O11" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O12->CFG_CENTER_LOGIC_OUTS_B23_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O12" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O13->CFG_CENTER_LOGIC_OUTS_B12_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O13" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O14->CFG_CENTER_LOGIC_OUTS_B13_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O14" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O15->CFG_CENTER_LOGIC_OUTS_B14_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O15" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O16->CFG_CENTER_LOGIC_OUTS_B15_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O16" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O17->CFG_CENTER_LOGIC_OUTS_B16_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O17" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O18->CFG_CENTER_LOGIC_OUTS_B17_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O18" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O19->CFG_CENTER_LOGIC_OUTS_B18_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O19" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O2->CFG_CENTER_LOGIC_OUTS_B13_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O2" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O20->CFG_CENTER_LOGIC_OUTS_B19_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O20" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O21->CFG_CENTER_LOGIC_OUTS_B20_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O21" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O22->CFG_CENTER_LOGIC_OUTS_B21_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O22" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O23->CFG_CENTER_LOGIC_OUTS_B22_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O23" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O24->CFG_CENTER_LOGIC_OUTS_B23_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O24" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O25->CFG_CENTER_LOGIC_OUTS_B10_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O25" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O26->CFG_CENTER_LOGIC_OUTS_B11_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O26" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O27->CFG_CENTER_LOGIC_OUTS_B12_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O27" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O28->CFG_CENTER_LOGIC_OUTS_B13_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O28" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O29->CFG_CENTER_LOGIC_OUTS_B14_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O29" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O3->CFG_CENTER_LOGIC_OUTS_B14_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O3" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O30->CFG_CENTER_LOGIC_OUTS_B15_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O30" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O31->CFG_CENTER_LOGIC_OUTS_B16_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O31" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O4->CFG_CENTER_LOGIC_OUTS_B15_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O4" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O5->CFG_CENTER_LOGIC_OUTS_B16_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O5" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O6->CFG_CENTER_LOGIC_OUTS_B17_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O6" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O7->CFG_CENTER_LOGIC_OUTS_B18_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O7" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O8->CFG_CENTER_LOGIC_OUTS_B19_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O8" }, "CFG_CENTER_MID.CFG_CENTER_ICAP1_O9->CFG_CENTER_LOGIC_OUTS_B20_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_ICAP1_O9" }, "CFG_CENTER_MID.CFG_CENTER_IMUX27_5->CFG_CENTER_ICAP0_I16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX27_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX28_12->CFG_CENTER_ICAP1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX28_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX28_13->CFG_CENTER_ICAP1_I16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX28_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX28_4->CFG_CENTER_ICAP0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX28_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX28_5->CFG_CENTER_ICAP0_I17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX28_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX29_12->CFG_CENTER_ICAP1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX29_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX29_13->CFG_CENTER_ICAP1_I17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX29_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX29_4->CFG_CENTER_ICAP0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX29_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX29_5->CFG_CENTER_ICAP0_I18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX29_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX30_12->CFG_CENTER_ICAP1_I2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX30_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX30_13->CFG_CENTER_ICAP1_I18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX30_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX30_4->CFG_CENTER_ICAP0_I2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX30_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX30_5->CFG_CENTER_ICAP0_I19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX30_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX31_12->CFG_CENTER_ICAP1_I3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX31_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX31_13->CFG_CENTER_ICAP1_I19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX31_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX31_4->CFG_CENTER_ICAP0_I3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX31_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX31_5->CFG_CENTER_ICAP0_I20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX31_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX32_12->CFG_CENTER_ICAP1_I4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX32_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX32_13->CFG_CENTER_ICAP1_I20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX32_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX32_4->CFG_CENTER_ICAP0_I4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX32_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX32_5->CFG_CENTER_ICAP0_I21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX32_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_12->CFG_CENTER_ICAP1_I5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_13->CFG_CENTER_ICAP1_I21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_3->CFG_CENTER_BSCAN1_TDO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_BSCAN1_TDO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_3" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_4->CFG_CENTER_ICAP0_I5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX33_5->CFG_CENTER_ICAP0_I22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX33_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_12->CFG_CENTER_ICAP1_I6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_13->CFG_CENTER_ICAP1_I22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_3->CFG_CENTER_BSCAN2_TDO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_BSCAN2_TDO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_3" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_4->CFG_CENTER_ICAP0_I6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX34_5->CFG_CENTER_ICAP0_I23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX34_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_12->CFG_CENTER_ICAP1_I7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_13->CFG_CENTER_ICAP1_I23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_4->CFG_CENTER_ICAP0_I7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_5->CFG_CENTER_ICAP0_I24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX35_8->CFG_CENTER_DCIRESET_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DCIRESET_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX35_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_12->CFG_CENTER_ICAP1_I8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_13->CFG_CENTER_ICAP1_I24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_4->CFG_CENTER_ICAP0_I8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_5->CFG_CENTER_ICAP0_I25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX36_8->CFG_CENTER_STARTUP_KEYCLEARB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_KEYCLEARB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX36_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_12->CFG_CENTER_ICAP1_I9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_13->CFG_CENTER_ICAP1_I25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_4->CFG_CENTER_ICAP0_I9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_5->CFG_CENTER_ICAP0_I26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX37_8->CFG_CENTER_CAPTURE_CAP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_CAPTURE_CAP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX37_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_11->CFG_CENTER_BSCAN3_TDO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_BSCAN3_TDO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_12->CFG_CENTER_ICAP1_I10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_13->CFG_CENTER_ICAP1_I26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_4->CFG_CENTER_ICAP0_I10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_5->CFG_CENTER_ICAP0_I27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX38_8->CFG_CENTER_STARTUP_USRCCLKTS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_USRCCLKTS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX38_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_11->CFG_CENTER_BSCAN4_TDO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_BSCAN4_TDO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_12->CFG_CENTER_ICAP1_I11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_13->CFG_CENTER_ICAP1_I27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_4->CFG_CENTER_ICAP0_I11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_5->CFG_CENTER_ICAP0_I28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX39_8->CFG_CENTER_STARTUP_GTS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_GTS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX39_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_11->CFG_CENTER_ICAP0_CSIB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_CSIB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_12->CFG_CENTER_ICAP1_I12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_13->CFG_CENTER_ICAP1_I28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_4->CFG_CENTER_ICAP0_I12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_5->CFG_CENTER_ICAP0_I29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX40_8->CFG_CENTER_STARTUP_GSR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_GSR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX40_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_11->CFG_CENTER_ICAP0_RDWRB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_RDWRB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_12->CFG_CENTER_ICAP1_I13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_13->CFG_CENTER_ICAP1_I29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_4->CFG_CENTER_ICAP0_I13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_5->CFG_CENTER_ICAP0_I30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX41_8->CFG_CENTER_STARTUP_USRDONETS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_USRDONETS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_11->CFG_CENTER_ICAP1_RDWRB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_RDWRB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_12->CFG_CENTER_ICAP1_I14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_13->CFG_CENTER_ICAP1_I30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_4->CFG_CENTER_ICAP0_I14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_5->CFG_CENTER_ICAP0_I31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_5" }, "CFG_CENTER_MID.CFG_CENTER_IMUX42_8->CFG_CENTER_STARTUP_USRDONEO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_USRDONEO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_8" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_11->CFG_CENTER_ICAP1_CSIB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_CSIB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_11" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_12->CFG_CENTER_ICAP1_I15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_12" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_13->CFG_CENTER_ICAP1_I31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_I31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_13" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_4->CFG_CENTER_ICAP0_I15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP0_I15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_4" }, "CFG_CENTER_MID.CFG_CENTER_IMUX43_8->CFG_CENTER_STARTUP_PACK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_STARTUP_PACK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_8" }, "CFG_CENTER_MID.CFG_CENTER_MID_ICAP1_CLK->CFG_CENTER_ICAP1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_ICAP1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_MID_ICAP1_CLK" }, "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGCLK->CFG_CENTER_LOGIC_OUTS_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_STARTUP_CFGCLK" }, "CFG_CENTER_MID.CFG_CENTER_STARTUP_CFGMCLK->CFG_CENTER_LOGIC_OUTS_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_STARTUP_CFGMCLK" }, "CFG_CENTER_MID.CFG_CENTER_STARTUP_EOS->CFG_CENTER_LOGIC_OUTS_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_STARTUP_EOS" }, "CFG_CENTER_MID.CFG_CENTER_STARTUP_PREQ->CFG_CENTER_LOGIC_OUTS_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_STARTUP_PREQ" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_CFGCLK->CFG_CENTER_LOGIC_OUTS_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_CFGCLK" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA0->CFG_CENTER_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA0" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA1->CFG_CENTER_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA1" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA10->CFG_CENTER_MID_USR_ACCESS_DATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA10" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA11->CFG_CENTER_MID_USR_ACCESS_DATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA11" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA12->CFG_CENTER_MID_USR_ACCESS_DATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA12" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA13->CFG_CENTER_MID_USR_ACCESS_DATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA13" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA14->CFG_CENTER_MID_USR_ACCESS_DATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA14" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA15->CFG_CENTER_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA15" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA16->CFG_CENTER_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA16" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA17->CFG_CENTER_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA17" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA18->CFG_CENTER_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA18" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA19->CFG_CENTER_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA19" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA2->CFG_CENTER_MID_USR_ACCESS_DATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA2" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA20->CFG_CENTER_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA20" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA21->CFG_CENTER_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA21" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA22->CFG_CENTER_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA22" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA23->CFG_CENTER_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA23" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA24->CFG_CENTER_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA24" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA25->CFG_CENTER_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA25" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA26->CFG_CENTER_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA26" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA27->CFG_CENTER_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA27" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA28->CFG_CENTER_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA28" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA29->CFG_CENTER_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA29" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA3->CFG_CENTER_MID_USR_ACCESS_DATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA3" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA30->CFG_CENTER_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA30" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA31->CFG_CENTER_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA31" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA4->CFG_CENTER_MID_USR_ACCESS_DATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA4" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA5->CFG_CENTER_MID_USR_ACCESS_DATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA5" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA6->CFG_CENTER_MID_USR_ACCESS_DATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA6" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA7->CFG_CENTER_MID_USR_ACCESS_DATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA7" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA8->CFG_CENTER_MID_USR_ACCESS_DATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA8" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATA9->CFG_CENTER_MID_USR_ACCESS_DATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_MID_USR_ACCESS_DATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATA9" }, "CFG_CENTER_MID.CFG_CENTER_USR_ACCESS_DATAVALID->CFG_CENTER_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_USR_ACCESS_DATAVALID" } }, @@ -2001,40 +5136,346 @@ "name": "X0Y0", "prefix": "USR_ACCESS", "site_pins": { - "CFGCLK": "CFG_CENTER_USR_ACCESS_CFGCLK", - "DATA0": "CFG_CENTER_USR_ACCESS_DATA0", - "DATA1": "CFG_CENTER_USR_ACCESS_DATA1", - "DATA10": "CFG_CENTER_USR_ACCESS_DATA10", - "DATA11": "CFG_CENTER_USR_ACCESS_DATA11", - "DATA12": "CFG_CENTER_USR_ACCESS_DATA12", - "DATA13": "CFG_CENTER_USR_ACCESS_DATA13", - "DATA14": "CFG_CENTER_USR_ACCESS_DATA14", - "DATA15": "CFG_CENTER_USR_ACCESS_DATA15", - "DATA16": "CFG_CENTER_USR_ACCESS_DATA16", - "DATA17": "CFG_CENTER_USR_ACCESS_DATA17", - "DATA18": "CFG_CENTER_USR_ACCESS_DATA18", - "DATA19": "CFG_CENTER_USR_ACCESS_DATA19", - "DATA2": "CFG_CENTER_USR_ACCESS_DATA2", - "DATA20": "CFG_CENTER_USR_ACCESS_DATA20", - "DATA21": "CFG_CENTER_USR_ACCESS_DATA21", - "DATA22": "CFG_CENTER_USR_ACCESS_DATA22", - "DATA23": "CFG_CENTER_USR_ACCESS_DATA23", - "DATA24": "CFG_CENTER_USR_ACCESS_DATA24", - "DATA25": "CFG_CENTER_USR_ACCESS_DATA25", - "DATA26": "CFG_CENTER_USR_ACCESS_DATA26", - "DATA27": "CFG_CENTER_USR_ACCESS_DATA27", - "DATA28": "CFG_CENTER_USR_ACCESS_DATA28", - "DATA29": "CFG_CENTER_USR_ACCESS_DATA29", - "DATA3": "CFG_CENTER_USR_ACCESS_DATA3", - "DATA30": "CFG_CENTER_USR_ACCESS_DATA30", - "DATA31": "CFG_CENTER_USR_ACCESS_DATA31", - "DATA4": "CFG_CENTER_USR_ACCESS_DATA4", - "DATA5": "CFG_CENTER_USR_ACCESS_DATA5", - "DATA6": "CFG_CENTER_USR_ACCESS_DATA6", - "DATA7": "CFG_CENTER_USR_ACCESS_DATA7", - "DATA8": "CFG_CENTER_USR_ACCESS_DATA8", - "DATA9": "CFG_CENTER_USR_ACCESS_DATA9", - "DATAVALID": "CFG_CENTER_USR_ACCESS_DATAVALID" + "CFGCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_CFGCLK" + }, + "DATA0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA0" + }, + "DATA1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA1" + }, + "DATA10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA10" + }, + "DATA11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA11" + }, + "DATA12": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA12" + }, + "DATA13": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA13" + }, + "DATA14": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA14" + }, + "DATA15": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA15" + }, + "DATA16": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA16" + }, + "DATA17": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA17" + }, + "DATA18": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA18" + }, + "DATA19": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA19" + }, + "DATA2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA2" + }, + "DATA20": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA20" + }, + "DATA21": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA21" + }, + "DATA22": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA22" + }, + "DATA23": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA23" + }, + "DATA24": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA24" + }, + "DATA25": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA25" + }, + "DATA26": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA26" + }, + "DATA27": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA27" + }, + "DATA28": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA28" + }, + "DATA29": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA29" + }, + "DATA3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA3" + }, + "DATA30": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA30" + }, + "DATA31": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA31" + }, + "DATA4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA4" + }, + "DATA5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA5" + }, + "DATA6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA6" + }, + "DATA7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA7" + }, + "DATA8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA8" + }, + "DATA9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATA9" + }, + "DATAVALID": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_USR_ACCESS_DATAVALID" + } }, "type": "USR_ACCESS", "x_coord": 0, @@ -2044,17 +5485,116 @@ "name": "X0Y0", "prefix": "BSCAN", "site_pins": { - "CAPTURE": "CFG_CENTER_BSCAN1_CAPTURE", - "DRCK": "CFG_CENTER_BSCAN1_DRCK", - "RESET": "CFG_CENTER_BSCAN1_RESET", - "RUNTEST": "CFG_CENTER_BSCAN1_RUNTEST", - "SEL": "CFG_CENTER_BSCAN1_SEL", - "SHIFT": "CFG_CENTER_BSCAN1_SHIFT", - "TCK": "CFG_CENTER_BSCAN1_TCK", - "TDI": "CFG_CENTER_BSCAN1_TDI", - "TDO": "CFG_CENTER_BSCAN1_TDO", - "TMS": "CFG_CENTER_BSCAN1_TMS", - "UPDATE": "CFG_CENTER_BSCAN1_UPDATE" + "CAPTURE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_CAPTURE" + }, + "DRCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_DRCK" + }, + "RESET": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_RESET" + }, + "RUNTEST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_RUNTEST" + }, + "SEL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_SEL" + }, + "SHIFT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_SHIFT" + }, + "TCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_TCK" + }, + "TDI": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_TDI" + }, + "TDO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_BSCAN1_TDO" + }, + "TMS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_TMS" + }, + "UPDATE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN1_UPDATE" + } }, "type": "BSCAN", "x_coord": 0, @@ -2064,17 +5604,116 @@ "name": "X0Y1", "prefix": "BSCAN", "site_pins": { - "CAPTURE": "CFG_CENTER_BSCAN2_CAPTURE", - "DRCK": "CFG_CENTER_BSCAN2_DRCK", - "RESET": "CFG_CENTER_BSCAN2_RESET", - "RUNTEST": "CFG_CENTER_BSCAN2_RUNTEST", - "SEL": "CFG_CENTER_BSCAN2_SEL", - "SHIFT": "CFG_CENTER_BSCAN2_SHIFT", - "TCK": "CFG_CENTER_BSCAN2_TCK", - "TDI": "CFG_CENTER_BSCAN2_TDI", - "TDO": "CFG_CENTER_BSCAN2_TDO", - "TMS": "CFG_CENTER_BSCAN2_TMS", - "UPDATE": "CFG_CENTER_BSCAN2_UPDATE" + "CAPTURE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_CAPTURE" + }, + "DRCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_DRCK" + }, + "RESET": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_RESET" + }, + "RUNTEST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_RUNTEST" + }, + "SEL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_SEL" + }, + "SHIFT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_SHIFT" + }, + "TCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_TCK" + }, + "TDI": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_TDI" + }, + "TDO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_BSCAN2_TDO" + }, + "TMS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_TMS" + }, + "UPDATE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN2_UPDATE" + } }, "type": "BSCAN", "x_coord": 0, @@ -2084,73 +5723,676 @@ "name": "X0Y0", "prefix": "ICAP", "site_pins": { - "CLK": "CFG_CENTER_ICAP0_CLK", - "CSIB": "CFG_CENTER_ICAP0_CSIB", - "I0": "CFG_CENTER_ICAP0_I0", - "I1": "CFG_CENTER_ICAP0_I1", - "I10": "CFG_CENTER_ICAP0_I10", - "I11": "CFG_CENTER_ICAP0_I11", - "I12": "CFG_CENTER_ICAP0_I12", - "I13": "CFG_CENTER_ICAP0_I13", - "I14": "CFG_CENTER_ICAP0_I14", - "I15": "CFG_CENTER_ICAP0_I15", - "I16": "CFG_CENTER_ICAP0_I16", - "I17": "CFG_CENTER_ICAP0_I17", - "I18": "CFG_CENTER_ICAP0_I18", - "I19": "CFG_CENTER_ICAP0_I19", - "I2": "CFG_CENTER_ICAP0_I2", - "I20": "CFG_CENTER_ICAP0_I20", - "I21": "CFG_CENTER_ICAP0_I21", - "I22": "CFG_CENTER_ICAP0_I22", - "I23": "CFG_CENTER_ICAP0_I23", - "I24": "CFG_CENTER_ICAP0_I24", - "I25": "CFG_CENTER_ICAP0_I25", - "I26": "CFG_CENTER_ICAP0_I26", - "I27": "CFG_CENTER_ICAP0_I27", - "I28": "CFG_CENTER_ICAP0_I28", - "I29": "CFG_CENTER_ICAP0_I29", - "I3": "CFG_CENTER_ICAP0_I3", - "I30": "CFG_CENTER_ICAP0_I30", - "I31": "CFG_CENTER_ICAP0_I31", - "I4": "CFG_CENTER_ICAP0_I4", - "I5": "CFG_CENTER_ICAP0_I5", - "I6": "CFG_CENTER_ICAP0_I6", - "I7": "CFG_CENTER_ICAP0_I7", - "I8": "CFG_CENTER_ICAP0_I8", - "I9": "CFG_CENTER_ICAP0_I9", - "O0": "CFG_CENTER_ICAP0_O0", - "O1": "CFG_CENTER_ICAP0_O1", - "O10": "CFG_CENTER_ICAP0_O10", - "O11": "CFG_CENTER_ICAP0_O11", - "O12": "CFG_CENTER_ICAP0_O12", - "O13": "CFG_CENTER_ICAP0_O13", - "O14": "CFG_CENTER_ICAP0_O14", - "O15": "CFG_CENTER_ICAP0_O15", - "O16": "CFG_CENTER_ICAP0_O16", - "O17": "CFG_CENTER_ICAP0_O17", - "O18": "CFG_CENTER_ICAP0_O18", - "O19": "CFG_CENTER_ICAP0_O19", - "O2": "CFG_CENTER_ICAP0_O2", - "O20": "CFG_CENTER_ICAP0_O20", - "O21": "CFG_CENTER_ICAP0_O21", - "O22": "CFG_CENTER_ICAP0_O22", - "O23": "CFG_CENTER_ICAP0_O23", - "O24": "CFG_CENTER_ICAP0_O24", - "O25": "CFG_CENTER_ICAP0_O25", - "O26": "CFG_CENTER_ICAP0_O26", - "O27": "CFG_CENTER_ICAP0_O27", - "O28": "CFG_CENTER_ICAP0_O28", - "O29": "CFG_CENTER_ICAP0_O29", - "O3": "CFG_CENTER_ICAP0_O3", - "O30": "CFG_CENTER_ICAP0_O30", - "O31": "CFG_CENTER_ICAP0_O31", - "O4": "CFG_CENTER_ICAP0_O4", - "O5": "CFG_CENTER_ICAP0_O5", - "O6": "CFG_CENTER_ICAP0_O6", - "O7": "CFG_CENTER_ICAP0_O7", - "O8": "CFG_CENTER_ICAP0_O8", - "O9": "CFG_CENTER_ICAP0_O9", - "RDWRB": "CFG_CENTER_ICAP0_RDWRB" + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_CLK" + }, + "CSIB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_CSIB" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I1" + }, + "I10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I10" + }, + "I11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I11" + }, + "I12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I12" + }, + "I13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I13" + }, + "I14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I14" + }, + "I15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I15" + }, + "I16": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I16" + }, + "I17": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I17" + }, + "I18": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I18" + }, + "I19": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I19" + }, + "I2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I2" + }, + "I20": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I20" + }, + "I21": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I21" + }, + "I22": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I22" + }, + "I23": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I23" + }, + "I24": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I24" + }, + "I25": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I25" + }, + "I26": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I26" + }, + "I27": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I27" + }, + "I28": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I28" + }, + "I29": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I29" + }, + "I3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I3" + }, + "I30": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I30" + }, + "I31": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I31" + }, + "I4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I4" + }, + "I5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I5" + }, + "I6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I6" + }, + "I7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I7" + }, + "I8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I8" + }, + "I9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_I9" + }, + "O0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O0" + }, + "O1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O1" + }, + "O10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O10" + }, + "O11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O11" + }, + "O12": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O12" + }, + "O13": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O13" + }, + "O14": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O14" + }, + "O15": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O15" + }, + "O16": { + "delay": [ + "0.000", + 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"O23": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O23" + }, + "O24": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O24" + }, + "O25": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O25" + }, + "O26": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O26" + }, + "O27": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O27" + }, + "O28": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O28" + }, + "O29": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O29" + }, + "O3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O3" + }, + "O30": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O30" + }, + "O31": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O31" + }, + "O4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O4" + }, + "O5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O5" + }, + "O6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O6" + }, + "O7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O7" + }, + "O8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O8" + }, + "O9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP0_O9" + }, + "RDWRB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP0_RDWRB" + } }, "type": "ICAP", "x_coord": 0, @@ -2160,61 +6402,556 @@ "name": "X0Y0", "prefix": "FRAME_ECC", "site_pins": { - "CRCERROR": "CFG_CENTER_FRAME_ECC_CRCERROR", - "ECCERROR": "CFG_CENTER_FRAME_ECC_ECCERROR", - "ECCERRORSINGLE": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", - "FAR0": "CFG_CENTER_FRAME_ECC_FAR0", - "FAR1": "CFG_CENTER_FRAME_ECC_FAR1", - "FAR10": "CFG_CENTER_FRAME_ECC_FAR10", - "FAR11": "CFG_CENTER_FRAME_ECC_FAR11", - "FAR12": "CFG_CENTER_FRAME_ECC_FAR12", - "FAR13": "CFG_CENTER_FRAME_ECC_FAR13", - "FAR14": "CFG_CENTER_FRAME_ECC_FAR14", - "FAR15": "CFG_CENTER_FRAME_ECC_FAR15", - "FAR16": "CFG_CENTER_FRAME_ECC_FAR16", - "FAR17": "CFG_CENTER_FRAME_ECC_FAR17", - "FAR18": "CFG_CENTER_FRAME_ECC_FAR18", - "FAR19": "CFG_CENTER_FRAME_ECC_FAR19", - "FAR2": "CFG_CENTER_FRAME_ECC_FAR2", - "FAR20": "CFG_CENTER_FRAME_ECC_FAR20", - "FAR21": "CFG_CENTER_FRAME_ECC_FAR21", - "FAR22": "CFG_CENTER_FRAME_ECC_FAR22", - "FAR23": "CFG_CENTER_FRAME_ECC_FAR23", - "FAR24": "CFG_CENTER_FRAME_ECC_FAR24", - "FAR25": "CFG_CENTER_FRAME_ECC_FAR25", - "FAR3": "CFG_CENTER_FRAME_ECC_FAR3", - "FAR4": "CFG_CENTER_FRAME_ECC_FAR4", - "FAR5": "CFG_CENTER_FRAME_ECC_FAR5", - "FAR6": "CFG_CENTER_FRAME_ECC_FAR6", - "FAR7": "CFG_CENTER_FRAME_ECC_FAR7", - "FAR8": "CFG_CENTER_FRAME_ECC_FAR8", - "FAR9": "CFG_CENTER_FRAME_ECC_FAR9", - "SYNBIT0": "CFG_CENTER_FRAME_ECC_SYNBIT0", - "SYNBIT1": "CFG_CENTER_FRAME_ECC_SYNBIT1", - "SYNBIT2": "CFG_CENTER_FRAME_ECC_SYNBIT2", - "SYNBIT3": "CFG_CENTER_FRAME_ECC_SYNBIT3", - "SYNBIT4": "CFG_CENTER_FRAME_ECC_SYNBIT4", - "SYNDROME0": "CFG_CENTER_FRAME_ECC_SYNDROME0", - "SYNDROME1": "CFG_CENTER_FRAME_ECC_SYNDROME1", - "SYNDROME10": "CFG_CENTER_FRAME_ECC_SYNDROME10", - "SYNDROME11": "CFG_CENTER_FRAME_ECC_SYNDROME11", - "SYNDROME12": "CFG_CENTER_FRAME_ECC_SYNDROME12", - "SYNDROME2": "CFG_CENTER_FRAME_ECC_SYNDROME2", - "SYNDROME3": "CFG_CENTER_FRAME_ECC_SYNDROME3", - "SYNDROME4": "CFG_CENTER_FRAME_ECC_SYNDROME4", - "SYNDROME5": "CFG_CENTER_FRAME_ECC_SYNDROME5", - "SYNDROME6": "CFG_CENTER_FRAME_ECC_SYNDROME6", - "SYNDROME7": "CFG_CENTER_FRAME_ECC_SYNDROME7", - "SYNDROME8": "CFG_CENTER_FRAME_ECC_SYNDROME8", - "SYNDROME9": "CFG_CENTER_FRAME_ECC_SYNDROME9", - "SYNDROMEVALID": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", - "SYNWORD0": "CFG_CENTER_FRAME_ECC_SYNWORD0", - "SYNWORD1": "CFG_CENTER_FRAME_ECC_SYNWORD1", - "SYNWORD2": "CFG_CENTER_FRAME_ECC_SYNWORD2", - "SYNWORD3": "CFG_CENTER_FRAME_ECC_SYNWORD3", - "SYNWORD4": "CFG_CENTER_FRAME_ECC_SYNWORD4", - "SYNWORD5": "CFG_CENTER_FRAME_ECC_SYNWORD5", - "SYNWORD6": "CFG_CENTER_FRAME_ECC_SYNWORD6" + "CRCERROR": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_CRCERROR" + }, + "ECCERROR": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_ECCERROR" + }, + "ECCERRORSINGLE": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE" + }, + "FAR0": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR0" + }, + "FAR1": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR1" + }, + "FAR10": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR10" + }, + "FAR11": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR11" + }, + "FAR12": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR12" + }, + "FAR13": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR13" + }, + "FAR14": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR14" + }, + "FAR15": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR15" + }, + "FAR16": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR16" + }, + "FAR17": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR17" + }, + "FAR18": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR18" + }, + "FAR19": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR19" + }, + "FAR2": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR2" + }, + "FAR20": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR20" + }, + "FAR21": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR21" + }, + "FAR22": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR22" + }, + "FAR23": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR23" + }, + "FAR24": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR24" + }, + "FAR25": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR25" + }, + "FAR3": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR3" + }, + "FAR4": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR4" + }, + "FAR5": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR5" + }, + "FAR6": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR6" + }, + "FAR7": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR7" + }, + "FAR8": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR8" + }, + "FAR9": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_FAR9" + }, + "SYNBIT0": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT0" + }, + "SYNBIT1": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT1" + }, + "SYNBIT2": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT2" + }, + "SYNBIT3": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT3" + }, + "SYNBIT4": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNBIT4" + }, + "SYNDROME0": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME0" + }, + "SYNDROME1": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME1" + }, + "SYNDROME10": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME10" + }, + "SYNDROME11": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME11" + }, + "SYNDROME12": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME12" + }, + "SYNDROME2": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME2" + }, + "SYNDROME3": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME3" + }, + "SYNDROME4": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME4" + }, + "SYNDROME5": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME5" + }, + "SYNDROME6": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME6" + }, + "SYNDROME7": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME7" + }, + "SYNDROME8": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME8" + }, + "SYNDROME9": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROME9" + }, + "SYNDROMEVALID": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNDROMEVALID" + }, + "SYNWORD0": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD0" + }, + "SYNWORD1": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD1" + }, + "SYNWORD2": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD2" + }, + "SYNWORD3": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD3" + }, + "SYNWORD4": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD4" + }, + "SYNWORD5": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD5" + }, + "SYNWORD6": { + "delay": [ + "4.709", + "4.709", + "5.000", + "5.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_FRAME_ECC_SYNWORD6" + } }, "type": "FRAME_ECC", "x_coord": 0, @@ -2224,19 +6961,136 @@ "name": "X0Y0", "prefix": "STARTUP", "site_pins": { - "CFGCLK": "CFG_CENTER_STARTUP_CFGCLK", - "CFGMCLK": "CFG_CENTER_STARTUP_CFGMCLK", - "CLK": "CFG_CENTER_STARTUP_CLK", - "EOS": "CFG_CENTER_STARTUP_EOS", - "GSR": "CFG_CENTER_STARTUP_GSR", - "GTS": "CFG_CENTER_STARTUP_GTS", - "KEYCLEARB": "CFG_CENTER_STARTUP_KEYCLEARB", - "PACK": "CFG_CENTER_STARTUP_PACK", - "PREQ": "CFG_CENTER_STARTUP_PREQ", - "USRCCLKO": "CFG_CENTER_STARTUP_USRCCLKO", - "USRCCLKTS": "CFG_CENTER_STARTUP_USRCCLKTS", - "USRDONEO": "CFG_CENTER_STARTUP_USRDONEO", - "USRDONETS": "CFG_CENTER_STARTUP_USRDONETS" + "CFGCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_STARTUP_CFGCLK" + }, + "CFGMCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_STARTUP_CFGMCLK" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_CLK" + }, + "EOS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_STARTUP_EOS" + }, + "GSR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_GSR" + }, + "GTS": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_GTS" + }, + "KEYCLEARB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_KEYCLEARB" + }, + "PACK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_PACK" + }, + "PREQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "237.1875", + "wire": "CFG_CENTER_STARTUP_PREQ" + }, + "USRCCLKO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_USRCCLKO" + }, + "USRCCLKTS": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_USRCCLKTS" + }, + "USRDONEO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_USRDONEO" + }, + "USRDONETS": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_STARTUP_USRDONETS" + } }, "type": "STARTUP", "x_coord": 0, @@ -2246,8 +7100,26 @@ "name": "X0Y0", "prefix": "CAPTURE", "site_pins": { - "CAP": "CFG_CENTER_CAPTURE_CAP", - "CLK": "CFG_CENTER_CAPTURE_CLK" + "CAP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_CAPTURE_CAP" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_CAPTURE_CLK" + } }, "type": "CAPTURE", "x_coord": 0, @@ -2257,8 +7129,26 @@ "name": "X0Y0", "prefix": "DCIRESET", "site_pins": { - "LOCKED": "CFG_CENTER_DCIRESET_LOCKED", - "RST": "CFG_CENTER_DCIRESET_RST" + "LOCKED": { + "delay": [ + "0.003", + "0.003", + "0.003", + "0.003" + ], + "res": "206.25", + "wire": "CFG_CENTER_DCIRESET_LOCKED" + }, + "RST": { + "cap": "1.615", + "delay": [ + "0.018", + "0.021", + "0.044", + "0.051" + ], + "wire": "CFG_CENTER_DCIRESET_RST" + } }, "type": "DCIRESET", "x_coord": 0, @@ -2268,17 +7158,116 @@ "name": "X0Y2", "prefix": "BSCAN", "site_pins": { - "CAPTURE": "CFG_CENTER_BSCAN3_CAPTURE", - "DRCK": "CFG_CENTER_BSCAN3_DRCK", - "RESET": "CFG_CENTER_BSCAN3_RESET", - "RUNTEST": "CFG_CENTER_BSCAN3_RUNTEST", - "SEL": "CFG_CENTER_BSCAN3_SEL", - "SHIFT": "CFG_CENTER_BSCAN3_SHIFT", - "TCK": "CFG_CENTER_BSCAN3_TCK", - "TDI": "CFG_CENTER_BSCAN3_TDI", - "TDO": "CFG_CENTER_BSCAN3_TDO", - "TMS": "CFG_CENTER_BSCAN3_TMS", - "UPDATE": "CFG_CENTER_BSCAN3_UPDATE" + "CAPTURE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_CAPTURE" + }, + "DRCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_DRCK" + }, + "RESET": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_RESET" + }, + "RUNTEST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_RUNTEST" + }, + "SEL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_SEL" + }, + "SHIFT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_SHIFT" + }, + "TCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_TCK" + }, + "TDI": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_TDI" + }, + "TDO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_BSCAN3_TDO" + }, + "TMS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_TMS" + }, + "UPDATE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN3_UPDATE" + } }, "type": "BSCAN", "x_coord": 0, @@ -2288,17 +7277,116 @@ "name": "X0Y3", "prefix": "BSCAN", "site_pins": { - "CAPTURE": "CFG_CENTER_BSCAN4_CAPTURE", - "DRCK": "CFG_CENTER_BSCAN4_DRCK", - "RESET": "CFG_CENTER_BSCAN4_RESET", - "RUNTEST": "CFG_CENTER_BSCAN4_RUNTEST", - "SEL": "CFG_CENTER_BSCAN4_SEL", - "SHIFT": "CFG_CENTER_BSCAN4_SHIFT", - "TCK": "CFG_CENTER_BSCAN4_TCK", - "TDI": "CFG_CENTER_BSCAN4_TDI", - "TDO": "CFG_CENTER_BSCAN4_TDO", - "TMS": "CFG_CENTER_BSCAN4_TMS", - "UPDATE": "CFG_CENTER_BSCAN4_UPDATE" + "CAPTURE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_CAPTURE" + }, + "DRCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_DRCK" + }, + "RESET": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_RESET" + }, + "RUNTEST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_RUNTEST" + }, + "SEL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_SEL" + }, + "SHIFT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_SHIFT" + }, + "TCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_TCK" + }, + "TDI": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_TDI" + }, + "TDO": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_BSCAN4_TDO" + }, + "TMS": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_TMS" + }, + "UPDATE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_BSCAN4_UPDATE" + } }, "type": "BSCAN", "x_coord": 0, @@ -2308,73 +7396,676 @@ "name": "X0Y1", "prefix": "ICAP", "site_pins": { - "CLK": "CFG_CENTER_ICAP1_CLK", - "CSIB": "CFG_CENTER_ICAP1_CSIB", - "I0": "CFG_CENTER_ICAP1_I0", - "I1": "CFG_CENTER_ICAP1_I1", - "I10": "CFG_CENTER_ICAP1_I10", - "I11": "CFG_CENTER_ICAP1_I11", - "I12": "CFG_CENTER_ICAP1_I12", - "I13": "CFG_CENTER_ICAP1_I13", - "I14": "CFG_CENTER_ICAP1_I14", - "I15": "CFG_CENTER_ICAP1_I15", - "I16": "CFG_CENTER_ICAP1_I16", - "I17": "CFG_CENTER_ICAP1_I17", - "I18": "CFG_CENTER_ICAP1_I18", - "I19": "CFG_CENTER_ICAP1_I19", - "I2": "CFG_CENTER_ICAP1_I2", - "I20": "CFG_CENTER_ICAP1_I20", - "I21": "CFG_CENTER_ICAP1_I21", - "I22": "CFG_CENTER_ICAP1_I22", - "I23": "CFG_CENTER_ICAP1_I23", - "I24": "CFG_CENTER_ICAP1_I24", - "I25": "CFG_CENTER_ICAP1_I25", - "I26": "CFG_CENTER_ICAP1_I26", - "I27": "CFG_CENTER_ICAP1_I27", - "I28": "CFG_CENTER_ICAP1_I28", - "I29": "CFG_CENTER_ICAP1_I29", - "I3": "CFG_CENTER_ICAP1_I3", - "I30": "CFG_CENTER_ICAP1_I30", - "I31": "CFG_CENTER_ICAP1_I31", - "I4": "CFG_CENTER_ICAP1_I4", - "I5": "CFG_CENTER_ICAP1_I5", - "I6": "CFG_CENTER_ICAP1_I6", - "I7": "CFG_CENTER_ICAP1_I7", - "I8": "CFG_CENTER_ICAP1_I8", - "I9": "CFG_CENTER_ICAP1_I9", - "O0": "CFG_CENTER_ICAP1_O0", - "O1": "CFG_CENTER_ICAP1_O1", - "O10": "CFG_CENTER_ICAP1_O10", - "O11": "CFG_CENTER_ICAP1_O11", - "O12": "CFG_CENTER_ICAP1_O12", - "O13": "CFG_CENTER_ICAP1_O13", - "O14": "CFG_CENTER_ICAP1_O14", - "O15": "CFG_CENTER_ICAP1_O15", - "O16": "CFG_CENTER_ICAP1_O16", - "O17": "CFG_CENTER_ICAP1_O17", - "O18": "CFG_CENTER_ICAP1_O18", - "O19": "CFG_CENTER_ICAP1_O19", - "O2": "CFG_CENTER_ICAP1_O2", - "O20": "CFG_CENTER_ICAP1_O20", - "O21": "CFG_CENTER_ICAP1_O21", - "O22": "CFG_CENTER_ICAP1_O22", - "O23": "CFG_CENTER_ICAP1_O23", - "O24": "CFG_CENTER_ICAP1_O24", - "O25": "CFG_CENTER_ICAP1_O25", - "O26": "CFG_CENTER_ICAP1_O26", - "O27": "CFG_CENTER_ICAP1_O27", - "O28": "CFG_CENTER_ICAP1_O28", - "O29": "CFG_CENTER_ICAP1_O29", - "O3": "CFG_CENTER_ICAP1_O3", - "O30": "CFG_CENTER_ICAP1_O30", - "O31": "CFG_CENTER_ICAP1_O31", - "O4": "CFG_CENTER_ICAP1_O4", - "O5": "CFG_CENTER_ICAP1_O5", - "O6": "CFG_CENTER_ICAP1_O6", - "O7": "CFG_CENTER_ICAP1_O7", - "O8": "CFG_CENTER_ICAP1_O8", - "O9": "CFG_CENTER_ICAP1_O9", - "RDWRB": "CFG_CENTER_ICAP1_RDWRB" + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_CLK" + }, + "CSIB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_CSIB" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I1" + }, + "I10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I10" + }, + "I11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I11" + }, + "I12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I12" + }, + "I13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I13" + }, + "I14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I14" + }, + "I15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I15" + }, + "I16": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I16" + }, + "I17": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I17" + }, + "I18": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I18" + }, + "I19": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I19" + }, + "I2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I2" + }, + "I20": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I20" + }, + "I21": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I21" + }, + "I22": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I22" + }, + "I23": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I23" + }, + "I24": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I24" + }, + "I25": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I25" + }, + "I26": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I26" + }, + "I27": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I27" + }, + "I28": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I28" + }, + "I29": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I29" + }, + "I3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I3" + }, + "I30": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I30" + }, + "I31": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I31" + }, + "I4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I4" + }, + "I5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I5" + }, + "I6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I6" + }, + "I7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I7" + }, + "I8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I8" + }, + "I9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_I9" + }, + "O0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O0" + }, + "O1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O1" + }, + "O10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O10" + }, + "O11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O11" + }, + "O12": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O12" + }, + "O13": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O13" + }, + "O14": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O14" + }, + "O15": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O15" + }, + "O16": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O16" + }, + "O17": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O17" + }, + "O18": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O18" + }, + "O19": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O19" + }, + "O2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O2" + }, + "O20": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O20" + }, + "O21": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O21" + }, + "O22": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O22" + }, + "O23": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O23" + }, + "O24": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O24" + }, + "O25": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O25" + }, + "O26": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O26" + }, + "O27": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O27" + }, + "O28": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O28" + }, + "O29": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O29" + }, + "O3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O3" + }, + "O30": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O30" + }, + "O31": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O31" + }, + "O4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O4" + }, + "O5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O5" + }, + "O6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O6" + }, + "O7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O7" + }, + "O8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O8" + }, + "O9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "206.25", + "wire": "CFG_CENTER_ICAP1_O9" + }, + "RDWRB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CFG_CENTER_ICAP1_RDWRB" + } }, "type": "ICAP", "x_coord": 0, @@ -2382,4806 +8073,17310 @@ } ], "tile_type": "CFG_CENTER_MID", - "wires": [ - "CFG_CENTER_BLOCK_OUTS_B0_0", - "CFG_CENTER_BLOCK_OUTS_B0_1", - "CFG_CENTER_BLOCK_OUTS_B0_10", - "CFG_CENTER_BLOCK_OUTS_B0_11", - "CFG_CENTER_BLOCK_OUTS_B0_12", - "CFG_CENTER_BLOCK_OUTS_B0_13", - "CFG_CENTER_BLOCK_OUTS_B0_14", - "CFG_CENTER_BLOCK_OUTS_B0_15", - "CFG_CENTER_BLOCK_OUTS_B0_16", - "CFG_CENTER_BLOCK_OUTS_B0_17", - "CFG_CENTER_BLOCK_OUTS_B0_18", - "CFG_CENTER_BLOCK_OUTS_B0_19", - "CFG_CENTER_BLOCK_OUTS_B0_2", - "CFG_CENTER_BLOCK_OUTS_B0_3", - "CFG_CENTER_BLOCK_OUTS_B0_4", - "CFG_CENTER_BLOCK_OUTS_B0_5", - "CFG_CENTER_BLOCK_OUTS_B0_6", - "CFG_CENTER_BLOCK_OUTS_B0_7", - "CFG_CENTER_BLOCK_OUTS_B0_8", - "CFG_CENTER_BLOCK_OUTS_B0_9", - "CFG_CENTER_BLOCK_OUTS_B1_0", - "CFG_CENTER_BLOCK_OUTS_B1_1", - "CFG_CENTER_BLOCK_OUTS_B1_10", - "CFG_CENTER_BLOCK_OUTS_B1_11", - "CFG_CENTER_BLOCK_OUTS_B1_12", - "CFG_CENTER_BLOCK_OUTS_B1_13", - "CFG_CENTER_BLOCK_OUTS_B1_14", - "CFG_CENTER_BLOCK_OUTS_B1_15", - "CFG_CENTER_BLOCK_OUTS_B1_16", - "CFG_CENTER_BLOCK_OUTS_B1_17", - "CFG_CENTER_BLOCK_OUTS_B1_18", - "CFG_CENTER_BLOCK_OUTS_B1_19", - "CFG_CENTER_BLOCK_OUTS_B1_2", - "CFG_CENTER_BLOCK_OUTS_B1_3", - "CFG_CENTER_BLOCK_OUTS_B1_4", - "CFG_CENTER_BLOCK_OUTS_B1_5", - "CFG_CENTER_BLOCK_OUTS_B1_6", - "CFG_CENTER_BLOCK_OUTS_B1_7", - "CFG_CENTER_BLOCK_OUTS_B1_8", - "CFG_CENTER_BLOCK_OUTS_B1_9", - "CFG_CENTER_BLOCK_OUTS_B2_0", - "CFG_CENTER_BLOCK_OUTS_B2_1", - "CFG_CENTER_BLOCK_OUTS_B2_10", - "CFG_CENTER_BLOCK_OUTS_B2_11", - "CFG_CENTER_BLOCK_OUTS_B2_12", - "CFG_CENTER_BLOCK_OUTS_B2_13", - "CFG_CENTER_BLOCK_OUTS_B2_14", - "CFG_CENTER_BLOCK_OUTS_B2_15", - "CFG_CENTER_BLOCK_OUTS_B2_16", - "CFG_CENTER_BLOCK_OUTS_B2_17", - "CFG_CENTER_BLOCK_OUTS_B2_18", - "CFG_CENTER_BLOCK_OUTS_B2_19", - "CFG_CENTER_BLOCK_OUTS_B2_2", - "CFG_CENTER_BLOCK_OUTS_B2_3", - "CFG_CENTER_BLOCK_OUTS_B2_4", - "CFG_CENTER_BLOCK_OUTS_B2_5", - "CFG_CENTER_BLOCK_OUTS_B2_6", - "CFG_CENTER_BLOCK_OUTS_B2_7", - "CFG_CENTER_BLOCK_OUTS_B2_8", - "CFG_CENTER_BLOCK_OUTS_B2_9", - "CFG_CENTER_BLOCK_OUTS_B3_0", - "CFG_CENTER_BLOCK_OUTS_B3_1", - "CFG_CENTER_BLOCK_OUTS_B3_10", - "CFG_CENTER_BLOCK_OUTS_B3_11", - "CFG_CENTER_BLOCK_OUTS_B3_12", - "CFG_CENTER_BLOCK_OUTS_B3_13", - "CFG_CENTER_BLOCK_OUTS_B3_14", - "CFG_CENTER_BLOCK_OUTS_B3_15", - "CFG_CENTER_BLOCK_OUTS_B3_16", - "CFG_CENTER_BLOCK_OUTS_B3_17", - "CFG_CENTER_BLOCK_OUTS_B3_18", - "CFG_CENTER_BLOCK_OUTS_B3_19", - "CFG_CENTER_BLOCK_OUTS_B3_2", - "CFG_CENTER_BLOCK_OUTS_B3_3", - "CFG_CENTER_BLOCK_OUTS_B3_4", - "CFG_CENTER_BLOCK_OUTS_B3_5", - "CFG_CENTER_BLOCK_OUTS_B3_6", - "CFG_CENTER_BLOCK_OUTS_B3_7", - "CFG_CENTER_BLOCK_OUTS_B3_8", - "CFG_CENTER_BLOCK_OUTS_B3_9", - "CFG_CENTER_BSCAN1_CAPTURE", - "CFG_CENTER_BSCAN1_DRCK", - "CFG_CENTER_BSCAN1_RESET", - "CFG_CENTER_BSCAN1_RUNTEST", - "CFG_CENTER_BSCAN1_SEL", - "CFG_CENTER_BSCAN1_SHIFT", - "CFG_CENTER_BSCAN1_TCK", - "CFG_CENTER_BSCAN1_TDI", - "CFG_CENTER_BSCAN1_TDO", - "CFG_CENTER_BSCAN1_TMS", - "CFG_CENTER_BSCAN1_UPDATE", - "CFG_CENTER_BSCAN2_CAPTURE", - "CFG_CENTER_BSCAN2_DRCK", - "CFG_CENTER_BSCAN2_RESET", - "CFG_CENTER_BSCAN2_RUNTEST", - "CFG_CENTER_BSCAN2_SEL", - "CFG_CENTER_BSCAN2_SHIFT", - "CFG_CENTER_BSCAN2_TCK", - "CFG_CENTER_BSCAN2_TDI", - "CFG_CENTER_BSCAN2_TDO", - "CFG_CENTER_BSCAN2_TMS", - "CFG_CENTER_BSCAN2_UPDATE", - "CFG_CENTER_BSCAN3_CAPTURE", - "CFG_CENTER_BSCAN3_DRCK", - "CFG_CENTER_BSCAN3_RESET", - "CFG_CENTER_BSCAN3_RUNTEST", - "CFG_CENTER_BSCAN3_SEL", - "CFG_CENTER_BSCAN3_SHIFT", - "CFG_CENTER_BSCAN3_TCK", - "CFG_CENTER_BSCAN3_TDI", - "CFG_CENTER_BSCAN3_TDO", - "CFG_CENTER_BSCAN3_TMS", - "CFG_CENTER_BSCAN3_UPDATE", - "CFG_CENTER_BSCAN4_CAPTURE", - "CFG_CENTER_BSCAN4_DRCK", - "CFG_CENTER_BSCAN4_RESET", - "CFG_CENTER_BSCAN4_RUNTEST", - "CFG_CENTER_BSCAN4_SEL", - "CFG_CENTER_BSCAN4_SHIFT", - "CFG_CENTER_BSCAN4_TCK", - "CFG_CENTER_BSCAN4_TDI", - "CFG_CENTER_BSCAN4_TDO", - "CFG_CENTER_BSCAN4_TMS", - "CFG_CENTER_BSCAN4_UPDATE", - "CFG_CENTER_BYP0_0", - "CFG_CENTER_BYP0_1", - "CFG_CENTER_BYP0_10", - "CFG_CENTER_BYP0_11", - "CFG_CENTER_BYP0_12", - "CFG_CENTER_BYP0_13", - "CFG_CENTER_BYP0_14", - "CFG_CENTER_BYP0_15", - "CFG_CENTER_BYP0_16", - "CFG_CENTER_BYP0_17", - "CFG_CENTER_BYP0_18", - "CFG_CENTER_BYP0_19", - "CFG_CENTER_BYP0_2", - "CFG_CENTER_BYP0_3", - "CFG_CENTER_BYP0_4", - "CFG_CENTER_BYP0_5", - "CFG_CENTER_BYP0_6", - "CFG_CENTER_BYP0_7", - "CFG_CENTER_BYP0_8", - "CFG_CENTER_BYP0_9", - "CFG_CENTER_BYP1_0", - "CFG_CENTER_BYP1_1", - "CFG_CENTER_BYP1_10", - "CFG_CENTER_BYP1_11", - "CFG_CENTER_BYP1_12", - "CFG_CENTER_BYP1_13", - "CFG_CENTER_BYP1_14", - "CFG_CENTER_BYP1_15", - "CFG_CENTER_BYP1_16", - "CFG_CENTER_BYP1_17", - "CFG_CENTER_BYP1_18", - "CFG_CENTER_BYP1_19", - "CFG_CENTER_BYP1_2", - "CFG_CENTER_BYP1_3", - "CFG_CENTER_BYP1_4", - "CFG_CENTER_BYP1_5", - "CFG_CENTER_BYP1_6", - "CFG_CENTER_BYP1_7", - "CFG_CENTER_BYP1_8", - "CFG_CENTER_BYP1_9", - "CFG_CENTER_BYP2_0", - "CFG_CENTER_BYP2_1", - "CFG_CENTER_BYP2_10", - "CFG_CENTER_BYP2_11", - "CFG_CENTER_BYP2_12", - "CFG_CENTER_BYP2_13", - "CFG_CENTER_BYP2_14", - "CFG_CENTER_BYP2_15", - "CFG_CENTER_BYP2_16", - "CFG_CENTER_BYP2_17", - "CFG_CENTER_BYP2_18", - "CFG_CENTER_BYP2_19", - "CFG_CENTER_BYP2_2", - "CFG_CENTER_BYP2_3", - "CFG_CENTER_BYP2_4", - "CFG_CENTER_BYP2_5", - "CFG_CENTER_BYP2_6", - "CFG_CENTER_BYP2_7", - "CFG_CENTER_BYP2_8", - "CFG_CENTER_BYP2_9", - "CFG_CENTER_BYP3_0", - "CFG_CENTER_BYP3_1", - "CFG_CENTER_BYP3_10", - "CFG_CENTER_BYP3_11", - "CFG_CENTER_BYP3_12", - "CFG_CENTER_BYP3_13", - "CFG_CENTER_BYP3_14", - "CFG_CENTER_BYP3_15", - "CFG_CENTER_BYP3_16", - "CFG_CENTER_BYP3_17", - "CFG_CENTER_BYP3_18", - "CFG_CENTER_BYP3_19", - "CFG_CENTER_BYP3_2", - "CFG_CENTER_BYP3_3", - "CFG_CENTER_BYP3_4", - "CFG_CENTER_BYP3_5", - "CFG_CENTER_BYP3_6", - "CFG_CENTER_BYP3_7", - "CFG_CENTER_BYP3_8", - "CFG_CENTER_BYP3_9", - "CFG_CENTER_BYP4_0", - "CFG_CENTER_BYP4_1", - "CFG_CENTER_BYP4_10", - "CFG_CENTER_BYP4_11", - "CFG_CENTER_BYP4_12", - "CFG_CENTER_BYP4_13", - "CFG_CENTER_BYP4_14", - "CFG_CENTER_BYP4_15", - "CFG_CENTER_BYP4_16", - "CFG_CENTER_BYP4_17", - "CFG_CENTER_BYP4_18", - "CFG_CENTER_BYP4_19", - "CFG_CENTER_BYP4_2", - "CFG_CENTER_BYP4_3", - "CFG_CENTER_BYP4_4", - "CFG_CENTER_BYP4_5", - "CFG_CENTER_BYP4_6", - "CFG_CENTER_BYP4_7", - "CFG_CENTER_BYP4_8", - "CFG_CENTER_BYP4_9", - "CFG_CENTER_BYP5_0", - "CFG_CENTER_BYP5_1", - "CFG_CENTER_BYP5_10", - "CFG_CENTER_BYP5_11", - "CFG_CENTER_BYP5_12", - "CFG_CENTER_BYP5_13", - "CFG_CENTER_BYP5_14", - "CFG_CENTER_BYP5_15", - "CFG_CENTER_BYP5_16", - "CFG_CENTER_BYP5_17", - "CFG_CENTER_BYP5_18", - "CFG_CENTER_BYP5_19", - "CFG_CENTER_BYP5_2", - "CFG_CENTER_BYP5_3", - "CFG_CENTER_BYP5_4", - "CFG_CENTER_BYP5_5", - "CFG_CENTER_BYP5_6", - "CFG_CENTER_BYP5_7", - "CFG_CENTER_BYP5_8", - "CFG_CENTER_BYP5_9", - "CFG_CENTER_BYP6_0", - "CFG_CENTER_BYP6_1", - "CFG_CENTER_BYP6_10", - "CFG_CENTER_BYP6_11", - "CFG_CENTER_BYP6_12", - "CFG_CENTER_BYP6_13", - "CFG_CENTER_BYP6_14", - "CFG_CENTER_BYP6_15", - "CFG_CENTER_BYP6_16", - "CFG_CENTER_BYP6_17", - "CFG_CENTER_BYP6_18", - "CFG_CENTER_BYP6_19", - "CFG_CENTER_BYP6_2", - "CFG_CENTER_BYP6_3", - "CFG_CENTER_BYP6_4", - "CFG_CENTER_BYP6_5", - "CFG_CENTER_BYP6_6", - "CFG_CENTER_BYP6_7", - "CFG_CENTER_BYP6_8", - "CFG_CENTER_BYP6_9", - "CFG_CENTER_BYP7_0", - "CFG_CENTER_BYP7_1", - "CFG_CENTER_BYP7_10", - "CFG_CENTER_BYP7_11", - "CFG_CENTER_BYP7_12", - "CFG_CENTER_BYP7_13", - "CFG_CENTER_BYP7_14", - "CFG_CENTER_BYP7_15", - "CFG_CENTER_BYP7_16", - "CFG_CENTER_BYP7_17", - "CFG_CENTER_BYP7_18", - "CFG_CENTER_BYP7_19", - "CFG_CENTER_BYP7_2", - "CFG_CENTER_BYP7_3", - "CFG_CENTER_BYP7_4", - "CFG_CENTER_BYP7_5", - "CFG_CENTER_BYP7_6", - "CFG_CENTER_BYP7_7", - "CFG_CENTER_BYP7_8", - "CFG_CENTER_BYP7_9", - "CFG_CENTER_CAPTURE_CAP", - "CFG_CENTER_CAPTURE_CLK", - "CFG_CENTER_CFG_IO_ACCESS_CCLK", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA0", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA1", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA10", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA2", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA3", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA4", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA5", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA6", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA7", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA8", - "CFG_CENTER_CFG_IO_ACCESS_CFGDATA9", - "CFG_CENTER_CFG_IO_ACCESS_INITBI", - "CFG_CENTER_CFG_IO_ACCESS_INITBO", - "CFG_CENTER_CFG_IO_ACCESS_MASTER", - "CFG_CENTER_CFG_IO_ACCESS_MODE0", - "CFG_CENTER_CFG_IO_ACCESS_MODE1", - "CFG_CENTER_CFG_IO_ACCESS_MODE2", - "CFG_CENTER_CFG_IO_ACCESS_PUDCB", - "CFG_CENTER_CFG_IO_ACCESS_RDWRB", - "CFG_CENTER_CFG_IO_ACCESS_TDO", - "CFG_CENTER_CFG_IO_ACCESS_VGGCOMPOUT", - "CFG_CENTER_CK_BUFHCLK0", - "CFG_CENTER_CK_BUFHCLK1", - "CFG_CENTER_CK_BUFHCLK10", - "CFG_CENTER_CK_BUFHCLK11", - "CFG_CENTER_CK_BUFHCLK2", - "CFG_CENTER_CK_BUFHCLK3", - "CFG_CENTER_CK_BUFHCLK4", - "CFG_CENTER_CK_BUFHCLK5", - "CFG_CENTER_CK_BUFHCLK6", - "CFG_CENTER_CK_BUFHCLK7", - "CFG_CENTER_CK_BUFHCLK8", - "CFG_CENTER_CK_BUFHCLK9", - "CFG_CENTER_CK_BUFRCLK0", - "CFG_CENTER_CK_BUFRCLK1", - "CFG_CENTER_CK_BUFRCLK2", - "CFG_CENTER_CK_BUFRCLK3", - "CFG_CENTER_CK_IN0", - "CFG_CENTER_CK_IN1", - "CFG_CENTER_CK_IN10", - "CFG_CENTER_CK_IN11", - "CFG_CENTER_CK_IN12", - "CFG_CENTER_CK_IN13", - "CFG_CENTER_CK_IN2", - "CFG_CENTER_CK_IN3", - "CFG_CENTER_CK_IN4", - "CFG_CENTER_CK_IN5", - "CFG_CENTER_CK_IN6", - "CFG_CENTER_CK_IN7", - "CFG_CENTER_CK_IN8", - "CFG_CENTER_CK_IN9", - "CFG_CENTER_CLK0_0", - "CFG_CENTER_CLK0_1", - "CFG_CENTER_CLK0_10", - "CFG_CENTER_CLK0_11", - "CFG_CENTER_CLK0_12", - "CFG_CENTER_CLK0_13", - "CFG_CENTER_CLK0_14", - "CFG_CENTER_CLK0_15", - "CFG_CENTER_CLK0_16", - "CFG_CENTER_CLK0_17", - "CFG_CENTER_CLK0_18", - "CFG_CENTER_CLK0_19", - "CFG_CENTER_CLK0_2", - "CFG_CENTER_CLK0_3", - "CFG_CENTER_CLK0_4", - "CFG_CENTER_CLK0_5", - "CFG_CENTER_CLK0_6", - "CFG_CENTER_CLK0_7", - "CFG_CENTER_CLK0_8", - "CFG_CENTER_CLK0_9", - "CFG_CENTER_CLK1_0", - "CFG_CENTER_CLK1_1", - "CFG_CENTER_CLK1_10", - "CFG_CENTER_CLK1_11", - "CFG_CENTER_CLK1_12", - "CFG_CENTER_CLK1_13", - "CFG_CENTER_CLK1_14", - "CFG_CENTER_CLK1_15", - "CFG_CENTER_CLK1_16", - "CFG_CENTER_CLK1_17", - "CFG_CENTER_CLK1_18", - "CFG_CENTER_CLK1_19", - "CFG_CENTER_CLK1_2", - "CFG_CENTER_CLK1_3", - "CFG_CENTER_CLK1_4", - "CFG_CENTER_CLK1_5", - "CFG_CENTER_CLK1_6", - "CFG_CENTER_CLK1_7", - "CFG_CENTER_CLK1_8", - "CFG_CENTER_CLK1_9", - "CFG_CENTER_CTRL0_0", - "CFG_CENTER_CTRL0_1", - "CFG_CENTER_CTRL0_10", - "CFG_CENTER_CTRL0_11", - "CFG_CENTER_CTRL0_12", - "CFG_CENTER_CTRL0_13", - "CFG_CENTER_CTRL0_14", - "CFG_CENTER_CTRL0_15", - "CFG_CENTER_CTRL0_16", - "CFG_CENTER_CTRL0_17", - "CFG_CENTER_CTRL0_18", - "CFG_CENTER_CTRL0_19", - "CFG_CENTER_CTRL0_2", - "CFG_CENTER_CTRL0_3", - "CFG_CENTER_CTRL0_4", - "CFG_CENTER_CTRL0_5", - "CFG_CENTER_CTRL0_6", - "CFG_CENTER_CTRL0_7", - "CFG_CENTER_CTRL0_8", - "CFG_CENTER_CTRL0_9", - "CFG_CENTER_CTRL1_0", - "CFG_CENTER_CTRL1_1", - "CFG_CENTER_CTRL1_10", - "CFG_CENTER_CTRL1_11", - "CFG_CENTER_CTRL1_12", - "CFG_CENTER_CTRL1_13", - "CFG_CENTER_CTRL1_14", - "CFG_CENTER_CTRL1_15", - "CFG_CENTER_CTRL1_16", - "CFG_CENTER_CTRL1_17", - "CFG_CENTER_CTRL1_18", - "CFG_CENTER_CTRL1_19", - "CFG_CENTER_CTRL1_2", - "CFG_CENTER_CTRL1_3", - "CFG_CENTER_CTRL1_4", - "CFG_CENTER_CTRL1_5", - "CFG_CENTER_CTRL1_6", - "CFG_CENTER_CTRL1_7", - "CFG_CENTER_CTRL1_8", - "CFG_CENTER_CTRL1_9", - "CFG_CENTER_DCIRESET_LOCKED", - "CFG_CENTER_DCIRESET_RST", - "CFG_CENTER_EE2A0_0", - "CFG_CENTER_EE2A0_1", - "CFG_CENTER_EE2A0_10", - "CFG_CENTER_EE2A0_11", - "CFG_CENTER_EE2A0_12", - "CFG_CENTER_EE2A0_13", - "CFG_CENTER_EE2A0_14", - "CFG_CENTER_EE2A0_15", - "CFG_CENTER_EE2A0_16", - "CFG_CENTER_EE2A0_17", - "CFG_CENTER_EE2A0_18", - "CFG_CENTER_EE2A0_19", - "CFG_CENTER_EE2A0_2", - "CFG_CENTER_EE2A0_3", - "CFG_CENTER_EE2A0_4", - "CFG_CENTER_EE2A0_5", - "CFG_CENTER_EE2A0_6", - "CFG_CENTER_EE2A0_7", - "CFG_CENTER_EE2A0_8", - "CFG_CENTER_EE2A0_9", - "CFG_CENTER_EE2A1_0", - "CFG_CENTER_EE2A1_1", - "CFG_CENTER_EE2A1_10", - "CFG_CENTER_EE2A1_11", - "CFG_CENTER_EE2A1_12", - "CFG_CENTER_EE2A1_13", - "CFG_CENTER_EE2A1_14", - "CFG_CENTER_EE2A1_15", - "CFG_CENTER_EE2A1_16", - "CFG_CENTER_EE2A1_17", - "CFG_CENTER_EE2A1_18", - "CFG_CENTER_EE2A1_19", - "CFG_CENTER_EE2A1_2", - "CFG_CENTER_EE2A1_3", - "CFG_CENTER_EE2A1_4", - "CFG_CENTER_EE2A1_5", - "CFG_CENTER_EE2A1_6", - "CFG_CENTER_EE2A1_7", - "CFG_CENTER_EE2A1_8", - "CFG_CENTER_EE2A1_9", - "CFG_CENTER_EE2A2_0", - "CFG_CENTER_EE2A2_1", - "CFG_CENTER_EE2A2_10", - "CFG_CENTER_EE2A2_11", - "CFG_CENTER_EE2A2_12", - "CFG_CENTER_EE2A2_13", - "CFG_CENTER_EE2A2_14", - "CFG_CENTER_EE2A2_15", - "CFG_CENTER_EE2A2_16", - "CFG_CENTER_EE2A2_17", - "CFG_CENTER_EE2A2_18", - "CFG_CENTER_EE2A2_19", - "CFG_CENTER_EE2A2_2", - "CFG_CENTER_EE2A2_3", - "CFG_CENTER_EE2A2_4", - "CFG_CENTER_EE2A2_5", - "CFG_CENTER_EE2A2_6", - "CFG_CENTER_EE2A2_7", - "CFG_CENTER_EE2A2_8", - "CFG_CENTER_EE2A2_9", - "CFG_CENTER_EE2A3_0", - "CFG_CENTER_EE2A3_1", - "CFG_CENTER_EE2A3_10", - "CFG_CENTER_EE2A3_11", - "CFG_CENTER_EE2A3_12", - "CFG_CENTER_EE2A3_13", - "CFG_CENTER_EE2A3_14", - "CFG_CENTER_EE2A3_15", - "CFG_CENTER_EE2A3_16", - "CFG_CENTER_EE2A3_17", - "CFG_CENTER_EE2A3_18", - "CFG_CENTER_EE2A3_19", - "CFG_CENTER_EE2A3_2", - "CFG_CENTER_EE2A3_3", - "CFG_CENTER_EE2A3_4", - "CFG_CENTER_EE2A3_5", - "CFG_CENTER_EE2A3_6", - "CFG_CENTER_EE2A3_7", - "CFG_CENTER_EE2A3_8", - "CFG_CENTER_EE2A3_9", - "CFG_CENTER_EE2BEG0_0", - "CFG_CENTER_EE2BEG0_1", - "CFG_CENTER_EE2BEG0_10", - "CFG_CENTER_EE2BEG0_11", - "CFG_CENTER_EE2BEG0_12", - "CFG_CENTER_EE2BEG0_13", - "CFG_CENTER_EE2BEG0_14", - "CFG_CENTER_EE2BEG0_15", - "CFG_CENTER_EE2BEG0_16", - "CFG_CENTER_EE2BEG0_17", - "CFG_CENTER_EE2BEG0_18", - "CFG_CENTER_EE2BEG0_19", - "CFG_CENTER_EE2BEG0_2", - "CFG_CENTER_EE2BEG0_3", - "CFG_CENTER_EE2BEG0_4", - "CFG_CENTER_EE2BEG0_5", - "CFG_CENTER_EE2BEG0_6", - "CFG_CENTER_EE2BEG0_7", - "CFG_CENTER_EE2BEG0_8", - "CFG_CENTER_EE2BEG0_9", - "CFG_CENTER_EE2BEG1_0", - "CFG_CENTER_EE2BEG1_1", - "CFG_CENTER_EE2BEG1_10", - "CFG_CENTER_EE2BEG1_11", - "CFG_CENTER_EE2BEG1_12", - "CFG_CENTER_EE2BEG1_13", - "CFG_CENTER_EE2BEG1_14", - "CFG_CENTER_EE2BEG1_15", - "CFG_CENTER_EE2BEG1_16", - "CFG_CENTER_EE2BEG1_17", - "CFG_CENTER_EE2BEG1_18", - "CFG_CENTER_EE2BEG1_19", - "CFG_CENTER_EE2BEG1_2", - "CFG_CENTER_EE2BEG1_3", - "CFG_CENTER_EE2BEG1_4", - "CFG_CENTER_EE2BEG1_5", - "CFG_CENTER_EE2BEG1_6", - "CFG_CENTER_EE2BEG1_7", - "CFG_CENTER_EE2BEG1_8", - "CFG_CENTER_EE2BEG1_9", - "CFG_CENTER_EE2BEG2_0", - "CFG_CENTER_EE2BEG2_1", - "CFG_CENTER_EE2BEG2_10", - "CFG_CENTER_EE2BEG2_11", - "CFG_CENTER_EE2BEG2_12", - "CFG_CENTER_EE2BEG2_13", - "CFG_CENTER_EE2BEG2_14", - "CFG_CENTER_EE2BEG2_15", - "CFG_CENTER_EE2BEG2_16", - "CFG_CENTER_EE2BEG2_17", - "CFG_CENTER_EE2BEG2_18", - "CFG_CENTER_EE2BEG2_19", - "CFG_CENTER_EE2BEG2_2", - "CFG_CENTER_EE2BEG2_3", - "CFG_CENTER_EE2BEG2_4", - "CFG_CENTER_EE2BEG2_5", - "CFG_CENTER_EE2BEG2_6", - "CFG_CENTER_EE2BEG2_7", - "CFG_CENTER_EE2BEG2_8", - "CFG_CENTER_EE2BEG2_9", - "CFG_CENTER_EE2BEG3_0", - "CFG_CENTER_EE2BEG3_1", - "CFG_CENTER_EE2BEG3_10", - "CFG_CENTER_EE2BEG3_11", - "CFG_CENTER_EE2BEG3_12", - "CFG_CENTER_EE2BEG3_13", - "CFG_CENTER_EE2BEG3_14", - "CFG_CENTER_EE2BEG3_15", - "CFG_CENTER_EE2BEG3_16", - "CFG_CENTER_EE2BEG3_17", - "CFG_CENTER_EE2BEG3_18", - "CFG_CENTER_EE2BEG3_19", - "CFG_CENTER_EE2BEG3_2", - "CFG_CENTER_EE2BEG3_3", - "CFG_CENTER_EE2BEG3_4", - "CFG_CENTER_EE2BEG3_5", - "CFG_CENTER_EE2BEG3_6", - "CFG_CENTER_EE2BEG3_7", - "CFG_CENTER_EE2BEG3_8", - "CFG_CENTER_EE2BEG3_9", - "CFG_CENTER_EE4A0_0", - "CFG_CENTER_EE4A0_1", - "CFG_CENTER_EE4A0_10", - "CFG_CENTER_EE4A0_11", - "CFG_CENTER_EE4A0_12", - "CFG_CENTER_EE4A0_13", - "CFG_CENTER_EE4A0_14", - "CFG_CENTER_EE4A0_15", - "CFG_CENTER_EE4A0_16", - "CFG_CENTER_EE4A0_17", - "CFG_CENTER_EE4A0_18", - "CFG_CENTER_EE4A0_19", - "CFG_CENTER_EE4A0_2", - "CFG_CENTER_EE4A0_3", - "CFG_CENTER_EE4A0_4", - "CFG_CENTER_EE4A0_5", - "CFG_CENTER_EE4A0_6", - "CFG_CENTER_EE4A0_7", - "CFG_CENTER_EE4A0_8", - "CFG_CENTER_EE4A0_9", - "CFG_CENTER_EE4A1_0", - "CFG_CENTER_EE4A1_1", - "CFG_CENTER_EE4A1_10", - "CFG_CENTER_EE4A1_11", - "CFG_CENTER_EE4A1_12", - "CFG_CENTER_EE4A1_13", - "CFG_CENTER_EE4A1_14", - "CFG_CENTER_EE4A1_15", - "CFG_CENTER_EE4A1_16", - "CFG_CENTER_EE4A1_17", - "CFG_CENTER_EE4A1_18", - "CFG_CENTER_EE4A1_19", - "CFG_CENTER_EE4A1_2", - "CFG_CENTER_EE4A1_3", - "CFG_CENTER_EE4A1_4", - "CFG_CENTER_EE4A1_5", - "CFG_CENTER_EE4A1_6", - "CFG_CENTER_EE4A1_7", - "CFG_CENTER_EE4A1_8", - "CFG_CENTER_EE4A1_9", - "CFG_CENTER_EE4A2_0", - "CFG_CENTER_EE4A2_1", - "CFG_CENTER_EE4A2_10", - "CFG_CENTER_EE4A2_11", - "CFG_CENTER_EE4A2_12", - "CFG_CENTER_EE4A2_13", - "CFG_CENTER_EE4A2_14", - "CFG_CENTER_EE4A2_15", - "CFG_CENTER_EE4A2_16", - "CFG_CENTER_EE4A2_17", - "CFG_CENTER_EE4A2_18", - "CFG_CENTER_EE4A2_19", - "CFG_CENTER_EE4A2_2", - "CFG_CENTER_EE4A2_3", - "CFG_CENTER_EE4A2_4", - "CFG_CENTER_EE4A2_5", - "CFG_CENTER_EE4A2_6", - "CFG_CENTER_EE4A2_7", - "CFG_CENTER_EE4A2_8", - "CFG_CENTER_EE4A2_9", - "CFG_CENTER_EE4A3_0", - "CFG_CENTER_EE4A3_1", - "CFG_CENTER_EE4A3_10", - "CFG_CENTER_EE4A3_11", - "CFG_CENTER_EE4A3_12", - "CFG_CENTER_EE4A3_13", - "CFG_CENTER_EE4A3_14", - "CFG_CENTER_EE4A3_15", - "CFG_CENTER_EE4A3_16", - "CFG_CENTER_EE4A3_17", - "CFG_CENTER_EE4A3_18", - "CFG_CENTER_EE4A3_19", - "CFG_CENTER_EE4A3_2", - "CFG_CENTER_EE4A3_3", - "CFG_CENTER_EE4A3_4", - "CFG_CENTER_EE4A3_5", - "CFG_CENTER_EE4A3_6", - "CFG_CENTER_EE4A3_7", - "CFG_CENTER_EE4A3_8", - "CFG_CENTER_EE4A3_9", - "CFG_CENTER_EE4B0_0", - "CFG_CENTER_EE4B0_1", - "CFG_CENTER_EE4B0_10", - "CFG_CENTER_EE4B0_11", - "CFG_CENTER_EE4B0_12", - "CFG_CENTER_EE4B0_13", - "CFG_CENTER_EE4B0_14", - "CFG_CENTER_EE4B0_15", - "CFG_CENTER_EE4B0_16", - "CFG_CENTER_EE4B0_17", - "CFG_CENTER_EE4B0_18", - "CFG_CENTER_EE4B0_19", - "CFG_CENTER_EE4B0_2", - "CFG_CENTER_EE4B0_3", - "CFG_CENTER_EE4B0_4", - "CFG_CENTER_EE4B0_5", - "CFG_CENTER_EE4B0_6", - "CFG_CENTER_EE4B0_7", - "CFG_CENTER_EE4B0_8", - "CFG_CENTER_EE4B0_9", - "CFG_CENTER_EE4B1_0", - "CFG_CENTER_EE4B1_1", - "CFG_CENTER_EE4B1_10", - "CFG_CENTER_EE4B1_11", - "CFG_CENTER_EE4B1_12", - "CFG_CENTER_EE4B1_13", - "CFG_CENTER_EE4B1_14", - "CFG_CENTER_EE4B1_15", - "CFG_CENTER_EE4B1_16", - "CFG_CENTER_EE4B1_17", - "CFG_CENTER_EE4B1_18", - "CFG_CENTER_EE4B1_19", - "CFG_CENTER_EE4B1_2", - "CFG_CENTER_EE4B1_3", - "CFG_CENTER_EE4B1_4", - "CFG_CENTER_EE4B1_5", - "CFG_CENTER_EE4B1_6", - "CFG_CENTER_EE4B1_7", - "CFG_CENTER_EE4B1_8", - "CFG_CENTER_EE4B1_9", - "CFG_CENTER_EE4B2_0", - "CFG_CENTER_EE4B2_1", - "CFG_CENTER_EE4B2_10", - "CFG_CENTER_EE4B2_11", - "CFG_CENTER_EE4B2_12", - "CFG_CENTER_EE4B2_13", - "CFG_CENTER_EE4B2_14", - "CFG_CENTER_EE4B2_15", - "CFG_CENTER_EE4B2_16", - "CFG_CENTER_EE4B2_17", - "CFG_CENTER_EE4B2_18", - "CFG_CENTER_EE4B2_19", - "CFG_CENTER_EE4B2_2", - "CFG_CENTER_EE4B2_3", - "CFG_CENTER_EE4B2_4", - "CFG_CENTER_EE4B2_5", - "CFG_CENTER_EE4B2_6", - "CFG_CENTER_EE4B2_7", - "CFG_CENTER_EE4B2_8", - "CFG_CENTER_EE4B2_9", - "CFG_CENTER_EE4B3_0", - "CFG_CENTER_EE4B3_1", - "CFG_CENTER_EE4B3_10", - "CFG_CENTER_EE4B3_11", - "CFG_CENTER_EE4B3_12", - "CFG_CENTER_EE4B3_13", - "CFG_CENTER_EE4B3_14", - "CFG_CENTER_EE4B3_15", - "CFG_CENTER_EE4B3_16", - "CFG_CENTER_EE4B3_17", - "CFG_CENTER_EE4B3_18", - "CFG_CENTER_EE4B3_19", - "CFG_CENTER_EE4B3_2", - "CFG_CENTER_EE4B3_3", - "CFG_CENTER_EE4B3_4", - "CFG_CENTER_EE4B3_5", - "CFG_CENTER_EE4B3_6", - "CFG_CENTER_EE4B3_7", - "CFG_CENTER_EE4B3_8", - "CFG_CENTER_EE4B3_9", - "CFG_CENTER_EE4BEG0_0", - "CFG_CENTER_EE4BEG0_1", - "CFG_CENTER_EE4BEG0_10", - "CFG_CENTER_EE4BEG0_11", - "CFG_CENTER_EE4BEG0_12", - "CFG_CENTER_EE4BEG0_13", - "CFG_CENTER_EE4BEG0_14", - "CFG_CENTER_EE4BEG0_15", - "CFG_CENTER_EE4BEG0_16", - "CFG_CENTER_EE4BEG0_17", - "CFG_CENTER_EE4BEG0_18", - "CFG_CENTER_EE4BEG0_19", - "CFG_CENTER_EE4BEG0_2", - "CFG_CENTER_EE4BEG0_3", - "CFG_CENTER_EE4BEG0_4", - "CFG_CENTER_EE4BEG0_5", - "CFG_CENTER_EE4BEG0_6", - "CFG_CENTER_EE4BEG0_7", - "CFG_CENTER_EE4BEG0_8", - "CFG_CENTER_EE4BEG0_9", - "CFG_CENTER_EE4BEG1_0", - "CFG_CENTER_EE4BEG1_1", - "CFG_CENTER_EE4BEG1_10", - "CFG_CENTER_EE4BEG1_11", - "CFG_CENTER_EE4BEG1_12", - "CFG_CENTER_EE4BEG1_13", - "CFG_CENTER_EE4BEG1_14", - "CFG_CENTER_EE4BEG1_15", - "CFG_CENTER_EE4BEG1_16", - "CFG_CENTER_EE4BEG1_17", - "CFG_CENTER_EE4BEG1_18", - "CFG_CENTER_EE4BEG1_19", - "CFG_CENTER_EE4BEG1_2", - "CFG_CENTER_EE4BEG1_3", - "CFG_CENTER_EE4BEG1_4", - "CFG_CENTER_EE4BEG1_5", - "CFG_CENTER_EE4BEG1_6", - "CFG_CENTER_EE4BEG1_7", - "CFG_CENTER_EE4BEG1_8", - "CFG_CENTER_EE4BEG1_9", - "CFG_CENTER_EE4BEG2_0", - "CFG_CENTER_EE4BEG2_1", - "CFG_CENTER_EE4BEG2_10", - "CFG_CENTER_EE4BEG2_11", - "CFG_CENTER_EE4BEG2_12", - "CFG_CENTER_EE4BEG2_13", - "CFG_CENTER_EE4BEG2_14", - "CFG_CENTER_EE4BEG2_15", - "CFG_CENTER_EE4BEG2_16", - "CFG_CENTER_EE4BEG2_17", - "CFG_CENTER_EE4BEG2_18", - "CFG_CENTER_EE4BEG2_19", - "CFG_CENTER_EE4BEG2_2", - "CFG_CENTER_EE4BEG2_3", - "CFG_CENTER_EE4BEG2_4", - "CFG_CENTER_EE4BEG2_5", - "CFG_CENTER_EE4BEG2_6", - "CFG_CENTER_EE4BEG2_7", - "CFG_CENTER_EE4BEG2_8", - "CFG_CENTER_EE4BEG2_9", - "CFG_CENTER_EE4BEG3_0", - "CFG_CENTER_EE4BEG3_1", - "CFG_CENTER_EE4BEG3_10", - "CFG_CENTER_EE4BEG3_11", - "CFG_CENTER_EE4BEG3_12", - "CFG_CENTER_EE4BEG3_13", - "CFG_CENTER_EE4BEG3_14", - "CFG_CENTER_EE4BEG3_15", - "CFG_CENTER_EE4BEG3_16", - "CFG_CENTER_EE4BEG3_17", - "CFG_CENTER_EE4BEG3_18", - "CFG_CENTER_EE4BEG3_19", - "CFG_CENTER_EE4BEG3_2", - "CFG_CENTER_EE4BEG3_3", - "CFG_CENTER_EE4BEG3_4", - "CFG_CENTER_EE4BEG3_5", - "CFG_CENTER_EE4BEG3_6", - "CFG_CENTER_EE4BEG3_7", - "CFG_CENTER_EE4BEG3_8", - "CFG_CENTER_EE4BEG3_9", - "CFG_CENTER_EE4C0_0", - "CFG_CENTER_EE4C0_1", - "CFG_CENTER_EE4C0_10", - "CFG_CENTER_EE4C0_11", - "CFG_CENTER_EE4C0_12", - "CFG_CENTER_EE4C0_13", - "CFG_CENTER_EE4C0_14", - "CFG_CENTER_EE4C0_15", - "CFG_CENTER_EE4C0_16", - "CFG_CENTER_EE4C0_17", - "CFG_CENTER_EE4C0_18", - "CFG_CENTER_EE4C0_19", - "CFG_CENTER_EE4C0_2", - "CFG_CENTER_EE4C0_3", - "CFG_CENTER_EE4C0_4", - "CFG_CENTER_EE4C0_5", - "CFG_CENTER_EE4C0_6", - "CFG_CENTER_EE4C0_7", - "CFG_CENTER_EE4C0_8", - "CFG_CENTER_EE4C0_9", - "CFG_CENTER_EE4C1_0", - "CFG_CENTER_EE4C1_1", - "CFG_CENTER_EE4C1_10", - "CFG_CENTER_EE4C1_11", - "CFG_CENTER_EE4C1_12", - "CFG_CENTER_EE4C1_13", - "CFG_CENTER_EE4C1_14", - "CFG_CENTER_EE4C1_15", - "CFG_CENTER_EE4C1_16", - "CFG_CENTER_EE4C1_17", - "CFG_CENTER_EE4C1_18", - "CFG_CENTER_EE4C1_19", - "CFG_CENTER_EE4C1_2", - "CFG_CENTER_EE4C1_3", - "CFG_CENTER_EE4C1_4", - "CFG_CENTER_EE4C1_5", - "CFG_CENTER_EE4C1_6", - "CFG_CENTER_EE4C1_7", - "CFG_CENTER_EE4C1_8", - "CFG_CENTER_EE4C1_9", - "CFG_CENTER_EE4C2_0", - "CFG_CENTER_EE4C2_1", - "CFG_CENTER_EE4C2_10", - "CFG_CENTER_EE4C2_11", - "CFG_CENTER_EE4C2_12", - "CFG_CENTER_EE4C2_13", - "CFG_CENTER_EE4C2_14", - "CFG_CENTER_EE4C2_15", - "CFG_CENTER_EE4C2_16", - "CFG_CENTER_EE4C2_17", - "CFG_CENTER_EE4C2_18", - "CFG_CENTER_EE4C2_19", - "CFG_CENTER_EE4C2_2", - "CFG_CENTER_EE4C2_3", - "CFG_CENTER_EE4C2_4", - "CFG_CENTER_EE4C2_5", - "CFG_CENTER_EE4C2_6", - "CFG_CENTER_EE4C2_7", - "CFG_CENTER_EE4C2_8", - "CFG_CENTER_EE4C2_9", - "CFG_CENTER_EE4C3_0", - "CFG_CENTER_EE4C3_1", - "CFG_CENTER_EE4C3_10", - "CFG_CENTER_EE4C3_11", - "CFG_CENTER_EE4C3_12", - "CFG_CENTER_EE4C3_13", - "CFG_CENTER_EE4C3_14", - "CFG_CENTER_EE4C3_15", - "CFG_CENTER_EE4C3_16", - "CFG_CENTER_EE4C3_17", - "CFG_CENTER_EE4C3_18", - "CFG_CENTER_EE4C3_19", - "CFG_CENTER_EE4C3_2", - "CFG_CENTER_EE4C3_3", - "CFG_CENTER_EE4C3_4", - "CFG_CENTER_EE4C3_5", - "CFG_CENTER_EE4C3_6", - "CFG_CENTER_EE4C3_7", - "CFG_CENTER_EE4C3_8", - "CFG_CENTER_EE4C3_9", - "CFG_CENTER_EL1BEG0_0", - "CFG_CENTER_EL1BEG0_1", - "CFG_CENTER_EL1BEG0_10", - "CFG_CENTER_EL1BEG0_11", - "CFG_CENTER_EL1BEG0_12", - "CFG_CENTER_EL1BEG0_13", - "CFG_CENTER_EL1BEG0_14", - "CFG_CENTER_EL1BEG0_15", - "CFG_CENTER_EL1BEG0_16", - "CFG_CENTER_EL1BEG0_17", - "CFG_CENTER_EL1BEG0_18", - "CFG_CENTER_EL1BEG0_19", - "CFG_CENTER_EL1BEG0_2", - "CFG_CENTER_EL1BEG0_3", - "CFG_CENTER_EL1BEG0_4", - "CFG_CENTER_EL1BEG0_5", - "CFG_CENTER_EL1BEG0_6", - "CFG_CENTER_EL1BEG0_7", - "CFG_CENTER_EL1BEG0_8", - "CFG_CENTER_EL1BEG0_9", - "CFG_CENTER_EL1BEG1_0", - "CFG_CENTER_EL1BEG1_1", - "CFG_CENTER_EL1BEG1_10", - "CFG_CENTER_EL1BEG1_11", - "CFG_CENTER_EL1BEG1_12", - "CFG_CENTER_EL1BEG1_13", - "CFG_CENTER_EL1BEG1_14", - "CFG_CENTER_EL1BEG1_15", - "CFG_CENTER_EL1BEG1_16", - "CFG_CENTER_EL1BEG1_17", - "CFG_CENTER_EL1BEG1_18", - "CFG_CENTER_EL1BEG1_19", - "CFG_CENTER_EL1BEG1_2", - "CFG_CENTER_EL1BEG1_3", - "CFG_CENTER_EL1BEG1_4", - "CFG_CENTER_EL1BEG1_5", - "CFG_CENTER_EL1BEG1_6", - "CFG_CENTER_EL1BEG1_7", - "CFG_CENTER_EL1BEG1_8", - "CFG_CENTER_EL1BEG1_9", - "CFG_CENTER_EL1BEG2_0", - "CFG_CENTER_EL1BEG2_1", - "CFG_CENTER_EL1BEG2_10", - "CFG_CENTER_EL1BEG2_11", - "CFG_CENTER_EL1BEG2_12", - "CFG_CENTER_EL1BEG2_13", - "CFG_CENTER_EL1BEG2_14", - "CFG_CENTER_EL1BEG2_15", - "CFG_CENTER_EL1BEG2_16", - "CFG_CENTER_EL1BEG2_17", - "CFG_CENTER_EL1BEG2_18", - "CFG_CENTER_EL1BEG2_19", - "CFG_CENTER_EL1BEG2_2", - "CFG_CENTER_EL1BEG2_3", - "CFG_CENTER_EL1BEG2_4", - "CFG_CENTER_EL1BEG2_5", - "CFG_CENTER_EL1BEG2_6", - "CFG_CENTER_EL1BEG2_7", - "CFG_CENTER_EL1BEG2_8", - "CFG_CENTER_EL1BEG2_9", - "CFG_CENTER_EL1BEG3_0", - "CFG_CENTER_EL1BEG3_1", - "CFG_CENTER_EL1BEG3_10", - "CFG_CENTER_EL1BEG3_11", - "CFG_CENTER_EL1BEG3_12", - "CFG_CENTER_EL1BEG3_13", - "CFG_CENTER_EL1BEG3_14", - "CFG_CENTER_EL1BEG3_15", - "CFG_CENTER_EL1BEG3_16", - "CFG_CENTER_EL1BEG3_17", - "CFG_CENTER_EL1BEG3_18", - "CFG_CENTER_EL1BEG3_19", - "CFG_CENTER_EL1BEG3_2", - "CFG_CENTER_EL1BEG3_3", - "CFG_CENTER_EL1BEG3_4", - "CFG_CENTER_EL1BEG3_5", - "CFG_CENTER_EL1BEG3_6", - "CFG_CENTER_EL1BEG3_7", - "CFG_CENTER_EL1BEG3_8", - "CFG_CENTER_EL1BEG3_9", - "CFG_CENTER_ER1BEG0_0", - "CFG_CENTER_ER1BEG0_1", - "CFG_CENTER_ER1BEG0_10", - "CFG_CENTER_ER1BEG0_11", - "CFG_CENTER_ER1BEG0_12", - "CFG_CENTER_ER1BEG0_13", - "CFG_CENTER_ER1BEG0_14", - "CFG_CENTER_ER1BEG0_15", - "CFG_CENTER_ER1BEG0_16", - "CFG_CENTER_ER1BEG0_17", - "CFG_CENTER_ER1BEG0_18", - "CFG_CENTER_ER1BEG0_19", - "CFG_CENTER_ER1BEG0_2", - "CFG_CENTER_ER1BEG0_3", - "CFG_CENTER_ER1BEG0_4", - "CFG_CENTER_ER1BEG0_5", - "CFG_CENTER_ER1BEG0_6", - "CFG_CENTER_ER1BEG0_7", - "CFG_CENTER_ER1BEG0_8", - "CFG_CENTER_ER1BEG0_9", - "CFG_CENTER_ER1BEG1_0", - "CFG_CENTER_ER1BEG1_1", - "CFG_CENTER_ER1BEG1_10", - "CFG_CENTER_ER1BEG1_11", - "CFG_CENTER_ER1BEG1_12", - "CFG_CENTER_ER1BEG1_13", - "CFG_CENTER_ER1BEG1_14", - "CFG_CENTER_ER1BEG1_15", - "CFG_CENTER_ER1BEG1_16", - "CFG_CENTER_ER1BEG1_17", - "CFG_CENTER_ER1BEG1_18", - "CFG_CENTER_ER1BEG1_19", - "CFG_CENTER_ER1BEG1_2", - "CFG_CENTER_ER1BEG1_3", - "CFG_CENTER_ER1BEG1_4", - "CFG_CENTER_ER1BEG1_5", - "CFG_CENTER_ER1BEG1_6", - "CFG_CENTER_ER1BEG1_7", - "CFG_CENTER_ER1BEG1_8", - "CFG_CENTER_ER1BEG1_9", - "CFG_CENTER_ER1BEG2_0", - "CFG_CENTER_ER1BEG2_1", - "CFG_CENTER_ER1BEG2_10", - "CFG_CENTER_ER1BEG2_11", - "CFG_CENTER_ER1BEG2_12", - "CFG_CENTER_ER1BEG2_13", - "CFG_CENTER_ER1BEG2_14", - "CFG_CENTER_ER1BEG2_15", - "CFG_CENTER_ER1BEG2_16", - "CFG_CENTER_ER1BEG2_17", - "CFG_CENTER_ER1BEG2_18", - "CFG_CENTER_ER1BEG2_19", - "CFG_CENTER_ER1BEG2_2", - "CFG_CENTER_ER1BEG2_3", - "CFG_CENTER_ER1BEG2_4", - "CFG_CENTER_ER1BEG2_5", - "CFG_CENTER_ER1BEG2_6", - "CFG_CENTER_ER1BEG2_7", - "CFG_CENTER_ER1BEG2_8", - "CFG_CENTER_ER1BEG2_9", - "CFG_CENTER_ER1BEG3_0", - "CFG_CENTER_ER1BEG3_1", - "CFG_CENTER_ER1BEG3_10", - "CFG_CENTER_ER1BEG3_11", - "CFG_CENTER_ER1BEG3_12", - "CFG_CENTER_ER1BEG3_13", - "CFG_CENTER_ER1BEG3_14", - "CFG_CENTER_ER1BEG3_15", - "CFG_CENTER_ER1BEG3_16", - "CFG_CENTER_ER1BEG3_17", - "CFG_CENTER_ER1BEG3_18", - "CFG_CENTER_ER1BEG3_19", - "CFG_CENTER_ER1BEG3_2", - "CFG_CENTER_ER1BEG3_3", - "CFG_CENTER_ER1BEG3_4", - "CFG_CENTER_ER1BEG3_5", - "CFG_CENTER_ER1BEG3_6", - "CFG_CENTER_ER1BEG3_7", - "CFG_CENTER_ER1BEG3_8", - "CFG_CENTER_ER1BEG3_9", - "CFG_CENTER_FAN0_0", - "CFG_CENTER_FAN0_1", - "CFG_CENTER_FAN0_10", - "CFG_CENTER_FAN0_11", - "CFG_CENTER_FAN0_12", - "CFG_CENTER_FAN0_13", - "CFG_CENTER_FAN0_14", - "CFG_CENTER_FAN0_15", - "CFG_CENTER_FAN0_16", - "CFG_CENTER_FAN0_17", - "CFG_CENTER_FAN0_18", - "CFG_CENTER_FAN0_19", - "CFG_CENTER_FAN0_2", - "CFG_CENTER_FAN0_3", - "CFG_CENTER_FAN0_4", - "CFG_CENTER_FAN0_5", - "CFG_CENTER_FAN0_6", - "CFG_CENTER_FAN0_7", - "CFG_CENTER_FAN0_8", - "CFG_CENTER_FAN0_9", - "CFG_CENTER_FAN1_0", - "CFG_CENTER_FAN1_1", - "CFG_CENTER_FAN1_10", - "CFG_CENTER_FAN1_11", - "CFG_CENTER_FAN1_12", - "CFG_CENTER_FAN1_13", - "CFG_CENTER_FAN1_14", - "CFG_CENTER_FAN1_15", - "CFG_CENTER_FAN1_16", - "CFG_CENTER_FAN1_17", - "CFG_CENTER_FAN1_18", - "CFG_CENTER_FAN1_19", - "CFG_CENTER_FAN1_2", - "CFG_CENTER_FAN1_3", - "CFG_CENTER_FAN1_4", - "CFG_CENTER_FAN1_5", - "CFG_CENTER_FAN1_6", - "CFG_CENTER_FAN1_7", - "CFG_CENTER_FAN1_8", - "CFG_CENTER_FAN1_9", - "CFG_CENTER_FAN2_0", - "CFG_CENTER_FAN2_1", - "CFG_CENTER_FAN2_10", - "CFG_CENTER_FAN2_11", - "CFG_CENTER_FAN2_12", - "CFG_CENTER_FAN2_13", - "CFG_CENTER_FAN2_14", - "CFG_CENTER_FAN2_15", - "CFG_CENTER_FAN2_16", - "CFG_CENTER_FAN2_17", - "CFG_CENTER_FAN2_18", - "CFG_CENTER_FAN2_19", - "CFG_CENTER_FAN2_2", - "CFG_CENTER_FAN2_3", - "CFG_CENTER_FAN2_4", - "CFG_CENTER_FAN2_5", - "CFG_CENTER_FAN2_6", - "CFG_CENTER_FAN2_7", - "CFG_CENTER_FAN2_8", - "CFG_CENTER_FAN2_9", - "CFG_CENTER_FAN3_0", - "CFG_CENTER_FAN3_1", - "CFG_CENTER_FAN3_10", - "CFG_CENTER_FAN3_11", - "CFG_CENTER_FAN3_12", - "CFG_CENTER_FAN3_13", - "CFG_CENTER_FAN3_14", - "CFG_CENTER_FAN3_15", - "CFG_CENTER_FAN3_16", - "CFG_CENTER_FAN3_17", - "CFG_CENTER_FAN3_18", - "CFG_CENTER_FAN3_19", - "CFG_CENTER_FAN3_2", - "CFG_CENTER_FAN3_3", - "CFG_CENTER_FAN3_4", - "CFG_CENTER_FAN3_5", - "CFG_CENTER_FAN3_6", - "CFG_CENTER_FAN3_7", - "CFG_CENTER_FAN3_8", - "CFG_CENTER_FAN3_9", - "CFG_CENTER_FAN4_0", - "CFG_CENTER_FAN4_1", - "CFG_CENTER_FAN4_10", - "CFG_CENTER_FAN4_11", - "CFG_CENTER_FAN4_12", - "CFG_CENTER_FAN4_13", - "CFG_CENTER_FAN4_14", - "CFG_CENTER_FAN4_15", - "CFG_CENTER_FAN4_16", - "CFG_CENTER_FAN4_17", - "CFG_CENTER_FAN4_18", - "CFG_CENTER_FAN4_19", - "CFG_CENTER_FAN4_2", - "CFG_CENTER_FAN4_3", - "CFG_CENTER_FAN4_4", - "CFG_CENTER_FAN4_5", - "CFG_CENTER_FAN4_6", - "CFG_CENTER_FAN4_7", - "CFG_CENTER_FAN4_8", - "CFG_CENTER_FAN4_9", - "CFG_CENTER_FAN5_0", - "CFG_CENTER_FAN5_1", - "CFG_CENTER_FAN5_10", - "CFG_CENTER_FAN5_11", - "CFG_CENTER_FAN5_12", - "CFG_CENTER_FAN5_13", - "CFG_CENTER_FAN5_14", - "CFG_CENTER_FAN5_15", - "CFG_CENTER_FAN5_16", - "CFG_CENTER_FAN5_17", - "CFG_CENTER_FAN5_18", - "CFG_CENTER_FAN5_19", - "CFG_CENTER_FAN5_2", - "CFG_CENTER_FAN5_3", - "CFG_CENTER_FAN5_4", - "CFG_CENTER_FAN5_5", - "CFG_CENTER_FAN5_6", - "CFG_CENTER_FAN5_7", - "CFG_CENTER_FAN5_8", - "CFG_CENTER_FAN5_9", - "CFG_CENTER_FAN6_0", - "CFG_CENTER_FAN6_1", - "CFG_CENTER_FAN6_10", - "CFG_CENTER_FAN6_11", - "CFG_CENTER_FAN6_12", - "CFG_CENTER_FAN6_13", - "CFG_CENTER_FAN6_14", - "CFG_CENTER_FAN6_15", - "CFG_CENTER_FAN6_16", - "CFG_CENTER_FAN6_17", - "CFG_CENTER_FAN6_18", - "CFG_CENTER_FAN6_19", - "CFG_CENTER_FAN6_2", - "CFG_CENTER_FAN6_3", - "CFG_CENTER_FAN6_4", - "CFG_CENTER_FAN6_5", - "CFG_CENTER_FAN6_6", - "CFG_CENTER_FAN6_7", - "CFG_CENTER_FAN6_8", - "CFG_CENTER_FAN6_9", - "CFG_CENTER_FAN7_0", - "CFG_CENTER_FAN7_1", - "CFG_CENTER_FAN7_10", - "CFG_CENTER_FAN7_11", - "CFG_CENTER_FAN7_12", - "CFG_CENTER_FAN7_13", - "CFG_CENTER_FAN7_14", - "CFG_CENTER_FAN7_15", - "CFG_CENTER_FAN7_16", - "CFG_CENTER_FAN7_17", - "CFG_CENTER_FAN7_18", - "CFG_CENTER_FAN7_19", - "CFG_CENTER_FAN7_2", - "CFG_CENTER_FAN7_3", - "CFG_CENTER_FAN7_4", - "CFG_CENTER_FAN7_5", - "CFG_CENTER_FAN7_6", - "CFG_CENTER_FAN7_7", - "CFG_CENTER_FAN7_8", - "CFG_CENTER_FAN7_9", - "CFG_CENTER_FRAME_ECC_CRCERROR", - "CFG_CENTER_FRAME_ECC_ECCERROR", - "CFG_CENTER_FRAME_ECC_ECCERRORSINGLE", - "CFG_CENTER_FRAME_ECC_FAR0", - "CFG_CENTER_FRAME_ECC_FAR1", - "CFG_CENTER_FRAME_ECC_FAR10", - "CFG_CENTER_FRAME_ECC_FAR11", - "CFG_CENTER_FRAME_ECC_FAR12", - "CFG_CENTER_FRAME_ECC_FAR13", - "CFG_CENTER_FRAME_ECC_FAR14", - "CFG_CENTER_FRAME_ECC_FAR15", - "CFG_CENTER_FRAME_ECC_FAR16", - "CFG_CENTER_FRAME_ECC_FAR17", - "CFG_CENTER_FRAME_ECC_FAR18", - "CFG_CENTER_FRAME_ECC_FAR19", - "CFG_CENTER_FRAME_ECC_FAR2", - "CFG_CENTER_FRAME_ECC_FAR20", - "CFG_CENTER_FRAME_ECC_FAR21", - "CFG_CENTER_FRAME_ECC_FAR22", - "CFG_CENTER_FRAME_ECC_FAR23", - "CFG_CENTER_FRAME_ECC_FAR24", - "CFG_CENTER_FRAME_ECC_FAR25", - "CFG_CENTER_FRAME_ECC_FAR3", - "CFG_CENTER_FRAME_ECC_FAR4", - "CFG_CENTER_FRAME_ECC_FAR5", - "CFG_CENTER_FRAME_ECC_FAR6", - "CFG_CENTER_FRAME_ECC_FAR7", - "CFG_CENTER_FRAME_ECC_FAR8", - "CFG_CENTER_FRAME_ECC_FAR9", - "CFG_CENTER_FRAME_ECC_SYNBIT0", - "CFG_CENTER_FRAME_ECC_SYNBIT1", - "CFG_CENTER_FRAME_ECC_SYNBIT2", - "CFG_CENTER_FRAME_ECC_SYNBIT3", - "CFG_CENTER_FRAME_ECC_SYNBIT4", - "CFG_CENTER_FRAME_ECC_SYNDROME0", - "CFG_CENTER_FRAME_ECC_SYNDROME1", - "CFG_CENTER_FRAME_ECC_SYNDROME10", - "CFG_CENTER_FRAME_ECC_SYNDROME11", - "CFG_CENTER_FRAME_ECC_SYNDROME12", - "CFG_CENTER_FRAME_ECC_SYNDROME2", - "CFG_CENTER_FRAME_ECC_SYNDROME3", - "CFG_CENTER_FRAME_ECC_SYNDROME4", - "CFG_CENTER_FRAME_ECC_SYNDROME5", - "CFG_CENTER_FRAME_ECC_SYNDROME6", - "CFG_CENTER_FRAME_ECC_SYNDROME7", - "CFG_CENTER_FRAME_ECC_SYNDROME8", - "CFG_CENTER_FRAME_ECC_SYNDROME9", - "CFG_CENTER_FRAME_ECC_SYNDROMEVALID", - "CFG_CENTER_FRAME_ECC_SYNWORD0", - "CFG_CENTER_FRAME_ECC_SYNWORD1", - "CFG_CENTER_FRAME_ECC_SYNWORD2", - "CFG_CENTER_FRAME_ECC_SYNWORD3", - "CFG_CENTER_FRAME_ECC_SYNWORD4", - "CFG_CENTER_FRAME_ECC_SYNWORD5", - "CFG_CENTER_FRAME_ECC_SYNWORD6", - "CFG_CENTER_ICAP0_CLK", - "CFG_CENTER_ICAP0_CSIB", - "CFG_CENTER_ICAP0_I0", - "CFG_CENTER_ICAP0_I1", - "CFG_CENTER_ICAP0_I10", - "CFG_CENTER_ICAP0_I11", - "CFG_CENTER_ICAP0_I12", - "CFG_CENTER_ICAP0_I13", - "CFG_CENTER_ICAP0_I14", - "CFG_CENTER_ICAP0_I15", - "CFG_CENTER_ICAP0_I16", - "CFG_CENTER_ICAP0_I17", - "CFG_CENTER_ICAP0_I18", - "CFG_CENTER_ICAP0_I19", - "CFG_CENTER_ICAP0_I2", - "CFG_CENTER_ICAP0_I20", - "CFG_CENTER_ICAP0_I21", - "CFG_CENTER_ICAP0_I22", - "CFG_CENTER_ICAP0_I23", - "CFG_CENTER_ICAP0_I24", - "CFG_CENTER_ICAP0_I25", - "CFG_CENTER_ICAP0_I26", - "CFG_CENTER_ICAP0_I27", - "CFG_CENTER_ICAP0_I28", - "CFG_CENTER_ICAP0_I29", - "CFG_CENTER_ICAP0_I3", - "CFG_CENTER_ICAP0_I30", - "CFG_CENTER_ICAP0_I31", - "CFG_CENTER_ICAP0_I4", - "CFG_CENTER_ICAP0_I5", - "CFG_CENTER_ICAP0_I6", - "CFG_CENTER_ICAP0_I7", - "CFG_CENTER_ICAP0_I8", - "CFG_CENTER_ICAP0_I9", - "CFG_CENTER_ICAP0_O0", - "CFG_CENTER_ICAP0_O1", - "CFG_CENTER_ICAP0_O10", - "CFG_CENTER_ICAP0_O11", - "CFG_CENTER_ICAP0_O12", - "CFG_CENTER_ICAP0_O13", - "CFG_CENTER_ICAP0_O14", - "CFG_CENTER_ICAP0_O15", - "CFG_CENTER_ICAP0_O16", - "CFG_CENTER_ICAP0_O17", - "CFG_CENTER_ICAP0_O18", - "CFG_CENTER_ICAP0_O19", - "CFG_CENTER_ICAP0_O2", - "CFG_CENTER_ICAP0_O20", - "CFG_CENTER_ICAP0_O21", - "CFG_CENTER_ICAP0_O22", - "CFG_CENTER_ICAP0_O23", - "CFG_CENTER_ICAP0_O24", - "CFG_CENTER_ICAP0_O25", - "CFG_CENTER_ICAP0_O26", - "CFG_CENTER_ICAP0_O27", - "CFG_CENTER_ICAP0_O28", - "CFG_CENTER_ICAP0_O29", - "CFG_CENTER_ICAP0_O3", - "CFG_CENTER_ICAP0_O30", - "CFG_CENTER_ICAP0_O31", - "CFG_CENTER_ICAP0_O4", - "CFG_CENTER_ICAP0_O5", - "CFG_CENTER_ICAP0_O6", - "CFG_CENTER_ICAP0_O7", - "CFG_CENTER_ICAP0_O8", - "CFG_CENTER_ICAP0_O9", - "CFG_CENTER_ICAP0_RDWRB", - "CFG_CENTER_ICAP1_CLK", - "CFG_CENTER_ICAP1_CSIB", - "CFG_CENTER_ICAP1_I0", - "CFG_CENTER_ICAP1_I1", - "CFG_CENTER_ICAP1_I10", - "CFG_CENTER_ICAP1_I11", - "CFG_CENTER_ICAP1_I12", - "CFG_CENTER_ICAP1_I13", - "CFG_CENTER_ICAP1_I14", - "CFG_CENTER_ICAP1_I15", - "CFG_CENTER_ICAP1_I16", - "CFG_CENTER_ICAP1_I17", - "CFG_CENTER_ICAP1_I18", - "CFG_CENTER_ICAP1_I19", - "CFG_CENTER_ICAP1_I2", - "CFG_CENTER_ICAP1_I20", - "CFG_CENTER_ICAP1_I21", - "CFG_CENTER_ICAP1_I22", - "CFG_CENTER_ICAP1_I23", - "CFG_CENTER_ICAP1_I24", - "CFG_CENTER_ICAP1_I25", - "CFG_CENTER_ICAP1_I26", - "CFG_CENTER_ICAP1_I27", - "CFG_CENTER_ICAP1_I28", - "CFG_CENTER_ICAP1_I29", - "CFG_CENTER_ICAP1_I3", - "CFG_CENTER_ICAP1_I30", - "CFG_CENTER_ICAP1_I31", - "CFG_CENTER_ICAP1_I4", - "CFG_CENTER_ICAP1_I5", - "CFG_CENTER_ICAP1_I6", - "CFG_CENTER_ICAP1_I7", - "CFG_CENTER_ICAP1_I8", - "CFG_CENTER_ICAP1_I9", - "CFG_CENTER_ICAP1_O0", - "CFG_CENTER_ICAP1_O1", - "CFG_CENTER_ICAP1_O10", - "CFG_CENTER_ICAP1_O11", - "CFG_CENTER_ICAP1_O12", - "CFG_CENTER_ICAP1_O13", - "CFG_CENTER_ICAP1_O14", - "CFG_CENTER_ICAP1_O15", - "CFG_CENTER_ICAP1_O16", - "CFG_CENTER_ICAP1_O17", - "CFG_CENTER_ICAP1_O18", - "CFG_CENTER_ICAP1_O19", - "CFG_CENTER_ICAP1_O2", - "CFG_CENTER_ICAP1_O20", - "CFG_CENTER_ICAP1_O21", - "CFG_CENTER_ICAP1_O22", - "CFG_CENTER_ICAP1_O23", - "CFG_CENTER_ICAP1_O24", - "CFG_CENTER_ICAP1_O25", - "CFG_CENTER_ICAP1_O26", - "CFG_CENTER_ICAP1_O27", - "CFG_CENTER_ICAP1_O28", - "CFG_CENTER_ICAP1_O29", - "CFG_CENTER_ICAP1_O3", - "CFG_CENTER_ICAP1_O30", - "CFG_CENTER_ICAP1_O31", - "CFG_CENTER_ICAP1_O4", - "CFG_CENTER_ICAP1_O5", - "CFG_CENTER_ICAP1_O6", - "CFG_CENTER_ICAP1_O7", - "CFG_CENTER_ICAP1_O8", - "CFG_CENTER_ICAP1_O9", - "CFG_CENTER_ICAP1_RDWRB", - "CFG_CENTER_IMUX0_0", - "CFG_CENTER_IMUX0_1", - "CFG_CENTER_IMUX0_10", - "CFG_CENTER_IMUX0_11", - "CFG_CENTER_IMUX0_12", - "CFG_CENTER_IMUX0_13", - "CFG_CENTER_IMUX0_14", - "CFG_CENTER_IMUX0_15", - "CFG_CENTER_IMUX0_16", - "CFG_CENTER_IMUX0_17", - "CFG_CENTER_IMUX0_18", - "CFG_CENTER_IMUX0_19", - "CFG_CENTER_IMUX0_2", - "CFG_CENTER_IMUX0_3", - "CFG_CENTER_IMUX0_4", - "CFG_CENTER_IMUX0_5", - "CFG_CENTER_IMUX0_6", - "CFG_CENTER_IMUX0_7", - "CFG_CENTER_IMUX0_8", - "CFG_CENTER_IMUX0_9", - "CFG_CENTER_IMUX10_0", - "CFG_CENTER_IMUX10_1", - "CFG_CENTER_IMUX10_10", - "CFG_CENTER_IMUX10_11", - "CFG_CENTER_IMUX10_12", - "CFG_CENTER_IMUX10_13", - "CFG_CENTER_IMUX10_14", - "CFG_CENTER_IMUX10_15", - "CFG_CENTER_IMUX10_16", - "CFG_CENTER_IMUX10_17", - "CFG_CENTER_IMUX10_18", - "CFG_CENTER_IMUX10_19", - "CFG_CENTER_IMUX10_2", - "CFG_CENTER_IMUX10_3", - "CFG_CENTER_IMUX10_4", - "CFG_CENTER_IMUX10_5", - "CFG_CENTER_IMUX10_6", - "CFG_CENTER_IMUX10_7", - "CFG_CENTER_IMUX10_8", - "CFG_CENTER_IMUX10_9", - "CFG_CENTER_IMUX11_0", - "CFG_CENTER_IMUX11_1", - "CFG_CENTER_IMUX11_10", - "CFG_CENTER_IMUX11_11", - "CFG_CENTER_IMUX11_12", - "CFG_CENTER_IMUX11_13", - "CFG_CENTER_IMUX11_14", - "CFG_CENTER_IMUX11_15", - "CFG_CENTER_IMUX11_16", - "CFG_CENTER_IMUX11_17", - "CFG_CENTER_IMUX11_18", - "CFG_CENTER_IMUX11_19", - "CFG_CENTER_IMUX11_2", - "CFG_CENTER_IMUX11_3", - "CFG_CENTER_IMUX11_4", - "CFG_CENTER_IMUX11_5", - "CFG_CENTER_IMUX11_6", - "CFG_CENTER_IMUX11_7", - "CFG_CENTER_IMUX11_8", - "CFG_CENTER_IMUX11_9", - "CFG_CENTER_IMUX12_0", - "CFG_CENTER_IMUX12_1", - "CFG_CENTER_IMUX12_10", - "CFG_CENTER_IMUX12_11", - "CFG_CENTER_IMUX12_12", - "CFG_CENTER_IMUX12_13", - "CFG_CENTER_IMUX12_14", - "CFG_CENTER_IMUX12_15", - "CFG_CENTER_IMUX12_16", - "CFG_CENTER_IMUX12_17", - "CFG_CENTER_IMUX12_18", - "CFG_CENTER_IMUX12_19", - "CFG_CENTER_IMUX12_2", - "CFG_CENTER_IMUX12_3", - "CFG_CENTER_IMUX12_4", - "CFG_CENTER_IMUX12_5", - "CFG_CENTER_IMUX12_6", - "CFG_CENTER_IMUX12_7", - "CFG_CENTER_IMUX12_8", - "CFG_CENTER_IMUX12_9", - "CFG_CENTER_IMUX13_0", - "CFG_CENTER_IMUX13_1", - "CFG_CENTER_IMUX13_10", - "CFG_CENTER_IMUX13_11", - "CFG_CENTER_IMUX13_12", - "CFG_CENTER_IMUX13_13", - "CFG_CENTER_IMUX13_14", - "CFG_CENTER_IMUX13_15", - "CFG_CENTER_IMUX13_16", - "CFG_CENTER_IMUX13_17", - "CFG_CENTER_IMUX13_18", - "CFG_CENTER_IMUX13_19", - "CFG_CENTER_IMUX13_2", - "CFG_CENTER_IMUX13_3", - "CFG_CENTER_IMUX13_4", - "CFG_CENTER_IMUX13_5", - "CFG_CENTER_IMUX13_6", - "CFG_CENTER_IMUX13_7", - "CFG_CENTER_IMUX13_8", - "CFG_CENTER_IMUX13_9", - "CFG_CENTER_IMUX14_0", - "CFG_CENTER_IMUX14_1", - "CFG_CENTER_IMUX14_10", - "CFG_CENTER_IMUX14_11", - "CFG_CENTER_IMUX14_12", - "CFG_CENTER_IMUX14_13", - "CFG_CENTER_IMUX14_14", - "CFG_CENTER_IMUX14_15", - "CFG_CENTER_IMUX14_16", - "CFG_CENTER_IMUX14_17", - "CFG_CENTER_IMUX14_18", - "CFG_CENTER_IMUX14_19", - "CFG_CENTER_IMUX14_2", - "CFG_CENTER_IMUX14_3", - "CFG_CENTER_IMUX14_4", - "CFG_CENTER_IMUX14_5", - "CFG_CENTER_IMUX14_6", - "CFG_CENTER_IMUX14_7", - "CFG_CENTER_IMUX14_8", - "CFG_CENTER_IMUX14_9", - "CFG_CENTER_IMUX15_0", - "CFG_CENTER_IMUX15_1", - "CFG_CENTER_IMUX15_10", - "CFG_CENTER_IMUX15_11", - "CFG_CENTER_IMUX15_12", - "CFG_CENTER_IMUX15_13", - "CFG_CENTER_IMUX15_14", - "CFG_CENTER_IMUX15_15", - "CFG_CENTER_IMUX15_16", - "CFG_CENTER_IMUX15_17", - "CFG_CENTER_IMUX15_18", - "CFG_CENTER_IMUX15_19", - "CFG_CENTER_IMUX15_2", - "CFG_CENTER_IMUX15_3", - "CFG_CENTER_IMUX15_4", - "CFG_CENTER_IMUX15_5", - "CFG_CENTER_IMUX15_6", - "CFG_CENTER_IMUX15_7", - "CFG_CENTER_IMUX15_8", - "CFG_CENTER_IMUX15_9", - "CFG_CENTER_IMUX16_0", - "CFG_CENTER_IMUX16_1", - "CFG_CENTER_IMUX16_10", - "CFG_CENTER_IMUX16_11", - "CFG_CENTER_IMUX16_12", - "CFG_CENTER_IMUX16_13", - "CFG_CENTER_IMUX16_14", - "CFG_CENTER_IMUX16_15", - "CFG_CENTER_IMUX16_16", - "CFG_CENTER_IMUX16_17", - "CFG_CENTER_IMUX16_18", - "CFG_CENTER_IMUX16_19", - "CFG_CENTER_IMUX16_2", - "CFG_CENTER_IMUX16_3", - "CFG_CENTER_IMUX16_4", - "CFG_CENTER_IMUX16_5", - "CFG_CENTER_IMUX16_6", - "CFG_CENTER_IMUX16_7", - "CFG_CENTER_IMUX16_8", - "CFG_CENTER_IMUX16_9", - "CFG_CENTER_IMUX17_0", - "CFG_CENTER_IMUX17_1", - "CFG_CENTER_IMUX17_10", - "CFG_CENTER_IMUX17_11", - "CFG_CENTER_IMUX17_12", - "CFG_CENTER_IMUX17_13", - "CFG_CENTER_IMUX17_14", - "CFG_CENTER_IMUX17_15", - "CFG_CENTER_IMUX17_16", - "CFG_CENTER_IMUX17_17", - "CFG_CENTER_IMUX17_18", - "CFG_CENTER_IMUX17_19", - "CFG_CENTER_IMUX17_2", - "CFG_CENTER_IMUX17_3", - "CFG_CENTER_IMUX17_4", - "CFG_CENTER_IMUX17_5", - "CFG_CENTER_IMUX17_6", - "CFG_CENTER_IMUX17_7", - "CFG_CENTER_IMUX17_8", - "CFG_CENTER_IMUX17_9", - "CFG_CENTER_IMUX18_0", - "CFG_CENTER_IMUX18_1", - "CFG_CENTER_IMUX18_10", - "CFG_CENTER_IMUX18_11", - "CFG_CENTER_IMUX18_12", - "CFG_CENTER_IMUX18_13", - "CFG_CENTER_IMUX18_14", - "CFG_CENTER_IMUX18_15", - "CFG_CENTER_IMUX18_16", - "CFG_CENTER_IMUX18_17", - "CFG_CENTER_IMUX18_18", - "CFG_CENTER_IMUX18_19", - "CFG_CENTER_IMUX18_2", - "CFG_CENTER_IMUX18_3", - "CFG_CENTER_IMUX18_4", - "CFG_CENTER_IMUX18_5", - "CFG_CENTER_IMUX18_6", - "CFG_CENTER_IMUX18_7", - "CFG_CENTER_IMUX18_8", - "CFG_CENTER_IMUX18_9", - "CFG_CENTER_IMUX19_0", - "CFG_CENTER_IMUX19_1", - "CFG_CENTER_IMUX19_10", - "CFG_CENTER_IMUX19_11", - "CFG_CENTER_IMUX19_12", - "CFG_CENTER_IMUX19_13", - "CFG_CENTER_IMUX19_14", - "CFG_CENTER_IMUX19_15", - "CFG_CENTER_IMUX19_16", - "CFG_CENTER_IMUX19_17", - "CFG_CENTER_IMUX19_18", - "CFG_CENTER_IMUX19_19", - "CFG_CENTER_IMUX19_2", - "CFG_CENTER_IMUX19_3", - "CFG_CENTER_IMUX19_4", - "CFG_CENTER_IMUX19_5", - "CFG_CENTER_IMUX19_6", - "CFG_CENTER_IMUX19_7", - "CFG_CENTER_IMUX19_8", - "CFG_CENTER_IMUX19_9", - "CFG_CENTER_IMUX1_0", - "CFG_CENTER_IMUX1_1", - "CFG_CENTER_IMUX1_10", - "CFG_CENTER_IMUX1_11", - "CFG_CENTER_IMUX1_12", - "CFG_CENTER_IMUX1_13", - "CFG_CENTER_IMUX1_14", - "CFG_CENTER_IMUX1_15", - "CFG_CENTER_IMUX1_16", - "CFG_CENTER_IMUX1_17", - "CFG_CENTER_IMUX1_18", - "CFG_CENTER_IMUX1_19", - "CFG_CENTER_IMUX1_2", - "CFG_CENTER_IMUX1_3", - "CFG_CENTER_IMUX1_4", - "CFG_CENTER_IMUX1_5", - "CFG_CENTER_IMUX1_6", - "CFG_CENTER_IMUX1_7", - "CFG_CENTER_IMUX1_8", - "CFG_CENTER_IMUX1_9", - "CFG_CENTER_IMUX20_0", - "CFG_CENTER_IMUX20_1", - "CFG_CENTER_IMUX20_10", - "CFG_CENTER_IMUX20_11", - "CFG_CENTER_IMUX20_12", - "CFG_CENTER_IMUX20_13", - "CFG_CENTER_IMUX20_14", - "CFG_CENTER_IMUX20_15", - "CFG_CENTER_IMUX20_16", - "CFG_CENTER_IMUX20_17", - "CFG_CENTER_IMUX20_18", - "CFG_CENTER_IMUX20_19", - "CFG_CENTER_IMUX20_2", - "CFG_CENTER_IMUX20_3", - "CFG_CENTER_IMUX20_4", - "CFG_CENTER_IMUX20_5", - "CFG_CENTER_IMUX20_6", - "CFG_CENTER_IMUX20_7", - "CFG_CENTER_IMUX20_8", - "CFG_CENTER_IMUX20_9", - "CFG_CENTER_IMUX21_0", - "CFG_CENTER_IMUX21_1", - "CFG_CENTER_IMUX21_10", - "CFG_CENTER_IMUX21_11", - "CFG_CENTER_IMUX21_12", - "CFG_CENTER_IMUX21_13", - "CFG_CENTER_IMUX21_14", - "CFG_CENTER_IMUX21_15", - "CFG_CENTER_IMUX21_16", - "CFG_CENTER_IMUX21_17", - "CFG_CENTER_IMUX21_18", - "CFG_CENTER_IMUX21_19", - "CFG_CENTER_IMUX21_2", - "CFG_CENTER_IMUX21_3", - "CFG_CENTER_IMUX21_4", - "CFG_CENTER_IMUX21_5", - "CFG_CENTER_IMUX21_6", - "CFG_CENTER_IMUX21_7", - "CFG_CENTER_IMUX21_8", - "CFG_CENTER_IMUX21_9", - "CFG_CENTER_IMUX22_0", - "CFG_CENTER_IMUX22_1", - "CFG_CENTER_IMUX22_10", - "CFG_CENTER_IMUX22_11", - "CFG_CENTER_IMUX22_12", - "CFG_CENTER_IMUX22_13", - "CFG_CENTER_IMUX22_14", - "CFG_CENTER_IMUX22_15", - "CFG_CENTER_IMUX22_16", - "CFG_CENTER_IMUX22_17", - "CFG_CENTER_IMUX22_18", - "CFG_CENTER_IMUX22_19", - "CFG_CENTER_IMUX22_2", - "CFG_CENTER_IMUX22_3", - "CFG_CENTER_IMUX22_4", - "CFG_CENTER_IMUX22_5", - "CFG_CENTER_IMUX22_6", - "CFG_CENTER_IMUX22_7", - "CFG_CENTER_IMUX22_8", - "CFG_CENTER_IMUX22_9", - "CFG_CENTER_IMUX23_0", - "CFG_CENTER_IMUX23_1", - "CFG_CENTER_IMUX23_10", - "CFG_CENTER_IMUX23_11", - "CFG_CENTER_IMUX23_12", - "CFG_CENTER_IMUX23_13", - "CFG_CENTER_IMUX23_14", - "CFG_CENTER_IMUX23_15", - "CFG_CENTER_IMUX23_16", - "CFG_CENTER_IMUX23_17", - "CFG_CENTER_IMUX23_18", - "CFG_CENTER_IMUX23_19", - "CFG_CENTER_IMUX23_2", - "CFG_CENTER_IMUX23_3", - "CFG_CENTER_IMUX23_4", - "CFG_CENTER_IMUX23_5", - "CFG_CENTER_IMUX23_6", - "CFG_CENTER_IMUX23_7", - "CFG_CENTER_IMUX23_8", - "CFG_CENTER_IMUX23_9", - "CFG_CENTER_IMUX24_0", - "CFG_CENTER_IMUX24_1", - "CFG_CENTER_IMUX24_10", - "CFG_CENTER_IMUX24_11", - "CFG_CENTER_IMUX24_12", - "CFG_CENTER_IMUX24_13", - "CFG_CENTER_IMUX24_14", - "CFG_CENTER_IMUX24_15", - "CFG_CENTER_IMUX24_16", - "CFG_CENTER_IMUX24_17", - "CFG_CENTER_IMUX24_18", - "CFG_CENTER_IMUX24_19", - "CFG_CENTER_IMUX24_2", - "CFG_CENTER_IMUX24_3", - "CFG_CENTER_IMUX24_4", - "CFG_CENTER_IMUX24_5", - "CFG_CENTER_IMUX24_6", - "CFG_CENTER_IMUX24_7", - "CFG_CENTER_IMUX24_8", - "CFG_CENTER_IMUX24_9", - "CFG_CENTER_IMUX25_0", - "CFG_CENTER_IMUX25_1", - "CFG_CENTER_IMUX25_10", - "CFG_CENTER_IMUX25_11", - "CFG_CENTER_IMUX25_12", - "CFG_CENTER_IMUX25_13", - "CFG_CENTER_IMUX25_14", - "CFG_CENTER_IMUX25_15", - "CFG_CENTER_IMUX25_16", - "CFG_CENTER_IMUX25_17", - "CFG_CENTER_IMUX25_18", - "CFG_CENTER_IMUX25_19", - "CFG_CENTER_IMUX25_2", - "CFG_CENTER_IMUX25_3", - "CFG_CENTER_IMUX25_4", - "CFG_CENTER_IMUX25_5", - "CFG_CENTER_IMUX25_6", - "CFG_CENTER_IMUX25_7", - "CFG_CENTER_IMUX25_8", - "CFG_CENTER_IMUX25_9", - "CFG_CENTER_IMUX26_0", - "CFG_CENTER_IMUX26_1", - "CFG_CENTER_IMUX26_10", - "CFG_CENTER_IMUX26_11", - "CFG_CENTER_IMUX26_12", - "CFG_CENTER_IMUX26_13", - "CFG_CENTER_IMUX26_14", - "CFG_CENTER_IMUX26_15", - "CFG_CENTER_IMUX26_16", - "CFG_CENTER_IMUX26_17", - "CFG_CENTER_IMUX26_18", - "CFG_CENTER_IMUX26_19", - "CFG_CENTER_IMUX26_2", - "CFG_CENTER_IMUX26_3", - "CFG_CENTER_IMUX26_4", - "CFG_CENTER_IMUX26_5", - "CFG_CENTER_IMUX26_6", - "CFG_CENTER_IMUX26_7", - "CFG_CENTER_IMUX26_8", - "CFG_CENTER_IMUX26_9", - "CFG_CENTER_IMUX27_0", - "CFG_CENTER_IMUX27_1", - "CFG_CENTER_IMUX27_10", - "CFG_CENTER_IMUX27_11", - "CFG_CENTER_IMUX27_12", - "CFG_CENTER_IMUX27_13", - "CFG_CENTER_IMUX27_14", - "CFG_CENTER_IMUX27_15", - "CFG_CENTER_IMUX27_16", - "CFG_CENTER_IMUX27_17", - "CFG_CENTER_IMUX27_18", - "CFG_CENTER_IMUX27_19", - "CFG_CENTER_IMUX27_2", - "CFG_CENTER_IMUX27_3", - "CFG_CENTER_IMUX27_4", - "CFG_CENTER_IMUX27_5", - "CFG_CENTER_IMUX27_6", - "CFG_CENTER_IMUX27_7", - "CFG_CENTER_IMUX27_8", - "CFG_CENTER_IMUX27_9", - "CFG_CENTER_IMUX28_0", - "CFG_CENTER_IMUX28_1", - "CFG_CENTER_IMUX28_10", - "CFG_CENTER_IMUX28_11", - "CFG_CENTER_IMUX28_12", - "CFG_CENTER_IMUX28_13", - "CFG_CENTER_IMUX28_14", - "CFG_CENTER_IMUX28_15", - "CFG_CENTER_IMUX28_16", - "CFG_CENTER_IMUX28_17", - "CFG_CENTER_IMUX28_18", - "CFG_CENTER_IMUX28_19", - "CFG_CENTER_IMUX28_2", - "CFG_CENTER_IMUX28_3", - "CFG_CENTER_IMUX28_4", - "CFG_CENTER_IMUX28_5", - "CFG_CENTER_IMUX28_6", - "CFG_CENTER_IMUX28_7", - "CFG_CENTER_IMUX28_8", - "CFG_CENTER_IMUX28_9", - "CFG_CENTER_IMUX29_0", - "CFG_CENTER_IMUX29_1", - "CFG_CENTER_IMUX29_10", - "CFG_CENTER_IMUX29_11", - "CFG_CENTER_IMUX29_12", - "CFG_CENTER_IMUX29_13", - "CFG_CENTER_IMUX29_14", - "CFG_CENTER_IMUX29_15", - "CFG_CENTER_IMUX29_16", - "CFG_CENTER_IMUX29_17", - "CFG_CENTER_IMUX29_18", - "CFG_CENTER_IMUX29_19", - "CFG_CENTER_IMUX29_2", - "CFG_CENTER_IMUX29_3", - "CFG_CENTER_IMUX29_4", - "CFG_CENTER_IMUX29_5", - "CFG_CENTER_IMUX29_6", - "CFG_CENTER_IMUX29_7", - "CFG_CENTER_IMUX29_8", - "CFG_CENTER_IMUX29_9", - "CFG_CENTER_IMUX2_0", - "CFG_CENTER_IMUX2_1", - "CFG_CENTER_IMUX2_10", - "CFG_CENTER_IMUX2_11", - "CFG_CENTER_IMUX2_12", - "CFG_CENTER_IMUX2_13", - "CFG_CENTER_IMUX2_14", - "CFG_CENTER_IMUX2_15", - "CFG_CENTER_IMUX2_16", - "CFG_CENTER_IMUX2_17", - "CFG_CENTER_IMUX2_18", - "CFG_CENTER_IMUX2_19", - "CFG_CENTER_IMUX2_2", - "CFG_CENTER_IMUX2_3", - "CFG_CENTER_IMUX2_4", - "CFG_CENTER_IMUX2_5", - "CFG_CENTER_IMUX2_6", - "CFG_CENTER_IMUX2_7", - "CFG_CENTER_IMUX2_8", - "CFG_CENTER_IMUX2_9", - "CFG_CENTER_IMUX30_0", - "CFG_CENTER_IMUX30_1", - "CFG_CENTER_IMUX30_10", - "CFG_CENTER_IMUX30_11", - "CFG_CENTER_IMUX30_12", - "CFG_CENTER_IMUX30_13", - "CFG_CENTER_IMUX30_14", - "CFG_CENTER_IMUX30_15", - "CFG_CENTER_IMUX30_16", - "CFG_CENTER_IMUX30_17", - "CFG_CENTER_IMUX30_18", - "CFG_CENTER_IMUX30_19", - "CFG_CENTER_IMUX30_2", - "CFG_CENTER_IMUX30_3", - "CFG_CENTER_IMUX30_4", - "CFG_CENTER_IMUX30_5", - "CFG_CENTER_IMUX30_6", - "CFG_CENTER_IMUX30_7", - "CFG_CENTER_IMUX30_8", - "CFG_CENTER_IMUX30_9", - "CFG_CENTER_IMUX31_0", - "CFG_CENTER_IMUX31_1", - "CFG_CENTER_IMUX31_10", - "CFG_CENTER_IMUX31_11", - "CFG_CENTER_IMUX31_12", - "CFG_CENTER_IMUX31_13", - "CFG_CENTER_IMUX31_14", - "CFG_CENTER_IMUX31_15", - "CFG_CENTER_IMUX31_16", - "CFG_CENTER_IMUX31_17", - "CFG_CENTER_IMUX31_18", - "CFG_CENTER_IMUX31_19", - "CFG_CENTER_IMUX31_2", - "CFG_CENTER_IMUX31_3", - "CFG_CENTER_IMUX31_4", - "CFG_CENTER_IMUX31_5", - "CFG_CENTER_IMUX31_6", - "CFG_CENTER_IMUX31_7", - "CFG_CENTER_IMUX31_8", - "CFG_CENTER_IMUX31_9", - "CFG_CENTER_IMUX32_0", - "CFG_CENTER_IMUX32_1", - "CFG_CENTER_IMUX32_10", - "CFG_CENTER_IMUX32_11", - "CFG_CENTER_IMUX32_12", - "CFG_CENTER_IMUX32_13", - "CFG_CENTER_IMUX32_14", - "CFG_CENTER_IMUX32_15", - "CFG_CENTER_IMUX32_16", - "CFG_CENTER_IMUX32_17", - "CFG_CENTER_IMUX32_18", - "CFG_CENTER_IMUX32_19", - "CFG_CENTER_IMUX32_2", - "CFG_CENTER_IMUX32_3", - "CFG_CENTER_IMUX32_4", - "CFG_CENTER_IMUX32_5", - "CFG_CENTER_IMUX32_6", - "CFG_CENTER_IMUX32_7", - "CFG_CENTER_IMUX32_8", - "CFG_CENTER_IMUX32_9", - "CFG_CENTER_IMUX33_0", - "CFG_CENTER_IMUX33_1", - "CFG_CENTER_IMUX33_10", - "CFG_CENTER_IMUX33_11", - "CFG_CENTER_IMUX33_12", - "CFG_CENTER_IMUX33_13", - "CFG_CENTER_IMUX33_14", - "CFG_CENTER_IMUX33_15", - "CFG_CENTER_IMUX33_16", - "CFG_CENTER_IMUX33_17", - "CFG_CENTER_IMUX33_18", - "CFG_CENTER_IMUX33_19", - "CFG_CENTER_IMUX33_2", - "CFG_CENTER_IMUX33_3", - "CFG_CENTER_IMUX33_4", - "CFG_CENTER_IMUX33_5", - "CFG_CENTER_IMUX33_6", - "CFG_CENTER_IMUX33_7", - "CFG_CENTER_IMUX33_8", - "CFG_CENTER_IMUX33_9", - "CFG_CENTER_IMUX34_0", - "CFG_CENTER_IMUX34_1", - "CFG_CENTER_IMUX34_10", - "CFG_CENTER_IMUX34_11", - "CFG_CENTER_IMUX34_12", - "CFG_CENTER_IMUX34_13", - "CFG_CENTER_IMUX34_14", - "CFG_CENTER_IMUX34_15", - "CFG_CENTER_IMUX34_16", - "CFG_CENTER_IMUX34_17", - "CFG_CENTER_IMUX34_18", - "CFG_CENTER_IMUX34_19", - "CFG_CENTER_IMUX34_2", - "CFG_CENTER_IMUX34_3", - "CFG_CENTER_IMUX34_4", - "CFG_CENTER_IMUX34_5", - "CFG_CENTER_IMUX34_6", - "CFG_CENTER_IMUX34_7", - "CFG_CENTER_IMUX34_8", - "CFG_CENTER_IMUX34_9", - "CFG_CENTER_IMUX35_0", - "CFG_CENTER_IMUX35_1", - "CFG_CENTER_IMUX35_10", - "CFG_CENTER_IMUX35_11", - "CFG_CENTER_IMUX35_12", - "CFG_CENTER_IMUX35_13", - "CFG_CENTER_IMUX35_14", - "CFG_CENTER_IMUX35_15", - "CFG_CENTER_IMUX35_16", - "CFG_CENTER_IMUX35_17", - "CFG_CENTER_IMUX35_18", - "CFG_CENTER_IMUX35_19", - "CFG_CENTER_IMUX35_2", - "CFG_CENTER_IMUX35_3", - "CFG_CENTER_IMUX35_4", - "CFG_CENTER_IMUX35_5", - "CFG_CENTER_IMUX35_6", - "CFG_CENTER_IMUX35_7", - "CFG_CENTER_IMUX35_8", - "CFG_CENTER_IMUX35_9", - "CFG_CENTER_IMUX36_0", - "CFG_CENTER_IMUX36_1", - "CFG_CENTER_IMUX36_10", - "CFG_CENTER_IMUX36_11", - "CFG_CENTER_IMUX36_12", - "CFG_CENTER_IMUX36_13", - "CFG_CENTER_IMUX36_14", - "CFG_CENTER_IMUX36_15", - "CFG_CENTER_IMUX36_16", - "CFG_CENTER_IMUX36_17", - "CFG_CENTER_IMUX36_18", - "CFG_CENTER_IMUX36_19", - "CFG_CENTER_IMUX36_2", - "CFG_CENTER_IMUX36_3", - "CFG_CENTER_IMUX36_4", - "CFG_CENTER_IMUX36_5", - "CFG_CENTER_IMUX36_6", - "CFG_CENTER_IMUX36_7", - "CFG_CENTER_IMUX36_8", - "CFG_CENTER_IMUX36_9", - "CFG_CENTER_IMUX37_0", - "CFG_CENTER_IMUX37_1", - "CFG_CENTER_IMUX37_10", - "CFG_CENTER_IMUX37_11", - "CFG_CENTER_IMUX37_12", - "CFG_CENTER_IMUX37_13", - "CFG_CENTER_IMUX37_14", - "CFG_CENTER_IMUX37_15", - "CFG_CENTER_IMUX37_16", - "CFG_CENTER_IMUX37_17", - "CFG_CENTER_IMUX37_18", - "CFG_CENTER_IMUX37_19", - "CFG_CENTER_IMUX37_2", - "CFG_CENTER_IMUX37_3", - "CFG_CENTER_IMUX37_4", - "CFG_CENTER_IMUX37_5", - "CFG_CENTER_IMUX37_6", - "CFG_CENTER_IMUX37_7", - "CFG_CENTER_IMUX37_8", - "CFG_CENTER_IMUX37_9", - "CFG_CENTER_IMUX38_0", - "CFG_CENTER_IMUX38_1", - "CFG_CENTER_IMUX38_10", - "CFG_CENTER_IMUX38_11", - "CFG_CENTER_IMUX38_12", - "CFG_CENTER_IMUX38_13", - "CFG_CENTER_IMUX38_14", - "CFG_CENTER_IMUX38_15", - "CFG_CENTER_IMUX38_16", - "CFG_CENTER_IMUX38_17", - "CFG_CENTER_IMUX38_18", - "CFG_CENTER_IMUX38_19", - "CFG_CENTER_IMUX38_2", - "CFG_CENTER_IMUX38_3", - "CFG_CENTER_IMUX38_4", - "CFG_CENTER_IMUX38_5", - "CFG_CENTER_IMUX38_6", - "CFG_CENTER_IMUX38_7", - "CFG_CENTER_IMUX38_8", - "CFG_CENTER_IMUX38_9", - "CFG_CENTER_IMUX39_0", - "CFG_CENTER_IMUX39_1", - "CFG_CENTER_IMUX39_10", - "CFG_CENTER_IMUX39_11", - "CFG_CENTER_IMUX39_12", - "CFG_CENTER_IMUX39_13", - "CFG_CENTER_IMUX39_14", - "CFG_CENTER_IMUX39_15", - "CFG_CENTER_IMUX39_16", - "CFG_CENTER_IMUX39_17", - "CFG_CENTER_IMUX39_18", - "CFG_CENTER_IMUX39_19", - "CFG_CENTER_IMUX39_2", - "CFG_CENTER_IMUX39_3", - "CFG_CENTER_IMUX39_4", - "CFG_CENTER_IMUX39_5", - "CFG_CENTER_IMUX39_6", - "CFG_CENTER_IMUX39_7", - "CFG_CENTER_IMUX39_8", - "CFG_CENTER_IMUX39_9", - "CFG_CENTER_IMUX3_0", - "CFG_CENTER_IMUX3_1", - "CFG_CENTER_IMUX3_10", - "CFG_CENTER_IMUX3_11", - "CFG_CENTER_IMUX3_12", - "CFG_CENTER_IMUX3_13", - "CFG_CENTER_IMUX3_14", - "CFG_CENTER_IMUX3_15", - "CFG_CENTER_IMUX3_16", - "CFG_CENTER_IMUX3_17", - "CFG_CENTER_IMUX3_18", - "CFG_CENTER_IMUX3_19", - "CFG_CENTER_IMUX3_2", - "CFG_CENTER_IMUX3_3", - "CFG_CENTER_IMUX3_4", - "CFG_CENTER_IMUX3_5", - "CFG_CENTER_IMUX3_6", - "CFG_CENTER_IMUX3_7", - "CFG_CENTER_IMUX3_8", - "CFG_CENTER_IMUX3_9", - "CFG_CENTER_IMUX40_0", - "CFG_CENTER_IMUX40_1", - "CFG_CENTER_IMUX40_10", - "CFG_CENTER_IMUX40_11", - "CFG_CENTER_IMUX40_12", - "CFG_CENTER_IMUX40_13", - "CFG_CENTER_IMUX40_14", - "CFG_CENTER_IMUX40_15", - "CFG_CENTER_IMUX40_16", - "CFG_CENTER_IMUX40_17", - "CFG_CENTER_IMUX40_18", - "CFG_CENTER_IMUX40_19", - "CFG_CENTER_IMUX40_2", - "CFG_CENTER_IMUX40_3", - "CFG_CENTER_IMUX40_4", - "CFG_CENTER_IMUX40_5", - "CFG_CENTER_IMUX40_6", - "CFG_CENTER_IMUX40_7", - "CFG_CENTER_IMUX40_8", - "CFG_CENTER_IMUX40_9", - "CFG_CENTER_IMUX41_0", - "CFG_CENTER_IMUX41_1", - "CFG_CENTER_IMUX41_10", - "CFG_CENTER_IMUX41_11", - "CFG_CENTER_IMUX41_12", - "CFG_CENTER_IMUX41_13", - "CFG_CENTER_IMUX41_14", - "CFG_CENTER_IMUX41_15", - "CFG_CENTER_IMUX41_16", - "CFG_CENTER_IMUX41_17", - "CFG_CENTER_IMUX41_18", - "CFG_CENTER_IMUX41_19", - "CFG_CENTER_IMUX41_2", - "CFG_CENTER_IMUX41_3", - "CFG_CENTER_IMUX41_4", - "CFG_CENTER_IMUX41_5", - "CFG_CENTER_IMUX41_6", - "CFG_CENTER_IMUX41_7", - "CFG_CENTER_IMUX41_8", - "CFG_CENTER_IMUX41_9", - "CFG_CENTER_IMUX42_0", - "CFG_CENTER_IMUX42_1", - "CFG_CENTER_IMUX42_10", - "CFG_CENTER_IMUX42_11", - "CFG_CENTER_IMUX42_12", - "CFG_CENTER_IMUX42_13", - "CFG_CENTER_IMUX42_14", - "CFG_CENTER_IMUX42_15", - "CFG_CENTER_IMUX42_16", - "CFG_CENTER_IMUX42_17", - "CFG_CENTER_IMUX42_18", - "CFG_CENTER_IMUX42_19", - "CFG_CENTER_IMUX42_2", - "CFG_CENTER_IMUX42_3", - "CFG_CENTER_IMUX42_4", - "CFG_CENTER_IMUX42_5", - "CFG_CENTER_IMUX42_6", - "CFG_CENTER_IMUX42_7", - "CFG_CENTER_IMUX42_8", - "CFG_CENTER_IMUX42_9", - "CFG_CENTER_IMUX43_0", - "CFG_CENTER_IMUX43_1", - "CFG_CENTER_IMUX43_10", - "CFG_CENTER_IMUX43_11", - "CFG_CENTER_IMUX43_12", - "CFG_CENTER_IMUX43_13", - "CFG_CENTER_IMUX43_14", - "CFG_CENTER_IMUX43_15", - "CFG_CENTER_IMUX43_16", - "CFG_CENTER_IMUX43_17", - "CFG_CENTER_IMUX43_18", - "CFG_CENTER_IMUX43_19", - "CFG_CENTER_IMUX43_2", - "CFG_CENTER_IMUX43_3", - "CFG_CENTER_IMUX43_4", - "CFG_CENTER_IMUX43_5", - "CFG_CENTER_IMUX43_6", - "CFG_CENTER_IMUX43_7", - "CFG_CENTER_IMUX43_8", - "CFG_CENTER_IMUX43_9", - "CFG_CENTER_IMUX44_0", - "CFG_CENTER_IMUX44_1", - "CFG_CENTER_IMUX44_10", - "CFG_CENTER_IMUX44_11", - "CFG_CENTER_IMUX44_12", - "CFG_CENTER_IMUX44_13", - "CFG_CENTER_IMUX44_14", - "CFG_CENTER_IMUX44_15", - "CFG_CENTER_IMUX44_16", - "CFG_CENTER_IMUX44_17", - "CFG_CENTER_IMUX44_18", - "CFG_CENTER_IMUX44_19", - "CFG_CENTER_IMUX44_2", - "CFG_CENTER_IMUX44_3", - "CFG_CENTER_IMUX44_4", - "CFG_CENTER_IMUX44_5", - "CFG_CENTER_IMUX44_6", - "CFG_CENTER_IMUX44_7", - "CFG_CENTER_IMUX44_8", - "CFG_CENTER_IMUX44_9", - "CFG_CENTER_IMUX45_0", - "CFG_CENTER_IMUX45_1", - "CFG_CENTER_IMUX45_10", - "CFG_CENTER_IMUX45_11", - "CFG_CENTER_IMUX45_12", - "CFG_CENTER_IMUX45_13", - "CFG_CENTER_IMUX45_14", - "CFG_CENTER_IMUX45_15", - "CFG_CENTER_IMUX45_16", - "CFG_CENTER_IMUX45_17", - "CFG_CENTER_IMUX45_18", - "CFG_CENTER_IMUX45_19", - "CFG_CENTER_IMUX45_2", - "CFG_CENTER_IMUX45_3", - "CFG_CENTER_IMUX45_4", - "CFG_CENTER_IMUX45_5", - "CFG_CENTER_IMUX45_6", - "CFG_CENTER_IMUX45_7", - "CFG_CENTER_IMUX45_8", - "CFG_CENTER_IMUX45_9", - "CFG_CENTER_IMUX46_0", - "CFG_CENTER_IMUX46_1", - "CFG_CENTER_IMUX46_10", - "CFG_CENTER_IMUX46_11", - "CFG_CENTER_IMUX46_12", - "CFG_CENTER_IMUX46_13", - "CFG_CENTER_IMUX46_14", - "CFG_CENTER_IMUX46_15", - "CFG_CENTER_IMUX46_16", - "CFG_CENTER_IMUX46_17", - "CFG_CENTER_IMUX46_18", - "CFG_CENTER_IMUX46_19", - "CFG_CENTER_IMUX46_2", - "CFG_CENTER_IMUX46_3", - "CFG_CENTER_IMUX46_4", - "CFG_CENTER_IMUX46_5", - "CFG_CENTER_IMUX46_6", - "CFG_CENTER_IMUX46_7", - "CFG_CENTER_IMUX46_8", - "CFG_CENTER_IMUX46_9", - "CFG_CENTER_IMUX47_0", - "CFG_CENTER_IMUX47_1", - "CFG_CENTER_IMUX47_10", - "CFG_CENTER_IMUX47_11", - "CFG_CENTER_IMUX47_12", - "CFG_CENTER_IMUX47_13", - "CFG_CENTER_IMUX47_14", - "CFG_CENTER_IMUX47_15", - "CFG_CENTER_IMUX47_16", - "CFG_CENTER_IMUX47_17", - "CFG_CENTER_IMUX47_18", - "CFG_CENTER_IMUX47_19", - "CFG_CENTER_IMUX47_2", - "CFG_CENTER_IMUX47_3", - "CFG_CENTER_IMUX47_4", - "CFG_CENTER_IMUX47_5", - "CFG_CENTER_IMUX47_6", - "CFG_CENTER_IMUX47_7", - "CFG_CENTER_IMUX47_8", - "CFG_CENTER_IMUX47_9", - "CFG_CENTER_IMUX4_0", - "CFG_CENTER_IMUX4_1", - "CFG_CENTER_IMUX4_10", - "CFG_CENTER_IMUX4_11", - "CFG_CENTER_IMUX4_12", - "CFG_CENTER_IMUX4_13", - "CFG_CENTER_IMUX4_14", - "CFG_CENTER_IMUX4_15", - "CFG_CENTER_IMUX4_16", - "CFG_CENTER_IMUX4_17", - "CFG_CENTER_IMUX4_18", - "CFG_CENTER_IMUX4_19", - "CFG_CENTER_IMUX4_2", - "CFG_CENTER_IMUX4_3", - "CFG_CENTER_IMUX4_4", - "CFG_CENTER_IMUX4_5", - "CFG_CENTER_IMUX4_6", - "CFG_CENTER_IMUX4_7", - "CFG_CENTER_IMUX4_8", - "CFG_CENTER_IMUX4_9", - "CFG_CENTER_IMUX5_0", - "CFG_CENTER_IMUX5_1", - "CFG_CENTER_IMUX5_10", - "CFG_CENTER_IMUX5_11", - "CFG_CENTER_IMUX5_12", - "CFG_CENTER_IMUX5_13", - "CFG_CENTER_IMUX5_14", - "CFG_CENTER_IMUX5_15", - "CFG_CENTER_IMUX5_16", - "CFG_CENTER_IMUX5_17", - "CFG_CENTER_IMUX5_18", - "CFG_CENTER_IMUX5_19", - "CFG_CENTER_IMUX5_2", - "CFG_CENTER_IMUX5_3", - "CFG_CENTER_IMUX5_4", - "CFG_CENTER_IMUX5_5", - "CFG_CENTER_IMUX5_6", - "CFG_CENTER_IMUX5_7", - "CFG_CENTER_IMUX5_8", - "CFG_CENTER_IMUX5_9", - "CFG_CENTER_IMUX6_0", - "CFG_CENTER_IMUX6_1", - "CFG_CENTER_IMUX6_10", - "CFG_CENTER_IMUX6_11", - "CFG_CENTER_IMUX6_12", - "CFG_CENTER_IMUX6_13", - "CFG_CENTER_IMUX6_14", - "CFG_CENTER_IMUX6_15", - "CFG_CENTER_IMUX6_16", - "CFG_CENTER_IMUX6_17", - "CFG_CENTER_IMUX6_18", - "CFG_CENTER_IMUX6_19", - "CFG_CENTER_IMUX6_2", - "CFG_CENTER_IMUX6_3", - "CFG_CENTER_IMUX6_4", - "CFG_CENTER_IMUX6_5", - "CFG_CENTER_IMUX6_6", - "CFG_CENTER_IMUX6_7", - "CFG_CENTER_IMUX6_8", - "CFG_CENTER_IMUX6_9", - "CFG_CENTER_IMUX7_0", - "CFG_CENTER_IMUX7_1", - "CFG_CENTER_IMUX7_10", - "CFG_CENTER_IMUX7_11", - "CFG_CENTER_IMUX7_12", - "CFG_CENTER_IMUX7_13", - "CFG_CENTER_IMUX7_14", - "CFG_CENTER_IMUX7_15", - "CFG_CENTER_IMUX7_16", - "CFG_CENTER_IMUX7_17", - "CFG_CENTER_IMUX7_18", - "CFG_CENTER_IMUX7_19", - "CFG_CENTER_IMUX7_2", - "CFG_CENTER_IMUX7_3", - "CFG_CENTER_IMUX7_4", - "CFG_CENTER_IMUX7_5", - "CFG_CENTER_IMUX7_6", - "CFG_CENTER_IMUX7_7", - "CFG_CENTER_IMUX7_8", - "CFG_CENTER_IMUX7_9", - "CFG_CENTER_IMUX8_0", - "CFG_CENTER_IMUX8_1", - "CFG_CENTER_IMUX8_10", - "CFG_CENTER_IMUX8_11", - "CFG_CENTER_IMUX8_12", - "CFG_CENTER_IMUX8_13", - "CFG_CENTER_IMUX8_14", - "CFG_CENTER_IMUX8_15", - "CFG_CENTER_IMUX8_16", - "CFG_CENTER_IMUX8_17", - "CFG_CENTER_IMUX8_18", - "CFG_CENTER_IMUX8_19", - "CFG_CENTER_IMUX8_2", - "CFG_CENTER_IMUX8_3", - "CFG_CENTER_IMUX8_4", - "CFG_CENTER_IMUX8_5", - "CFG_CENTER_IMUX8_6", - "CFG_CENTER_IMUX8_7", - "CFG_CENTER_IMUX8_8", - "CFG_CENTER_IMUX8_9", - "CFG_CENTER_IMUX9_0", - "CFG_CENTER_IMUX9_1", - "CFG_CENTER_IMUX9_10", - "CFG_CENTER_IMUX9_11", - "CFG_CENTER_IMUX9_12", - "CFG_CENTER_IMUX9_13", - "CFG_CENTER_IMUX9_14", - "CFG_CENTER_IMUX9_15", - "CFG_CENTER_IMUX9_16", - "CFG_CENTER_IMUX9_17", - "CFG_CENTER_IMUX9_18", - "CFG_CENTER_IMUX9_19", - "CFG_CENTER_IMUX9_2", - "CFG_CENTER_IMUX9_3", - "CFG_CENTER_IMUX9_4", - "CFG_CENTER_IMUX9_5", - "CFG_CENTER_IMUX9_6", - "CFG_CENTER_IMUX9_7", - "CFG_CENTER_IMUX9_8", - "CFG_CENTER_IMUX9_9", - "CFG_CENTER_LH10_0", - "CFG_CENTER_LH10_1", - "CFG_CENTER_LH10_10", - "CFG_CENTER_LH10_11", - "CFG_CENTER_LH10_12", - "CFG_CENTER_LH10_13", - "CFG_CENTER_LH10_14", - "CFG_CENTER_LH10_15", - "CFG_CENTER_LH10_16", - "CFG_CENTER_LH10_17", - "CFG_CENTER_LH10_18", - "CFG_CENTER_LH10_19", - "CFG_CENTER_LH10_2", - "CFG_CENTER_LH10_3", - "CFG_CENTER_LH10_4", - "CFG_CENTER_LH10_5", - "CFG_CENTER_LH10_6", - "CFG_CENTER_LH10_7", - "CFG_CENTER_LH10_8", - "CFG_CENTER_LH10_9", - "CFG_CENTER_LH11_0", - "CFG_CENTER_LH11_1", - "CFG_CENTER_LH11_10", - "CFG_CENTER_LH11_11", - "CFG_CENTER_LH11_12", - "CFG_CENTER_LH11_13", - "CFG_CENTER_LH11_14", - "CFG_CENTER_LH11_15", - "CFG_CENTER_LH11_16", - "CFG_CENTER_LH11_17", - "CFG_CENTER_LH11_18", - "CFG_CENTER_LH11_19", - "CFG_CENTER_LH11_2", - "CFG_CENTER_LH11_3", - "CFG_CENTER_LH11_4", - "CFG_CENTER_LH11_5", - "CFG_CENTER_LH11_6", - "CFG_CENTER_LH11_7", - "CFG_CENTER_LH11_8", - "CFG_CENTER_LH11_9", - "CFG_CENTER_LH12_0", - "CFG_CENTER_LH12_1", - "CFG_CENTER_LH12_10", - "CFG_CENTER_LH12_11", - "CFG_CENTER_LH12_12", - "CFG_CENTER_LH12_13", - "CFG_CENTER_LH12_14", - "CFG_CENTER_LH12_15", - "CFG_CENTER_LH12_16", - "CFG_CENTER_LH12_17", - "CFG_CENTER_LH12_18", - "CFG_CENTER_LH12_19", - "CFG_CENTER_LH12_2", - "CFG_CENTER_LH12_3", - "CFG_CENTER_LH12_4", - "CFG_CENTER_LH12_5", - "CFG_CENTER_LH12_6", - "CFG_CENTER_LH12_7", - "CFG_CENTER_LH12_8", - "CFG_CENTER_LH12_9", - "CFG_CENTER_LH1_0", - "CFG_CENTER_LH1_1", - "CFG_CENTER_LH1_10", - "CFG_CENTER_LH1_11", - "CFG_CENTER_LH1_12", - "CFG_CENTER_LH1_13", - "CFG_CENTER_LH1_14", - "CFG_CENTER_LH1_15", - "CFG_CENTER_LH1_16", - "CFG_CENTER_LH1_17", - "CFG_CENTER_LH1_18", - "CFG_CENTER_LH1_19", - "CFG_CENTER_LH1_2", - "CFG_CENTER_LH1_3", - "CFG_CENTER_LH1_4", - "CFG_CENTER_LH1_5", - "CFG_CENTER_LH1_6", - "CFG_CENTER_LH1_7", - "CFG_CENTER_LH1_8", - "CFG_CENTER_LH1_9", - "CFG_CENTER_LH2_0", - "CFG_CENTER_LH2_1", - "CFG_CENTER_LH2_10", - "CFG_CENTER_LH2_11", - "CFG_CENTER_LH2_12", - "CFG_CENTER_LH2_13", - "CFG_CENTER_LH2_14", - "CFG_CENTER_LH2_15", - "CFG_CENTER_LH2_16", - "CFG_CENTER_LH2_17", - "CFG_CENTER_LH2_18", - "CFG_CENTER_LH2_19", - "CFG_CENTER_LH2_2", - "CFG_CENTER_LH2_3", - "CFG_CENTER_LH2_4", - "CFG_CENTER_LH2_5", - "CFG_CENTER_LH2_6", - "CFG_CENTER_LH2_7", - "CFG_CENTER_LH2_8", - "CFG_CENTER_LH2_9", - "CFG_CENTER_LH3_0", - "CFG_CENTER_LH3_1", - "CFG_CENTER_LH3_10", - "CFG_CENTER_LH3_11", - "CFG_CENTER_LH3_12", - "CFG_CENTER_LH3_13", - "CFG_CENTER_LH3_14", - "CFG_CENTER_LH3_15", - "CFG_CENTER_LH3_16", - "CFG_CENTER_LH3_17", - "CFG_CENTER_LH3_18", - "CFG_CENTER_LH3_19", - "CFG_CENTER_LH3_2", - "CFG_CENTER_LH3_3", - "CFG_CENTER_LH3_4", - "CFG_CENTER_LH3_5", - "CFG_CENTER_LH3_6", - "CFG_CENTER_LH3_7", - "CFG_CENTER_LH3_8", - "CFG_CENTER_LH3_9", - "CFG_CENTER_LH4_0", - "CFG_CENTER_LH4_1", - "CFG_CENTER_LH4_10", - "CFG_CENTER_LH4_11", - "CFG_CENTER_LH4_12", - "CFG_CENTER_LH4_13", - "CFG_CENTER_LH4_14", - "CFG_CENTER_LH4_15", - "CFG_CENTER_LH4_16", - "CFG_CENTER_LH4_17", - "CFG_CENTER_LH4_18", - "CFG_CENTER_LH4_19", - "CFG_CENTER_LH4_2", - "CFG_CENTER_LH4_3", - "CFG_CENTER_LH4_4", - "CFG_CENTER_LH4_5", - "CFG_CENTER_LH4_6", - "CFG_CENTER_LH4_7", - "CFG_CENTER_LH4_8", - "CFG_CENTER_LH4_9", - "CFG_CENTER_LH5_0", - "CFG_CENTER_LH5_1", - "CFG_CENTER_LH5_10", - "CFG_CENTER_LH5_11", - "CFG_CENTER_LH5_12", - "CFG_CENTER_LH5_13", - "CFG_CENTER_LH5_14", - "CFG_CENTER_LH5_15", - "CFG_CENTER_LH5_16", - "CFG_CENTER_LH5_17", - "CFG_CENTER_LH5_18", - "CFG_CENTER_LH5_19", - "CFG_CENTER_LH5_2", - "CFG_CENTER_LH5_3", - "CFG_CENTER_LH5_4", - "CFG_CENTER_LH5_5", - "CFG_CENTER_LH5_6", - "CFG_CENTER_LH5_7", - "CFG_CENTER_LH5_8", - "CFG_CENTER_LH5_9", - "CFG_CENTER_LH6_0", - "CFG_CENTER_LH6_1", - "CFG_CENTER_LH6_10", - "CFG_CENTER_LH6_11", - "CFG_CENTER_LH6_12", - "CFG_CENTER_LH6_13", - "CFG_CENTER_LH6_14", - "CFG_CENTER_LH6_15", - "CFG_CENTER_LH6_16", - "CFG_CENTER_LH6_17", - "CFG_CENTER_LH6_18", - "CFG_CENTER_LH6_19", - "CFG_CENTER_LH6_2", - "CFG_CENTER_LH6_3", - "CFG_CENTER_LH6_4", - "CFG_CENTER_LH6_5", - "CFG_CENTER_LH6_6", - "CFG_CENTER_LH6_7", - "CFG_CENTER_LH6_8", - "CFG_CENTER_LH6_9", - "CFG_CENTER_LH7_0", - "CFG_CENTER_LH7_1", - "CFG_CENTER_LH7_10", - "CFG_CENTER_LH7_11", - "CFG_CENTER_LH7_12", - "CFG_CENTER_LH7_13", - "CFG_CENTER_LH7_14", - "CFG_CENTER_LH7_15", - "CFG_CENTER_LH7_16", - "CFG_CENTER_LH7_17", - "CFG_CENTER_LH7_18", - "CFG_CENTER_LH7_19", - "CFG_CENTER_LH7_2", - "CFG_CENTER_LH7_3", - "CFG_CENTER_LH7_4", - "CFG_CENTER_LH7_5", - "CFG_CENTER_LH7_6", - "CFG_CENTER_LH7_7", - "CFG_CENTER_LH7_8", - "CFG_CENTER_LH7_9", - "CFG_CENTER_LH8_0", - "CFG_CENTER_LH8_1", - "CFG_CENTER_LH8_10", - "CFG_CENTER_LH8_11", - "CFG_CENTER_LH8_12", - "CFG_CENTER_LH8_13", - "CFG_CENTER_LH8_14", - "CFG_CENTER_LH8_15", - "CFG_CENTER_LH8_16", - "CFG_CENTER_LH8_17", - "CFG_CENTER_LH8_18", - "CFG_CENTER_LH8_19", - "CFG_CENTER_LH8_2", - "CFG_CENTER_LH8_3", - "CFG_CENTER_LH8_4", - "CFG_CENTER_LH8_5", - "CFG_CENTER_LH8_6", - "CFG_CENTER_LH8_7", - "CFG_CENTER_LH8_8", - "CFG_CENTER_LH8_9", - "CFG_CENTER_LH9_0", - "CFG_CENTER_LH9_1", - "CFG_CENTER_LH9_10", - "CFG_CENTER_LH9_11", - "CFG_CENTER_LH9_12", - "CFG_CENTER_LH9_13", - "CFG_CENTER_LH9_14", - "CFG_CENTER_LH9_15", - "CFG_CENTER_LH9_16", - "CFG_CENTER_LH9_17", - "CFG_CENTER_LH9_18", - "CFG_CENTER_LH9_19", - "CFG_CENTER_LH9_2", - "CFG_CENTER_LH9_3", - "CFG_CENTER_LH9_4", - "CFG_CENTER_LH9_5", - "CFG_CENTER_LH9_6", - "CFG_CENTER_LH9_7", - "CFG_CENTER_LH9_8", - "CFG_CENTER_LH9_9", - "CFG_CENTER_LOGIC_OUTS_B0_0", - "CFG_CENTER_LOGIC_OUTS_B0_1", - "CFG_CENTER_LOGIC_OUTS_B0_10", - "CFG_CENTER_LOGIC_OUTS_B0_11", - "CFG_CENTER_LOGIC_OUTS_B0_12", - "CFG_CENTER_LOGIC_OUTS_B0_13", - "CFG_CENTER_LOGIC_OUTS_B0_14", - "CFG_CENTER_LOGIC_OUTS_B0_15", - "CFG_CENTER_LOGIC_OUTS_B0_16", - "CFG_CENTER_LOGIC_OUTS_B0_17", - "CFG_CENTER_LOGIC_OUTS_B0_18", - "CFG_CENTER_LOGIC_OUTS_B0_19", - "CFG_CENTER_LOGIC_OUTS_B0_2", - "CFG_CENTER_LOGIC_OUTS_B0_3", - "CFG_CENTER_LOGIC_OUTS_B0_4", - "CFG_CENTER_LOGIC_OUTS_B0_5", - "CFG_CENTER_LOGIC_OUTS_B0_6", - "CFG_CENTER_LOGIC_OUTS_B0_7", - "CFG_CENTER_LOGIC_OUTS_B0_8", - "CFG_CENTER_LOGIC_OUTS_B0_9", - "CFG_CENTER_LOGIC_OUTS_B10_0", - "CFG_CENTER_LOGIC_OUTS_B10_1", - "CFG_CENTER_LOGIC_OUTS_B10_10", - "CFG_CENTER_LOGIC_OUTS_B10_11", - "CFG_CENTER_LOGIC_OUTS_B10_12", - "CFG_CENTER_LOGIC_OUTS_B10_13", - "CFG_CENTER_LOGIC_OUTS_B10_14", - "CFG_CENTER_LOGIC_OUTS_B10_15", - "CFG_CENTER_LOGIC_OUTS_B10_16", - "CFG_CENTER_LOGIC_OUTS_B10_17", - "CFG_CENTER_LOGIC_OUTS_B10_18", - "CFG_CENTER_LOGIC_OUTS_B10_19", - "CFG_CENTER_LOGIC_OUTS_B10_2", - "CFG_CENTER_LOGIC_OUTS_B10_3", - "CFG_CENTER_LOGIC_OUTS_B10_4", - "CFG_CENTER_LOGIC_OUTS_B10_5", - "CFG_CENTER_LOGIC_OUTS_B10_6", - "CFG_CENTER_LOGIC_OUTS_B10_7", - "CFG_CENTER_LOGIC_OUTS_B10_8", - "CFG_CENTER_LOGIC_OUTS_B10_9", - "CFG_CENTER_LOGIC_OUTS_B11_0", - "CFG_CENTER_LOGIC_OUTS_B11_1", - "CFG_CENTER_LOGIC_OUTS_B11_10", - "CFG_CENTER_LOGIC_OUTS_B11_11", - "CFG_CENTER_LOGIC_OUTS_B11_12", - "CFG_CENTER_LOGIC_OUTS_B11_13", - "CFG_CENTER_LOGIC_OUTS_B11_14", - "CFG_CENTER_LOGIC_OUTS_B11_15", - "CFG_CENTER_LOGIC_OUTS_B11_16", - "CFG_CENTER_LOGIC_OUTS_B11_17", - "CFG_CENTER_LOGIC_OUTS_B11_18", - "CFG_CENTER_LOGIC_OUTS_B11_19", - "CFG_CENTER_LOGIC_OUTS_B11_2", - "CFG_CENTER_LOGIC_OUTS_B11_3", - "CFG_CENTER_LOGIC_OUTS_B11_4", - "CFG_CENTER_LOGIC_OUTS_B11_5", - "CFG_CENTER_LOGIC_OUTS_B11_6", - "CFG_CENTER_LOGIC_OUTS_B11_7", - "CFG_CENTER_LOGIC_OUTS_B11_8", - "CFG_CENTER_LOGIC_OUTS_B11_9", - "CFG_CENTER_LOGIC_OUTS_B12_0", - "CFG_CENTER_LOGIC_OUTS_B12_1", - "CFG_CENTER_LOGIC_OUTS_B12_10", - "CFG_CENTER_LOGIC_OUTS_B12_11", - "CFG_CENTER_LOGIC_OUTS_B12_12", - "CFG_CENTER_LOGIC_OUTS_B12_13", - "CFG_CENTER_LOGIC_OUTS_B12_14", - "CFG_CENTER_LOGIC_OUTS_B12_15", - "CFG_CENTER_LOGIC_OUTS_B12_16", - "CFG_CENTER_LOGIC_OUTS_B12_17", - "CFG_CENTER_LOGIC_OUTS_B12_18", - "CFG_CENTER_LOGIC_OUTS_B12_19", - "CFG_CENTER_LOGIC_OUTS_B12_2", - "CFG_CENTER_LOGIC_OUTS_B12_3", - "CFG_CENTER_LOGIC_OUTS_B12_4", - "CFG_CENTER_LOGIC_OUTS_B12_5", - "CFG_CENTER_LOGIC_OUTS_B12_6", - "CFG_CENTER_LOGIC_OUTS_B12_7", - "CFG_CENTER_LOGIC_OUTS_B12_8", - "CFG_CENTER_LOGIC_OUTS_B12_9", - "CFG_CENTER_LOGIC_OUTS_B13_0", - "CFG_CENTER_LOGIC_OUTS_B13_1", - "CFG_CENTER_LOGIC_OUTS_B13_10", - "CFG_CENTER_LOGIC_OUTS_B13_11", - "CFG_CENTER_LOGIC_OUTS_B13_12", - "CFG_CENTER_LOGIC_OUTS_B13_13", - "CFG_CENTER_LOGIC_OUTS_B13_14", - "CFG_CENTER_LOGIC_OUTS_B13_15", - "CFG_CENTER_LOGIC_OUTS_B13_16", - "CFG_CENTER_LOGIC_OUTS_B13_17", - "CFG_CENTER_LOGIC_OUTS_B13_18", - "CFG_CENTER_LOGIC_OUTS_B13_19", - "CFG_CENTER_LOGIC_OUTS_B13_2", - "CFG_CENTER_LOGIC_OUTS_B13_3", - "CFG_CENTER_LOGIC_OUTS_B13_4", - "CFG_CENTER_LOGIC_OUTS_B13_5", - "CFG_CENTER_LOGIC_OUTS_B13_6", - "CFG_CENTER_LOGIC_OUTS_B13_7", - "CFG_CENTER_LOGIC_OUTS_B13_8", - "CFG_CENTER_LOGIC_OUTS_B13_9", - "CFG_CENTER_LOGIC_OUTS_B14_0", - "CFG_CENTER_LOGIC_OUTS_B14_1", - "CFG_CENTER_LOGIC_OUTS_B14_10", - "CFG_CENTER_LOGIC_OUTS_B14_11", - "CFG_CENTER_LOGIC_OUTS_B14_12", - "CFG_CENTER_LOGIC_OUTS_B14_13", - "CFG_CENTER_LOGIC_OUTS_B14_14", - "CFG_CENTER_LOGIC_OUTS_B14_15", - "CFG_CENTER_LOGIC_OUTS_B14_16", - "CFG_CENTER_LOGIC_OUTS_B14_17", - "CFG_CENTER_LOGIC_OUTS_B14_18", - "CFG_CENTER_LOGIC_OUTS_B14_19", - "CFG_CENTER_LOGIC_OUTS_B14_2", - "CFG_CENTER_LOGIC_OUTS_B14_3", - "CFG_CENTER_LOGIC_OUTS_B14_4", - "CFG_CENTER_LOGIC_OUTS_B14_5", - "CFG_CENTER_LOGIC_OUTS_B14_6", - "CFG_CENTER_LOGIC_OUTS_B14_7", - "CFG_CENTER_LOGIC_OUTS_B14_8", - "CFG_CENTER_LOGIC_OUTS_B14_9", - "CFG_CENTER_LOGIC_OUTS_B15_0", - "CFG_CENTER_LOGIC_OUTS_B15_1", - "CFG_CENTER_LOGIC_OUTS_B15_10", - "CFG_CENTER_LOGIC_OUTS_B15_11", - "CFG_CENTER_LOGIC_OUTS_B15_12", - "CFG_CENTER_LOGIC_OUTS_B15_13", - "CFG_CENTER_LOGIC_OUTS_B15_14", - "CFG_CENTER_LOGIC_OUTS_B15_15", - "CFG_CENTER_LOGIC_OUTS_B15_16", - "CFG_CENTER_LOGIC_OUTS_B15_17", - "CFG_CENTER_LOGIC_OUTS_B15_18", - "CFG_CENTER_LOGIC_OUTS_B15_19", - "CFG_CENTER_LOGIC_OUTS_B15_2", - "CFG_CENTER_LOGIC_OUTS_B15_3", - "CFG_CENTER_LOGIC_OUTS_B15_4", - "CFG_CENTER_LOGIC_OUTS_B15_5", - "CFG_CENTER_LOGIC_OUTS_B15_6", - "CFG_CENTER_LOGIC_OUTS_B15_7", - "CFG_CENTER_LOGIC_OUTS_B15_8", - "CFG_CENTER_LOGIC_OUTS_B15_9", - "CFG_CENTER_LOGIC_OUTS_B16_0", - "CFG_CENTER_LOGIC_OUTS_B16_1", - "CFG_CENTER_LOGIC_OUTS_B16_10", - "CFG_CENTER_LOGIC_OUTS_B16_11", - "CFG_CENTER_LOGIC_OUTS_B16_12", - "CFG_CENTER_LOGIC_OUTS_B16_13", - "CFG_CENTER_LOGIC_OUTS_B16_14", - "CFG_CENTER_LOGIC_OUTS_B16_15", - "CFG_CENTER_LOGIC_OUTS_B16_16", - "CFG_CENTER_LOGIC_OUTS_B16_17", - "CFG_CENTER_LOGIC_OUTS_B16_18", - "CFG_CENTER_LOGIC_OUTS_B16_19", - "CFG_CENTER_LOGIC_OUTS_B16_2", - "CFG_CENTER_LOGIC_OUTS_B16_3", - "CFG_CENTER_LOGIC_OUTS_B16_4", - "CFG_CENTER_LOGIC_OUTS_B16_5", - "CFG_CENTER_LOGIC_OUTS_B16_6", - "CFG_CENTER_LOGIC_OUTS_B16_7", - "CFG_CENTER_LOGIC_OUTS_B16_8", - "CFG_CENTER_LOGIC_OUTS_B16_9", - "CFG_CENTER_LOGIC_OUTS_B17_0", - "CFG_CENTER_LOGIC_OUTS_B17_1", - "CFG_CENTER_LOGIC_OUTS_B17_10", - "CFG_CENTER_LOGIC_OUTS_B17_11", - "CFG_CENTER_LOGIC_OUTS_B17_12", - "CFG_CENTER_LOGIC_OUTS_B17_13", - "CFG_CENTER_LOGIC_OUTS_B17_14", - "CFG_CENTER_LOGIC_OUTS_B17_15", - "CFG_CENTER_LOGIC_OUTS_B17_16", - "CFG_CENTER_LOGIC_OUTS_B17_17", - "CFG_CENTER_LOGIC_OUTS_B17_18", - "CFG_CENTER_LOGIC_OUTS_B17_19", - "CFG_CENTER_LOGIC_OUTS_B17_2", - "CFG_CENTER_LOGIC_OUTS_B17_3", - "CFG_CENTER_LOGIC_OUTS_B17_4", - "CFG_CENTER_LOGIC_OUTS_B17_5", - "CFG_CENTER_LOGIC_OUTS_B17_6", - "CFG_CENTER_LOGIC_OUTS_B17_7", - "CFG_CENTER_LOGIC_OUTS_B17_8", - "CFG_CENTER_LOGIC_OUTS_B17_9", - "CFG_CENTER_LOGIC_OUTS_B18_0", - "CFG_CENTER_LOGIC_OUTS_B18_1", - "CFG_CENTER_LOGIC_OUTS_B18_10", - "CFG_CENTER_LOGIC_OUTS_B18_11", - "CFG_CENTER_LOGIC_OUTS_B18_12", - "CFG_CENTER_LOGIC_OUTS_B18_13", - "CFG_CENTER_LOGIC_OUTS_B18_14", - "CFG_CENTER_LOGIC_OUTS_B18_15", - "CFG_CENTER_LOGIC_OUTS_B18_16", - "CFG_CENTER_LOGIC_OUTS_B18_17", - "CFG_CENTER_LOGIC_OUTS_B18_18", - "CFG_CENTER_LOGIC_OUTS_B18_19", - "CFG_CENTER_LOGIC_OUTS_B18_2", - "CFG_CENTER_LOGIC_OUTS_B18_3", - "CFG_CENTER_LOGIC_OUTS_B18_4", - "CFG_CENTER_LOGIC_OUTS_B18_5", - "CFG_CENTER_LOGIC_OUTS_B18_6", - "CFG_CENTER_LOGIC_OUTS_B18_7", - "CFG_CENTER_LOGIC_OUTS_B18_8", - "CFG_CENTER_LOGIC_OUTS_B18_9", - "CFG_CENTER_LOGIC_OUTS_B19_0", - "CFG_CENTER_LOGIC_OUTS_B19_1", - "CFG_CENTER_LOGIC_OUTS_B19_10", - "CFG_CENTER_LOGIC_OUTS_B19_11", - "CFG_CENTER_LOGIC_OUTS_B19_12", - "CFG_CENTER_LOGIC_OUTS_B19_13", - "CFG_CENTER_LOGIC_OUTS_B19_14", - "CFG_CENTER_LOGIC_OUTS_B19_15", - "CFG_CENTER_LOGIC_OUTS_B19_16", - "CFG_CENTER_LOGIC_OUTS_B19_17", - "CFG_CENTER_LOGIC_OUTS_B19_18", - "CFG_CENTER_LOGIC_OUTS_B19_19", - "CFG_CENTER_LOGIC_OUTS_B19_2", - "CFG_CENTER_LOGIC_OUTS_B19_3", - "CFG_CENTER_LOGIC_OUTS_B19_4", - "CFG_CENTER_LOGIC_OUTS_B19_5", - "CFG_CENTER_LOGIC_OUTS_B19_6", - "CFG_CENTER_LOGIC_OUTS_B19_7", - "CFG_CENTER_LOGIC_OUTS_B19_8", - "CFG_CENTER_LOGIC_OUTS_B19_9", - "CFG_CENTER_LOGIC_OUTS_B1_0", - "CFG_CENTER_LOGIC_OUTS_B1_1", - "CFG_CENTER_LOGIC_OUTS_B1_10", - "CFG_CENTER_LOGIC_OUTS_B1_11", - "CFG_CENTER_LOGIC_OUTS_B1_12", - "CFG_CENTER_LOGIC_OUTS_B1_13", - "CFG_CENTER_LOGIC_OUTS_B1_14", - "CFG_CENTER_LOGIC_OUTS_B1_15", - "CFG_CENTER_LOGIC_OUTS_B1_16", - "CFG_CENTER_LOGIC_OUTS_B1_17", - "CFG_CENTER_LOGIC_OUTS_B1_18", - "CFG_CENTER_LOGIC_OUTS_B1_19", - "CFG_CENTER_LOGIC_OUTS_B1_2", - "CFG_CENTER_LOGIC_OUTS_B1_3", - "CFG_CENTER_LOGIC_OUTS_B1_4", - "CFG_CENTER_LOGIC_OUTS_B1_5", - "CFG_CENTER_LOGIC_OUTS_B1_6", - "CFG_CENTER_LOGIC_OUTS_B1_7", - "CFG_CENTER_LOGIC_OUTS_B1_8", - "CFG_CENTER_LOGIC_OUTS_B1_9", - "CFG_CENTER_LOGIC_OUTS_B20_0", - "CFG_CENTER_LOGIC_OUTS_B20_1", - "CFG_CENTER_LOGIC_OUTS_B20_10", - "CFG_CENTER_LOGIC_OUTS_B20_11", - "CFG_CENTER_LOGIC_OUTS_B20_12", - "CFG_CENTER_LOGIC_OUTS_B20_13", - "CFG_CENTER_LOGIC_OUTS_B20_14", - "CFG_CENTER_LOGIC_OUTS_B20_15", - "CFG_CENTER_LOGIC_OUTS_B20_16", - "CFG_CENTER_LOGIC_OUTS_B20_17", - "CFG_CENTER_LOGIC_OUTS_B20_18", - "CFG_CENTER_LOGIC_OUTS_B20_19", - "CFG_CENTER_LOGIC_OUTS_B20_2", - "CFG_CENTER_LOGIC_OUTS_B20_3", - "CFG_CENTER_LOGIC_OUTS_B20_4", - "CFG_CENTER_LOGIC_OUTS_B20_5", - "CFG_CENTER_LOGIC_OUTS_B20_6", - "CFG_CENTER_LOGIC_OUTS_B20_7", - "CFG_CENTER_LOGIC_OUTS_B20_8", - "CFG_CENTER_LOGIC_OUTS_B20_9", - "CFG_CENTER_LOGIC_OUTS_B21_0", - "CFG_CENTER_LOGIC_OUTS_B21_1", - "CFG_CENTER_LOGIC_OUTS_B21_10", - "CFG_CENTER_LOGIC_OUTS_B21_11", - "CFG_CENTER_LOGIC_OUTS_B21_12", - "CFG_CENTER_LOGIC_OUTS_B21_13", - "CFG_CENTER_LOGIC_OUTS_B21_14", - "CFG_CENTER_LOGIC_OUTS_B21_15", - "CFG_CENTER_LOGIC_OUTS_B21_16", - "CFG_CENTER_LOGIC_OUTS_B21_17", - "CFG_CENTER_LOGIC_OUTS_B21_18", - "CFG_CENTER_LOGIC_OUTS_B21_19", - "CFG_CENTER_LOGIC_OUTS_B21_2", - "CFG_CENTER_LOGIC_OUTS_B21_3", - "CFG_CENTER_LOGIC_OUTS_B21_4", - "CFG_CENTER_LOGIC_OUTS_B21_5", - "CFG_CENTER_LOGIC_OUTS_B21_6", - "CFG_CENTER_LOGIC_OUTS_B21_7", - "CFG_CENTER_LOGIC_OUTS_B21_8", - "CFG_CENTER_LOGIC_OUTS_B21_9", - "CFG_CENTER_LOGIC_OUTS_B22_0", - "CFG_CENTER_LOGIC_OUTS_B22_1", - "CFG_CENTER_LOGIC_OUTS_B22_10", - "CFG_CENTER_LOGIC_OUTS_B22_11", - "CFG_CENTER_LOGIC_OUTS_B22_12", - "CFG_CENTER_LOGIC_OUTS_B22_13", - "CFG_CENTER_LOGIC_OUTS_B22_14", - "CFG_CENTER_LOGIC_OUTS_B22_15", - "CFG_CENTER_LOGIC_OUTS_B22_16", - "CFG_CENTER_LOGIC_OUTS_B22_17", - "CFG_CENTER_LOGIC_OUTS_B22_18", - "CFG_CENTER_LOGIC_OUTS_B22_19", - "CFG_CENTER_LOGIC_OUTS_B22_2", - "CFG_CENTER_LOGIC_OUTS_B22_3", - "CFG_CENTER_LOGIC_OUTS_B22_4", - "CFG_CENTER_LOGIC_OUTS_B22_5", - "CFG_CENTER_LOGIC_OUTS_B22_6", - "CFG_CENTER_LOGIC_OUTS_B22_7", - "CFG_CENTER_LOGIC_OUTS_B22_8", - "CFG_CENTER_LOGIC_OUTS_B22_9", - "CFG_CENTER_LOGIC_OUTS_B23_0", - "CFG_CENTER_LOGIC_OUTS_B23_1", - "CFG_CENTER_LOGIC_OUTS_B23_10", - "CFG_CENTER_LOGIC_OUTS_B23_11", - "CFG_CENTER_LOGIC_OUTS_B23_12", - "CFG_CENTER_LOGIC_OUTS_B23_13", - "CFG_CENTER_LOGIC_OUTS_B23_14", - "CFG_CENTER_LOGIC_OUTS_B23_15", - "CFG_CENTER_LOGIC_OUTS_B23_16", - "CFG_CENTER_LOGIC_OUTS_B23_17", - "CFG_CENTER_LOGIC_OUTS_B23_18", - "CFG_CENTER_LOGIC_OUTS_B23_19", - "CFG_CENTER_LOGIC_OUTS_B23_2", - "CFG_CENTER_LOGIC_OUTS_B23_3", - "CFG_CENTER_LOGIC_OUTS_B23_4", - "CFG_CENTER_LOGIC_OUTS_B23_5", - "CFG_CENTER_LOGIC_OUTS_B23_6", - "CFG_CENTER_LOGIC_OUTS_B23_7", - "CFG_CENTER_LOGIC_OUTS_B23_8", - "CFG_CENTER_LOGIC_OUTS_B23_9", - "CFG_CENTER_LOGIC_OUTS_B2_0", - "CFG_CENTER_LOGIC_OUTS_B2_1", - "CFG_CENTER_LOGIC_OUTS_B2_10", - "CFG_CENTER_LOGIC_OUTS_B2_11", - "CFG_CENTER_LOGIC_OUTS_B2_12", - "CFG_CENTER_LOGIC_OUTS_B2_13", - "CFG_CENTER_LOGIC_OUTS_B2_14", - "CFG_CENTER_LOGIC_OUTS_B2_15", - "CFG_CENTER_LOGIC_OUTS_B2_16", - "CFG_CENTER_LOGIC_OUTS_B2_17", - "CFG_CENTER_LOGIC_OUTS_B2_18", - "CFG_CENTER_LOGIC_OUTS_B2_19", - "CFG_CENTER_LOGIC_OUTS_B2_2", - "CFG_CENTER_LOGIC_OUTS_B2_3", - "CFG_CENTER_LOGIC_OUTS_B2_4", - "CFG_CENTER_LOGIC_OUTS_B2_5", - "CFG_CENTER_LOGIC_OUTS_B2_6", - "CFG_CENTER_LOGIC_OUTS_B2_7", - "CFG_CENTER_LOGIC_OUTS_B2_8", - "CFG_CENTER_LOGIC_OUTS_B2_9", - "CFG_CENTER_LOGIC_OUTS_B3_0", - "CFG_CENTER_LOGIC_OUTS_B3_1", - "CFG_CENTER_LOGIC_OUTS_B3_10", - "CFG_CENTER_LOGIC_OUTS_B3_11", - "CFG_CENTER_LOGIC_OUTS_B3_12", - "CFG_CENTER_LOGIC_OUTS_B3_13", - "CFG_CENTER_LOGIC_OUTS_B3_14", - "CFG_CENTER_LOGIC_OUTS_B3_15", - "CFG_CENTER_LOGIC_OUTS_B3_16", - "CFG_CENTER_LOGIC_OUTS_B3_17", - "CFG_CENTER_LOGIC_OUTS_B3_18", - "CFG_CENTER_LOGIC_OUTS_B3_19", - "CFG_CENTER_LOGIC_OUTS_B3_2", - "CFG_CENTER_LOGIC_OUTS_B3_3", - "CFG_CENTER_LOGIC_OUTS_B3_4", - "CFG_CENTER_LOGIC_OUTS_B3_5", - "CFG_CENTER_LOGIC_OUTS_B3_6", - "CFG_CENTER_LOGIC_OUTS_B3_7", - "CFG_CENTER_LOGIC_OUTS_B3_8", - "CFG_CENTER_LOGIC_OUTS_B3_9", - "CFG_CENTER_LOGIC_OUTS_B4_0", - "CFG_CENTER_LOGIC_OUTS_B4_1", - "CFG_CENTER_LOGIC_OUTS_B4_10", - "CFG_CENTER_LOGIC_OUTS_B4_11", - "CFG_CENTER_LOGIC_OUTS_B4_12", - "CFG_CENTER_LOGIC_OUTS_B4_13", - "CFG_CENTER_LOGIC_OUTS_B4_14", - "CFG_CENTER_LOGIC_OUTS_B4_15", - "CFG_CENTER_LOGIC_OUTS_B4_16", - "CFG_CENTER_LOGIC_OUTS_B4_17", - "CFG_CENTER_LOGIC_OUTS_B4_18", - "CFG_CENTER_LOGIC_OUTS_B4_19", - "CFG_CENTER_LOGIC_OUTS_B4_2", - "CFG_CENTER_LOGIC_OUTS_B4_3", - "CFG_CENTER_LOGIC_OUTS_B4_4", - "CFG_CENTER_LOGIC_OUTS_B4_5", - "CFG_CENTER_LOGIC_OUTS_B4_6", - "CFG_CENTER_LOGIC_OUTS_B4_7", - "CFG_CENTER_LOGIC_OUTS_B4_8", - "CFG_CENTER_LOGIC_OUTS_B4_9", - "CFG_CENTER_LOGIC_OUTS_B5_0", - "CFG_CENTER_LOGIC_OUTS_B5_1", - "CFG_CENTER_LOGIC_OUTS_B5_10", - "CFG_CENTER_LOGIC_OUTS_B5_11", - "CFG_CENTER_LOGIC_OUTS_B5_12", - "CFG_CENTER_LOGIC_OUTS_B5_13", - "CFG_CENTER_LOGIC_OUTS_B5_14", - "CFG_CENTER_LOGIC_OUTS_B5_15", - "CFG_CENTER_LOGIC_OUTS_B5_16", - "CFG_CENTER_LOGIC_OUTS_B5_17", - "CFG_CENTER_LOGIC_OUTS_B5_18", - "CFG_CENTER_LOGIC_OUTS_B5_19", - "CFG_CENTER_LOGIC_OUTS_B5_2", - "CFG_CENTER_LOGIC_OUTS_B5_3", - "CFG_CENTER_LOGIC_OUTS_B5_4", - "CFG_CENTER_LOGIC_OUTS_B5_5", - "CFG_CENTER_LOGIC_OUTS_B5_6", - "CFG_CENTER_LOGIC_OUTS_B5_7", - "CFG_CENTER_LOGIC_OUTS_B5_8", - "CFG_CENTER_LOGIC_OUTS_B5_9", - "CFG_CENTER_LOGIC_OUTS_B6_0", - "CFG_CENTER_LOGIC_OUTS_B6_1", - "CFG_CENTER_LOGIC_OUTS_B6_10", - "CFG_CENTER_LOGIC_OUTS_B6_11", - "CFG_CENTER_LOGIC_OUTS_B6_12", - "CFG_CENTER_LOGIC_OUTS_B6_13", - "CFG_CENTER_LOGIC_OUTS_B6_14", - "CFG_CENTER_LOGIC_OUTS_B6_15", - "CFG_CENTER_LOGIC_OUTS_B6_16", - "CFG_CENTER_LOGIC_OUTS_B6_17", - "CFG_CENTER_LOGIC_OUTS_B6_18", - "CFG_CENTER_LOGIC_OUTS_B6_19", - "CFG_CENTER_LOGIC_OUTS_B6_2", - "CFG_CENTER_LOGIC_OUTS_B6_3", - "CFG_CENTER_LOGIC_OUTS_B6_4", - "CFG_CENTER_LOGIC_OUTS_B6_5", - "CFG_CENTER_LOGIC_OUTS_B6_6", - "CFG_CENTER_LOGIC_OUTS_B6_7", - "CFG_CENTER_LOGIC_OUTS_B6_8", - "CFG_CENTER_LOGIC_OUTS_B6_9", - "CFG_CENTER_LOGIC_OUTS_B7_0", - "CFG_CENTER_LOGIC_OUTS_B7_1", - "CFG_CENTER_LOGIC_OUTS_B7_10", - "CFG_CENTER_LOGIC_OUTS_B7_11", - "CFG_CENTER_LOGIC_OUTS_B7_12", - "CFG_CENTER_LOGIC_OUTS_B7_13", - "CFG_CENTER_LOGIC_OUTS_B7_14", - "CFG_CENTER_LOGIC_OUTS_B7_15", - "CFG_CENTER_LOGIC_OUTS_B7_16", - "CFG_CENTER_LOGIC_OUTS_B7_17", - "CFG_CENTER_LOGIC_OUTS_B7_18", - "CFG_CENTER_LOGIC_OUTS_B7_19", - "CFG_CENTER_LOGIC_OUTS_B7_2", - "CFG_CENTER_LOGIC_OUTS_B7_3", - "CFG_CENTER_LOGIC_OUTS_B7_4", - "CFG_CENTER_LOGIC_OUTS_B7_5", - "CFG_CENTER_LOGIC_OUTS_B7_6", - "CFG_CENTER_LOGIC_OUTS_B7_7", - "CFG_CENTER_LOGIC_OUTS_B7_8", - "CFG_CENTER_LOGIC_OUTS_B7_9", - "CFG_CENTER_LOGIC_OUTS_B8_0", - "CFG_CENTER_LOGIC_OUTS_B8_1", - "CFG_CENTER_LOGIC_OUTS_B8_10", - "CFG_CENTER_LOGIC_OUTS_B8_11", - "CFG_CENTER_LOGIC_OUTS_B8_12", - "CFG_CENTER_LOGIC_OUTS_B8_13", - "CFG_CENTER_LOGIC_OUTS_B8_14", - "CFG_CENTER_LOGIC_OUTS_B8_15", - "CFG_CENTER_LOGIC_OUTS_B8_16", - "CFG_CENTER_LOGIC_OUTS_B8_17", - "CFG_CENTER_LOGIC_OUTS_B8_18", - "CFG_CENTER_LOGIC_OUTS_B8_19", - "CFG_CENTER_LOGIC_OUTS_B8_2", - "CFG_CENTER_LOGIC_OUTS_B8_3", - "CFG_CENTER_LOGIC_OUTS_B8_4", - "CFG_CENTER_LOGIC_OUTS_B8_5", - "CFG_CENTER_LOGIC_OUTS_B8_6", - "CFG_CENTER_LOGIC_OUTS_B8_7", - "CFG_CENTER_LOGIC_OUTS_B8_8", - "CFG_CENTER_LOGIC_OUTS_B8_9", - "CFG_CENTER_LOGIC_OUTS_B9_0", - "CFG_CENTER_LOGIC_OUTS_B9_1", - "CFG_CENTER_LOGIC_OUTS_B9_10", - "CFG_CENTER_LOGIC_OUTS_B9_11", - "CFG_CENTER_LOGIC_OUTS_B9_12", - "CFG_CENTER_LOGIC_OUTS_B9_13", - "CFG_CENTER_LOGIC_OUTS_B9_14", - "CFG_CENTER_LOGIC_OUTS_B9_15", - "CFG_CENTER_LOGIC_OUTS_B9_16", - "CFG_CENTER_LOGIC_OUTS_B9_17", - "CFG_CENTER_LOGIC_OUTS_B9_18", - "CFG_CENTER_LOGIC_OUTS_B9_19", - "CFG_CENTER_LOGIC_OUTS_B9_2", - "CFG_CENTER_LOGIC_OUTS_B9_3", - "CFG_CENTER_LOGIC_OUTS_B9_4", - "CFG_CENTER_LOGIC_OUTS_B9_5", - "CFG_CENTER_LOGIC_OUTS_B9_6", - "CFG_CENTER_LOGIC_OUTS_B9_7", - "CFG_CENTER_LOGIC_OUTS_B9_8", - "CFG_CENTER_LOGIC_OUTS_B9_9", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_MID_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_MID_CFG_IO_ACCESS_VGGCOMPOUT", - "CFG_CENTER_MID_DNA_PORT_CLK", - "CFG_CENTER_MID_ICAP1_CLK", - "CFG_CENTER_MID_USR_ACCESS_DATA10", - "CFG_CENTER_MID_USR_ACCESS_DATA11", - "CFG_CENTER_MID_USR_ACCESS_DATA12", - "CFG_CENTER_MID_USR_ACCESS_DATA13", - "CFG_CENTER_MID_USR_ACCESS_DATA14", - "CFG_CENTER_MID_USR_ACCESS_DATA2", - "CFG_CENTER_MID_USR_ACCESS_DATA3", - "CFG_CENTER_MID_USR_ACCESS_DATA4", - "CFG_CENTER_MID_USR_ACCESS_DATA5", - "CFG_CENTER_MID_USR_ACCESS_DATA6", - "CFG_CENTER_MID_USR_ACCESS_DATA7", - "CFG_CENTER_MID_USR_ACCESS_DATA8", - "CFG_CENTER_MID_USR_ACCESS_DATA9", - "CFG_CENTER_NE2A0_0", - "CFG_CENTER_NE2A0_1", - "CFG_CENTER_NE2A0_10", - "CFG_CENTER_NE2A0_11", - "CFG_CENTER_NE2A0_12", - "CFG_CENTER_NE2A0_13", - "CFG_CENTER_NE2A0_14", - "CFG_CENTER_NE2A0_15", - "CFG_CENTER_NE2A0_16", - "CFG_CENTER_NE2A0_17", - "CFG_CENTER_NE2A0_18", - "CFG_CENTER_NE2A0_19", - "CFG_CENTER_NE2A0_2", - "CFG_CENTER_NE2A0_3", - "CFG_CENTER_NE2A0_4", - "CFG_CENTER_NE2A0_5", - "CFG_CENTER_NE2A0_6", - "CFG_CENTER_NE2A0_7", - "CFG_CENTER_NE2A0_8", - "CFG_CENTER_NE2A0_9", - "CFG_CENTER_NE2A1_0", - "CFG_CENTER_NE2A1_1", - "CFG_CENTER_NE2A1_10", - "CFG_CENTER_NE2A1_11", - "CFG_CENTER_NE2A1_12", - "CFG_CENTER_NE2A1_13", - "CFG_CENTER_NE2A1_14", - "CFG_CENTER_NE2A1_15", - "CFG_CENTER_NE2A1_16", - "CFG_CENTER_NE2A1_17", - "CFG_CENTER_NE2A1_18", - "CFG_CENTER_NE2A1_19", - "CFG_CENTER_NE2A1_2", - "CFG_CENTER_NE2A1_3", - "CFG_CENTER_NE2A1_4", - "CFG_CENTER_NE2A1_5", - "CFG_CENTER_NE2A1_6", - "CFG_CENTER_NE2A1_7", - "CFG_CENTER_NE2A1_8", - "CFG_CENTER_NE2A1_9", - "CFG_CENTER_NE2A2_0", - "CFG_CENTER_NE2A2_1", - "CFG_CENTER_NE2A2_10", - "CFG_CENTER_NE2A2_11", - "CFG_CENTER_NE2A2_12", - "CFG_CENTER_NE2A2_13", - "CFG_CENTER_NE2A2_14", - "CFG_CENTER_NE2A2_15", - "CFG_CENTER_NE2A2_16", - "CFG_CENTER_NE2A2_17", - "CFG_CENTER_NE2A2_18", - "CFG_CENTER_NE2A2_19", - "CFG_CENTER_NE2A2_2", - "CFG_CENTER_NE2A2_3", - "CFG_CENTER_NE2A2_4", - "CFG_CENTER_NE2A2_5", - "CFG_CENTER_NE2A2_6", - "CFG_CENTER_NE2A2_7", - "CFG_CENTER_NE2A2_8", - "CFG_CENTER_NE2A2_9", - "CFG_CENTER_NE2A3_0", - "CFG_CENTER_NE2A3_1", - "CFG_CENTER_NE2A3_10", - "CFG_CENTER_NE2A3_11", - "CFG_CENTER_NE2A3_12", - "CFG_CENTER_NE2A3_13", - "CFG_CENTER_NE2A3_14", - "CFG_CENTER_NE2A3_15", - "CFG_CENTER_NE2A3_16", - "CFG_CENTER_NE2A3_17", - "CFG_CENTER_NE2A3_18", - "CFG_CENTER_NE2A3_19", - "CFG_CENTER_NE2A3_2", - "CFG_CENTER_NE2A3_3", - "CFG_CENTER_NE2A3_4", - "CFG_CENTER_NE2A3_5", - "CFG_CENTER_NE2A3_6", - "CFG_CENTER_NE2A3_7", - "CFG_CENTER_NE2A3_8", - "CFG_CENTER_NE2A3_9", - "CFG_CENTER_NE4BEG0_0", - "CFG_CENTER_NE4BEG0_1", - "CFG_CENTER_NE4BEG0_10", - "CFG_CENTER_NE4BEG0_11", - "CFG_CENTER_NE4BEG0_12", - "CFG_CENTER_NE4BEG0_13", - "CFG_CENTER_NE4BEG0_14", - "CFG_CENTER_NE4BEG0_15", - "CFG_CENTER_NE4BEG0_16", - "CFG_CENTER_NE4BEG0_17", - "CFG_CENTER_NE4BEG0_18", - "CFG_CENTER_NE4BEG0_19", - "CFG_CENTER_NE4BEG0_2", - "CFG_CENTER_NE4BEG0_3", - "CFG_CENTER_NE4BEG0_4", - "CFG_CENTER_NE4BEG0_5", - "CFG_CENTER_NE4BEG0_6", - "CFG_CENTER_NE4BEG0_7", - "CFG_CENTER_NE4BEG0_8", - "CFG_CENTER_NE4BEG0_9", - "CFG_CENTER_NE4BEG1_0", - "CFG_CENTER_NE4BEG1_1", - "CFG_CENTER_NE4BEG1_10", - "CFG_CENTER_NE4BEG1_11", - "CFG_CENTER_NE4BEG1_12", - "CFG_CENTER_NE4BEG1_13", - "CFG_CENTER_NE4BEG1_14", - "CFG_CENTER_NE4BEG1_15", - "CFG_CENTER_NE4BEG1_16", - "CFG_CENTER_NE4BEG1_17", - "CFG_CENTER_NE4BEG1_18", - "CFG_CENTER_NE4BEG1_19", - "CFG_CENTER_NE4BEG1_2", - "CFG_CENTER_NE4BEG1_3", - "CFG_CENTER_NE4BEG1_4", - "CFG_CENTER_NE4BEG1_5", - "CFG_CENTER_NE4BEG1_6", - "CFG_CENTER_NE4BEG1_7", - "CFG_CENTER_NE4BEG1_8", - "CFG_CENTER_NE4BEG1_9", - "CFG_CENTER_NE4BEG2_0", - "CFG_CENTER_NE4BEG2_1", - "CFG_CENTER_NE4BEG2_10", - "CFG_CENTER_NE4BEG2_11", - "CFG_CENTER_NE4BEG2_12", - "CFG_CENTER_NE4BEG2_13", - "CFG_CENTER_NE4BEG2_14", - "CFG_CENTER_NE4BEG2_15", - "CFG_CENTER_NE4BEG2_16", - "CFG_CENTER_NE4BEG2_17", - "CFG_CENTER_NE4BEG2_18", - "CFG_CENTER_NE4BEG2_19", - "CFG_CENTER_NE4BEG2_2", - "CFG_CENTER_NE4BEG2_3", - "CFG_CENTER_NE4BEG2_4", - "CFG_CENTER_NE4BEG2_5", - "CFG_CENTER_NE4BEG2_6", - "CFG_CENTER_NE4BEG2_7", - "CFG_CENTER_NE4BEG2_8", - "CFG_CENTER_NE4BEG2_9", - "CFG_CENTER_NE4BEG3_0", - "CFG_CENTER_NE4BEG3_1", - "CFG_CENTER_NE4BEG3_10", - "CFG_CENTER_NE4BEG3_11", - "CFG_CENTER_NE4BEG3_12", - "CFG_CENTER_NE4BEG3_13", - "CFG_CENTER_NE4BEG3_14", - "CFG_CENTER_NE4BEG3_15", - "CFG_CENTER_NE4BEG3_16", - "CFG_CENTER_NE4BEG3_17", - "CFG_CENTER_NE4BEG3_18", - "CFG_CENTER_NE4BEG3_19", - "CFG_CENTER_NE4BEG3_2", - "CFG_CENTER_NE4BEG3_3", - "CFG_CENTER_NE4BEG3_4", - "CFG_CENTER_NE4BEG3_5", - "CFG_CENTER_NE4BEG3_6", - "CFG_CENTER_NE4BEG3_7", - "CFG_CENTER_NE4BEG3_8", - "CFG_CENTER_NE4BEG3_9", - "CFG_CENTER_NE4C0_0", - "CFG_CENTER_NE4C0_1", - "CFG_CENTER_NE4C0_10", - "CFG_CENTER_NE4C0_11", - "CFG_CENTER_NE4C0_12", - "CFG_CENTER_NE4C0_13", - "CFG_CENTER_NE4C0_14", - "CFG_CENTER_NE4C0_15", - "CFG_CENTER_NE4C0_16", - "CFG_CENTER_NE4C0_17", - "CFG_CENTER_NE4C0_18", - "CFG_CENTER_NE4C0_19", - "CFG_CENTER_NE4C0_2", - "CFG_CENTER_NE4C0_3", - "CFG_CENTER_NE4C0_4", - "CFG_CENTER_NE4C0_5", - "CFG_CENTER_NE4C0_6", - "CFG_CENTER_NE4C0_7", - "CFG_CENTER_NE4C0_8", - "CFG_CENTER_NE4C0_9", - "CFG_CENTER_NE4C1_0", - "CFG_CENTER_NE4C1_1", - "CFG_CENTER_NE4C1_10", - "CFG_CENTER_NE4C1_11", - "CFG_CENTER_NE4C1_12", - "CFG_CENTER_NE4C1_13", - "CFG_CENTER_NE4C1_14", - "CFG_CENTER_NE4C1_15", - "CFG_CENTER_NE4C1_16", - "CFG_CENTER_NE4C1_17", - "CFG_CENTER_NE4C1_18", - "CFG_CENTER_NE4C1_19", - "CFG_CENTER_NE4C1_2", - "CFG_CENTER_NE4C1_3", - "CFG_CENTER_NE4C1_4", - "CFG_CENTER_NE4C1_5", - "CFG_CENTER_NE4C1_6", - "CFG_CENTER_NE4C1_7", - "CFG_CENTER_NE4C1_8", - "CFG_CENTER_NE4C1_9", - "CFG_CENTER_NE4C2_0", - "CFG_CENTER_NE4C2_1", - "CFG_CENTER_NE4C2_10", - "CFG_CENTER_NE4C2_11", - "CFG_CENTER_NE4C2_12", - "CFG_CENTER_NE4C2_13", - "CFG_CENTER_NE4C2_14", - "CFG_CENTER_NE4C2_15", - "CFG_CENTER_NE4C2_16", - "CFG_CENTER_NE4C2_17", - "CFG_CENTER_NE4C2_18", - "CFG_CENTER_NE4C2_19", - "CFG_CENTER_NE4C2_2", - "CFG_CENTER_NE4C2_3", - "CFG_CENTER_NE4C2_4", - "CFG_CENTER_NE4C2_5", - "CFG_CENTER_NE4C2_6", - "CFG_CENTER_NE4C2_7", - "CFG_CENTER_NE4C2_8", - "CFG_CENTER_NE4C2_9", - "CFG_CENTER_NE4C3_0", - "CFG_CENTER_NE4C3_1", - "CFG_CENTER_NE4C3_10", - "CFG_CENTER_NE4C3_11", - "CFG_CENTER_NE4C3_12", - "CFG_CENTER_NE4C3_13", - "CFG_CENTER_NE4C3_14", - "CFG_CENTER_NE4C3_15", - "CFG_CENTER_NE4C3_16", - "CFG_CENTER_NE4C3_17", - "CFG_CENTER_NE4C3_18", - "CFG_CENTER_NE4C3_19", - "CFG_CENTER_NE4C3_2", - "CFG_CENTER_NE4C3_3", - "CFG_CENTER_NE4C3_4", - "CFG_CENTER_NE4C3_5", - "CFG_CENTER_NE4C3_6", - "CFG_CENTER_NE4C3_7", - "CFG_CENTER_NE4C3_8", - "CFG_CENTER_NE4C3_9", - "CFG_CENTER_NW2A0_0", - "CFG_CENTER_NW2A0_1", - "CFG_CENTER_NW2A0_10", - "CFG_CENTER_NW2A0_11", - "CFG_CENTER_NW2A0_12", - "CFG_CENTER_NW2A0_13", - "CFG_CENTER_NW2A0_14", - "CFG_CENTER_NW2A0_15", - "CFG_CENTER_NW2A0_16", - "CFG_CENTER_NW2A0_17", - "CFG_CENTER_NW2A0_18", - "CFG_CENTER_NW2A0_19", - "CFG_CENTER_NW2A0_2", - "CFG_CENTER_NW2A0_3", - "CFG_CENTER_NW2A0_4", - "CFG_CENTER_NW2A0_5", - "CFG_CENTER_NW2A0_6", - "CFG_CENTER_NW2A0_7", - "CFG_CENTER_NW2A0_8", - "CFG_CENTER_NW2A0_9", - "CFG_CENTER_NW2A1_0", - "CFG_CENTER_NW2A1_1", - "CFG_CENTER_NW2A1_10", - "CFG_CENTER_NW2A1_11", - "CFG_CENTER_NW2A1_12", - "CFG_CENTER_NW2A1_13", - "CFG_CENTER_NW2A1_14", - "CFG_CENTER_NW2A1_15", - "CFG_CENTER_NW2A1_16", - "CFG_CENTER_NW2A1_17", - "CFG_CENTER_NW2A1_18", - "CFG_CENTER_NW2A1_19", - "CFG_CENTER_NW2A1_2", - "CFG_CENTER_NW2A1_3", - "CFG_CENTER_NW2A1_4", - "CFG_CENTER_NW2A1_5", - "CFG_CENTER_NW2A1_6", - "CFG_CENTER_NW2A1_7", - "CFG_CENTER_NW2A1_8", - "CFG_CENTER_NW2A1_9", - "CFG_CENTER_NW2A2_0", - "CFG_CENTER_NW2A2_1", - "CFG_CENTER_NW2A2_10", - "CFG_CENTER_NW2A2_11", - "CFG_CENTER_NW2A2_12", - "CFG_CENTER_NW2A2_13", - "CFG_CENTER_NW2A2_14", - "CFG_CENTER_NW2A2_15", - "CFG_CENTER_NW2A2_16", - "CFG_CENTER_NW2A2_17", - "CFG_CENTER_NW2A2_18", - "CFG_CENTER_NW2A2_19", - "CFG_CENTER_NW2A2_2", - "CFG_CENTER_NW2A2_3", - "CFG_CENTER_NW2A2_4", - "CFG_CENTER_NW2A2_5", - "CFG_CENTER_NW2A2_6", - "CFG_CENTER_NW2A2_7", - "CFG_CENTER_NW2A2_8", - "CFG_CENTER_NW2A2_9", - "CFG_CENTER_NW2A3_0", - "CFG_CENTER_NW2A3_1", - "CFG_CENTER_NW2A3_10", - "CFG_CENTER_NW2A3_11", - "CFG_CENTER_NW2A3_12", - "CFG_CENTER_NW2A3_13", - "CFG_CENTER_NW2A3_14", - "CFG_CENTER_NW2A3_15", - "CFG_CENTER_NW2A3_16", - "CFG_CENTER_NW2A3_17", - "CFG_CENTER_NW2A3_18", - "CFG_CENTER_NW2A3_19", - "CFG_CENTER_NW2A3_2", - "CFG_CENTER_NW2A3_3", - "CFG_CENTER_NW2A3_4", - "CFG_CENTER_NW2A3_5", - "CFG_CENTER_NW2A3_6", - "CFG_CENTER_NW2A3_7", - "CFG_CENTER_NW2A3_8", - "CFG_CENTER_NW2A3_9", - "CFG_CENTER_NW4A0_0", - "CFG_CENTER_NW4A0_1", - "CFG_CENTER_NW4A0_10", - "CFG_CENTER_NW4A0_11", - "CFG_CENTER_NW4A0_12", - "CFG_CENTER_NW4A0_13", - "CFG_CENTER_NW4A0_14", - "CFG_CENTER_NW4A0_15", - "CFG_CENTER_NW4A0_16", - "CFG_CENTER_NW4A0_17", - "CFG_CENTER_NW4A0_18", - "CFG_CENTER_NW4A0_19", - "CFG_CENTER_NW4A0_2", - "CFG_CENTER_NW4A0_3", - "CFG_CENTER_NW4A0_4", - "CFG_CENTER_NW4A0_5", - "CFG_CENTER_NW4A0_6", - "CFG_CENTER_NW4A0_7", - "CFG_CENTER_NW4A0_8", - "CFG_CENTER_NW4A0_9", - "CFG_CENTER_NW4A1_0", - "CFG_CENTER_NW4A1_1", - "CFG_CENTER_NW4A1_10", - "CFG_CENTER_NW4A1_11", - "CFG_CENTER_NW4A1_12", - "CFG_CENTER_NW4A1_13", - "CFG_CENTER_NW4A1_14", - "CFG_CENTER_NW4A1_15", - "CFG_CENTER_NW4A1_16", - "CFG_CENTER_NW4A1_17", - "CFG_CENTER_NW4A1_18", - "CFG_CENTER_NW4A1_19", - "CFG_CENTER_NW4A1_2", - "CFG_CENTER_NW4A1_3", - "CFG_CENTER_NW4A1_4", - "CFG_CENTER_NW4A1_5", - "CFG_CENTER_NW4A1_6", - "CFG_CENTER_NW4A1_7", - "CFG_CENTER_NW4A1_8", - "CFG_CENTER_NW4A1_9", - "CFG_CENTER_NW4A2_0", - "CFG_CENTER_NW4A2_1", - "CFG_CENTER_NW4A2_10", - "CFG_CENTER_NW4A2_11", - "CFG_CENTER_NW4A2_12", - "CFG_CENTER_NW4A2_13", - "CFG_CENTER_NW4A2_14", - "CFG_CENTER_NW4A2_15", - "CFG_CENTER_NW4A2_16", - "CFG_CENTER_NW4A2_17", - "CFG_CENTER_NW4A2_18", - "CFG_CENTER_NW4A2_19", - "CFG_CENTER_NW4A2_2", - "CFG_CENTER_NW4A2_3", - "CFG_CENTER_NW4A2_4", - "CFG_CENTER_NW4A2_5", - "CFG_CENTER_NW4A2_6", - "CFG_CENTER_NW4A2_7", - "CFG_CENTER_NW4A2_8", - "CFG_CENTER_NW4A2_9", - "CFG_CENTER_NW4A3_0", - "CFG_CENTER_NW4A3_1", - "CFG_CENTER_NW4A3_10", - "CFG_CENTER_NW4A3_11", - "CFG_CENTER_NW4A3_12", - "CFG_CENTER_NW4A3_13", - "CFG_CENTER_NW4A3_14", - "CFG_CENTER_NW4A3_15", - "CFG_CENTER_NW4A3_16", - "CFG_CENTER_NW4A3_17", - "CFG_CENTER_NW4A3_18", - "CFG_CENTER_NW4A3_19", - "CFG_CENTER_NW4A3_2", - "CFG_CENTER_NW4A3_3", - "CFG_CENTER_NW4A3_4", - "CFG_CENTER_NW4A3_5", - "CFG_CENTER_NW4A3_6", - "CFG_CENTER_NW4A3_7", - "CFG_CENTER_NW4A3_8", - "CFG_CENTER_NW4A3_9", - "CFG_CENTER_NW4END0_0", - "CFG_CENTER_NW4END0_1", - "CFG_CENTER_NW4END0_10", - "CFG_CENTER_NW4END0_11", - "CFG_CENTER_NW4END0_12", - "CFG_CENTER_NW4END0_13", - "CFG_CENTER_NW4END0_14", - "CFG_CENTER_NW4END0_15", - "CFG_CENTER_NW4END0_16", - "CFG_CENTER_NW4END0_17", - "CFG_CENTER_NW4END0_18", - "CFG_CENTER_NW4END0_19", - "CFG_CENTER_NW4END0_2", - "CFG_CENTER_NW4END0_3", - "CFG_CENTER_NW4END0_4", - "CFG_CENTER_NW4END0_5", - "CFG_CENTER_NW4END0_6", - "CFG_CENTER_NW4END0_7", - "CFG_CENTER_NW4END0_8", - "CFG_CENTER_NW4END0_9", - "CFG_CENTER_NW4END1_0", - "CFG_CENTER_NW4END1_1", - "CFG_CENTER_NW4END1_10", - "CFG_CENTER_NW4END1_11", - "CFG_CENTER_NW4END1_12", - "CFG_CENTER_NW4END1_13", - "CFG_CENTER_NW4END1_14", - "CFG_CENTER_NW4END1_15", - "CFG_CENTER_NW4END1_16", - "CFG_CENTER_NW4END1_17", - "CFG_CENTER_NW4END1_18", - "CFG_CENTER_NW4END1_19", - "CFG_CENTER_NW4END1_2", - "CFG_CENTER_NW4END1_3", - "CFG_CENTER_NW4END1_4", - "CFG_CENTER_NW4END1_5", - "CFG_CENTER_NW4END1_6", - "CFG_CENTER_NW4END1_7", - "CFG_CENTER_NW4END1_8", - "CFG_CENTER_NW4END1_9", - "CFG_CENTER_NW4END2_0", - "CFG_CENTER_NW4END2_1", - "CFG_CENTER_NW4END2_10", - "CFG_CENTER_NW4END2_11", - "CFG_CENTER_NW4END2_12", - "CFG_CENTER_NW4END2_13", - "CFG_CENTER_NW4END2_14", - "CFG_CENTER_NW4END2_15", - "CFG_CENTER_NW4END2_16", - "CFG_CENTER_NW4END2_17", - "CFG_CENTER_NW4END2_18", - "CFG_CENTER_NW4END2_19", - "CFG_CENTER_NW4END2_2", - "CFG_CENTER_NW4END2_3", - "CFG_CENTER_NW4END2_4", - "CFG_CENTER_NW4END2_5", - "CFG_CENTER_NW4END2_6", - "CFG_CENTER_NW4END2_7", - "CFG_CENTER_NW4END2_8", - "CFG_CENTER_NW4END2_9", - "CFG_CENTER_NW4END3_0", - "CFG_CENTER_NW4END3_1", - "CFG_CENTER_NW4END3_10", - "CFG_CENTER_NW4END3_11", - "CFG_CENTER_NW4END3_12", - "CFG_CENTER_NW4END3_13", - "CFG_CENTER_NW4END3_14", - "CFG_CENTER_NW4END3_15", - "CFG_CENTER_NW4END3_16", - "CFG_CENTER_NW4END3_17", - "CFG_CENTER_NW4END3_18", - "CFG_CENTER_NW4END3_19", - "CFG_CENTER_NW4END3_2", - "CFG_CENTER_NW4END3_3", - "CFG_CENTER_NW4END3_4", - "CFG_CENTER_NW4END3_5", - "CFG_CENTER_NW4END3_6", - "CFG_CENTER_NW4END3_7", - "CFG_CENTER_NW4END3_8", - "CFG_CENTER_NW4END3_9", - "CFG_CENTER_PMVIOB_A0", - "CFG_CENTER_PMVIOB_A1", - "CFG_CENTER_PMVIOB_EN", - "CFG_CENTER_PMVIOB_O", - "CFG_CENTER_PMVIOB_ODIV2", - "CFG_CENTER_PMVIOB_ODIV4", - "CFG_CENTER_SE2A0_0", - "CFG_CENTER_SE2A0_1", - "CFG_CENTER_SE2A0_10", - "CFG_CENTER_SE2A0_11", - "CFG_CENTER_SE2A0_12", - "CFG_CENTER_SE2A0_13", - "CFG_CENTER_SE2A0_14", - "CFG_CENTER_SE2A0_15", - "CFG_CENTER_SE2A0_16", - "CFG_CENTER_SE2A0_17", - "CFG_CENTER_SE2A0_18", - "CFG_CENTER_SE2A0_19", - "CFG_CENTER_SE2A0_2", - "CFG_CENTER_SE2A0_3", - "CFG_CENTER_SE2A0_4", - "CFG_CENTER_SE2A0_5", - "CFG_CENTER_SE2A0_6", - "CFG_CENTER_SE2A0_7", - "CFG_CENTER_SE2A0_8", - "CFG_CENTER_SE2A0_9", - "CFG_CENTER_SE2A1_0", - "CFG_CENTER_SE2A1_1", - "CFG_CENTER_SE2A1_10", - "CFG_CENTER_SE2A1_11", - "CFG_CENTER_SE2A1_12", - "CFG_CENTER_SE2A1_13", - "CFG_CENTER_SE2A1_14", - "CFG_CENTER_SE2A1_15", - "CFG_CENTER_SE2A1_16", - "CFG_CENTER_SE2A1_17", - "CFG_CENTER_SE2A1_18", - "CFG_CENTER_SE2A1_19", - "CFG_CENTER_SE2A1_2", - "CFG_CENTER_SE2A1_3", - "CFG_CENTER_SE2A1_4", - "CFG_CENTER_SE2A1_5", - "CFG_CENTER_SE2A1_6", - "CFG_CENTER_SE2A1_7", - "CFG_CENTER_SE2A1_8", - "CFG_CENTER_SE2A1_9", - "CFG_CENTER_SE2A2_0", - "CFG_CENTER_SE2A2_1", - "CFG_CENTER_SE2A2_10", - "CFG_CENTER_SE2A2_11", - "CFG_CENTER_SE2A2_12", - "CFG_CENTER_SE2A2_13", - "CFG_CENTER_SE2A2_14", - "CFG_CENTER_SE2A2_15", - "CFG_CENTER_SE2A2_16", - "CFG_CENTER_SE2A2_17", - "CFG_CENTER_SE2A2_18", - "CFG_CENTER_SE2A2_19", - "CFG_CENTER_SE2A2_2", - "CFG_CENTER_SE2A2_3", - "CFG_CENTER_SE2A2_4", - "CFG_CENTER_SE2A2_5", - "CFG_CENTER_SE2A2_6", - "CFG_CENTER_SE2A2_7", - "CFG_CENTER_SE2A2_8", - "CFG_CENTER_SE2A2_9", - "CFG_CENTER_SE2A3_0", - "CFG_CENTER_SE2A3_1", - "CFG_CENTER_SE2A3_10", - "CFG_CENTER_SE2A3_11", - "CFG_CENTER_SE2A3_12", - "CFG_CENTER_SE2A3_13", - "CFG_CENTER_SE2A3_14", - "CFG_CENTER_SE2A3_15", - "CFG_CENTER_SE2A3_16", - "CFG_CENTER_SE2A3_17", - "CFG_CENTER_SE2A3_18", - "CFG_CENTER_SE2A3_19", - "CFG_CENTER_SE2A3_2", - "CFG_CENTER_SE2A3_3", - "CFG_CENTER_SE2A3_4", - "CFG_CENTER_SE2A3_5", - "CFG_CENTER_SE2A3_6", - "CFG_CENTER_SE2A3_7", - "CFG_CENTER_SE2A3_8", - "CFG_CENTER_SE2A3_9", - "CFG_CENTER_SE4BEG0_0", - "CFG_CENTER_SE4BEG0_1", - "CFG_CENTER_SE4BEG0_10", - "CFG_CENTER_SE4BEG0_11", - "CFG_CENTER_SE4BEG0_12", - "CFG_CENTER_SE4BEG0_13", - "CFG_CENTER_SE4BEG0_14", - "CFG_CENTER_SE4BEG0_15", - "CFG_CENTER_SE4BEG0_16", - "CFG_CENTER_SE4BEG0_17", - "CFG_CENTER_SE4BEG0_18", - "CFG_CENTER_SE4BEG0_19", - "CFG_CENTER_SE4BEG0_2", - "CFG_CENTER_SE4BEG0_3", - "CFG_CENTER_SE4BEG0_4", - "CFG_CENTER_SE4BEG0_5", - "CFG_CENTER_SE4BEG0_6", - "CFG_CENTER_SE4BEG0_7", - "CFG_CENTER_SE4BEG0_8", - "CFG_CENTER_SE4BEG0_9", - "CFG_CENTER_SE4BEG1_0", - "CFG_CENTER_SE4BEG1_1", - "CFG_CENTER_SE4BEG1_10", - "CFG_CENTER_SE4BEG1_11", - "CFG_CENTER_SE4BEG1_12", - "CFG_CENTER_SE4BEG1_13", - "CFG_CENTER_SE4BEG1_14", - "CFG_CENTER_SE4BEG1_15", - "CFG_CENTER_SE4BEG1_16", - "CFG_CENTER_SE4BEG1_17", - "CFG_CENTER_SE4BEG1_18", - "CFG_CENTER_SE4BEG1_19", - "CFG_CENTER_SE4BEG1_2", - "CFG_CENTER_SE4BEG1_3", - "CFG_CENTER_SE4BEG1_4", - "CFG_CENTER_SE4BEG1_5", - "CFG_CENTER_SE4BEG1_6", - "CFG_CENTER_SE4BEG1_7", - "CFG_CENTER_SE4BEG1_8", - "CFG_CENTER_SE4BEG1_9", - "CFG_CENTER_SE4BEG2_0", - "CFG_CENTER_SE4BEG2_1", - "CFG_CENTER_SE4BEG2_10", - "CFG_CENTER_SE4BEG2_11", - "CFG_CENTER_SE4BEG2_12", - "CFG_CENTER_SE4BEG2_13", - "CFG_CENTER_SE4BEG2_14", - "CFG_CENTER_SE4BEG2_15", - "CFG_CENTER_SE4BEG2_16", - "CFG_CENTER_SE4BEG2_17", - "CFG_CENTER_SE4BEG2_18", - "CFG_CENTER_SE4BEG2_19", - "CFG_CENTER_SE4BEG2_2", - "CFG_CENTER_SE4BEG2_3", - "CFG_CENTER_SE4BEG2_4", - "CFG_CENTER_SE4BEG2_5", - "CFG_CENTER_SE4BEG2_6", - "CFG_CENTER_SE4BEG2_7", - "CFG_CENTER_SE4BEG2_8", - "CFG_CENTER_SE4BEG2_9", - "CFG_CENTER_SE4BEG3_0", - "CFG_CENTER_SE4BEG3_1", - "CFG_CENTER_SE4BEG3_10", - "CFG_CENTER_SE4BEG3_11", - "CFG_CENTER_SE4BEG3_12", - "CFG_CENTER_SE4BEG3_13", - "CFG_CENTER_SE4BEG3_14", - "CFG_CENTER_SE4BEG3_15", - "CFG_CENTER_SE4BEG3_16", - "CFG_CENTER_SE4BEG3_17", - "CFG_CENTER_SE4BEG3_18", - "CFG_CENTER_SE4BEG3_19", - "CFG_CENTER_SE4BEG3_2", - "CFG_CENTER_SE4BEG3_3", - "CFG_CENTER_SE4BEG3_4", - "CFG_CENTER_SE4BEG3_5", - "CFG_CENTER_SE4BEG3_6", - "CFG_CENTER_SE4BEG3_7", - "CFG_CENTER_SE4BEG3_8", - "CFG_CENTER_SE4BEG3_9", - "CFG_CENTER_SE4C0_0", - "CFG_CENTER_SE4C0_1", - "CFG_CENTER_SE4C0_10", - "CFG_CENTER_SE4C0_11", - "CFG_CENTER_SE4C0_12", - "CFG_CENTER_SE4C0_13", - "CFG_CENTER_SE4C0_14", - "CFG_CENTER_SE4C0_15", - "CFG_CENTER_SE4C0_16", - "CFG_CENTER_SE4C0_17", - "CFG_CENTER_SE4C0_18", - "CFG_CENTER_SE4C0_19", - "CFG_CENTER_SE4C0_2", - "CFG_CENTER_SE4C0_3", - "CFG_CENTER_SE4C0_4", - "CFG_CENTER_SE4C0_5", - "CFG_CENTER_SE4C0_6", - "CFG_CENTER_SE4C0_7", - "CFG_CENTER_SE4C0_8", - "CFG_CENTER_SE4C0_9", - "CFG_CENTER_SE4C1_0", - "CFG_CENTER_SE4C1_1", - "CFG_CENTER_SE4C1_10", - "CFG_CENTER_SE4C1_11", - "CFG_CENTER_SE4C1_12", - "CFG_CENTER_SE4C1_13", - "CFG_CENTER_SE4C1_14", - "CFG_CENTER_SE4C1_15", - "CFG_CENTER_SE4C1_16", - "CFG_CENTER_SE4C1_17", - "CFG_CENTER_SE4C1_18", - "CFG_CENTER_SE4C1_19", - "CFG_CENTER_SE4C1_2", - "CFG_CENTER_SE4C1_3", - "CFG_CENTER_SE4C1_4", - "CFG_CENTER_SE4C1_5", - "CFG_CENTER_SE4C1_6", - "CFG_CENTER_SE4C1_7", - "CFG_CENTER_SE4C1_8", - "CFG_CENTER_SE4C1_9", - "CFG_CENTER_SE4C2_0", - "CFG_CENTER_SE4C2_1", - "CFG_CENTER_SE4C2_10", - "CFG_CENTER_SE4C2_11", - "CFG_CENTER_SE4C2_12", - "CFG_CENTER_SE4C2_13", - "CFG_CENTER_SE4C2_14", - "CFG_CENTER_SE4C2_15", - "CFG_CENTER_SE4C2_16", - "CFG_CENTER_SE4C2_17", - "CFG_CENTER_SE4C2_18", - "CFG_CENTER_SE4C2_19", - "CFG_CENTER_SE4C2_2", - "CFG_CENTER_SE4C2_3", - "CFG_CENTER_SE4C2_4", - "CFG_CENTER_SE4C2_5", - "CFG_CENTER_SE4C2_6", - "CFG_CENTER_SE4C2_7", - "CFG_CENTER_SE4C2_8", - "CFG_CENTER_SE4C2_9", - "CFG_CENTER_SE4C3_0", - "CFG_CENTER_SE4C3_1", - "CFG_CENTER_SE4C3_10", - "CFG_CENTER_SE4C3_11", - "CFG_CENTER_SE4C3_12", - "CFG_CENTER_SE4C3_13", - "CFG_CENTER_SE4C3_14", - "CFG_CENTER_SE4C3_15", - "CFG_CENTER_SE4C3_16", - "CFG_CENTER_SE4C3_17", - "CFG_CENTER_SE4C3_18", - "CFG_CENTER_SE4C3_19", - "CFG_CENTER_SE4C3_2", - "CFG_CENTER_SE4C3_3", - "CFG_CENTER_SE4C3_4", - "CFG_CENTER_SE4C3_5", - "CFG_CENTER_SE4C3_6", - "CFG_CENTER_SE4C3_7", - "CFG_CENTER_SE4C3_8", - "CFG_CENTER_SE4C3_9", - "CFG_CENTER_STARTUP_CFGCLK", - "CFG_CENTER_STARTUP_CFGMCLK", - "CFG_CENTER_STARTUP_CLK", - "CFG_CENTER_STARTUP_EOS", - "CFG_CENTER_STARTUP_GSR", - "CFG_CENTER_STARTUP_GTS", - "CFG_CENTER_STARTUP_KEYCLEARB", - "CFG_CENTER_STARTUP_PACK", - "CFG_CENTER_STARTUP_PREQ", - "CFG_CENTER_STARTUP_USRCCLKO", - "CFG_CENTER_STARTUP_USRCCLKTS", - "CFG_CENTER_STARTUP_USRDONEO", - "CFG_CENTER_STARTUP_USRDONETS", - "CFG_CENTER_SW2A0_0", - "CFG_CENTER_SW2A0_1", - "CFG_CENTER_SW2A0_10", - "CFG_CENTER_SW2A0_11", - "CFG_CENTER_SW2A0_12", - "CFG_CENTER_SW2A0_13", - "CFG_CENTER_SW2A0_14", - "CFG_CENTER_SW2A0_15", - "CFG_CENTER_SW2A0_16", - "CFG_CENTER_SW2A0_17", - "CFG_CENTER_SW2A0_18", - "CFG_CENTER_SW2A0_19", - "CFG_CENTER_SW2A0_2", - "CFG_CENTER_SW2A0_3", - "CFG_CENTER_SW2A0_4", - "CFG_CENTER_SW2A0_5", - "CFG_CENTER_SW2A0_6", - "CFG_CENTER_SW2A0_7", - "CFG_CENTER_SW2A0_8", - "CFG_CENTER_SW2A0_9", - "CFG_CENTER_SW2A1_0", - "CFG_CENTER_SW2A1_1", - "CFG_CENTER_SW2A1_10", - "CFG_CENTER_SW2A1_11", - "CFG_CENTER_SW2A1_12", - "CFG_CENTER_SW2A1_13", - "CFG_CENTER_SW2A1_14", - "CFG_CENTER_SW2A1_15", - "CFG_CENTER_SW2A1_16", - "CFG_CENTER_SW2A1_17", - "CFG_CENTER_SW2A1_18", - "CFG_CENTER_SW2A1_19", - "CFG_CENTER_SW2A1_2", - "CFG_CENTER_SW2A1_3", - "CFG_CENTER_SW2A1_4", - "CFG_CENTER_SW2A1_5", - "CFG_CENTER_SW2A1_6", - "CFG_CENTER_SW2A1_7", - "CFG_CENTER_SW2A1_8", - "CFG_CENTER_SW2A1_9", - "CFG_CENTER_SW2A2_0", - "CFG_CENTER_SW2A2_1", - "CFG_CENTER_SW2A2_10", - "CFG_CENTER_SW2A2_11", - "CFG_CENTER_SW2A2_12", - "CFG_CENTER_SW2A2_13", - "CFG_CENTER_SW2A2_14", - "CFG_CENTER_SW2A2_15", - "CFG_CENTER_SW2A2_16", - "CFG_CENTER_SW2A2_17", - "CFG_CENTER_SW2A2_18", - "CFG_CENTER_SW2A2_19", - "CFG_CENTER_SW2A2_2", - "CFG_CENTER_SW2A2_3", - "CFG_CENTER_SW2A2_4", - "CFG_CENTER_SW2A2_5", - "CFG_CENTER_SW2A2_6", - "CFG_CENTER_SW2A2_7", - "CFG_CENTER_SW2A2_8", - "CFG_CENTER_SW2A2_9", - "CFG_CENTER_SW2A3_0", - "CFG_CENTER_SW2A3_1", - "CFG_CENTER_SW2A3_10", - "CFG_CENTER_SW2A3_11", - "CFG_CENTER_SW2A3_12", - "CFG_CENTER_SW2A3_13", - "CFG_CENTER_SW2A3_14", - "CFG_CENTER_SW2A3_15", - "CFG_CENTER_SW2A3_16", - "CFG_CENTER_SW2A3_17", - "CFG_CENTER_SW2A3_18", - "CFG_CENTER_SW2A3_19", - "CFG_CENTER_SW2A3_2", - "CFG_CENTER_SW2A3_3", - "CFG_CENTER_SW2A3_4", - "CFG_CENTER_SW2A3_5", - "CFG_CENTER_SW2A3_6", - "CFG_CENTER_SW2A3_7", - "CFG_CENTER_SW2A3_8", - "CFG_CENTER_SW2A3_9", - "CFG_CENTER_SW4A0_0", - "CFG_CENTER_SW4A0_1", - "CFG_CENTER_SW4A0_10", - "CFG_CENTER_SW4A0_11", - "CFG_CENTER_SW4A0_12", - "CFG_CENTER_SW4A0_13", - "CFG_CENTER_SW4A0_14", - "CFG_CENTER_SW4A0_15", - "CFG_CENTER_SW4A0_16", - "CFG_CENTER_SW4A0_17", - "CFG_CENTER_SW4A0_18", - "CFG_CENTER_SW4A0_19", - "CFG_CENTER_SW4A0_2", - "CFG_CENTER_SW4A0_3", - "CFG_CENTER_SW4A0_4", - "CFG_CENTER_SW4A0_5", - "CFG_CENTER_SW4A0_6", - "CFG_CENTER_SW4A0_7", - "CFG_CENTER_SW4A0_8", - "CFG_CENTER_SW4A0_9", - "CFG_CENTER_SW4A1_0", - "CFG_CENTER_SW4A1_1", - "CFG_CENTER_SW4A1_10", - "CFG_CENTER_SW4A1_11", - "CFG_CENTER_SW4A1_12", - "CFG_CENTER_SW4A1_13", - "CFG_CENTER_SW4A1_14", - "CFG_CENTER_SW4A1_15", - "CFG_CENTER_SW4A1_16", - "CFG_CENTER_SW4A1_17", - "CFG_CENTER_SW4A1_18", - "CFG_CENTER_SW4A1_19", - "CFG_CENTER_SW4A1_2", - "CFG_CENTER_SW4A1_3", - "CFG_CENTER_SW4A1_4", - "CFG_CENTER_SW4A1_5", - "CFG_CENTER_SW4A1_6", - "CFG_CENTER_SW4A1_7", - "CFG_CENTER_SW4A1_8", - "CFG_CENTER_SW4A1_9", - "CFG_CENTER_SW4A2_0", - "CFG_CENTER_SW4A2_1", - "CFG_CENTER_SW4A2_10", - "CFG_CENTER_SW4A2_11", - "CFG_CENTER_SW4A2_12", - "CFG_CENTER_SW4A2_13", - "CFG_CENTER_SW4A2_14", - "CFG_CENTER_SW4A2_15", - "CFG_CENTER_SW4A2_16", - "CFG_CENTER_SW4A2_17", - "CFG_CENTER_SW4A2_18", - "CFG_CENTER_SW4A2_19", - "CFG_CENTER_SW4A2_2", - "CFG_CENTER_SW4A2_3", - "CFG_CENTER_SW4A2_4", - "CFG_CENTER_SW4A2_5", - "CFG_CENTER_SW4A2_6", - "CFG_CENTER_SW4A2_7", - "CFG_CENTER_SW4A2_8", - "CFG_CENTER_SW4A2_9", - "CFG_CENTER_SW4A3_0", - "CFG_CENTER_SW4A3_1", - "CFG_CENTER_SW4A3_10", - "CFG_CENTER_SW4A3_11", - "CFG_CENTER_SW4A3_12", - "CFG_CENTER_SW4A3_13", - "CFG_CENTER_SW4A3_14", - "CFG_CENTER_SW4A3_15", - "CFG_CENTER_SW4A3_16", - "CFG_CENTER_SW4A3_17", - "CFG_CENTER_SW4A3_18", - "CFG_CENTER_SW4A3_19", - "CFG_CENTER_SW4A3_2", - "CFG_CENTER_SW4A3_3", - "CFG_CENTER_SW4A3_4", - "CFG_CENTER_SW4A3_5", - "CFG_CENTER_SW4A3_6", - "CFG_CENTER_SW4A3_7", - "CFG_CENTER_SW4A3_8", - "CFG_CENTER_SW4A3_9", - "CFG_CENTER_SW4END0_0", - "CFG_CENTER_SW4END0_1", - "CFG_CENTER_SW4END0_10", - "CFG_CENTER_SW4END0_11", - "CFG_CENTER_SW4END0_12", - "CFG_CENTER_SW4END0_13", - "CFG_CENTER_SW4END0_14", - "CFG_CENTER_SW4END0_15", - "CFG_CENTER_SW4END0_16", - "CFG_CENTER_SW4END0_17", - "CFG_CENTER_SW4END0_18", - "CFG_CENTER_SW4END0_19", - "CFG_CENTER_SW4END0_2", - "CFG_CENTER_SW4END0_3", - "CFG_CENTER_SW4END0_4", - "CFG_CENTER_SW4END0_5", - "CFG_CENTER_SW4END0_6", - "CFG_CENTER_SW4END0_7", - "CFG_CENTER_SW4END0_8", - "CFG_CENTER_SW4END0_9", - "CFG_CENTER_SW4END1_0", - "CFG_CENTER_SW4END1_1", - "CFG_CENTER_SW4END1_10", - "CFG_CENTER_SW4END1_11", - "CFG_CENTER_SW4END1_12", - "CFG_CENTER_SW4END1_13", - "CFG_CENTER_SW4END1_14", - "CFG_CENTER_SW4END1_15", - "CFG_CENTER_SW4END1_16", - "CFG_CENTER_SW4END1_17", - "CFG_CENTER_SW4END1_18", - "CFG_CENTER_SW4END1_19", - "CFG_CENTER_SW4END1_2", - "CFG_CENTER_SW4END1_3", - "CFG_CENTER_SW4END1_4", - "CFG_CENTER_SW4END1_5", - "CFG_CENTER_SW4END1_6", - "CFG_CENTER_SW4END1_7", - "CFG_CENTER_SW4END1_8", - "CFG_CENTER_SW4END1_9", - "CFG_CENTER_SW4END2_0", - "CFG_CENTER_SW4END2_1", - "CFG_CENTER_SW4END2_10", - "CFG_CENTER_SW4END2_11", - "CFG_CENTER_SW4END2_12", - "CFG_CENTER_SW4END2_13", - "CFG_CENTER_SW4END2_14", - "CFG_CENTER_SW4END2_15", - "CFG_CENTER_SW4END2_16", - "CFG_CENTER_SW4END2_17", - "CFG_CENTER_SW4END2_18", - "CFG_CENTER_SW4END2_19", - "CFG_CENTER_SW4END2_2", - "CFG_CENTER_SW4END2_3", - "CFG_CENTER_SW4END2_4", - "CFG_CENTER_SW4END2_5", - "CFG_CENTER_SW4END2_6", - "CFG_CENTER_SW4END2_7", - "CFG_CENTER_SW4END2_8", - "CFG_CENTER_SW4END2_9", - "CFG_CENTER_SW4END3_0", - "CFG_CENTER_SW4END3_1", - "CFG_CENTER_SW4END3_10", - "CFG_CENTER_SW4END3_11", - "CFG_CENTER_SW4END3_12", - "CFG_CENTER_SW4END3_13", - "CFG_CENTER_SW4END3_14", - "CFG_CENTER_SW4END3_15", - "CFG_CENTER_SW4END3_16", - "CFG_CENTER_SW4END3_17", - "CFG_CENTER_SW4END3_18", - "CFG_CENTER_SW4END3_19", - "CFG_CENTER_SW4END3_2", - "CFG_CENTER_SW4END3_3", - "CFG_CENTER_SW4END3_4", - "CFG_CENTER_SW4END3_5", - "CFG_CENTER_SW4END3_6", - "CFG_CENTER_SW4END3_7", - "CFG_CENTER_SW4END3_8", - "CFG_CENTER_SW4END3_9", - "CFG_CENTER_USR_ACCESS_CFGCLK", - "CFG_CENTER_USR_ACCESS_DATA0", - "CFG_CENTER_USR_ACCESS_DATA1", - "CFG_CENTER_USR_ACCESS_DATA10", - "CFG_CENTER_USR_ACCESS_DATA11", - "CFG_CENTER_USR_ACCESS_DATA12", - "CFG_CENTER_USR_ACCESS_DATA13", - "CFG_CENTER_USR_ACCESS_DATA14", - "CFG_CENTER_USR_ACCESS_DATA15", - "CFG_CENTER_USR_ACCESS_DATA16", - "CFG_CENTER_USR_ACCESS_DATA17", - "CFG_CENTER_USR_ACCESS_DATA18", - "CFG_CENTER_USR_ACCESS_DATA19", - "CFG_CENTER_USR_ACCESS_DATA2", - "CFG_CENTER_USR_ACCESS_DATA20", - "CFG_CENTER_USR_ACCESS_DATA21", - "CFG_CENTER_USR_ACCESS_DATA22", - "CFG_CENTER_USR_ACCESS_DATA23", - "CFG_CENTER_USR_ACCESS_DATA24", - "CFG_CENTER_USR_ACCESS_DATA25", - "CFG_CENTER_USR_ACCESS_DATA26", - "CFG_CENTER_USR_ACCESS_DATA27", - "CFG_CENTER_USR_ACCESS_DATA28", - "CFG_CENTER_USR_ACCESS_DATA29", - "CFG_CENTER_USR_ACCESS_DATA3", - "CFG_CENTER_USR_ACCESS_DATA30", - "CFG_CENTER_USR_ACCESS_DATA31", - "CFG_CENTER_USR_ACCESS_DATA4", - "CFG_CENTER_USR_ACCESS_DATA5", - "CFG_CENTER_USR_ACCESS_DATA6", - "CFG_CENTER_USR_ACCESS_DATA7", - "CFG_CENTER_USR_ACCESS_DATA8", - "CFG_CENTER_USR_ACCESS_DATA9", - "CFG_CENTER_USR_ACCESS_DATAVALID", - "CFG_CENTER_WL1END0_0", - "CFG_CENTER_WL1END0_1", - "CFG_CENTER_WL1END0_10", - "CFG_CENTER_WL1END0_11", - "CFG_CENTER_WL1END0_12", - "CFG_CENTER_WL1END0_13", - "CFG_CENTER_WL1END0_14", - "CFG_CENTER_WL1END0_15", - "CFG_CENTER_WL1END0_16", - "CFG_CENTER_WL1END0_17", - "CFG_CENTER_WL1END0_18", - "CFG_CENTER_WL1END0_19", - "CFG_CENTER_WL1END0_2", - "CFG_CENTER_WL1END0_3", - "CFG_CENTER_WL1END0_4", - "CFG_CENTER_WL1END0_5", - "CFG_CENTER_WL1END0_6", - "CFG_CENTER_WL1END0_7", - "CFG_CENTER_WL1END0_8", - "CFG_CENTER_WL1END0_9", - "CFG_CENTER_WL1END1_0", - "CFG_CENTER_WL1END1_1", - "CFG_CENTER_WL1END1_10", - "CFG_CENTER_WL1END1_11", - "CFG_CENTER_WL1END1_12", - "CFG_CENTER_WL1END1_13", - "CFG_CENTER_WL1END1_14", - "CFG_CENTER_WL1END1_15", - "CFG_CENTER_WL1END1_16", - "CFG_CENTER_WL1END1_17", - "CFG_CENTER_WL1END1_18", - "CFG_CENTER_WL1END1_19", - "CFG_CENTER_WL1END1_2", - "CFG_CENTER_WL1END1_3", - "CFG_CENTER_WL1END1_4", - "CFG_CENTER_WL1END1_5", - "CFG_CENTER_WL1END1_6", - "CFG_CENTER_WL1END1_7", - "CFG_CENTER_WL1END1_8", - "CFG_CENTER_WL1END1_9", - "CFG_CENTER_WL1END2_0", - "CFG_CENTER_WL1END2_1", - "CFG_CENTER_WL1END2_10", - "CFG_CENTER_WL1END2_11", - "CFG_CENTER_WL1END2_12", - "CFG_CENTER_WL1END2_13", - "CFG_CENTER_WL1END2_14", - "CFG_CENTER_WL1END2_15", - "CFG_CENTER_WL1END2_16", - "CFG_CENTER_WL1END2_17", - "CFG_CENTER_WL1END2_18", - "CFG_CENTER_WL1END2_19", - "CFG_CENTER_WL1END2_2", - "CFG_CENTER_WL1END2_3", - "CFG_CENTER_WL1END2_4", - "CFG_CENTER_WL1END2_5", - "CFG_CENTER_WL1END2_6", - "CFG_CENTER_WL1END2_7", - "CFG_CENTER_WL1END2_8", - "CFG_CENTER_WL1END2_9", - "CFG_CENTER_WL1END3_0", - "CFG_CENTER_WL1END3_1", - "CFG_CENTER_WL1END3_10", - "CFG_CENTER_WL1END3_11", - "CFG_CENTER_WL1END3_12", - "CFG_CENTER_WL1END3_13", - "CFG_CENTER_WL1END3_14", - "CFG_CENTER_WL1END3_15", - "CFG_CENTER_WL1END3_16", - "CFG_CENTER_WL1END3_17", - "CFG_CENTER_WL1END3_18", - "CFG_CENTER_WL1END3_19", - "CFG_CENTER_WL1END3_2", - "CFG_CENTER_WL1END3_3", - "CFG_CENTER_WL1END3_4", - "CFG_CENTER_WL1END3_5", - "CFG_CENTER_WL1END3_6", - "CFG_CENTER_WL1END3_7", - "CFG_CENTER_WL1END3_8", - "CFG_CENTER_WL1END3_9", - "CFG_CENTER_WR1END0_0", - "CFG_CENTER_WR1END0_1", - "CFG_CENTER_WR1END0_10", - "CFG_CENTER_WR1END0_11", - "CFG_CENTER_WR1END0_12", - "CFG_CENTER_WR1END0_13", - "CFG_CENTER_WR1END0_14", - "CFG_CENTER_WR1END0_15", - "CFG_CENTER_WR1END0_16", - "CFG_CENTER_WR1END0_17", - "CFG_CENTER_WR1END0_18", - "CFG_CENTER_WR1END0_19", - "CFG_CENTER_WR1END0_2", - "CFG_CENTER_WR1END0_3", - "CFG_CENTER_WR1END0_4", - "CFG_CENTER_WR1END0_5", - "CFG_CENTER_WR1END0_6", - "CFG_CENTER_WR1END0_7", - "CFG_CENTER_WR1END0_8", - "CFG_CENTER_WR1END0_9", - "CFG_CENTER_WR1END1_0", - "CFG_CENTER_WR1END1_1", - "CFG_CENTER_WR1END1_10", - "CFG_CENTER_WR1END1_11", - "CFG_CENTER_WR1END1_12", - "CFG_CENTER_WR1END1_13", - "CFG_CENTER_WR1END1_14", - "CFG_CENTER_WR1END1_15", - "CFG_CENTER_WR1END1_16", - "CFG_CENTER_WR1END1_17", - "CFG_CENTER_WR1END1_18", - "CFG_CENTER_WR1END1_19", - "CFG_CENTER_WR1END1_2", - "CFG_CENTER_WR1END1_3", - "CFG_CENTER_WR1END1_4", - "CFG_CENTER_WR1END1_5", - "CFG_CENTER_WR1END1_6", - "CFG_CENTER_WR1END1_7", - "CFG_CENTER_WR1END1_8", - "CFG_CENTER_WR1END1_9", - "CFG_CENTER_WR1END2_0", - "CFG_CENTER_WR1END2_1", - "CFG_CENTER_WR1END2_10", - "CFG_CENTER_WR1END2_11", - "CFG_CENTER_WR1END2_12", - "CFG_CENTER_WR1END2_13", - "CFG_CENTER_WR1END2_14", - "CFG_CENTER_WR1END2_15", - "CFG_CENTER_WR1END2_16", - "CFG_CENTER_WR1END2_17", - "CFG_CENTER_WR1END2_18", - "CFG_CENTER_WR1END2_19", - "CFG_CENTER_WR1END2_2", - "CFG_CENTER_WR1END2_3", - "CFG_CENTER_WR1END2_4", - "CFG_CENTER_WR1END2_5", - "CFG_CENTER_WR1END2_6", - "CFG_CENTER_WR1END2_7", - "CFG_CENTER_WR1END2_8", - "CFG_CENTER_WR1END2_9", - "CFG_CENTER_WR1END3_0", - "CFG_CENTER_WR1END3_1", - "CFG_CENTER_WR1END3_10", - "CFG_CENTER_WR1END3_11", - "CFG_CENTER_WR1END3_12", - "CFG_CENTER_WR1END3_13", - "CFG_CENTER_WR1END3_14", - "CFG_CENTER_WR1END3_15", - "CFG_CENTER_WR1END3_16", - "CFG_CENTER_WR1END3_17", - "CFG_CENTER_WR1END3_18", - "CFG_CENTER_WR1END3_19", - "CFG_CENTER_WR1END3_2", - "CFG_CENTER_WR1END3_3", - "CFG_CENTER_WR1END3_4", - "CFG_CENTER_WR1END3_5", - "CFG_CENTER_WR1END3_6", - "CFG_CENTER_WR1END3_7", - "CFG_CENTER_WR1END3_8", - "CFG_CENTER_WR1END3_9", - "CFG_CENTER_WW2A0_0", - "CFG_CENTER_WW2A0_1", - "CFG_CENTER_WW2A0_10", - "CFG_CENTER_WW2A0_11", - "CFG_CENTER_WW2A0_12", - "CFG_CENTER_WW2A0_13", - "CFG_CENTER_WW2A0_14", - "CFG_CENTER_WW2A0_15", - "CFG_CENTER_WW2A0_16", - "CFG_CENTER_WW2A0_17", - "CFG_CENTER_WW2A0_18", - "CFG_CENTER_WW2A0_19", - "CFG_CENTER_WW2A0_2", - "CFG_CENTER_WW2A0_3", - "CFG_CENTER_WW2A0_4", - "CFG_CENTER_WW2A0_5", - "CFG_CENTER_WW2A0_6", - "CFG_CENTER_WW2A0_7", - "CFG_CENTER_WW2A0_8", - "CFG_CENTER_WW2A0_9", - "CFG_CENTER_WW2A1_0", - "CFG_CENTER_WW2A1_1", - "CFG_CENTER_WW2A1_10", - "CFG_CENTER_WW2A1_11", - "CFG_CENTER_WW2A1_12", - "CFG_CENTER_WW2A1_13", - "CFG_CENTER_WW2A1_14", - "CFG_CENTER_WW2A1_15", - "CFG_CENTER_WW2A1_16", - "CFG_CENTER_WW2A1_17", - "CFG_CENTER_WW2A1_18", - "CFG_CENTER_WW2A1_19", - "CFG_CENTER_WW2A1_2", - "CFG_CENTER_WW2A1_3", - "CFG_CENTER_WW2A1_4", - "CFG_CENTER_WW2A1_5", - "CFG_CENTER_WW2A1_6", - "CFG_CENTER_WW2A1_7", - "CFG_CENTER_WW2A1_8", - "CFG_CENTER_WW2A1_9", - "CFG_CENTER_WW2A2_0", - "CFG_CENTER_WW2A2_1", - "CFG_CENTER_WW2A2_10", - "CFG_CENTER_WW2A2_11", - "CFG_CENTER_WW2A2_12", - "CFG_CENTER_WW2A2_13", - "CFG_CENTER_WW2A2_14", - "CFG_CENTER_WW2A2_15", - "CFG_CENTER_WW2A2_16", - "CFG_CENTER_WW2A2_17", - "CFG_CENTER_WW2A2_18", - "CFG_CENTER_WW2A2_19", - "CFG_CENTER_WW2A2_2", - "CFG_CENTER_WW2A2_3", - "CFG_CENTER_WW2A2_4", - "CFG_CENTER_WW2A2_5", - "CFG_CENTER_WW2A2_6", - "CFG_CENTER_WW2A2_7", - "CFG_CENTER_WW2A2_8", - "CFG_CENTER_WW2A2_9", - "CFG_CENTER_WW2A3_0", - "CFG_CENTER_WW2A3_1", - "CFG_CENTER_WW2A3_10", - "CFG_CENTER_WW2A3_11", - "CFG_CENTER_WW2A3_12", - "CFG_CENTER_WW2A3_13", - "CFG_CENTER_WW2A3_14", - "CFG_CENTER_WW2A3_15", - "CFG_CENTER_WW2A3_16", - "CFG_CENTER_WW2A3_17", - "CFG_CENTER_WW2A3_18", - "CFG_CENTER_WW2A3_19", - "CFG_CENTER_WW2A3_2", - "CFG_CENTER_WW2A3_3", - "CFG_CENTER_WW2A3_4", - "CFG_CENTER_WW2A3_5", - "CFG_CENTER_WW2A3_6", - "CFG_CENTER_WW2A3_7", - "CFG_CENTER_WW2A3_8", - "CFG_CENTER_WW2A3_9", - "CFG_CENTER_WW2END0_0", - "CFG_CENTER_WW2END0_1", - "CFG_CENTER_WW2END0_10", - "CFG_CENTER_WW2END0_11", - "CFG_CENTER_WW2END0_12", - "CFG_CENTER_WW2END0_13", - "CFG_CENTER_WW2END0_14", - "CFG_CENTER_WW2END0_15", - "CFG_CENTER_WW2END0_16", - "CFG_CENTER_WW2END0_17", - "CFG_CENTER_WW2END0_18", - "CFG_CENTER_WW2END0_19", - "CFG_CENTER_WW2END0_2", - "CFG_CENTER_WW2END0_3", - "CFG_CENTER_WW2END0_4", - "CFG_CENTER_WW2END0_5", - "CFG_CENTER_WW2END0_6", - "CFG_CENTER_WW2END0_7", - "CFG_CENTER_WW2END0_8", - "CFG_CENTER_WW2END0_9", - "CFG_CENTER_WW2END1_0", - "CFG_CENTER_WW2END1_1", - "CFG_CENTER_WW2END1_10", - "CFG_CENTER_WW2END1_11", - "CFG_CENTER_WW2END1_12", - "CFG_CENTER_WW2END1_13", - "CFG_CENTER_WW2END1_14", - "CFG_CENTER_WW2END1_15", - "CFG_CENTER_WW2END1_16", - "CFG_CENTER_WW2END1_17", - "CFG_CENTER_WW2END1_18", - "CFG_CENTER_WW2END1_19", - "CFG_CENTER_WW2END1_2", - "CFG_CENTER_WW2END1_3", - "CFG_CENTER_WW2END1_4", - "CFG_CENTER_WW2END1_5", - "CFG_CENTER_WW2END1_6", - "CFG_CENTER_WW2END1_7", - "CFG_CENTER_WW2END1_8", - "CFG_CENTER_WW2END1_9", - "CFG_CENTER_WW2END2_0", - "CFG_CENTER_WW2END2_1", - "CFG_CENTER_WW2END2_10", - "CFG_CENTER_WW2END2_11", - "CFG_CENTER_WW2END2_12", - "CFG_CENTER_WW2END2_13", - "CFG_CENTER_WW2END2_14", - "CFG_CENTER_WW2END2_15", - "CFG_CENTER_WW2END2_16", - "CFG_CENTER_WW2END2_17", - "CFG_CENTER_WW2END2_18", - "CFG_CENTER_WW2END2_19", - "CFG_CENTER_WW2END2_2", - "CFG_CENTER_WW2END2_3", - "CFG_CENTER_WW2END2_4", - "CFG_CENTER_WW2END2_5", - "CFG_CENTER_WW2END2_6", - "CFG_CENTER_WW2END2_7", - "CFG_CENTER_WW2END2_8", - "CFG_CENTER_WW2END2_9", - "CFG_CENTER_WW2END3_0", - "CFG_CENTER_WW2END3_1", - "CFG_CENTER_WW2END3_10", - "CFG_CENTER_WW2END3_11", - "CFG_CENTER_WW2END3_12", - "CFG_CENTER_WW2END3_13", - "CFG_CENTER_WW2END3_14", - "CFG_CENTER_WW2END3_15", - "CFG_CENTER_WW2END3_16", - "CFG_CENTER_WW2END3_17", - "CFG_CENTER_WW2END3_18", - "CFG_CENTER_WW2END3_19", - "CFG_CENTER_WW2END3_2", - "CFG_CENTER_WW2END3_3", - "CFG_CENTER_WW2END3_4", - "CFG_CENTER_WW2END3_5", - "CFG_CENTER_WW2END3_6", - "CFG_CENTER_WW2END3_7", - "CFG_CENTER_WW2END3_8", - "CFG_CENTER_WW2END3_9", - "CFG_CENTER_WW4A0_0", - "CFG_CENTER_WW4A0_1", - "CFG_CENTER_WW4A0_10", - "CFG_CENTER_WW4A0_11", - "CFG_CENTER_WW4A0_12", - "CFG_CENTER_WW4A0_13", - "CFG_CENTER_WW4A0_14", - "CFG_CENTER_WW4A0_15", - "CFG_CENTER_WW4A0_16", - "CFG_CENTER_WW4A0_17", - "CFG_CENTER_WW4A0_18", - "CFG_CENTER_WW4A0_19", - "CFG_CENTER_WW4A0_2", - "CFG_CENTER_WW4A0_3", - "CFG_CENTER_WW4A0_4", - "CFG_CENTER_WW4A0_5", - "CFG_CENTER_WW4A0_6", - "CFG_CENTER_WW4A0_7", - "CFG_CENTER_WW4A0_8", - "CFG_CENTER_WW4A0_9", - "CFG_CENTER_WW4A1_0", - "CFG_CENTER_WW4A1_1", - "CFG_CENTER_WW4A1_10", - "CFG_CENTER_WW4A1_11", - "CFG_CENTER_WW4A1_12", - "CFG_CENTER_WW4A1_13", - "CFG_CENTER_WW4A1_14", - "CFG_CENTER_WW4A1_15", - "CFG_CENTER_WW4A1_16", - "CFG_CENTER_WW4A1_17", - "CFG_CENTER_WW4A1_18", - "CFG_CENTER_WW4A1_19", - "CFG_CENTER_WW4A1_2", - "CFG_CENTER_WW4A1_3", - "CFG_CENTER_WW4A1_4", - "CFG_CENTER_WW4A1_5", - "CFG_CENTER_WW4A1_6", - "CFG_CENTER_WW4A1_7", - "CFG_CENTER_WW4A1_8", - "CFG_CENTER_WW4A1_9", - "CFG_CENTER_WW4A2_0", - "CFG_CENTER_WW4A2_1", - "CFG_CENTER_WW4A2_10", - "CFG_CENTER_WW4A2_11", - "CFG_CENTER_WW4A2_12", - "CFG_CENTER_WW4A2_13", - "CFG_CENTER_WW4A2_14", - "CFG_CENTER_WW4A2_15", - "CFG_CENTER_WW4A2_16", - "CFG_CENTER_WW4A2_17", - "CFG_CENTER_WW4A2_18", - "CFG_CENTER_WW4A2_19", - "CFG_CENTER_WW4A2_2", - "CFG_CENTER_WW4A2_3", - "CFG_CENTER_WW4A2_4", - "CFG_CENTER_WW4A2_5", - "CFG_CENTER_WW4A2_6", - "CFG_CENTER_WW4A2_7", - "CFG_CENTER_WW4A2_8", - "CFG_CENTER_WW4A2_9", - "CFG_CENTER_WW4A3_0", - "CFG_CENTER_WW4A3_1", - "CFG_CENTER_WW4A3_10", - "CFG_CENTER_WW4A3_11", - "CFG_CENTER_WW4A3_12", - "CFG_CENTER_WW4A3_13", - "CFG_CENTER_WW4A3_14", - "CFG_CENTER_WW4A3_15", - "CFG_CENTER_WW4A3_16", - "CFG_CENTER_WW4A3_17", - "CFG_CENTER_WW4A3_18", - "CFG_CENTER_WW4A3_19", - "CFG_CENTER_WW4A3_2", - "CFG_CENTER_WW4A3_3", - "CFG_CENTER_WW4A3_4", - "CFG_CENTER_WW4A3_5", - "CFG_CENTER_WW4A3_6", - "CFG_CENTER_WW4A3_7", - "CFG_CENTER_WW4A3_8", - "CFG_CENTER_WW4A3_9", - "CFG_CENTER_WW4B0_0", - "CFG_CENTER_WW4B0_1", - "CFG_CENTER_WW4B0_10", - "CFG_CENTER_WW4B0_11", - "CFG_CENTER_WW4B0_12", - "CFG_CENTER_WW4B0_13", - "CFG_CENTER_WW4B0_14", - "CFG_CENTER_WW4B0_15", - "CFG_CENTER_WW4B0_16", - "CFG_CENTER_WW4B0_17", - "CFG_CENTER_WW4B0_18", - "CFG_CENTER_WW4B0_19", - "CFG_CENTER_WW4B0_2", - "CFG_CENTER_WW4B0_3", - "CFG_CENTER_WW4B0_4", - "CFG_CENTER_WW4B0_5", - "CFG_CENTER_WW4B0_6", - "CFG_CENTER_WW4B0_7", - "CFG_CENTER_WW4B0_8", - "CFG_CENTER_WW4B0_9", - "CFG_CENTER_WW4B1_0", - "CFG_CENTER_WW4B1_1", - "CFG_CENTER_WW4B1_10", - "CFG_CENTER_WW4B1_11", - "CFG_CENTER_WW4B1_12", - "CFG_CENTER_WW4B1_13", - "CFG_CENTER_WW4B1_14", - "CFG_CENTER_WW4B1_15", - "CFG_CENTER_WW4B1_16", - "CFG_CENTER_WW4B1_17", - "CFG_CENTER_WW4B1_18", - "CFG_CENTER_WW4B1_19", - "CFG_CENTER_WW4B1_2", - "CFG_CENTER_WW4B1_3", - "CFG_CENTER_WW4B1_4", - "CFG_CENTER_WW4B1_5", - "CFG_CENTER_WW4B1_6", - "CFG_CENTER_WW4B1_7", - "CFG_CENTER_WW4B1_8", - "CFG_CENTER_WW4B1_9", - "CFG_CENTER_WW4B2_0", - "CFG_CENTER_WW4B2_1", - "CFG_CENTER_WW4B2_10", - "CFG_CENTER_WW4B2_11", - "CFG_CENTER_WW4B2_12", - "CFG_CENTER_WW4B2_13", - "CFG_CENTER_WW4B2_14", - "CFG_CENTER_WW4B2_15", - "CFG_CENTER_WW4B2_16", - "CFG_CENTER_WW4B2_17", - "CFG_CENTER_WW4B2_18", - "CFG_CENTER_WW4B2_19", - "CFG_CENTER_WW4B2_2", - "CFG_CENTER_WW4B2_3", - "CFG_CENTER_WW4B2_4", - "CFG_CENTER_WW4B2_5", - "CFG_CENTER_WW4B2_6", - "CFG_CENTER_WW4B2_7", - "CFG_CENTER_WW4B2_8", - "CFG_CENTER_WW4B2_9", - "CFG_CENTER_WW4B3_0", - "CFG_CENTER_WW4B3_1", - "CFG_CENTER_WW4B3_10", - "CFG_CENTER_WW4B3_11", - "CFG_CENTER_WW4B3_12", - "CFG_CENTER_WW4B3_13", - "CFG_CENTER_WW4B3_14", - "CFG_CENTER_WW4B3_15", - "CFG_CENTER_WW4B3_16", - "CFG_CENTER_WW4B3_17", - "CFG_CENTER_WW4B3_18", - "CFG_CENTER_WW4B3_19", - "CFG_CENTER_WW4B3_2", - "CFG_CENTER_WW4B3_3", - "CFG_CENTER_WW4B3_4", - "CFG_CENTER_WW4B3_5", - "CFG_CENTER_WW4B3_6", - "CFG_CENTER_WW4B3_7", - "CFG_CENTER_WW4B3_8", - "CFG_CENTER_WW4B3_9", - "CFG_CENTER_WW4C0_0", - "CFG_CENTER_WW4C0_1", - "CFG_CENTER_WW4C0_10", - "CFG_CENTER_WW4C0_11", - "CFG_CENTER_WW4C0_12", - "CFG_CENTER_WW4C0_13", - "CFG_CENTER_WW4C0_14", - "CFG_CENTER_WW4C0_15", - "CFG_CENTER_WW4C0_16", - "CFG_CENTER_WW4C0_17", - "CFG_CENTER_WW4C0_18", - "CFG_CENTER_WW4C0_19", - "CFG_CENTER_WW4C0_2", - "CFG_CENTER_WW4C0_3", - "CFG_CENTER_WW4C0_4", - "CFG_CENTER_WW4C0_5", - "CFG_CENTER_WW4C0_6", - "CFG_CENTER_WW4C0_7", - "CFG_CENTER_WW4C0_8", - "CFG_CENTER_WW4C0_9", - "CFG_CENTER_WW4C1_0", - "CFG_CENTER_WW4C1_1", - "CFG_CENTER_WW4C1_10", - "CFG_CENTER_WW4C1_11", - "CFG_CENTER_WW4C1_12", - "CFG_CENTER_WW4C1_13", - "CFG_CENTER_WW4C1_14", - "CFG_CENTER_WW4C1_15", - "CFG_CENTER_WW4C1_16", - "CFG_CENTER_WW4C1_17", - "CFG_CENTER_WW4C1_18", - "CFG_CENTER_WW4C1_19", - "CFG_CENTER_WW4C1_2", - "CFG_CENTER_WW4C1_3", - "CFG_CENTER_WW4C1_4", - "CFG_CENTER_WW4C1_5", - "CFG_CENTER_WW4C1_6", - "CFG_CENTER_WW4C1_7", - "CFG_CENTER_WW4C1_8", - "CFG_CENTER_WW4C1_9", - "CFG_CENTER_WW4C2_0", - "CFG_CENTER_WW4C2_1", - "CFG_CENTER_WW4C2_10", - "CFG_CENTER_WW4C2_11", - "CFG_CENTER_WW4C2_12", - "CFG_CENTER_WW4C2_13", - "CFG_CENTER_WW4C2_14", - "CFG_CENTER_WW4C2_15", - "CFG_CENTER_WW4C2_16", - "CFG_CENTER_WW4C2_17", - "CFG_CENTER_WW4C2_18", - "CFG_CENTER_WW4C2_19", - "CFG_CENTER_WW4C2_2", - "CFG_CENTER_WW4C2_3", - "CFG_CENTER_WW4C2_4", - "CFG_CENTER_WW4C2_5", - "CFG_CENTER_WW4C2_6", - "CFG_CENTER_WW4C2_7", - "CFG_CENTER_WW4C2_8", - "CFG_CENTER_WW4C2_9", - "CFG_CENTER_WW4C3_0", - "CFG_CENTER_WW4C3_1", - "CFG_CENTER_WW4C3_10", - "CFG_CENTER_WW4C3_11", - "CFG_CENTER_WW4C3_12", - "CFG_CENTER_WW4C3_13", - "CFG_CENTER_WW4C3_14", - "CFG_CENTER_WW4C3_15", - "CFG_CENTER_WW4C3_16", - "CFG_CENTER_WW4C3_17", - "CFG_CENTER_WW4C3_18", - "CFG_CENTER_WW4C3_19", - "CFG_CENTER_WW4C3_2", - "CFG_CENTER_WW4C3_3", - "CFG_CENTER_WW4C3_4", - "CFG_CENTER_WW4C3_5", - "CFG_CENTER_WW4C3_6", - "CFG_CENTER_WW4C3_7", - "CFG_CENTER_WW4C3_8", - "CFG_CENTER_WW4C3_9", - "CFG_CENTER_WW4END0_0", - "CFG_CENTER_WW4END0_1", - "CFG_CENTER_WW4END0_10", - "CFG_CENTER_WW4END0_11", - "CFG_CENTER_WW4END0_12", - "CFG_CENTER_WW4END0_13", - "CFG_CENTER_WW4END0_14", - "CFG_CENTER_WW4END0_15", - "CFG_CENTER_WW4END0_16", - "CFG_CENTER_WW4END0_17", - "CFG_CENTER_WW4END0_18", - "CFG_CENTER_WW4END0_19", - "CFG_CENTER_WW4END0_2", - "CFG_CENTER_WW4END0_3", - "CFG_CENTER_WW4END0_4", - "CFG_CENTER_WW4END0_5", - "CFG_CENTER_WW4END0_6", - "CFG_CENTER_WW4END0_7", - "CFG_CENTER_WW4END0_8", - "CFG_CENTER_WW4END0_9", - "CFG_CENTER_WW4END1_0", - "CFG_CENTER_WW4END1_1", - "CFG_CENTER_WW4END1_10", - "CFG_CENTER_WW4END1_11", - "CFG_CENTER_WW4END1_12", - "CFG_CENTER_WW4END1_13", - "CFG_CENTER_WW4END1_14", - "CFG_CENTER_WW4END1_15", - "CFG_CENTER_WW4END1_16", - "CFG_CENTER_WW4END1_17", - "CFG_CENTER_WW4END1_18", - "CFG_CENTER_WW4END1_19", - "CFG_CENTER_WW4END1_2", - "CFG_CENTER_WW4END1_3", - "CFG_CENTER_WW4END1_4", - "CFG_CENTER_WW4END1_5", - "CFG_CENTER_WW4END1_6", - "CFG_CENTER_WW4END1_7", - "CFG_CENTER_WW4END1_8", - "CFG_CENTER_WW4END1_9", - "CFG_CENTER_WW4END2_0", - "CFG_CENTER_WW4END2_1", - "CFG_CENTER_WW4END2_10", - "CFG_CENTER_WW4END2_11", - "CFG_CENTER_WW4END2_12", - "CFG_CENTER_WW4END2_13", - "CFG_CENTER_WW4END2_14", - "CFG_CENTER_WW4END2_15", - "CFG_CENTER_WW4END2_16", - "CFG_CENTER_WW4END2_17", - "CFG_CENTER_WW4END2_18", - "CFG_CENTER_WW4END2_19", - "CFG_CENTER_WW4END2_2", - "CFG_CENTER_WW4END2_3", - "CFG_CENTER_WW4END2_4", - "CFG_CENTER_WW4END2_5", - "CFG_CENTER_WW4END2_6", - "CFG_CENTER_WW4END2_7", - "CFG_CENTER_WW4END2_8", - "CFG_CENTER_WW4END2_9", - "CFG_CENTER_WW4END3_0", - "CFG_CENTER_WW4END3_1", - "CFG_CENTER_WW4END3_10", - "CFG_CENTER_WW4END3_11", - "CFG_CENTER_WW4END3_12", - "CFG_CENTER_WW4END3_13", - "CFG_CENTER_WW4END3_14", - "CFG_CENTER_WW4END3_15", - "CFG_CENTER_WW4END3_16", - "CFG_CENTER_WW4END3_17", - "CFG_CENTER_WW4END3_18", - "CFG_CENTER_WW4END3_19", - "CFG_CENTER_WW4END3_2", - "CFG_CENTER_WW4END3_3", - "CFG_CENTER_WW4END3_4", - "CFG_CENTER_WW4END3_5", - "CFG_CENTER_WW4END3_6", - "CFG_CENTER_WW4END3_7", - "CFG_CENTER_WW4END3_8", - "CFG_CENTER_WW4END3_9" - ] + "wires": { + "CFG_CENTER_BLOCK_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BSCAN1_CAPTURE": null, + "CFG_CENTER_BSCAN1_DRCK": null, + "CFG_CENTER_BSCAN1_RESET": null, + "CFG_CENTER_BSCAN1_RUNTEST": null, + "CFG_CENTER_BSCAN1_SEL": null, + "CFG_CENTER_BSCAN1_SHIFT": null, + "CFG_CENTER_BSCAN1_TCK": null, + "CFG_CENTER_BSCAN1_TDI": null, + "CFG_CENTER_BSCAN1_TDO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_BSCAN1_TMS": null, + "CFG_CENTER_BSCAN1_UPDATE": null, + "CFG_CENTER_BSCAN2_CAPTURE": null, + "CFG_CENTER_BSCAN2_DRCK": null, + "CFG_CENTER_BSCAN2_RESET": null, + "CFG_CENTER_BSCAN2_RUNTEST": null, + "CFG_CENTER_BSCAN2_SEL": null, + "CFG_CENTER_BSCAN2_SHIFT": null, + "CFG_CENTER_BSCAN2_TCK": null, + "CFG_CENTER_BSCAN2_TDI": null, + "CFG_CENTER_BSCAN2_TDO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_BSCAN2_TMS": null, + "CFG_CENTER_BSCAN2_UPDATE": null, + "CFG_CENTER_BSCAN3_CAPTURE": null, + "CFG_CENTER_BSCAN3_DRCK": null, + "CFG_CENTER_BSCAN3_RESET": null, + "CFG_CENTER_BSCAN3_RUNTEST": null, + "CFG_CENTER_BSCAN3_SEL": null, + "CFG_CENTER_BSCAN3_SHIFT": null, + "CFG_CENTER_BSCAN3_TCK": null, + "CFG_CENTER_BSCAN3_TDI": null, + "CFG_CENTER_BSCAN3_TDO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_BSCAN3_TMS": null, + "CFG_CENTER_BSCAN3_UPDATE": null, + "CFG_CENTER_BSCAN4_CAPTURE": null, + "CFG_CENTER_BSCAN4_DRCK": null, + "CFG_CENTER_BSCAN4_RESET": null, + "CFG_CENTER_BSCAN4_RUNTEST": null, + "CFG_CENTER_BSCAN4_SEL": null, + "CFG_CENTER_BSCAN4_SHIFT": null, + "CFG_CENTER_BSCAN4_TCK": null, + "CFG_CENTER_BSCAN4_TDI": null, + "CFG_CENTER_BSCAN4_TDO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_BSCAN4_TMS": null, + "CFG_CENTER_BSCAN4_UPDATE": null, + "CFG_CENTER_BYP0_0": null, + "CFG_CENTER_BYP0_1": null, + "CFG_CENTER_BYP0_10": null, + "CFG_CENTER_BYP0_11": null, + "CFG_CENTER_BYP0_12": null, + "CFG_CENTER_BYP0_13": null, + "CFG_CENTER_BYP0_14": null, + "CFG_CENTER_BYP0_15": null, + "CFG_CENTER_BYP0_16": null, + "CFG_CENTER_BYP0_17": null, + "CFG_CENTER_BYP0_18": null, + "CFG_CENTER_BYP0_19": null, + "CFG_CENTER_BYP0_2": null, + "CFG_CENTER_BYP0_3": null, + "CFG_CENTER_BYP0_4": null, + "CFG_CENTER_BYP0_5": null, + "CFG_CENTER_BYP0_6": null, + "CFG_CENTER_BYP0_7": null, + "CFG_CENTER_BYP0_8": null, + "CFG_CENTER_BYP0_9": null, + "CFG_CENTER_BYP1_0": null, + "CFG_CENTER_BYP1_1": null, + "CFG_CENTER_BYP1_10": null, + "CFG_CENTER_BYP1_11": null, + "CFG_CENTER_BYP1_12": null, + "CFG_CENTER_BYP1_13": null, + "CFG_CENTER_BYP1_14": null, + "CFG_CENTER_BYP1_15": null, + "CFG_CENTER_BYP1_16": null, + "CFG_CENTER_BYP1_17": null, + "CFG_CENTER_BYP1_18": null, + "CFG_CENTER_BYP1_19": null, + "CFG_CENTER_BYP1_2": null, + "CFG_CENTER_BYP1_3": null, + "CFG_CENTER_BYP1_4": null, + "CFG_CENTER_BYP1_5": null, + "CFG_CENTER_BYP1_6": null, + "CFG_CENTER_BYP1_7": null, + "CFG_CENTER_BYP1_8": null, + "CFG_CENTER_BYP1_9": null, + "CFG_CENTER_BYP2_0": null, + "CFG_CENTER_BYP2_1": null, + "CFG_CENTER_BYP2_10": null, + "CFG_CENTER_BYP2_11": null, + "CFG_CENTER_BYP2_12": null, + "CFG_CENTER_BYP2_13": null, + "CFG_CENTER_BYP2_14": null, + "CFG_CENTER_BYP2_15": null, + "CFG_CENTER_BYP2_16": null, + "CFG_CENTER_BYP2_17": null, + "CFG_CENTER_BYP2_18": null, + "CFG_CENTER_BYP2_19": null, + "CFG_CENTER_BYP2_2": null, + "CFG_CENTER_BYP2_3": null, + "CFG_CENTER_BYP2_4": null, + "CFG_CENTER_BYP2_5": null, + "CFG_CENTER_BYP2_6": null, + "CFG_CENTER_BYP2_7": null, + "CFG_CENTER_BYP2_8": null, + "CFG_CENTER_BYP2_9": null, + "CFG_CENTER_BYP3_0": null, + "CFG_CENTER_BYP3_1": null, + "CFG_CENTER_BYP3_10": null, + "CFG_CENTER_BYP3_11": null, + "CFG_CENTER_BYP3_12": null, + "CFG_CENTER_BYP3_13": null, + "CFG_CENTER_BYP3_14": null, + "CFG_CENTER_BYP3_15": null, + "CFG_CENTER_BYP3_16": null, + "CFG_CENTER_BYP3_17": null, + "CFG_CENTER_BYP3_18": null, + "CFG_CENTER_BYP3_19": null, + "CFG_CENTER_BYP3_2": null, + "CFG_CENTER_BYP3_3": null, + "CFG_CENTER_BYP3_4": null, + "CFG_CENTER_BYP3_5": null, + "CFG_CENTER_BYP3_6": null, + "CFG_CENTER_BYP3_7": null, + "CFG_CENTER_BYP3_8": null, + "CFG_CENTER_BYP3_9": null, + "CFG_CENTER_BYP4_0": null, + "CFG_CENTER_BYP4_1": null, + "CFG_CENTER_BYP4_10": null, + "CFG_CENTER_BYP4_11": null, + "CFG_CENTER_BYP4_12": null, + "CFG_CENTER_BYP4_13": null, + "CFG_CENTER_BYP4_14": null, + "CFG_CENTER_BYP4_15": null, + "CFG_CENTER_BYP4_16": null, + "CFG_CENTER_BYP4_17": null, + "CFG_CENTER_BYP4_18": null, + "CFG_CENTER_BYP4_19": null, + "CFG_CENTER_BYP4_2": null, + "CFG_CENTER_BYP4_3": null, + "CFG_CENTER_BYP4_4": null, + "CFG_CENTER_BYP4_5": null, + "CFG_CENTER_BYP4_6": null, + "CFG_CENTER_BYP4_7": null, + "CFG_CENTER_BYP4_8": null, + "CFG_CENTER_BYP4_9": null, + "CFG_CENTER_BYP5_0": null, + "CFG_CENTER_BYP5_1": null, + "CFG_CENTER_BYP5_10": null, + "CFG_CENTER_BYP5_11": null, + "CFG_CENTER_BYP5_12": null, + "CFG_CENTER_BYP5_13": null, + "CFG_CENTER_BYP5_14": null, + "CFG_CENTER_BYP5_15": null, + "CFG_CENTER_BYP5_16": null, + "CFG_CENTER_BYP5_17": null, + "CFG_CENTER_BYP5_18": null, + "CFG_CENTER_BYP5_19": null, + "CFG_CENTER_BYP5_2": null, + "CFG_CENTER_BYP5_3": null, + "CFG_CENTER_BYP5_4": null, + "CFG_CENTER_BYP5_5": null, + "CFG_CENTER_BYP5_6": null, + "CFG_CENTER_BYP5_7": null, + "CFG_CENTER_BYP5_8": null, + "CFG_CENTER_BYP5_9": null, + "CFG_CENTER_BYP6_0": null, + "CFG_CENTER_BYP6_1": null, + "CFG_CENTER_BYP6_10": null, + "CFG_CENTER_BYP6_11": null, + "CFG_CENTER_BYP6_12": null, + "CFG_CENTER_BYP6_13": null, + "CFG_CENTER_BYP6_14": null, + "CFG_CENTER_BYP6_15": null, + "CFG_CENTER_BYP6_16": null, + "CFG_CENTER_BYP6_17": null, + "CFG_CENTER_BYP6_18": null, + "CFG_CENTER_BYP6_19": null, + "CFG_CENTER_BYP6_2": null, + "CFG_CENTER_BYP6_3": null, + "CFG_CENTER_BYP6_4": null, + "CFG_CENTER_BYP6_5": null, + "CFG_CENTER_BYP6_6": null, + "CFG_CENTER_BYP6_7": null, + "CFG_CENTER_BYP6_8": null, + "CFG_CENTER_BYP6_9": null, + "CFG_CENTER_BYP7_0": null, + "CFG_CENTER_BYP7_1": null, + "CFG_CENTER_BYP7_10": null, + "CFG_CENTER_BYP7_11": null, + "CFG_CENTER_BYP7_12": null, + "CFG_CENTER_BYP7_13": null, + "CFG_CENTER_BYP7_14": null, + "CFG_CENTER_BYP7_15": null, + "CFG_CENTER_BYP7_16": null, + "CFG_CENTER_BYP7_17": null, + "CFG_CENTER_BYP7_18": null, + "CFG_CENTER_BYP7_19": null, + "CFG_CENTER_BYP7_2": null, + "CFG_CENTER_BYP7_3": null, + "CFG_CENTER_BYP7_4": null, + "CFG_CENTER_BYP7_5": null, + "CFG_CENTER_BYP7_6": null, + "CFG_CENTER_BYP7_7": null, + "CFG_CENTER_BYP7_8": null, + "CFG_CENTER_BYP7_9": null, + "CFG_CENTER_CAPTURE_CAP": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_CAPTURE_CLK": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_CFG_IO_ACCESS_CCLK": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA0": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA1": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA10": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA11": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA12": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA13": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA14": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA15": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA16": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA17": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA18": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA19": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA2": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA20": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA21": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA22": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA23": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA24": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA25": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA26": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA27": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA28": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA29": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA3": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA30": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA31": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA4": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA5": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA6": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA7": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA8": null, + "CFG_CENTER_CFG_IO_ACCESS_CFGDATA9": null, + "CFG_CENTER_CFG_IO_ACCESS_INITBI": null, + "CFG_CENTER_CFG_IO_ACCESS_INITBO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_CFG_IO_ACCESS_MASTER": null, + "CFG_CENTER_CFG_IO_ACCESS_MODE0": null, + "CFG_CENTER_CFG_IO_ACCESS_MODE1": null, + "CFG_CENTER_CFG_IO_ACCESS_MODE2": null, + "CFG_CENTER_CFG_IO_ACCESS_PUDCB": null, + "CFG_CENTER_CFG_IO_ACCESS_RDWRB": null, + "CFG_CENTER_CFG_IO_ACCESS_TDO": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_CFG_IO_ACCESS_VGGCOMPOUT": null, + "CFG_CENTER_CK_BUFHCLK0": null, + "CFG_CENTER_CK_BUFHCLK1": null, + "CFG_CENTER_CK_BUFHCLK10": null, + "CFG_CENTER_CK_BUFHCLK11": null, + "CFG_CENTER_CK_BUFHCLK2": null, + "CFG_CENTER_CK_BUFHCLK3": null, + "CFG_CENTER_CK_BUFHCLK4": null, + "CFG_CENTER_CK_BUFHCLK5": null, + "CFG_CENTER_CK_BUFHCLK6": null, + "CFG_CENTER_CK_BUFHCLK7": null, + "CFG_CENTER_CK_BUFHCLK8": null, + "CFG_CENTER_CK_BUFHCLK9": null, + "CFG_CENTER_CK_BUFRCLK0": null, + "CFG_CENTER_CK_BUFRCLK1": null, + "CFG_CENTER_CK_BUFRCLK2": null, + "CFG_CENTER_CK_BUFRCLK3": null, + "CFG_CENTER_CK_IN0": null, + "CFG_CENTER_CK_IN1": null, + "CFG_CENTER_CK_IN10": null, + "CFG_CENTER_CK_IN11": null, + "CFG_CENTER_CK_IN12": null, + "CFG_CENTER_CK_IN13": null, + "CFG_CENTER_CK_IN2": null, + "CFG_CENTER_CK_IN3": null, + "CFG_CENTER_CK_IN4": null, + "CFG_CENTER_CK_IN5": null, + "CFG_CENTER_CK_IN6": null, + "CFG_CENTER_CK_IN7": null, + "CFG_CENTER_CK_IN8": null, + "CFG_CENTER_CK_IN9": null, + "CFG_CENTER_CLK0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_9": { + "cap": "1.111", + "res": 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"CFG_CENTER_ICAP1_O22": null, + "CFG_CENTER_ICAP1_O23": null, + "CFG_CENTER_ICAP1_O24": null, + "CFG_CENTER_ICAP1_O25": null, + "CFG_CENTER_ICAP1_O26": null, + "CFG_CENTER_ICAP1_O27": null, + "CFG_CENTER_ICAP1_O28": null, + "CFG_CENTER_ICAP1_O29": null, + "CFG_CENTER_ICAP1_O3": null, + "CFG_CENTER_ICAP1_O30": null, + "CFG_CENTER_ICAP1_O31": null, + "CFG_CENTER_ICAP1_O4": null, + "CFG_CENTER_ICAP1_O5": null, + "CFG_CENTER_ICAP1_O6": null, + "CFG_CENTER_ICAP1_O7": null, + "CFG_CENTER_ICAP1_O8": null, + "CFG_CENTER_ICAP1_O9": null, + "CFG_CENTER_ICAP1_RDWRB": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX10_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX11_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX12_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_4": { + "cap": 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"CFG_CENTER_IMUX16_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_15": { + "cap": "1.111", + "res": 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+ "res": "0.000" + }, + "CFG_CENTER_IMUX18_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_14": { 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"0.000" + }, + "CFG_CENTER_IMUX23_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_13": { 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"0.000" + }, + "CFG_CENTER_IMUX26_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_17": { + "cap": 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"0.000" + }, + "CFG_CENTER_IMUX29_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_2": { + "cap": "1.111", + "res": "0.000" + }, + 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+ "res": "0.000" + }, + "CFG_CENTER_IMUX33_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_7": { + 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+ "res": "0.000" + }, + "CFG_CENTER_IMUX36_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_2": { + "cap": "1.111", + "res": "0.000" + }, + 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"0.000" + }, + "CFG_CENTER_IMUX45_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LH10_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_10": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_11": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_12": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_13": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_14": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_15": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_16": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_17": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_18": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_19": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LOGIC_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_13": { 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"0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_19": { + "cap": "1.111", + "res": "0.000" + }, + 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"CFG_CENTER_LOGIC_OUTS_B19_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_19": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_10": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_11": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_12": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_13": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_14": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_15": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_16": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_17": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_18": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_19": { + "cap": "1.111", + "res": "0.000" + }, + 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"325.400" + }, + "CFG_CENTER_WL1END3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WL1END3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WR1END0_13": { + "cap": "99.000", + "res": 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"cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4B3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_10": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_11": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_12": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_13": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_14": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_15": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_16": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_17": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_18": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_19": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_9": { + "cap": "99.000", + "res": "325.400" + } + } } diff --git a/kintex7/tile_type_CFG_CENTER_TOP.json b/kintex7/tile_type_CFG_CENTER_TOP.json index e0a60f6..e00c785 100644 --- a/kintex7/tile_type_CFG_CENTER_TOP.json +++ b/kintex7/tile_type_CFG_CENTER_TOP.json @@ -2,268 +2,686 @@ "pips": { "CFG_CENTER_TOP.CFG_CENTER_CLK1_0->CFG_CENTER_TOP_ICAP1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_TOP_ICAP1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_CLK1_0" }, "CFG_CENTER_TOP.CFG_CENTER_DNA_PORT_DOUT->CFG_CENTER_LOGIC_OUTS_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_DNA_PORT_DOUT" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR0->CFG_CENTER_LOGIC_OUTS_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR0" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR1->CFG_CENTER_LOGIC_OUTS_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR1" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR10->CFG_CENTER_LOGIC_OUTS_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR10" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR11->CFG_CENTER_LOGIC_OUTS_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR11" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR12->CFG_CENTER_LOGIC_OUTS_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR12" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR13->CFG_CENTER_LOGIC_OUTS_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR13" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR14->CFG_CENTER_LOGIC_OUTS_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR14" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR15->CFG_CENTER_LOGIC_OUTS_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR15" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR16->CFG_CENTER_LOGIC_OUTS_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR16" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR17->CFG_CENTER_LOGIC_OUTS_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR17" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR18->CFG_CENTER_LOGIC_OUTS_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR18" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR19->CFG_CENTER_LOGIC_OUTS_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR19" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR2->CFG_CENTER_LOGIC_OUTS_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR2" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR20->CFG_CENTER_LOGIC_OUTS_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR20" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR21->CFG_CENTER_LOGIC_OUTS_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR21" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR22->CFG_CENTER_LOGIC_OUTS_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR22" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR23->CFG_CENTER_LOGIC_OUTS_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR23" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR24->CFG_CENTER_LOGIC_OUTS_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR24" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR25->CFG_CENTER_LOGIC_OUTS_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR25" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR26->CFG_CENTER_LOGIC_OUTS_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR26" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR27->CFG_CENTER_LOGIC_OUTS_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR27" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR28->CFG_CENTER_LOGIC_OUTS_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR28" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR29->CFG_CENTER_LOGIC_OUTS_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR29" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR3->CFG_CENTER_LOGIC_OUTS_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR3" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR30->CFG_CENTER_LOGIC_OUTS_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR30" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR31->CFG_CENTER_LOGIC_OUTS_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR31" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR4->CFG_CENTER_LOGIC_OUTS_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR4" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR5->CFG_CENTER_LOGIC_OUTS_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR5" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR6->CFG_CENTER_LOGIC_OUTS_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR6" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR7->CFG_CENTER_LOGIC_OUTS_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR7" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR8->CFG_CENTER_LOGIC_OUTS_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR8" }, "CFG_CENTER_TOP.CFG_CENTER_EFUSE_USR_EFUSEUSR9->CFG_CENTER_LOGIC_OUTS_B17_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_LOGIC_OUTS_B17_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR9" }, "CFG_CENTER_TOP.CFG_CENTER_IMUX41_5->CFG_CENTER_DNA_PORT_READ": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DNA_PORT_READ", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX41_5" }, "CFG_CENTER_TOP.CFG_CENTER_IMUX42_5->CFG_CENTER_DNA_PORT_SHIFT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DNA_PORT_SHIFT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX42_5" }, "CFG_CENTER_TOP.CFG_CENTER_IMUX43_5->CFG_CENTER_DNA_PORT_DIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DNA_PORT_DIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_IMUX43_5" }, "CFG_CENTER_TOP.CFG_CENTER_TOP_DNA_PORT_CLK->CFG_CENTER_DNA_PORT_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CFG_CENTER_DNA_PORT_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CFG_CENTER_TOP_DNA_PORT_CLK" } }, @@ -272,11 +690,56 @@ "name": "X0Y0", "prefix": "DNA_PORT", "site_pins": { - "CLK": "CFG_CENTER_DNA_PORT_CLK", - "DIN": "CFG_CENTER_DNA_PORT_DIN", - "DOUT": "CFG_CENTER_DNA_PORT_DOUT", - "READ": "CFG_CENTER_DNA_PORT_READ", - "SHIFT": "CFG_CENTER_DNA_PORT_SHIFT" + "CLK": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.009", + "0.010" + ], + "wire": "CFG_CENTER_DNA_PORT_CLK" + }, + "DIN": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.009", + "0.010" + ], + "wire": "CFG_CENTER_DNA_PORT_DIN" + }, + "DOUT": { + "delay": [ + "0.001", + "0.001", + "0.009", + "0.010" + ], + "res": "0.0", + "wire": "CFG_CENTER_DNA_PORT_DOUT" + }, + "READ": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.009", + "0.010" + ], + "wire": "CFG_CENTER_DNA_PORT_READ" + }, + "SHIFT": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.009", + "0.010" + ], + "wire": "CFG_CENTER_DNA_PORT_SHIFT" + } }, "type": "DNA_PORT", "x_coord": 0, @@ -286,38 +749,326 @@ "name": "X0Y0", "prefix": "EFUSE_USR", "site_pins": { - "EFUSEUSR0": "CFG_CENTER_EFUSE_USR_EFUSEUSR0", - "EFUSEUSR1": "CFG_CENTER_EFUSE_USR_EFUSEUSR1", - "EFUSEUSR10": "CFG_CENTER_EFUSE_USR_EFUSEUSR10", - "EFUSEUSR11": "CFG_CENTER_EFUSE_USR_EFUSEUSR11", - "EFUSEUSR12": "CFG_CENTER_EFUSE_USR_EFUSEUSR12", - "EFUSEUSR13": "CFG_CENTER_EFUSE_USR_EFUSEUSR13", - "EFUSEUSR14": "CFG_CENTER_EFUSE_USR_EFUSEUSR14", - "EFUSEUSR15": "CFG_CENTER_EFUSE_USR_EFUSEUSR15", - "EFUSEUSR16": "CFG_CENTER_EFUSE_USR_EFUSEUSR16", - "EFUSEUSR17": "CFG_CENTER_EFUSE_USR_EFUSEUSR17", - "EFUSEUSR18": "CFG_CENTER_EFUSE_USR_EFUSEUSR18", - "EFUSEUSR19": "CFG_CENTER_EFUSE_USR_EFUSEUSR19", - "EFUSEUSR2": "CFG_CENTER_EFUSE_USR_EFUSEUSR2", - "EFUSEUSR20": "CFG_CENTER_EFUSE_USR_EFUSEUSR20", - "EFUSEUSR21": "CFG_CENTER_EFUSE_USR_EFUSEUSR21", - "EFUSEUSR22": "CFG_CENTER_EFUSE_USR_EFUSEUSR22", - "EFUSEUSR23": "CFG_CENTER_EFUSE_USR_EFUSEUSR23", - "EFUSEUSR24": "CFG_CENTER_EFUSE_USR_EFUSEUSR24", - "EFUSEUSR25": "CFG_CENTER_EFUSE_USR_EFUSEUSR25", - "EFUSEUSR26": "CFG_CENTER_EFUSE_USR_EFUSEUSR26", - "EFUSEUSR27": "CFG_CENTER_EFUSE_USR_EFUSEUSR27", - "EFUSEUSR28": "CFG_CENTER_EFUSE_USR_EFUSEUSR28", - "EFUSEUSR29": "CFG_CENTER_EFUSE_USR_EFUSEUSR29", - "EFUSEUSR3": "CFG_CENTER_EFUSE_USR_EFUSEUSR3", - "EFUSEUSR30": "CFG_CENTER_EFUSE_USR_EFUSEUSR30", - "EFUSEUSR31": "CFG_CENTER_EFUSE_USR_EFUSEUSR31", - "EFUSEUSR4": "CFG_CENTER_EFUSE_USR_EFUSEUSR4", - "EFUSEUSR5": "CFG_CENTER_EFUSE_USR_EFUSEUSR5", - "EFUSEUSR6": "CFG_CENTER_EFUSE_USR_EFUSEUSR6", - "EFUSEUSR7": "CFG_CENTER_EFUSE_USR_EFUSEUSR7", - "EFUSEUSR8": "CFG_CENTER_EFUSE_USR_EFUSEUSR8", - "EFUSEUSR9": "CFG_CENTER_EFUSE_USR_EFUSEUSR9" + "EFUSEUSR0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR0" + }, + "EFUSEUSR1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR1" + }, + "EFUSEUSR10": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR10" + }, + "EFUSEUSR11": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR11" + }, + "EFUSEUSR12": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR12" + }, + "EFUSEUSR13": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR13" + }, + "EFUSEUSR14": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR14" + }, + "EFUSEUSR15": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR15" + }, + "EFUSEUSR16": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR16" + }, + "EFUSEUSR17": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR17" + }, + "EFUSEUSR18": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR18" + }, + "EFUSEUSR19": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR19" + }, + "EFUSEUSR2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR2" + }, + "EFUSEUSR20": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR20" + }, + "EFUSEUSR21": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR21" + }, + "EFUSEUSR22": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR22" + }, + "EFUSEUSR23": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR23" + }, + "EFUSEUSR24": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR24" + }, + "EFUSEUSR25": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR25" + }, + "EFUSEUSR26": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR26" + }, + "EFUSEUSR27": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR27" + }, + "EFUSEUSR28": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR28" + }, + "EFUSEUSR29": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR29" + }, + "EFUSEUSR3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR3" + }, + "EFUSEUSR30": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR30" + }, + "EFUSEUSR31": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR31" + }, + "EFUSEUSR4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR4" + }, + "EFUSEUSR5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR5" + }, + "EFUSEUSR6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR6" + }, + "EFUSEUSR7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR7" + }, + "EFUSEUSR8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR8" + }, + "EFUSEUSR9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "152.625", + "wire": "CFG_CENTER_EFUSE_USR_EFUSEUSR9" + } }, "type": "EFUSE_USR", "x_coord": 0, @@ -325,2266 +1076,8398 @@ } ], "tile_type": "CFG_CENTER_TOP", - "wires": [ - "CFG_CENTER_BLOCK_OUTS_B0_0", - "CFG_CENTER_BLOCK_OUTS_B0_1", - "CFG_CENTER_BLOCK_OUTS_B0_2", - "CFG_CENTER_BLOCK_OUTS_B0_3", - "CFG_CENTER_BLOCK_OUTS_B0_4", - "CFG_CENTER_BLOCK_OUTS_B0_5", - "CFG_CENTER_BLOCK_OUTS_B0_6", - "CFG_CENTER_BLOCK_OUTS_B0_7", - "CFG_CENTER_BLOCK_OUTS_B0_8", - "CFG_CENTER_BLOCK_OUTS_B0_9", - "CFG_CENTER_BLOCK_OUTS_B1_0", - "CFG_CENTER_BLOCK_OUTS_B1_1", - "CFG_CENTER_BLOCK_OUTS_B1_2", - "CFG_CENTER_BLOCK_OUTS_B1_3", - "CFG_CENTER_BLOCK_OUTS_B1_4", - "CFG_CENTER_BLOCK_OUTS_B1_5", - "CFG_CENTER_BLOCK_OUTS_B1_6", - "CFG_CENTER_BLOCK_OUTS_B1_7", - "CFG_CENTER_BLOCK_OUTS_B1_8", - "CFG_CENTER_BLOCK_OUTS_B1_9", - "CFG_CENTER_BLOCK_OUTS_B2_0", - "CFG_CENTER_BLOCK_OUTS_B2_1", - "CFG_CENTER_BLOCK_OUTS_B2_2", - "CFG_CENTER_BLOCK_OUTS_B2_3", - "CFG_CENTER_BLOCK_OUTS_B2_4", - "CFG_CENTER_BLOCK_OUTS_B2_5", - "CFG_CENTER_BLOCK_OUTS_B2_6", - "CFG_CENTER_BLOCK_OUTS_B2_7", - "CFG_CENTER_BLOCK_OUTS_B2_8", - "CFG_CENTER_BLOCK_OUTS_B2_9", - "CFG_CENTER_BLOCK_OUTS_B3_0", - "CFG_CENTER_BLOCK_OUTS_B3_1", - "CFG_CENTER_BLOCK_OUTS_B3_2", - "CFG_CENTER_BLOCK_OUTS_B3_3", - "CFG_CENTER_BLOCK_OUTS_B3_4", - "CFG_CENTER_BLOCK_OUTS_B3_5", - "CFG_CENTER_BLOCK_OUTS_B3_6", - "CFG_CENTER_BLOCK_OUTS_B3_7", - "CFG_CENTER_BLOCK_OUTS_B3_8", - "CFG_CENTER_BLOCK_OUTS_B3_9", - "CFG_CENTER_BYP0_0", - "CFG_CENTER_BYP0_1", - "CFG_CENTER_BYP0_2", - "CFG_CENTER_BYP0_3", - "CFG_CENTER_BYP0_4", - "CFG_CENTER_BYP0_5", - "CFG_CENTER_BYP0_6", - "CFG_CENTER_BYP0_7", - "CFG_CENTER_BYP0_8", - "CFG_CENTER_BYP0_9", - "CFG_CENTER_BYP1_0", - "CFG_CENTER_BYP1_1", - "CFG_CENTER_BYP1_2", - "CFG_CENTER_BYP1_3", - "CFG_CENTER_BYP1_4", - "CFG_CENTER_BYP1_5", - "CFG_CENTER_BYP1_6", - "CFG_CENTER_BYP1_7", - "CFG_CENTER_BYP1_8", - "CFG_CENTER_BYP1_9", - "CFG_CENTER_BYP2_0", - "CFG_CENTER_BYP2_1", - "CFG_CENTER_BYP2_2", - "CFG_CENTER_BYP2_3", - "CFG_CENTER_BYP2_4", - "CFG_CENTER_BYP2_5", - "CFG_CENTER_BYP2_6", - "CFG_CENTER_BYP2_7", - "CFG_CENTER_BYP2_8", - "CFG_CENTER_BYP2_9", - "CFG_CENTER_BYP3_0", - "CFG_CENTER_BYP3_1", - "CFG_CENTER_BYP3_2", - "CFG_CENTER_BYP3_3", - "CFG_CENTER_BYP3_4", - "CFG_CENTER_BYP3_5", - "CFG_CENTER_BYP3_6", - "CFG_CENTER_BYP3_7", - "CFG_CENTER_BYP3_8", - "CFG_CENTER_BYP3_9", - "CFG_CENTER_BYP4_0", - "CFG_CENTER_BYP4_1", - "CFG_CENTER_BYP4_2", - "CFG_CENTER_BYP4_3", - "CFG_CENTER_BYP4_4", - "CFG_CENTER_BYP4_5", - "CFG_CENTER_BYP4_6", - "CFG_CENTER_BYP4_7", - "CFG_CENTER_BYP4_8", - "CFG_CENTER_BYP4_9", - "CFG_CENTER_BYP5_0", - "CFG_CENTER_BYP5_1", - "CFG_CENTER_BYP5_2", - "CFG_CENTER_BYP5_3", - "CFG_CENTER_BYP5_4", - "CFG_CENTER_BYP5_5", - "CFG_CENTER_BYP5_6", - "CFG_CENTER_BYP5_7", - "CFG_CENTER_BYP5_8", - "CFG_CENTER_BYP5_9", - "CFG_CENTER_BYP6_0", - "CFG_CENTER_BYP6_1", - "CFG_CENTER_BYP6_2", - "CFG_CENTER_BYP6_3", - "CFG_CENTER_BYP6_4", - "CFG_CENTER_BYP6_5", - "CFG_CENTER_BYP6_6", - "CFG_CENTER_BYP6_7", - "CFG_CENTER_BYP6_8", - "CFG_CENTER_BYP6_9", - "CFG_CENTER_BYP7_0", - "CFG_CENTER_BYP7_1", - "CFG_CENTER_BYP7_2", - "CFG_CENTER_BYP7_3", - "CFG_CENTER_BYP7_4", - "CFG_CENTER_BYP7_5", - "CFG_CENTER_BYP7_6", - "CFG_CENTER_BYP7_7", - "CFG_CENTER_BYP7_8", - "CFG_CENTER_BYP7_9", - "CFG_CENTER_CLK0_0", - "CFG_CENTER_CLK0_1", - "CFG_CENTER_CLK0_2", - "CFG_CENTER_CLK0_3", - "CFG_CENTER_CLK0_4", - "CFG_CENTER_CLK0_5", - "CFG_CENTER_CLK0_6", - "CFG_CENTER_CLK0_7", - "CFG_CENTER_CLK0_8", - "CFG_CENTER_CLK0_9", - "CFG_CENTER_CLK1_0", - "CFG_CENTER_CLK1_1", - "CFG_CENTER_CLK1_2", - "CFG_CENTER_CLK1_3", - "CFG_CENTER_CLK1_4", - "CFG_CENTER_CLK1_5", - "CFG_CENTER_CLK1_6", - "CFG_CENTER_CLK1_7", - "CFG_CENTER_CLK1_8", - "CFG_CENTER_CLK1_9", - "CFG_CENTER_CTRL0_0", - "CFG_CENTER_CTRL0_1", - "CFG_CENTER_CTRL0_2", - "CFG_CENTER_CTRL0_3", - "CFG_CENTER_CTRL0_4", - "CFG_CENTER_CTRL0_5", - "CFG_CENTER_CTRL0_6", - "CFG_CENTER_CTRL0_7", - "CFG_CENTER_CTRL0_8", - "CFG_CENTER_CTRL0_9", - "CFG_CENTER_CTRL1_0", - "CFG_CENTER_CTRL1_1", - "CFG_CENTER_CTRL1_2", - "CFG_CENTER_CTRL1_3", - "CFG_CENTER_CTRL1_4", - "CFG_CENTER_CTRL1_5", - "CFG_CENTER_CTRL1_6", - "CFG_CENTER_CTRL1_7", - "CFG_CENTER_CTRL1_8", - "CFG_CENTER_CTRL1_9", - "CFG_CENTER_DNA_PORT_CLK", - "CFG_CENTER_DNA_PORT_DIN", - "CFG_CENTER_DNA_PORT_DOUT", - "CFG_CENTER_DNA_PORT_READ", - "CFG_CENTER_DNA_PORT_SHIFT", - "CFG_CENTER_EE2A0_0", - "CFG_CENTER_EE2A0_1", - "CFG_CENTER_EE2A0_2", - "CFG_CENTER_EE2A0_3", - "CFG_CENTER_EE2A0_4", - "CFG_CENTER_EE2A0_5", - "CFG_CENTER_EE2A0_6", - "CFG_CENTER_EE2A0_7", - "CFG_CENTER_EE2A0_8", - "CFG_CENTER_EE2A0_9", - "CFG_CENTER_EE2A1_0", - "CFG_CENTER_EE2A1_1", - "CFG_CENTER_EE2A1_2", - "CFG_CENTER_EE2A1_3", - "CFG_CENTER_EE2A1_4", - "CFG_CENTER_EE2A1_5", - "CFG_CENTER_EE2A1_6", - "CFG_CENTER_EE2A1_7", - "CFG_CENTER_EE2A1_8", - "CFG_CENTER_EE2A1_9", - "CFG_CENTER_EE2A2_0", - "CFG_CENTER_EE2A2_1", - "CFG_CENTER_EE2A2_2", - "CFG_CENTER_EE2A2_3", - "CFG_CENTER_EE2A2_4", - "CFG_CENTER_EE2A2_5", - "CFG_CENTER_EE2A2_6", - "CFG_CENTER_EE2A2_7", - "CFG_CENTER_EE2A2_8", - "CFG_CENTER_EE2A2_9", - "CFG_CENTER_EE2A3_0", - "CFG_CENTER_EE2A3_1", - "CFG_CENTER_EE2A3_2", - "CFG_CENTER_EE2A3_3", - "CFG_CENTER_EE2A3_4", - "CFG_CENTER_EE2A3_5", - "CFG_CENTER_EE2A3_6", - "CFG_CENTER_EE2A3_7", - "CFG_CENTER_EE2A3_8", - "CFG_CENTER_EE2A3_9", - "CFG_CENTER_EE2BEG0_0", - "CFG_CENTER_EE2BEG0_1", - "CFG_CENTER_EE2BEG0_2", - "CFG_CENTER_EE2BEG0_3", - "CFG_CENTER_EE2BEG0_4", - "CFG_CENTER_EE2BEG0_5", - "CFG_CENTER_EE2BEG0_6", - "CFG_CENTER_EE2BEG0_7", - "CFG_CENTER_EE2BEG0_8", - "CFG_CENTER_EE2BEG0_9", - "CFG_CENTER_EE2BEG1_0", - "CFG_CENTER_EE2BEG1_1", - "CFG_CENTER_EE2BEG1_2", - "CFG_CENTER_EE2BEG1_3", - "CFG_CENTER_EE2BEG1_4", - "CFG_CENTER_EE2BEG1_5", - "CFG_CENTER_EE2BEG1_6", - "CFG_CENTER_EE2BEG1_7", - "CFG_CENTER_EE2BEG1_8", - "CFG_CENTER_EE2BEG1_9", - "CFG_CENTER_EE2BEG2_0", - "CFG_CENTER_EE2BEG2_1", - "CFG_CENTER_EE2BEG2_2", - "CFG_CENTER_EE2BEG2_3", - "CFG_CENTER_EE2BEG2_4", - "CFG_CENTER_EE2BEG2_5", - "CFG_CENTER_EE2BEG2_6", - "CFG_CENTER_EE2BEG2_7", - "CFG_CENTER_EE2BEG2_8", - "CFG_CENTER_EE2BEG2_9", - "CFG_CENTER_EE2BEG3_0", - "CFG_CENTER_EE2BEG3_1", - "CFG_CENTER_EE2BEG3_2", - "CFG_CENTER_EE2BEG3_3", - "CFG_CENTER_EE2BEG3_4", - "CFG_CENTER_EE2BEG3_5", - "CFG_CENTER_EE2BEG3_6", - "CFG_CENTER_EE2BEG3_7", - "CFG_CENTER_EE2BEG3_8", - "CFG_CENTER_EE2BEG3_9", - "CFG_CENTER_EE4A0_0", - "CFG_CENTER_EE4A0_1", - "CFG_CENTER_EE4A0_2", - "CFG_CENTER_EE4A0_3", - "CFG_CENTER_EE4A0_4", - "CFG_CENTER_EE4A0_5", - "CFG_CENTER_EE4A0_6", - "CFG_CENTER_EE4A0_7", - "CFG_CENTER_EE4A0_8", - "CFG_CENTER_EE4A0_9", - "CFG_CENTER_EE4A1_0", - "CFG_CENTER_EE4A1_1", - "CFG_CENTER_EE4A1_2", - "CFG_CENTER_EE4A1_3", - "CFG_CENTER_EE4A1_4", - "CFG_CENTER_EE4A1_5", - "CFG_CENTER_EE4A1_6", - "CFG_CENTER_EE4A1_7", - "CFG_CENTER_EE4A1_8", - "CFG_CENTER_EE4A1_9", - "CFG_CENTER_EE4A2_0", - "CFG_CENTER_EE4A2_1", - "CFG_CENTER_EE4A2_2", - "CFG_CENTER_EE4A2_3", - "CFG_CENTER_EE4A2_4", - "CFG_CENTER_EE4A2_5", - "CFG_CENTER_EE4A2_6", - "CFG_CENTER_EE4A2_7", - "CFG_CENTER_EE4A2_8", - "CFG_CENTER_EE4A2_9", - "CFG_CENTER_EE4A3_0", - "CFG_CENTER_EE4A3_1", - "CFG_CENTER_EE4A3_2", - "CFG_CENTER_EE4A3_3", - "CFG_CENTER_EE4A3_4", - "CFG_CENTER_EE4A3_5", - "CFG_CENTER_EE4A3_6", - "CFG_CENTER_EE4A3_7", - "CFG_CENTER_EE4A3_8", - "CFG_CENTER_EE4A3_9", - "CFG_CENTER_EE4B0_0", - "CFG_CENTER_EE4B0_1", - "CFG_CENTER_EE4B0_2", - "CFG_CENTER_EE4B0_3", - "CFG_CENTER_EE4B0_4", - "CFG_CENTER_EE4B0_5", - "CFG_CENTER_EE4B0_6", - "CFG_CENTER_EE4B0_7", - "CFG_CENTER_EE4B0_8", - "CFG_CENTER_EE4B0_9", - "CFG_CENTER_EE4B1_0", - "CFG_CENTER_EE4B1_1", - "CFG_CENTER_EE4B1_2", - "CFG_CENTER_EE4B1_3", - "CFG_CENTER_EE4B1_4", - "CFG_CENTER_EE4B1_5", - "CFG_CENTER_EE4B1_6", - "CFG_CENTER_EE4B1_7", - "CFG_CENTER_EE4B1_8", - "CFG_CENTER_EE4B1_9", - "CFG_CENTER_EE4B2_0", - "CFG_CENTER_EE4B2_1", - "CFG_CENTER_EE4B2_2", - "CFG_CENTER_EE4B2_3", - "CFG_CENTER_EE4B2_4", - "CFG_CENTER_EE4B2_5", - "CFG_CENTER_EE4B2_6", - "CFG_CENTER_EE4B2_7", - "CFG_CENTER_EE4B2_8", - "CFG_CENTER_EE4B2_9", - "CFG_CENTER_EE4B3_0", - "CFG_CENTER_EE4B3_1", - "CFG_CENTER_EE4B3_2", - "CFG_CENTER_EE4B3_3", - "CFG_CENTER_EE4B3_4", - "CFG_CENTER_EE4B3_5", - "CFG_CENTER_EE4B3_6", - "CFG_CENTER_EE4B3_7", - "CFG_CENTER_EE4B3_8", - "CFG_CENTER_EE4B3_9", - "CFG_CENTER_EE4BEG0_0", - "CFG_CENTER_EE4BEG0_1", - "CFG_CENTER_EE4BEG0_2", - "CFG_CENTER_EE4BEG0_3", - "CFG_CENTER_EE4BEG0_4", - "CFG_CENTER_EE4BEG0_5", - "CFG_CENTER_EE4BEG0_6", - "CFG_CENTER_EE4BEG0_7", - "CFG_CENTER_EE4BEG0_8", - "CFG_CENTER_EE4BEG0_9", - "CFG_CENTER_EE4BEG1_0", - "CFG_CENTER_EE4BEG1_1", - "CFG_CENTER_EE4BEG1_2", - "CFG_CENTER_EE4BEG1_3", - "CFG_CENTER_EE4BEG1_4", - "CFG_CENTER_EE4BEG1_5", - "CFG_CENTER_EE4BEG1_6", - "CFG_CENTER_EE4BEG1_7", - "CFG_CENTER_EE4BEG1_8", - "CFG_CENTER_EE4BEG1_9", - "CFG_CENTER_EE4BEG2_0", - "CFG_CENTER_EE4BEG2_1", - "CFG_CENTER_EE4BEG2_2", - "CFG_CENTER_EE4BEG2_3", - "CFG_CENTER_EE4BEG2_4", - "CFG_CENTER_EE4BEG2_5", - "CFG_CENTER_EE4BEG2_6", - "CFG_CENTER_EE4BEG2_7", - "CFG_CENTER_EE4BEG2_8", - "CFG_CENTER_EE4BEG2_9", - "CFG_CENTER_EE4BEG3_0", - "CFG_CENTER_EE4BEG3_1", - "CFG_CENTER_EE4BEG3_2", - "CFG_CENTER_EE4BEG3_3", - "CFG_CENTER_EE4BEG3_4", - "CFG_CENTER_EE4BEG3_5", - "CFG_CENTER_EE4BEG3_6", - "CFG_CENTER_EE4BEG3_7", - "CFG_CENTER_EE4BEG3_8", - "CFG_CENTER_EE4BEG3_9", - "CFG_CENTER_EE4C0_0", - "CFG_CENTER_EE4C0_1", - "CFG_CENTER_EE4C0_2", - "CFG_CENTER_EE4C0_3", - "CFG_CENTER_EE4C0_4", - "CFG_CENTER_EE4C0_5", - "CFG_CENTER_EE4C0_6", - "CFG_CENTER_EE4C0_7", - "CFG_CENTER_EE4C0_8", - "CFG_CENTER_EE4C0_9", - "CFG_CENTER_EE4C1_0", - "CFG_CENTER_EE4C1_1", - "CFG_CENTER_EE4C1_2", - "CFG_CENTER_EE4C1_3", - "CFG_CENTER_EE4C1_4", - "CFG_CENTER_EE4C1_5", - "CFG_CENTER_EE4C1_6", - "CFG_CENTER_EE4C1_7", - "CFG_CENTER_EE4C1_8", - "CFG_CENTER_EE4C1_9", - "CFG_CENTER_EE4C2_0", - "CFG_CENTER_EE4C2_1", - "CFG_CENTER_EE4C2_2", - "CFG_CENTER_EE4C2_3", - "CFG_CENTER_EE4C2_4", - "CFG_CENTER_EE4C2_5", - "CFG_CENTER_EE4C2_6", - "CFG_CENTER_EE4C2_7", - "CFG_CENTER_EE4C2_8", - "CFG_CENTER_EE4C2_9", - "CFG_CENTER_EE4C3_0", - "CFG_CENTER_EE4C3_1", - "CFG_CENTER_EE4C3_2", - "CFG_CENTER_EE4C3_3", - "CFG_CENTER_EE4C3_4", - "CFG_CENTER_EE4C3_5", - "CFG_CENTER_EE4C3_6", - "CFG_CENTER_EE4C3_7", - "CFG_CENTER_EE4C3_8", - "CFG_CENTER_EE4C3_9", - "CFG_CENTER_EFUSE_USR_EFUSEUSR0", - "CFG_CENTER_EFUSE_USR_EFUSEUSR1", - "CFG_CENTER_EFUSE_USR_EFUSEUSR10", - "CFG_CENTER_EFUSE_USR_EFUSEUSR11", - "CFG_CENTER_EFUSE_USR_EFUSEUSR12", - "CFG_CENTER_EFUSE_USR_EFUSEUSR13", - "CFG_CENTER_EFUSE_USR_EFUSEUSR14", - "CFG_CENTER_EFUSE_USR_EFUSEUSR15", - "CFG_CENTER_EFUSE_USR_EFUSEUSR16", - "CFG_CENTER_EFUSE_USR_EFUSEUSR17", - "CFG_CENTER_EFUSE_USR_EFUSEUSR18", - "CFG_CENTER_EFUSE_USR_EFUSEUSR19", - "CFG_CENTER_EFUSE_USR_EFUSEUSR2", - "CFG_CENTER_EFUSE_USR_EFUSEUSR20", - "CFG_CENTER_EFUSE_USR_EFUSEUSR21", - "CFG_CENTER_EFUSE_USR_EFUSEUSR22", - "CFG_CENTER_EFUSE_USR_EFUSEUSR23", - "CFG_CENTER_EFUSE_USR_EFUSEUSR24", - "CFG_CENTER_EFUSE_USR_EFUSEUSR25", - "CFG_CENTER_EFUSE_USR_EFUSEUSR26", - "CFG_CENTER_EFUSE_USR_EFUSEUSR27", - "CFG_CENTER_EFUSE_USR_EFUSEUSR28", - "CFG_CENTER_EFUSE_USR_EFUSEUSR29", - "CFG_CENTER_EFUSE_USR_EFUSEUSR3", - "CFG_CENTER_EFUSE_USR_EFUSEUSR30", - "CFG_CENTER_EFUSE_USR_EFUSEUSR31", - "CFG_CENTER_EFUSE_USR_EFUSEUSR4", - "CFG_CENTER_EFUSE_USR_EFUSEUSR5", - "CFG_CENTER_EFUSE_USR_EFUSEUSR6", - "CFG_CENTER_EFUSE_USR_EFUSEUSR7", - "CFG_CENTER_EFUSE_USR_EFUSEUSR8", - "CFG_CENTER_EFUSE_USR_EFUSEUSR9", - "CFG_CENTER_EL1BEG0_0", - "CFG_CENTER_EL1BEG0_1", - "CFG_CENTER_EL1BEG0_2", - "CFG_CENTER_EL1BEG0_3", - "CFG_CENTER_EL1BEG0_4", - "CFG_CENTER_EL1BEG0_5", - "CFG_CENTER_EL1BEG0_6", - "CFG_CENTER_EL1BEG0_7", - "CFG_CENTER_EL1BEG0_8", - "CFG_CENTER_EL1BEG0_9", - "CFG_CENTER_EL1BEG1_0", - "CFG_CENTER_EL1BEG1_1", - "CFG_CENTER_EL1BEG1_2", - "CFG_CENTER_EL1BEG1_3", - "CFG_CENTER_EL1BEG1_4", - "CFG_CENTER_EL1BEG1_5", - "CFG_CENTER_EL1BEG1_6", - "CFG_CENTER_EL1BEG1_7", - "CFG_CENTER_EL1BEG1_8", - "CFG_CENTER_EL1BEG1_9", - "CFG_CENTER_EL1BEG2_0", - "CFG_CENTER_EL1BEG2_1", - "CFG_CENTER_EL1BEG2_2", - "CFG_CENTER_EL1BEG2_3", - "CFG_CENTER_EL1BEG2_4", - "CFG_CENTER_EL1BEG2_5", - "CFG_CENTER_EL1BEG2_6", - "CFG_CENTER_EL1BEG2_7", - "CFG_CENTER_EL1BEG2_8", - "CFG_CENTER_EL1BEG2_9", - "CFG_CENTER_EL1BEG3_0", - "CFG_CENTER_EL1BEG3_1", - "CFG_CENTER_EL1BEG3_2", - "CFG_CENTER_EL1BEG3_3", - "CFG_CENTER_EL1BEG3_4", - "CFG_CENTER_EL1BEG3_5", - "CFG_CENTER_EL1BEG3_6", - "CFG_CENTER_EL1BEG3_7", - "CFG_CENTER_EL1BEG3_8", - "CFG_CENTER_EL1BEG3_9", - "CFG_CENTER_ER1BEG0_0", - "CFG_CENTER_ER1BEG0_1", - "CFG_CENTER_ER1BEG0_2", - "CFG_CENTER_ER1BEG0_3", - "CFG_CENTER_ER1BEG0_4", - "CFG_CENTER_ER1BEG0_5", - "CFG_CENTER_ER1BEG0_6", - "CFG_CENTER_ER1BEG0_7", - "CFG_CENTER_ER1BEG0_8", - "CFG_CENTER_ER1BEG0_9", - "CFG_CENTER_ER1BEG1_0", - "CFG_CENTER_ER1BEG1_1", - "CFG_CENTER_ER1BEG1_2", - "CFG_CENTER_ER1BEG1_3", - "CFG_CENTER_ER1BEG1_4", - "CFG_CENTER_ER1BEG1_5", - "CFG_CENTER_ER1BEG1_6", - "CFG_CENTER_ER1BEG1_7", - "CFG_CENTER_ER1BEG1_8", - "CFG_CENTER_ER1BEG1_9", - "CFG_CENTER_ER1BEG2_0", - "CFG_CENTER_ER1BEG2_1", - "CFG_CENTER_ER1BEG2_2", - "CFG_CENTER_ER1BEG2_3", - "CFG_CENTER_ER1BEG2_4", - "CFG_CENTER_ER1BEG2_5", - "CFG_CENTER_ER1BEG2_6", - "CFG_CENTER_ER1BEG2_7", - "CFG_CENTER_ER1BEG2_8", - "CFG_CENTER_ER1BEG2_9", - "CFG_CENTER_ER1BEG3_0", - "CFG_CENTER_ER1BEG3_1", - "CFG_CENTER_ER1BEG3_2", - "CFG_CENTER_ER1BEG3_3", - "CFG_CENTER_ER1BEG3_4", - "CFG_CENTER_ER1BEG3_5", - "CFG_CENTER_ER1BEG3_6", - "CFG_CENTER_ER1BEG3_7", - "CFG_CENTER_ER1BEG3_8", - "CFG_CENTER_ER1BEG3_9", - "CFG_CENTER_FAN0_0", - "CFG_CENTER_FAN0_1", - "CFG_CENTER_FAN0_2", - "CFG_CENTER_FAN0_3", - "CFG_CENTER_FAN0_4", - "CFG_CENTER_FAN0_5", - "CFG_CENTER_FAN0_6", - "CFG_CENTER_FAN0_7", - "CFG_CENTER_FAN0_8", - "CFG_CENTER_FAN0_9", - "CFG_CENTER_FAN1_0", - "CFG_CENTER_FAN1_1", - "CFG_CENTER_FAN1_2", - "CFG_CENTER_FAN1_3", - "CFG_CENTER_FAN1_4", - "CFG_CENTER_FAN1_5", - "CFG_CENTER_FAN1_6", - "CFG_CENTER_FAN1_7", - "CFG_CENTER_FAN1_8", - "CFG_CENTER_FAN1_9", - "CFG_CENTER_FAN2_0", - "CFG_CENTER_FAN2_1", - "CFG_CENTER_FAN2_2", - "CFG_CENTER_FAN2_3", - "CFG_CENTER_FAN2_4", - "CFG_CENTER_FAN2_5", - "CFG_CENTER_FAN2_6", - "CFG_CENTER_FAN2_7", - "CFG_CENTER_FAN2_8", - "CFG_CENTER_FAN2_9", - "CFG_CENTER_FAN3_0", - "CFG_CENTER_FAN3_1", - "CFG_CENTER_FAN3_2", - "CFG_CENTER_FAN3_3", - "CFG_CENTER_FAN3_4", - "CFG_CENTER_FAN3_5", - "CFG_CENTER_FAN3_6", - "CFG_CENTER_FAN3_7", - "CFG_CENTER_FAN3_8", - "CFG_CENTER_FAN3_9", - "CFG_CENTER_FAN4_0", - "CFG_CENTER_FAN4_1", - "CFG_CENTER_FAN4_2", - "CFG_CENTER_FAN4_3", - "CFG_CENTER_FAN4_4", - "CFG_CENTER_FAN4_5", - "CFG_CENTER_FAN4_6", - "CFG_CENTER_FAN4_7", - "CFG_CENTER_FAN4_8", - "CFG_CENTER_FAN4_9", - "CFG_CENTER_FAN5_0", - "CFG_CENTER_FAN5_1", - "CFG_CENTER_FAN5_2", - "CFG_CENTER_FAN5_3", - "CFG_CENTER_FAN5_4", - "CFG_CENTER_FAN5_5", - "CFG_CENTER_FAN5_6", - "CFG_CENTER_FAN5_7", - "CFG_CENTER_FAN5_8", - "CFG_CENTER_FAN5_9", - "CFG_CENTER_FAN6_0", - "CFG_CENTER_FAN6_1", - "CFG_CENTER_FAN6_2", - "CFG_CENTER_FAN6_3", - "CFG_CENTER_FAN6_4", - "CFG_CENTER_FAN6_5", - "CFG_CENTER_FAN6_6", - "CFG_CENTER_FAN6_7", - "CFG_CENTER_FAN6_8", - "CFG_CENTER_FAN6_9", - "CFG_CENTER_FAN7_0", - "CFG_CENTER_FAN7_1", - "CFG_CENTER_FAN7_2", - "CFG_CENTER_FAN7_3", - "CFG_CENTER_FAN7_4", - "CFG_CENTER_FAN7_5", - "CFG_CENTER_FAN7_6", - "CFG_CENTER_FAN7_7", - "CFG_CENTER_FAN7_8", - "CFG_CENTER_FAN7_9", - "CFG_CENTER_IMUX0_0", - "CFG_CENTER_IMUX0_1", - "CFG_CENTER_IMUX0_2", - "CFG_CENTER_IMUX0_3", - "CFG_CENTER_IMUX0_4", - "CFG_CENTER_IMUX0_5", - "CFG_CENTER_IMUX0_6", - "CFG_CENTER_IMUX0_7", - "CFG_CENTER_IMUX0_8", - "CFG_CENTER_IMUX0_9", - "CFG_CENTER_IMUX10_0", - "CFG_CENTER_IMUX10_1", - "CFG_CENTER_IMUX10_2", - "CFG_CENTER_IMUX10_3", - "CFG_CENTER_IMUX10_4", - "CFG_CENTER_IMUX10_5", - "CFG_CENTER_IMUX10_6", - "CFG_CENTER_IMUX10_7", - "CFG_CENTER_IMUX10_8", - "CFG_CENTER_IMUX10_9", - "CFG_CENTER_IMUX11_0", - "CFG_CENTER_IMUX11_1", - "CFG_CENTER_IMUX11_2", - "CFG_CENTER_IMUX11_3", - "CFG_CENTER_IMUX11_4", - "CFG_CENTER_IMUX11_5", - "CFG_CENTER_IMUX11_6", - "CFG_CENTER_IMUX11_7", - "CFG_CENTER_IMUX11_8", - "CFG_CENTER_IMUX11_9", - "CFG_CENTER_IMUX12_0", - "CFG_CENTER_IMUX12_1", - "CFG_CENTER_IMUX12_2", - "CFG_CENTER_IMUX12_3", - "CFG_CENTER_IMUX12_4", - "CFG_CENTER_IMUX12_5", - "CFG_CENTER_IMUX12_6", - "CFG_CENTER_IMUX12_7", - "CFG_CENTER_IMUX12_8", - "CFG_CENTER_IMUX12_9", - "CFG_CENTER_IMUX13_0", - "CFG_CENTER_IMUX13_1", - "CFG_CENTER_IMUX13_2", - "CFG_CENTER_IMUX13_3", - "CFG_CENTER_IMUX13_4", - "CFG_CENTER_IMUX13_5", - "CFG_CENTER_IMUX13_6", - "CFG_CENTER_IMUX13_7", - "CFG_CENTER_IMUX13_8", - "CFG_CENTER_IMUX13_9", - "CFG_CENTER_IMUX14_0", - "CFG_CENTER_IMUX14_1", - "CFG_CENTER_IMUX14_2", - "CFG_CENTER_IMUX14_3", - "CFG_CENTER_IMUX14_4", - "CFG_CENTER_IMUX14_5", - "CFG_CENTER_IMUX14_6", - "CFG_CENTER_IMUX14_7", - "CFG_CENTER_IMUX14_8", - "CFG_CENTER_IMUX14_9", - "CFG_CENTER_IMUX15_0", - "CFG_CENTER_IMUX15_1", - "CFG_CENTER_IMUX15_2", - "CFG_CENTER_IMUX15_3", - "CFG_CENTER_IMUX15_4", - "CFG_CENTER_IMUX15_5", - "CFG_CENTER_IMUX15_6", - "CFG_CENTER_IMUX15_7", - "CFG_CENTER_IMUX15_8", - "CFG_CENTER_IMUX15_9", - "CFG_CENTER_IMUX16_0", - "CFG_CENTER_IMUX16_1", - "CFG_CENTER_IMUX16_2", - "CFG_CENTER_IMUX16_3", - "CFG_CENTER_IMUX16_4", - "CFG_CENTER_IMUX16_5", - "CFG_CENTER_IMUX16_6", - "CFG_CENTER_IMUX16_7", - "CFG_CENTER_IMUX16_8", - "CFG_CENTER_IMUX16_9", - "CFG_CENTER_IMUX17_0", - "CFG_CENTER_IMUX17_1", - "CFG_CENTER_IMUX17_2", - "CFG_CENTER_IMUX17_3", - "CFG_CENTER_IMUX17_4", - "CFG_CENTER_IMUX17_5", - "CFG_CENTER_IMUX17_6", - "CFG_CENTER_IMUX17_7", - "CFG_CENTER_IMUX17_8", - "CFG_CENTER_IMUX17_9", - "CFG_CENTER_IMUX18_0", - "CFG_CENTER_IMUX18_1", - "CFG_CENTER_IMUX18_2", - "CFG_CENTER_IMUX18_3", - "CFG_CENTER_IMUX18_4", - "CFG_CENTER_IMUX18_5", - "CFG_CENTER_IMUX18_6", - "CFG_CENTER_IMUX18_7", - "CFG_CENTER_IMUX18_8", - "CFG_CENTER_IMUX18_9", - "CFG_CENTER_IMUX19_0", - "CFG_CENTER_IMUX19_1", - "CFG_CENTER_IMUX19_2", - "CFG_CENTER_IMUX19_3", - "CFG_CENTER_IMUX19_4", - "CFG_CENTER_IMUX19_5", - "CFG_CENTER_IMUX19_6", - "CFG_CENTER_IMUX19_7", - "CFG_CENTER_IMUX19_8", - "CFG_CENTER_IMUX19_9", - "CFG_CENTER_IMUX1_0", - "CFG_CENTER_IMUX1_1", - "CFG_CENTER_IMUX1_2", - "CFG_CENTER_IMUX1_3", - "CFG_CENTER_IMUX1_4", - "CFG_CENTER_IMUX1_5", - "CFG_CENTER_IMUX1_6", - "CFG_CENTER_IMUX1_7", - "CFG_CENTER_IMUX1_8", - "CFG_CENTER_IMUX1_9", - "CFG_CENTER_IMUX20_0", - "CFG_CENTER_IMUX20_1", - "CFG_CENTER_IMUX20_2", - "CFG_CENTER_IMUX20_3", - "CFG_CENTER_IMUX20_4", - "CFG_CENTER_IMUX20_5", - "CFG_CENTER_IMUX20_6", - "CFG_CENTER_IMUX20_7", - "CFG_CENTER_IMUX20_8", - "CFG_CENTER_IMUX20_9", - "CFG_CENTER_IMUX21_0", - "CFG_CENTER_IMUX21_1", - "CFG_CENTER_IMUX21_2", - "CFG_CENTER_IMUX21_3", - "CFG_CENTER_IMUX21_4", - "CFG_CENTER_IMUX21_5", - "CFG_CENTER_IMUX21_6", - "CFG_CENTER_IMUX21_7", - "CFG_CENTER_IMUX21_8", - "CFG_CENTER_IMUX21_9", - "CFG_CENTER_IMUX22_0", - "CFG_CENTER_IMUX22_1", - "CFG_CENTER_IMUX22_2", - "CFG_CENTER_IMUX22_3", - "CFG_CENTER_IMUX22_4", - "CFG_CENTER_IMUX22_5", - "CFG_CENTER_IMUX22_6", - "CFG_CENTER_IMUX22_7", - "CFG_CENTER_IMUX22_8", - "CFG_CENTER_IMUX22_9", - "CFG_CENTER_IMUX23_0", - "CFG_CENTER_IMUX23_1", - "CFG_CENTER_IMUX23_2", - "CFG_CENTER_IMUX23_3", - "CFG_CENTER_IMUX23_4", - "CFG_CENTER_IMUX23_5", - "CFG_CENTER_IMUX23_6", - "CFG_CENTER_IMUX23_7", - "CFG_CENTER_IMUX23_8", - "CFG_CENTER_IMUX23_9", - "CFG_CENTER_IMUX24_0", - "CFG_CENTER_IMUX24_1", - "CFG_CENTER_IMUX24_2", - "CFG_CENTER_IMUX24_3", - "CFG_CENTER_IMUX24_4", - "CFG_CENTER_IMUX24_5", - "CFG_CENTER_IMUX24_6", - "CFG_CENTER_IMUX24_7", - "CFG_CENTER_IMUX24_8", - "CFG_CENTER_IMUX24_9", - "CFG_CENTER_IMUX25_0", - "CFG_CENTER_IMUX25_1", - "CFG_CENTER_IMUX25_2", - "CFG_CENTER_IMUX25_3", - "CFG_CENTER_IMUX25_4", - "CFG_CENTER_IMUX25_5", - "CFG_CENTER_IMUX25_6", - "CFG_CENTER_IMUX25_7", - "CFG_CENTER_IMUX25_8", - "CFG_CENTER_IMUX25_9", - "CFG_CENTER_IMUX26_0", - "CFG_CENTER_IMUX26_1", - "CFG_CENTER_IMUX26_2", - "CFG_CENTER_IMUX26_3", - "CFG_CENTER_IMUX26_4", - "CFG_CENTER_IMUX26_5", - "CFG_CENTER_IMUX26_6", - "CFG_CENTER_IMUX26_7", - "CFG_CENTER_IMUX26_8", - "CFG_CENTER_IMUX26_9", - "CFG_CENTER_IMUX27_0", - "CFG_CENTER_IMUX27_1", - "CFG_CENTER_IMUX27_2", - "CFG_CENTER_IMUX27_3", - "CFG_CENTER_IMUX27_4", - "CFG_CENTER_IMUX27_5", - "CFG_CENTER_IMUX27_6", - "CFG_CENTER_IMUX27_7", - "CFG_CENTER_IMUX27_8", - "CFG_CENTER_IMUX27_9", - "CFG_CENTER_IMUX28_0", - "CFG_CENTER_IMUX28_1", - "CFG_CENTER_IMUX28_2", - "CFG_CENTER_IMUX28_3", - "CFG_CENTER_IMUX28_4", - "CFG_CENTER_IMUX28_5", - "CFG_CENTER_IMUX28_6", - "CFG_CENTER_IMUX28_7", - "CFG_CENTER_IMUX28_8", - "CFG_CENTER_IMUX28_9", - "CFG_CENTER_IMUX29_0", - "CFG_CENTER_IMUX29_1", - "CFG_CENTER_IMUX29_2", - "CFG_CENTER_IMUX29_3", - "CFG_CENTER_IMUX29_4", - "CFG_CENTER_IMUX29_5", - "CFG_CENTER_IMUX29_6", - "CFG_CENTER_IMUX29_7", - "CFG_CENTER_IMUX29_8", - "CFG_CENTER_IMUX29_9", - "CFG_CENTER_IMUX2_0", - "CFG_CENTER_IMUX2_1", - "CFG_CENTER_IMUX2_2", - "CFG_CENTER_IMUX2_3", - "CFG_CENTER_IMUX2_4", - "CFG_CENTER_IMUX2_5", - "CFG_CENTER_IMUX2_6", - "CFG_CENTER_IMUX2_7", - "CFG_CENTER_IMUX2_8", - "CFG_CENTER_IMUX2_9", - "CFG_CENTER_IMUX30_0", - "CFG_CENTER_IMUX30_1", - "CFG_CENTER_IMUX30_2", - "CFG_CENTER_IMUX30_3", - "CFG_CENTER_IMUX30_4", - "CFG_CENTER_IMUX30_5", - "CFG_CENTER_IMUX30_6", - "CFG_CENTER_IMUX30_7", - "CFG_CENTER_IMUX30_8", - "CFG_CENTER_IMUX30_9", - "CFG_CENTER_IMUX31_0", - "CFG_CENTER_IMUX31_1", - "CFG_CENTER_IMUX31_2", - "CFG_CENTER_IMUX31_3", - "CFG_CENTER_IMUX31_4", - "CFG_CENTER_IMUX31_5", - "CFG_CENTER_IMUX31_6", - "CFG_CENTER_IMUX31_7", - "CFG_CENTER_IMUX31_8", - "CFG_CENTER_IMUX31_9", - "CFG_CENTER_IMUX32_0", - "CFG_CENTER_IMUX32_1", - "CFG_CENTER_IMUX32_2", - "CFG_CENTER_IMUX32_3", - "CFG_CENTER_IMUX32_4", - "CFG_CENTER_IMUX32_5", - "CFG_CENTER_IMUX32_6", - "CFG_CENTER_IMUX32_7", - "CFG_CENTER_IMUX32_8", - "CFG_CENTER_IMUX32_9", - "CFG_CENTER_IMUX33_0", - "CFG_CENTER_IMUX33_1", - "CFG_CENTER_IMUX33_2", - "CFG_CENTER_IMUX33_3", - "CFG_CENTER_IMUX33_4", - "CFG_CENTER_IMUX33_5", - "CFG_CENTER_IMUX33_6", - "CFG_CENTER_IMUX33_7", - "CFG_CENTER_IMUX33_8", - "CFG_CENTER_IMUX33_9", - "CFG_CENTER_IMUX34_0", - "CFG_CENTER_IMUX34_1", - "CFG_CENTER_IMUX34_2", - "CFG_CENTER_IMUX34_3", - "CFG_CENTER_IMUX34_4", - "CFG_CENTER_IMUX34_5", - "CFG_CENTER_IMUX34_6", - "CFG_CENTER_IMUX34_7", - "CFG_CENTER_IMUX34_8", - "CFG_CENTER_IMUX34_9", - "CFG_CENTER_IMUX35_0", - "CFG_CENTER_IMUX35_1", - "CFG_CENTER_IMUX35_2", - "CFG_CENTER_IMUX35_3", - "CFG_CENTER_IMUX35_4", - "CFG_CENTER_IMUX35_5", - "CFG_CENTER_IMUX35_6", - "CFG_CENTER_IMUX35_7", - "CFG_CENTER_IMUX35_8", - "CFG_CENTER_IMUX35_9", - "CFG_CENTER_IMUX36_0", - "CFG_CENTER_IMUX36_1", - "CFG_CENTER_IMUX36_2", - "CFG_CENTER_IMUX36_3", - "CFG_CENTER_IMUX36_4", - "CFG_CENTER_IMUX36_5", - "CFG_CENTER_IMUX36_6", - "CFG_CENTER_IMUX36_7", - "CFG_CENTER_IMUX36_8", - "CFG_CENTER_IMUX36_9", - "CFG_CENTER_IMUX37_0", - "CFG_CENTER_IMUX37_1", - "CFG_CENTER_IMUX37_2", - "CFG_CENTER_IMUX37_3", - "CFG_CENTER_IMUX37_4", - "CFG_CENTER_IMUX37_5", - "CFG_CENTER_IMUX37_6", - "CFG_CENTER_IMUX37_7", - "CFG_CENTER_IMUX37_8", - "CFG_CENTER_IMUX37_9", - "CFG_CENTER_IMUX38_0", - "CFG_CENTER_IMUX38_1", - "CFG_CENTER_IMUX38_2", - "CFG_CENTER_IMUX38_3", - "CFG_CENTER_IMUX38_4", - "CFG_CENTER_IMUX38_5", - "CFG_CENTER_IMUX38_6", - "CFG_CENTER_IMUX38_7", - "CFG_CENTER_IMUX38_8", - "CFG_CENTER_IMUX38_9", - "CFG_CENTER_IMUX39_0", - "CFG_CENTER_IMUX39_1", - "CFG_CENTER_IMUX39_2", - "CFG_CENTER_IMUX39_3", - "CFG_CENTER_IMUX39_4", - "CFG_CENTER_IMUX39_5", - "CFG_CENTER_IMUX39_6", - "CFG_CENTER_IMUX39_7", - "CFG_CENTER_IMUX39_8", - "CFG_CENTER_IMUX39_9", - "CFG_CENTER_IMUX3_0", - "CFG_CENTER_IMUX3_1", - "CFG_CENTER_IMUX3_2", - "CFG_CENTER_IMUX3_3", - "CFG_CENTER_IMUX3_4", - "CFG_CENTER_IMUX3_5", - "CFG_CENTER_IMUX3_6", - "CFG_CENTER_IMUX3_7", - "CFG_CENTER_IMUX3_8", - "CFG_CENTER_IMUX3_9", - "CFG_CENTER_IMUX40_0", - "CFG_CENTER_IMUX40_1", - "CFG_CENTER_IMUX40_2", - "CFG_CENTER_IMUX40_3", - "CFG_CENTER_IMUX40_4", - "CFG_CENTER_IMUX40_5", - "CFG_CENTER_IMUX40_6", - "CFG_CENTER_IMUX40_7", - "CFG_CENTER_IMUX40_8", - "CFG_CENTER_IMUX40_9", - "CFG_CENTER_IMUX41_0", - "CFG_CENTER_IMUX41_1", - "CFG_CENTER_IMUX41_2", - "CFG_CENTER_IMUX41_3", - "CFG_CENTER_IMUX41_4", - "CFG_CENTER_IMUX41_5", - "CFG_CENTER_IMUX41_6", - "CFG_CENTER_IMUX41_7", - "CFG_CENTER_IMUX41_8", - "CFG_CENTER_IMUX41_9", - "CFG_CENTER_IMUX42_0", - "CFG_CENTER_IMUX42_1", - "CFG_CENTER_IMUX42_2", - "CFG_CENTER_IMUX42_3", - "CFG_CENTER_IMUX42_4", - "CFG_CENTER_IMUX42_5", - "CFG_CENTER_IMUX42_6", - "CFG_CENTER_IMUX42_7", - "CFG_CENTER_IMUX42_8", - "CFG_CENTER_IMUX42_9", - "CFG_CENTER_IMUX43_0", - "CFG_CENTER_IMUX43_1", - "CFG_CENTER_IMUX43_2", - "CFG_CENTER_IMUX43_3", - "CFG_CENTER_IMUX43_4", - "CFG_CENTER_IMUX43_5", - "CFG_CENTER_IMUX43_6", - "CFG_CENTER_IMUX43_7", - "CFG_CENTER_IMUX43_8", - "CFG_CENTER_IMUX43_9", - "CFG_CENTER_IMUX44_0", - "CFG_CENTER_IMUX44_1", - "CFG_CENTER_IMUX44_2", - "CFG_CENTER_IMUX44_3", - "CFG_CENTER_IMUX44_4", - "CFG_CENTER_IMUX44_5", - "CFG_CENTER_IMUX44_6", - "CFG_CENTER_IMUX44_7", - "CFG_CENTER_IMUX44_8", - "CFG_CENTER_IMUX44_9", - "CFG_CENTER_IMUX45_0", - "CFG_CENTER_IMUX45_1", - "CFG_CENTER_IMUX45_2", - "CFG_CENTER_IMUX45_3", - "CFG_CENTER_IMUX45_4", - "CFG_CENTER_IMUX45_5", - "CFG_CENTER_IMUX45_6", - "CFG_CENTER_IMUX45_7", - "CFG_CENTER_IMUX45_8", - "CFG_CENTER_IMUX45_9", - "CFG_CENTER_IMUX46_0", - "CFG_CENTER_IMUX46_1", - "CFG_CENTER_IMUX46_2", - "CFG_CENTER_IMUX46_3", - "CFG_CENTER_IMUX46_4", - "CFG_CENTER_IMUX46_5", - "CFG_CENTER_IMUX46_6", - "CFG_CENTER_IMUX46_7", - "CFG_CENTER_IMUX46_8", - "CFG_CENTER_IMUX46_9", - "CFG_CENTER_IMUX47_0", - "CFG_CENTER_IMUX47_1", - "CFG_CENTER_IMUX47_2", - "CFG_CENTER_IMUX47_3", - "CFG_CENTER_IMUX47_4", - "CFG_CENTER_IMUX47_5", - "CFG_CENTER_IMUX47_6", - "CFG_CENTER_IMUX47_7", - "CFG_CENTER_IMUX47_8", - "CFG_CENTER_IMUX47_9", - "CFG_CENTER_IMUX4_0", - "CFG_CENTER_IMUX4_1", - "CFG_CENTER_IMUX4_2", - "CFG_CENTER_IMUX4_3", - "CFG_CENTER_IMUX4_4", - "CFG_CENTER_IMUX4_5", - "CFG_CENTER_IMUX4_6", - "CFG_CENTER_IMUX4_7", - "CFG_CENTER_IMUX4_8", - "CFG_CENTER_IMUX4_9", - "CFG_CENTER_IMUX5_0", - "CFG_CENTER_IMUX5_1", - "CFG_CENTER_IMUX5_2", - "CFG_CENTER_IMUX5_3", - "CFG_CENTER_IMUX5_4", - "CFG_CENTER_IMUX5_5", - "CFG_CENTER_IMUX5_6", - "CFG_CENTER_IMUX5_7", - "CFG_CENTER_IMUX5_8", - "CFG_CENTER_IMUX5_9", - "CFG_CENTER_IMUX6_0", - "CFG_CENTER_IMUX6_1", - "CFG_CENTER_IMUX6_2", - "CFG_CENTER_IMUX6_3", - "CFG_CENTER_IMUX6_4", - "CFG_CENTER_IMUX6_5", - "CFG_CENTER_IMUX6_6", - "CFG_CENTER_IMUX6_7", - "CFG_CENTER_IMUX6_8", - "CFG_CENTER_IMUX6_9", - "CFG_CENTER_IMUX7_0", - "CFG_CENTER_IMUX7_1", - "CFG_CENTER_IMUX7_2", - "CFG_CENTER_IMUX7_3", - "CFG_CENTER_IMUX7_4", - "CFG_CENTER_IMUX7_5", - "CFG_CENTER_IMUX7_6", - "CFG_CENTER_IMUX7_7", - "CFG_CENTER_IMUX7_8", - "CFG_CENTER_IMUX7_9", - "CFG_CENTER_IMUX8_0", - "CFG_CENTER_IMUX8_1", - "CFG_CENTER_IMUX8_2", - "CFG_CENTER_IMUX8_3", - "CFG_CENTER_IMUX8_4", - "CFG_CENTER_IMUX8_5", - "CFG_CENTER_IMUX8_6", - "CFG_CENTER_IMUX8_7", - "CFG_CENTER_IMUX8_8", - "CFG_CENTER_IMUX8_9", - "CFG_CENTER_IMUX9_0", - "CFG_CENTER_IMUX9_1", - "CFG_CENTER_IMUX9_2", - "CFG_CENTER_IMUX9_3", - "CFG_CENTER_IMUX9_4", - "CFG_CENTER_IMUX9_5", - "CFG_CENTER_IMUX9_6", - "CFG_CENTER_IMUX9_7", - "CFG_CENTER_IMUX9_8", - "CFG_CENTER_IMUX9_9", - "CFG_CENTER_LH10_0", - "CFG_CENTER_LH10_1", - "CFG_CENTER_LH10_2", - "CFG_CENTER_LH10_3", - "CFG_CENTER_LH10_4", - "CFG_CENTER_LH10_5", - "CFG_CENTER_LH10_6", - "CFG_CENTER_LH10_7", - "CFG_CENTER_LH10_8", - "CFG_CENTER_LH10_9", - "CFG_CENTER_LH11_0", - "CFG_CENTER_LH11_1", - "CFG_CENTER_LH11_2", - "CFG_CENTER_LH11_3", - "CFG_CENTER_LH11_4", - "CFG_CENTER_LH11_5", - "CFG_CENTER_LH11_6", - "CFG_CENTER_LH11_7", - "CFG_CENTER_LH11_8", - "CFG_CENTER_LH11_9", - "CFG_CENTER_LH12_0", - "CFG_CENTER_LH12_1", - "CFG_CENTER_LH12_2", - "CFG_CENTER_LH12_3", - "CFG_CENTER_LH12_4", - "CFG_CENTER_LH12_5", - "CFG_CENTER_LH12_6", - "CFG_CENTER_LH12_7", - "CFG_CENTER_LH12_8", - "CFG_CENTER_LH12_9", - "CFG_CENTER_LH1_0", - "CFG_CENTER_LH1_1", - "CFG_CENTER_LH1_2", - "CFG_CENTER_LH1_3", - "CFG_CENTER_LH1_4", - "CFG_CENTER_LH1_5", - "CFG_CENTER_LH1_6", - "CFG_CENTER_LH1_7", - "CFG_CENTER_LH1_8", - "CFG_CENTER_LH1_9", - "CFG_CENTER_LH2_0", - "CFG_CENTER_LH2_1", - "CFG_CENTER_LH2_2", - "CFG_CENTER_LH2_3", - "CFG_CENTER_LH2_4", - "CFG_CENTER_LH2_5", - "CFG_CENTER_LH2_6", - "CFG_CENTER_LH2_7", - "CFG_CENTER_LH2_8", - "CFG_CENTER_LH2_9", - "CFG_CENTER_LH3_0", - "CFG_CENTER_LH3_1", - "CFG_CENTER_LH3_2", - "CFG_CENTER_LH3_3", - "CFG_CENTER_LH3_4", - "CFG_CENTER_LH3_5", - "CFG_CENTER_LH3_6", - "CFG_CENTER_LH3_7", - "CFG_CENTER_LH3_8", - "CFG_CENTER_LH3_9", - "CFG_CENTER_LH4_0", - "CFG_CENTER_LH4_1", - "CFG_CENTER_LH4_2", - "CFG_CENTER_LH4_3", - "CFG_CENTER_LH4_4", - "CFG_CENTER_LH4_5", - "CFG_CENTER_LH4_6", - "CFG_CENTER_LH4_7", - "CFG_CENTER_LH4_8", - "CFG_CENTER_LH4_9", - "CFG_CENTER_LH5_0", - "CFG_CENTER_LH5_1", - "CFG_CENTER_LH5_2", - "CFG_CENTER_LH5_3", - "CFG_CENTER_LH5_4", - "CFG_CENTER_LH5_5", - "CFG_CENTER_LH5_6", - "CFG_CENTER_LH5_7", - "CFG_CENTER_LH5_8", - "CFG_CENTER_LH5_9", - "CFG_CENTER_LH6_0", - "CFG_CENTER_LH6_1", - "CFG_CENTER_LH6_2", - "CFG_CENTER_LH6_3", - "CFG_CENTER_LH6_4", - "CFG_CENTER_LH6_5", - "CFG_CENTER_LH6_6", - "CFG_CENTER_LH6_7", - "CFG_CENTER_LH6_8", - "CFG_CENTER_LH6_9", - "CFG_CENTER_LH7_0", - "CFG_CENTER_LH7_1", - "CFG_CENTER_LH7_2", - "CFG_CENTER_LH7_3", - "CFG_CENTER_LH7_4", - "CFG_CENTER_LH7_5", - "CFG_CENTER_LH7_6", - "CFG_CENTER_LH7_7", - "CFG_CENTER_LH7_8", - "CFG_CENTER_LH7_9", - "CFG_CENTER_LH8_0", - "CFG_CENTER_LH8_1", - "CFG_CENTER_LH8_2", - "CFG_CENTER_LH8_3", - "CFG_CENTER_LH8_4", - "CFG_CENTER_LH8_5", - "CFG_CENTER_LH8_6", - "CFG_CENTER_LH8_7", - "CFG_CENTER_LH8_8", - "CFG_CENTER_LH8_9", - "CFG_CENTER_LH9_0", - "CFG_CENTER_LH9_1", - "CFG_CENTER_LH9_2", - "CFG_CENTER_LH9_3", - "CFG_CENTER_LH9_4", - "CFG_CENTER_LH9_5", - "CFG_CENTER_LH9_6", - "CFG_CENTER_LH9_7", - "CFG_CENTER_LH9_8", - "CFG_CENTER_LH9_9", - "CFG_CENTER_LOGIC_OUTS_B0_0", - "CFG_CENTER_LOGIC_OUTS_B0_1", - "CFG_CENTER_LOGIC_OUTS_B0_2", - "CFG_CENTER_LOGIC_OUTS_B0_3", - "CFG_CENTER_LOGIC_OUTS_B0_4", - "CFG_CENTER_LOGIC_OUTS_B0_5", - "CFG_CENTER_LOGIC_OUTS_B0_6", - "CFG_CENTER_LOGIC_OUTS_B0_7", - "CFG_CENTER_LOGIC_OUTS_B0_8", - "CFG_CENTER_LOGIC_OUTS_B0_9", - "CFG_CENTER_LOGIC_OUTS_B10_0", - "CFG_CENTER_LOGIC_OUTS_B10_1", - "CFG_CENTER_LOGIC_OUTS_B10_2", - "CFG_CENTER_LOGIC_OUTS_B10_3", - "CFG_CENTER_LOGIC_OUTS_B10_4", - "CFG_CENTER_LOGIC_OUTS_B10_5", - "CFG_CENTER_LOGIC_OUTS_B10_6", - "CFG_CENTER_LOGIC_OUTS_B10_7", - "CFG_CENTER_LOGIC_OUTS_B10_8", - "CFG_CENTER_LOGIC_OUTS_B10_9", - "CFG_CENTER_LOGIC_OUTS_B11_0", - "CFG_CENTER_LOGIC_OUTS_B11_1", - "CFG_CENTER_LOGIC_OUTS_B11_2", - "CFG_CENTER_LOGIC_OUTS_B11_3", - "CFG_CENTER_LOGIC_OUTS_B11_4", - "CFG_CENTER_LOGIC_OUTS_B11_5", - "CFG_CENTER_LOGIC_OUTS_B11_6", - "CFG_CENTER_LOGIC_OUTS_B11_7", - "CFG_CENTER_LOGIC_OUTS_B11_8", - "CFG_CENTER_LOGIC_OUTS_B11_9", - "CFG_CENTER_LOGIC_OUTS_B12_0", - "CFG_CENTER_LOGIC_OUTS_B12_1", - "CFG_CENTER_LOGIC_OUTS_B12_2", - "CFG_CENTER_LOGIC_OUTS_B12_3", - "CFG_CENTER_LOGIC_OUTS_B12_4", - "CFG_CENTER_LOGIC_OUTS_B12_5", - "CFG_CENTER_LOGIC_OUTS_B12_6", - "CFG_CENTER_LOGIC_OUTS_B12_7", - "CFG_CENTER_LOGIC_OUTS_B12_8", - "CFG_CENTER_LOGIC_OUTS_B12_9", - "CFG_CENTER_LOGIC_OUTS_B13_0", - "CFG_CENTER_LOGIC_OUTS_B13_1", - "CFG_CENTER_LOGIC_OUTS_B13_2", - "CFG_CENTER_LOGIC_OUTS_B13_3", - "CFG_CENTER_LOGIC_OUTS_B13_4", - "CFG_CENTER_LOGIC_OUTS_B13_5", - "CFG_CENTER_LOGIC_OUTS_B13_6", - "CFG_CENTER_LOGIC_OUTS_B13_7", - "CFG_CENTER_LOGIC_OUTS_B13_8", - "CFG_CENTER_LOGIC_OUTS_B13_9", - "CFG_CENTER_LOGIC_OUTS_B14_0", - "CFG_CENTER_LOGIC_OUTS_B14_1", - "CFG_CENTER_LOGIC_OUTS_B14_2", - "CFG_CENTER_LOGIC_OUTS_B14_3", - "CFG_CENTER_LOGIC_OUTS_B14_4", - "CFG_CENTER_LOGIC_OUTS_B14_5", - "CFG_CENTER_LOGIC_OUTS_B14_6", - "CFG_CENTER_LOGIC_OUTS_B14_7", - "CFG_CENTER_LOGIC_OUTS_B14_8", - "CFG_CENTER_LOGIC_OUTS_B14_9", - "CFG_CENTER_LOGIC_OUTS_B15_0", - "CFG_CENTER_LOGIC_OUTS_B15_1", - "CFG_CENTER_LOGIC_OUTS_B15_2", - "CFG_CENTER_LOGIC_OUTS_B15_3", - "CFG_CENTER_LOGIC_OUTS_B15_4", - "CFG_CENTER_LOGIC_OUTS_B15_5", - "CFG_CENTER_LOGIC_OUTS_B15_6", - "CFG_CENTER_LOGIC_OUTS_B15_7", - "CFG_CENTER_LOGIC_OUTS_B15_8", - "CFG_CENTER_LOGIC_OUTS_B15_9", - "CFG_CENTER_LOGIC_OUTS_B16_0", - "CFG_CENTER_LOGIC_OUTS_B16_1", - "CFG_CENTER_LOGIC_OUTS_B16_2", - "CFG_CENTER_LOGIC_OUTS_B16_3", - "CFG_CENTER_LOGIC_OUTS_B16_4", - "CFG_CENTER_LOGIC_OUTS_B16_5", - "CFG_CENTER_LOGIC_OUTS_B16_6", - "CFG_CENTER_LOGIC_OUTS_B16_7", - "CFG_CENTER_LOGIC_OUTS_B16_8", - "CFG_CENTER_LOGIC_OUTS_B16_9", - "CFG_CENTER_LOGIC_OUTS_B17_0", - "CFG_CENTER_LOGIC_OUTS_B17_1", - "CFG_CENTER_LOGIC_OUTS_B17_2", - "CFG_CENTER_LOGIC_OUTS_B17_3", - "CFG_CENTER_LOGIC_OUTS_B17_4", - "CFG_CENTER_LOGIC_OUTS_B17_5", - "CFG_CENTER_LOGIC_OUTS_B17_6", - "CFG_CENTER_LOGIC_OUTS_B17_7", - "CFG_CENTER_LOGIC_OUTS_B17_8", - "CFG_CENTER_LOGIC_OUTS_B17_9", - "CFG_CENTER_LOGIC_OUTS_B18_0", - "CFG_CENTER_LOGIC_OUTS_B18_1", - "CFG_CENTER_LOGIC_OUTS_B18_2", - "CFG_CENTER_LOGIC_OUTS_B18_3", - "CFG_CENTER_LOGIC_OUTS_B18_4", - "CFG_CENTER_LOGIC_OUTS_B18_5", - "CFG_CENTER_LOGIC_OUTS_B18_6", - "CFG_CENTER_LOGIC_OUTS_B18_7", - "CFG_CENTER_LOGIC_OUTS_B18_8", - "CFG_CENTER_LOGIC_OUTS_B18_9", - "CFG_CENTER_LOGIC_OUTS_B19_0", - "CFG_CENTER_LOGIC_OUTS_B19_1", - "CFG_CENTER_LOGIC_OUTS_B19_2", - "CFG_CENTER_LOGIC_OUTS_B19_3", - "CFG_CENTER_LOGIC_OUTS_B19_4", - "CFG_CENTER_LOGIC_OUTS_B19_5", - "CFG_CENTER_LOGIC_OUTS_B19_6", - "CFG_CENTER_LOGIC_OUTS_B19_7", - "CFG_CENTER_LOGIC_OUTS_B19_8", - "CFG_CENTER_LOGIC_OUTS_B19_9", - "CFG_CENTER_LOGIC_OUTS_B1_0", - "CFG_CENTER_LOGIC_OUTS_B1_1", - "CFG_CENTER_LOGIC_OUTS_B1_2", - "CFG_CENTER_LOGIC_OUTS_B1_3", - "CFG_CENTER_LOGIC_OUTS_B1_4", - "CFG_CENTER_LOGIC_OUTS_B1_5", - "CFG_CENTER_LOGIC_OUTS_B1_6", - "CFG_CENTER_LOGIC_OUTS_B1_7", - "CFG_CENTER_LOGIC_OUTS_B1_8", - "CFG_CENTER_LOGIC_OUTS_B1_9", - "CFG_CENTER_LOGIC_OUTS_B20_0", - "CFG_CENTER_LOGIC_OUTS_B20_1", - "CFG_CENTER_LOGIC_OUTS_B20_2", - "CFG_CENTER_LOGIC_OUTS_B20_3", - "CFG_CENTER_LOGIC_OUTS_B20_4", - "CFG_CENTER_LOGIC_OUTS_B20_5", - "CFG_CENTER_LOGIC_OUTS_B20_6", - "CFG_CENTER_LOGIC_OUTS_B20_7", - "CFG_CENTER_LOGIC_OUTS_B20_8", - "CFG_CENTER_LOGIC_OUTS_B20_9", - "CFG_CENTER_LOGIC_OUTS_B21_0", - "CFG_CENTER_LOGIC_OUTS_B21_1", - "CFG_CENTER_LOGIC_OUTS_B21_2", - "CFG_CENTER_LOGIC_OUTS_B21_3", - "CFG_CENTER_LOGIC_OUTS_B21_4", - "CFG_CENTER_LOGIC_OUTS_B21_5", - "CFG_CENTER_LOGIC_OUTS_B21_6", - "CFG_CENTER_LOGIC_OUTS_B21_7", - "CFG_CENTER_LOGIC_OUTS_B21_8", - "CFG_CENTER_LOGIC_OUTS_B21_9", - "CFG_CENTER_LOGIC_OUTS_B22_0", - "CFG_CENTER_LOGIC_OUTS_B22_1", - "CFG_CENTER_LOGIC_OUTS_B22_2", - "CFG_CENTER_LOGIC_OUTS_B22_3", - "CFG_CENTER_LOGIC_OUTS_B22_4", - "CFG_CENTER_LOGIC_OUTS_B22_5", - "CFG_CENTER_LOGIC_OUTS_B22_6", - "CFG_CENTER_LOGIC_OUTS_B22_7", - "CFG_CENTER_LOGIC_OUTS_B22_8", - "CFG_CENTER_LOGIC_OUTS_B22_9", - "CFG_CENTER_LOGIC_OUTS_B23_0", - "CFG_CENTER_LOGIC_OUTS_B23_1", - "CFG_CENTER_LOGIC_OUTS_B23_2", - "CFG_CENTER_LOGIC_OUTS_B23_3", - "CFG_CENTER_LOGIC_OUTS_B23_4", - "CFG_CENTER_LOGIC_OUTS_B23_5", - "CFG_CENTER_LOGIC_OUTS_B23_6", - "CFG_CENTER_LOGIC_OUTS_B23_7", - "CFG_CENTER_LOGIC_OUTS_B23_8", - "CFG_CENTER_LOGIC_OUTS_B23_9", - "CFG_CENTER_LOGIC_OUTS_B2_0", - "CFG_CENTER_LOGIC_OUTS_B2_1", - "CFG_CENTER_LOGIC_OUTS_B2_2", - "CFG_CENTER_LOGIC_OUTS_B2_3", - "CFG_CENTER_LOGIC_OUTS_B2_4", - "CFG_CENTER_LOGIC_OUTS_B2_5", - "CFG_CENTER_LOGIC_OUTS_B2_6", - "CFG_CENTER_LOGIC_OUTS_B2_7", - "CFG_CENTER_LOGIC_OUTS_B2_8", - "CFG_CENTER_LOGIC_OUTS_B2_9", - "CFG_CENTER_LOGIC_OUTS_B3_0", - "CFG_CENTER_LOGIC_OUTS_B3_1", - "CFG_CENTER_LOGIC_OUTS_B3_2", - "CFG_CENTER_LOGIC_OUTS_B3_3", - "CFG_CENTER_LOGIC_OUTS_B3_4", - "CFG_CENTER_LOGIC_OUTS_B3_5", - "CFG_CENTER_LOGIC_OUTS_B3_6", - "CFG_CENTER_LOGIC_OUTS_B3_7", - "CFG_CENTER_LOGIC_OUTS_B3_8", - "CFG_CENTER_LOGIC_OUTS_B3_9", - "CFG_CENTER_LOGIC_OUTS_B4_0", - "CFG_CENTER_LOGIC_OUTS_B4_1", - "CFG_CENTER_LOGIC_OUTS_B4_2", - "CFG_CENTER_LOGIC_OUTS_B4_3", - "CFG_CENTER_LOGIC_OUTS_B4_4", - "CFG_CENTER_LOGIC_OUTS_B4_5", - "CFG_CENTER_LOGIC_OUTS_B4_6", - "CFG_CENTER_LOGIC_OUTS_B4_7", - "CFG_CENTER_LOGIC_OUTS_B4_8", - "CFG_CENTER_LOGIC_OUTS_B4_9", - "CFG_CENTER_LOGIC_OUTS_B5_0", - "CFG_CENTER_LOGIC_OUTS_B5_1", - "CFG_CENTER_LOGIC_OUTS_B5_2", - "CFG_CENTER_LOGIC_OUTS_B5_3", - "CFG_CENTER_LOGIC_OUTS_B5_4", - "CFG_CENTER_LOGIC_OUTS_B5_5", - "CFG_CENTER_LOGIC_OUTS_B5_6", - "CFG_CENTER_LOGIC_OUTS_B5_7", - "CFG_CENTER_LOGIC_OUTS_B5_8", - "CFG_CENTER_LOGIC_OUTS_B5_9", - "CFG_CENTER_LOGIC_OUTS_B6_0", - "CFG_CENTER_LOGIC_OUTS_B6_1", - "CFG_CENTER_LOGIC_OUTS_B6_2", - "CFG_CENTER_LOGIC_OUTS_B6_3", - "CFG_CENTER_LOGIC_OUTS_B6_4", - "CFG_CENTER_LOGIC_OUTS_B6_5", - "CFG_CENTER_LOGIC_OUTS_B6_6", - "CFG_CENTER_LOGIC_OUTS_B6_7", - "CFG_CENTER_LOGIC_OUTS_B6_8", - "CFG_CENTER_LOGIC_OUTS_B6_9", - "CFG_CENTER_LOGIC_OUTS_B7_0", - "CFG_CENTER_LOGIC_OUTS_B7_1", - "CFG_CENTER_LOGIC_OUTS_B7_2", - "CFG_CENTER_LOGIC_OUTS_B7_3", - "CFG_CENTER_LOGIC_OUTS_B7_4", - "CFG_CENTER_LOGIC_OUTS_B7_5", - "CFG_CENTER_LOGIC_OUTS_B7_6", - "CFG_CENTER_LOGIC_OUTS_B7_7", - "CFG_CENTER_LOGIC_OUTS_B7_8", - "CFG_CENTER_LOGIC_OUTS_B7_9", - "CFG_CENTER_LOGIC_OUTS_B8_0", - "CFG_CENTER_LOGIC_OUTS_B8_1", - "CFG_CENTER_LOGIC_OUTS_B8_2", - "CFG_CENTER_LOGIC_OUTS_B8_3", - "CFG_CENTER_LOGIC_OUTS_B8_4", - "CFG_CENTER_LOGIC_OUTS_B8_5", - "CFG_CENTER_LOGIC_OUTS_B8_6", - "CFG_CENTER_LOGIC_OUTS_B8_7", - "CFG_CENTER_LOGIC_OUTS_B8_8", - "CFG_CENTER_LOGIC_OUTS_B8_9", - "CFG_CENTER_LOGIC_OUTS_B9_0", - "CFG_CENTER_LOGIC_OUTS_B9_1", - "CFG_CENTER_LOGIC_OUTS_B9_2", - "CFG_CENTER_LOGIC_OUTS_B9_3", - "CFG_CENTER_LOGIC_OUTS_B9_4", - "CFG_CENTER_LOGIC_OUTS_B9_5", - "CFG_CENTER_LOGIC_OUTS_B9_6", - "CFG_CENTER_LOGIC_OUTS_B9_7", - "CFG_CENTER_LOGIC_OUTS_B9_8", - "CFG_CENTER_LOGIC_OUTS_B9_9", - "CFG_CENTER_NE2A0_0", - "CFG_CENTER_NE2A0_1", - "CFG_CENTER_NE2A0_2", - "CFG_CENTER_NE2A0_3", - "CFG_CENTER_NE2A0_4", - "CFG_CENTER_NE2A0_5", - "CFG_CENTER_NE2A0_6", - "CFG_CENTER_NE2A0_7", - "CFG_CENTER_NE2A0_8", - "CFG_CENTER_NE2A0_9", - "CFG_CENTER_NE2A1_0", - "CFG_CENTER_NE2A1_1", - "CFG_CENTER_NE2A1_2", - "CFG_CENTER_NE2A1_3", - "CFG_CENTER_NE2A1_4", - "CFG_CENTER_NE2A1_5", - "CFG_CENTER_NE2A1_6", - "CFG_CENTER_NE2A1_7", - "CFG_CENTER_NE2A1_8", - "CFG_CENTER_NE2A1_9", - "CFG_CENTER_NE2A2_0", - "CFG_CENTER_NE2A2_1", - "CFG_CENTER_NE2A2_2", - "CFG_CENTER_NE2A2_3", - "CFG_CENTER_NE2A2_4", - "CFG_CENTER_NE2A2_5", - "CFG_CENTER_NE2A2_6", - "CFG_CENTER_NE2A2_7", - "CFG_CENTER_NE2A2_8", - "CFG_CENTER_NE2A2_9", - "CFG_CENTER_NE2A3_0", - "CFG_CENTER_NE2A3_1", - "CFG_CENTER_NE2A3_2", - "CFG_CENTER_NE2A3_3", - "CFG_CENTER_NE2A3_4", - "CFG_CENTER_NE2A3_5", - "CFG_CENTER_NE2A3_6", - "CFG_CENTER_NE2A3_7", - "CFG_CENTER_NE2A3_8", - "CFG_CENTER_NE2A3_9", - "CFG_CENTER_NE4BEG0_0", - "CFG_CENTER_NE4BEG0_1", - "CFG_CENTER_NE4BEG0_2", - "CFG_CENTER_NE4BEG0_3", - "CFG_CENTER_NE4BEG0_4", - "CFG_CENTER_NE4BEG0_5", - "CFG_CENTER_NE4BEG0_6", - "CFG_CENTER_NE4BEG0_7", - "CFG_CENTER_NE4BEG0_8", - "CFG_CENTER_NE4BEG0_9", - "CFG_CENTER_NE4BEG1_0", - "CFG_CENTER_NE4BEG1_1", - "CFG_CENTER_NE4BEG1_2", - "CFG_CENTER_NE4BEG1_3", - "CFG_CENTER_NE4BEG1_4", - "CFG_CENTER_NE4BEG1_5", - "CFG_CENTER_NE4BEG1_6", - "CFG_CENTER_NE4BEG1_7", - "CFG_CENTER_NE4BEG1_8", - "CFG_CENTER_NE4BEG1_9", - "CFG_CENTER_NE4BEG2_0", - "CFG_CENTER_NE4BEG2_1", - "CFG_CENTER_NE4BEG2_2", - "CFG_CENTER_NE4BEG2_3", - "CFG_CENTER_NE4BEG2_4", - "CFG_CENTER_NE4BEG2_5", - "CFG_CENTER_NE4BEG2_6", - "CFG_CENTER_NE4BEG2_7", - "CFG_CENTER_NE4BEG2_8", - "CFG_CENTER_NE4BEG2_9", - "CFG_CENTER_NE4BEG3_0", - "CFG_CENTER_NE4BEG3_1", - "CFG_CENTER_NE4BEG3_2", - "CFG_CENTER_NE4BEG3_3", - "CFG_CENTER_NE4BEG3_4", - "CFG_CENTER_NE4BEG3_5", - "CFG_CENTER_NE4BEG3_6", - "CFG_CENTER_NE4BEG3_7", - "CFG_CENTER_NE4BEG3_8", - "CFG_CENTER_NE4BEG3_9", - "CFG_CENTER_NE4C0_0", - "CFG_CENTER_NE4C0_1", - "CFG_CENTER_NE4C0_2", - "CFG_CENTER_NE4C0_3", - "CFG_CENTER_NE4C0_4", - "CFG_CENTER_NE4C0_5", - "CFG_CENTER_NE4C0_6", - "CFG_CENTER_NE4C0_7", - "CFG_CENTER_NE4C0_8", - "CFG_CENTER_NE4C0_9", - "CFG_CENTER_NE4C1_0", - "CFG_CENTER_NE4C1_1", - "CFG_CENTER_NE4C1_2", - "CFG_CENTER_NE4C1_3", - "CFG_CENTER_NE4C1_4", - "CFG_CENTER_NE4C1_5", - "CFG_CENTER_NE4C1_6", - "CFG_CENTER_NE4C1_7", - "CFG_CENTER_NE4C1_8", - "CFG_CENTER_NE4C1_9", - "CFG_CENTER_NE4C2_0", - "CFG_CENTER_NE4C2_1", - "CFG_CENTER_NE4C2_2", - "CFG_CENTER_NE4C2_3", - "CFG_CENTER_NE4C2_4", - "CFG_CENTER_NE4C2_5", - "CFG_CENTER_NE4C2_6", - "CFG_CENTER_NE4C2_7", - "CFG_CENTER_NE4C2_8", - "CFG_CENTER_NE4C2_9", - "CFG_CENTER_NE4C3_0", - "CFG_CENTER_NE4C3_1", - "CFG_CENTER_NE4C3_2", - "CFG_CENTER_NE4C3_3", - "CFG_CENTER_NE4C3_4", - "CFG_CENTER_NE4C3_5", - "CFG_CENTER_NE4C3_6", - "CFG_CENTER_NE4C3_7", - "CFG_CENTER_NE4C3_8", - "CFG_CENTER_NE4C3_9", - "CFG_CENTER_NW2A0_0", - "CFG_CENTER_NW2A0_1", - "CFG_CENTER_NW2A0_2", - "CFG_CENTER_NW2A0_3", - "CFG_CENTER_NW2A0_4", - "CFG_CENTER_NW2A0_5", - "CFG_CENTER_NW2A0_6", - "CFG_CENTER_NW2A0_7", - "CFG_CENTER_NW2A0_8", - "CFG_CENTER_NW2A0_9", - "CFG_CENTER_NW2A1_0", - "CFG_CENTER_NW2A1_1", - "CFG_CENTER_NW2A1_2", - "CFG_CENTER_NW2A1_3", - "CFG_CENTER_NW2A1_4", - "CFG_CENTER_NW2A1_5", - "CFG_CENTER_NW2A1_6", - "CFG_CENTER_NW2A1_7", - "CFG_CENTER_NW2A1_8", - "CFG_CENTER_NW2A1_9", - "CFG_CENTER_NW2A2_0", - "CFG_CENTER_NW2A2_1", - "CFG_CENTER_NW2A2_2", - "CFG_CENTER_NW2A2_3", - "CFG_CENTER_NW2A2_4", - "CFG_CENTER_NW2A2_5", - "CFG_CENTER_NW2A2_6", - "CFG_CENTER_NW2A2_7", - "CFG_CENTER_NW2A2_8", - "CFG_CENTER_NW2A2_9", - "CFG_CENTER_NW2A3_0", - "CFG_CENTER_NW2A3_1", - "CFG_CENTER_NW2A3_2", - "CFG_CENTER_NW2A3_3", - "CFG_CENTER_NW2A3_4", - "CFG_CENTER_NW2A3_5", - "CFG_CENTER_NW2A3_6", - "CFG_CENTER_NW2A3_7", - "CFG_CENTER_NW2A3_8", - "CFG_CENTER_NW2A3_9", - "CFG_CENTER_NW4A0_0", - "CFG_CENTER_NW4A0_1", - "CFG_CENTER_NW4A0_2", - "CFG_CENTER_NW4A0_3", - "CFG_CENTER_NW4A0_4", - "CFG_CENTER_NW4A0_5", - "CFG_CENTER_NW4A0_6", - "CFG_CENTER_NW4A0_7", - "CFG_CENTER_NW4A0_8", - "CFG_CENTER_NW4A0_9", - "CFG_CENTER_NW4A1_0", - "CFG_CENTER_NW4A1_1", - "CFG_CENTER_NW4A1_2", - "CFG_CENTER_NW4A1_3", - "CFG_CENTER_NW4A1_4", - "CFG_CENTER_NW4A1_5", - "CFG_CENTER_NW4A1_6", - "CFG_CENTER_NW4A1_7", - "CFG_CENTER_NW4A1_8", - "CFG_CENTER_NW4A1_9", - "CFG_CENTER_NW4A2_0", - "CFG_CENTER_NW4A2_1", - "CFG_CENTER_NW4A2_2", - "CFG_CENTER_NW4A2_3", - "CFG_CENTER_NW4A2_4", - "CFG_CENTER_NW4A2_5", - "CFG_CENTER_NW4A2_6", - "CFG_CENTER_NW4A2_7", - "CFG_CENTER_NW4A2_8", - "CFG_CENTER_NW4A2_9", - "CFG_CENTER_NW4A3_0", - "CFG_CENTER_NW4A3_1", - "CFG_CENTER_NW4A3_2", - "CFG_CENTER_NW4A3_3", - "CFG_CENTER_NW4A3_4", - "CFG_CENTER_NW4A3_5", - "CFG_CENTER_NW4A3_6", - "CFG_CENTER_NW4A3_7", - "CFG_CENTER_NW4A3_8", - "CFG_CENTER_NW4A3_9", - "CFG_CENTER_NW4END0_0", - "CFG_CENTER_NW4END0_1", - "CFG_CENTER_NW4END0_2", - "CFG_CENTER_NW4END0_3", - "CFG_CENTER_NW4END0_4", - "CFG_CENTER_NW4END0_5", - "CFG_CENTER_NW4END0_6", - "CFG_CENTER_NW4END0_7", - "CFG_CENTER_NW4END0_8", - "CFG_CENTER_NW4END0_9", - "CFG_CENTER_NW4END1_0", - "CFG_CENTER_NW4END1_1", - "CFG_CENTER_NW4END1_2", - "CFG_CENTER_NW4END1_3", - "CFG_CENTER_NW4END1_4", - "CFG_CENTER_NW4END1_5", - "CFG_CENTER_NW4END1_6", - "CFG_CENTER_NW4END1_7", - "CFG_CENTER_NW4END1_8", - "CFG_CENTER_NW4END1_9", - "CFG_CENTER_NW4END2_0", - "CFG_CENTER_NW4END2_1", - "CFG_CENTER_NW4END2_2", - "CFG_CENTER_NW4END2_3", - "CFG_CENTER_NW4END2_4", - "CFG_CENTER_NW4END2_5", - "CFG_CENTER_NW4END2_6", - "CFG_CENTER_NW4END2_7", - "CFG_CENTER_NW4END2_8", - "CFG_CENTER_NW4END2_9", - "CFG_CENTER_NW4END3_0", - "CFG_CENTER_NW4END3_1", - "CFG_CENTER_NW4END3_2", - "CFG_CENTER_NW4END3_3", - "CFG_CENTER_NW4END3_4", - "CFG_CENTER_NW4END3_5", - "CFG_CENTER_NW4END3_6", - "CFG_CENTER_NW4END3_7", - "CFG_CENTER_NW4END3_8", - "CFG_CENTER_NW4END3_9", - "CFG_CENTER_SE2A0_0", - "CFG_CENTER_SE2A0_1", - "CFG_CENTER_SE2A0_2", - "CFG_CENTER_SE2A0_3", - "CFG_CENTER_SE2A0_4", - "CFG_CENTER_SE2A0_5", - "CFG_CENTER_SE2A0_6", - "CFG_CENTER_SE2A0_7", - "CFG_CENTER_SE2A0_8", - "CFG_CENTER_SE2A0_9", - "CFG_CENTER_SE2A1_0", - "CFG_CENTER_SE2A1_1", - "CFG_CENTER_SE2A1_2", - "CFG_CENTER_SE2A1_3", - "CFG_CENTER_SE2A1_4", - "CFG_CENTER_SE2A1_5", - "CFG_CENTER_SE2A1_6", - "CFG_CENTER_SE2A1_7", - "CFG_CENTER_SE2A1_8", - "CFG_CENTER_SE2A1_9", - "CFG_CENTER_SE2A2_0", - "CFG_CENTER_SE2A2_1", - "CFG_CENTER_SE2A2_2", - "CFG_CENTER_SE2A2_3", - "CFG_CENTER_SE2A2_4", - "CFG_CENTER_SE2A2_5", - "CFG_CENTER_SE2A2_6", - "CFG_CENTER_SE2A2_7", - "CFG_CENTER_SE2A2_8", - "CFG_CENTER_SE2A2_9", - "CFG_CENTER_SE2A3_0", - "CFG_CENTER_SE2A3_1", - "CFG_CENTER_SE2A3_2", - "CFG_CENTER_SE2A3_3", - "CFG_CENTER_SE2A3_4", - "CFG_CENTER_SE2A3_5", - "CFG_CENTER_SE2A3_6", - "CFG_CENTER_SE2A3_7", - "CFG_CENTER_SE2A3_8", - "CFG_CENTER_SE2A3_9", - "CFG_CENTER_SE4BEG0_0", - "CFG_CENTER_SE4BEG0_1", - "CFG_CENTER_SE4BEG0_2", - "CFG_CENTER_SE4BEG0_3", - "CFG_CENTER_SE4BEG0_4", - "CFG_CENTER_SE4BEG0_5", - "CFG_CENTER_SE4BEG0_6", - "CFG_CENTER_SE4BEG0_7", - "CFG_CENTER_SE4BEG0_8", - "CFG_CENTER_SE4BEG0_9", - "CFG_CENTER_SE4BEG1_0", - "CFG_CENTER_SE4BEG1_1", - "CFG_CENTER_SE4BEG1_2", - "CFG_CENTER_SE4BEG1_3", - "CFG_CENTER_SE4BEG1_4", - "CFG_CENTER_SE4BEG1_5", - "CFG_CENTER_SE4BEG1_6", - "CFG_CENTER_SE4BEG1_7", - "CFG_CENTER_SE4BEG1_8", - "CFG_CENTER_SE4BEG1_9", - "CFG_CENTER_SE4BEG2_0", - "CFG_CENTER_SE4BEG2_1", - "CFG_CENTER_SE4BEG2_2", - "CFG_CENTER_SE4BEG2_3", - "CFG_CENTER_SE4BEG2_4", - "CFG_CENTER_SE4BEG2_5", - "CFG_CENTER_SE4BEG2_6", - "CFG_CENTER_SE4BEG2_7", - "CFG_CENTER_SE4BEG2_8", - "CFG_CENTER_SE4BEG2_9", - "CFG_CENTER_SE4BEG3_0", - "CFG_CENTER_SE4BEG3_1", - "CFG_CENTER_SE4BEG3_2", - "CFG_CENTER_SE4BEG3_3", - "CFG_CENTER_SE4BEG3_4", - "CFG_CENTER_SE4BEG3_5", - "CFG_CENTER_SE4BEG3_6", - "CFG_CENTER_SE4BEG3_7", - "CFG_CENTER_SE4BEG3_8", - "CFG_CENTER_SE4BEG3_9", - "CFG_CENTER_SE4C0_0", - "CFG_CENTER_SE4C0_1", - "CFG_CENTER_SE4C0_2", - "CFG_CENTER_SE4C0_3", - "CFG_CENTER_SE4C0_4", - "CFG_CENTER_SE4C0_5", - "CFG_CENTER_SE4C0_6", - "CFG_CENTER_SE4C0_7", - "CFG_CENTER_SE4C0_8", - "CFG_CENTER_SE4C0_9", - "CFG_CENTER_SE4C1_0", - "CFG_CENTER_SE4C1_1", - "CFG_CENTER_SE4C1_2", - "CFG_CENTER_SE4C1_3", - "CFG_CENTER_SE4C1_4", - "CFG_CENTER_SE4C1_5", - "CFG_CENTER_SE4C1_6", - "CFG_CENTER_SE4C1_7", - "CFG_CENTER_SE4C1_8", - "CFG_CENTER_SE4C1_9", - "CFG_CENTER_SE4C2_0", - "CFG_CENTER_SE4C2_1", - "CFG_CENTER_SE4C2_2", - "CFG_CENTER_SE4C2_3", - "CFG_CENTER_SE4C2_4", - "CFG_CENTER_SE4C2_5", - "CFG_CENTER_SE4C2_6", - "CFG_CENTER_SE4C2_7", - "CFG_CENTER_SE4C2_8", - "CFG_CENTER_SE4C2_9", - "CFG_CENTER_SE4C3_0", - "CFG_CENTER_SE4C3_1", - "CFG_CENTER_SE4C3_2", - "CFG_CENTER_SE4C3_3", - "CFG_CENTER_SE4C3_4", - "CFG_CENTER_SE4C3_5", - "CFG_CENTER_SE4C3_6", - "CFG_CENTER_SE4C3_7", - "CFG_CENTER_SE4C3_8", - "CFG_CENTER_SE4C3_9", - "CFG_CENTER_SW2A0_0", - "CFG_CENTER_SW2A0_1", - "CFG_CENTER_SW2A0_2", - "CFG_CENTER_SW2A0_3", - "CFG_CENTER_SW2A0_4", - "CFG_CENTER_SW2A0_5", - "CFG_CENTER_SW2A0_6", - "CFG_CENTER_SW2A0_7", - "CFG_CENTER_SW2A0_8", - "CFG_CENTER_SW2A0_9", - "CFG_CENTER_SW2A1_0", - "CFG_CENTER_SW2A1_1", - "CFG_CENTER_SW2A1_2", - "CFG_CENTER_SW2A1_3", - "CFG_CENTER_SW2A1_4", - "CFG_CENTER_SW2A1_5", - "CFG_CENTER_SW2A1_6", - "CFG_CENTER_SW2A1_7", - "CFG_CENTER_SW2A1_8", - "CFG_CENTER_SW2A1_9", - "CFG_CENTER_SW2A2_0", - "CFG_CENTER_SW2A2_1", - "CFG_CENTER_SW2A2_2", - "CFG_CENTER_SW2A2_3", - "CFG_CENTER_SW2A2_4", - "CFG_CENTER_SW2A2_5", - "CFG_CENTER_SW2A2_6", - "CFG_CENTER_SW2A2_7", - "CFG_CENTER_SW2A2_8", - "CFG_CENTER_SW2A2_9", - "CFG_CENTER_SW2A3_0", - "CFG_CENTER_SW2A3_1", - "CFG_CENTER_SW2A3_2", - "CFG_CENTER_SW2A3_3", - "CFG_CENTER_SW2A3_4", - "CFG_CENTER_SW2A3_5", - "CFG_CENTER_SW2A3_6", - "CFG_CENTER_SW2A3_7", - "CFG_CENTER_SW2A3_8", - "CFG_CENTER_SW2A3_9", - "CFG_CENTER_SW4A0_0", - "CFG_CENTER_SW4A0_1", - "CFG_CENTER_SW4A0_2", - "CFG_CENTER_SW4A0_3", - "CFG_CENTER_SW4A0_4", - "CFG_CENTER_SW4A0_5", - "CFG_CENTER_SW4A0_6", - "CFG_CENTER_SW4A0_7", - "CFG_CENTER_SW4A0_8", - "CFG_CENTER_SW4A0_9", - "CFG_CENTER_SW4A1_0", - "CFG_CENTER_SW4A1_1", - "CFG_CENTER_SW4A1_2", - "CFG_CENTER_SW4A1_3", - "CFG_CENTER_SW4A1_4", - "CFG_CENTER_SW4A1_5", - "CFG_CENTER_SW4A1_6", - "CFG_CENTER_SW4A1_7", - "CFG_CENTER_SW4A1_8", - "CFG_CENTER_SW4A1_9", - "CFG_CENTER_SW4A2_0", - "CFG_CENTER_SW4A2_1", - "CFG_CENTER_SW4A2_2", - "CFG_CENTER_SW4A2_3", - "CFG_CENTER_SW4A2_4", - "CFG_CENTER_SW4A2_5", - "CFG_CENTER_SW4A2_6", - "CFG_CENTER_SW4A2_7", - "CFG_CENTER_SW4A2_8", - "CFG_CENTER_SW4A2_9", - "CFG_CENTER_SW4A3_0", - "CFG_CENTER_SW4A3_1", - "CFG_CENTER_SW4A3_2", - "CFG_CENTER_SW4A3_3", - "CFG_CENTER_SW4A3_4", - "CFG_CENTER_SW4A3_5", - "CFG_CENTER_SW4A3_6", - "CFG_CENTER_SW4A3_7", - "CFG_CENTER_SW4A3_8", - "CFG_CENTER_SW4A3_9", - "CFG_CENTER_SW4END0_0", - "CFG_CENTER_SW4END0_1", - "CFG_CENTER_SW4END0_2", - "CFG_CENTER_SW4END0_3", - "CFG_CENTER_SW4END0_4", - "CFG_CENTER_SW4END0_5", - "CFG_CENTER_SW4END0_6", - "CFG_CENTER_SW4END0_7", - "CFG_CENTER_SW4END0_8", - "CFG_CENTER_SW4END0_9", - "CFG_CENTER_SW4END1_0", - "CFG_CENTER_SW4END1_1", - "CFG_CENTER_SW4END1_2", - "CFG_CENTER_SW4END1_3", - "CFG_CENTER_SW4END1_4", - "CFG_CENTER_SW4END1_5", - "CFG_CENTER_SW4END1_6", - "CFG_CENTER_SW4END1_7", - "CFG_CENTER_SW4END1_8", - "CFG_CENTER_SW4END1_9", - "CFG_CENTER_SW4END2_0", - "CFG_CENTER_SW4END2_1", - "CFG_CENTER_SW4END2_2", - "CFG_CENTER_SW4END2_3", - "CFG_CENTER_SW4END2_4", - "CFG_CENTER_SW4END2_5", - "CFG_CENTER_SW4END2_6", - "CFG_CENTER_SW4END2_7", - "CFG_CENTER_SW4END2_8", - "CFG_CENTER_SW4END2_9", - "CFG_CENTER_SW4END3_0", - "CFG_CENTER_SW4END3_1", - "CFG_CENTER_SW4END3_2", - "CFG_CENTER_SW4END3_3", - "CFG_CENTER_SW4END3_4", - "CFG_CENTER_SW4END3_5", - "CFG_CENTER_SW4END3_6", - "CFG_CENTER_SW4END3_7", - "CFG_CENTER_SW4END3_8", - "CFG_CENTER_SW4END3_9", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA11", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA12", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA13", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA14", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA15", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA16", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA17", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA18", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA19", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA20", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA21", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA22", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA23", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA24", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA25", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA26", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA27", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA28", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA29", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA30", - "CFG_CENTER_TOP_CFG_IO_ACCESS_CFGDATA31", - "CFG_CENTER_TOP_DNA_PORT_CLK", - "CFG_CENTER_TOP_ICAP1_CLK", - "CFG_CENTER_WL1END0_0", - "CFG_CENTER_WL1END0_1", - "CFG_CENTER_WL1END0_2", - "CFG_CENTER_WL1END0_3", - "CFG_CENTER_WL1END0_4", - "CFG_CENTER_WL1END0_5", - "CFG_CENTER_WL1END0_6", - "CFG_CENTER_WL1END0_7", - "CFG_CENTER_WL1END0_8", - "CFG_CENTER_WL1END0_9", - "CFG_CENTER_WL1END1_0", - "CFG_CENTER_WL1END1_1", - "CFG_CENTER_WL1END1_2", - "CFG_CENTER_WL1END1_3", - "CFG_CENTER_WL1END1_4", - "CFG_CENTER_WL1END1_5", - "CFG_CENTER_WL1END1_6", - "CFG_CENTER_WL1END1_7", - "CFG_CENTER_WL1END1_8", - "CFG_CENTER_WL1END1_9", - "CFG_CENTER_WL1END2_0", - "CFG_CENTER_WL1END2_1", - "CFG_CENTER_WL1END2_2", - "CFG_CENTER_WL1END2_3", - "CFG_CENTER_WL1END2_4", - "CFG_CENTER_WL1END2_5", - "CFG_CENTER_WL1END2_6", - "CFG_CENTER_WL1END2_7", - "CFG_CENTER_WL1END2_8", - "CFG_CENTER_WL1END2_9", - "CFG_CENTER_WL1END3_0", - "CFG_CENTER_WL1END3_1", - "CFG_CENTER_WL1END3_2", - "CFG_CENTER_WL1END3_3", - "CFG_CENTER_WL1END3_4", - "CFG_CENTER_WL1END3_5", - "CFG_CENTER_WL1END3_6", - "CFG_CENTER_WL1END3_7", - "CFG_CENTER_WL1END3_8", - "CFG_CENTER_WL1END3_9", - "CFG_CENTER_WR1END0_0", - "CFG_CENTER_WR1END0_1", - "CFG_CENTER_WR1END0_2", - "CFG_CENTER_WR1END0_3", - "CFG_CENTER_WR1END0_4", - "CFG_CENTER_WR1END0_5", - "CFG_CENTER_WR1END0_6", - "CFG_CENTER_WR1END0_7", - "CFG_CENTER_WR1END0_8", - "CFG_CENTER_WR1END0_9", - "CFG_CENTER_WR1END1_0", - "CFG_CENTER_WR1END1_1", - "CFG_CENTER_WR1END1_2", - "CFG_CENTER_WR1END1_3", - "CFG_CENTER_WR1END1_4", - "CFG_CENTER_WR1END1_5", - "CFG_CENTER_WR1END1_6", - "CFG_CENTER_WR1END1_7", - "CFG_CENTER_WR1END1_8", - "CFG_CENTER_WR1END1_9", - "CFG_CENTER_WR1END2_0", - "CFG_CENTER_WR1END2_1", - "CFG_CENTER_WR1END2_2", - "CFG_CENTER_WR1END2_3", - "CFG_CENTER_WR1END2_4", - "CFG_CENTER_WR1END2_5", - "CFG_CENTER_WR1END2_6", - "CFG_CENTER_WR1END2_7", - "CFG_CENTER_WR1END2_8", - "CFG_CENTER_WR1END2_9", - "CFG_CENTER_WR1END3_0", - "CFG_CENTER_WR1END3_1", - "CFG_CENTER_WR1END3_2", - "CFG_CENTER_WR1END3_3", - "CFG_CENTER_WR1END3_4", - "CFG_CENTER_WR1END3_5", - "CFG_CENTER_WR1END3_6", - "CFG_CENTER_WR1END3_7", - "CFG_CENTER_WR1END3_8", - "CFG_CENTER_WR1END3_9", - "CFG_CENTER_WW2A0_0", - "CFG_CENTER_WW2A0_1", - "CFG_CENTER_WW2A0_2", - "CFG_CENTER_WW2A0_3", - "CFG_CENTER_WW2A0_4", - "CFG_CENTER_WW2A0_5", - "CFG_CENTER_WW2A0_6", - "CFG_CENTER_WW2A0_7", - "CFG_CENTER_WW2A0_8", - "CFG_CENTER_WW2A0_9", - "CFG_CENTER_WW2A1_0", - "CFG_CENTER_WW2A1_1", - "CFG_CENTER_WW2A1_2", - "CFG_CENTER_WW2A1_3", - "CFG_CENTER_WW2A1_4", - "CFG_CENTER_WW2A1_5", - "CFG_CENTER_WW2A1_6", - "CFG_CENTER_WW2A1_7", - "CFG_CENTER_WW2A1_8", - "CFG_CENTER_WW2A1_9", - "CFG_CENTER_WW2A2_0", - "CFG_CENTER_WW2A2_1", - "CFG_CENTER_WW2A2_2", - "CFG_CENTER_WW2A2_3", - "CFG_CENTER_WW2A2_4", - "CFG_CENTER_WW2A2_5", - "CFG_CENTER_WW2A2_6", - "CFG_CENTER_WW2A2_7", - "CFG_CENTER_WW2A2_8", - "CFG_CENTER_WW2A2_9", - "CFG_CENTER_WW2A3_0", - "CFG_CENTER_WW2A3_1", - "CFG_CENTER_WW2A3_2", - "CFG_CENTER_WW2A3_3", - "CFG_CENTER_WW2A3_4", - "CFG_CENTER_WW2A3_5", - "CFG_CENTER_WW2A3_6", - "CFG_CENTER_WW2A3_7", - "CFG_CENTER_WW2A3_8", - "CFG_CENTER_WW2A3_9", - "CFG_CENTER_WW2END0_0", - "CFG_CENTER_WW2END0_1", - "CFG_CENTER_WW2END0_2", - "CFG_CENTER_WW2END0_3", - "CFG_CENTER_WW2END0_4", - "CFG_CENTER_WW2END0_5", - "CFG_CENTER_WW2END0_6", - "CFG_CENTER_WW2END0_7", - "CFG_CENTER_WW2END0_8", - "CFG_CENTER_WW2END0_9", - "CFG_CENTER_WW2END1_0", - "CFG_CENTER_WW2END1_1", - "CFG_CENTER_WW2END1_2", - "CFG_CENTER_WW2END1_3", - "CFG_CENTER_WW2END1_4", - "CFG_CENTER_WW2END1_5", - "CFG_CENTER_WW2END1_6", - "CFG_CENTER_WW2END1_7", - "CFG_CENTER_WW2END1_8", - "CFG_CENTER_WW2END1_9", - "CFG_CENTER_WW2END2_0", - "CFG_CENTER_WW2END2_1", - "CFG_CENTER_WW2END2_2", - "CFG_CENTER_WW2END2_3", - "CFG_CENTER_WW2END2_4", - "CFG_CENTER_WW2END2_5", - "CFG_CENTER_WW2END2_6", - "CFG_CENTER_WW2END2_7", - "CFG_CENTER_WW2END2_8", - "CFG_CENTER_WW2END2_9", - "CFG_CENTER_WW2END3_0", - "CFG_CENTER_WW2END3_1", - "CFG_CENTER_WW2END3_2", - "CFG_CENTER_WW2END3_3", - "CFG_CENTER_WW2END3_4", - "CFG_CENTER_WW2END3_5", - "CFG_CENTER_WW2END3_6", - "CFG_CENTER_WW2END3_7", - "CFG_CENTER_WW2END3_8", - "CFG_CENTER_WW2END3_9", - "CFG_CENTER_WW4A0_0", - "CFG_CENTER_WW4A0_1", - "CFG_CENTER_WW4A0_2", - "CFG_CENTER_WW4A0_3", - "CFG_CENTER_WW4A0_4", - "CFG_CENTER_WW4A0_5", - "CFG_CENTER_WW4A0_6", - "CFG_CENTER_WW4A0_7", - "CFG_CENTER_WW4A0_8", - "CFG_CENTER_WW4A0_9", - "CFG_CENTER_WW4A1_0", - "CFG_CENTER_WW4A1_1", - "CFG_CENTER_WW4A1_2", - "CFG_CENTER_WW4A1_3", - "CFG_CENTER_WW4A1_4", - "CFG_CENTER_WW4A1_5", - "CFG_CENTER_WW4A1_6", - "CFG_CENTER_WW4A1_7", - "CFG_CENTER_WW4A1_8", - "CFG_CENTER_WW4A1_9", - "CFG_CENTER_WW4A2_0", - "CFG_CENTER_WW4A2_1", - "CFG_CENTER_WW4A2_2", - "CFG_CENTER_WW4A2_3", - "CFG_CENTER_WW4A2_4", - "CFG_CENTER_WW4A2_5", - "CFG_CENTER_WW4A2_6", - "CFG_CENTER_WW4A2_7", - "CFG_CENTER_WW4A2_8", - "CFG_CENTER_WW4A2_9", - "CFG_CENTER_WW4A3_0", - "CFG_CENTER_WW4A3_1", - "CFG_CENTER_WW4A3_2", - "CFG_CENTER_WW4A3_3", - "CFG_CENTER_WW4A3_4", - "CFG_CENTER_WW4A3_5", - "CFG_CENTER_WW4A3_6", - "CFG_CENTER_WW4A3_7", - "CFG_CENTER_WW4A3_8", - "CFG_CENTER_WW4A3_9", - "CFG_CENTER_WW4B0_0", - "CFG_CENTER_WW4B0_1", - "CFG_CENTER_WW4B0_2", - "CFG_CENTER_WW4B0_3", - "CFG_CENTER_WW4B0_4", - "CFG_CENTER_WW4B0_5", - "CFG_CENTER_WW4B0_6", - "CFG_CENTER_WW4B0_7", - "CFG_CENTER_WW4B0_8", - "CFG_CENTER_WW4B0_9", - "CFG_CENTER_WW4B1_0", - "CFG_CENTER_WW4B1_1", - "CFG_CENTER_WW4B1_2", - "CFG_CENTER_WW4B1_3", - "CFG_CENTER_WW4B1_4", - "CFG_CENTER_WW4B1_5", - "CFG_CENTER_WW4B1_6", - "CFG_CENTER_WW4B1_7", - "CFG_CENTER_WW4B1_8", - "CFG_CENTER_WW4B1_9", - "CFG_CENTER_WW4B2_0", - "CFG_CENTER_WW4B2_1", - "CFG_CENTER_WW4B2_2", - "CFG_CENTER_WW4B2_3", - "CFG_CENTER_WW4B2_4", - "CFG_CENTER_WW4B2_5", - "CFG_CENTER_WW4B2_6", - "CFG_CENTER_WW4B2_7", - "CFG_CENTER_WW4B2_8", - "CFG_CENTER_WW4B2_9", - "CFG_CENTER_WW4B3_0", - "CFG_CENTER_WW4B3_1", - "CFG_CENTER_WW4B3_2", - "CFG_CENTER_WW4B3_3", - "CFG_CENTER_WW4B3_4", - "CFG_CENTER_WW4B3_5", - "CFG_CENTER_WW4B3_6", - "CFG_CENTER_WW4B3_7", - "CFG_CENTER_WW4B3_8", - "CFG_CENTER_WW4B3_9", - "CFG_CENTER_WW4C0_0", - "CFG_CENTER_WW4C0_1", - "CFG_CENTER_WW4C0_2", - "CFG_CENTER_WW4C0_3", - "CFG_CENTER_WW4C0_4", - "CFG_CENTER_WW4C0_5", - "CFG_CENTER_WW4C0_6", - "CFG_CENTER_WW4C0_7", - "CFG_CENTER_WW4C0_8", - "CFG_CENTER_WW4C0_9", - "CFG_CENTER_WW4C1_0", - "CFG_CENTER_WW4C1_1", - "CFG_CENTER_WW4C1_2", - "CFG_CENTER_WW4C1_3", - "CFG_CENTER_WW4C1_4", - "CFG_CENTER_WW4C1_5", - "CFG_CENTER_WW4C1_6", - "CFG_CENTER_WW4C1_7", - "CFG_CENTER_WW4C1_8", - "CFG_CENTER_WW4C1_9", - "CFG_CENTER_WW4C2_0", - "CFG_CENTER_WW4C2_1", - "CFG_CENTER_WW4C2_2", - "CFG_CENTER_WW4C2_3", - "CFG_CENTER_WW4C2_4", - "CFG_CENTER_WW4C2_5", - "CFG_CENTER_WW4C2_6", - "CFG_CENTER_WW4C2_7", - "CFG_CENTER_WW4C2_8", - "CFG_CENTER_WW4C2_9", - "CFG_CENTER_WW4C3_0", - "CFG_CENTER_WW4C3_1", - "CFG_CENTER_WW4C3_2", - "CFG_CENTER_WW4C3_3", - "CFG_CENTER_WW4C3_4", - "CFG_CENTER_WW4C3_5", - "CFG_CENTER_WW4C3_6", - "CFG_CENTER_WW4C3_7", - "CFG_CENTER_WW4C3_8", - "CFG_CENTER_WW4C3_9", - "CFG_CENTER_WW4END0_0", - "CFG_CENTER_WW4END0_1", - "CFG_CENTER_WW4END0_2", - "CFG_CENTER_WW4END0_3", - "CFG_CENTER_WW4END0_4", - "CFG_CENTER_WW4END0_5", - "CFG_CENTER_WW4END0_6", - "CFG_CENTER_WW4END0_7", - "CFG_CENTER_WW4END0_8", - "CFG_CENTER_WW4END0_9", - "CFG_CENTER_WW4END1_0", - "CFG_CENTER_WW4END1_1", - "CFG_CENTER_WW4END1_2", - "CFG_CENTER_WW4END1_3", - "CFG_CENTER_WW4END1_4", - "CFG_CENTER_WW4END1_5", - "CFG_CENTER_WW4END1_6", - "CFG_CENTER_WW4END1_7", - "CFG_CENTER_WW4END1_8", - "CFG_CENTER_WW4END1_9", - "CFG_CENTER_WW4END2_0", - "CFG_CENTER_WW4END2_1", - "CFG_CENTER_WW4END2_2", - "CFG_CENTER_WW4END2_3", - "CFG_CENTER_WW4END2_4", - "CFG_CENTER_WW4END2_5", - "CFG_CENTER_WW4END2_6", - "CFG_CENTER_WW4END2_7", - "CFG_CENTER_WW4END2_8", - "CFG_CENTER_WW4END2_9", - "CFG_CENTER_WW4END3_0", - "CFG_CENTER_WW4END3_1", - "CFG_CENTER_WW4END3_2", - "CFG_CENTER_WW4END3_3", - "CFG_CENTER_WW4END3_4", - "CFG_CENTER_WW4END3_5", - "CFG_CENTER_WW4END3_6", - "CFG_CENTER_WW4END3_7", - "CFG_CENTER_WW4END3_8", - "CFG_CENTER_WW4END3_9" - ] + "wires": { + "CFG_CENTER_BLOCK_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BLOCK_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_BYP0_0": null, + "CFG_CENTER_BYP0_1": null, + "CFG_CENTER_BYP0_2": null, + "CFG_CENTER_BYP0_3": null, + "CFG_CENTER_BYP0_4": null, + "CFG_CENTER_BYP0_5": null, + "CFG_CENTER_BYP0_6": null, + "CFG_CENTER_BYP0_7": null, + "CFG_CENTER_BYP0_8": null, + "CFG_CENTER_BYP0_9": null, + "CFG_CENTER_BYP1_0": null, + "CFG_CENTER_BYP1_1": null, + "CFG_CENTER_BYP1_2": null, + "CFG_CENTER_BYP1_3": null, + "CFG_CENTER_BYP1_4": null, + "CFG_CENTER_BYP1_5": null, + "CFG_CENTER_BYP1_6": null, + "CFG_CENTER_BYP1_7": null, + "CFG_CENTER_BYP1_8": null, + "CFG_CENTER_BYP1_9": null, + "CFG_CENTER_BYP2_0": null, + "CFG_CENTER_BYP2_1": null, + "CFG_CENTER_BYP2_2": null, + "CFG_CENTER_BYP2_3": null, + "CFG_CENTER_BYP2_4": null, + "CFG_CENTER_BYP2_5": null, + "CFG_CENTER_BYP2_6": null, + "CFG_CENTER_BYP2_7": null, + "CFG_CENTER_BYP2_8": null, + "CFG_CENTER_BYP2_9": null, + "CFG_CENTER_BYP3_0": null, + "CFG_CENTER_BYP3_1": null, + "CFG_CENTER_BYP3_2": null, + "CFG_CENTER_BYP3_3": null, + "CFG_CENTER_BYP3_4": null, + "CFG_CENTER_BYP3_5": null, + "CFG_CENTER_BYP3_6": null, + "CFG_CENTER_BYP3_7": null, + "CFG_CENTER_BYP3_8": null, + "CFG_CENTER_BYP3_9": null, + "CFG_CENTER_BYP4_0": null, + "CFG_CENTER_BYP4_1": null, + "CFG_CENTER_BYP4_2": null, + "CFG_CENTER_BYP4_3": null, + "CFG_CENTER_BYP4_4": null, + "CFG_CENTER_BYP4_5": null, + "CFG_CENTER_BYP4_6": null, + "CFG_CENTER_BYP4_7": null, + "CFG_CENTER_BYP4_8": null, + "CFG_CENTER_BYP4_9": null, + "CFG_CENTER_BYP5_0": null, + "CFG_CENTER_BYP5_1": null, + "CFG_CENTER_BYP5_2": null, + "CFG_CENTER_BYP5_3": null, + "CFG_CENTER_BYP5_4": null, + "CFG_CENTER_BYP5_5": null, + "CFG_CENTER_BYP5_6": null, + "CFG_CENTER_BYP5_7": null, + "CFG_CENTER_BYP5_8": null, + "CFG_CENTER_BYP5_9": null, + "CFG_CENTER_BYP6_0": null, + "CFG_CENTER_BYP6_1": null, + "CFG_CENTER_BYP6_2": null, + "CFG_CENTER_BYP6_3": null, + "CFG_CENTER_BYP6_4": null, + "CFG_CENTER_BYP6_5": null, + "CFG_CENTER_BYP6_6": null, + "CFG_CENTER_BYP6_7": null, + "CFG_CENTER_BYP6_8": null, + "CFG_CENTER_BYP6_9": null, + "CFG_CENTER_BYP7_0": null, + "CFG_CENTER_BYP7_1": null, + "CFG_CENTER_BYP7_2": null, + "CFG_CENTER_BYP7_3": null, + "CFG_CENTER_BYP7_4": null, + "CFG_CENTER_BYP7_5": null, + "CFG_CENTER_BYP7_6": null, + "CFG_CENTER_BYP7_7": null, + "CFG_CENTER_BYP7_8": null, + "CFG_CENTER_BYP7_9": null, + "CFG_CENTER_CLK0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CLK1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_CTRL1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_DNA_PORT_CLK": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_DNA_PORT_DIN": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_DNA_PORT_DOUT": null, + "CFG_CENTER_DNA_PORT_READ": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_DNA_PORT_SHIFT": { + "cap": "20.000", + "res": "0.000" + }, + "CFG_CENTER_EE2A0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_EE2A1_6": { + "cap": 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"1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX13_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX14_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX15_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX16_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX17_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX18_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX19_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX20_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX21_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX22_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX23_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX24_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX25_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX26_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX27_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX28_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX29_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX30_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX31_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX32_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX33_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX34_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX35_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX36_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX37_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX38_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX39_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX40_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX41_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX42_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX43_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX44_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX45_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX46_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX47_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX6_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX7_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX8_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_IMUX9_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LH10_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH10_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH11_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH12_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH1_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH2_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH3_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH4_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH5_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH6_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH7_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH8_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_0": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_1": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_2": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_3": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_4": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_5": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_6": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_7": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_8": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LH9_9": { + "cap": "61.760", + "res": "15.560" + }, + "CFG_CENTER_LOGIC_OUTS_B0_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B0_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B10_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B11_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B12_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B13_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B14_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B15_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B16_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B17_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B18_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B19_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B1_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B20_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B21_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B22_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B23_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B2_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B3_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B4_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B5_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B6_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B7_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B8_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_0": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_1": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_2": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_3": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_4": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_5": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_6": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_7": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_8": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_LOGIC_OUTS_B9_9": { + "cap": "1.111", + "res": "0.000" + }, + "CFG_CENTER_NE2A0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE2A3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4BEG3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NE4C3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW2A3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4A3_5": { + "cap": "99.000", + "res": "325.400" + }, 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"CFG_CENTER_NW4END1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_NW4END3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE2A3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4BEG3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_SE4C3_1": { + "cap": "99.000", + "res": "325.400" + }, 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"99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4C3_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END0_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END1_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END2_9": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_0": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_1": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_2": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_3": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_4": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_5": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_6": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_7": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_8": { + "cap": "99.000", + "res": "325.400" + }, + "CFG_CENTER_WW4END3_9": { + "cap": "99.000", + "res": "325.400" + } + } } diff --git a/kintex7/tile_type_CLBLL_L.json b/kintex7/tile_type_CLBLL_L.json index d0ef2e2..e510bf0 100644 --- a/kintex7/tile_type_CLBLL_L.json +++ b/kintex7/tile_type_CLBLL_L.json @@ -2,1024 +2,3210 @@ "pips": { "CLBLL_L.CLBLL_BYP0->CLBLL_L_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP0" }, "CLBLL_L.CLBLL_BYP1->CLBLL_LL_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP1" }, "CLBLL_L.CLBLL_BYP2->CLBLL_L_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP2" }, "CLBLL_L.CLBLL_BYP3->CLBLL_LL_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP3" }, "CLBLL_L.CLBLL_BYP4->CLBLL_LL_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP4" }, "CLBLL_L.CLBLL_BYP5->CLBLL_L_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP5" }, "CLBLL_L.CLBLL_BYP6->CLBLL_LL_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP6" }, "CLBLL_L.CLBLL_BYP7->CLBLL_L_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP7" }, "CLBLL_L.CLBLL_CLK0->CLBLL_L_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CLK0" }, "CLBLL_L.CLBLL_CLK1->CLBLL_LL_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CLK1" }, "CLBLL_L.CLBLL_CTRL0->CLBLL_L_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CTRL0" }, "CLBLL_L.CLBLL_CTRL1->CLBLL_LL_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CTRL1" }, "CLBLL_L.CLBLL_FAN6->CLBLL_L_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_FAN6" }, "CLBLL_L.CLBLL_FAN7->CLBLL_LL_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_FAN7" }, "CLBLL_L.CLBLL_IMUX0->CLBLL_L_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX0" }, "CLBLL_L.CLBLL_IMUX1->CLBLL_LL_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX1" }, "CLBLL_L.CLBLL_IMUX10->CLBLL_L_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX10" }, "CLBLL_L.CLBLL_IMUX11->CLBLL_LL_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX11" }, "CLBLL_L.CLBLL_IMUX12->CLBLL_LL_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX12" }, "CLBLL_L.CLBLL_IMUX13->CLBLL_L_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX13" }, "CLBLL_L.CLBLL_IMUX14->CLBLL_L_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX14" }, "CLBLL_L.CLBLL_IMUX15->CLBLL_LL_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX15" }, "CLBLL_L.CLBLL_IMUX16->CLBLL_L_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX16" }, "CLBLL_L.CLBLL_IMUX17->CLBLL_LL_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX17" }, "CLBLL_L.CLBLL_IMUX18->CLBLL_LL_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX18" }, "CLBLL_L.CLBLL_IMUX19->CLBLL_L_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX19" }, "CLBLL_L.CLBLL_IMUX2->CLBLL_LL_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX2" }, "CLBLL_L.CLBLL_IMUX20->CLBLL_L_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX20" }, "CLBLL_L.CLBLL_IMUX21->CLBLL_L_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX21" }, "CLBLL_L.CLBLL_IMUX22->CLBLL_LL_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX22" }, "CLBLL_L.CLBLL_IMUX23->CLBLL_L_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX23" }, "CLBLL_L.CLBLL_IMUX24->CLBLL_LL_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX24" }, "CLBLL_L.CLBLL_IMUX25->CLBLL_L_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX25" }, "CLBLL_L.CLBLL_IMUX26->CLBLL_L_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX26" }, "CLBLL_L.CLBLL_IMUX27->CLBLL_LL_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX27" }, "CLBLL_L.CLBLL_IMUX28->CLBLL_LL_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX28" }, "CLBLL_L.CLBLL_IMUX29->CLBLL_LL_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX29" }, "CLBLL_L.CLBLL_IMUX3->CLBLL_L_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX3" }, "CLBLL_L.CLBLL_IMUX30->CLBLL_L_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX30" }, "CLBLL_L.CLBLL_IMUX31->CLBLL_LL_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX31" }, "CLBLL_L.CLBLL_IMUX32->CLBLL_LL_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX32" }, "CLBLL_L.CLBLL_IMUX33->CLBLL_L_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX33" }, "CLBLL_L.CLBLL_IMUX34->CLBLL_L_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX34" }, "CLBLL_L.CLBLL_IMUX35->CLBLL_LL_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX35" }, "CLBLL_L.CLBLL_IMUX36->CLBLL_L_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX36" }, "CLBLL_L.CLBLL_IMUX37->CLBLL_L_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX37" }, "CLBLL_L.CLBLL_IMUX38->CLBLL_LL_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX38" }, "CLBLL_L.CLBLL_IMUX39->CLBLL_L_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX39" }, "CLBLL_L.CLBLL_IMUX4->CLBLL_LL_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX4" }, "CLBLL_L.CLBLL_IMUX40->CLBLL_LL_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX40" }, "CLBLL_L.CLBLL_IMUX41->CLBLL_L_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX41" }, "CLBLL_L.CLBLL_IMUX42->CLBLL_L_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX42" }, "CLBLL_L.CLBLL_IMUX43->CLBLL_LL_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX43" }, "CLBLL_L.CLBLL_IMUX44->CLBLL_LL_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX44" }, "CLBLL_L.CLBLL_IMUX45->CLBLL_LL_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX45" }, "CLBLL_L.CLBLL_IMUX46->CLBLL_L_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX46" }, "CLBLL_L.CLBLL_IMUX47->CLBLL_LL_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX47" }, "CLBLL_L.CLBLL_IMUX5->CLBLL_L_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX5" }, "CLBLL_L.CLBLL_IMUX6->CLBLL_L_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX6" }, "CLBLL_L.CLBLL_IMUX7->CLBLL_LL_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX7" }, "CLBLL_L.CLBLL_IMUX8->CLBLL_LL_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX8" }, "CLBLL_L.CLBLL_IMUX9->CLBLL_L_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX9" }, "CLBLL_L.CLBLL_LL_A->>CLBLL_LL_AMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.058", + "0.075", + "0.095" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_AMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.058", + "0.075", + "0.095" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A" }, "CLBLL_L.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_A" }, "CLBLL_L.CLBLL_LL_A1->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A1" }, "CLBLL_L.CLBLL_LL_A2->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A2" }, "CLBLL_L.CLBLL_LL_A3->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A3" }, "CLBLL_L.CLBLL_LL_A4->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A4" }, "CLBLL_L.CLBLL_LL_A5->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A5" }, "CLBLL_L.CLBLL_LL_A6->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A6" }, "CLBLL_L.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_AMUX" }, "CLBLL_L.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_AQ" }, "CLBLL_L.CLBLL_LL_B->>CLBLL_LL_BMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_BMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_B" }, "CLBLL_L.CLBLL_LL_B->CLBLL_LOGIC_OUTS13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_B" }, "CLBLL_L.CLBLL_LL_B1->>CLBLL_LL_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_B1" }, "CLBLL_L.CLBLL_LL_B2->>CLBLL_LL_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, 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"in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_A1" }, "CLBLL_L.CLBLL_L_A2->>CLBLL_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_A2" }, "CLBLL_L.CLBLL_L_A3->>CLBLL_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_A3" }, "CLBLL_L.CLBLL_L_A4->>CLBLL_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_A4" }, "CLBLL_L.CLBLL_L_A5->>CLBLL_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_A5" }, "CLBLL_L.CLBLL_L_A6->>CLBLL_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_A6" }, "CLBLL_L.CLBLL_L_AMUX->CLBLL_LOGIC_OUTS16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_AMUX" }, "CLBLL_L.CLBLL_L_AQ->CLBLL_LOGIC_OUTS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_AQ" }, "CLBLL_L.CLBLL_L_B->>CLBLL_L_BMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_BMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B" }, "CLBLL_L.CLBLL_L_B->CLBLL_LOGIC_OUTS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_B" }, "CLBLL_L.CLBLL_L_B1->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B1" }, "CLBLL_L.CLBLL_L_B2->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B2" }, "CLBLL_L.CLBLL_L_B3->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B3" }, "CLBLL_L.CLBLL_L_B4->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B4" }, "CLBLL_L.CLBLL_L_B5->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B5" }, "CLBLL_L.CLBLL_L_B6->>CLBLL_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_B6" }, "CLBLL_L.CLBLL_L_BMUX->CLBLL_LOGIC_OUTS17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_BMUX" }, "CLBLL_L.CLBLL_L_BQ->CLBLL_LOGIC_OUTS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_BQ" }, "CLBLL_L.CLBLL_L_C->>CLBLL_L_CMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.073", + "0.092" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_CMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.073", + "0.092" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C" }, "CLBLL_L.CLBLL_L_C->CLBLL_LOGIC_OUTS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_C" }, "CLBLL_L.CLBLL_L_C1->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C1" }, "CLBLL_L.CLBLL_L_C2->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C2" }, "CLBLL_L.CLBLL_L_C3->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C3" }, "CLBLL_L.CLBLL_L_C4->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C4" }, "CLBLL_L.CLBLL_L_C5->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C5" }, "CLBLL_L.CLBLL_L_C6->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C6" }, "CLBLL_L.CLBLL_L_CMUX->CLBLL_LOGIC_OUTS18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_CMUX" }, "CLBLL_L.CLBLL_L_COUT->>CLBLL_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.089", + "0.109", + "0.137" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.072", + "0.089", + "0.109", + "0.137" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_COUT" }, "CLBLL_L.CLBLL_L_COUT->CLBLL_L_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_COUT" }, "CLBLL_L.CLBLL_L_CQ->CLBLL_LOGIC_OUTS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_CQ" }, "CLBLL_L.CLBLL_L_D->>CLBLL_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.073", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.073", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D" }, "CLBLL_L.CLBLL_L_D->CLBLL_LOGIC_OUTS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_D" }, "CLBLL_L.CLBLL_L_D1->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D1" }, "CLBLL_L.CLBLL_L_D2->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D2" }, "CLBLL_L.CLBLL_L_D3->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D3" }, "CLBLL_L.CLBLL_L_D4->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D4" }, "CLBLL_L.CLBLL_L_D5->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D5" }, "CLBLL_L.CLBLL_L_D6->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D6" }, "CLBLL_L.CLBLL_L_DMUX->CLBLL_LOGIC_OUTS19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_DMUX" }, "CLBLL_L.CLBLL_L_DQ->CLBLL_LOGIC_OUTS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_DQ" } }, @@ -1028,51 +3214,456 @@ "name": "X1Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLL_L_A", - "A1": "CLBLL_L_A1", - "A2": "CLBLL_L_A2", - "A3": "CLBLL_L_A3", - "A4": "CLBLL_L_A4", - "A5": "CLBLL_L_A5", - "A6": "CLBLL_L_A6", - "AMUX": "CLBLL_L_AMUX", - "AQ": "CLBLL_L_AQ", - "AX": "CLBLL_L_AX", - "B": "CLBLL_L_B", - "B1": "CLBLL_L_B1", - "B2": "CLBLL_L_B2", - "B3": "CLBLL_L_B3", - "B4": "CLBLL_L_B4", - "B5": "CLBLL_L_B5", - "B6": "CLBLL_L_B6", - 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"CLBLL_L_SR" + } }, "type": "SLICEL", "x_coord": 1, @@ -1082,51 +3673,456 @@ "name": "X0Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLL_LL_A", - "A1": "CLBLL_LL_A1", - "A2": "CLBLL_LL_A2", - "A3": "CLBLL_LL_A3", - "A4": "CLBLL_LL_A4", - "A5": "CLBLL_LL_A5", - "A6": "CLBLL_LL_A6", - "AMUX": "CLBLL_LL_AMUX", - "AQ": "CLBLL_LL_AQ", - "AX": "CLBLL_LL_AX", - "B": "CLBLL_LL_B", - "B1": "CLBLL_LL_B1", - "B2": "CLBLL_LL_B2", - "B3": "CLBLL_LL_B3", - "B4": "CLBLL_LL_B4", - "B5": "CLBLL_LL_B5", - "B6": "CLBLL_LL_B6", - "BMUX": "CLBLL_LL_BMUX", - "BQ": "CLBLL_LL_BQ", - "BX": "CLBLL_LL_BX", - "C": "CLBLL_LL_C", - "C1": "CLBLL_LL_C1", - "C2": "CLBLL_LL_C2", - "C3": "CLBLL_LL_C3", - "C4": "CLBLL_LL_C4", - "C5": "CLBLL_LL_C5", - "C6": "CLBLL_LL_C6", - "CE": "CLBLL_LL_CE", - "CIN": "CLBLL_LL_CIN", - "CLK": "CLBLL_LL_CLK", - "CMUX": "CLBLL_LL_CMUX", - "COUT": "CLBLL_LL_COUT", - "CQ": "CLBLL_LL_CQ", - "CX": "CLBLL_LL_CX", - "D": "CLBLL_LL_D", - "D1": "CLBLL_LL_D1", - "D2": "CLBLL_LL_D2", - "D3": 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+ "wire": "CLBLL_LL_COUT" + }, + "CQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLL_LL_CQ" + }, + "CX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_LL_CX" + }, + "D": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "810.3796249999999", + "wire": "CLBLL_LL_D" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.135", + "0.168", + "0.221", + "0.262" + ], + "wire": "CLBLL_LL_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.131", + "0.163", + "0.213", + "0.252" + ], + "wire": "CLBLL_LL_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.079", + "0.099", + "0.141", + "0.167" + ], + "wire": "CLBLL_LL_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.066", + "0.082", + "0.116", + "0.138" + ], + "wire": "CLBLL_LL_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.026", + "0.032", + "0.042", + "0.050" + ], + "wire": "CLBLL_LL_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.002", + "0.002", + "0.002", + "0.003" + ], + "wire": "CLBLL_LL_D6" + }, + "DMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "825.0027499999999", + "wire": "CLBLL_LL_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLL_LL_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_LL_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_LL_SR" + } }, "type": "SLICEL", "x_coord": 0, @@ -1134,316 +4130,490 @@ } ], "tile_type": "CLBLL_L", - "wires": [ - "CLBLL_BYP0", - "CLBLL_BYP1", - "CLBLL_BYP2", - "CLBLL_BYP3", - "CLBLL_BYP4", - "CLBLL_BYP5", - "CLBLL_BYP6", - "CLBLL_BYP7", - "CLBLL_CLK0", - "CLBLL_CLK1", - "CLBLL_CTRL0", - "CLBLL_CTRL1", - "CLBLL_EE2A0", - "CLBLL_EE2A1", - "CLBLL_EE2A2", - "CLBLL_EE2A3", - "CLBLL_EE2BEG0", - "CLBLL_EE2BEG1", - "CLBLL_EE2BEG2", - "CLBLL_EE2BEG3", - "CLBLL_EE4A0", - "CLBLL_EE4A1", - "CLBLL_EE4A2", - "CLBLL_EE4A3", - "CLBLL_EE4B0", - "CLBLL_EE4B1", - "CLBLL_EE4B2", - "CLBLL_EE4B3", - "CLBLL_EE4BEG0", - "CLBLL_EE4BEG1", - "CLBLL_EE4BEG2", - "CLBLL_EE4BEG3", - "CLBLL_EE4C0", - "CLBLL_EE4C1", - "CLBLL_EE4C2", - "CLBLL_EE4C3", - "CLBLL_EL1BEG0", - "CLBLL_EL1BEG1", - "CLBLL_EL1BEG2", - "CLBLL_EL1BEG3", - "CLBLL_ER1BEG0", - "CLBLL_ER1BEG1", - "CLBLL_ER1BEG2", - "CLBLL_ER1BEG3", - "CLBLL_FAN0", - "CLBLL_FAN1", - "CLBLL_FAN2", - "CLBLL_FAN3", - "CLBLL_FAN4", - "CLBLL_FAN5", - "CLBLL_FAN6", - "CLBLL_FAN7", - "CLBLL_IMUX0", - "CLBLL_IMUX1", - "CLBLL_IMUX10", - "CLBLL_IMUX11", - "CLBLL_IMUX12", - "CLBLL_IMUX13", - "CLBLL_IMUX14", - "CLBLL_IMUX15", - "CLBLL_IMUX16", - "CLBLL_IMUX17", - "CLBLL_IMUX18", - "CLBLL_IMUX19", - "CLBLL_IMUX2", - "CLBLL_IMUX20", - "CLBLL_IMUX21", - "CLBLL_IMUX22", - "CLBLL_IMUX23", - "CLBLL_IMUX24", - "CLBLL_IMUX25", - "CLBLL_IMUX26", - "CLBLL_IMUX27", - "CLBLL_IMUX28", - "CLBLL_IMUX29", - "CLBLL_IMUX3", - "CLBLL_IMUX30", - "CLBLL_IMUX31", - "CLBLL_IMUX32", - "CLBLL_IMUX33", - "CLBLL_IMUX34", - "CLBLL_IMUX35", - "CLBLL_IMUX36", - "CLBLL_IMUX37", - "CLBLL_IMUX38", - "CLBLL_IMUX39", - "CLBLL_IMUX4", - "CLBLL_IMUX40", - "CLBLL_IMUX41", - "CLBLL_IMUX42", - "CLBLL_IMUX43", - "CLBLL_IMUX44", - "CLBLL_IMUX45", - "CLBLL_IMUX46", - "CLBLL_IMUX47", - "CLBLL_IMUX5", - "CLBLL_IMUX6", - "CLBLL_IMUX7", - "CLBLL_IMUX8", - "CLBLL_IMUX9", - "CLBLL_LH1", - "CLBLL_LH10", - "CLBLL_LH11", - "CLBLL_LH12", - "CLBLL_LH2", - "CLBLL_LH3", - "CLBLL_LH4", - "CLBLL_LH5", - "CLBLL_LH6", - "CLBLL_LH7", - "CLBLL_LH8", - "CLBLL_LH9", - "CLBLL_LL_A", - "CLBLL_LL_A1", - "CLBLL_LL_A2", - "CLBLL_LL_A3", - "CLBLL_LL_A4", - "CLBLL_LL_A5", - "CLBLL_LL_A6", - "CLBLL_LL_AMUX", - "CLBLL_LL_AQ", - "CLBLL_LL_AX", - "CLBLL_LL_B", - "CLBLL_LL_B1", - "CLBLL_LL_B2", - "CLBLL_LL_B3", - "CLBLL_LL_B4", - "CLBLL_LL_B5", - "CLBLL_LL_B6", - "CLBLL_LL_BMUX", - "CLBLL_LL_BQ", - "CLBLL_LL_BX", - "CLBLL_LL_C", - "CLBLL_LL_C1", - "CLBLL_LL_C2", - "CLBLL_LL_C3", - "CLBLL_LL_C4", - "CLBLL_LL_C5", - "CLBLL_LL_C6", - "CLBLL_LL_CE", - "CLBLL_LL_CIN", - "CLBLL_LL_CLK", - "CLBLL_LL_CMUX", - "CLBLL_LL_COUT", - "CLBLL_LL_COUT_N", - "CLBLL_LL_CQ", - "CLBLL_LL_CX", - "CLBLL_LL_D", - "CLBLL_LL_D1", - "CLBLL_LL_D2", - "CLBLL_LL_D3", - "CLBLL_LL_D4", - "CLBLL_LL_D5", - "CLBLL_LL_D6", - "CLBLL_LL_DMUX", - "CLBLL_LL_DQ", - "CLBLL_LL_DX", - "CLBLL_LL_SR", - "CLBLL_LOGIC_OUTS0", - "CLBLL_LOGIC_OUTS1", - "CLBLL_LOGIC_OUTS10", - "CLBLL_LOGIC_OUTS11", - "CLBLL_LOGIC_OUTS12", - "CLBLL_LOGIC_OUTS13", - "CLBLL_LOGIC_OUTS14", - "CLBLL_LOGIC_OUTS15", - "CLBLL_LOGIC_OUTS16", - "CLBLL_LOGIC_OUTS17", - "CLBLL_LOGIC_OUTS18", - "CLBLL_LOGIC_OUTS19", - "CLBLL_LOGIC_OUTS2", - "CLBLL_LOGIC_OUTS20", - "CLBLL_LOGIC_OUTS21", - "CLBLL_LOGIC_OUTS22", - "CLBLL_LOGIC_OUTS23", - "CLBLL_LOGIC_OUTS3", - "CLBLL_LOGIC_OUTS4", - "CLBLL_LOGIC_OUTS5", - "CLBLL_LOGIC_OUTS6", - "CLBLL_LOGIC_OUTS7", - "CLBLL_LOGIC_OUTS8", - "CLBLL_LOGIC_OUTS9", - "CLBLL_L_A", - "CLBLL_L_A1", - "CLBLL_L_A2", - "CLBLL_L_A3", - "CLBLL_L_A4", - "CLBLL_L_A5", - "CLBLL_L_A6", - "CLBLL_L_AMUX", - "CLBLL_L_AQ", - "CLBLL_L_AX", - "CLBLL_L_B", - "CLBLL_L_B1", - "CLBLL_L_B2", - "CLBLL_L_B3", - "CLBLL_L_B4", - "CLBLL_L_B5", - "CLBLL_L_B6", - "CLBLL_L_BMUX", - "CLBLL_L_BQ", - "CLBLL_L_BX", - "CLBLL_L_C", - "CLBLL_L_C1", - "CLBLL_L_C2", - "CLBLL_L_C3", - "CLBLL_L_C4", - "CLBLL_L_C5", - "CLBLL_L_C6", - "CLBLL_L_CE", - "CLBLL_L_CIN", - "CLBLL_L_CLK", - "CLBLL_L_CMUX", - "CLBLL_L_COUT", - "CLBLL_L_COUT_N", - "CLBLL_L_CQ", - "CLBLL_L_CX", - "CLBLL_L_D", - "CLBLL_L_D1", - "CLBLL_L_D2", - "CLBLL_L_D3", - "CLBLL_L_D4", - "CLBLL_L_D5", - "CLBLL_L_D6", - "CLBLL_L_DMUX", - "CLBLL_L_DQ", - "CLBLL_L_DX", - "CLBLL_L_SR", - "CLBLL_MONITOR_N", - "CLBLL_MONITOR_P", - "CLBLL_NE2A0", - "CLBLL_NE2A1", - "CLBLL_NE2A2", - "CLBLL_NE2A3", - "CLBLL_NE4BEG0", - "CLBLL_NE4BEG1", - "CLBLL_NE4BEG2", - "CLBLL_NE4BEG3", - "CLBLL_NE4C0", - "CLBLL_NE4C1", - "CLBLL_NE4C2", - "CLBLL_NE4C3", - "CLBLL_NW2A0", - "CLBLL_NW2A1", - "CLBLL_NW2A2", - "CLBLL_NW2A3", - "CLBLL_NW4A0", - "CLBLL_NW4A1", - "CLBLL_NW4A2", - "CLBLL_NW4A3", - "CLBLL_NW4END0", - "CLBLL_NW4END1", - "CLBLL_NW4END2", - "CLBLL_NW4END3", - "CLBLL_SE2A0", - "CLBLL_SE2A1", - "CLBLL_SE2A2", - "CLBLL_SE2A3", - "CLBLL_SE4BEG0", - "CLBLL_SE4BEG1", - "CLBLL_SE4BEG2", - "CLBLL_SE4BEG3", - "CLBLL_SE4C0", - "CLBLL_SE4C1", - "CLBLL_SE4C2", - "CLBLL_SE4C3", - "CLBLL_SW2A0", - "CLBLL_SW2A1", - "CLBLL_SW2A2", - "CLBLL_SW2A3", - "CLBLL_SW4A0", - "CLBLL_SW4A1", - "CLBLL_SW4A2", - "CLBLL_SW4A3", - "CLBLL_SW4END0", - "CLBLL_SW4END1", - "CLBLL_SW4END2", - "CLBLL_SW4END3", - "CLBLL_WL1END0", - "CLBLL_WL1END1", - "CLBLL_WL1END2", - "CLBLL_WL1END3", - "CLBLL_WR1END0", - "CLBLL_WR1END1", - "CLBLL_WR1END2", - "CLBLL_WR1END3", - "CLBLL_WW2A0", - "CLBLL_WW2A1", - "CLBLL_WW2A2", - "CLBLL_WW2A3", - "CLBLL_WW2END0", - "CLBLL_WW2END1", - "CLBLL_WW2END2", - "CLBLL_WW2END3", - "CLBLL_WW4A0", - "CLBLL_WW4A1", - "CLBLL_WW4A2", - "CLBLL_WW4A3", - "CLBLL_WW4B0", - "CLBLL_WW4B1", - "CLBLL_WW4B2", - "CLBLL_WW4B3", - "CLBLL_WW4C0", - "CLBLL_WW4C1", - "CLBLL_WW4C2", - "CLBLL_WW4C3", - "CLBLL_WW4END0", - "CLBLL_WW4END1", - "CLBLL_WW4END2", - "CLBLL_WW4END3" - ] + "wires": { + "CLBLL_BYP0": null, + "CLBLL_BYP1": null, + "CLBLL_BYP2": null, + "CLBLL_BYP3": null, + "CLBLL_BYP4": null, + "CLBLL_BYP5": null, + "CLBLL_BYP6": null, + "CLBLL_BYP7": null, + "CLBLL_CLK0": null, + "CLBLL_CLK1": null, + "CLBLL_CTRL0": null, + "CLBLL_CTRL1": null, + "CLBLL_EE2A0": null, + "CLBLL_EE2A1": null, + "CLBLL_EE2A2": null, + "CLBLL_EE2A3": null, + "CLBLL_EE2BEG0": null, + "CLBLL_EE2BEG1": null, + "CLBLL_EE2BEG2": null, + "CLBLL_EE2BEG3": null, + "CLBLL_EE4A0": null, + "CLBLL_EE4A1": null, + "CLBLL_EE4A2": null, + "CLBLL_EE4A3": null, + "CLBLL_EE4B0": null, + "CLBLL_EE4B1": null, + "CLBLL_EE4B2": null, + "CLBLL_EE4B3": null, + "CLBLL_EE4BEG0": null, + "CLBLL_EE4BEG1": null, + "CLBLL_EE4BEG2": null, + "CLBLL_EE4BEG3": null, + "CLBLL_EE4C0": null, + "CLBLL_EE4C1": null, + "CLBLL_EE4C2": null, + "CLBLL_EE4C3": null, + "CLBLL_EL1BEG0": { + "cap": "5.223", + "res": "45.964" + }, + "CLBLL_EL1BEG1": { + "cap": "5.223", + "res": "45.964" + }, + "CLBLL_EL1BEG2": { + "cap": "5.223", + "res": "45.964" + }, + "CLBLL_EL1BEG3": { + "cap": "5.223", + "res": "45.964" + }, + "CLBLL_ER1BEG0": { + "cap": "6.083", + "res": "79.256" + }, + "CLBLL_ER1BEG1": { + "cap": "6.083", + "res": "79.256" + }, + "CLBLL_ER1BEG2": { + "cap": "6.083", + "res": "79.256" + }, + "CLBLL_ER1BEG3": { + "cap": "6.083", + "res": "79.256" + }, + "CLBLL_FAN0": null, + "CLBLL_FAN1": null, + "CLBLL_FAN2": null, + "CLBLL_FAN3": null, + "CLBLL_FAN4": null, + "CLBLL_FAN5": null, + "CLBLL_FAN6": null, + "CLBLL_FAN7": null, + "CLBLL_IMUX0": null, + "CLBLL_IMUX1": null, + "CLBLL_IMUX10": null, + "CLBLL_IMUX11": null, + "CLBLL_IMUX12": null, + "CLBLL_IMUX13": null, + "CLBLL_IMUX14": null, + "CLBLL_IMUX15": null, + "CLBLL_IMUX16": null, + "CLBLL_IMUX17": null, + "CLBLL_IMUX18": null, + "CLBLL_IMUX19": null, + "CLBLL_IMUX2": null, + "CLBLL_IMUX20": null, + "CLBLL_IMUX21": null, + "CLBLL_IMUX22": null, + "CLBLL_IMUX23": null, + "CLBLL_IMUX24": null, + "CLBLL_IMUX25": null, + "CLBLL_IMUX26": null, + "CLBLL_IMUX27": null, + "CLBLL_IMUX28": null, + "CLBLL_IMUX29": null, + "CLBLL_IMUX3": null, + "CLBLL_IMUX30": null, + "CLBLL_IMUX31": null, + "CLBLL_IMUX32": null, + "CLBLL_IMUX33": null, + "CLBLL_IMUX34": null, + "CLBLL_IMUX35": null, + "CLBLL_IMUX36": null, + "CLBLL_IMUX37": null, + "CLBLL_IMUX38": null, + "CLBLL_IMUX39": null, + "CLBLL_IMUX4": null, + "CLBLL_IMUX40": null, + "CLBLL_IMUX41": null, + "CLBLL_IMUX42": null, + "CLBLL_IMUX43": null, + "CLBLL_IMUX44": null, + "CLBLL_IMUX45": null, + "CLBLL_IMUX46": null, + "CLBLL_IMUX47": null, + "CLBLL_IMUX5": null, + "CLBLL_IMUX6": null, + "CLBLL_IMUX7": null, + "CLBLL_IMUX8": null, + "CLBLL_IMUX9": null, + "CLBLL_LH1": null, + "CLBLL_LH10": null, + "CLBLL_LH11": null, + "CLBLL_LH12": null, + "CLBLL_LH2": null, + "CLBLL_LH3": null, + "CLBLL_LH4": null, + "CLBLL_LH5": null, + "CLBLL_LH6": null, + "CLBLL_LH7": null, + "CLBLL_LH8": null, + "CLBLL_LH9": null, + "CLBLL_LL_A": null, + "CLBLL_LL_A1": { + "cap": "6.628", + "res": "0.000" + }, + "CLBLL_LL_A2": null, + "CLBLL_LL_A3": { + "cap": "5.387", + "res": "0.000" + }, + "CLBLL_LL_A4": { + "cap": "9.361", + "res": "0.000" + }, + "CLBLL_LL_A5": { + "cap": "9.080", + "res": "0.000" + }, + "CLBLL_LL_A6": { + "cap": "5.078", + "res": "0.000" + }, + "CLBLL_LL_AMUX": null, + "CLBLL_LL_AQ": { + "cap": "2.234", + "res": "0.000" + }, + "CLBLL_LL_AX": { + "cap": "1.616", + "res": "0.000" + }, + "CLBLL_LL_B": null, + "CLBLL_LL_B1": null, + "CLBLL_LL_B2": { + "cap": "5.683", + "res": "0.000" + }, + "CLBLL_LL_B3": null, + "CLBLL_LL_B4": { + "cap": "2.841", + "res": "0.000" + }, + "CLBLL_LL_B5": { + "cap": "12.481", + "res": "0.000" + }, + "CLBLL_LL_B6": { + "cap": "6.241", + "res": "0.000" + }, + "CLBLL_LL_BMUX": { + "cap": "1.644", + "res": "0.000" + }, + "CLBLL_LL_BQ": { + "cap": "1.258", + "res": "0.000" + }, + "CLBLL_LL_BX": null, + "CLBLL_LL_C": null, + "CLBLL_LL_C1": { + "cap": "4.375", + "res": "0.000" + }, + "CLBLL_LL_C2": { + "cap": "4.047", + "res": "0.000" + }, + "CLBLL_LL_C3": { + "cap": "1.560", + "res": "0.000" + }, + "CLBLL_LL_C4": { + "cap": "6.241", + "res": "0.000" + }, + "CLBLL_LL_C5": { + "cap": "11.705", + "res": "0.000" + }, + "CLBLL_LL_C6": { + "cap": "6.628", + "res": "0.000" + }, + "CLBLL_LL_CE": null, + "CLBLL_LL_CIN": null, + "CLBLL_LL_CLK": null, + "CLBLL_LL_CMUX": null, + "CLBLL_LL_COUT": null, + "CLBLL_LL_COUT_N": null, + "CLBLL_LL_CQ": { + "cap": "2.355", + "res": "0.000" + }, + "CLBLL_LL_CX": null, + "CLBLL_LL_D": null, + "CLBLL_LL_D1": null, + "CLBLL_LL_D2": null, + "CLBLL_LL_D3": null, + "CLBLL_LL_D4": null, + "CLBLL_LL_D5": { + "cap": "8.611", + "res": "0.000" + }, + "CLBLL_LL_D6": { + "cap": "7.474", + "res": "0.000" + }, + "CLBLL_LL_DMUX": { + "cap": "2.636", + "res": "0.000" + }, + "CLBLL_LL_DQ": { + "cap": "1.728", + "res": "0.000" + }, + "CLBLL_LL_DX": { + "cap": "0.746", + "res": "0.000" + }, + "CLBLL_LL_SR": { + "cap": "1.259", + "res": "0.000" + }, + "CLBLL_LOGIC_OUTS0": null, + "CLBLL_LOGIC_OUTS1": null, + "CLBLL_LOGIC_OUTS10": null, + "CLBLL_LOGIC_OUTS11": null, + "CLBLL_LOGIC_OUTS12": null, + "CLBLL_LOGIC_OUTS13": null, + "CLBLL_LOGIC_OUTS14": null, + "CLBLL_LOGIC_OUTS15": null, + "CLBLL_LOGIC_OUTS16": null, + "CLBLL_LOGIC_OUTS17": null, + "CLBLL_LOGIC_OUTS18": null, + "CLBLL_LOGIC_OUTS19": null, + "CLBLL_LOGIC_OUTS2": null, + "CLBLL_LOGIC_OUTS20": null, + "CLBLL_LOGIC_OUTS21": null, + "CLBLL_LOGIC_OUTS22": null, + "CLBLL_LOGIC_OUTS23": null, + "CLBLL_LOGIC_OUTS3": null, + "CLBLL_LOGIC_OUTS4": null, + "CLBLL_LOGIC_OUTS5": null, + "CLBLL_LOGIC_OUTS6": null, + "CLBLL_LOGIC_OUTS7": null, + "CLBLL_LOGIC_OUTS8": null, + "CLBLL_LOGIC_OUTS9": null, + "CLBLL_L_A": null, + "CLBLL_L_A1": null, + "CLBLL_L_A2": null, + "CLBLL_L_A3": null, + "CLBLL_L_A4": null, + "CLBLL_L_A5": null, + "CLBLL_L_A6": null, + "CLBLL_L_AMUX": null, + "CLBLL_L_AQ": null, + "CLBLL_L_AX": null, + "CLBLL_L_B": null, + "CLBLL_L_B1": null, + "CLBLL_L_B2": null, + "CLBLL_L_B3": null, + "CLBLL_L_B4": null, + "CLBLL_L_B5": null, + "CLBLL_L_B6": null, + "CLBLL_L_BMUX": null, + "CLBLL_L_BQ": null, + "CLBLL_L_BX": null, + "CLBLL_L_C": null, + "CLBLL_L_C1": null, + "CLBLL_L_C2": null, + "CLBLL_L_C3": null, + "CLBLL_L_C4": null, + "CLBLL_L_C5": null, + "CLBLL_L_C6": null, + "CLBLL_L_CE": null, + "CLBLL_L_CIN": null, + "CLBLL_L_CLK": null, + "CLBLL_L_CMUX": null, + "CLBLL_L_COUT": null, + "CLBLL_L_COUT_N": null, + "CLBLL_L_CQ": null, + "CLBLL_L_CX": null, + "CLBLL_L_D": null, + "CLBLL_L_D1": null, + "CLBLL_L_D2": null, + "CLBLL_L_D3": null, + "CLBLL_L_D4": null, + "CLBLL_L_D5": null, + "CLBLL_L_D6": null, + "CLBLL_L_DMUX": null, + "CLBLL_L_DQ": null, + "CLBLL_L_DX": null, + "CLBLL_L_SR": null, + "CLBLL_MONITOR_N": null, + "CLBLL_MONITOR_P": null, + "CLBLL_NE2A0": { + "cap": "6.623", + "res": "89.705" + }, + "CLBLL_NE2A1": { + "cap": "6.623", + "res": "89.705" + }, + "CLBLL_NE2A2": { + "cap": "6.623", + "res": "89.705" + }, + "CLBLL_NE2A3": { + "cap": "6.623", + "res": "89.705" + }, + "CLBLL_NE4BEG0": null, + "CLBLL_NE4BEG1": null, + "CLBLL_NE4BEG2": null, + "CLBLL_NE4BEG3": null, + "CLBLL_NE4C0": null, + "CLBLL_NE4C1": null, + "CLBLL_NE4C2": null, + "CLBLL_NE4C3": null, + "CLBLL_NW2A0": { + "cap": "6.905", + "res": "81.493" + }, + "CLBLL_NW2A1": { + "cap": "6.905", + "res": "81.493" + }, + "CLBLL_NW2A2": { + "cap": "6.905", + "res": "81.493" + }, + "CLBLL_NW2A3": { + "cap": "6.905", + "res": "81.493" + }, + "CLBLL_NW4A0": null, + "CLBLL_NW4A1": null, + "CLBLL_NW4A2": null, + "CLBLL_NW4A3": null, + "CLBLL_NW4END0": null, + "CLBLL_NW4END1": null, + "CLBLL_NW4END2": null, + "CLBLL_NW4END3": null, + "CLBLL_SE2A0": { + "cap": "6.347", + "res": "80.329" + }, + "CLBLL_SE2A1": { + "cap": "6.347", + "res": "80.329" + }, + "CLBLL_SE2A2": { + "cap": "6.347", + "res": "80.329" + }, + "CLBLL_SE2A3": { + "cap": "6.347", + "res": "80.329" + }, + "CLBLL_SE4BEG0": null, + "CLBLL_SE4BEG1": null, + "CLBLL_SE4BEG2": null, + "CLBLL_SE4BEG3": null, + "CLBLL_SE4C0": null, + "CLBLL_SE4C1": null, + "CLBLL_SE4C2": null, + "CLBLL_SE4C3": null, + "CLBLL_SW2A0": { + "cap": "6.966", + "res": "79.992" + }, + "CLBLL_SW2A1": { + "cap": "6.966", + "res": "79.992" + }, + "CLBLL_SW2A2": { + "cap": "6.966", + "res": "79.992" + }, + "CLBLL_SW2A3": { + "cap": "6.966", + "res": "79.992" + }, + "CLBLL_SW4A0": null, + "CLBLL_SW4A1": null, + "CLBLL_SW4A2": null, + "CLBLL_SW4A3": null, + "CLBLL_SW4END0": null, + "CLBLL_SW4END1": null, + "CLBLL_SW4END2": null, + "CLBLL_SW4END3": null, + "CLBLL_WL1END0": { + "cap": "6.547", + "res": "52.107" + }, + "CLBLL_WL1END1": { + "cap": "6.547", + "res": "52.107" + }, + "CLBLL_WL1END2": { + "cap": "6.547", + "res": "52.107" + }, + "CLBLL_WL1END3": { + "cap": "6.547", + "res": "52.107" + }, + "CLBLL_WR1END0": { + "cap": "6.641", + "res": "81.873" + }, + "CLBLL_WR1END1": { + "cap": "6.641", + "res": "81.873" + }, + "CLBLL_WR1END2": { + "cap": "6.641", + "res": "81.873" + }, + "CLBLL_WR1END3": { + "cap": "6.641", + "res": "81.873" + }, + "CLBLL_WW2A0": null, + "CLBLL_WW2A1": null, + "CLBLL_WW2A2": null, + "CLBLL_WW2A3": null, + "CLBLL_WW2END0": null, + "CLBLL_WW2END1": null, + "CLBLL_WW2END2": null, + "CLBLL_WW2END3": null, + "CLBLL_WW4A0": null, + "CLBLL_WW4A1": null, + "CLBLL_WW4A2": null, + "CLBLL_WW4A3": null, + "CLBLL_WW4B0": null, + "CLBLL_WW4B1": null, + "CLBLL_WW4B2": null, + "CLBLL_WW4B3": null, + "CLBLL_WW4C0": null, + "CLBLL_WW4C1": null, + "CLBLL_WW4C2": null, + "CLBLL_WW4C3": null, + "CLBLL_WW4END0": null, + "CLBLL_WW4END1": null, + "CLBLL_WW4END2": null, + "CLBLL_WW4END3": null + } } diff --git a/kintex7/tile_type_CLBLL_R.json b/kintex7/tile_type_CLBLL_R.json index 288a860..49e5b43 100644 --- a/kintex7/tile_type_CLBLL_R.json +++ b/kintex7/tile_type_CLBLL_R.json @@ -2,1024 +2,3210 @@ "pips": { "CLBLL_R.CLBLL_BYP0->CLBLL_L_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP0" }, "CLBLL_R.CLBLL_BYP1->CLBLL_LL_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP1" }, "CLBLL_R.CLBLL_BYP2->CLBLL_L_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP2" }, "CLBLL_R.CLBLL_BYP3->CLBLL_LL_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP3" }, "CLBLL_R.CLBLL_BYP4->CLBLL_LL_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP4" }, "CLBLL_R.CLBLL_BYP5->CLBLL_L_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP5" }, "CLBLL_R.CLBLL_BYP6->CLBLL_LL_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP6" }, "CLBLL_R.CLBLL_BYP7->CLBLL_L_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_BYP7" }, "CLBLL_R.CLBLL_CLK0->CLBLL_L_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CLK0" }, "CLBLL_R.CLBLL_CLK1->CLBLL_LL_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CLK1" }, "CLBLL_R.CLBLL_CTRL0->CLBLL_L_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CTRL0" }, "CLBLL_R.CLBLL_CTRL1->CLBLL_LL_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_CTRL1" }, "CLBLL_R.CLBLL_FAN6->CLBLL_L_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_FAN6" }, "CLBLL_R.CLBLL_FAN7->CLBLL_LL_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_FAN7" }, "CLBLL_R.CLBLL_IMUX0->CLBLL_L_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX0" }, "CLBLL_R.CLBLL_IMUX1->CLBLL_LL_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX1" }, "CLBLL_R.CLBLL_IMUX10->CLBLL_L_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX10" }, "CLBLL_R.CLBLL_IMUX11->CLBLL_LL_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX11" }, "CLBLL_R.CLBLL_IMUX12->CLBLL_LL_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX12" }, "CLBLL_R.CLBLL_IMUX13->CLBLL_L_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX13" }, "CLBLL_R.CLBLL_IMUX14->CLBLL_L_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX14" }, "CLBLL_R.CLBLL_IMUX15->CLBLL_LL_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX15" }, "CLBLL_R.CLBLL_IMUX16->CLBLL_L_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX16" }, "CLBLL_R.CLBLL_IMUX17->CLBLL_LL_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX17" }, "CLBLL_R.CLBLL_IMUX18->CLBLL_LL_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX18" }, "CLBLL_R.CLBLL_IMUX19->CLBLL_L_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX19" }, "CLBLL_R.CLBLL_IMUX2->CLBLL_LL_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX2" }, "CLBLL_R.CLBLL_IMUX20->CLBLL_L_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX20" }, "CLBLL_R.CLBLL_IMUX21->CLBLL_L_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX21" }, "CLBLL_R.CLBLL_IMUX22->CLBLL_LL_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX22" }, "CLBLL_R.CLBLL_IMUX23->CLBLL_L_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX23" }, "CLBLL_R.CLBLL_IMUX24->CLBLL_LL_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX24" }, "CLBLL_R.CLBLL_IMUX25->CLBLL_L_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX25" }, "CLBLL_R.CLBLL_IMUX26->CLBLL_L_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX26" }, "CLBLL_R.CLBLL_IMUX27->CLBLL_LL_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX27" }, "CLBLL_R.CLBLL_IMUX28->CLBLL_LL_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX28" }, "CLBLL_R.CLBLL_IMUX29->CLBLL_LL_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX29" }, "CLBLL_R.CLBLL_IMUX3->CLBLL_L_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX3" }, "CLBLL_R.CLBLL_IMUX30->CLBLL_L_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX30" }, "CLBLL_R.CLBLL_IMUX31->CLBLL_LL_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX31" }, "CLBLL_R.CLBLL_IMUX32->CLBLL_LL_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX32" }, "CLBLL_R.CLBLL_IMUX33->CLBLL_L_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX33" }, "CLBLL_R.CLBLL_IMUX34->CLBLL_L_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX34" }, "CLBLL_R.CLBLL_IMUX35->CLBLL_LL_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX35" }, "CLBLL_R.CLBLL_IMUX36->CLBLL_L_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX36" }, "CLBLL_R.CLBLL_IMUX37->CLBLL_L_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX37" }, "CLBLL_R.CLBLL_IMUX38->CLBLL_LL_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX38" }, "CLBLL_R.CLBLL_IMUX39->CLBLL_L_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX39" }, "CLBLL_R.CLBLL_IMUX4->CLBLL_LL_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX4" }, "CLBLL_R.CLBLL_IMUX40->CLBLL_LL_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX40" }, "CLBLL_R.CLBLL_IMUX41->CLBLL_L_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX41" }, "CLBLL_R.CLBLL_IMUX42->CLBLL_L_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX42" }, "CLBLL_R.CLBLL_IMUX43->CLBLL_LL_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX43" }, "CLBLL_R.CLBLL_IMUX44->CLBLL_LL_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX44" }, "CLBLL_R.CLBLL_IMUX45->CLBLL_LL_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX45" }, "CLBLL_R.CLBLL_IMUX46->CLBLL_L_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX46" }, "CLBLL_R.CLBLL_IMUX47->CLBLL_LL_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX47" }, "CLBLL_R.CLBLL_IMUX5->CLBLL_L_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX5" }, "CLBLL_R.CLBLL_IMUX6->CLBLL_L_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX6" }, "CLBLL_R.CLBLL_IMUX7->CLBLL_LL_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX7" }, "CLBLL_R.CLBLL_IMUX8->CLBLL_LL_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LL_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX8" }, "CLBLL_R.CLBLL_IMUX9->CLBLL_L_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_IMUX9" }, "CLBLL_R.CLBLL_LL_A->>CLBLL_LL_AMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.058", + "0.075", + "0.095" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_AMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.058", + "0.075", + "0.095" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A" }, "CLBLL_R.CLBLL_LL_A->CLBLL_LOGIC_OUTS12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_A" }, "CLBLL_R.CLBLL_LL_A1->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A1" }, "CLBLL_R.CLBLL_LL_A2->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A2" }, "CLBLL_R.CLBLL_LL_A3->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A3" }, "CLBLL_R.CLBLL_LL_A4->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A4" }, "CLBLL_R.CLBLL_LL_A5->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A5" }, "CLBLL_R.CLBLL_LL_A6->>CLBLL_LL_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_LL_A6" }, "CLBLL_R.CLBLL_LL_AMUX->CLBLL_LOGIC_OUTS20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_AMUX" }, "CLBLL_R.CLBLL_LL_AQ->CLBLL_LOGIC_OUTS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_LL_AQ" }, "CLBLL_R.CLBLL_LL_B->>CLBLL_LL_BMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_LL_BMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, 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null, + "res": "0.000" + }, "src_wire": "CLBLL_L_A" }, "CLBLL_R.CLBLL_L_A1->>CLBLL_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_A1" }, "CLBLL_R.CLBLL_L_A2->>CLBLL_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_A2" }, "CLBLL_R.CLBLL_L_A3->>CLBLL_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + 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"is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_BQ" }, "CLBLL_R.CLBLL_L_C->>CLBLL_L_CMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.073", + "0.092" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_CMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.073", + "0.092" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C" }, "CLBLL_R.CLBLL_L_C->CLBLL_LOGIC_OUTS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_C" }, "CLBLL_R.CLBLL_L_C1->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C1" }, "CLBLL_R.CLBLL_L_C2->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C2" }, "CLBLL_R.CLBLL_L_C3->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C3" }, "CLBLL_R.CLBLL_L_C4->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C4" }, "CLBLL_R.CLBLL_L_C5->>CLBLL_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_C5" }, "CLBLL_R.CLBLL_L_C6->>CLBLL_L_C": { "can_invert": "0", + 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"delay": [ + "0.072", + "0.089", + "0.109", + "0.137" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_COUT" }, "CLBLL_R.CLBLL_L_COUT->CLBLL_L_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_L_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_COUT" }, "CLBLL_R.CLBLL_L_CQ->CLBLL_LOGIC_OUTS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLL_LOGIC_OUTS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLL_L_CQ" }, "CLBLL_R.CLBLL_L_D->>CLBLL_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.073", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": 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"dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D4" }, "CLBLL_R.CLBLL_L_D5->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLL_L_D5" }, "CLBLL_R.CLBLL_L_D6->>CLBLL_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLL_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + 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+ }, + "CMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "858.1766875000001", + "wire": "CLBLL_L_CMUX" + }, + "COUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "CLBLL_L_COUT" + }, + "CQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLL_L_CQ" + }, + "CX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_L_CX" + }, + "D": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "810.3796249999999", + "wire": "CLBLL_L_D" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.135", + "0.168", + "0.221", + "0.262" + ], + "wire": "CLBLL_L_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.131", + "0.163", + "0.213", + "0.252" + ], + "wire": "CLBLL_L_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.079", + "0.099", + "0.141", + "0.167" + ], + "wire": "CLBLL_L_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.066", + "0.082", + "0.116", + "0.138" + ], + "wire": "CLBLL_L_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.026", + "0.032", + "0.042", + "0.050" + ], + "wire": "CLBLL_L_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.002", + "0.002", + "0.002", + "0.003" + ], + "wire": "CLBLL_L_D6" + }, + "DMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "825.0027499999999", + "wire": "CLBLL_L_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLL_L_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_L_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLL_L_SR" + } }, "type": "SLICEL", "x_coord": 1, @@ -1134,316 +4130,490 @@ } ], "tile_type": "CLBLL_R", - "wires": [ - "CLBLL_BYP0", - "CLBLL_BYP1", - "CLBLL_BYP2", - "CLBLL_BYP3", - "CLBLL_BYP4", - "CLBLL_BYP5", - "CLBLL_BYP6", - "CLBLL_BYP7", - "CLBLL_CLK0", - "CLBLL_CLK1", - "CLBLL_CTRL0", - "CLBLL_CTRL1", - "CLBLL_EE2A0", - "CLBLL_EE2A1", - "CLBLL_EE2A2", - "CLBLL_EE2A3", - "CLBLL_EE2BEG0", - "CLBLL_EE2BEG1", - "CLBLL_EE2BEG2", - "CLBLL_EE2BEG3", - "CLBLL_EE4A0", - "CLBLL_EE4A1", - "CLBLL_EE4A2", - "CLBLL_EE4A3", - "CLBLL_EE4B0", - "CLBLL_EE4B1", - "CLBLL_EE4B2", - "CLBLL_EE4B3", - "CLBLL_EE4BEG0", - "CLBLL_EE4BEG1", - "CLBLL_EE4BEG2", - "CLBLL_EE4BEG3", - "CLBLL_EE4C0", - "CLBLL_EE4C1", - "CLBLL_EE4C2", - "CLBLL_EE4C3", - "CLBLL_EL1BEG0", - "CLBLL_EL1BEG1", - "CLBLL_EL1BEG2", - "CLBLL_EL1BEG3", - "CLBLL_ER1BEG0", - "CLBLL_ER1BEG1", - "CLBLL_ER1BEG2", - "CLBLL_ER1BEG3", - "CLBLL_FAN0", - "CLBLL_FAN1", - "CLBLL_FAN2", - "CLBLL_FAN3", - "CLBLL_FAN4", - "CLBLL_FAN5", - "CLBLL_FAN6", - "CLBLL_FAN7", - "CLBLL_IMUX0", - "CLBLL_IMUX1", - "CLBLL_IMUX10", - "CLBLL_IMUX11", - "CLBLL_IMUX12", - "CLBLL_IMUX13", - "CLBLL_IMUX14", - "CLBLL_IMUX15", - "CLBLL_IMUX16", - "CLBLL_IMUX17", - "CLBLL_IMUX18", - "CLBLL_IMUX19", - "CLBLL_IMUX2", - "CLBLL_IMUX20", - "CLBLL_IMUX21", - "CLBLL_IMUX22", - "CLBLL_IMUX23", - "CLBLL_IMUX24", - "CLBLL_IMUX25", - "CLBLL_IMUX26", - "CLBLL_IMUX27", - "CLBLL_IMUX28", - "CLBLL_IMUX29", - "CLBLL_IMUX3", - "CLBLL_IMUX30", - "CLBLL_IMUX31", - "CLBLL_IMUX32", - "CLBLL_IMUX33", - "CLBLL_IMUX34", - "CLBLL_IMUX35", - "CLBLL_IMUX36", - "CLBLL_IMUX37", - "CLBLL_IMUX38", - "CLBLL_IMUX39", - "CLBLL_IMUX4", - "CLBLL_IMUX40", - "CLBLL_IMUX41", - "CLBLL_IMUX42", - "CLBLL_IMUX43", - "CLBLL_IMUX44", - "CLBLL_IMUX45", - "CLBLL_IMUX46", - "CLBLL_IMUX47", - "CLBLL_IMUX5", - "CLBLL_IMUX6", - "CLBLL_IMUX7", - "CLBLL_IMUX8", - "CLBLL_IMUX9", - "CLBLL_LH1", - "CLBLL_LH10", - "CLBLL_LH11", - "CLBLL_LH12", - "CLBLL_LH2", - "CLBLL_LH3", - "CLBLL_LH4", - "CLBLL_LH5", - "CLBLL_LH6", - "CLBLL_LH7", - "CLBLL_LH8", - "CLBLL_LH9", - "CLBLL_LL_A", - "CLBLL_LL_A1", - "CLBLL_LL_A2", - "CLBLL_LL_A3", - "CLBLL_LL_A4", - "CLBLL_LL_A5", - "CLBLL_LL_A6", - "CLBLL_LL_AMUX", - "CLBLL_LL_AQ", - "CLBLL_LL_AX", - "CLBLL_LL_B", - "CLBLL_LL_B1", - "CLBLL_LL_B2", - "CLBLL_LL_B3", - "CLBLL_LL_B4", - "CLBLL_LL_B5", - "CLBLL_LL_B6", - "CLBLL_LL_BMUX", - "CLBLL_LL_BQ", - "CLBLL_LL_BX", - "CLBLL_LL_C", - "CLBLL_LL_C1", - "CLBLL_LL_C2", - "CLBLL_LL_C3", - "CLBLL_LL_C4", - "CLBLL_LL_C5", - "CLBLL_LL_C6", - "CLBLL_LL_CE", - "CLBLL_LL_CIN", - "CLBLL_LL_CLK", - "CLBLL_LL_CMUX", - "CLBLL_LL_COUT", - "CLBLL_LL_COUT_N", - "CLBLL_LL_CQ", - "CLBLL_LL_CX", - "CLBLL_LL_D", - "CLBLL_LL_D1", - "CLBLL_LL_D2", - "CLBLL_LL_D3", - "CLBLL_LL_D4", - "CLBLL_LL_D5", - "CLBLL_LL_D6", - "CLBLL_LL_DMUX", - "CLBLL_LL_DQ", - "CLBLL_LL_DX", - "CLBLL_LL_SR", - "CLBLL_LOGIC_OUTS0", - "CLBLL_LOGIC_OUTS1", - "CLBLL_LOGIC_OUTS10", - "CLBLL_LOGIC_OUTS11", - "CLBLL_LOGIC_OUTS12", - "CLBLL_LOGIC_OUTS13", - "CLBLL_LOGIC_OUTS14", - "CLBLL_LOGIC_OUTS15", - "CLBLL_LOGIC_OUTS16", - "CLBLL_LOGIC_OUTS17", - "CLBLL_LOGIC_OUTS18", - "CLBLL_LOGIC_OUTS19", - "CLBLL_LOGIC_OUTS2", - "CLBLL_LOGIC_OUTS20", - "CLBLL_LOGIC_OUTS21", - "CLBLL_LOGIC_OUTS22", - "CLBLL_LOGIC_OUTS23", - "CLBLL_LOGIC_OUTS3", - "CLBLL_LOGIC_OUTS4", - "CLBLL_LOGIC_OUTS5", - "CLBLL_LOGIC_OUTS6", - "CLBLL_LOGIC_OUTS7", - "CLBLL_LOGIC_OUTS8", - "CLBLL_LOGIC_OUTS9", - "CLBLL_L_A", - "CLBLL_L_A1", - "CLBLL_L_A2", - "CLBLL_L_A3", - "CLBLL_L_A4", - "CLBLL_L_A5", - "CLBLL_L_A6", - "CLBLL_L_AMUX", - "CLBLL_L_AQ", - "CLBLL_L_AX", - "CLBLL_L_B", - "CLBLL_L_B1", - "CLBLL_L_B2", - "CLBLL_L_B3", - "CLBLL_L_B4", - "CLBLL_L_B5", - "CLBLL_L_B6", - "CLBLL_L_BMUX", - "CLBLL_L_BQ", - "CLBLL_L_BX", - "CLBLL_L_C", - "CLBLL_L_C1", - "CLBLL_L_C2", - "CLBLL_L_C3", - "CLBLL_L_C4", - "CLBLL_L_C5", - "CLBLL_L_C6", - "CLBLL_L_CE", - "CLBLL_L_CIN", - "CLBLL_L_CLK", - "CLBLL_L_CMUX", - "CLBLL_L_COUT", - "CLBLL_L_COUT_N", - "CLBLL_L_CQ", - "CLBLL_L_CX", - "CLBLL_L_D", - "CLBLL_L_D1", - "CLBLL_L_D2", - "CLBLL_L_D3", - "CLBLL_L_D4", - "CLBLL_L_D5", - "CLBLL_L_D6", - "CLBLL_L_DMUX", - "CLBLL_L_DQ", - "CLBLL_L_DX", - "CLBLL_L_SR", - "CLBLL_MONITOR_N", - "CLBLL_MONITOR_P", - "CLBLL_NE2A0", - "CLBLL_NE2A1", - "CLBLL_NE2A2", - "CLBLL_NE2A3", - "CLBLL_NE4BEG0", - "CLBLL_NE4BEG1", - "CLBLL_NE4BEG2", - "CLBLL_NE4BEG3", - "CLBLL_NE4C0", - "CLBLL_NE4C1", - "CLBLL_NE4C2", - "CLBLL_NE4C3", - "CLBLL_NW2A0", - "CLBLL_NW2A1", - "CLBLL_NW2A2", - "CLBLL_NW2A3", - "CLBLL_NW4A0", - "CLBLL_NW4A1", - "CLBLL_NW4A2", - "CLBLL_NW4A3", - "CLBLL_NW4END0", - "CLBLL_NW4END1", - "CLBLL_NW4END2", - "CLBLL_NW4END3", - "CLBLL_SE2A0", - "CLBLL_SE2A1", - "CLBLL_SE2A2", - "CLBLL_SE2A3", - "CLBLL_SE4BEG0", - "CLBLL_SE4BEG1", - "CLBLL_SE4BEG2", - "CLBLL_SE4BEG3", - "CLBLL_SE4C0", - "CLBLL_SE4C1", - "CLBLL_SE4C2", - "CLBLL_SE4C3", - "CLBLL_SW2A0", - "CLBLL_SW2A1", - "CLBLL_SW2A2", - "CLBLL_SW2A3", - "CLBLL_SW4A0", - "CLBLL_SW4A1", - "CLBLL_SW4A2", - "CLBLL_SW4A3", - "CLBLL_SW4END0", - "CLBLL_SW4END1", - "CLBLL_SW4END2", - "CLBLL_SW4END3", - "CLBLL_WL1END0", - "CLBLL_WL1END1", - "CLBLL_WL1END2", - "CLBLL_WL1END3", - "CLBLL_WR1END0", - "CLBLL_WR1END1", - "CLBLL_WR1END2", - "CLBLL_WR1END3", - "CLBLL_WW2A0", - "CLBLL_WW2A1", - "CLBLL_WW2A2", - "CLBLL_WW2A3", - "CLBLL_WW2END0", - "CLBLL_WW2END1", - "CLBLL_WW2END2", - "CLBLL_WW2END3", - "CLBLL_WW4A0", - "CLBLL_WW4A1", - "CLBLL_WW4A2", - "CLBLL_WW4A3", - "CLBLL_WW4B0", - "CLBLL_WW4B1", - "CLBLL_WW4B2", - "CLBLL_WW4B3", - "CLBLL_WW4C0", - "CLBLL_WW4C1", - "CLBLL_WW4C2", - "CLBLL_WW4C3", - "CLBLL_WW4END0", - "CLBLL_WW4END1", - "CLBLL_WW4END2", - "CLBLL_WW4END3" - ] + "wires": { + "CLBLL_BYP0": null, + "CLBLL_BYP1": null, + "CLBLL_BYP2": null, + "CLBLL_BYP3": null, + "CLBLL_BYP4": null, + "CLBLL_BYP5": null, + "CLBLL_BYP6": null, + "CLBLL_BYP7": null, + "CLBLL_CLK0": null, + "CLBLL_CLK1": null, + "CLBLL_CTRL0": null, + "CLBLL_CTRL1": null, + "CLBLL_EE2A0": null, + "CLBLL_EE2A1": null, + "CLBLL_EE2A2": null, + "CLBLL_EE2A3": null, + "CLBLL_EE2BEG0": null, + "CLBLL_EE2BEG1": null, + "CLBLL_EE2BEG2": null, + "CLBLL_EE2BEG3": null, + "CLBLL_EE4A0": null, + "CLBLL_EE4A1": null, + "CLBLL_EE4A2": null, + "CLBLL_EE4A3": null, + "CLBLL_EE4B0": null, + "CLBLL_EE4B1": null, + "CLBLL_EE4B2": null, + "CLBLL_EE4B3": null, + "CLBLL_EE4BEG0": null, + "CLBLL_EE4BEG1": null, + "CLBLL_EE4BEG2": null, + "CLBLL_EE4BEG3": null, + "CLBLL_EE4C0": null, + "CLBLL_EE4C1": null, + "CLBLL_EE4C2": null, + "CLBLL_EE4C3": null, + "CLBLL_EL1BEG0": { + "cap": "5.223", + "res": "45.964" + }, + "CLBLL_EL1BEG1": { + "cap": "5.223", + "res": "45.964" + }, + "CLBLL_EL1BEG2": { + "cap": "5.223", + "res": "45.964" + }, + "CLBLL_EL1BEG3": { + "cap": "5.223", + "res": "45.964" + }, + "CLBLL_ER1BEG0": { + "cap": "6.083", + "res": "79.256" + }, + "CLBLL_ER1BEG1": { + "cap": "6.083", + "res": "79.256" + }, + "CLBLL_ER1BEG2": { + "cap": "6.083", + "res": "79.256" + }, + "CLBLL_ER1BEG3": { + "cap": "6.083", + "res": "79.256" + }, + "CLBLL_FAN0": null, + "CLBLL_FAN1": null, + "CLBLL_FAN2": null, + "CLBLL_FAN3": null, + "CLBLL_FAN4": null, + "CLBLL_FAN5": null, + "CLBLL_FAN6": null, + "CLBLL_FAN7": null, + "CLBLL_IMUX0": null, + "CLBLL_IMUX1": null, + "CLBLL_IMUX10": null, + "CLBLL_IMUX11": null, + "CLBLL_IMUX12": null, + "CLBLL_IMUX13": null, + "CLBLL_IMUX14": null, + "CLBLL_IMUX15": null, + "CLBLL_IMUX16": null, + "CLBLL_IMUX17": null, + "CLBLL_IMUX18": null, + "CLBLL_IMUX19": null, + "CLBLL_IMUX2": null, + "CLBLL_IMUX20": null, + "CLBLL_IMUX21": null, + "CLBLL_IMUX22": null, + "CLBLL_IMUX23": null, + "CLBLL_IMUX24": null, + "CLBLL_IMUX25": null, + "CLBLL_IMUX26": null, + "CLBLL_IMUX27": null, + "CLBLL_IMUX28": null, + "CLBLL_IMUX29": null, + "CLBLL_IMUX3": null, + "CLBLL_IMUX30": null, + "CLBLL_IMUX31": null, + "CLBLL_IMUX32": null, + "CLBLL_IMUX33": null, + "CLBLL_IMUX34": null, + "CLBLL_IMUX35": null, + "CLBLL_IMUX36": null, + "CLBLL_IMUX37": null, + "CLBLL_IMUX38": null, + "CLBLL_IMUX39": null, + "CLBLL_IMUX4": null, + "CLBLL_IMUX40": null, + "CLBLL_IMUX41": null, + "CLBLL_IMUX42": null, + "CLBLL_IMUX43": null, + "CLBLL_IMUX44": null, + "CLBLL_IMUX45": null, + "CLBLL_IMUX46": null, + "CLBLL_IMUX47": null, + "CLBLL_IMUX5": null, + "CLBLL_IMUX6": null, + "CLBLL_IMUX7": null, + "CLBLL_IMUX8": null, + "CLBLL_IMUX9": null, + "CLBLL_LH1": null, + "CLBLL_LH10": null, + "CLBLL_LH11": null, + "CLBLL_LH12": null, + "CLBLL_LH2": null, + "CLBLL_LH3": null, + "CLBLL_LH4": null, + "CLBLL_LH5": null, + "CLBLL_LH6": null, + "CLBLL_LH7": null, + "CLBLL_LH8": null, + "CLBLL_LH9": null, + "CLBLL_LL_A": null, + "CLBLL_LL_A1": { + "cap": "6.628", + "res": "0.000" + }, + "CLBLL_LL_A2": null, + "CLBLL_LL_A3": { + "cap": "5.387", + "res": "0.000" + }, + "CLBLL_LL_A4": { + "cap": "9.361", + "res": "0.000" + }, + "CLBLL_LL_A5": { + "cap": "9.080", + "res": "0.000" + }, + "CLBLL_LL_A6": { + "cap": "5.078", + "res": "0.000" + }, + "CLBLL_LL_AMUX": null, + "CLBLL_LL_AQ": { + "cap": "2.234", + "res": "0.000" + }, + "CLBLL_LL_AX": { + "cap": "1.616", + "res": "0.000" + }, + "CLBLL_LL_B": null, + "CLBLL_LL_B1": null, + "CLBLL_LL_B2": { + "cap": "5.683", + "res": "0.000" + }, + "CLBLL_LL_B3": null, + "CLBLL_LL_B4": { + "cap": "2.841", + "res": "0.000" + }, + "CLBLL_LL_B5": { + "cap": "12.481", + "res": "0.000" + }, + "CLBLL_LL_B6": { + "cap": "6.241", + "res": "0.000" + }, + "CLBLL_LL_BMUX": { + "cap": "1.644", + "res": "0.000" + }, + "CLBLL_LL_BQ": { + "cap": "1.258", + "res": "0.000" + }, + "CLBLL_LL_BX": null, + "CLBLL_LL_C": null, + "CLBLL_LL_C1": { + "cap": "4.375", + "res": "0.000" + }, + "CLBLL_LL_C2": { + "cap": "4.047", + "res": "0.000" + }, + "CLBLL_LL_C3": { + "cap": "1.560", + "res": "0.000" + }, + "CLBLL_LL_C4": { + "cap": "6.241", + "res": "0.000" + }, + "CLBLL_LL_C5": { + "cap": "11.705", + "res": "0.000" + }, + "CLBLL_LL_C6": { + "cap": "6.628", + "res": "0.000" + }, + "CLBLL_LL_CE": null, + "CLBLL_LL_CIN": null, + "CLBLL_LL_CLK": null, + "CLBLL_LL_CMUX": null, + "CLBLL_LL_COUT": null, + "CLBLL_LL_COUT_N": null, + "CLBLL_LL_CQ": { + "cap": "2.355", + "res": "0.000" + }, + "CLBLL_LL_CX": null, + "CLBLL_LL_D": null, + "CLBLL_LL_D1": null, + "CLBLL_LL_D2": null, + "CLBLL_LL_D3": null, + "CLBLL_LL_D4": null, + "CLBLL_LL_D5": { + "cap": "8.611", + "res": "0.000" + }, + "CLBLL_LL_D6": { + "cap": "7.474", + "res": "0.000" + }, + "CLBLL_LL_DMUX": { + "cap": "2.636", + "res": "0.000" + }, + "CLBLL_LL_DQ": { + "cap": "1.728", + "res": "0.000" + }, + "CLBLL_LL_DX": { + "cap": "0.746", + "res": "0.000" + }, + "CLBLL_LL_SR": { + "cap": "1.259", + "res": "0.000" + }, + "CLBLL_LOGIC_OUTS0": null, + "CLBLL_LOGIC_OUTS1": null, + "CLBLL_LOGIC_OUTS10": null, + "CLBLL_LOGIC_OUTS11": null, + "CLBLL_LOGIC_OUTS12": null, + "CLBLL_LOGIC_OUTS13": null, + "CLBLL_LOGIC_OUTS14": null, + "CLBLL_LOGIC_OUTS15": null, + "CLBLL_LOGIC_OUTS16": null, + "CLBLL_LOGIC_OUTS17": null, + "CLBLL_LOGIC_OUTS18": null, + "CLBLL_LOGIC_OUTS19": null, + "CLBLL_LOGIC_OUTS2": null, + "CLBLL_LOGIC_OUTS20": null, + "CLBLL_LOGIC_OUTS21": null, + "CLBLL_LOGIC_OUTS22": null, + "CLBLL_LOGIC_OUTS23": null, + "CLBLL_LOGIC_OUTS3": null, + "CLBLL_LOGIC_OUTS4": null, + "CLBLL_LOGIC_OUTS5": null, + "CLBLL_LOGIC_OUTS6": null, + "CLBLL_LOGIC_OUTS7": null, + "CLBLL_LOGIC_OUTS8": null, + "CLBLL_LOGIC_OUTS9": null, + "CLBLL_L_A": null, + "CLBLL_L_A1": null, + "CLBLL_L_A2": null, + "CLBLL_L_A3": null, + "CLBLL_L_A4": null, + "CLBLL_L_A5": null, + "CLBLL_L_A6": null, + "CLBLL_L_AMUX": null, + "CLBLL_L_AQ": null, + "CLBLL_L_AX": null, + "CLBLL_L_B": null, + "CLBLL_L_B1": null, + "CLBLL_L_B2": null, + "CLBLL_L_B3": null, + "CLBLL_L_B4": null, + "CLBLL_L_B5": null, + "CLBLL_L_B6": null, + "CLBLL_L_BMUX": null, + "CLBLL_L_BQ": null, + "CLBLL_L_BX": null, + "CLBLL_L_C": null, + "CLBLL_L_C1": null, + "CLBLL_L_C2": null, + "CLBLL_L_C3": null, + "CLBLL_L_C4": null, + "CLBLL_L_C5": null, + "CLBLL_L_C6": null, + "CLBLL_L_CE": null, + "CLBLL_L_CIN": null, + "CLBLL_L_CLK": null, + "CLBLL_L_CMUX": null, + "CLBLL_L_COUT": null, + "CLBLL_L_COUT_N": null, + "CLBLL_L_CQ": null, + "CLBLL_L_CX": null, + "CLBLL_L_D": null, + "CLBLL_L_D1": null, + "CLBLL_L_D2": null, + "CLBLL_L_D3": null, + "CLBLL_L_D4": null, + "CLBLL_L_D5": null, + "CLBLL_L_D6": null, + "CLBLL_L_DMUX": null, + "CLBLL_L_DQ": null, + "CLBLL_L_DX": null, + "CLBLL_L_SR": null, + "CLBLL_MONITOR_N": null, + "CLBLL_MONITOR_P": null, + "CLBLL_NE2A0": { + "cap": "6.623", + "res": "89.705" + }, + "CLBLL_NE2A1": { + "cap": "6.623", + "res": "89.705" + }, + "CLBLL_NE2A2": { + "cap": "6.623", + "res": "89.705" + }, + "CLBLL_NE2A3": { + "cap": "6.623", + "res": "89.705" + }, + "CLBLL_NE4BEG0": null, + "CLBLL_NE4BEG1": null, + "CLBLL_NE4BEG2": null, + "CLBLL_NE4BEG3": null, + "CLBLL_NE4C0": null, + "CLBLL_NE4C1": null, + "CLBLL_NE4C2": null, + "CLBLL_NE4C3": null, + "CLBLL_NW2A0": { + "cap": "6.905", + "res": "81.493" + }, + "CLBLL_NW2A1": { + "cap": "6.905", + "res": "81.493" + }, + "CLBLL_NW2A2": { + "cap": "6.905", + "res": "81.493" + }, + "CLBLL_NW2A3": { + "cap": "6.905", + "res": "81.493" + }, + "CLBLL_NW4A0": null, + "CLBLL_NW4A1": null, + "CLBLL_NW4A2": null, + "CLBLL_NW4A3": null, + "CLBLL_NW4END0": null, + "CLBLL_NW4END1": null, + "CLBLL_NW4END2": null, + "CLBLL_NW4END3": null, + "CLBLL_SE2A0": { + "cap": "6.347", + "res": "80.329" + }, + "CLBLL_SE2A1": { + "cap": "6.347", + "res": "80.329" + }, + "CLBLL_SE2A2": { + "cap": "6.347", + "res": "80.329" + }, + "CLBLL_SE2A3": { + "cap": "6.347", + "res": "80.329" + }, + "CLBLL_SE4BEG0": null, + "CLBLL_SE4BEG1": null, + "CLBLL_SE4BEG2": null, + "CLBLL_SE4BEG3": null, + "CLBLL_SE4C0": null, + "CLBLL_SE4C1": null, + "CLBLL_SE4C2": null, + "CLBLL_SE4C3": null, + "CLBLL_SW2A0": { + "cap": "6.966", + "res": "79.992" + }, + "CLBLL_SW2A1": { + "cap": "6.966", + "res": "79.992" + }, + "CLBLL_SW2A2": { + "cap": "6.966", + "res": "79.992" + }, + "CLBLL_SW2A3": { + "cap": "6.966", + "res": "79.992" + }, + "CLBLL_SW4A0": null, + "CLBLL_SW4A1": null, + "CLBLL_SW4A2": null, + "CLBLL_SW4A3": null, + "CLBLL_SW4END0": null, + "CLBLL_SW4END1": null, + "CLBLL_SW4END2": null, + "CLBLL_SW4END3": null, + "CLBLL_WL1END0": { + "cap": "6.547", + "res": "52.107" + }, + "CLBLL_WL1END1": { + "cap": "6.547", + "res": "52.107" + }, + "CLBLL_WL1END2": { + "cap": "6.547", + "res": "52.107" + }, + "CLBLL_WL1END3": { + "cap": "6.547", + "res": "52.107" + }, + "CLBLL_WR1END0": { + "cap": "6.641", + "res": "81.873" + }, + "CLBLL_WR1END1": { + "cap": "6.641", + "res": "81.873" + }, + "CLBLL_WR1END2": { + "cap": "6.641", + "res": "81.873" + }, + "CLBLL_WR1END3": { + "cap": "6.641", + "res": "81.873" + }, + "CLBLL_WW2A0": null, + "CLBLL_WW2A1": null, + "CLBLL_WW2A2": null, + "CLBLL_WW2A3": null, + "CLBLL_WW2END0": null, + "CLBLL_WW2END1": null, + "CLBLL_WW2END2": null, + "CLBLL_WW2END3": null, + "CLBLL_WW4A0": null, + "CLBLL_WW4A1": null, + "CLBLL_WW4A2": null, + "CLBLL_WW4A3": null, + "CLBLL_WW4B0": null, + "CLBLL_WW4B1": null, + "CLBLL_WW4B2": null, + "CLBLL_WW4B3": null, + "CLBLL_WW4C0": null, + "CLBLL_WW4C1": null, + "CLBLL_WW4C2": null, + "CLBLL_WW4C3": null, + "CLBLL_WW4END0": null, + "CLBLL_WW4END1": null, + "CLBLL_WW4END2": null, + "CLBLL_WW4END3": null + } } diff --git a/kintex7/tile_type_CLBLM_L.json b/kintex7/tile_type_CLBLM_L.json index c4c1a5a..2391af3 100644 --- a/kintex7/tile_type_CLBLM_L.json +++ b/kintex7/tile_type_CLBLM_L.json @@ -2,1059 +2,3300 @@ "pips": { "CLBLM_L.CLBLM_BYP0->CLBLM_L_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP0" }, "CLBLM_L.CLBLM_BYP1->CLBLM_M_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP1" }, "CLBLM_L.CLBLM_BYP2->CLBLM_L_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP2" }, "CLBLM_L.CLBLM_BYP3->CLBLM_M_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP3" }, "CLBLM_L.CLBLM_BYP4->CLBLM_M_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP4" }, "CLBLM_L.CLBLM_BYP5->CLBLM_L_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP5" }, "CLBLM_L.CLBLM_BYP6->CLBLM_M_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP6" }, "CLBLM_L.CLBLM_BYP7->CLBLM_L_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP7" }, "CLBLM_L.CLBLM_CLK0->CLBLM_L_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CLK0" }, "CLBLM_L.CLBLM_CLK1->CLBLM_M_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CLK1" }, "CLBLM_L.CLBLM_CTRL0->CLBLM_L_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CTRL0" }, "CLBLM_L.CLBLM_CTRL1->CLBLM_M_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CTRL1" }, "CLBLM_L.CLBLM_FAN0->CLBLM_M_AI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_AI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN0" }, "CLBLM_L.CLBLM_FAN2->CLBLM_M_BI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_BI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN2" }, "CLBLM_L.CLBLM_FAN3->CLBLM_M_DI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_DI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN3" }, "CLBLM_L.CLBLM_FAN4->CLBLM_M_WE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_WE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN4" }, "CLBLM_L.CLBLM_FAN5->CLBLM_M_CI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN5" }, "CLBLM_L.CLBLM_FAN6->CLBLM_L_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN6" }, "CLBLM_L.CLBLM_FAN7->CLBLM_M_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN7" }, "CLBLM_L.CLBLM_IMUX0->CLBLM_L_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX0" }, "CLBLM_L.CLBLM_IMUX1->CLBLM_M_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX1" }, "CLBLM_L.CLBLM_IMUX10->CLBLM_L_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX10" }, "CLBLM_L.CLBLM_IMUX11->CLBLM_M_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX11" }, "CLBLM_L.CLBLM_IMUX12->CLBLM_M_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX12" }, "CLBLM_L.CLBLM_IMUX13->CLBLM_L_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX13" }, "CLBLM_L.CLBLM_IMUX14->CLBLM_L_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX14" }, "CLBLM_L.CLBLM_IMUX15->CLBLM_M_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX15" }, "CLBLM_L.CLBLM_IMUX16->CLBLM_L_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX16" }, "CLBLM_L.CLBLM_IMUX17->CLBLM_M_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX17" }, "CLBLM_L.CLBLM_IMUX18->CLBLM_M_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX18" }, "CLBLM_L.CLBLM_IMUX19->CLBLM_L_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX19" }, "CLBLM_L.CLBLM_IMUX2->CLBLM_M_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX2" }, "CLBLM_L.CLBLM_IMUX20->CLBLM_L_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX20" }, "CLBLM_L.CLBLM_IMUX21->CLBLM_L_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX21" }, "CLBLM_L.CLBLM_IMUX22->CLBLM_M_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX22" }, "CLBLM_L.CLBLM_IMUX23->CLBLM_L_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX23" }, "CLBLM_L.CLBLM_IMUX24->CLBLM_M_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX24" }, "CLBLM_L.CLBLM_IMUX25->CLBLM_L_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX25" }, "CLBLM_L.CLBLM_IMUX26->CLBLM_L_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX26" }, "CLBLM_L.CLBLM_IMUX27->CLBLM_M_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX27" }, "CLBLM_L.CLBLM_IMUX28->CLBLM_M_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX28" }, "CLBLM_L.CLBLM_IMUX29->CLBLM_M_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX29" }, "CLBLM_L.CLBLM_IMUX3->CLBLM_L_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX3" }, "CLBLM_L.CLBLM_IMUX30->CLBLM_L_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX30" }, "CLBLM_L.CLBLM_IMUX31->CLBLM_M_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX31" }, "CLBLM_L.CLBLM_IMUX32->CLBLM_M_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX32" }, "CLBLM_L.CLBLM_IMUX33->CLBLM_L_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX33" }, "CLBLM_L.CLBLM_IMUX34->CLBLM_L_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX34" }, "CLBLM_L.CLBLM_IMUX35->CLBLM_M_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX35" }, "CLBLM_L.CLBLM_IMUX36->CLBLM_L_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX36" }, "CLBLM_L.CLBLM_IMUX37->CLBLM_L_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX37" }, "CLBLM_L.CLBLM_IMUX38->CLBLM_M_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX38" }, "CLBLM_L.CLBLM_IMUX39->CLBLM_L_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX39" }, "CLBLM_L.CLBLM_IMUX4->CLBLM_M_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX4" }, "CLBLM_L.CLBLM_IMUX40->CLBLM_M_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX40" }, "CLBLM_L.CLBLM_IMUX41->CLBLM_L_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX41" }, "CLBLM_L.CLBLM_IMUX42->CLBLM_L_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX42" }, "CLBLM_L.CLBLM_IMUX43->CLBLM_M_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX43" }, "CLBLM_L.CLBLM_IMUX44->CLBLM_M_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX44" }, "CLBLM_L.CLBLM_IMUX45->CLBLM_M_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX45" }, "CLBLM_L.CLBLM_IMUX46->CLBLM_L_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX46" }, "CLBLM_L.CLBLM_IMUX47->CLBLM_M_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX47" }, "CLBLM_L.CLBLM_IMUX5->CLBLM_L_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX5" }, "CLBLM_L.CLBLM_IMUX6->CLBLM_L_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX6" }, "CLBLM_L.CLBLM_IMUX7->CLBLM_M_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX7" }, "CLBLM_L.CLBLM_IMUX8->CLBLM_M_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX8" }, "CLBLM_L.CLBLM_IMUX9->CLBLM_L_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX9" }, "CLBLM_L.CLBLM_L_A->>CLBLM_L_AMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.058", + "0.075", + "0.095" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_AMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.058", + "0.075", + "0.095" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A" }, "CLBLM_L.CLBLM_L_A->CLBLM_LOGIC_OUTS8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_A" }, "CLBLM_L.CLBLM_L_A1->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A1" }, "CLBLM_L.CLBLM_L_A2->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A2" }, "CLBLM_L.CLBLM_L_A3->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A3" }, "CLBLM_L.CLBLM_L_A4->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A4" }, "CLBLM_L.CLBLM_L_A5->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A5" }, "CLBLM_L.CLBLM_L_A6->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A6" }, "CLBLM_L.CLBLM_L_AMUX->CLBLM_LOGIC_OUTS16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_AMUX" }, "CLBLM_L.CLBLM_L_AQ->CLBLM_LOGIC_OUTS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_AQ" }, "CLBLM_L.CLBLM_L_B->>CLBLM_L_BMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_BMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B" }, "CLBLM_L.CLBLM_L_B->CLBLM_LOGIC_OUTS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_B" }, "CLBLM_L.CLBLM_L_B1->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B1" }, "CLBLM_L.CLBLM_L_B2->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B2" }, "CLBLM_L.CLBLM_L_B3->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B3" }, "CLBLM_L.CLBLM_L_B4->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B4" }, "CLBLM_L.CLBLM_L_B5->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B5" }, "CLBLM_L.CLBLM_L_B6->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B6" }, "CLBLM_L.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_BMUX" }, "CLBLM_L.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_BQ" }, "CLBLM_L.CLBLM_L_C->>CLBLM_L_CMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.073", + "0.092" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_CMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.073", + "0.092" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C" }, "CLBLM_L.CLBLM_L_C->CLBLM_LOGIC_OUTS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_C" }, "CLBLM_L.CLBLM_L_C1->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C1" }, "CLBLM_L.CLBLM_L_C2->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C2" }, "CLBLM_L.CLBLM_L_C3->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C3" }, "CLBLM_L.CLBLM_L_C4->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C4" }, "CLBLM_L.CLBLM_L_C5->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C5" }, "CLBLM_L.CLBLM_L_C6->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C6" }, "CLBLM_L.CLBLM_L_CMUX->CLBLM_LOGIC_OUTS18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_CMUX" }, "CLBLM_L.CLBLM_L_COUT->>CLBLM_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.089", + "0.109", + "0.137" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.072", + "0.089", + "0.109", + "0.137" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_COUT" }, "CLBLM_L.CLBLM_L_COUT->CLBLM_L_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_COUT" }, "CLBLM_L.CLBLM_L_CQ->CLBLM_LOGIC_OUTS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_CQ" }, "CLBLM_L.CLBLM_L_D->>CLBLM_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.073", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.073", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_D" }, "CLBLM_L.CLBLM_L_D->CLBLM_LOGIC_OUTS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_D" }, "CLBLM_L.CLBLM_L_D1->>CLBLM_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_D1" }, "CLBLM_L.CLBLM_L_D2->>CLBLM_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_D2" }, "CLBLM_L.CLBLM_L_D3->>CLBLM_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_D3" }, 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"dst_wire": "CLBLM_M_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_B4" }, "CLBLM_L.CLBLM_M_B5->>CLBLM_M_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_B5" }, "CLBLM_L.CLBLM_M_B6->>CLBLM_M_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_B6" }, "CLBLM_L.CLBLM_M_BMUX->CLBLM_LOGIC_OUTS21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_BMUX" }, "CLBLM_L.CLBLM_M_BQ->CLBLM_LOGIC_OUTS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_BQ" }, "CLBLM_L.CLBLM_M_C->>CLBLM_M_CMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.042", + "0.053", + "0.070", + "0.087" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_CMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.042", + "0.053", + "0.070", + "0.087" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C" }, "CLBLM_L.CLBLM_M_C->CLBLM_LOGIC_OUTS14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_C" }, "CLBLM_L.CLBLM_M_C1->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C1" }, "CLBLM_L.CLBLM_M_C2->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": 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+ "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C4" }, "CLBLM_L.CLBLM_M_C5->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C5" }, "CLBLM_L.CLBLM_M_C6->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C6" }, "CLBLM_L.CLBLM_M_CMUX->CLBLM_LOGIC_OUTS22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_CMUX" }, "CLBLM_L.CLBLM_M_COUT->>CLBLM_M_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.070", + "0.087", + "0.107", + "0.134" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.070", + "0.087", + "0.107", + "0.134" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_COUT" }, "CLBLM_L.CLBLM_M_COUT->CLBLM_M_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_COUT" }, "CLBLM_L.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_CQ" }, "CLBLM_L.CLBLM_M_D->>CLBLM_M_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.044", + "0.055", + "0.071", + "0.089" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.044", + "0.055", + "0.071", + "0.089" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D" }, "CLBLM_L.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_D" }, "CLBLM_L.CLBLM_M_D1->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D1" }, "CLBLM_L.CLBLM_M_D2->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D2" }, "CLBLM_L.CLBLM_M_D3->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D3" }, "CLBLM_L.CLBLM_M_D4->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D4" }, "CLBLM_L.CLBLM_M_D5->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D5" }, "CLBLM_L.CLBLM_M_D6->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D6" }, "CLBLM_L.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_DMUX" }, "CLBLM_L.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_DQ" } }, @@ -1063,51 +3304,456 @@ "name": "X1Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLM_L_A", - "A1": "CLBLM_L_A1", - "A2": "CLBLM_L_A2", - "A3": "CLBLM_L_A3", - "A4": "CLBLM_L_A4", - "A5": "CLBLM_L_A5", - "A6": "CLBLM_L_A6", - "AMUX": "CLBLM_L_AMUX", - "AQ": "CLBLM_L_AQ", - "AX": "CLBLM_L_AX", - "B": "CLBLM_L_B", - "B1": "CLBLM_L_B1", - "B2": "CLBLM_L_B2", - "B3": "CLBLM_L_B3", - "B4": "CLBLM_L_B4", - "B5": "CLBLM_L_B5", - "B6": "CLBLM_L_B6", - "BMUX": "CLBLM_L_BMUX", - "BQ": "CLBLM_L_BQ", - "BX": "CLBLM_L_BX", - "C": "CLBLM_L_C", - "C1": "CLBLM_L_C1", - "C2": "CLBLM_L_C2", - "C3": "CLBLM_L_C3", - "C4": "CLBLM_L_C4", - "C5": "CLBLM_L_C5", - "C6": "CLBLM_L_C6", - "CE": "CLBLM_L_CE", - "CIN": "CLBLM_L_CIN", - "CLK": "CLBLM_L_CLK", - "CMUX": "CLBLM_L_CMUX", - "COUT": "CLBLM_L_COUT", - "CQ": "CLBLM_L_CQ", - "CX": "CLBLM_L_CX", - "D": "CLBLM_L_D", - "D1": "CLBLM_L_D1", - "D2": "CLBLM_L_D2", - "D3": "CLBLM_L_D3", - "D4": "CLBLM_L_D4", - "D5": "CLBLM_L_D5", - "D6": "CLBLM_L_D6", - "DMUX": "CLBLM_L_DMUX", - "DQ": "CLBLM_L_DQ", - "DX": "CLBLM_L_DX", - "SR": "CLBLM_L_SR" + "A": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "835.1804999999999", + "wire": "CLBLM_L_A" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.133", + "0.165", + "0.217", + "0.257" + ], + "wire": "CLBLM_L_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.130", + "0.162", + "0.212", + "0.250" + ], + "wire": "CLBLM_L_A2" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.078", + "0.097", + "0.138", + "0.163" + ], + "wire": "CLBLM_L_A3" + }, + "A4": { + "cap": "0.000", + "delay": [ + "0.064", + "0.080", + "0.113", + "0.134" + ], + "wire": "CLBLM_L_A4" + }, + "A5": { + "cap": "0.000", + "delay": [ + "0.026", + "0.032", + "0.042", + "0.050" + ], + "wire": "CLBLM_L_A5" + }, + "A6": { + "cap": "0.000", + "delay": [ + "0.002", + "0.002", + "0.002", + "0.003" + ], + "wire": "CLBLM_L_A6" + }, + "AMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "894.144625", + "wire": "CLBLM_L_AMUX" + }, + "AQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLM_L_AQ" + }, + "AX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_AX" + }, + "B": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "810.616125", + "wire": "CLBLM_L_B" + }, + "B1": { + "cap": "0.000", + "delay": [ + "0.133", + "0.165", + "0.217", + "0.257" + ], + "wire": "CLBLM_L_B1" + }, + "B2": { + "cap": "0.000", + "delay": [ + "0.129", + "0.161", + "0.213", + "0.251" + ], + "wire": "CLBLM_L_B2" + }, + "B3": { + "cap": "0.000", + "delay": [ + "0.080", + "0.100", + "0.142", + "0.168" + ], + "wire": "CLBLM_L_B3" + }, + "B4": { + "cap": "0.000", + "delay": [ + "0.065", + "0.081", + "0.113", + "0.134" + ], + "wire": "CLBLM_L_B4" + }, + "B5": { + "cap": "0.000", + "delay": [ + "0.027", + "0.033", + "0.043", + "0.051" + ], + "wire": "CLBLM_L_B5" + }, + "B6": { + "cap": "0.000", + "delay": [ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLBLM_L_B6" + }, + "BMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "884.3346875000001", + "wire": "CLBLM_L_BMUX" + }, + "BQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLM_L_BQ" + }, + "BX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_BX" + }, + "C": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "808.31575", + "wire": "CLBLM_L_C" + }, + "C1": { + "cap": "0.000", + "delay": [ + "0.133", + "0.165", + "0.217", + "0.257" + ], + "wire": "CLBLM_L_C1" + }, + "C2": { + "cap": "0.000", + "delay": [ + "0.129", + "0.161", + "0.212", + "0.250" + ], + "wire": "CLBLM_L_C2" + }, + "C3": { + "cap": "0.000", + "delay": [ + "0.080", + "0.100", + "0.142", + "0.168" + ], + "wire": "CLBLM_L_C3" + }, + "C4": { + "cap": "0.000", + "delay": [ + "0.065", + "0.081", + "0.114", + "0.135" + ], + "wire": "CLBLM_L_C4" + }, + "C5": { + "cap": "0.000", + "delay": [ + "0.026", + "0.032", + "0.044", + "0.052" + ], + "wire": "CLBLM_L_C5" + }, + "C6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_C6" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CE" + }, + "CIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CIN" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CLK" + }, + "CMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "858.1766875000001", + "wire": "CLBLM_L_CMUX" + }, + "COUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "CLBLM_L_COUT" + }, + "CQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLM_L_CQ" + }, + "CX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CX" + }, + "D": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "810.3796249999999", + "wire": "CLBLM_L_D" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.135", + "0.168", + "0.221", + "0.262" + ], + "wire": "CLBLM_L_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.131", + "0.163", + "0.213", + "0.252" + ], + "wire": "CLBLM_L_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.079", + "0.099", + "0.141", + "0.167" + ], + "wire": "CLBLM_L_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.066", + "0.082", + "0.116", + "0.138" + ], + "wire": "CLBLM_L_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.026", + "0.032", + "0.042", + "0.050" + ], + "wire": "CLBLM_L_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.002", + "0.002", + "0.002", + "0.003" + ], + "wire": "CLBLM_L_D6" + }, + "DMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "825.0027499999999", + "wire": "CLBLM_L_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLM_L_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_SR" + } }, "type": "SLICEL", "x_coord": 1, @@ -1117,56 +3763,506 @@ "name": "X0Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLM_M_A", - "A1": "CLBLM_M_A1", - "A2": "CLBLM_M_A2", - "A3": "CLBLM_M_A3", - "A4": "CLBLM_M_A4", - "A5": "CLBLM_M_A5", - "A6": "CLBLM_M_A6", - "AI": "CLBLM_M_AI", - "AMUX": "CLBLM_M_AMUX", - "AQ": "CLBLM_M_AQ", - "AX": "CLBLM_M_AX", - "B": "CLBLM_M_B", - "B1": "CLBLM_M_B1", - "B2": "CLBLM_M_B2", - "B3": "CLBLM_M_B3", - "B4": "CLBLM_M_B4", - "B5": "CLBLM_M_B5", - "B6": "CLBLM_M_B6", - "BI": "CLBLM_M_BI", - "BMUX": "CLBLM_M_BMUX", - "BQ": "CLBLM_M_BQ", - "BX": "CLBLM_M_BX", - "C": "CLBLM_M_C", - "C1": "CLBLM_M_C1", - "C2": "CLBLM_M_C2", - "C3": "CLBLM_M_C3", - "C4": "CLBLM_M_C4", - "C5": "CLBLM_M_C5", - "C6": "CLBLM_M_C6", - "CE": "CLBLM_M_CE", - "CI": "CLBLM_M_CI", - "CIN": "CLBLM_M_CIN", - "CLK": "CLBLM_M_CLK", - "CMUX": "CLBLM_M_CMUX", - "COUT": "CLBLM_M_COUT", - "CQ": "CLBLM_M_CQ", - "CX": "CLBLM_M_CX", - "D": "CLBLM_M_D", - "D1": "CLBLM_M_D1", - "D2": "CLBLM_M_D2", - "D3": "CLBLM_M_D3", - "D4": "CLBLM_M_D4", - "D5": "CLBLM_M_D5", - "D6": "CLBLM_M_D6", - "DI": "CLBLM_M_DI", - "DMUX": "CLBLM_M_DMUX", - "DQ": "CLBLM_M_DQ", - "DX": "CLBLM_M_DX", - "SR": "CLBLM_M_SR", - "WE": "CLBLM_M_WE" + "A": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "834.5342499999999", + "wire": "CLBLM_M_A" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.143", + "0.178", + "0.226", + "0.268" + ], + "wire": "CLBLM_M_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.136", + "0.170", + "0.216", + "0.256" + ], + "wire": "CLBLM_M_A2" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.088", + "0.109", + "0.150", + "0.178" + ], + "wire": "CLBLM_M_A3" + }, + "A4": { + "cap": "0.000", + "delay": [ + "0.071", + "0.088", + "0.124", + "0.146" + ], + "wire": "CLBLM_M_A4" + }, + "A5": { + "cap": "0.000", + "delay": [ + "0.030", + "0.037", + "0.052", + "0.061" + ], + "wire": "CLBLM_M_A5" + }, + "A6": { + "cap": "0.000", + "delay": [ + "0.005", + "0.006", + "0.007", + "0.009" + ], + "wire": "CLBLM_M_A6" + }, + "AI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_AI" + }, + "AMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "803.0701250000001", + "wire": "CLBLM_M_AMUX" + }, + "AQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLM_M_AQ" + }, + "AX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_AX" + }, + "B": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "869.1326875", + "wire": "CLBLM_M_B" + }, + "B1": { + "cap": "0.000", + "delay": [ + "0.140", + "0.175", + "0.223", + "0.264" + ], + "wire": "CLBLM_M_B1" + }, + "B2": { + "cap": "0.000", + "delay": [ + "0.136", + "0.170", + "0.215", + "0.254" + ], + "wire": "CLBLM_M_B2" + }, + "B3": { + "cap": "0.000", + "delay": [ + "0.088", + "0.109", + "0.151", + "0.179" + ], + "wire": "CLBLM_M_B3" + }, + "B4": { + "cap": "0.000", + "delay": [ + "0.071", + "0.088", + "0.124", + "0.146" + ], + "wire": "CLBLM_M_B4" + }, + "B5": { + "cap": "0.000", + "delay": [ + "0.032", + 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"CLBLM_M_WE" + } }, "type": "SLICEM", "x_coord": 0, @@ -1174,321 +4270,417 @@ } ], "tile_type": "CLBLM_L", - "wires": [ - "CLBLM_BYP0", - "CLBLM_BYP1", - "CLBLM_BYP2", - "CLBLM_BYP3", - "CLBLM_BYP4", - "CLBLM_BYP5", - "CLBLM_BYP6", - "CLBLM_BYP7", - "CLBLM_CLK0", - "CLBLM_CLK1", - "CLBLM_CTRL0", - "CLBLM_CTRL1", - "CLBLM_EE2A0", - "CLBLM_EE2A1", - "CLBLM_EE2A2", - "CLBLM_EE2A3", - "CLBLM_EE2BEG0", - "CLBLM_EE2BEG1", - "CLBLM_EE2BEG2", - "CLBLM_EE2BEG3", - "CLBLM_EE4A0", - "CLBLM_EE4A1", - "CLBLM_EE4A2", - "CLBLM_EE4A3", - "CLBLM_EE4B0", - "CLBLM_EE4B1", - "CLBLM_EE4B2", - "CLBLM_EE4B3", - "CLBLM_EE4BEG0", - "CLBLM_EE4BEG1", - "CLBLM_EE4BEG2", - "CLBLM_EE4BEG3", - "CLBLM_EE4C0", - "CLBLM_EE4C1", - "CLBLM_EE4C2", - "CLBLM_EE4C3", - "CLBLM_EL1BEG0", - "CLBLM_EL1BEG1", - "CLBLM_EL1BEG2", - "CLBLM_EL1BEG3", - "CLBLM_ER1BEG0", - "CLBLM_ER1BEG1", - "CLBLM_ER1BEG2", - "CLBLM_ER1BEG3", - "CLBLM_FAN0", - "CLBLM_FAN1", - "CLBLM_FAN2", - "CLBLM_FAN3", - "CLBLM_FAN4", - "CLBLM_FAN5", - "CLBLM_FAN6", - "CLBLM_FAN7", - "CLBLM_IMUX0", - "CLBLM_IMUX1", - "CLBLM_IMUX10", - "CLBLM_IMUX11", - "CLBLM_IMUX12", - "CLBLM_IMUX13", - "CLBLM_IMUX14", - "CLBLM_IMUX15", - "CLBLM_IMUX16", - "CLBLM_IMUX17", - "CLBLM_IMUX18", - "CLBLM_IMUX19", - "CLBLM_IMUX2", - "CLBLM_IMUX20", - "CLBLM_IMUX21", - "CLBLM_IMUX22", - "CLBLM_IMUX23", - "CLBLM_IMUX24", - "CLBLM_IMUX25", - "CLBLM_IMUX26", - "CLBLM_IMUX27", - "CLBLM_IMUX28", - "CLBLM_IMUX29", - "CLBLM_IMUX3", - "CLBLM_IMUX30", - "CLBLM_IMUX31", - "CLBLM_IMUX32", - "CLBLM_IMUX33", - "CLBLM_IMUX34", - "CLBLM_IMUX35", - "CLBLM_IMUX36", - "CLBLM_IMUX37", - "CLBLM_IMUX38", - "CLBLM_IMUX39", - "CLBLM_IMUX4", - "CLBLM_IMUX40", - "CLBLM_IMUX41", - "CLBLM_IMUX42", - "CLBLM_IMUX43", - "CLBLM_IMUX44", - "CLBLM_IMUX45", - "CLBLM_IMUX46", - "CLBLM_IMUX47", - "CLBLM_IMUX5", - "CLBLM_IMUX6", - "CLBLM_IMUX7", - "CLBLM_IMUX8", - "CLBLM_IMUX9", - "CLBLM_LH1", - "CLBLM_LH10", - "CLBLM_LH11", - "CLBLM_LH12", - "CLBLM_LH2", - "CLBLM_LH3", - "CLBLM_LH4", - "CLBLM_LH5", - "CLBLM_LH6", - "CLBLM_LH7", - "CLBLM_LH8", - "CLBLM_LH9", - "CLBLM_LOGIC_OUTS0", - "CLBLM_LOGIC_OUTS1", - "CLBLM_LOGIC_OUTS10", - "CLBLM_LOGIC_OUTS11", - "CLBLM_LOGIC_OUTS12", - "CLBLM_LOGIC_OUTS13", - "CLBLM_LOGIC_OUTS14", - "CLBLM_LOGIC_OUTS15", - "CLBLM_LOGIC_OUTS16", - "CLBLM_LOGIC_OUTS17", - "CLBLM_LOGIC_OUTS18", - "CLBLM_LOGIC_OUTS19", - "CLBLM_LOGIC_OUTS2", - "CLBLM_LOGIC_OUTS20", - "CLBLM_LOGIC_OUTS21", - "CLBLM_LOGIC_OUTS22", - "CLBLM_LOGIC_OUTS23", - "CLBLM_LOGIC_OUTS3", - "CLBLM_LOGIC_OUTS4", - "CLBLM_LOGIC_OUTS5", - "CLBLM_LOGIC_OUTS6", - "CLBLM_LOGIC_OUTS7", - "CLBLM_LOGIC_OUTS8", - "CLBLM_LOGIC_OUTS9", - "CLBLM_L_A", - "CLBLM_L_A1", - "CLBLM_L_A2", - "CLBLM_L_A3", - "CLBLM_L_A4", - "CLBLM_L_A5", - "CLBLM_L_A6", - "CLBLM_L_AMUX", - "CLBLM_L_AQ", - "CLBLM_L_AX", - "CLBLM_L_B", - "CLBLM_L_B1", - "CLBLM_L_B2", - "CLBLM_L_B3", - "CLBLM_L_B4", - "CLBLM_L_B5", - "CLBLM_L_B6", - "CLBLM_L_BMUX", - "CLBLM_L_BQ", - "CLBLM_L_BX", - "CLBLM_L_C", - "CLBLM_L_C1", - "CLBLM_L_C2", - "CLBLM_L_C3", - "CLBLM_L_C4", - "CLBLM_L_C5", - "CLBLM_L_C6", - "CLBLM_L_CE", - "CLBLM_L_CIN", - "CLBLM_L_CLK", - "CLBLM_L_CMUX", - "CLBLM_L_COUT", - "CLBLM_L_COUT_N", - "CLBLM_L_CQ", - "CLBLM_L_CX", - "CLBLM_L_D", - "CLBLM_L_D1", - "CLBLM_L_D2", - "CLBLM_L_D3", - "CLBLM_L_D4", - "CLBLM_L_D5", - "CLBLM_L_D6", - "CLBLM_L_DMUX", - "CLBLM_L_DQ", - "CLBLM_L_DX", - "CLBLM_L_SR", - "CLBLM_MONITOR_N", - "CLBLM_MONITOR_P", - "CLBLM_M_A", - "CLBLM_M_A1", - "CLBLM_M_A2", - "CLBLM_M_A3", - "CLBLM_M_A4", - "CLBLM_M_A5", - "CLBLM_M_A6", - "CLBLM_M_AI", - "CLBLM_M_AMUX", - "CLBLM_M_AQ", - "CLBLM_M_AX", - "CLBLM_M_B", - "CLBLM_M_B1", - "CLBLM_M_B2", - "CLBLM_M_B3", - "CLBLM_M_B4", - "CLBLM_M_B5", - "CLBLM_M_B6", - "CLBLM_M_BI", - "CLBLM_M_BMUX", - "CLBLM_M_BQ", - "CLBLM_M_BX", - "CLBLM_M_C", - "CLBLM_M_C1", - "CLBLM_M_C2", - "CLBLM_M_C3", - "CLBLM_M_C4", - "CLBLM_M_C5", - "CLBLM_M_C6", - "CLBLM_M_CE", - "CLBLM_M_CI", - "CLBLM_M_CIN", - "CLBLM_M_CLK", - "CLBLM_M_CMUX", - "CLBLM_M_COUT", - "CLBLM_M_COUT_N", - "CLBLM_M_CQ", - "CLBLM_M_CX", - "CLBLM_M_D", - "CLBLM_M_D1", - "CLBLM_M_D2", - "CLBLM_M_D3", - "CLBLM_M_D4", - "CLBLM_M_D5", - "CLBLM_M_D6", - "CLBLM_M_DI", - "CLBLM_M_DMUX", - "CLBLM_M_DQ", - "CLBLM_M_DX", - "CLBLM_M_SR", - "CLBLM_M_WE", - "CLBLM_NE2A0", - "CLBLM_NE2A1", - "CLBLM_NE2A2", - "CLBLM_NE2A3", - "CLBLM_NE4BEG0", - "CLBLM_NE4BEG1", - "CLBLM_NE4BEG2", - "CLBLM_NE4BEG3", - "CLBLM_NE4C0", - "CLBLM_NE4C1", - "CLBLM_NE4C2", - "CLBLM_NE4C3", - "CLBLM_NW2A0", - "CLBLM_NW2A1", - "CLBLM_NW2A2", - "CLBLM_NW2A3", - "CLBLM_NW4A0", - "CLBLM_NW4A1", - "CLBLM_NW4A2", - "CLBLM_NW4A3", - "CLBLM_NW4END0", - "CLBLM_NW4END1", - "CLBLM_NW4END2", - "CLBLM_NW4END3", - "CLBLM_SE2A0", - "CLBLM_SE2A1", - "CLBLM_SE2A2", - "CLBLM_SE2A3", - "CLBLM_SE4BEG0", - "CLBLM_SE4BEG1", - "CLBLM_SE4BEG2", - "CLBLM_SE4BEG3", - "CLBLM_SE4C0", - "CLBLM_SE4C1", - "CLBLM_SE4C2", - "CLBLM_SE4C3", - "CLBLM_SW2A0", - "CLBLM_SW2A1", - "CLBLM_SW2A2", - "CLBLM_SW2A3", - "CLBLM_SW4A0", - "CLBLM_SW4A1", - "CLBLM_SW4A2", - "CLBLM_SW4A3", - "CLBLM_SW4END0", - "CLBLM_SW4END1", - "CLBLM_SW4END2", - "CLBLM_SW4END3", - "CLBLM_WL1END0", - "CLBLM_WL1END1", - "CLBLM_WL1END2", - "CLBLM_WL1END3", - "CLBLM_WR1END0", - "CLBLM_WR1END1", - "CLBLM_WR1END2", - "CLBLM_WR1END3", - "CLBLM_WW2A0", - "CLBLM_WW2A1", - "CLBLM_WW2A2", - "CLBLM_WW2A3", - "CLBLM_WW2END0", - "CLBLM_WW2END1", - "CLBLM_WW2END2", - "CLBLM_WW2END3", - "CLBLM_WW4A0", - "CLBLM_WW4A1", - "CLBLM_WW4A2", - "CLBLM_WW4A3", - "CLBLM_WW4B0", - "CLBLM_WW4B1", - "CLBLM_WW4B2", - "CLBLM_WW4B3", - "CLBLM_WW4C0", - "CLBLM_WW4C1", - "CLBLM_WW4C2", - "CLBLM_WW4C3", - "CLBLM_WW4END0", - "CLBLM_WW4END1", - "CLBLM_WW4END2", - "CLBLM_WW4END3" - ] + "wires": { + "CLBLM_BYP0": null, + "CLBLM_BYP1": null, + "CLBLM_BYP2": null, + "CLBLM_BYP3": null, + "CLBLM_BYP4": null, + "CLBLM_BYP5": null, + "CLBLM_BYP6": null, + "CLBLM_BYP7": null, + "CLBLM_CLK0": null, + "CLBLM_CLK1": null, + "CLBLM_CTRL0": null, + "CLBLM_CTRL1": null, + "CLBLM_EE2A0": null, + "CLBLM_EE2A1": null, + "CLBLM_EE2A2": null, + "CLBLM_EE2A3": null, + "CLBLM_EE2BEG0": null, + "CLBLM_EE2BEG1": null, + "CLBLM_EE2BEG2": null, + "CLBLM_EE2BEG3": null, + "CLBLM_EE4A0": null, + "CLBLM_EE4A1": null, + "CLBLM_EE4A2": null, + "CLBLM_EE4A3": null, + "CLBLM_EE4B0": null, + "CLBLM_EE4B1": null, + "CLBLM_EE4B2": null, + "CLBLM_EE4B3": null, + "CLBLM_EE4BEG0": null, + "CLBLM_EE4BEG1": null, + "CLBLM_EE4BEG2": null, + "CLBLM_EE4BEG3": null, + "CLBLM_EE4C0": null, + "CLBLM_EE4C1": null, + "CLBLM_EE4C2": null, + "CLBLM_EE4C3": null, + "CLBLM_EL1BEG0": { + "cap": "5.223", + "res": "52.531" + }, + "CLBLM_EL1BEG1": { + "cap": "5.223", + "res": "52.531" + }, + "CLBLM_EL1BEG2": { + "cap": "5.223", + "res": "52.531" + }, + "CLBLM_EL1BEG3": { + "cap": "5.223", + "res": "52.531" + }, + "CLBLM_ER1BEG0": { + "cap": "6.083", + "res": "90.578" + }, + "CLBLM_ER1BEG1": { + "cap": "6.083", + "res": "90.578" + }, + "CLBLM_ER1BEG2": { + "cap": "6.083", + "res": "90.578" + }, + "CLBLM_ER1BEG3": { + "cap": "6.083", + "res": "90.578" + }, + "CLBLM_FAN0": null, + "CLBLM_FAN1": null, + "CLBLM_FAN2": null, + "CLBLM_FAN3": null, + "CLBLM_FAN4": null, + "CLBLM_FAN5": null, + "CLBLM_FAN6": null, + "CLBLM_FAN7": null, + "CLBLM_IMUX0": null, + "CLBLM_IMUX1": null, + "CLBLM_IMUX10": null, + "CLBLM_IMUX11": null, + "CLBLM_IMUX12": null, + "CLBLM_IMUX13": null, + "CLBLM_IMUX14": null, + "CLBLM_IMUX15": null, + "CLBLM_IMUX16": null, + "CLBLM_IMUX17": null, + "CLBLM_IMUX18": null, + "CLBLM_IMUX19": null, + "CLBLM_IMUX2": null, + "CLBLM_IMUX20": null, + "CLBLM_IMUX21": null, + "CLBLM_IMUX22": null, + "CLBLM_IMUX23": null, + "CLBLM_IMUX24": null, + "CLBLM_IMUX25": null, + "CLBLM_IMUX26": null, + "CLBLM_IMUX27": null, + "CLBLM_IMUX28": null, + "CLBLM_IMUX29": null, + "CLBLM_IMUX3": null, + "CLBLM_IMUX30": null, + "CLBLM_IMUX31": null, + "CLBLM_IMUX32": null, + "CLBLM_IMUX33": null, + "CLBLM_IMUX34": null, + "CLBLM_IMUX35": null, + "CLBLM_IMUX36": null, + "CLBLM_IMUX37": null, + "CLBLM_IMUX38": null, + "CLBLM_IMUX39": null, + "CLBLM_IMUX4": null, + "CLBLM_IMUX40": null, + "CLBLM_IMUX41": null, + "CLBLM_IMUX42": null, + "CLBLM_IMUX43": null, + "CLBLM_IMUX44": null, + "CLBLM_IMUX45": null, + "CLBLM_IMUX46": null, + "CLBLM_IMUX47": null, + "CLBLM_IMUX5": null, + "CLBLM_IMUX6": null, + "CLBLM_IMUX7": null, + "CLBLM_IMUX8": null, + "CLBLM_IMUX9": null, + "CLBLM_LH1": null, + "CLBLM_LH10": null, + "CLBLM_LH11": null, + "CLBLM_LH12": null, + "CLBLM_LH2": null, + "CLBLM_LH3": null, + "CLBLM_LH4": null, + "CLBLM_LH5": null, + "CLBLM_LH6": null, + "CLBLM_LH7": null, + "CLBLM_LH8": null, + "CLBLM_LH9": null, + "CLBLM_LOGIC_OUTS0": null, + "CLBLM_LOGIC_OUTS1": null, + "CLBLM_LOGIC_OUTS10": null, + "CLBLM_LOGIC_OUTS11": null, + "CLBLM_LOGIC_OUTS12": null, + "CLBLM_LOGIC_OUTS13": null, + "CLBLM_LOGIC_OUTS14": null, + "CLBLM_LOGIC_OUTS15": null, + "CLBLM_LOGIC_OUTS16": null, + "CLBLM_LOGIC_OUTS17": null, + "CLBLM_LOGIC_OUTS18": null, + "CLBLM_LOGIC_OUTS19": null, + "CLBLM_LOGIC_OUTS2": null, + "CLBLM_LOGIC_OUTS20": null, + "CLBLM_LOGIC_OUTS21": null, + "CLBLM_LOGIC_OUTS22": null, + "CLBLM_LOGIC_OUTS23": null, + "CLBLM_LOGIC_OUTS3": null, + "CLBLM_LOGIC_OUTS4": null, + "CLBLM_LOGIC_OUTS5": null, + "CLBLM_LOGIC_OUTS6": null, + "CLBLM_LOGIC_OUTS7": null, + "CLBLM_LOGIC_OUTS8": null, + "CLBLM_LOGIC_OUTS9": null, + "CLBLM_L_A": null, + "CLBLM_L_A1": null, + "CLBLM_L_A2": null, + "CLBLM_L_A3": null, + "CLBLM_L_A4": null, + "CLBLM_L_A5": null, + "CLBLM_L_A6": null, + "CLBLM_L_AMUX": null, + "CLBLM_L_AQ": null, + "CLBLM_L_AX": null, + "CLBLM_L_B": null, + "CLBLM_L_B1": null, + "CLBLM_L_B2": null, + "CLBLM_L_B3": null, + "CLBLM_L_B4": null, + "CLBLM_L_B5": null, + "CLBLM_L_B6": null, + "CLBLM_L_BMUX": null, + "CLBLM_L_BQ": null, + "CLBLM_L_BX": null, + "CLBLM_L_C": null, + "CLBLM_L_C1": null, + "CLBLM_L_C2": null, + "CLBLM_L_C3": null, + "CLBLM_L_C4": null, + "CLBLM_L_C5": null, + "CLBLM_L_C6": null, + "CLBLM_L_CE": null, + "CLBLM_L_CIN": null, + "CLBLM_L_CLK": null, + "CLBLM_L_CMUX": null, + "CLBLM_L_COUT": null, + "CLBLM_L_COUT_N": null, + "CLBLM_L_CQ": null, + "CLBLM_L_CX": null, + "CLBLM_L_D": null, + "CLBLM_L_D1": null, + "CLBLM_L_D2": null, + "CLBLM_L_D3": null, + "CLBLM_L_D4": null, + "CLBLM_L_D5": null, + "CLBLM_L_D6": null, + "CLBLM_L_DMUX": null, + "CLBLM_L_DQ": null, + "CLBLM_L_DX": null, + "CLBLM_L_SR": null, + "CLBLM_MONITOR_N": null, + "CLBLM_MONITOR_P": null, + "CLBLM_M_A": null, + "CLBLM_M_A1": null, + "CLBLM_M_A2": null, + "CLBLM_M_A3": null, + "CLBLM_M_A4": null, + "CLBLM_M_A5": null, + "CLBLM_M_A6": null, + "CLBLM_M_AI": null, + "CLBLM_M_AMUX": null, + "CLBLM_M_AQ": null, + "CLBLM_M_AX": null, + "CLBLM_M_B": null, + "CLBLM_M_B1": null, + "CLBLM_M_B2": null, + "CLBLM_M_B3": null, + "CLBLM_M_B4": null, + "CLBLM_M_B5": null, + "CLBLM_M_B6": null, + "CLBLM_M_BI": null, + "CLBLM_M_BMUX": null, + "CLBLM_M_BQ": null, + "CLBLM_M_BX": null, + "CLBLM_M_C": null, + "CLBLM_M_C1": null, + "CLBLM_M_C2": null, + "CLBLM_M_C3": null, + "CLBLM_M_C4": null, + "CLBLM_M_C5": null, + "CLBLM_M_C6": null, + "CLBLM_M_CE": null, + "CLBLM_M_CI": null, + "CLBLM_M_CIN": null, + "CLBLM_M_CLK": null, + "CLBLM_M_CMUX": null, + "CLBLM_M_COUT": null, + "CLBLM_M_COUT_N": null, + "CLBLM_M_CQ": null, + "CLBLM_M_CX": null, + "CLBLM_M_D": null, + "CLBLM_M_D1": null, + "CLBLM_M_D2": null, + "CLBLM_M_D3": null, + "CLBLM_M_D4": null, + "CLBLM_M_D5": null, + "CLBLM_M_D6": null, + "CLBLM_M_DI": null, + "CLBLM_M_DMUX": null, + "CLBLM_M_DQ": null, + "CLBLM_M_DX": null, + "CLBLM_M_SR": null, + "CLBLM_M_WE": null, + "CLBLM_NE2A0": { + "cap": "6.623", + "res": "102.520" + }, + "CLBLM_NE2A1": { + "cap": "6.623", + "res": "102.520" + }, + "CLBLM_NE2A2": { + "cap": "6.623", + "res": "102.520" + }, + "CLBLM_NE2A3": { + "cap": "6.623", + "res": "102.520" + }, + "CLBLM_NE4BEG0": null, + "CLBLM_NE4BEG1": null, + "CLBLM_NE4BEG2": null, + "CLBLM_NE4BEG3": null, + "CLBLM_NE4C0": null, + "CLBLM_NE4C1": null, + "CLBLM_NE4C2": null, + "CLBLM_NE4C3": null, + "CLBLM_NW2A0": { + "cap": "6.905", + "res": "93.135" + }, + "CLBLM_NW2A1": { + "cap": "6.905", + "res": "93.135" + }, + "CLBLM_NW2A2": { + "cap": "6.905", + "res": "93.135" + }, + "CLBLM_NW2A3": { + "cap": "6.905", + "res": "93.135" + }, + "CLBLM_NW4A0": null, + "CLBLM_NW4A1": null, + "CLBLM_NW4A2": null, + "CLBLM_NW4A3": null, + "CLBLM_NW4END0": null, + "CLBLM_NW4END1": null, + "CLBLM_NW4END2": null, + "CLBLM_NW4END3": null, + "CLBLM_SE2A0": { + "cap": "6.347", + "res": "91.805" + }, + "CLBLM_SE2A1": { + "cap": "6.347", + "res": "91.805" + }, + "CLBLM_SE2A2": { + "cap": "6.347", + "res": "91.805" + }, + "CLBLM_SE2A3": { + "cap": "6.347", + "res": "91.805" + }, + "CLBLM_SE4BEG0": null, + "CLBLM_SE4BEG1": null, + "CLBLM_SE4BEG2": null, + "CLBLM_SE4BEG3": null, + "CLBLM_SE4C0": null, + "CLBLM_SE4C1": null, + "CLBLM_SE4C2": null, + "CLBLM_SE4C3": null, + "CLBLM_SW2A0": { + "cap": "6.966", + "res": "91.419" + }, + "CLBLM_SW2A1": { + "cap": "6.966", + "res": "91.419" + }, + "CLBLM_SW2A2": { + "cap": "6.966", + "res": "91.419" + }, + "CLBLM_SW2A3": { + "cap": "6.966", + "res": "91.419" + }, + "CLBLM_SW4A0": null, + "CLBLM_SW4A1": null, + "CLBLM_SW4A2": null, + "CLBLM_SW4A3": null, + "CLBLM_SW4END0": null, + "CLBLM_SW4END1": null, + "CLBLM_SW4END2": null, + "CLBLM_SW4END3": null, + "CLBLM_WL1END0": { + "cap": "6.547", + "res": "59.551" + }, + "CLBLM_WL1END1": { + "cap": "6.547", + "res": "59.551" + }, + "CLBLM_WL1END2": { + "cap": "6.547", + "res": "59.551" + }, + "CLBLM_WL1END3": { + "cap": "6.547", + "res": "59.551" + }, + "CLBLM_WR1END0": { + "cap": "6.641", + "res": "93.569" + }, + "CLBLM_WR1END1": { + "cap": "6.641", + "res": "93.569" + }, + "CLBLM_WR1END2": { + "cap": "6.641", + "res": "93.569" + }, + "CLBLM_WR1END3": { + "cap": "6.641", + "res": "93.569" + }, + "CLBLM_WW2A0": null, + "CLBLM_WW2A1": null, + "CLBLM_WW2A2": null, + "CLBLM_WW2A3": null, + "CLBLM_WW2END0": null, + "CLBLM_WW2END1": null, + "CLBLM_WW2END2": null, + "CLBLM_WW2END3": null, + "CLBLM_WW4A0": null, + "CLBLM_WW4A1": null, + "CLBLM_WW4A2": null, + "CLBLM_WW4A3": null, + "CLBLM_WW4B0": null, + "CLBLM_WW4B1": null, + "CLBLM_WW4B2": null, + "CLBLM_WW4B3": null, + "CLBLM_WW4C0": null, + "CLBLM_WW4C1": null, + "CLBLM_WW4C2": null, + "CLBLM_WW4C3": null, + "CLBLM_WW4END0": null, + "CLBLM_WW4END1": null, + "CLBLM_WW4END2": null, + "CLBLM_WW4END3": null + } } diff --git a/kintex7/tile_type_CLBLM_R.json b/kintex7/tile_type_CLBLM_R.json index 466403b..fea07f8 100644 --- a/kintex7/tile_type_CLBLM_R.json +++ b/kintex7/tile_type_CLBLM_R.json @@ -2,1059 +2,3300 @@ "pips": { "CLBLM_R.CLBLM_BYP0->CLBLM_L_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP0" }, "CLBLM_R.CLBLM_BYP1->CLBLM_M_AX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_AX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP1" }, "CLBLM_R.CLBLM_BYP2->CLBLM_L_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP2" }, "CLBLM_R.CLBLM_BYP3->CLBLM_M_CX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP3" }, "CLBLM_R.CLBLM_BYP4->CLBLM_M_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP4" }, "CLBLM_R.CLBLM_BYP5->CLBLM_L_BX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_BX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP5" }, "CLBLM_R.CLBLM_BYP6->CLBLM_M_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP6" }, "CLBLM_R.CLBLM_BYP7->CLBLM_L_DX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_DX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_BYP7" }, "CLBLM_R.CLBLM_CLK0->CLBLM_L_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CLK0" }, "CLBLM_R.CLBLM_CLK1->CLBLM_M_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CLK1" }, "CLBLM_R.CLBLM_CTRL0->CLBLM_L_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CTRL0" }, "CLBLM_R.CLBLM_CTRL1->CLBLM_M_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_CTRL1" }, "CLBLM_R.CLBLM_FAN0->CLBLM_M_AI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_AI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN0" }, "CLBLM_R.CLBLM_FAN2->CLBLM_M_BI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_BI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN2" }, "CLBLM_R.CLBLM_FAN3->CLBLM_M_DI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_DI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN3" }, "CLBLM_R.CLBLM_FAN4->CLBLM_M_WE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_WE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN4" }, "CLBLM_R.CLBLM_FAN5->CLBLM_M_CI": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CI", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN5" }, "CLBLM_R.CLBLM_FAN6->CLBLM_L_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN6" }, "CLBLM_R.CLBLM_FAN7->CLBLM_M_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_FAN7" }, "CLBLM_R.CLBLM_IMUX0->CLBLM_L_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX0" }, "CLBLM_R.CLBLM_IMUX1->CLBLM_M_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX1" }, "CLBLM_R.CLBLM_IMUX10->CLBLM_L_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX10" }, "CLBLM_R.CLBLM_IMUX11->CLBLM_M_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX11" }, "CLBLM_R.CLBLM_IMUX12->CLBLM_M_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX12" }, "CLBLM_R.CLBLM_IMUX13->CLBLM_L_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX13" }, "CLBLM_R.CLBLM_IMUX14->CLBLM_L_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX14" }, "CLBLM_R.CLBLM_IMUX15->CLBLM_M_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX15" }, "CLBLM_R.CLBLM_IMUX16->CLBLM_L_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX16" }, "CLBLM_R.CLBLM_IMUX17->CLBLM_M_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX17" }, "CLBLM_R.CLBLM_IMUX18->CLBLM_M_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX18" }, "CLBLM_R.CLBLM_IMUX19->CLBLM_L_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX19" }, "CLBLM_R.CLBLM_IMUX2->CLBLM_M_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX2" }, "CLBLM_R.CLBLM_IMUX20->CLBLM_L_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX20" }, "CLBLM_R.CLBLM_IMUX21->CLBLM_L_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX21" }, "CLBLM_R.CLBLM_IMUX22->CLBLM_M_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX22" }, "CLBLM_R.CLBLM_IMUX23->CLBLM_L_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX23" }, "CLBLM_R.CLBLM_IMUX24->CLBLM_M_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX24" }, "CLBLM_R.CLBLM_IMUX25->CLBLM_L_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX25" }, "CLBLM_R.CLBLM_IMUX26->CLBLM_L_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX26" }, "CLBLM_R.CLBLM_IMUX27->CLBLM_M_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX27" }, "CLBLM_R.CLBLM_IMUX28->CLBLM_M_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX28" }, "CLBLM_R.CLBLM_IMUX29->CLBLM_M_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX29" }, "CLBLM_R.CLBLM_IMUX3->CLBLM_L_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX3" }, "CLBLM_R.CLBLM_IMUX30->CLBLM_L_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX30" }, "CLBLM_R.CLBLM_IMUX31->CLBLM_M_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX31" }, "CLBLM_R.CLBLM_IMUX32->CLBLM_M_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX32" }, "CLBLM_R.CLBLM_IMUX33->CLBLM_L_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX33" }, "CLBLM_R.CLBLM_IMUX34->CLBLM_L_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX34" }, "CLBLM_R.CLBLM_IMUX35->CLBLM_M_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX35" }, "CLBLM_R.CLBLM_IMUX36->CLBLM_L_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX36" }, "CLBLM_R.CLBLM_IMUX37->CLBLM_L_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX37" }, "CLBLM_R.CLBLM_IMUX38->CLBLM_M_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX38" }, "CLBLM_R.CLBLM_IMUX39->CLBLM_L_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX39" }, "CLBLM_R.CLBLM_IMUX4->CLBLM_M_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX4" }, "CLBLM_R.CLBLM_IMUX40->CLBLM_M_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX40" }, "CLBLM_R.CLBLM_IMUX41->CLBLM_L_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX41" }, "CLBLM_R.CLBLM_IMUX42->CLBLM_L_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX42" }, "CLBLM_R.CLBLM_IMUX43->CLBLM_M_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX43" }, "CLBLM_R.CLBLM_IMUX44->CLBLM_M_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX44" }, "CLBLM_R.CLBLM_IMUX45->CLBLM_M_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX45" }, "CLBLM_R.CLBLM_IMUX46->CLBLM_L_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX46" }, "CLBLM_R.CLBLM_IMUX47->CLBLM_M_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX47" }, "CLBLM_R.CLBLM_IMUX5->CLBLM_L_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX5" }, "CLBLM_R.CLBLM_IMUX6->CLBLM_L_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX6" }, "CLBLM_R.CLBLM_IMUX7->CLBLM_M_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX7" }, "CLBLM_R.CLBLM_IMUX8->CLBLM_M_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX8" }, "CLBLM_R.CLBLM_IMUX9->CLBLM_L_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_IMUX9" }, "CLBLM_R.CLBLM_L_A->>CLBLM_L_AMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.058", + "0.075", + "0.095" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": 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"dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A4" }, "CLBLM_R.CLBLM_L_A5->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A5" }, "CLBLM_R.CLBLM_L_A6->>CLBLM_L_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_A6" }, "CLBLM_R.CLBLM_L_AMUX->CLBLM_LOGIC_OUTS16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_AMUX" }, "CLBLM_R.CLBLM_L_AQ->CLBLM_LOGIC_OUTS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_AQ" }, "CLBLM_R.CLBLM_L_B->>CLBLM_L_BMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_BMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.047", + "0.058", + "0.074", + "0.094" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B" }, "CLBLM_R.CLBLM_L_B->CLBLM_LOGIC_OUTS9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_B" }, "CLBLM_R.CLBLM_L_B1->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B1" }, "CLBLM_R.CLBLM_L_B2->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ 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"src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B4" }, "CLBLM_R.CLBLM_L_B5->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B5" }, "CLBLM_R.CLBLM_L_B6->>CLBLM_L_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_B6" }, "CLBLM_R.CLBLM_L_BMUX->CLBLM_LOGIC_OUTS17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_BMUX" }, "CLBLM_R.CLBLM_L_BQ->CLBLM_LOGIC_OUTS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_BQ" }, "CLBLM_R.CLBLM_L_C->>CLBLM_L_CMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.073", + "0.092" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_CMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.073", + "0.092" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C" }, "CLBLM_R.CLBLM_L_C->CLBLM_LOGIC_OUTS10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_C" }, "CLBLM_R.CLBLM_L_C1->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C1" }, "CLBLM_R.CLBLM_L_C2->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C2" }, "CLBLM_R.CLBLM_L_C3->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_C3" }, "CLBLM_R.CLBLM_L_C4->>CLBLM_L_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_CMUX" }, "CLBLM_R.CLBLM_L_COUT->>CLBLM_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.072", + "0.089", + "0.109", + "0.137" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.072", + "0.089", + "0.109", + "0.137" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_COUT" }, "CLBLM_R.CLBLM_L_COUT->CLBLM_L_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_L_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_COUT" }, "CLBLM_R.CLBLM_L_CQ->CLBLM_LOGIC_OUTS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_CQ" }, "CLBLM_R.CLBLM_L_D->>CLBLM_L_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.056", + "0.073", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.045", + "0.056", + "0.073", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_D" }, "CLBLM_R.CLBLM_L_D->CLBLM_LOGIC_OUTS11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_L_D" }, "CLBLM_R.CLBLM_L_D1->>CLBLM_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_D1" }, "CLBLM_R.CLBLM_L_D2->>CLBLM_L_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_L_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_L_D2" }, "CLBLM_R.CLBLM_L_D3->>CLBLM_L_D": { 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null, + "res": "0.000" + }, "src_wire": "CLBLM_M_A" }, "CLBLM_R.CLBLM_M_A1->>CLBLM_M_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_A1" }, "CLBLM_R.CLBLM_M_A2->>CLBLM_M_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_A2" }, "CLBLM_R.CLBLM_M_A3->>CLBLM_M_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_A3" }, "CLBLM_R.CLBLM_M_A4->>CLBLM_M_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_A4" }, "CLBLM_R.CLBLM_M_A5->>CLBLM_M_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_A5" }, "CLBLM_R.CLBLM_M_A6->>CLBLM_M_A": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_A", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_A6" }, "CLBLM_R.CLBLM_M_AMUX->CLBLM_LOGIC_OUTS20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_AMUX" }, "CLBLM_R.CLBLM_M_AQ->CLBLM_LOGIC_OUTS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" 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"CLBLM_M_B5" }, "CLBLM_R.CLBLM_M_B6->>CLBLM_M_B": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_B", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_B6" }, "CLBLM_R.CLBLM_M_BMUX->CLBLM_LOGIC_OUTS21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_BMUX" }, "CLBLM_R.CLBLM_M_BQ->CLBLM_LOGIC_OUTS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_BQ" }, "CLBLM_R.CLBLM_M_C->>CLBLM_M_CMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.042", + "0.053", + "0.070", + "0.087" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_CMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.042", + "0.053", + "0.070", + "0.087" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C" }, "CLBLM_R.CLBLM_M_C->CLBLM_LOGIC_OUTS14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_C" }, "CLBLM_R.CLBLM_M_C1->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C1" }, "CLBLM_R.CLBLM_M_C2->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C2" }, "CLBLM_R.CLBLM_M_C3->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C3" }, "CLBLM_R.CLBLM_M_C4->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C4" }, "CLBLM_R.CLBLM_M_C5->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C5" }, "CLBLM_R.CLBLM_M_C6->>CLBLM_M_C": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_C", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_C6" }, "CLBLM_R.CLBLM_M_CMUX->CLBLM_LOGIC_OUTS22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_CMUX" }, "CLBLM_R.CLBLM_M_COUT->>CLBLM_M_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.070", + "0.087", + "0.107", + "0.134" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.070", + "0.087", + "0.107", + "0.134" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_COUT" }, "CLBLM_R.CLBLM_M_COUT->CLBLM_M_COUT_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_M_COUT_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_COUT" }, "CLBLM_R.CLBLM_M_CQ->CLBLM_LOGIC_OUTS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_CQ" }, "CLBLM_R.CLBLM_M_D->>CLBLM_M_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.044", + "0.055", + "0.071", + "0.089" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.044", + "0.055", + "0.071", + "0.089" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D" }, "CLBLM_R.CLBLM_M_D->CLBLM_LOGIC_OUTS15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_D" }, "CLBLM_R.CLBLM_M_D1->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D1" }, "CLBLM_R.CLBLM_M_D2->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D2" }, "CLBLM_R.CLBLM_M_D3->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D3" }, "CLBLM_R.CLBLM_M_D4->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D4" }, "CLBLM_R.CLBLM_M_D5->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D5" }, "CLBLM_R.CLBLM_M_D6->>CLBLM_M_D": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLBLM_M_D", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.028", + "0.035", + "0.036", + "0.043" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLBLM_M_D6" }, "CLBLM_R.CLBLM_M_DMUX->CLBLM_LOGIC_OUTS23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_DMUX" }, "CLBLM_R.CLBLM_M_DQ->CLBLM_LOGIC_OUTS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLBLM_LOGIC_OUTS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLBLM_M_DQ" } }, @@ -1063,56 +3304,506 @@ "name": "X0Y0", "prefix": "SLICE", "site_pins": { - "A": "CLBLM_M_A", - "A1": "CLBLM_M_A1", - "A2": "CLBLM_M_A2", - "A3": "CLBLM_M_A3", - "A4": "CLBLM_M_A4", - "A5": "CLBLM_M_A5", - "A6": "CLBLM_M_A6", - "AI": "CLBLM_M_AI", - "AMUX": "CLBLM_M_AMUX", - "AQ": "CLBLM_M_AQ", - "AX": "CLBLM_M_AX", - "B": "CLBLM_M_B", - "B1": "CLBLM_M_B1", - "B2": "CLBLM_M_B2", - "B3": "CLBLM_M_B3", - "B4": "CLBLM_M_B4", - "B5": "CLBLM_M_B5", - "B6": "CLBLM_M_B6", - "BI": "CLBLM_M_BI", - "BMUX": "CLBLM_M_BMUX", - "BQ": "CLBLM_M_BQ", - "BX": "CLBLM_M_BX", - "C": "CLBLM_M_C", - "C1": "CLBLM_M_C1", - "C2": "CLBLM_M_C2", - "C3": "CLBLM_M_C3", - "C4": "CLBLM_M_C4", - "C5": "CLBLM_M_C5", - "C6": "CLBLM_M_C6", - "CE": "CLBLM_M_CE", - "CI": "CLBLM_M_CI", - "CIN": "CLBLM_M_CIN", - "CLK": "CLBLM_M_CLK", - "CMUX": "CLBLM_M_CMUX", - "COUT": "CLBLM_M_COUT", - "CQ": "CLBLM_M_CQ", - "CX": "CLBLM_M_CX", - "D": "CLBLM_M_D", - "D1": "CLBLM_M_D1", - "D2": "CLBLM_M_D2", - "D3": "CLBLM_M_D3", - "D4": "CLBLM_M_D4", - "D5": "CLBLM_M_D5", - "D6": "CLBLM_M_D6", - "DI": "CLBLM_M_DI", - "DMUX": "CLBLM_M_DMUX", - "DQ": "CLBLM_M_DQ", - "DX": "CLBLM_M_DX", - "SR": "CLBLM_M_SR", - "WE": "CLBLM_M_WE" + "A": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "834.5342499999999", + "wire": "CLBLM_M_A" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.143", + "0.178", + "0.226", + "0.268" + ], + "wire": "CLBLM_M_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.136", + "0.170", + "0.216", + "0.256" + ], + "wire": "CLBLM_M_A2" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.088", + "0.109", + "0.150", + "0.178" + ], + "wire": "CLBLM_M_A3" + }, + "A4": { + "cap": "0.000", + "delay": [ + "0.071", + "0.088", + "0.124", + "0.146" + ], + "wire": "CLBLM_M_A4" + }, + "A5": { + "cap": "0.000", + "delay": [ + "0.030", + "0.037", + "0.052", + "0.061" + ], + "wire": "CLBLM_M_A5" + }, + "A6": { + "cap": "0.000", + "delay": [ + "0.005", + "0.006", + "0.007", + "0.009" + ], + "wire": "CLBLM_M_A6" + }, + "AI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_M_AI" + }, + "AMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": 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"CLBLM_L_DQ", - "DX": "CLBLM_L_DX", - "SR": "CLBLM_L_SR" + "A": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "835.1804999999999", + "wire": "CLBLM_L_A" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.133", + "0.165", + "0.217", + "0.257" + ], + "wire": "CLBLM_L_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.130", + "0.162", + "0.212", + "0.250" + ], + "wire": "CLBLM_L_A2" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.078", + "0.097", + "0.138", + "0.163" + ], + "wire": "CLBLM_L_A3" + }, + "A4": { + "cap": "0.000", + "delay": [ + "0.064", + "0.080", + "0.113", + "0.134" + ], + "wire": "CLBLM_L_A4" + }, + "A5": { + "cap": "0.000", + "delay": [ + "0.026", + "0.032", + "0.042", + "0.050" + ], + "wire": "CLBLM_L_A5" + }, + "A6": { + "cap": "0.000", + "delay": [ + "0.002", + "0.002", + "0.002", + "0.003" + ], + "wire": "CLBLM_L_A6" + }, + "AMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "894.144625", + "wire": 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[ + "0.001", + "0.001", + "0.001", + "0.001" + ], + "wire": "CLBLM_L_B6" + }, + "BMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "884.3346875000001", + "wire": "CLBLM_L_BMUX" + }, + "BQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLM_L_BQ" + }, + "BX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_BX" + }, + "C": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "808.31575", + "wire": "CLBLM_L_C" + }, + "C1": { + "cap": "0.000", + "delay": [ + "0.133", + "0.165", + "0.217", + "0.257" + ], + "wire": "CLBLM_L_C1" + }, + "C2": { + "cap": "0.000", + "delay": [ + "0.129", + "0.161", + "0.212", + "0.250" + ], + "wire": "CLBLM_L_C2" + }, + "C3": { + "cap": "0.000", + "delay": [ + "0.080", + "0.100", + "0.142", + "0.168" + ], + "wire": "CLBLM_L_C3" + }, + "C4": { + "cap": "0.000", + "delay": [ + "0.065", + "0.081", + "0.114", + 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}, + "CX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_CX" + }, + "D": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "810.3796249999999", + "wire": "CLBLM_L_D" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.135", + "0.168", + "0.221", + "0.262" + ], + "wire": "CLBLM_L_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.131", + "0.163", + "0.213", + "0.252" + ], + "wire": "CLBLM_L_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.079", + "0.099", + "0.141", + "0.167" + ], + "wire": "CLBLM_L_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.066", + "0.082", + "0.116", + "0.138" + ], + "wire": "CLBLM_L_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.026", + "0.032", + "0.042", + "0.050" + ], + "wire": "CLBLM_L_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.002", + "0.002", + "0.002", + "0.003" + ], + "wire": "CLBLM_L_D6" + }, + "DMUX": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "825.0027499999999", + "wire": "CLBLM_L_DMUX" + }, + "DQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "982.5915", + "wire": "CLBLM_L_DQ" + }, + "DX": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_DX" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLBLM_L_SR" + } }, "type": "SLICEL", "x_coord": 1, @@ -1174,321 +4270,417 @@ } ], "tile_type": "CLBLM_R", - "wires": [ - "CLBLM_BYP0", - "CLBLM_BYP1", - "CLBLM_BYP2", - "CLBLM_BYP3", - "CLBLM_BYP4", - "CLBLM_BYP5", - "CLBLM_BYP6", - "CLBLM_BYP7", - "CLBLM_CLK0", - "CLBLM_CLK1", - "CLBLM_CTRL0", - "CLBLM_CTRL1", - "CLBLM_EE2A0", - "CLBLM_EE2A1", - "CLBLM_EE2A2", - "CLBLM_EE2A3", - "CLBLM_EE2BEG0", - "CLBLM_EE2BEG1", - "CLBLM_EE2BEG2", - "CLBLM_EE2BEG3", - "CLBLM_EE4A0", - "CLBLM_EE4A1", - "CLBLM_EE4A2", - "CLBLM_EE4A3", - "CLBLM_EE4B0", - "CLBLM_EE4B1", - "CLBLM_EE4B2", - "CLBLM_EE4B3", - "CLBLM_EE4BEG0", - "CLBLM_EE4BEG1", - "CLBLM_EE4BEG2", - "CLBLM_EE4BEG3", - "CLBLM_EE4C0", - "CLBLM_EE4C1", - "CLBLM_EE4C2", - "CLBLM_EE4C3", - "CLBLM_EL1BEG0", - "CLBLM_EL1BEG1", - "CLBLM_EL1BEG2", - "CLBLM_EL1BEG3", - "CLBLM_ER1BEG0", - "CLBLM_ER1BEG1", - "CLBLM_ER1BEG2", - "CLBLM_ER1BEG3", - "CLBLM_FAN0", - "CLBLM_FAN1", - "CLBLM_FAN2", - "CLBLM_FAN3", - "CLBLM_FAN4", - "CLBLM_FAN5", - "CLBLM_FAN6", - "CLBLM_FAN7", - "CLBLM_IMUX0", - "CLBLM_IMUX1", - "CLBLM_IMUX10", - "CLBLM_IMUX11", - "CLBLM_IMUX12", - "CLBLM_IMUX13", - "CLBLM_IMUX14", - "CLBLM_IMUX15", - "CLBLM_IMUX16", - "CLBLM_IMUX17", - "CLBLM_IMUX18", - "CLBLM_IMUX19", - "CLBLM_IMUX2", - "CLBLM_IMUX20", - "CLBLM_IMUX21", - "CLBLM_IMUX22", - "CLBLM_IMUX23", - "CLBLM_IMUX24", - "CLBLM_IMUX25", - "CLBLM_IMUX26", - "CLBLM_IMUX27", - "CLBLM_IMUX28", - "CLBLM_IMUX29", - "CLBLM_IMUX3", - "CLBLM_IMUX30", - "CLBLM_IMUX31", - "CLBLM_IMUX32", - "CLBLM_IMUX33", - "CLBLM_IMUX34", - "CLBLM_IMUX35", - "CLBLM_IMUX36", - "CLBLM_IMUX37", - "CLBLM_IMUX38", - "CLBLM_IMUX39", - "CLBLM_IMUX4", - "CLBLM_IMUX40", - "CLBLM_IMUX41", - "CLBLM_IMUX42", - "CLBLM_IMUX43", - "CLBLM_IMUX44", - "CLBLM_IMUX45", - "CLBLM_IMUX46", - "CLBLM_IMUX47", - "CLBLM_IMUX5", - "CLBLM_IMUX6", - "CLBLM_IMUX7", - "CLBLM_IMUX8", - "CLBLM_IMUX9", - "CLBLM_LH1", - "CLBLM_LH10", - "CLBLM_LH11", - "CLBLM_LH12", - "CLBLM_LH2", - "CLBLM_LH3", - "CLBLM_LH4", - "CLBLM_LH5", - "CLBLM_LH6", - "CLBLM_LH7", - "CLBLM_LH8", - "CLBLM_LH9", - "CLBLM_LOGIC_OUTS0", - "CLBLM_LOGIC_OUTS1", - "CLBLM_LOGIC_OUTS10", - "CLBLM_LOGIC_OUTS11", - "CLBLM_LOGIC_OUTS12", - "CLBLM_LOGIC_OUTS13", - "CLBLM_LOGIC_OUTS14", - "CLBLM_LOGIC_OUTS15", - "CLBLM_LOGIC_OUTS16", - "CLBLM_LOGIC_OUTS17", - "CLBLM_LOGIC_OUTS18", - "CLBLM_LOGIC_OUTS19", - "CLBLM_LOGIC_OUTS2", - "CLBLM_LOGIC_OUTS20", - "CLBLM_LOGIC_OUTS21", - "CLBLM_LOGIC_OUTS22", - "CLBLM_LOGIC_OUTS23", - "CLBLM_LOGIC_OUTS3", - "CLBLM_LOGIC_OUTS4", - "CLBLM_LOGIC_OUTS5", - "CLBLM_LOGIC_OUTS6", - "CLBLM_LOGIC_OUTS7", - "CLBLM_LOGIC_OUTS8", - "CLBLM_LOGIC_OUTS9", - "CLBLM_L_A", - "CLBLM_L_A1", - "CLBLM_L_A2", - "CLBLM_L_A3", - "CLBLM_L_A4", - "CLBLM_L_A5", - "CLBLM_L_A6", - "CLBLM_L_AMUX", - "CLBLM_L_AQ", - "CLBLM_L_AX", - "CLBLM_L_B", - "CLBLM_L_B1", - "CLBLM_L_B2", - "CLBLM_L_B3", - "CLBLM_L_B4", - "CLBLM_L_B5", - "CLBLM_L_B6", - "CLBLM_L_BMUX", - "CLBLM_L_BQ", - "CLBLM_L_BX", - "CLBLM_L_C", - "CLBLM_L_C1", - "CLBLM_L_C2", - "CLBLM_L_C3", - "CLBLM_L_C4", - "CLBLM_L_C5", - "CLBLM_L_C6", - "CLBLM_L_CE", - "CLBLM_L_CIN", - "CLBLM_L_CLK", - "CLBLM_L_CMUX", - "CLBLM_L_COUT", - "CLBLM_L_COUT_N", - "CLBLM_L_CQ", - "CLBLM_L_CX", - "CLBLM_L_D", - "CLBLM_L_D1", - "CLBLM_L_D2", - "CLBLM_L_D3", - "CLBLM_L_D4", - "CLBLM_L_D5", - "CLBLM_L_D6", - "CLBLM_L_DMUX", - "CLBLM_L_DQ", - "CLBLM_L_DX", - "CLBLM_L_SR", - "CLBLM_MONITOR_N", - "CLBLM_MONITOR_P", - "CLBLM_M_A", - "CLBLM_M_A1", - "CLBLM_M_A2", - "CLBLM_M_A3", - "CLBLM_M_A4", - "CLBLM_M_A5", - "CLBLM_M_A6", - "CLBLM_M_AI", - "CLBLM_M_AMUX", - "CLBLM_M_AQ", - "CLBLM_M_AX", - "CLBLM_M_B", - "CLBLM_M_B1", - "CLBLM_M_B2", - "CLBLM_M_B3", - "CLBLM_M_B4", - "CLBLM_M_B5", - "CLBLM_M_B6", - "CLBLM_M_BI", - "CLBLM_M_BMUX", - "CLBLM_M_BQ", - "CLBLM_M_BX", - "CLBLM_M_C", - "CLBLM_M_C1", - "CLBLM_M_C2", - "CLBLM_M_C3", - "CLBLM_M_C4", - "CLBLM_M_C5", - "CLBLM_M_C6", - "CLBLM_M_CE", - "CLBLM_M_CI", - "CLBLM_M_CIN", - "CLBLM_M_CLK", - "CLBLM_M_CMUX", - "CLBLM_M_COUT", - "CLBLM_M_COUT_N", - "CLBLM_M_CQ", - "CLBLM_M_CX", - "CLBLM_M_D", - "CLBLM_M_D1", - "CLBLM_M_D2", - "CLBLM_M_D3", - "CLBLM_M_D4", - "CLBLM_M_D5", - "CLBLM_M_D6", - "CLBLM_M_DI", - "CLBLM_M_DMUX", - "CLBLM_M_DQ", - "CLBLM_M_DX", - "CLBLM_M_SR", - "CLBLM_M_WE", - "CLBLM_NE2A0", - "CLBLM_NE2A1", - "CLBLM_NE2A2", - "CLBLM_NE2A3", - "CLBLM_NE4BEG0", - "CLBLM_NE4BEG1", - "CLBLM_NE4BEG2", - "CLBLM_NE4BEG3", - "CLBLM_NE4C0", - "CLBLM_NE4C1", - "CLBLM_NE4C2", - "CLBLM_NE4C3", - "CLBLM_NW2A0", - "CLBLM_NW2A1", - "CLBLM_NW2A2", - "CLBLM_NW2A3", - "CLBLM_NW4A0", - "CLBLM_NW4A1", - "CLBLM_NW4A2", - "CLBLM_NW4A3", - "CLBLM_NW4END0", - "CLBLM_NW4END1", - "CLBLM_NW4END2", - "CLBLM_NW4END3", - "CLBLM_SE2A0", - "CLBLM_SE2A1", - "CLBLM_SE2A2", - "CLBLM_SE2A3", - "CLBLM_SE4BEG0", - "CLBLM_SE4BEG1", - "CLBLM_SE4BEG2", - "CLBLM_SE4BEG3", - "CLBLM_SE4C0", - "CLBLM_SE4C1", - "CLBLM_SE4C2", - "CLBLM_SE4C3", - "CLBLM_SW2A0", - "CLBLM_SW2A1", - "CLBLM_SW2A2", - "CLBLM_SW2A3", - "CLBLM_SW4A0", - "CLBLM_SW4A1", - "CLBLM_SW4A2", - "CLBLM_SW4A3", - "CLBLM_SW4END0", - "CLBLM_SW4END1", - "CLBLM_SW4END2", - "CLBLM_SW4END3", - "CLBLM_WL1END0", - "CLBLM_WL1END1", - "CLBLM_WL1END2", - "CLBLM_WL1END3", - "CLBLM_WR1END0", - "CLBLM_WR1END1", - "CLBLM_WR1END2", - "CLBLM_WR1END3", - "CLBLM_WW2A0", - "CLBLM_WW2A1", - "CLBLM_WW2A2", - "CLBLM_WW2A3", - "CLBLM_WW2END0", - "CLBLM_WW2END1", - "CLBLM_WW2END2", - "CLBLM_WW2END3", - "CLBLM_WW4A0", - "CLBLM_WW4A1", - "CLBLM_WW4A2", - "CLBLM_WW4A3", - "CLBLM_WW4B0", - "CLBLM_WW4B1", - "CLBLM_WW4B2", - "CLBLM_WW4B3", - "CLBLM_WW4C0", - "CLBLM_WW4C1", - "CLBLM_WW4C2", - "CLBLM_WW4C3", - "CLBLM_WW4END0", - "CLBLM_WW4END1", - "CLBLM_WW4END2", - "CLBLM_WW4END3" - ] + "wires": { + "CLBLM_BYP0": null, + "CLBLM_BYP1": null, + "CLBLM_BYP2": null, + "CLBLM_BYP3": null, + "CLBLM_BYP4": null, + "CLBLM_BYP5": null, + "CLBLM_BYP6": null, + "CLBLM_BYP7": null, + "CLBLM_CLK0": null, + "CLBLM_CLK1": null, + "CLBLM_CTRL0": null, + "CLBLM_CTRL1": null, + "CLBLM_EE2A0": null, + "CLBLM_EE2A1": null, + "CLBLM_EE2A2": null, + "CLBLM_EE2A3": null, + "CLBLM_EE2BEG0": null, + "CLBLM_EE2BEG1": null, + "CLBLM_EE2BEG2": null, + "CLBLM_EE2BEG3": null, + "CLBLM_EE4A0": null, + "CLBLM_EE4A1": null, + "CLBLM_EE4A2": null, + "CLBLM_EE4A3": null, + "CLBLM_EE4B0": null, + "CLBLM_EE4B1": null, + "CLBLM_EE4B2": null, + "CLBLM_EE4B3": null, + "CLBLM_EE4BEG0": null, + "CLBLM_EE4BEG1": null, + "CLBLM_EE4BEG2": null, + "CLBLM_EE4BEG3": null, + "CLBLM_EE4C0": null, + "CLBLM_EE4C1": null, + "CLBLM_EE4C2": null, + "CLBLM_EE4C3": null, + "CLBLM_EL1BEG0": { + "cap": "5.223", + "res": "52.531" + }, + "CLBLM_EL1BEG1": { + "cap": "5.223", + "res": "52.531" + }, + "CLBLM_EL1BEG2": { + "cap": "5.223", + "res": "52.531" + }, + "CLBLM_EL1BEG3": { + "cap": "5.223", + "res": "52.531" + }, + "CLBLM_ER1BEG0": { + "cap": "6.083", + "res": "90.578" + }, + "CLBLM_ER1BEG1": { + "cap": "6.083", + "res": "90.578" + }, + "CLBLM_ER1BEG2": { + "cap": "6.083", + "res": "90.578" + }, + "CLBLM_ER1BEG3": { + "cap": "6.083", + "res": "90.578" + }, + "CLBLM_FAN0": null, + "CLBLM_FAN1": null, + "CLBLM_FAN2": null, + "CLBLM_FAN3": null, + "CLBLM_FAN4": null, + "CLBLM_FAN5": null, + "CLBLM_FAN6": null, + "CLBLM_FAN7": null, + "CLBLM_IMUX0": null, + "CLBLM_IMUX1": null, + "CLBLM_IMUX10": null, + "CLBLM_IMUX11": null, + "CLBLM_IMUX12": null, + "CLBLM_IMUX13": null, + "CLBLM_IMUX14": null, + "CLBLM_IMUX15": null, + "CLBLM_IMUX16": null, + "CLBLM_IMUX17": null, + "CLBLM_IMUX18": null, + "CLBLM_IMUX19": null, + "CLBLM_IMUX2": null, + "CLBLM_IMUX20": null, + "CLBLM_IMUX21": null, + "CLBLM_IMUX22": null, + "CLBLM_IMUX23": null, + "CLBLM_IMUX24": null, + "CLBLM_IMUX25": null, + "CLBLM_IMUX26": null, + "CLBLM_IMUX27": null, + "CLBLM_IMUX28": null, + "CLBLM_IMUX29": null, + "CLBLM_IMUX3": null, + "CLBLM_IMUX30": null, + "CLBLM_IMUX31": null, + "CLBLM_IMUX32": null, + "CLBLM_IMUX33": null, + "CLBLM_IMUX34": null, + "CLBLM_IMUX35": null, + "CLBLM_IMUX36": null, + "CLBLM_IMUX37": null, + "CLBLM_IMUX38": null, + "CLBLM_IMUX39": null, + "CLBLM_IMUX4": null, + "CLBLM_IMUX40": null, + "CLBLM_IMUX41": null, + "CLBLM_IMUX42": null, + "CLBLM_IMUX43": null, + "CLBLM_IMUX44": null, + "CLBLM_IMUX45": null, + "CLBLM_IMUX46": null, + "CLBLM_IMUX47": null, + "CLBLM_IMUX5": null, + "CLBLM_IMUX6": null, + "CLBLM_IMUX7": null, + "CLBLM_IMUX8": null, + "CLBLM_IMUX9": null, + "CLBLM_LH1": null, + "CLBLM_LH10": null, + "CLBLM_LH11": null, + "CLBLM_LH12": null, + "CLBLM_LH2": null, + "CLBLM_LH3": null, + "CLBLM_LH4": null, + "CLBLM_LH5": null, + "CLBLM_LH6": null, + "CLBLM_LH7": null, + "CLBLM_LH8": null, + "CLBLM_LH9": null, + "CLBLM_LOGIC_OUTS0": null, + "CLBLM_LOGIC_OUTS1": null, + "CLBLM_LOGIC_OUTS10": null, + "CLBLM_LOGIC_OUTS11": null, + "CLBLM_LOGIC_OUTS12": null, + "CLBLM_LOGIC_OUTS13": null, + "CLBLM_LOGIC_OUTS14": null, + "CLBLM_LOGIC_OUTS15": null, + "CLBLM_LOGIC_OUTS16": null, + "CLBLM_LOGIC_OUTS17": null, + "CLBLM_LOGIC_OUTS18": null, + "CLBLM_LOGIC_OUTS19": null, + "CLBLM_LOGIC_OUTS2": null, + "CLBLM_LOGIC_OUTS20": null, + "CLBLM_LOGIC_OUTS21": null, + "CLBLM_LOGIC_OUTS22": null, + "CLBLM_LOGIC_OUTS23": null, + "CLBLM_LOGIC_OUTS3": null, + "CLBLM_LOGIC_OUTS4": null, + "CLBLM_LOGIC_OUTS5": null, + "CLBLM_LOGIC_OUTS6": null, + "CLBLM_LOGIC_OUTS7": null, + "CLBLM_LOGIC_OUTS8": null, + "CLBLM_LOGIC_OUTS9": null, + "CLBLM_L_A": null, + "CLBLM_L_A1": null, + "CLBLM_L_A2": null, + "CLBLM_L_A3": null, + "CLBLM_L_A4": null, + "CLBLM_L_A5": null, + "CLBLM_L_A6": null, + "CLBLM_L_AMUX": null, + "CLBLM_L_AQ": null, + "CLBLM_L_AX": null, + "CLBLM_L_B": null, + "CLBLM_L_B1": null, + "CLBLM_L_B2": null, + "CLBLM_L_B3": null, + "CLBLM_L_B4": null, + "CLBLM_L_B5": null, + "CLBLM_L_B6": null, + "CLBLM_L_BMUX": null, + "CLBLM_L_BQ": null, + "CLBLM_L_BX": null, + "CLBLM_L_C": null, + "CLBLM_L_C1": null, + "CLBLM_L_C2": null, + "CLBLM_L_C3": null, + "CLBLM_L_C4": null, + "CLBLM_L_C5": null, + "CLBLM_L_C6": null, + "CLBLM_L_CE": null, + "CLBLM_L_CIN": null, + "CLBLM_L_CLK": null, + "CLBLM_L_CMUX": null, + "CLBLM_L_COUT": null, + "CLBLM_L_COUT_N": null, + "CLBLM_L_CQ": null, + "CLBLM_L_CX": null, + "CLBLM_L_D": null, + "CLBLM_L_D1": null, + "CLBLM_L_D2": null, + "CLBLM_L_D3": null, + "CLBLM_L_D4": null, + "CLBLM_L_D5": null, + "CLBLM_L_D6": null, + "CLBLM_L_DMUX": null, + "CLBLM_L_DQ": null, + "CLBLM_L_DX": null, + "CLBLM_L_SR": null, + "CLBLM_MONITOR_N": null, + "CLBLM_MONITOR_P": null, + "CLBLM_M_A": null, + "CLBLM_M_A1": null, + "CLBLM_M_A2": null, + "CLBLM_M_A3": null, + "CLBLM_M_A4": null, + "CLBLM_M_A5": null, + "CLBLM_M_A6": null, + "CLBLM_M_AI": null, + "CLBLM_M_AMUX": null, + "CLBLM_M_AQ": null, + "CLBLM_M_AX": null, + "CLBLM_M_B": null, + "CLBLM_M_B1": null, + "CLBLM_M_B2": null, + "CLBLM_M_B3": null, + "CLBLM_M_B4": null, + "CLBLM_M_B5": null, + "CLBLM_M_B6": null, + "CLBLM_M_BI": null, + "CLBLM_M_BMUX": null, + "CLBLM_M_BQ": null, + "CLBLM_M_BX": null, + "CLBLM_M_C": null, + "CLBLM_M_C1": null, + "CLBLM_M_C2": null, + "CLBLM_M_C3": null, + "CLBLM_M_C4": null, + "CLBLM_M_C5": null, + "CLBLM_M_C6": null, + "CLBLM_M_CE": null, + "CLBLM_M_CI": null, + "CLBLM_M_CIN": null, + "CLBLM_M_CLK": null, + "CLBLM_M_CMUX": null, + "CLBLM_M_COUT": null, + "CLBLM_M_COUT_N": null, + "CLBLM_M_CQ": null, + "CLBLM_M_CX": null, + "CLBLM_M_D": null, + "CLBLM_M_D1": null, + "CLBLM_M_D2": null, + "CLBLM_M_D3": null, + "CLBLM_M_D4": null, + "CLBLM_M_D5": null, + "CLBLM_M_D6": null, + "CLBLM_M_DI": null, + "CLBLM_M_DMUX": null, + "CLBLM_M_DQ": null, + "CLBLM_M_DX": null, + "CLBLM_M_SR": null, + "CLBLM_M_WE": null, + "CLBLM_NE2A0": { + "cap": "6.623", + "res": "102.520" + }, + "CLBLM_NE2A1": { + "cap": "6.623", + "res": "102.520" + }, + "CLBLM_NE2A2": { + "cap": "6.623", + "res": "102.520" + }, + "CLBLM_NE2A3": { + "cap": "6.623", + "res": "102.520" + }, + "CLBLM_NE4BEG0": null, + "CLBLM_NE4BEG1": null, + "CLBLM_NE4BEG2": null, + "CLBLM_NE4BEG3": null, + "CLBLM_NE4C0": null, + "CLBLM_NE4C1": null, + "CLBLM_NE4C2": null, + "CLBLM_NE4C3": null, + "CLBLM_NW2A0": { + "cap": "6.905", + "res": "93.135" + }, + "CLBLM_NW2A1": { + "cap": "6.905", + "res": "93.135" + }, + "CLBLM_NW2A2": { + "cap": "6.905", + "res": "93.135" + }, + "CLBLM_NW2A3": { + "cap": "6.905", + "res": "93.135" + }, + "CLBLM_NW4A0": null, + "CLBLM_NW4A1": null, + "CLBLM_NW4A2": null, + "CLBLM_NW4A3": null, + "CLBLM_NW4END0": null, + "CLBLM_NW4END1": null, + "CLBLM_NW4END2": null, + "CLBLM_NW4END3": null, + "CLBLM_SE2A0": { + "cap": "6.347", + "res": "91.805" + }, + "CLBLM_SE2A1": { + "cap": "6.347", + "res": "91.805" + }, + "CLBLM_SE2A2": { + "cap": "6.347", + "res": "91.805" + }, + "CLBLM_SE2A3": { + "cap": "6.347", + "res": "91.805" + }, + "CLBLM_SE4BEG0": null, + "CLBLM_SE4BEG1": null, + "CLBLM_SE4BEG2": null, + "CLBLM_SE4BEG3": null, + "CLBLM_SE4C0": null, + "CLBLM_SE4C1": null, + "CLBLM_SE4C2": null, + "CLBLM_SE4C3": null, + "CLBLM_SW2A0": { + "cap": "6.966", + "res": "91.419" + }, + "CLBLM_SW2A1": { + "cap": "6.966", + "res": "91.419" + }, + "CLBLM_SW2A2": { + "cap": "6.966", + "res": "91.419" + }, + "CLBLM_SW2A3": { + "cap": "6.966", + "res": "91.419" + }, + "CLBLM_SW4A0": null, + "CLBLM_SW4A1": null, + "CLBLM_SW4A2": null, + "CLBLM_SW4A3": null, + "CLBLM_SW4END0": null, + "CLBLM_SW4END1": null, + "CLBLM_SW4END2": null, + "CLBLM_SW4END3": null, + "CLBLM_WL1END0": { + "cap": "6.547", + "res": "59.551" + }, + "CLBLM_WL1END1": { + "cap": "6.547", + "res": "59.551" + }, + "CLBLM_WL1END2": { + "cap": "6.547", + "res": "59.551" + }, + "CLBLM_WL1END3": { + "cap": "6.547", + "res": "59.551" + }, + "CLBLM_WR1END0": { + "cap": "6.641", + "res": "93.569" + }, + "CLBLM_WR1END1": { + "cap": "6.641", + "res": "93.569" + }, + "CLBLM_WR1END2": { + "cap": "6.641", + "res": "93.569" + }, + "CLBLM_WR1END3": { + "cap": "6.641", + "res": "93.569" + }, + "CLBLM_WW2A0": null, + "CLBLM_WW2A1": null, + "CLBLM_WW2A2": null, + "CLBLM_WW2A3": null, + "CLBLM_WW2END0": null, + "CLBLM_WW2END1": null, + "CLBLM_WW2END2": null, + "CLBLM_WW2END3": null, + "CLBLM_WW4A0": null, + "CLBLM_WW4A1": null, + "CLBLM_WW4A2": null, + "CLBLM_WW4A3": null, + "CLBLM_WW4B0": null, + "CLBLM_WW4B1": null, + "CLBLM_WW4B2": null, + "CLBLM_WW4B3": null, + "CLBLM_WW4C0": null, + "CLBLM_WW4C1": null, + "CLBLM_WW4C2": null, + "CLBLM_WW4C3": null, + "CLBLM_WW4END0": null, + "CLBLM_WW4END1": null, + "CLBLM_WW4END2": null, + "CLBLM_WW4END3": null + } } diff --git a/kintex7/tile_type_CLK_BUFG_BOT_R.json b/kintex7/tile_type_CLK_BUFG_BOT_R.json index 164a90a..bda36d0 100644 --- a/kintex7/tile_type_CLK_BUFG_BOT_R.json +++ b/kintex7/tile_type_CLK_BUFG_BOT_R.json @@ -2,2130 +2,8514 @@ "pips": { "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED1" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED10" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED11" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED12" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED13" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED14" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED15" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED16" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED17" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED18" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED19" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED2" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED20" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED21" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED22" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED23" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED24" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED25" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED26" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED27" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED28" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED29" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED3" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED30" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED31" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED4" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED5" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED6" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED7" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED8" }, "CLK_BUFG_BOT_R.CLK_BUFG_BOT_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BOT_R_CK_MUXED9" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL0_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL10_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL11_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL12_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL13_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL14_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL15_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL1_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL2_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL3_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL4_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL5_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL6_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL7_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL8_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL9_I0" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, 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"0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { 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"0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_0->>CLK_BUFG_R_BUFGCTRL3_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_0" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_1" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_2" }, "CLK_BUFG_BOT_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_BOT_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" } }, @@ -2134,15 +8518,96 @@ "name": "X0Y0", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", - "I0": "CLK_BUFG_BUFGCTRL0_I0", - "I1": "CLK_BUFG_BUFGCTRL0_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL0_O", - "S0": "CLK_BUFG_R_BUFGCTRL0_S0", - "S1": "CLK_BUFG_R_BUFGCTRL0_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL0_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2152,15 +8617,96 @@ "name": "X0Y1", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", - "I0": "CLK_BUFG_BUFGCTRL1_I0", - "I1": "CLK_BUFG_BUFGCTRL1_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL1_O", - "S0": "CLK_BUFG_R_BUFGCTRL1_S0", - "S1": "CLK_BUFG_R_BUFGCTRL1_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL1_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2170,15 +8716,96 @@ "name": "X0Y2", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", - "I0": "CLK_BUFG_BUFGCTRL2_I0", - "I1": "CLK_BUFG_BUFGCTRL2_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL2_O", - "S0": "CLK_BUFG_R_BUFGCTRL2_S0", - "S1": "CLK_BUFG_R_BUFGCTRL2_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL2_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2188,15 +8815,96 @@ "name": "X0Y3", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", - "I0": "CLK_BUFG_BUFGCTRL3_I0", - "I1": "CLK_BUFG_BUFGCTRL3_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL3_O", - "S0": "CLK_BUFG_R_BUFGCTRL3_S0", - "S1": "CLK_BUFG_R_BUFGCTRL3_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL3_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2206,15 +8914,96 @@ "name": "X0Y4", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", - "I0": "CLK_BUFG_BUFGCTRL4_I0", - "I1": "CLK_BUFG_BUFGCTRL4_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL4_O", - "S0": "CLK_BUFG_R_BUFGCTRL4_S0", - "S1": "CLK_BUFG_R_BUFGCTRL4_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL4_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2224,15 +9013,96 @@ "name": "X0Y5", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", - "I0": "CLK_BUFG_BUFGCTRL5_I0", - "I1": "CLK_BUFG_BUFGCTRL5_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL5_O", - "S0": "CLK_BUFG_R_BUFGCTRL5_S0", - "S1": "CLK_BUFG_R_BUFGCTRL5_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL5_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2242,15 +9112,96 @@ "name": "X0Y6", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", - "I0": "CLK_BUFG_BUFGCTRL6_I0", - "I1": "CLK_BUFG_BUFGCTRL6_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL6_O", - "S0": "CLK_BUFG_R_BUFGCTRL6_S0", - "S1": "CLK_BUFG_R_BUFGCTRL6_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL6_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2260,15 +9211,96 @@ "name": "X0Y7", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", - "I0": "CLK_BUFG_BUFGCTRL7_I0", - "I1": "CLK_BUFG_BUFGCTRL7_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL7_O", - "S0": "CLK_BUFG_R_BUFGCTRL7_S0", - "S1": "CLK_BUFG_R_BUFGCTRL7_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL7_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2278,15 +9310,96 @@ "name": "X0Y8", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", - "I0": "CLK_BUFG_BUFGCTRL8_I0", - "I1": "CLK_BUFG_BUFGCTRL8_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL8_O", - "S0": "CLK_BUFG_R_BUFGCTRL8_S0", - "S1": "CLK_BUFG_R_BUFGCTRL8_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL8_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2296,15 +9409,96 @@ "name": "X0Y9", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", - "I0": "CLK_BUFG_BUFGCTRL9_I0", - "I1": "CLK_BUFG_BUFGCTRL9_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL9_O", - "S0": "CLK_BUFG_R_BUFGCTRL9_S0", - "S1": "CLK_BUFG_R_BUFGCTRL9_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL9_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2314,15 +9508,96 @@ "name": "X0Y10", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", - "I0": "CLK_BUFG_BUFGCTRL10_I0", - "I1": "CLK_BUFG_BUFGCTRL10_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL10_O", - "S0": "CLK_BUFG_R_BUFGCTRL10_S0", - "S1": "CLK_BUFG_R_BUFGCTRL10_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL10_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2332,15 +9607,96 @@ "name": "X0Y11", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", - "I0": "CLK_BUFG_BUFGCTRL11_I0", - "I1": "CLK_BUFG_BUFGCTRL11_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL11_O", - "S0": "CLK_BUFG_R_BUFGCTRL11_S0", - "S1": "CLK_BUFG_R_BUFGCTRL11_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL11_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2350,15 +9706,96 @@ "name": "X0Y12", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", - "I0": "CLK_BUFG_BUFGCTRL12_I0", - "I1": "CLK_BUFG_BUFGCTRL12_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL12_O", - "S0": "CLK_BUFG_R_BUFGCTRL12_S0", - "S1": "CLK_BUFG_R_BUFGCTRL12_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL12_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2368,15 +9805,96 @@ "name": "X0Y13", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", - "I0": "CLK_BUFG_BUFGCTRL13_I0", - "I1": "CLK_BUFG_BUFGCTRL13_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL13_O", - "S0": "CLK_BUFG_R_BUFGCTRL13_S0", - "S1": "CLK_BUFG_R_BUFGCTRL13_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL13_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2386,15 +9904,96 @@ "name": "X0Y14", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", - "I0": "CLK_BUFG_BUFGCTRL14_I0", - "I1": "CLK_BUFG_BUFGCTRL14_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL14_O", - "S0": "CLK_BUFG_R_BUFGCTRL14_S0", - "S1": "CLK_BUFG_R_BUFGCTRL14_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL14_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2404,15 +10003,96 @@ "name": "X0Y15", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", - "I0": "CLK_BUFG_BUFGCTRL15_I0", - "I1": "CLK_BUFG_BUFGCTRL15_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL15_O", - "S0": "CLK_BUFG_R_BUFGCTRL15_S0", - "S1": "CLK_BUFG_R_BUFGCTRL15_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL15_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2420,1150 +10100,1750 @@ } ], "tile_type": "CLK_BUFG_BOT_R", - "wires": [ - "CLK_BUFG_BOT_R_CK_MUXED0", - "CLK_BUFG_BOT_R_CK_MUXED1", - "CLK_BUFG_BOT_R_CK_MUXED10", - "CLK_BUFG_BOT_R_CK_MUXED11", - "CLK_BUFG_BOT_R_CK_MUXED12", - "CLK_BUFG_BOT_R_CK_MUXED13", - "CLK_BUFG_BOT_R_CK_MUXED14", - "CLK_BUFG_BOT_R_CK_MUXED15", - "CLK_BUFG_BOT_R_CK_MUXED16", - "CLK_BUFG_BOT_R_CK_MUXED17", - "CLK_BUFG_BOT_R_CK_MUXED18", - "CLK_BUFG_BOT_R_CK_MUXED19", - "CLK_BUFG_BOT_R_CK_MUXED2", - "CLK_BUFG_BOT_R_CK_MUXED20", - "CLK_BUFG_BOT_R_CK_MUXED21", - "CLK_BUFG_BOT_R_CK_MUXED22", - "CLK_BUFG_BOT_R_CK_MUXED23", - "CLK_BUFG_BOT_R_CK_MUXED24", - "CLK_BUFG_BOT_R_CK_MUXED25", - "CLK_BUFG_BOT_R_CK_MUXED26", - "CLK_BUFG_BOT_R_CK_MUXED27", - "CLK_BUFG_BOT_R_CK_MUXED28", - "CLK_BUFG_BOT_R_CK_MUXED29", - "CLK_BUFG_BOT_R_CK_MUXED3", - "CLK_BUFG_BOT_R_CK_MUXED30", - "CLK_BUFG_BOT_R_CK_MUXED31", - "CLK_BUFG_BOT_R_CK_MUXED4", - "CLK_BUFG_BOT_R_CK_MUXED5", - "CLK_BUFG_BOT_R_CK_MUXED6", - "CLK_BUFG_BOT_R_CK_MUXED7", - "CLK_BUFG_BOT_R_CK_MUXED8", - "CLK_BUFG_BOT_R_CK_MUXED9", - "CLK_BUFG_BUFGCTRL0_I0", - "CLK_BUFG_BUFGCTRL0_I1", - "CLK_BUFG_BUFGCTRL0_O", - "CLK_BUFG_BUFGCTRL10_I0", - "CLK_BUFG_BUFGCTRL10_I1", - "CLK_BUFG_BUFGCTRL10_O", - "CLK_BUFG_BUFGCTRL11_I0", - "CLK_BUFG_BUFGCTRL11_I1", - "CLK_BUFG_BUFGCTRL11_O", - "CLK_BUFG_BUFGCTRL12_I0", - "CLK_BUFG_BUFGCTRL12_I1", - "CLK_BUFG_BUFGCTRL12_O", - "CLK_BUFG_BUFGCTRL13_I0", - "CLK_BUFG_BUFGCTRL13_I1", - "CLK_BUFG_BUFGCTRL13_O", - "CLK_BUFG_BUFGCTRL14_I0", - "CLK_BUFG_BUFGCTRL14_I1", - "CLK_BUFG_BUFGCTRL14_O", - "CLK_BUFG_BUFGCTRL15_I0", - "CLK_BUFG_BUFGCTRL15_I1", - "CLK_BUFG_BUFGCTRL15_O", - "CLK_BUFG_BUFGCTRL1_I0", - "CLK_BUFG_BUFGCTRL1_I1", - "CLK_BUFG_BUFGCTRL1_O", - "CLK_BUFG_BUFGCTRL2_I0", - "CLK_BUFG_BUFGCTRL2_I1", - "CLK_BUFG_BUFGCTRL2_O", - "CLK_BUFG_BUFGCTRL3_I0", - "CLK_BUFG_BUFGCTRL3_I1", - "CLK_BUFG_BUFGCTRL3_O", - "CLK_BUFG_BUFGCTRL4_I0", - "CLK_BUFG_BUFGCTRL4_I1", - "CLK_BUFG_BUFGCTRL4_O", - "CLK_BUFG_BUFGCTRL5_I0", - "CLK_BUFG_BUFGCTRL5_I1", - "CLK_BUFG_BUFGCTRL5_O", - "CLK_BUFG_BUFGCTRL6_I0", - "CLK_BUFG_BUFGCTRL6_I1", - "CLK_BUFG_BUFGCTRL6_O", - "CLK_BUFG_BUFGCTRL7_I0", - "CLK_BUFG_BUFGCTRL7_I1", - "CLK_BUFG_BUFGCTRL7_O", - "CLK_BUFG_BUFGCTRL8_I0", - "CLK_BUFG_BUFGCTRL8_I1", - "CLK_BUFG_BUFGCTRL8_O", - "CLK_BUFG_BUFGCTRL9_I0", - "CLK_BUFG_BUFGCTRL9_I1", - "CLK_BUFG_BUFGCTRL9_O", - "CLK_BUFG_CK_GCLK0", - "CLK_BUFG_CK_GCLK1", - "CLK_BUFG_CK_GCLK10", - "CLK_BUFG_CK_GCLK11", - "CLK_BUFG_CK_GCLK12", - "CLK_BUFG_CK_GCLK13", - "CLK_BUFG_CK_GCLK14", - "CLK_BUFG_CK_GCLK15", - "CLK_BUFG_CK_GCLK16", - "CLK_BUFG_CK_GCLK17", - "CLK_BUFG_CK_GCLK18", - "CLK_BUFG_CK_GCLK19", - "CLK_BUFG_CK_GCLK2", - "CLK_BUFG_CK_GCLK20", - "CLK_BUFG_CK_GCLK21", - "CLK_BUFG_CK_GCLK22", - "CLK_BUFG_CK_GCLK23", - "CLK_BUFG_CK_GCLK24", - "CLK_BUFG_CK_GCLK25", - "CLK_BUFG_CK_GCLK26", - "CLK_BUFG_CK_GCLK27", - "CLK_BUFG_CK_GCLK28", - "CLK_BUFG_CK_GCLK29", - "CLK_BUFG_CK_GCLK3", - "CLK_BUFG_CK_GCLK30", - "CLK_BUFG_CK_GCLK31", - "CLK_BUFG_CK_GCLK4", - "CLK_BUFG_CK_GCLK5", - "CLK_BUFG_CK_GCLK6", - "CLK_BUFG_CK_GCLK7", - "CLK_BUFG_CK_GCLK8", - "CLK_BUFG_CK_GCLK9", - "CLK_BUFG_IMUX0_0", - "CLK_BUFG_IMUX0_1", - "CLK_BUFG_IMUX0_2", - "CLK_BUFG_IMUX0_3", - "CLK_BUFG_IMUX10_0", - "CLK_BUFG_IMUX10_1", - "CLK_BUFG_IMUX10_2", - "CLK_BUFG_IMUX10_3", - "CLK_BUFG_IMUX11_0", - "CLK_BUFG_IMUX11_1", - "CLK_BUFG_IMUX11_2", - "CLK_BUFG_IMUX11_3", - "CLK_BUFG_IMUX12_0", - "CLK_BUFG_IMUX12_1", - "CLK_BUFG_IMUX12_2", - "CLK_BUFG_IMUX12_3", - "CLK_BUFG_IMUX13_0", - "CLK_BUFG_IMUX13_1", - "CLK_BUFG_IMUX13_2", - "CLK_BUFG_IMUX13_3", - "CLK_BUFG_IMUX14_0", - "CLK_BUFG_IMUX14_1", - "CLK_BUFG_IMUX14_2", - "CLK_BUFG_IMUX14_3", - "CLK_BUFG_IMUX15_0", - "CLK_BUFG_IMUX15_1", - "CLK_BUFG_IMUX15_2", - "CLK_BUFG_IMUX15_3", - "CLK_BUFG_IMUX16_0", - "CLK_BUFG_IMUX16_1", - "CLK_BUFG_IMUX16_2", - "CLK_BUFG_IMUX16_3", - "CLK_BUFG_IMUX17_0", - "CLK_BUFG_IMUX17_1", - "CLK_BUFG_IMUX17_2", - "CLK_BUFG_IMUX17_3", - "CLK_BUFG_IMUX18_0", - "CLK_BUFG_IMUX18_1", - "CLK_BUFG_IMUX18_2", - "CLK_BUFG_IMUX18_3", - "CLK_BUFG_IMUX19_0", - "CLK_BUFG_IMUX19_1", - "CLK_BUFG_IMUX19_2", - "CLK_BUFG_IMUX19_3", - "CLK_BUFG_IMUX1_0", - "CLK_BUFG_IMUX1_1", - "CLK_BUFG_IMUX1_2", - "CLK_BUFG_IMUX1_3", - "CLK_BUFG_IMUX20_0", - "CLK_BUFG_IMUX20_1", - "CLK_BUFG_IMUX20_2", - "CLK_BUFG_IMUX20_3", - "CLK_BUFG_IMUX21_0", - "CLK_BUFG_IMUX21_1", - "CLK_BUFG_IMUX21_2", - "CLK_BUFG_IMUX21_3", - "CLK_BUFG_IMUX22_0", - "CLK_BUFG_IMUX22_1", - "CLK_BUFG_IMUX22_2", - "CLK_BUFG_IMUX22_3", - "CLK_BUFG_IMUX23_0", - "CLK_BUFG_IMUX23_1", - "CLK_BUFG_IMUX23_2", - "CLK_BUFG_IMUX23_3", - "CLK_BUFG_IMUX24_0", - "CLK_BUFG_IMUX24_1", - "CLK_BUFG_IMUX24_2", - "CLK_BUFG_IMUX24_3", - "CLK_BUFG_IMUX25_0", - "CLK_BUFG_IMUX25_1", - "CLK_BUFG_IMUX25_2", - "CLK_BUFG_IMUX25_3", - "CLK_BUFG_IMUX26_0", - "CLK_BUFG_IMUX26_1", - "CLK_BUFG_IMUX26_2", - "CLK_BUFG_IMUX26_3", - "CLK_BUFG_IMUX27_0", - "CLK_BUFG_IMUX27_1", - "CLK_BUFG_IMUX27_2", - "CLK_BUFG_IMUX27_3", - "CLK_BUFG_IMUX28_0", - "CLK_BUFG_IMUX28_1", - "CLK_BUFG_IMUX28_2", - "CLK_BUFG_IMUX28_3", - "CLK_BUFG_IMUX29_0", - "CLK_BUFG_IMUX29_1", - "CLK_BUFG_IMUX29_2", - "CLK_BUFG_IMUX29_3", - "CLK_BUFG_IMUX2_0", - "CLK_BUFG_IMUX2_1", - "CLK_BUFG_IMUX2_2", - "CLK_BUFG_IMUX2_3", - "CLK_BUFG_IMUX30_0", - "CLK_BUFG_IMUX30_1", - "CLK_BUFG_IMUX30_2", - "CLK_BUFG_IMUX30_3", - "CLK_BUFG_IMUX31_0", - "CLK_BUFG_IMUX31_1", - "CLK_BUFG_IMUX31_2", - "CLK_BUFG_IMUX31_3", - "CLK_BUFG_IMUX32_0", - "CLK_BUFG_IMUX32_1", - "CLK_BUFG_IMUX32_2", - "CLK_BUFG_IMUX32_3", - "CLK_BUFG_IMUX33_0", - "CLK_BUFG_IMUX33_1", - "CLK_BUFG_IMUX33_2", - "CLK_BUFG_IMUX33_3", - "CLK_BUFG_IMUX34_0", - "CLK_BUFG_IMUX34_1", - "CLK_BUFG_IMUX34_2", - "CLK_BUFG_IMUX34_3", - "CLK_BUFG_IMUX35_0", - "CLK_BUFG_IMUX35_1", - "CLK_BUFG_IMUX35_2", - "CLK_BUFG_IMUX35_3", - "CLK_BUFG_IMUX36_0", - "CLK_BUFG_IMUX36_1", - "CLK_BUFG_IMUX36_2", - "CLK_BUFG_IMUX36_3", - "CLK_BUFG_IMUX37_0", - "CLK_BUFG_IMUX37_1", - "CLK_BUFG_IMUX37_2", - "CLK_BUFG_IMUX37_3", - "CLK_BUFG_IMUX38_0", - "CLK_BUFG_IMUX38_1", - "CLK_BUFG_IMUX38_2", - "CLK_BUFG_IMUX38_3", - "CLK_BUFG_IMUX39_0", - "CLK_BUFG_IMUX39_1", - "CLK_BUFG_IMUX39_2", - "CLK_BUFG_IMUX39_3", - "CLK_BUFG_IMUX3_0", - "CLK_BUFG_IMUX3_1", - "CLK_BUFG_IMUX3_2", - "CLK_BUFG_IMUX3_3", - "CLK_BUFG_IMUX40_0", - "CLK_BUFG_IMUX40_1", - "CLK_BUFG_IMUX40_2", - "CLK_BUFG_IMUX40_3", - "CLK_BUFG_IMUX41_0", - "CLK_BUFG_IMUX41_1", - "CLK_BUFG_IMUX41_2", - "CLK_BUFG_IMUX41_3", - "CLK_BUFG_IMUX42_0", - "CLK_BUFG_IMUX42_1", - "CLK_BUFG_IMUX42_2", - "CLK_BUFG_IMUX42_3", - "CLK_BUFG_IMUX43_0", - "CLK_BUFG_IMUX43_1", - "CLK_BUFG_IMUX43_2", - "CLK_BUFG_IMUX43_3", - "CLK_BUFG_IMUX44_0", - "CLK_BUFG_IMUX44_1", - "CLK_BUFG_IMUX44_2", - "CLK_BUFG_IMUX44_3", - "CLK_BUFG_IMUX45_0", - "CLK_BUFG_IMUX45_1", - "CLK_BUFG_IMUX45_2", - "CLK_BUFG_IMUX45_3", - "CLK_BUFG_IMUX46_0", - "CLK_BUFG_IMUX46_1", - "CLK_BUFG_IMUX46_2", - "CLK_BUFG_IMUX46_3", - "CLK_BUFG_IMUX47_0", - "CLK_BUFG_IMUX47_1", - "CLK_BUFG_IMUX47_2", - "CLK_BUFG_IMUX47_3", - "CLK_BUFG_IMUX4_0", - "CLK_BUFG_IMUX4_1", - "CLK_BUFG_IMUX4_2", - "CLK_BUFG_IMUX4_3", - "CLK_BUFG_IMUX5_0", - "CLK_BUFG_IMUX5_1", - "CLK_BUFG_IMUX5_2", - "CLK_BUFG_IMUX5_3", - "CLK_BUFG_IMUX6_0", - "CLK_BUFG_IMUX6_1", - "CLK_BUFG_IMUX6_2", - "CLK_BUFG_IMUX6_3", - "CLK_BUFG_IMUX7_0", - "CLK_BUFG_IMUX7_1", - "CLK_BUFG_IMUX7_2", - "CLK_BUFG_IMUX7_3", - "CLK_BUFG_IMUX8_0", - "CLK_BUFG_IMUX8_1", - "CLK_BUFG_IMUX8_2", - "CLK_BUFG_IMUX8_3", - "CLK_BUFG_IMUX9_0", - "CLK_BUFG_IMUX9_1", - "CLK_BUFG_IMUX9_2", - "CLK_BUFG_IMUX9_3", - "CLK_BUFG_LOGIC_OUTS_B0_0", - "CLK_BUFG_LOGIC_OUTS_B0_1", - "CLK_BUFG_LOGIC_OUTS_B0_2", - "CLK_BUFG_LOGIC_OUTS_B0_3", - "CLK_BUFG_LOGIC_OUTS_B10_0", - "CLK_BUFG_LOGIC_OUTS_B10_1", - "CLK_BUFG_LOGIC_OUTS_B10_2", - "CLK_BUFG_LOGIC_OUTS_B10_3", - "CLK_BUFG_LOGIC_OUTS_B11_0", - "CLK_BUFG_LOGIC_OUTS_B11_1", - "CLK_BUFG_LOGIC_OUTS_B11_2", - "CLK_BUFG_LOGIC_OUTS_B11_3", - "CLK_BUFG_LOGIC_OUTS_B12_0", - "CLK_BUFG_LOGIC_OUTS_B12_1", - "CLK_BUFG_LOGIC_OUTS_B12_2", - "CLK_BUFG_LOGIC_OUTS_B12_3", - "CLK_BUFG_LOGIC_OUTS_B13_0", - "CLK_BUFG_LOGIC_OUTS_B13_1", - "CLK_BUFG_LOGIC_OUTS_B13_2", - "CLK_BUFG_LOGIC_OUTS_B13_3", - "CLK_BUFG_LOGIC_OUTS_B14_0", - "CLK_BUFG_LOGIC_OUTS_B14_1", - "CLK_BUFG_LOGIC_OUTS_B14_2", - "CLK_BUFG_LOGIC_OUTS_B14_3", - "CLK_BUFG_LOGIC_OUTS_B15_0", - "CLK_BUFG_LOGIC_OUTS_B15_1", - "CLK_BUFG_LOGIC_OUTS_B15_2", - "CLK_BUFG_LOGIC_OUTS_B15_3", - "CLK_BUFG_LOGIC_OUTS_B16_0", - "CLK_BUFG_LOGIC_OUTS_B16_1", - "CLK_BUFG_LOGIC_OUTS_B16_2", - "CLK_BUFG_LOGIC_OUTS_B16_3", - "CLK_BUFG_LOGIC_OUTS_B17_0", - "CLK_BUFG_LOGIC_OUTS_B17_1", - "CLK_BUFG_LOGIC_OUTS_B17_2", - "CLK_BUFG_LOGIC_OUTS_B17_3", - "CLK_BUFG_LOGIC_OUTS_B18_0", - "CLK_BUFG_LOGIC_OUTS_B18_1", - "CLK_BUFG_LOGIC_OUTS_B18_2", - "CLK_BUFG_LOGIC_OUTS_B18_3", - "CLK_BUFG_LOGIC_OUTS_B19_0", - "CLK_BUFG_LOGIC_OUTS_B19_1", - "CLK_BUFG_LOGIC_OUTS_B19_2", - "CLK_BUFG_LOGIC_OUTS_B19_3", - "CLK_BUFG_LOGIC_OUTS_B1_0", - "CLK_BUFG_LOGIC_OUTS_B1_1", - "CLK_BUFG_LOGIC_OUTS_B1_2", - "CLK_BUFG_LOGIC_OUTS_B1_3", - "CLK_BUFG_LOGIC_OUTS_B20_0", - "CLK_BUFG_LOGIC_OUTS_B20_1", - "CLK_BUFG_LOGIC_OUTS_B20_2", - "CLK_BUFG_LOGIC_OUTS_B20_3", - "CLK_BUFG_LOGIC_OUTS_B21_0", - "CLK_BUFG_LOGIC_OUTS_B21_1", - "CLK_BUFG_LOGIC_OUTS_B21_2", - "CLK_BUFG_LOGIC_OUTS_B21_3", - "CLK_BUFG_LOGIC_OUTS_B22_0", - "CLK_BUFG_LOGIC_OUTS_B22_1", - "CLK_BUFG_LOGIC_OUTS_B22_2", - "CLK_BUFG_LOGIC_OUTS_B22_3", - "CLK_BUFG_LOGIC_OUTS_B23_0", - "CLK_BUFG_LOGIC_OUTS_B23_1", - "CLK_BUFG_LOGIC_OUTS_B23_2", - "CLK_BUFG_LOGIC_OUTS_B23_3", - "CLK_BUFG_LOGIC_OUTS_B2_0", - "CLK_BUFG_LOGIC_OUTS_B2_1", - "CLK_BUFG_LOGIC_OUTS_B2_2", - "CLK_BUFG_LOGIC_OUTS_B2_3", - "CLK_BUFG_LOGIC_OUTS_B3_0", - "CLK_BUFG_LOGIC_OUTS_B3_1", - "CLK_BUFG_LOGIC_OUTS_B3_2", - "CLK_BUFG_LOGIC_OUTS_B3_3", - "CLK_BUFG_LOGIC_OUTS_B4_0", - "CLK_BUFG_LOGIC_OUTS_B4_1", - "CLK_BUFG_LOGIC_OUTS_B4_2", - "CLK_BUFG_LOGIC_OUTS_B4_3", - "CLK_BUFG_LOGIC_OUTS_B5_0", - "CLK_BUFG_LOGIC_OUTS_B5_1", - "CLK_BUFG_LOGIC_OUTS_B5_2", - "CLK_BUFG_LOGIC_OUTS_B5_3", - "CLK_BUFG_LOGIC_OUTS_B6_0", - "CLK_BUFG_LOGIC_OUTS_B6_1", - "CLK_BUFG_LOGIC_OUTS_B6_2", - "CLK_BUFG_LOGIC_OUTS_B6_3", - "CLK_BUFG_LOGIC_OUTS_B7_0", - "CLK_BUFG_LOGIC_OUTS_B7_1", - "CLK_BUFG_LOGIC_OUTS_B7_2", - "CLK_BUFG_LOGIC_OUTS_B7_3", - "CLK_BUFG_LOGIC_OUTS_B8_0", - "CLK_BUFG_LOGIC_OUTS_B8_1", - "CLK_BUFG_LOGIC_OUTS_B8_2", - "CLK_BUFG_LOGIC_OUTS_B8_3", - "CLK_BUFG_LOGIC_OUTS_B9_0", - "CLK_BUFG_LOGIC_OUTS_B9_1", - "CLK_BUFG_LOGIC_OUTS_B9_2", - "CLK_BUFG_LOGIC_OUTS_B9_3", - "CLK_BUFG_R_BUFGCTRL0_CE0", - "CLK_BUFG_R_BUFGCTRL0_CE1", - "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "CLK_BUFG_R_BUFGCTRL0_S0", - "CLK_BUFG_R_BUFGCTRL0_S1", - "CLK_BUFG_R_BUFGCTRL10_CE0", - "CLK_BUFG_R_BUFGCTRL10_CE1", - "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "CLK_BUFG_R_BUFGCTRL10_S0", - "CLK_BUFG_R_BUFGCTRL10_S1", - "CLK_BUFG_R_BUFGCTRL11_CE0", - "CLK_BUFG_R_BUFGCTRL11_CE1", - "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "CLK_BUFG_R_BUFGCTRL11_S0", - "CLK_BUFG_R_BUFGCTRL11_S1", - "CLK_BUFG_R_BUFGCTRL12_CE0", - "CLK_BUFG_R_BUFGCTRL12_CE1", - "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "CLK_BUFG_R_BUFGCTRL12_S0", - "CLK_BUFG_R_BUFGCTRL12_S1", - "CLK_BUFG_R_BUFGCTRL13_CE0", - "CLK_BUFG_R_BUFGCTRL13_CE1", - "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "CLK_BUFG_R_BUFGCTRL13_S0", - "CLK_BUFG_R_BUFGCTRL13_S1", - "CLK_BUFG_R_BUFGCTRL14_CE0", - "CLK_BUFG_R_BUFGCTRL14_CE1", - "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "CLK_BUFG_R_BUFGCTRL14_S0", - "CLK_BUFG_R_BUFGCTRL14_S1", - "CLK_BUFG_R_BUFGCTRL15_CE0", - "CLK_BUFG_R_BUFGCTRL15_CE1", - "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "CLK_BUFG_R_BUFGCTRL15_S0", - "CLK_BUFG_R_BUFGCTRL15_S1", - "CLK_BUFG_R_BUFGCTRL1_CE0", - "CLK_BUFG_R_BUFGCTRL1_CE1", - "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "CLK_BUFG_R_BUFGCTRL1_S0", - "CLK_BUFG_R_BUFGCTRL1_S1", - "CLK_BUFG_R_BUFGCTRL2_CE0", - "CLK_BUFG_R_BUFGCTRL2_CE1", - "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "CLK_BUFG_R_BUFGCTRL2_S0", - "CLK_BUFG_R_BUFGCTRL2_S1", - "CLK_BUFG_R_BUFGCTRL3_CE0", - "CLK_BUFG_R_BUFGCTRL3_CE1", - "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "CLK_BUFG_R_BUFGCTRL3_S0", - "CLK_BUFG_R_BUFGCTRL3_S1", - "CLK_BUFG_R_BUFGCTRL4_CE0", - "CLK_BUFG_R_BUFGCTRL4_CE1", - "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "CLK_BUFG_R_BUFGCTRL4_S0", - "CLK_BUFG_R_BUFGCTRL4_S1", - "CLK_BUFG_R_BUFGCTRL5_CE0", - "CLK_BUFG_R_BUFGCTRL5_CE1", - "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "CLK_BUFG_R_BUFGCTRL5_S0", - "CLK_BUFG_R_BUFGCTRL5_S1", - "CLK_BUFG_R_BUFGCTRL6_CE0", - "CLK_BUFG_R_BUFGCTRL6_CE1", - "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "CLK_BUFG_R_BUFGCTRL6_S0", - "CLK_BUFG_R_BUFGCTRL6_S1", - "CLK_BUFG_R_BUFGCTRL7_CE0", - "CLK_BUFG_R_BUFGCTRL7_CE1", - "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "CLK_BUFG_R_BUFGCTRL7_S0", - "CLK_BUFG_R_BUFGCTRL7_S1", - "CLK_BUFG_R_BUFGCTRL8_CE0", - "CLK_BUFG_R_BUFGCTRL8_CE1", - "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "CLK_BUFG_R_BUFGCTRL8_S0", - "CLK_BUFG_R_BUFGCTRL8_S1", - "CLK_BUFG_R_BUFGCTRL9_CE0", - "CLK_BUFG_R_BUFGCTRL9_CE1", - "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "CLK_BUFG_R_BUFGCTRL9_S0", - "CLK_BUFG_R_BUFGCTRL9_S1", - "CLK_BUFG_R_CK_FB_TEST0_0", - "CLK_BUFG_R_CK_FB_TEST0_1", - "CLK_BUFG_R_CK_FB_TEST0_10", - "CLK_BUFG_R_CK_FB_TEST0_11", - "CLK_BUFG_R_CK_FB_TEST0_12", - "CLK_BUFG_R_CK_FB_TEST0_13", - "CLK_BUFG_R_CK_FB_TEST0_14", - "CLK_BUFG_R_CK_FB_TEST0_15", - "CLK_BUFG_R_CK_FB_TEST0_2", - "CLK_BUFG_R_CK_FB_TEST0_3", - "CLK_BUFG_R_CK_FB_TEST0_4", - "CLK_BUFG_R_CK_FB_TEST0_5", - "CLK_BUFG_R_CK_FB_TEST0_6", - "CLK_BUFG_R_CK_FB_TEST0_7", - "CLK_BUFG_R_CK_FB_TEST0_8", - "CLK_BUFG_R_CK_FB_TEST0_9", - "CLK_BUFG_R_CK_FB_TEST1_0", - "CLK_BUFG_R_CK_FB_TEST1_1", - "CLK_BUFG_R_CK_FB_TEST1_10", - "CLK_BUFG_R_CK_FB_TEST1_11", - "CLK_BUFG_R_CK_FB_TEST1_12", - "CLK_BUFG_R_CK_FB_TEST1_13", - "CLK_BUFG_R_CK_FB_TEST1_14", - "CLK_BUFG_R_CK_FB_TEST1_15", - "CLK_BUFG_R_CK_FB_TEST1_2", - "CLK_BUFG_R_CK_FB_TEST1_3", - "CLK_BUFG_R_CK_FB_TEST1_4", - "CLK_BUFG_R_CK_FB_TEST1_5", - "CLK_BUFG_R_CK_FB_TEST1_6", - "CLK_BUFG_R_CK_FB_TEST1_7", - "CLK_BUFG_R_CK_FB_TEST1_8", - "CLK_BUFG_R_CK_FB_TEST1_9", - "CLK_BUFG_R_FBG_OUT0", - "CLK_BUFG_R_FBG_OUT1", - "CLK_BUFG_R_FBG_OUT10", - "CLK_BUFG_R_FBG_OUT11", - "CLK_BUFG_R_FBG_OUT12", - "CLK_BUFG_R_FBG_OUT13", - "CLK_BUFG_R_FBG_OUT14", - "CLK_BUFG_R_FBG_OUT15", - "CLK_BUFG_R_FBG_OUT2", - "CLK_BUFG_R_FBG_OUT3", - "CLK_BUFG_R_FBG_OUT4", - "CLK_BUFG_R_FBG_OUT5", - "CLK_BUFG_R_FBG_OUT6", - "CLK_BUFG_R_FBG_OUT7", - "CLK_BUFG_R_FBG_OUT8", - "CLK_BUFG_R_FBG_OUT9", - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_BYP0_0", - "CLK_HROW_BYP0_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_BYP0_3", - "CLK_HROW_BYP1_0", - "CLK_HROW_BYP1_1", - "CLK_HROW_BYP1_2", - "CLK_HROW_BYP1_3", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_1", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_3", - "CLK_HROW_BYP3_0", - "CLK_HROW_BYP3_1", - "CLK_HROW_BYP3_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_BYP4_0", - "CLK_HROW_BYP4_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_BYP5_0", - "CLK_HROW_BYP5_1", - "CLK_HROW_BYP5_2", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP6_0", - "CLK_HROW_BYP6_1", - "CLK_HROW_BYP6_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_BYP7_0", - "CLK_HROW_BYP7_1", - "CLK_HROW_BYP7_2", - "CLK_HROW_BYP7_3", - "CLK_HROW_CLK0_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_CLK0_2", - "CLK_HROW_CLK0_3", - "CLK_HROW_CLK1_0", - "CLK_HROW_CLK1_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_CLK1_3", - "CLK_HROW_CTRL0_0", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CTRL0_2", - "CLK_HROW_CTRL0_3", - "CLK_HROW_CTRL1_0", - "CLK_HROW_CTRL1_1", - "CLK_HROW_CTRL1_2", - "CLK_HROW_CTRL1_3", - "CLK_HROW_EE2A0_0", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_EE2A0_3", - "CLK_HROW_EE2A1_0", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE2A1_2", - "CLK_HROW_EE2A1_3", - "CLK_HROW_EE2A2_0", - "CLK_HROW_EE2A2_1", - "CLK_HROW_EE2A2_2", - "CLK_HROW_EE2A2_3", - "CLK_HROW_EE2A3_0", - "CLK_HROW_EE2A3_1", - "CLK_HROW_EE2A3_2", - "CLK_HROW_EE2A3_3", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_EE4A0_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_EE4A0_2", - "CLK_HROW_EE4A0_3", - "CLK_HROW_EE4A1_0", - "CLK_HROW_EE4A1_1", - "CLK_HROW_EE4A1_2", - "CLK_HROW_EE4A1_3", - "CLK_HROW_EE4A2_0", - "CLK_HROW_EE4A2_1", - "CLK_HROW_EE4A2_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_EE4A3_0", - "CLK_HROW_EE4A3_1", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE4B0_0", - "CLK_HROW_EE4B0_1", - "CLK_HROW_EE4B0_2", - "CLK_HROW_EE4B0_3", - "CLK_HROW_EE4B1_0", - "CLK_HROW_EE4B1_1", - "CLK_HROW_EE4B1_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_EE4B2_0", - "CLK_HROW_EE4B2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_EE4B3_0", - "CLK_HROW_EE4B3_1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_EE4C0_0", - "CLK_HROW_EE4C0_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE4C0_3", - "CLK_HROW_EE4C1_0", - "CLK_HROW_EE4C1_1", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE4C1_3", - "CLK_HROW_EE4C2_0", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4C2_2", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4C3_0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_EE4C3_2", - "CLK_HROW_EE4C3_3", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_FAN0_0", - "CLK_HROW_FAN0_1", - "CLK_HROW_FAN0_2", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN1_0", - "CLK_HROW_FAN1_1", - "CLK_HROW_FAN1_2", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN2_0", - "CLK_HROW_FAN2_1", - "CLK_HROW_FAN2_2", - "CLK_HROW_FAN2_3", - "CLK_HROW_FAN3_0", - "CLK_HROW_FAN3_1", - "CLK_HROW_FAN3_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_FAN4_0", - "CLK_HROW_FAN4_1", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_3", - "CLK_HROW_FAN5_0", - "CLK_HROW_FAN5_1", - "CLK_HROW_FAN5_2", - "CLK_HROW_FAN5_3", - "CLK_HROW_FAN6_0", - "CLK_HROW_FAN6_1", - "CLK_HROW_FAN6_2", - "CLK_HROW_FAN6_3", - "CLK_HROW_FAN7_0", - "CLK_HROW_FAN7_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_FAN7_3", - "CLK_HROW_LH10_0", - "CLK_HROW_LH10_1", - "CLK_HROW_LH10_2", - "CLK_HROW_LH10_3", - "CLK_HROW_LH11_0", - "CLK_HROW_LH11_1", - "CLK_HROW_LH11_2", - "CLK_HROW_LH11_3", - "CLK_HROW_LH12_0", - "CLK_HROW_LH12_1", - "CLK_HROW_LH12_2", - "CLK_HROW_LH12_3", - "CLK_HROW_LH1_0", - "CLK_HROW_LH1_1", - "CLK_HROW_LH1_2", - "CLK_HROW_LH1_3", - "CLK_HROW_LH2_0", - "CLK_HROW_LH2_1", - "CLK_HROW_LH2_2", - "CLK_HROW_LH2_3", - "CLK_HROW_LH3_0", - "CLK_HROW_LH3_1", - "CLK_HROW_LH3_2", - "CLK_HROW_LH3_3", - "CLK_HROW_LH4_0", - "CLK_HROW_LH4_1", - "CLK_HROW_LH4_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LH5_0", - "CLK_HROW_LH5_1", - "CLK_HROW_LH5_2", - "CLK_HROW_LH5_3", - "CLK_HROW_LH6_0", - "CLK_HROW_LH6_1", - "CLK_HROW_LH6_2", - "CLK_HROW_LH6_3", - "CLK_HROW_LH7_0", - "CLK_HROW_LH7_1", - "CLK_HROW_LH7_2", - "CLK_HROW_LH7_3", - "CLK_HROW_LH8_0", - "CLK_HROW_LH8_1", - "CLK_HROW_LH8_2", - "CLK_HROW_LH8_3", - "CLK_HROW_LH9_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH9_2", - "CLK_HROW_LH9_3", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_NE2A0_0", - "CLK_HROW_NE2A0_1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A0_3", - "CLK_HROW_NE2A1_0", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NE2A1_2", - "CLK_HROW_NE2A1_3", - "CLK_HROW_NE2A2_0", - "CLK_HROW_NE2A2_1", - "CLK_HROW_NE2A2_2", - "CLK_HROW_NE2A2_3", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NE2A3_1", - "CLK_HROW_NE2A3_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_NE4C0_0", - "CLK_HROW_NE4C0_1", - "CLK_HROW_NE4C0_2", - "CLK_HROW_NE4C0_3", - "CLK_HROW_NE4C1_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_NE4C1_3", - "CLK_HROW_NE4C2_0", - "CLK_HROW_NE4C2_1", - "CLK_HROW_NE4C2_2", - "CLK_HROW_NE4C2_3", - "CLK_HROW_NE4C3_0", - "CLK_HROW_NE4C3_1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_NE4C3_3", - "CLK_HROW_NW2A0_0", - "CLK_HROW_NW2A0_1", - "CLK_HROW_NW2A0_2", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_NW2A1_2", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A2_0", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW2A2_3", - "CLK_HROW_NW2A3_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_NW2A3_2", - "CLK_HROW_NW2A3_3", - "CLK_HROW_NW4A0_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_NW4A0_3", - "CLK_HROW_NW4A1_0", - "CLK_HROW_NW4A1_1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_NW4A1_3", - "CLK_HROW_NW4A2_0", - "CLK_HROW_NW4A2_1", - "CLK_HROW_NW4A2_2", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A3_0", - "CLK_HROW_NW4A3_1", - "CLK_HROW_NW4A3_2", - "CLK_HROW_NW4A3_3", - "CLK_HROW_NW4END0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_NW4END0_3", - "CLK_HROW_NW4END1_0", - "CLK_HROW_NW4END1_1", - "CLK_HROW_NW4END1_2", - "CLK_HROW_NW4END1_3", - "CLK_HROW_NW4END2_0", - "CLK_HROW_NW4END2_1", - "CLK_HROW_NW4END2_2", - "CLK_HROW_NW4END2_3", - "CLK_HROW_NW4END3_0", - "CLK_HROW_NW4END3_1", - "CLK_HROW_NW4END3_2", - "CLK_HROW_NW4END3_3", - "CLK_HROW_SE2A0_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_SE2A0_3", - "CLK_HROW_SE2A1_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_SE2A1_2", - "CLK_HROW_SE2A1_3", - "CLK_HROW_SE2A2_0", - "CLK_HROW_SE2A2_1", - "CLK_HROW_SE2A2_2", - "CLK_HROW_SE2A2_3", - "CLK_HROW_SE2A3_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_SE2A3_2", - "CLK_HROW_SE2A3_3", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_SE4C0_0", - "CLK_HROW_SE4C0_1", - "CLK_HROW_SE4C0_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SE4C1_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_SE4C1_3", - "CLK_HROW_SE4C2_0", - "CLK_HROW_SE4C2_1", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SE4C2_3", - "CLK_HROW_SE4C3_0", - "CLK_HROW_SE4C3_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_SW2A0_0", - "CLK_HROW_SW2A0_1", - "CLK_HROW_SW2A0_2", - "CLK_HROW_SW2A0_3", - "CLK_HROW_SW2A1_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_SW2A1_3", - "CLK_HROW_SW2A2_0", - "CLK_HROW_SW2A2_1", - "CLK_HROW_SW2A2_2", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SW2A3_0", - "CLK_HROW_SW2A3_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_SW2A3_3", - "CLK_HROW_SW4A0_0", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_SW4A1_0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_SW4A1_2", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_1", - "CLK_HROW_SW4A2_2", - "CLK_HROW_SW4A2_3", - "CLK_HROW_SW4A3_0", - "CLK_HROW_SW4A3_1", - "CLK_HROW_SW4A3_2", - "CLK_HROW_SW4A3_3", - "CLK_HROW_SW4END0_0", - "CLK_HROW_SW4END0_1", - "CLK_HROW_SW4END0_2", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW4END1_0", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SW4END1_2", - "CLK_HROW_SW4END1_3", - "CLK_HROW_SW4END2_0", - "CLK_HROW_SW4END2_1", - "CLK_HROW_SW4END2_2", - "CLK_HROW_SW4END2_3", - "CLK_HROW_SW4END3_0", - "CLK_HROW_SW4END3_1", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_1", - "CLK_HROW_WL1END0_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_WL1END1_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_WL1END2_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WL1END3_0", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WL1END3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_WR1END0_0", - "CLK_HROW_WR1END0_1", - "CLK_HROW_WR1END0_2", - "CLK_HROW_WR1END0_3", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WR1END1_1", - "CLK_HROW_WR1END1_2", - "CLK_HROW_WR1END1_3", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WR1END2_1", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_WR1END3_2", - "CLK_HROW_WR1END3_3", - "CLK_HROW_WW2A0_0", - "CLK_HROW_WW2A0_1", - "CLK_HROW_WW2A0_2", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WW2A1_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_WW2A1_3", - "CLK_HROW_WW2A2_0", - "CLK_HROW_WW2A2_1", - "CLK_HROW_WW2A2_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_WW2A3_0", - "CLK_HROW_WW2A3_1", - "CLK_HROW_WW2A3_2", - "CLK_HROW_WW2A3_3", - "CLK_HROW_WW2END0_0", - "CLK_HROW_WW2END0_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_WW2END0_3", - "CLK_HROW_WW2END1_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_WW2END1_2", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW2END2_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW2END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_WW2END3_2", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW4A0_0", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4A0_2", - "CLK_HROW_WW4A0_3", - "CLK_HROW_WW4A1_0", - "CLK_HROW_WW4A1_1", - "CLK_HROW_WW4A1_2", - "CLK_HROW_WW4A1_3", - "CLK_HROW_WW4A2_0", - "CLK_HROW_WW4A2_1", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW4A2_3", - "CLK_HROW_WW4A3_0", - "CLK_HROW_WW4A3_1", - "CLK_HROW_WW4A3_2", - "CLK_HROW_WW4A3_3", - "CLK_HROW_WW4B0_0", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4B0_2", - "CLK_HROW_WW4B0_3", - "CLK_HROW_WW4B1_0", - "CLK_HROW_WW4B1_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_WW4B1_3", - "CLK_HROW_WW4B2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_WW4B2_2", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4B3_0", - "CLK_HROW_WW4B3_1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_WW4B3_3", - "CLK_HROW_WW4C0_0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_WW4C0_2", - "CLK_HROW_WW4C0_3", - "CLK_HROW_WW4C1_0", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WW4C1_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_WW4C2_0", - "CLK_HROW_WW4C2_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_WW4C2_3", - "CLK_HROW_WW4C3_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_WW4C3_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_WW4END0_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW4END0_2", - "CLK_HROW_WW4END0_3", - "CLK_HROW_WW4END1_0", - "CLK_HROW_WW4END1_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_WW4END1_3", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_WW4END2_3", - "CLK_HROW_WW4END3_0", - "CLK_HROW_WW4END3_1", - "CLK_HROW_WW4END3_2", - "CLK_HROW_WW4END3_3" - ] + "wires": { + "CLK_BUFG_BOT_R_CK_MUXED0": null, + "CLK_BUFG_BOT_R_CK_MUXED1": null, + "CLK_BUFG_BOT_R_CK_MUXED10": null, + "CLK_BUFG_BOT_R_CK_MUXED11": null, + "CLK_BUFG_BOT_R_CK_MUXED12": null, + "CLK_BUFG_BOT_R_CK_MUXED13": null, + "CLK_BUFG_BOT_R_CK_MUXED14": null, + "CLK_BUFG_BOT_R_CK_MUXED15": null, + "CLK_BUFG_BOT_R_CK_MUXED16": null, + "CLK_BUFG_BOT_R_CK_MUXED17": null, + "CLK_BUFG_BOT_R_CK_MUXED18": null, + "CLK_BUFG_BOT_R_CK_MUXED19": null, + "CLK_BUFG_BOT_R_CK_MUXED2": null, + "CLK_BUFG_BOT_R_CK_MUXED20": null, + "CLK_BUFG_BOT_R_CK_MUXED21": null, + "CLK_BUFG_BOT_R_CK_MUXED22": null, + "CLK_BUFG_BOT_R_CK_MUXED23": null, + "CLK_BUFG_BOT_R_CK_MUXED24": null, + "CLK_BUFG_BOT_R_CK_MUXED25": null, + "CLK_BUFG_BOT_R_CK_MUXED26": null, + "CLK_BUFG_BOT_R_CK_MUXED27": null, + "CLK_BUFG_BOT_R_CK_MUXED28": null, + "CLK_BUFG_BOT_R_CK_MUXED29": null, + "CLK_BUFG_BOT_R_CK_MUXED3": null, + "CLK_BUFG_BOT_R_CK_MUXED30": null, + "CLK_BUFG_BOT_R_CK_MUXED31": null, + "CLK_BUFG_BOT_R_CK_MUXED4": null, + "CLK_BUFG_BOT_R_CK_MUXED5": null, + "CLK_BUFG_BOT_R_CK_MUXED6": null, + "CLK_BUFG_BOT_R_CK_MUXED7": null, + "CLK_BUFG_BOT_R_CK_MUXED8": null, + "CLK_BUFG_BOT_R_CK_MUXED9": null, + "CLK_BUFG_BUFGCTRL0_I0": null, + "CLK_BUFG_BUFGCTRL0_I1": null, + "CLK_BUFG_BUFGCTRL0_O": null, + "CLK_BUFG_BUFGCTRL10_I0": null, + "CLK_BUFG_BUFGCTRL10_I1": null, + "CLK_BUFG_BUFGCTRL10_O": null, + "CLK_BUFG_BUFGCTRL11_I0": null, + "CLK_BUFG_BUFGCTRL11_I1": null, + "CLK_BUFG_BUFGCTRL11_O": null, + "CLK_BUFG_BUFGCTRL12_I0": null, + "CLK_BUFG_BUFGCTRL12_I1": null, + "CLK_BUFG_BUFGCTRL12_O": null, + "CLK_BUFG_BUFGCTRL13_I0": null, + "CLK_BUFG_BUFGCTRL13_I1": null, + "CLK_BUFG_BUFGCTRL13_O": null, + "CLK_BUFG_BUFGCTRL14_I0": null, + "CLK_BUFG_BUFGCTRL14_I1": null, + "CLK_BUFG_BUFGCTRL14_O": null, + "CLK_BUFG_BUFGCTRL15_I0": null, + "CLK_BUFG_BUFGCTRL15_I1": null, + "CLK_BUFG_BUFGCTRL15_O": null, + "CLK_BUFG_BUFGCTRL1_I0": null, + "CLK_BUFG_BUFGCTRL1_I1": null, + "CLK_BUFG_BUFGCTRL1_O": null, + "CLK_BUFG_BUFGCTRL2_I0": null, + "CLK_BUFG_BUFGCTRL2_I1": null, + "CLK_BUFG_BUFGCTRL2_O": null, + "CLK_BUFG_BUFGCTRL3_I0": null, + "CLK_BUFG_BUFGCTRL3_I1": null, + "CLK_BUFG_BUFGCTRL3_O": null, + "CLK_BUFG_BUFGCTRL4_I0": null, + "CLK_BUFG_BUFGCTRL4_I1": null, + "CLK_BUFG_BUFGCTRL4_O": null, + "CLK_BUFG_BUFGCTRL5_I0": null, + "CLK_BUFG_BUFGCTRL5_I1": null, + "CLK_BUFG_BUFGCTRL5_O": null, + "CLK_BUFG_BUFGCTRL6_I0": null, + "CLK_BUFG_BUFGCTRL6_I1": null, + "CLK_BUFG_BUFGCTRL6_O": null, + "CLK_BUFG_BUFGCTRL7_I0": null, + "CLK_BUFG_BUFGCTRL7_I1": null, + "CLK_BUFG_BUFGCTRL7_O": null, + "CLK_BUFG_BUFGCTRL8_I0": null, + "CLK_BUFG_BUFGCTRL8_I1": null, + "CLK_BUFG_BUFGCTRL8_O": null, + "CLK_BUFG_BUFGCTRL9_I0": null, + "CLK_BUFG_BUFGCTRL9_I1": null, + "CLK_BUFG_BUFGCTRL9_O": null, + "CLK_BUFG_CK_GCLK0": null, + "CLK_BUFG_CK_GCLK1": null, + "CLK_BUFG_CK_GCLK10": null, + "CLK_BUFG_CK_GCLK11": null, + "CLK_BUFG_CK_GCLK12": null, + "CLK_BUFG_CK_GCLK13": null, + "CLK_BUFG_CK_GCLK14": null, + "CLK_BUFG_CK_GCLK15": null, + "CLK_BUFG_CK_GCLK16": null, + "CLK_BUFG_CK_GCLK17": null, + "CLK_BUFG_CK_GCLK18": null, + "CLK_BUFG_CK_GCLK19": null, + "CLK_BUFG_CK_GCLK2": null, + "CLK_BUFG_CK_GCLK20": null, + "CLK_BUFG_CK_GCLK21": null, + "CLK_BUFG_CK_GCLK22": null, + "CLK_BUFG_CK_GCLK23": null, + "CLK_BUFG_CK_GCLK24": null, + "CLK_BUFG_CK_GCLK25": null, + "CLK_BUFG_CK_GCLK26": null, + "CLK_BUFG_CK_GCLK27": null, + "CLK_BUFG_CK_GCLK28": null, + "CLK_BUFG_CK_GCLK29": null, + "CLK_BUFG_CK_GCLK3": null, + "CLK_BUFG_CK_GCLK30": null, + "CLK_BUFG_CK_GCLK31": null, + "CLK_BUFG_CK_GCLK4": null, + "CLK_BUFG_CK_GCLK5": null, + "CLK_BUFG_CK_GCLK6": null, + "CLK_BUFG_CK_GCLK7": null, + "CLK_BUFG_CK_GCLK8": null, + "CLK_BUFG_CK_GCLK9": null, + "CLK_BUFG_IMUX0_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX25_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX25_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX25_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX25_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX26_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX26_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX26_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX26_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX27_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX27_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX27_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX27_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX28_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX28_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX28_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX28_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX29_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX29_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX29_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX29_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX2_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX2_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX2_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX2_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX30_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX30_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX30_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX30_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX31_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX31_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX31_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX31_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX32_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX32_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX32_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX32_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX33_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX33_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX33_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX33_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX34_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX34_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX34_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX34_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX35_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX35_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX35_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX35_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX36_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX36_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX36_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX36_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX37_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX37_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX37_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX37_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX38_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX38_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX38_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX38_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX39_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX39_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX39_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX39_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX3_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX3_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX3_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX3_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX40_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX40_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX40_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX40_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX41_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX41_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX41_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX41_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX42_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX42_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX42_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX42_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX43_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX43_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX43_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX43_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX44_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX44_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX44_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX44_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX45_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX45_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX45_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX45_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX46_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX46_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX46_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX46_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX47_0": { + "cap": "25.974", + "res": "0.000" + }, + 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"CLK_BUFG_R_BUFGCTRL1_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL1_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL1_S0": null, + "CLK_BUFG_R_BUFGCTRL1_S1": null, + "CLK_BUFG_R_BUFGCTRL2_CE0": null, + "CLK_BUFG_R_BUFGCTRL2_CE1": null, + "CLK_BUFG_R_BUFGCTRL2_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL2_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL2_S0": null, + "CLK_BUFG_R_BUFGCTRL2_S1": null, + "CLK_BUFG_R_BUFGCTRL3_CE0": null, + "CLK_BUFG_R_BUFGCTRL3_CE1": null, + "CLK_BUFG_R_BUFGCTRL3_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL3_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL3_S0": null, + "CLK_BUFG_R_BUFGCTRL3_S1": null, + "CLK_BUFG_R_BUFGCTRL4_CE0": null, + "CLK_BUFG_R_BUFGCTRL4_CE1": null, + "CLK_BUFG_R_BUFGCTRL4_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL4_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL4_S0": null, + "CLK_BUFG_R_BUFGCTRL4_S1": null, + "CLK_BUFG_R_BUFGCTRL5_CE0": null, + "CLK_BUFG_R_BUFGCTRL5_CE1": null, + "CLK_BUFG_R_BUFGCTRL5_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL5_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL5_S0": null, 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"CLK_BUFG_R_CK_FB_TEST0_10": null, + "CLK_BUFG_R_CK_FB_TEST0_11": null, + "CLK_BUFG_R_CK_FB_TEST0_12": null, + "CLK_BUFG_R_CK_FB_TEST0_13": null, + "CLK_BUFG_R_CK_FB_TEST0_14": null, + "CLK_BUFG_R_CK_FB_TEST0_15": null, + "CLK_BUFG_R_CK_FB_TEST0_2": null, + "CLK_BUFG_R_CK_FB_TEST0_3": null, + "CLK_BUFG_R_CK_FB_TEST0_4": null, + "CLK_BUFG_R_CK_FB_TEST0_5": null, + "CLK_BUFG_R_CK_FB_TEST0_6": null, + "CLK_BUFG_R_CK_FB_TEST0_7": null, + "CLK_BUFG_R_CK_FB_TEST0_8": null, + "CLK_BUFG_R_CK_FB_TEST0_9": null, + "CLK_BUFG_R_CK_FB_TEST1_0": null, + "CLK_BUFG_R_CK_FB_TEST1_1": null, + "CLK_BUFG_R_CK_FB_TEST1_10": null, + "CLK_BUFG_R_CK_FB_TEST1_11": null, + "CLK_BUFG_R_CK_FB_TEST1_12": null, + "CLK_BUFG_R_CK_FB_TEST1_13": null, + "CLK_BUFG_R_CK_FB_TEST1_14": null, + "CLK_BUFG_R_CK_FB_TEST1_15": null, + "CLK_BUFG_R_CK_FB_TEST1_2": null, + "CLK_BUFG_R_CK_FB_TEST1_3": null, + "CLK_BUFG_R_CK_FB_TEST1_4": null, + "CLK_BUFG_R_CK_FB_TEST1_5": null, + "CLK_BUFG_R_CK_FB_TEST1_6": null, + "CLK_BUFG_R_CK_FB_TEST1_7": null, + "CLK_BUFG_R_CK_FB_TEST1_8": null, + "CLK_BUFG_R_CK_FB_TEST1_9": null, + "CLK_BUFG_R_FBG_OUT0": null, + "CLK_BUFG_R_FBG_OUT1": null, + "CLK_BUFG_R_FBG_OUT10": null, + "CLK_BUFG_R_FBG_OUT11": null, + "CLK_BUFG_R_FBG_OUT12": null, + "CLK_BUFG_R_FBG_OUT13": null, + "CLK_BUFG_R_FBG_OUT14": null, + "CLK_BUFG_R_FBG_OUT15": null, + "CLK_BUFG_R_FBG_OUT2": null, + "CLK_BUFG_R_FBG_OUT3": null, + "CLK_BUFG_R_FBG_OUT4": null, + "CLK_BUFG_R_FBG_OUT5": null, + "CLK_BUFG_R_FBG_OUT6": null, + "CLK_BUFG_R_FBG_OUT7": null, + "CLK_BUFG_R_FBG_OUT8": null, + "CLK_BUFG_R_FBG_OUT9": null, + "CLK_HROW_BLOCK_OUTS_B0_0": null, + "CLK_HROW_BLOCK_OUTS_B0_1": null, + "CLK_HROW_BLOCK_OUTS_B0_2": null, + "CLK_HROW_BLOCK_OUTS_B0_3": null, + "CLK_HROW_BLOCK_OUTS_B1_0": null, + "CLK_HROW_BLOCK_OUTS_B1_1": null, + "CLK_HROW_BLOCK_OUTS_B1_2": null, + "CLK_HROW_BLOCK_OUTS_B1_3": null, + "CLK_HROW_BLOCK_OUTS_B2_0": null, + "CLK_HROW_BLOCK_OUTS_B2_1": null, + "CLK_HROW_BLOCK_OUTS_B2_2": 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"CLK_HROW_SE4C3_0": null, + "CLK_HROW_SE4C3_1": null, + "CLK_HROW_SE4C3_2": null, + "CLK_HROW_SE4C3_3": null, + "CLK_HROW_SW2A0_0": null, + "CLK_HROW_SW2A0_1": null, + "CLK_HROW_SW2A0_2": null, + "CLK_HROW_SW2A0_3": null, + "CLK_HROW_SW2A1_0": null, + "CLK_HROW_SW2A1_1": null, + "CLK_HROW_SW2A1_2": null, + "CLK_HROW_SW2A1_3": null, + "CLK_HROW_SW2A2_0": null, + "CLK_HROW_SW2A2_1": null, + "CLK_HROW_SW2A2_2": null, + "CLK_HROW_SW2A2_3": null, + "CLK_HROW_SW2A3_0": null, + "CLK_HROW_SW2A3_1": null, + "CLK_HROW_SW2A3_2": null, + "CLK_HROW_SW2A3_3": null, + "CLK_HROW_SW4A0_0": null, + "CLK_HROW_SW4A0_1": null, + "CLK_HROW_SW4A0_2": null, + "CLK_HROW_SW4A0_3": null, + "CLK_HROW_SW4A1_0": null, + "CLK_HROW_SW4A1_1": null, + "CLK_HROW_SW4A1_2": null, + "CLK_HROW_SW4A1_3": null, + "CLK_HROW_SW4A2_0": null, + "CLK_HROW_SW4A2_1": null, + "CLK_HROW_SW4A2_2": null, + "CLK_HROW_SW4A2_3": null, + "CLK_HROW_SW4A3_0": null, + "CLK_HROW_SW4A3_1": null, + "CLK_HROW_SW4A3_2": null, + "CLK_HROW_SW4A3_3": null, + "CLK_HROW_SW4END0_0": null, + "CLK_HROW_SW4END0_1": null, + "CLK_HROW_SW4END0_2": null, + "CLK_HROW_SW4END0_3": null, + "CLK_HROW_SW4END1_0": null, + "CLK_HROW_SW4END1_1": null, + "CLK_HROW_SW4END1_2": null, + "CLK_HROW_SW4END1_3": null, + "CLK_HROW_SW4END2_0": null, + "CLK_HROW_SW4END2_1": null, + "CLK_HROW_SW4END2_2": null, + "CLK_HROW_SW4END2_3": null, + "CLK_HROW_SW4END3_0": null, + "CLK_HROW_SW4END3_1": null, + "CLK_HROW_SW4END3_2": null, + "CLK_HROW_SW4END3_3": null, + "CLK_HROW_WL1END0_0": null, + "CLK_HROW_WL1END0_1": null, + "CLK_HROW_WL1END0_2": null, + "CLK_HROW_WL1END0_3": null, + "CLK_HROW_WL1END1_0": null, + "CLK_HROW_WL1END1_1": null, + "CLK_HROW_WL1END1_2": null, + "CLK_HROW_WL1END1_3": null, + "CLK_HROW_WL1END2_0": null, + "CLK_HROW_WL1END2_1": null, + "CLK_HROW_WL1END2_2": null, + "CLK_HROW_WL1END2_3": null, + "CLK_HROW_WL1END3_0": null, + "CLK_HROW_WL1END3_1": null, + "CLK_HROW_WL1END3_2": null, + "CLK_HROW_WL1END3_3": null, + "CLK_HROW_WR1END0_0": null, + "CLK_HROW_WR1END0_1": null, + "CLK_HROW_WR1END0_2": null, + "CLK_HROW_WR1END0_3": null, + "CLK_HROW_WR1END1_0": null, + "CLK_HROW_WR1END1_1": null, + "CLK_HROW_WR1END1_2": null, + "CLK_HROW_WR1END1_3": null, + "CLK_HROW_WR1END2_0": null, + "CLK_HROW_WR1END2_1": null, + "CLK_HROW_WR1END2_2": null, + "CLK_HROW_WR1END2_3": null, + "CLK_HROW_WR1END3_0": null, + "CLK_HROW_WR1END3_1": null, + "CLK_HROW_WR1END3_2": null, + "CLK_HROW_WR1END3_3": null, + "CLK_HROW_WW2A0_0": null, + "CLK_HROW_WW2A0_1": null, + "CLK_HROW_WW2A0_2": null, + "CLK_HROW_WW2A0_3": null, + "CLK_HROW_WW2A1_0": null, + "CLK_HROW_WW2A1_1": null, + "CLK_HROW_WW2A1_2": null, + "CLK_HROW_WW2A1_3": null, + "CLK_HROW_WW2A2_0": null, + "CLK_HROW_WW2A2_1": null, + "CLK_HROW_WW2A2_2": null, + "CLK_HROW_WW2A2_3": null, + "CLK_HROW_WW2A3_0": null, + "CLK_HROW_WW2A3_1": null, + "CLK_HROW_WW2A3_2": null, + "CLK_HROW_WW2A3_3": null, + "CLK_HROW_WW2END0_0": null, + "CLK_HROW_WW2END0_1": null, + "CLK_HROW_WW2END0_2": null, + "CLK_HROW_WW2END0_3": null, + "CLK_HROW_WW2END1_0": null, + "CLK_HROW_WW2END1_1": null, + "CLK_HROW_WW2END1_2": null, + "CLK_HROW_WW2END1_3": null, + "CLK_HROW_WW2END2_0": null, + "CLK_HROW_WW2END2_1": null, + "CLK_HROW_WW2END2_2": null, + "CLK_HROW_WW2END2_3": null, + "CLK_HROW_WW2END3_0": null, + "CLK_HROW_WW2END3_1": null, + "CLK_HROW_WW2END3_2": null, + "CLK_HROW_WW2END3_3": null, + "CLK_HROW_WW4A0_0": null, + "CLK_HROW_WW4A0_1": null, + "CLK_HROW_WW4A0_2": null, + "CLK_HROW_WW4A0_3": null, + "CLK_HROW_WW4A1_0": null, + "CLK_HROW_WW4A1_1": null, + "CLK_HROW_WW4A1_2": null, + "CLK_HROW_WW4A1_3": null, + "CLK_HROW_WW4A2_0": null, + "CLK_HROW_WW4A2_1": null, + "CLK_HROW_WW4A2_2": null, + "CLK_HROW_WW4A2_3": null, + "CLK_HROW_WW4A3_0": null, + "CLK_HROW_WW4A3_1": null, + "CLK_HROW_WW4A3_2": null, + "CLK_HROW_WW4A3_3": null, + "CLK_HROW_WW4B0_0": null, + "CLK_HROW_WW4B0_1": null, + "CLK_HROW_WW4B0_2": null, + "CLK_HROW_WW4B0_3": null, + "CLK_HROW_WW4B1_0": null, + "CLK_HROW_WW4B1_1": null, + "CLK_HROW_WW4B1_2": null, + "CLK_HROW_WW4B1_3": null, + "CLK_HROW_WW4B2_0": null, + "CLK_HROW_WW4B2_1": null, + "CLK_HROW_WW4B2_2": null, + "CLK_HROW_WW4B2_3": null, + "CLK_HROW_WW4B3_0": null, + "CLK_HROW_WW4B3_1": null, + "CLK_HROW_WW4B3_2": null, + "CLK_HROW_WW4B3_3": null, + "CLK_HROW_WW4C0_0": null, + "CLK_HROW_WW4C0_1": null, + "CLK_HROW_WW4C0_2": null, + "CLK_HROW_WW4C0_3": null, + "CLK_HROW_WW4C1_0": null, + "CLK_HROW_WW4C1_1": null, + "CLK_HROW_WW4C1_2": null, + "CLK_HROW_WW4C1_3": null, + "CLK_HROW_WW4C2_0": null, + "CLK_HROW_WW4C2_1": null, + "CLK_HROW_WW4C2_2": null, + "CLK_HROW_WW4C2_3": null, + "CLK_HROW_WW4C3_0": null, + "CLK_HROW_WW4C3_1": null, + "CLK_HROW_WW4C3_2": null, + "CLK_HROW_WW4C3_3": null, + "CLK_HROW_WW4END0_0": null, + "CLK_HROW_WW4END0_1": null, + "CLK_HROW_WW4END0_2": null, + "CLK_HROW_WW4END0_3": null, + "CLK_HROW_WW4END1_0": null, + "CLK_HROW_WW4END1_1": null, + "CLK_HROW_WW4END1_2": null, + "CLK_HROW_WW4END1_3": null, + "CLK_HROW_WW4END2_0": null, + "CLK_HROW_WW4END2_1": null, + "CLK_HROW_WW4END2_2": null, + "CLK_HROW_WW4END2_3": null, + "CLK_HROW_WW4END3_0": null, + "CLK_HROW_WW4END3_1": null, + "CLK_HROW_WW4END3_2": null, + "CLK_HROW_WW4END3_3": null + } } diff --git a/kintex7/tile_type_CLK_BUFG_REBUF.json b/kintex7/tile_type_CLK_BUFG_REBUF.json index 9473289..bd161eb 100644 --- a/kintex7/tile_type_CLK_BUFG_REBUF.json +++ b/kintex7/tile_type_CLK_BUFG_REBUF.json @@ -2,1187 +2,3203 @@ "pips": { "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT->>GCLK0_1_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK0_1_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK0_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT->>GCLK10_11_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK10_11_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK10_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK11_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK11_TOP->>GCLK11_10_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK11_10_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT->>GCLK12_13_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK12_13_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK12_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK13_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK13_TOP->>GCLK13_12_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK13_12_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT->>GCLK14_15_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK14_15_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK14_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK15_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK15_TOP->>GCLK15_14_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK15_14_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT->>GCLK16_17_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK16_17_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK16_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK17_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK17_TOP->>GCLK17_16_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK17_16_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT->>GCLK18_19_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK18_19_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK18_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK18_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK19_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK19_TOP->>GCLK19_18_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK19_18_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK1_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK1_TOP->>GCLK1_0_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK1_0_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT->>GCLK20_21_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK20_21_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK20_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK21_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK21_TOP->>GCLK21_20_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK21_20_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT->>GCLK22_23_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK22_23_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK22_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK23_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK23_TOP->>GCLK23_22_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK23_22_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT->>GCLK24_25_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK24_25_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK24_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK25_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK25_TOP->>GCLK25_24_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK25_24_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT->>GCLK26_27_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK26_27_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK26_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK27_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK27_TOP->>GCLK27_26_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK27_26_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT->>GCLK28_29_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK28_29_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK28_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK29_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK29_TOP->>GCLK29_28_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK29_28_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT->>GCLK2_3_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK2_3_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK2_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT->>GCLK30_31_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK30_31_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK30_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK31_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK31_TOP->>GCLK31_30_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK31_30_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK3_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK3_TOP->>GCLK3_2_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK3_2_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT->>GCLK4_5_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK4_5_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK4_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK5_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK5_TOP->>GCLK5_4_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK5_4_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT->>GCLK6_7_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK6_7_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK6_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK7_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK7_TOP->>GCLK7_6_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK7_6_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_TOP" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT->>GCLK8_9_DN_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK8_9_DN_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK8_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_BOT<<->>CLK_BUFG_REBUF_R_CK_GCLK9_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT" }, "CLK_BUFG_REBUF.CLK_BUFG_REBUF_R_CK_GCLK9_TOP->>GCLK9_8_UP_TEST_RING_IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "GCLK9_8_UP_TEST_RING_IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_TOP" }, "CLK_BUFG_REBUF.GCLK0_1_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK1_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK0_1_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK10_11_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK11_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK10_11_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK11_10_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK10_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK11_10_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK12_13_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK13_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK12_13_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK13_12_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK12_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK13_12_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK14_15_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK15_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK14_15_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK15_14_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK14_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK15_14_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK16_17_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK17_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK16_17_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK17_16_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK16_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK17_16_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK18_19_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK19_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK18_19_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK19_18_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK18_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK19_18_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK1_0_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK0_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK1_0_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK20_21_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK21_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK20_21_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK21_20_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK20_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK21_20_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK22_23_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK23_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK22_23_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK23_22_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK22_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK23_22_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK24_25_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK25_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK24_25_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK25_24_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK24_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK25_24_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK26_27_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK27_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK26_27_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK27_26_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK26_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK27_26_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK28_29_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK29_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK28_29_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK29_28_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK28_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK29_28_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK2_3_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK3_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK2_3_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK30_31_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK31_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK30_31_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK31_30_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK30_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK31_30_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK3_2_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK2_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK3_2_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK4_5_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK5_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK4_5_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK5_4_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK4_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK5_4_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK6_7_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK7_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK6_7_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK7_6_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK6_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK7_6_UP_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK8_9_DN_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK9_BOT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK8_9_DN_TEST_RING_OUT" }, "CLK_BUFG_REBUF.GCLK9_8_UP_TEST_RING_OUT->>CLK_BUFG_REBUF_R_CK_GCLK8_TOP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GCLK9_8_UP_TEST_RING_OUT" } }, "sites": [], "tile_type": "CLK_BUFG_REBUF", - "wires": [ - "CLK_BUFG_REBUF_CK_BUFG_CASC0", - "CLK_BUFG_REBUF_CK_BUFG_CASC1", - "CLK_BUFG_REBUF_CK_BUFG_CASC10", - "CLK_BUFG_REBUF_CK_BUFG_CASC11", - "CLK_BUFG_REBUF_CK_BUFG_CASC12", - "CLK_BUFG_REBUF_CK_BUFG_CASC13", - "CLK_BUFG_REBUF_CK_BUFG_CASC14", - "CLK_BUFG_REBUF_CK_BUFG_CASC15", - "CLK_BUFG_REBUF_CK_BUFG_CASC16", - "CLK_BUFG_REBUF_CK_BUFG_CASC17", - "CLK_BUFG_REBUF_CK_BUFG_CASC18", - "CLK_BUFG_REBUF_CK_BUFG_CASC19", - "CLK_BUFG_REBUF_CK_BUFG_CASC2", - "CLK_BUFG_REBUF_CK_BUFG_CASC20", - "CLK_BUFG_REBUF_CK_BUFG_CASC21", - "CLK_BUFG_REBUF_CK_BUFG_CASC22", - "CLK_BUFG_REBUF_CK_BUFG_CASC23", - "CLK_BUFG_REBUF_CK_BUFG_CASC24", - "CLK_BUFG_REBUF_CK_BUFG_CASC25", - "CLK_BUFG_REBUF_CK_BUFG_CASC26", - "CLK_BUFG_REBUF_CK_BUFG_CASC27", - "CLK_BUFG_REBUF_CK_BUFG_CASC28", - "CLK_BUFG_REBUF_CK_BUFG_CASC29", - "CLK_BUFG_REBUF_CK_BUFG_CASC3", - "CLK_BUFG_REBUF_CK_BUFG_CASC30", - "CLK_BUFG_REBUF_CK_BUFG_CASC31", - "CLK_BUFG_REBUF_CK_BUFG_CASC4", - "CLK_BUFG_REBUF_CK_BUFG_CASC5", - "CLK_BUFG_REBUF_CK_BUFG_CASC6", - "CLK_BUFG_REBUF_CK_BUFG_CASC7", - "CLK_BUFG_REBUF_CK_BUFG_CASC8", - "CLK_BUFG_REBUF_CK_BUFG_CASC9", - "CLK_BUFG_REBUF_CK_GCLK0_BOT", - "CLK_BUFG_REBUF_CK_GCLK0_TOP", - "CLK_BUFG_REBUF_CK_GCLK10_BOT", - "CLK_BUFG_REBUF_CK_GCLK10_TOP", - "CLK_BUFG_REBUF_CK_GCLK11_BOT", - "CLK_BUFG_REBUF_CK_GCLK11_TOP", - "CLK_BUFG_REBUF_CK_GCLK12_BOT", - "CLK_BUFG_REBUF_CK_GCLK12_TOP", - "CLK_BUFG_REBUF_CK_GCLK13_BOT", - "CLK_BUFG_REBUF_CK_GCLK13_TOP", - "CLK_BUFG_REBUF_CK_GCLK14_BOT", - "CLK_BUFG_REBUF_CK_GCLK14_TOP", - "CLK_BUFG_REBUF_CK_GCLK15_BOT", - "CLK_BUFG_REBUF_CK_GCLK15_TOP", - "CLK_BUFG_REBUF_CK_GCLK16_BOT", - "CLK_BUFG_REBUF_CK_GCLK16_TOP", - "CLK_BUFG_REBUF_CK_GCLK17_BOT", - "CLK_BUFG_REBUF_CK_GCLK17_TOP", - "CLK_BUFG_REBUF_CK_GCLK18_BOT", - "CLK_BUFG_REBUF_CK_GCLK18_TOP", - "CLK_BUFG_REBUF_CK_GCLK19_BOT", - "CLK_BUFG_REBUF_CK_GCLK19_TOP", - "CLK_BUFG_REBUF_CK_GCLK1_BOT", - "CLK_BUFG_REBUF_CK_GCLK1_TOP", - "CLK_BUFG_REBUF_CK_GCLK20_BOT", - "CLK_BUFG_REBUF_CK_GCLK20_TOP", - "CLK_BUFG_REBUF_CK_GCLK21_BOT", - "CLK_BUFG_REBUF_CK_GCLK21_TOP", - "CLK_BUFG_REBUF_CK_GCLK22_BOT", - "CLK_BUFG_REBUF_CK_GCLK22_TOP", - "CLK_BUFG_REBUF_CK_GCLK23_BOT", - "CLK_BUFG_REBUF_CK_GCLK23_TOP", - "CLK_BUFG_REBUF_CK_GCLK24_BOT", - "CLK_BUFG_REBUF_CK_GCLK24_TOP", - "CLK_BUFG_REBUF_CK_GCLK25_BOT", - "CLK_BUFG_REBUF_CK_GCLK25_TOP", - "CLK_BUFG_REBUF_CK_GCLK26_BOT", - "CLK_BUFG_REBUF_CK_GCLK26_TOP", - "CLK_BUFG_REBUF_CK_GCLK27_BOT", - "CLK_BUFG_REBUF_CK_GCLK27_TOP", - "CLK_BUFG_REBUF_CK_GCLK28_BOT", - "CLK_BUFG_REBUF_CK_GCLK28_TOP", - "CLK_BUFG_REBUF_CK_GCLK29_BOT", - "CLK_BUFG_REBUF_CK_GCLK29_TOP", - "CLK_BUFG_REBUF_CK_GCLK2_BOT", - "CLK_BUFG_REBUF_CK_GCLK2_TOP", - "CLK_BUFG_REBUF_CK_GCLK30_BOT", - "CLK_BUFG_REBUF_CK_GCLK30_TOP", - "CLK_BUFG_REBUF_CK_GCLK31_BOT", - "CLK_BUFG_REBUF_CK_GCLK31_TOP", - "CLK_BUFG_REBUF_CK_GCLK3_BOT", - "CLK_BUFG_REBUF_CK_GCLK3_TOP", - "CLK_BUFG_REBUF_CK_GCLK4_BOT", - "CLK_BUFG_REBUF_CK_GCLK4_TOP", - "CLK_BUFG_REBUF_CK_GCLK5_BOT", - "CLK_BUFG_REBUF_CK_GCLK5_TOP", - "CLK_BUFG_REBUF_CK_GCLK6_BOT", - "CLK_BUFG_REBUF_CK_GCLK6_TOP", - "CLK_BUFG_REBUF_CK_GCLK7_BOT", - "CLK_BUFG_REBUF_CK_GCLK7_TOP", - "CLK_BUFG_REBUF_CK_GCLK8_BOT", - "CLK_BUFG_REBUF_CK_GCLK8_TOP", - "CLK_BUFG_REBUF_CK_GCLK9_BOT", - "CLK_BUFG_REBUF_CK_GCLK9_TOP", - "CLK_BUFG_REBUF_EE2A0_0", - "CLK_BUFG_REBUF_EE2A0_1", - "CLK_BUFG_REBUF_EE2A1_0", - "CLK_BUFG_REBUF_EE2A1_1", - "CLK_BUFG_REBUF_EE2A2_0", - "CLK_BUFG_REBUF_EE2A2_1", - "CLK_BUFG_REBUF_EE2A3_0", - "CLK_BUFG_REBUF_EE2A3_1", - "CLK_BUFG_REBUF_EE2BEG0_0", - "CLK_BUFG_REBUF_EE2BEG0_1", - "CLK_BUFG_REBUF_EE2BEG1_0", - "CLK_BUFG_REBUF_EE2BEG1_1", - "CLK_BUFG_REBUF_EE2BEG2_0", - "CLK_BUFG_REBUF_EE2BEG2_1", - "CLK_BUFG_REBUF_EE2BEG3_0", - "CLK_BUFG_REBUF_EE2BEG3_1", - "CLK_BUFG_REBUF_EE4A0_0", - "CLK_BUFG_REBUF_EE4A0_1", - "CLK_BUFG_REBUF_EE4A1_0", - "CLK_BUFG_REBUF_EE4A1_1", - "CLK_BUFG_REBUF_EE4A2_0", - "CLK_BUFG_REBUF_EE4A2_1", - "CLK_BUFG_REBUF_EE4A3_0", - "CLK_BUFG_REBUF_EE4A3_1", - "CLK_BUFG_REBUF_EE4B0_0", - "CLK_BUFG_REBUF_EE4B0_1", - "CLK_BUFG_REBUF_EE4B1_0", - "CLK_BUFG_REBUF_EE4B1_1", - "CLK_BUFG_REBUF_EE4B2_0", - "CLK_BUFG_REBUF_EE4B2_1", - "CLK_BUFG_REBUF_EE4B3_0", - "CLK_BUFG_REBUF_EE4B3_1", - "CLK_BUFG_REBUF_EE4BEG0_0", - "CLK_BUFG_REBUF_EE4BEG0_1", - "CLK_BUFG_REBUF_EE4BEG1_0", - "CLK_BUFG_REBUF_EE4BEG1_1", - "CLK_BUFG_REBUF_EE4BEG2_0", - "CLK_BUFG_REBUF_EE4BEG2_1", - "CLK_BUFG_REBUF_EE4BEG3_0", - "CLK_BUFG_REBUF_EE4BEG3_1", - "CLK_BUFG_REBUF_EE4C0_0", - "CLK_BUFG_REBUF_EE4C0_1", - "CLK_BUFG_REBUF_EE4C1_0", - "CLK_BUFG_REBUF_EE4C1_1", - "CLK_BUFG_REBUF_EE4C2_0", - "CLK_BUFG_REBUF_EE4C2_1", - "CLK_BUFG_REBUF_EE4C3_0", - "CLK_BUFG_REBUF_EE4C3_1", - "CLK_BUFG_REBUF_EL1BEG0_0", - "CLK_BUFG_REBUF_EL1BEG0_1", - "CLK_BUFG_REBUF_EL1BEG1_0", - "CLK_BUFG_REBUF_EL1BEG1_1", - "CLK_BUFG_REBUF_EL1BEG2_0", - "CLK_BUFG_REBUF_EL1BEG2_1", - "CLK_BUFG_REBUF_EL1BEG3_0", - "CLK_BUFG_REBUF_EL1BEG3_1", - "CLK_BUFG_REBUF_ER1BEG0_0", - "CLK_BUFG_REBUF_ER1BEG0_1", - "CLK_BUFG_REBUF_ER1BEG1_0", - "CLK_BUFG_REBUF_ER1BEG1_1", - "CLK_BUFG_REBUF_ER1BEG2_0", - "CLK_BUFG_REBUF_ER1BEG2_1", - "CLK_BUFG_REBUF_ER1BEG3_0", - "CLK_BUFG_REBUF_ER1BEG3_1", - "CLK_BUFG_REBUF_LH10_0", - "CLK_BUFG_REBUF_LH10_1", - "CLK_BUFG_REBUF_LH11_0", - "CLK_BUFG_REBUF_LH11_1", - "CLK_BUFG_REBUF_LH12_0", - "CLK_BUFG_REBUF_LH12_1", - "CLK_BUFG_REBUF_LH1_0", - "CLK_BUFG_REBUF_LH1_1", - "CLK_BUFG_REBUF_LH2_0", - "CLK_BUFG_REBUF_LH2_1", - "CLK_BUFG_REBUF_LH3_0", - "CLK_BUFG_REBUF_LH3_1", - "CLK_BUFG_REBUF_LH4_0", - "CLK_BUFG_REBUF_LH4_1", - "CLK_BUFG_REBUF_LH5_0", - "CLK_BUFG_REBUF_LH5_1", - "CLK_BUFG_REBUF_LH6_0", - "CLK_BUFG_REBUF_LH6_1", - "CLK_BUFG_REBUF_LH7_0", - "CLK_BUFG_REBUF_LH7_1", - "CLK_BUFG_REBUF_LH8_0", - "CLK_BUFG_REBUF_LH8_1", - "CLK_BUFG_REBUF_LH9_0", - "CLK_BUFG_REBUF_LH9_1", - "CLK_BUFG_REBUF_MONITOR_N_0", - "CLK_BUFG_REBUF_MONITOR_N_1", - "CLK_BUFG_REBUF_MONITOR_P_0", - "CLK_BUFG_REBUF_MONITOR_P_1", - "CLK_BUFG_REBUF_NE2A0_0", - "CLK_BUFG_REBUF_NE2A0_1", - "CLK_BUFG_REBUF_NE2A1_0", - "CLK_BUFG_REBUF_NE2A1_1", - "CLK_BUFG_REBUF_NE2A2_0", - "CLK_BUFG_REBUF_NE2A2_1", - "CLK_BUFG_REBUF_NE2A3_0", - "CLK_BUFG_REBUF_NE2A3_1", - "CLK_BUFG_REBUF_NE4BEG0_0", - "CLK_BUFG_REBUF_NE4BEG0_1", - "CLK_BUFG_REBUF_NE4BEG1_0", - "CLK_BUFG_REBUF_NE4BEG1_1", - "CLK_BUFG_REBUF_NE4BEG2_0", - "CLK_BUFG_REBUF_NE4BEG2_1", - "CLK_BUFG_REBUF_NE4BEG3_0", - "CLK_BUFG_REBUF_NE4BEG3_1", - "CLK_BUFG_REBUF_NE4C0_0", - "CLK_BUFG_REBUF_NE4C0_1", - "CLK_BUFG_REBUF_NE4C1_0", - "CLK_BUFG_REBUF_NE4C1_1", - "CLK_BUFG_REBUF_NE4C2_0", - "CLK_BUFG_REBUF_NE4C2_1", - "CLK_BUFG_REBUF_NE4C3_0", - "CLK_BUFG_REBUF_NE4C3_1", - "CLK_BUFG_REBUF_NW2A0_0", - "CLK_BUFG_REBUF_NW2A0_1", - "CLK_BUFG_REBUF_NW2A1_0", - "CLK_BUFG_REBUF_NW2A1_1", - "CLK_BUFG_REBUF_NW2A2_0", - "CLK_BUFG_REBUF_NW2A2_1", - "CLK_BUFG_REBUF_NW2A3_0", - "CLK_BUFG_REBUF_NW2A3_1", - "CLK_BUFG_REBUF_NW4A0_0", - "CLK_BUFG_REBUF_NW4A0_1", - "CLK_BUFG_REBUF_NW4A1_0", - "CLK_BUFG_REBUF_NW4A1_1", - "CLK_BUFG_REBUF_NW4A2_0", - "CLK_BUFG_REBUF_NW4A2_1", - "CLK_BUFG_REBUF_NW4A3_0", - "CLK_BUFG_REBUF_NW4A3_1", - "CLK_BUFG_REBUF_NW4END0_0", - "CLK_BUFG_REBUF_NW4END0_1", - "CLK_BUFG_REBUF_NW4END1_0", - "CLK_BUFG_REBUF_NW4END1_1", - "CLK_BUFG_REBUF_NW4END2_0", - "CLK_BUFG_REBUF_NW4END2_1", - "CLK_BUFG_REBUF_NW4END3_0", - "CLK_BUFG_REBUF_NW4END3_1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC0", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC1", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC10", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC11", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC12", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC13", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC14", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC15", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC16", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC17", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC18", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC19", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC2", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC20", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC21", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC22", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC23", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC24", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC25", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC26", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC27", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC28", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC29", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC3", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC30", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC31", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC4", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC5", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC6", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC7", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC8", - "CLK_BUFG_REBUF_R_CK_BUFG_CASC9", - "CLK_BUFG_REBUF_R_CK_GCLK0_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK0_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK10_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK10_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK11_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK11_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK12_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK12_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK13_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK13_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK14_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK14_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK15_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK15_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK16_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK16_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK17_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK17_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK18_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK18_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK19_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK19_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK1_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK1_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK20_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK20_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK21_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK21_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK22_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK22_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK23_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK23_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK24_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK24_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK25_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK25_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK26_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK26_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK27_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK27_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK28_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK28_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK29_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK29_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK2_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK2_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK30_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK30_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK31_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK31_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK3_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK3_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK4_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK4_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK5_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK5_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK6_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK6_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK7_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK7_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK8_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK8_TOP", - "CLK_BUFG_REBUF_R_CK_GCLK9_BOT", - "CLK_BUFG_REBUF_R_CK_GCLK9_TOP", - "CLK_BUFG_REBUF_SE2A0_0", - "CLK_BUFG_REBUF_SE2A0_1", - "CLK_BUFG_REBUF_SE2A1_0", - "CLK_BUFG_REBUF_SE2A1_1", - "CLK_BUFG_REBUF_SE2A2_0", - "CLK_BUFG_REBUF_SE2A2_1", - "CLK_BUFG_REBUF_SE2A3_0", - "CLK_BUFG_REBUF_SE2A3_1", - "CLK_BUFG_REBUF_SE4BEG0_0", - "CLK_BUFG_REBUF_SE4BEG0_1", - "CLK_BUFG_REBUF_SE4BEG1_0", - "CLK_BUFG_REBUF_SE4BEG1_1", - "CLK_BUFG_REBUF_SE4BEG2_0", - "CLK_BUFG_REBUF_SE4BEG2_1", - "CLK_BUFG_REBUF_SE4BEG3_0", - "CLK_BUFG_REBUF_SE4BEG3_1", - "CLK_BUFG_REBUF_SE4C0_0", - "CLK_BUFG_REBUF_SE4C0_1", - "CLK_BUFG_REBUF_SE4C1_0", - "CLK_BUFG_REBUF_SE4C1_1", - "CLK_BUFG_REBUF_SE4C2_0", - "CLK_BUFG_REBUF_SE4C2_1", - "CLK_BUFG_REBUF_SE4C3_0", - "CLK_BUFG_REBUF_SE4C3_1", - "CLK_BUFG_REBUF_SW2A0_0", - "CLK_BUFG_REBUF_SW2A0_1", - "CLK_BUFG_REBUF_SW2A1_0", - "CLK_BUFG_REBUF_SW2A1_1", - "CLK_BUFG_REBUF_SW2A2_0", - "CLK_BUFG_REBUF_SW2A2_1", - "CLK_BUFG_REBUF_SW2A3_0", - "CLK_BUFG_REBUF_SW2A3_1", - "CLK_BUFG_REBUF_SW4A0_0", - "CLK_BUFG_REBUF_SW4A0_1", - "CLK_BUFG_REBUF_SW4A1_0", - "CLK_BUFG_REBUF_SW4A1_1", - "CLK_BUFG_REBUF_SW4A2_0", - "CLK_BUFG_REBUF_SW4A2_1", - "CLK_BUFG_REBUF_SW4A3_0", - "CLK_BUFG_REBUF_SW4A3_1", - "CLK_BUFG_REBUF_SW4END0_0", - "CLK_BUFG_REBUF_SW4END0_1", - "CLK_BUFG_REBUF_SW4END1_0", - "CLK_BUFG_REBUF_SW4END1_1", - "CLK_BUFG_REBUF_SW4END2_0", - "CLK_BUFG_REBUF_SW4END2_1", - "CLK_BUFG_REBUF_SW4END3_0", - "CLK_BUFG_REBUF_SW4END3_1", - "CLK_BUFG_REBUF_WL1END0_0", - "CLK_BUFG_REBUF_WL1END0_1", - "CLK_BUFG_REBUF_WL1END1_0", - "CLK_BUFG_REBUF_WL1END1_1", - "CLK_BUFG_REBUF_WL1END2_0", - "CLK_BUFG_REBUF_WL1END2_1", - "CLK_BUFG_REBUF_WL1END3_0", - "CLK_BUFG_REBUF_WL1END3_1", - "CLK_BUFG_REBUF_WR1END0_0", - "CLK_BUFG_REBUF_WR1END0_1", - "CLK_BUFG_REBUF_WR1END1_0", - "CLK_BUFG_REBUF_WR1END1_1", - "CLK_BUFG_REBUF_WR1END2_0", - "CLK_BUFG_REBUF_WR1END2_1", - "CLK_BUFG_REBUF_WR1END3_0", - "CLK_BUFG_REBUF_WR1END3_1", - "CLK_BUFG_REBUF_WW2A0_0", - "CLK_BUFG_REBUF_WW2A0_1", - "CLK_BUFG_REBUF_WW2A1_0", - "CLK_BUFG_REBUF_WW2A1_1", - "CLK_BUFG_REBUF_WW2A2_0", - "CLK_BUFG_REBUF_WW2A2_1", - "CLK_BUFG_REBUF_WW2A3_0", - "CLK_BUFG_REBUF_WW2A3_1", - "CLK_BUFG_REBUF_WW2END0_0", - "CLK_BUFG_REBUF_WW2END0_1", - "CLK_BUFG_REBUF_WW2END1_0", - "CLK_BUFG_REBUF_WW2END1_1", - "CLK_BUFG_REBUF_WW2END2_0", - "CLK_BUFG_REBUF_WW2END2_1", - "CLK_BUFG_REBUF_WW2END3_0", - "CLK_BUFG_REBUF_WW2END3_1", - "CLK_BUFG_REBUF_WW4A0_0", - "CLK_BUFG_REBUF_WW4A0_1", - "CLK_BUFG_REBUF_WW4A1_0", - "CLK_BUFG_REBUF_WW4A1_1", - "CLK_BUFG_REBUF_WW4A2_0", - "CLK_BUFG_REBUF_WW4A2_1", - "CLK_BUFG_REBUF_WW4A3_0", - "CLK_BUFG_REBUF_WW4A3_1", - "CLK_BUFG_REBUF_WW4B0_0", - "CLK_BUFG_REBUF_WW4B0_1", - "CLK_BUFG_REBUF_WW4B1_0", - "CLK_BUFG_REBUF_WW4B1_1", - "CLK_BUFG_REBUF_WW4B2_0", - "CLK_BUFG_REBUF_WW4B2_1", - "CLK_BUFG_REBUF_WW4B3_0", - "CLK_BUFG_REBUF_WW4B3_1", - "CLK_BUFG_REBUF_WW4C0_0", - "CLK_BUFG_REBUF_WW4C0_1", - "CLK_BUFG_REBUF_WW4C1_0", - "CLK_BUFG_REBUF_WW4C1_1", - "CLK_BUFG_REBUF_WW4C2_0", - "CLK_BUFG_REBUF_WW4C2_1", - "CLK_BUFG_REBUF_WW4C3_0", - "CLK_BUFG_REBUF_WW4C3_1", - "CLK_BUFG_REBUF_WW4END0_0", - "CLK_BUFG_REBUF_WW4END0_1", - "CLK_BUFG_REBUF_WW4END1_0", - "CLK_BUFG_REBUF_WW4END1_1", - "CLK_BUFG_REBUF_WW4END2_0", - "CLK_BUFG_REBUF_WW4END2_1", - "CLK_BUFG_REBUF_WW4END3_0", - "CLK_BUFG_REBUF_WW4END3_1", - "GCLK0_1_DN_TEST_RING_IN", - "GCLK0_1_DN_TEST_RING_OUT", - "GCLK10_11_DN_TEST_RING_IN", - "GCLK10_11_DN_TEST_RING_OUT", - "GCLK11_10_UP_TEST_RING_IN", - "GCLK11_10_UP_TEST_RING_OUT", - "GCLK12_13_DN_TEST_RING_IN", - "GCLK12_13_DN_TEST_RING_OUT", - "GCLK13_12_UP_TEST_RING_IN", - "GCLK13_12_UP_TEST_RING_OUT", - "GCLK14_15_DN_TEST_RING_IN", - "GCLK14_15_DN_TEST_RING_OUT", - "GCLK15_14_UP_TEST_RING_IN", - "GCLK15_14_UP_TEST_RING_OUT", - "GCLK16_17_DN_TEST_RING_IN", - "GCLK16_17_DN_TEST_RING_OUT", - "GCLK17_16_UP_TEST_RING_IN", - "GCLK17_16_UP_TEST_RING_OUT", - "GCLK18_19_DN_TEST_RING_IN", - "GCLK18_19_DN_TEST_RING_OUT", - "GCLK19_18_UP_TEST_RING_IN", - "GCLK19_18_UP_TEST_RING_OUT", - "GCLK1_0_UP_TEST_RING_IN", - "GCLK1_0_UP_TEST_RING_OUT", - "GCLK20_21_DN_TEST_RING_IN", - "GCLK20_21_DN_TEST_RING_OUT", - "GCLK21_20_UP_TEST_RING_IN", - "GCLK21_20_UP_TEST_RING_OUT", - "GCLK22_23_DN_TEST_RING_IN", - "GCLK22_23_DN_TEST_RING_OUT", - "GCLK23_22_UP_TEST_RING_IN", - "GCLK23_22_UP_TEST_RING_OUT", - "GCLK24_25_DN_TEST_RING_IN", - "GCLK24_25_DN_TEST_RING_OUT", - "GCLK25_24_UP_TEST_RING_IN", - "GCLK25_24_UP_TEST_RING_OUT", - "GCLK26_27_DN_TEST_RING_IN", - "GCLK26_27_DN_TEST_RING_OUT", - "GCLK27_26_UP_TEST_RING_IN", - "GCLK27_26_UP_TEST_RING_OUT", - "GCLK28_29_DN_TEST_RING_IN", - "GCLK28_29_DN_TEST_RING_OUT", - "GCLK29_28_UP_TEST_RING_IN", - "GCLK29_28_UP_TEST_RING_OUT", - "GCLK2_3_DN_TEST_RING_IN", - "GCLK2_3_DN_TEST_RING_OUT", - "GCLK30_31_DN_TEST_RING_IN", - "GCLK30_31_DN_TEST_RING_OUT", - "GCLK31_30_UP_TEST_RING_IN", - "GCLK31_30_UP_TEST_RING_OUT", - "GCLK3_2_UP_TEST_RING_IN", - "GCLK3_2_UP_TEST_RING_OUT", - "GCLK4_5_DN_TEST_RING_IN", - "GCLK4_5_DN_TEST_RING_OUT", - "GCLK5_4_UP_TEST_RING_IN", - "GCLK5_4_UP_TEST_RING_OUT", - "GCLK6_7_DN_TEST_RING_IN", - "GCLK6_7_DN_TEST_RING_OUT", - "GCLK7_6_UP_TEST_RING_IN", - "GCLK7_6_UP_TEST_RING_OUT", - "GCLK8_9_DN_TEST_RING_IN", - "GCLK8_9_DN_TEST_RING_OUT", - "GCLK9_8_UP_TEST_RING_IN", - "GCLK9_8_UP_TEST_RING_OUT" - ] + "wires": { + "CLK_BUFG_REBUF_CK_BUFG_CASC0": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC1": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC10": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC11": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC12": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC13": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC14": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC15": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC16": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC17": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC18": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC19": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC2": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC20": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC21": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC22": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC23": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC24": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC25": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC26": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC27": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC28": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC29": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC3": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC30": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC31": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC4": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC5": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC6": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC7": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC8": null, + "CLK_BUFG_REBUF_CK_BUFG_CASC9": null, + "CLK_BUFG_REBUF_CK_GCLK0_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK0_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK10_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK10_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK11_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK11_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK12_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK12_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK13_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK13_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK14_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK14_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK15_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK15_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK16_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK16_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK17_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK17_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK18_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK18_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK19_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK19_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK1_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK1_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK20_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK20_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK21_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK21_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK22_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK22_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK23_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK23_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK24_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK24_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK25_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK25_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK26_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK26_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK27_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK27_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK28_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK28_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK29_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK29_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK2_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK2_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK30_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK30_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK31_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK31_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK3_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK3_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK4_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK4_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK5_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK5_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK6_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK6_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK7_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK7_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK8_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK8_TOP": null, + "CLK_BUFG_REBUF_CK_GCLK9_BOT": null, + "CLK_BUFG_REBUF_CK_GCLK9_TOP": null, + "CLK_BUFG_REBUF_EE2A0_0": null, + "CLK_BUFG_REBUF_EE2A0_1": null, + "CLK_BUFG_REBUF_EE2A1_0": null, + "CLK_BUFG_REBUF_EE2A1_1": null, + "CLK_BUFG_REBUF_EE2A2_0": null, + "CLK_BUFG_REBUF_EE2A2_1": null, + "CLK_BUFG_REBUF_EE2A3_0": null, + "CLK_BUFG_REBUF_EE2A3_1": null, + "CLK_BUFG_REBUF_EE2BEG0_0": null, + "CLK_BUFG_REBUF_EE2BEG0_1": null, + "CLK_BUFG_REBUF_EE2BEG1_0": null, + "CLK_BUFG_REBUF_EE2BEG1_1": null, + "CLK_BUFG_REBUF_EE2BEG2_0": null, + "CLK_BUFG_REBUF_EE2BEG2_1": null, + "CLK_BUFG_REBUF_EE2BEG3_0": null, + "CLK_BUFG_REBUF_EE2BEG3_1": null, + "CLK_BUFG_REBUF_EE4A0_0": null, + "CLK_BUFG_REBUF_EE4A0_1": null, + "CLK_BUFG_REBUF_EE4A1_0": null, + "CLK_BUFG_REBUF_EE4A1_1": null, + "CLK_BUFG_REBUF_EE4A2_0": null, + "CLK_BUFG_REBUF_EE4A2_1": null, + "CLK_BUFG_REBUF_EE4A3_0": null, + "CLK_BUFG_REBUF_EE4A3_1": null, + "CLK_BUFG_REBUF_EE4B0_0": null, + "CLK_BUFG_REBUF_EE4B0_1": null, + "CLK_BUFG_REBUF_EE4B1_0": null, + "CLK_BUFG_REBUF_EE4B1_1": null, + "CLK_BUFG_REBUF_EE4B2_0": null, + "CLK_BUFG_REBUF_EE4B2_1": null, + "CLK_BUFG_REBUF_EE4B3_0": null, + "CLK_BUFG_REBUF_EE4B3_1": null, + "CLK_BUFG_REBUF_EE4BEG0_0": null, + "CLK_BUFG_REBUF_EE4BEG0_1": null, + "CLK_BUFG_REBUF_EE4BEG1_0": null, + "CLK_BUFG_REBUF_EE4BEG1_1": null, + "CLK_BUFG_REBUF_EE4BEG2_0": null, + "CLK_BUFG_REBUF_EE4BEG2_1": null, + "CLK_BUFG_REBUF_EE4BEG3_0": null, + "CLK_BUFG_REBUF_EE4BEG3_1": null, + "CLK_BUFG_REBUF_EE4C0_0": null, + "CLK_BUFG_REBUF_EE4C0_1": null, + "CLK_BUFG_REBUF_EE4C1_0": null, + "CLK_BUFG_REBUF_EE4C1_1": null, + "CLK_BUFG_REBUF_EE4C2_0": null, + "CLK_BUFG_REBUF_EE4C2_1": null, + "CLK_BUFG_REBUF_EE4C3_0": null, + "CLK_BUFG_REBUF_EE4C3_1": null, + "CLK_BUFG_REBUF_EL1BEG0_0": null, + "CLK_BUFG_REBUF_EL1BEG0_1": null, + "CLK_BUFG_REBUF_EL1BEG1_0": null, + "CLK_BUFG_REBUF_EL1BEG1_1": null, + "CLK_BUFG_REBUF_EL1BEG2_0": null, + "CLK_BUFG_REBUF_EL1BEG2_1": null, + "CLK_BUFG_REBUF_EL1BEG3_0": null, + "CLK_BUFG_REBUF_EL1BEG3_1": null, + "CLK_BUFG_REBUF_ER1BEG0_0": null, + "CLK_BUFG_REBUF_ER1BEG0_1": null, + "CLK_BUFG_REBUF_ER1BEG1_0": null, + "CLK_BUFG_REBUF_ER1BEG1_1": null, + "CLK_BUFG_REBUF_ER1BEG2_0": null, + "CLK_BUFG_REBUF_ER1BEG2_1": null, + "CLK_BUFG_REBUF_ER1BEG3_0": null, + "CLK_BUFG_REBUF_ER1BEG3_1": null, + "CLK_BUFG_REBUF_LH10_0": null, + "CLK_BUFG_REBUF_LH10_1": null, + "CLK_BUFG_REBUF_LH11_0": null, + "CLK_BUFG_REBUF_LH11_1": null, + "CLK_BUFG_REBUF_LH12_0": null, + "CLK_BUFG_REBUF_LH12_1": null, + "CLK_BUFG_REBUF_LH1_0": null, + "CLK_BUFG_REBUF_LH1_1": null, + "CLK_BUFG_REBUF_LH2_0": null, + "CLK_BUFG_REBUF_LH2_1": null, + "CLK_BUFG_REBUF_LH3_0": null, + "CLK_BUFG_REBUF_LH3_1": null, + "CLK_BUFG_REBUF_LH4_0": null, + "CLK_BUFG_REBUF_LH4_1": null, + "CLK_BUFG_REBUF_LH5_0": null, + "CLK_BUFG_REBUF_LH5_1": null, + "CLK_BUFG_REBUF_LH6_0": null, + "CLK_BUFG_REBUF_LH6_1": null, + "CLK_BUFG_REBUF_LH7_0": null, + "CLK_BUFG_REBUF_LH7_1": null, + "CLK_BUFG_REBUF_LH8_0": null, + "CLK_BUFG_REBUF_LH8_1": null, + "CLK_BUFG_REBUF_LH9_0": null, + "CLK_BUFG_REBUF_LH9_1": null, + "CLK_BUFG_REBUF_MONITOR_N_0": null, + "CLK_BUFG_REBUF_MONITOR_N_1": null, + "CLK_BUFG_REBUF_MONITOR_P_0": null, + "CLK_BUFG_REBUF_MONITOR_P_1": null, + "CLK_BUFG_REBUF_NE2A0_0": null, + "CLK_BUFG_REBUF_NE2A0_1": null, + "CLK_BUFG_REBUF_NE2A1_0": null, + "CLK_BUFG_REBUF_NE2A1_1": null, + "CLK_BUFG_REBUF_NE2A2_0": null, + "CLK_BUFG_REBUF_NE2A2_1": null, + "CLK_BUFG_REBUF_NE2A3_0": null, + "CLK_BUFG_REBUF_NE2A3_1": null, + "CLK_BUFG_REBUF_NE4BEG0_0": null, + "CLK_BUFG_REBUF_NE4BEG0_1": null, + "CLK_BUFG_REBUF_NE4BEG1_0": null, + "CLK_BUFG_REBUF_NE4BEG1_1": null, + "CLK_BUFG_REBUF_NE4BEG2_0": null, + "CLK_BUFG_REBUF_NE4BEG2_1": null, + "CLK_BUFG_REBUF_NE4BEG3_0": null, + "CLK_BUFG_REBUF_NE4BEG3_1": null, + "CLK_BUFG_REBUF_NE4C0_0": null, + "CLK_BUFG_REBUF_NE4C0_1": null, + "CLK_BUFG_REBUF_NE4C1_0": null, + "CLK_BUFG_REBUF_NE4C1_1": null, + "CLK_BUFG_REBUF_NE4C2_0": null, + "CLK_BUFG_REBUF_NE4C2_1": null, + "CLK_BUFG_REBUF_NE4C3_0": null, + "CLK_BUFG_REBUF_NE4C3_1": null, + "CLK_BUFG_REBUF_NW2A0_0": null, + "CLK_BUFG_REBUF_NW2A0_1": null, + "CLK_BUFG_REBUF_NW2A1_0": null, + "CLK_BUFG_REBUF_NW2A1_1": null, + "CLK_BUFG_REBUF_NW2A2_0": null, + "CLK_BUFG_REBUF_NW2A2_1": null, + "CLK_BUFG_REBUF_NW2A3_0": null, + "CLK_BUFG_REBUF_NW2A3_1": null, + "CLK_BUFG_REBUF_NW4A0_0": null, + "CLK_BUFG_REBUF_NW4A0_1": null, + "CLK_BUFG_REBUF_NW4A1_0": null, + "CLK_BUFG_REBUF_NW4A1_1": null, + "CLK_BUFG_REBUF_NW4A2_0": null, + "CLK_BUFG_REBUF_NW4A2_1": null, + "CLK_BUFG_REBUF_NW4A3_0": null, + "CLK_BUFG_REBUF_NW4A3_1": null, + "CLK_BUFG_REBUF_NW4END0_0": null, + "CLK_BUFG_REBUF_NW4END0_1": null, + "CLK_BUFG_REBUF_NW4END1_0": null, + "CLK_BUFG_REBUF_NW4END1_1": null, + "CLK_BUFG_REBUF_NW4END2_0": null, + "CLK_BUFG_REBUF_NW4END2_1": null, + "CLK_BUFG_REBUF_NW4END3_0": null, + "CLK_BUFG_REBUF_NW4END3_1": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC0": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC1": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC10": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC11": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC12": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC13": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC14": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC15": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC16": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC17": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC18": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC19": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC2": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC20": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC21": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC22": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC23": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC24": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC25": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC26": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC27": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC28": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC29": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC3": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC30": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC31": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC4": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC5": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC6": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC7": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC8": null, + "CLK_BUFG_REBUF_R_CK_BUFG_CASC9": null, + "CLK_BUFG_REBUF_R_CK_GCLK0_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK0_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK10_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK10_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK11_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK11_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK12_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK12_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK13_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK13_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK14_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK14_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK15_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK15_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK16_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK16_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK17_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK17_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK18_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK18_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK19_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK19_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK1_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK1_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK20_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK20_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK21_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK21_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK22_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK22_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK23_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK23_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK24_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK24_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK25_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK25_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK26_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK26_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK27_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK27_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK28_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK28_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK29_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK29_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK2_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK2_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK30_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK30_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK31_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK31_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK3_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK3_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK4_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK4_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK5_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK5_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK6_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK6_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK7_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK7_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK8_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK8_TOP": null, + "CLK_BUFG_REBUF_R_CK_GCLK9_BOT": null, + "CLK_BUFG_REBUF_R_CK_GCLK9_TOP": null, + "CLK_BUFG_REBUF_SE2A0_0": null, + "CLK_BUFG_REBUF_SE2A0_1": null, + "CLK_BUFG_REBUF_SE2A1_0": null, + "CLK_BUFG_REBUF_SE2A1_1": null, + "CLK_BUFG_REBUF_SE2A2_0": null, + "CLK_BUFG_REBUF_SE2A2_1": null, + "CLK_BUFG_REBUF_SE2A3_0": null, + "CLK_BUFG_REBUF_SE2A3_1": null, + "CLK_BUFG_REBUF_SE4BEG0_0": null, + "CLK_BUFG_REBUF_SE4BEG0_1": null, + "CLK_BUFG_REBUF_SE4BEG1_0": null, + "CLK_BUFG_REBUF_SE4BEG1_1": null, + "CLK_BUFG_REBUF_SE4BEG2_0": null, + "CLK_BUFG_REBUF_SE4BEG2_1": null, + "CLK_BUFG_REBUF_SE4BEG3_0": null, + "CLK_BUFG_REBUF_SE4BEG3_1": null, + "CLK_BUFG_REBUF_SE4C0_0": null, + "CLK_BUFG_REBUF_SE4C0_1": null, + "CLK_BUFG_REBUF_SE4C1_0": null, + "CLK_BUFG_REBUF_SE4C1_1": null, + "CLK_BUFG_REBUF_SE4C2_0": null, + "CLK_BUFG_REBUF_SE4C2_1": null, + "CLK_BUFG_REBUF_SE4C3_0": null, + "CLK_BUFG_REBUF_SE4C3_1": null, + "CLK_BUFG_REBUF_SW2A0_0": null, + "CLK_BUFG_REBUF_SW2A0_1": null, + "CLK_BUFG_REBUF_SW2A1_0": null, + "CLK_BUFG_REBUF_SW2A1_1": null, + "CLK_BUFG_REBUF_SW2A2_0": null, + "CLK_BUFG_REBUF_SW2A2_1": null, + "CLK_BUFG_REBUF_SW2A3_0": null, + "CLK_BUFG_REBUF_SW2A3_1": null, + "CLK_BUFG_REBUF_SW4A0_0": null, + "CLK_BUFG_REBUF_SW4A0_1": null, + "CLK_BUFG_REBUF_SW4A1_0": null, + "CLK_BUFG_REBUF_SW4A1_1": null, + "CLK_BUFG_REBUF_SW4A2_0": null, + "CLK_BUFG_REBUF_SW4A2_1": null, + "CLK_BUFG_REBUF_SW4A3_0": null, + "CLK_BUFG_REBUF_SW4A3_1": null, + "CLK_BUFG_REBUF_SW4END0_0": null, + "CLK_BUFG_REBUF_SW4END0_1": null, + "CLK_BUFG_REBUF_SW4END1_0": null, + "CLK_BUFG_REBUF_SW4END1_1": null, + "CLK_BUFG_REBUF_SW4END2_0": null, + "CLK_BUFG_REBUF_SW4END2_1": null, + "CLK_BUFG_REBUF_SW4END3_0": null, + "CLK_BUFG_REBUF_SW4END3_1": null, + "CLK_BUFG_REBUF_WL1END0_0": null, + "CLK_BUFG_REBUF_WL1END0_1": null, + "CLK_BUFG_REBUF_WL1END1_0": null, + "CLK_BUFG_REBUF_WL1END1_1": null, + "CLK_BUFG_REBUF_WL1END2_0": null, + "CLK_BUFG_REBUF_WL1END2_1": null, + "CLK_BUFG_REBUF_WL1END3_0": null, + "CLK_BUFG_REBUF_WL1END3_1": null, + "CLK_BUFG_REBUF_WR1END0_0": null, + "CLK_BUFG_REBUF_WR1END0_1": null, + "CLK_BUFG_REBUF_WR1END1_0": null, + "CLK_BUFG_REBUF_WR1END1_1": null, + "CLK_BUFG_REBUF_WR1END2_0": null, + "CLK_BUFG_REBUF_WR1END2_1": null, + "CLK_BUFG_REBUF_WR1END3_0": null, + "CLK_BUFG_REBUF_WR1END3_1": null, + "CLK_BUFG_REBUF_WW2A0_0": null, + "CLK_BUFG_REBUF_WW2A0_1": null, + "CLK_BUFG_REBUF_WW2A1_0": null, + "CLK_BUFG_REBUF_WW2A1_1": null, + "CLK_BUFG_REBUF_WW2A2_0": null, + "CLK_BUFG_REBUF_WW2A2_1": null, + "CLK_BUFG_REBUF_WW2A3_0": null, + "CLK_BUFG_REBUF_WW2A3_1": null, + "CLK_BUFG_REBUF_WW2END0_0": null, + "CLK_BUFG_REBUF_WW2END0_1": null, + "CLK_BUFG_REBUF_WW2END1_0": null, + "CLK_BUFG_REBUF_WW2END1_1": null, + "CLK_BUFG_REBUF_WW2END2_0": null, + "CLK_BUFG_REBUF_WW2END2_1": null, + "CLK_BUFG_REBUF_WW2END3_0": null, + "CLK_BUFG_REBUF_WW2END3_1": null, + "CLK_BUFG_REBUF_WW4A0_0": null, + "CLK_BUFG_REBUF_WW4A0_1": null, + "CLK_BUFG_REBUF_WW4A1_0": null, + "CLK_BUFG_REBUF_WW4A1_1": null, + "CLK_BUFG_REBUF_WW4A2_0": null, + "CLK_BUFG_REBUF_WW4A2_1": null, + "CLK_BUFG_REBUF_WW4A3_0": null, + "CLK_BUFG_REBUF_WW4A3_1": null, + "CLK_BUFG_REBUF_WW4B0_0": null, + "CLK_BUFG_REBUF_WW4B0_1": null, + "CLK_BUFG_REBUF_WW4B1_0": null, + "CLK_BUFG_REBUF_WW4B1_1": null, + "CLK_BUFG_REBUF_WW4B2_0": null, + "CLK_BUFG_REBUF_WW4B2_1": null, + "CLK_BUFG_REBUF_WW4B3_0": null, + "CLK_BUFG_REBUF_WW4B3_1": null, + "CLK_BUFG_REBUF_WW4C0_0": null, + "CLK_BUFG_REBUF_WW4C0_1": null, + "CLK_BUFG_REBUF_WW4C1_0": null, + "CLK_BUFG_REBUF_WW4C1_1": null, + "CLK_BUFG_REBUF_WW4C2_0": null, + "CLK_BUFG_REBUF_WW4C2_1": null, + "CLK_BUFG_REBUF_WW4C3_0": null, + "CLK_BUFG_REBUF_WW4C3_1": null, + "CLK_BUFG_REBUF_WW4END0_0": null, + "CLK_BUFG_REBUF_WW4END0_1": null, + "CLK_BUFG_REBUF_WW4END1_0": null, + "CLK_BUFG_REBUF_WW4END1_1": null, + "CLK_BUFG_REBUF_WW4END2_0": null, + "CLK_BUFG_REBUF_WW4END2_1": null, + "CLK_BUFG_REBUF_WW4END3_0": null, + "CLK_BUFG_REBUF_WW4END3_1": null, + "GCLK0_1_DN_TEST_RING_IN": null, + "GCLK0_1_DN_TEST_RING_OUT": null, + "GCLK10_11_DN_TEST_RING_IN": null, + "GCLK10_11_DN_TEST_RING_OUT": null, + "GCLK11_10_UP_TEST_RING_IN": null, + "GCLK11_10_UP_TEST_RING_OUT": null, + "GCLK12_13_DN_TEST_RING_IN": null, + "GCLK12_13_DN_TEST_RING_OUT": null, + "GCLK13_12_UP_TEST_RING_IN": null, + "GCLK13_12_UP_TEST_RING_OUT": null, + "GCLK14_15_DN_TEST_RING_IN": null, + "GCLK14_15_DN_TEST_RING_OUT": null, + "GCLK15_14_UP_TEST_RING_IN": null, + "GCLK15_14_UP_TEST_RING_OUT": null, + "GCLK16_17_DN_TEST_RING_IN": null, + "GCLK16_17_DN_TEST_RING_OUT": null, + "GCLK17_16_UP_TEST_RING_IN": null, + "GCLK17_16_UP_TEST_RING_OUT": null, + "GCLK18_19_DN_TEST_RING_IN": null, + "GCLK18_19_DN_TEST_RING_OUT": null, + "GCLK19_18_UP_TEST_RING_IN": null, + "GCLK19_18_UP_TEST_RING_OUT": null, + "GCLK1_0_UP_TEST_RING_IN": null, + "GCLK1_0_UP_TEST_RING_OUT": null, + "GCLK20_21_DN_TEST_RING_IN": null, + "GCLK20_21_DN_TEST_RING_OUT": null, + "GCLK21_20_UP_TEST_RING_IN": null, + "GCLK21_20_UP_TEST_RING_OUT": null, + "GCLK22_23_DN_TEST_RING_IN": null, + "GCLK22_23_DN_TEST_RING_OUT": null, + "GCLK23_22_UP_TEST_RING_IN": null, + "GCLK23_22_UP_TEST_RING_OUT": null, + "GCLK24_25_DN_TEST_RING_IN": null, + "GCLK24_25_DN_TEST_RING_OUT": null, + "GCLK25_24_UP_TEST_RING_IN": null, + "GCLK25_24_UP_TEST_RING_OUT": null, + "GCLK26_27_DN_TEST_RING_IN": null, + "GCLK26_27_DN_TEST_RING_OUT": null, + "GCLK27_26_UP_TEST_RING_IN": null, + "GCLK27_26_UP_TEST_RING_OUT": null, + "GCLK28_29_DN_TEST_RING_IN": null, + "GCLK28_29_DN_TEST_RING_OUT": null, + "GCLK29_28_UP_TEST_RING_IN": null, + "GCLK29_28_UP_TEST_RING_OUT": null, + "GCLK2_3_DN_TEST_RING_IN": null, + "GCLK2_3_DN_TEST_RING_OUT": null, + "GCLK30_31_DN_TEST_RING_IN": null, + "GCLK30_31_DN_TEST_RING_OUT": null, + "GCLK31_30_UP_TEST_RING_IN": null, + "GCLK31_30_UP_TEST_RING_OUT": null, + "GCLK3_2_UP_TEST_RING_IN": null, + "GCLK3_2_UP_TEST_RING_OUT": null, + "GCLK4_5_DN_TEST_RING_IN": null, + "GCLK4_5_DN_TEST_RING_OUT": null, + "GCLK5_4_UP_TEST_RING_IN": null, + "GCLK5_4_UP_TEST_RING_OUT": null, + "GCLK6_7_DN_TEST_RING_IN": null, + "GCLK6_7_DN_TEST_RING_OUT": null, + "GCLK7_6_UP_TEST_RING_IN": null, + "GCLK7_6_UP_TEST_RING_OUT": null, + "GCLK8_9_DN_TEST_RING_IN": null, + "GCLK8_9_DN_TEST_RING_OUT": null, + "GCLK9_8_UP_TEST_RING_IN": null, + "GCLK9_8_UP_TEST_RING_OUT": null + } } diff --git a/kintex7/tile_type_CLK_BUFG_TOP_R.json b/kintex7/tile_type_CLK_BUFG_TOP_R.json index c2f91e8..2882075 100644 --- a/kintex7/tile_type_CLK_BUFG_TOP_R.json +++ b/kintex7/tile_type_CLK_BUFG_TOP_R.json @@ -2,2130 +2,8514 @@ "pips": { "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_I0->>CLK_BUFG_BUFGCTRL0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL0_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_CK_GCLK16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL0_O->>CLK_BUFG_R_FBG_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL0_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_I0->>CLK_BUFG_BUFGCTRL10_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL10_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_CK_GCLK26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL10_O->>CLK_BUFG_R_FBG_OUT10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL10_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_I0->>CLK_BUFG_BUFGCTRL11_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL11_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_CK_GCLK27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL11_O->>CLK_BUFG_R_FBG_OUT11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL11_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_I0->>CLK_BUFG_BUFGCTRL12_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL12_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_CK_GCLK28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL12_O->>CLK_BUFG_R_FBG_OUT12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL12_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_I0->>CLK_BUFG_BUFGCTRL13_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL13_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_CK_GCLK29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL13_O->>CLK_BUFG_R_FBG_OUT13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL13_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_I0->>CLK_BUFG_BUFGCTRL14_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL14_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_CK_GCLK30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL14_O->>CLK_BUFG_R_FBG_OUT14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL14_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_I0->>CLK_BUFG_BUFGCTRL15_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL15_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_CK_GCLK31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL15_O->>CLK_BUFG_R_FBG_OUT15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL15_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_I0->>CLK_BUFG_BUFGCTRL1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL1_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_CK_GCLK17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL1_O->>CLK_BUFG_R_FBG_OUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL1_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_I0->>CLK_BUFG_BUFGCTRL2_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL2_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_CK_GCLK18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL2_O->>CLK_BUFG_R_FBG_OUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL2_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_I0->>CLK_BUFG_BUFGCTRL3_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL3_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_CK_GCLK19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL3_O->>CLK_BUFG_R_FBG_OUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL3_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_I0->>CLK_BUFG_BUFGCTRL4_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL4_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_CK_GCLK20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL4_O->>CLK_BUFG_R_FBG_OUT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL4_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_I0->>CLK_BUFG_BUFGCTRL5_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL5_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_CK_GCLK21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL5_O->>CLK_BUFG_R_FBG_OUT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL5_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_I0->>CLK_BUFG_BUFGCTRL6_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL6_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_CK_GCLK22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL6_O->>CLK_BUFG_R_FBG_OUT6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL6_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_I0->>CLK_BUFG_BUFGCTRL7_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL7_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_CK_GCLK23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL7_O->>CLK_BUFG_R_FBG_OUT7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL7_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_I0->>CLK_BUFG_BUFGCTRL8_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL8_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_CK_GCLK24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL8_O->>CLK_BUFG_R_FBG_OUT8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL8_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_I0->>CLK_BUFG_BUFGCTRL9_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.026", + "0.030", + "0.083", + "0.093" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL9_I0" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_CK_GCLK25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_BUFG_CK_GCLK25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_BUFGCTRL9_O->>CLK_BUFG_R_FBG_OUT9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_FBG_OUT9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_BUFGCTRL9_O" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_0->>CLK_BUFG_R_BUFGCTRL0_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_1->>CLK_BUFG_R_BUFGCTRL4_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_2->>CLK_BUFG_R_BUFGCTRL8_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX0_3->>CLK_BUFG_R_BUFGCTRL12_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX0_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX10_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX10_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX11_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX11_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX12_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX12_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX13_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX13_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_0->>CLK_BUFG_R_BUFGCTRL2_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_1->>CLK_BUFG_R_BUFGCTRL6_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_2->>CLK_BUFG_R_BUFGCTRL10_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX14_3->>CLK_BUFG_R_BUFGCTRL14_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX14_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_0->>CLK_BUFG_R_BUFGCTRL3_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_1->>CLK_BUFG_R_BUFGCTRL7_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_2->>CLK_BUFG_R_BUFGCTRL11_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX15_3->>CLK_BUFG_R_BUFGCTRL15_IGNORE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX15_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_0->>CLK_BUFG_R_BUFGCTRL0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_1->>CLK_BUFG_R_BUFGCTRL4_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_2->>CLK_BUFG_R_BUFGCTRL8_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX16_3->>CLK_BUFG_R_BUFGCTRL12_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX16_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_0->>CLK_BUFG_R_BUFGCTRL1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_1->>CLK_BUFG_R_BUFGCTRL5_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_2->>CLK_BUFG_R_BUFGCTRL9_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX17_3->>CLK_BUFG_R_BUFGCTRL13_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX17_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_0->>CLK_BUFG_R_BUFGCTRL2_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_1->>CLK_BUFG_R_BUFGCTRL6_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_2->>CLK_BUFG_R_BUFGCTRL10_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX18_3->>CLK_BUFG_R_BUFGCTRL14_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX18_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_0->>CLK_BUFG_R_BUFGCTRL3_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_1->>CLK_BUFG_R_BUFGCTRL7_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_2->>CLK_BUFG_R_BUFGCTRL11_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX19_3->>CLK_BUFG_R_BUFGCTRL15_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX19_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_0->>CLK_BUFG_R_BUFGCTRL1_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_1->>CLK_BUFG_R_BUFGCTRL5_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_2->>CLK_BUFG_R_BUFGCTRL9_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX1_3->>CLK_BUFG_R_BUFGCTRL13_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX1_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_0->>CLK_BUFG_R_BUFGCTRL0_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_1->>CLK_BUFG_R_BUFGCTRL4_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_2->>CLK_BUFG_R_BUFGCTRL8_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX20_3->>CLK_BUFG_R_BUFGCTRL12_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX20_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_0->>CLK_BUFG_R_BUFGCTRL1_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_1->>CLK_BUFG_R_BUFGCTRL5_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_2->>CLK_BUFG_R_BUFGCTRL9_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX21_3->>CLK_BUFG_R_BUFGCTRL13_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX21_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_0->>CLK_BUFG_R_BUFGCTRL2_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_1->>CLK_BUFG_R_BUFGCTRL6_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_2->>CLK_BUFG_R_BUFGCTRL10_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX22_3->>CLK_BUFG_R_BUFGCTRL14_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX22_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_0->>CLK_BUFG_R_BUFGCTRL3_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_1->>CLK_BUFG_R_BUFGCTRL7_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_2->>CLK_BUFG_R_BUFGCTRL11_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX23_3->>CLK_BUFG_R_BUFGCTRL15_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_CE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX23_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_2->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX24_3->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX24_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_1->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_2->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX25_3->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX25_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX26_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX26_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_0->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX27_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX27_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_0->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_1->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_2->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX28_3->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX28_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_1->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_2->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX29_3->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX29_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_0->>CLK_BUFG_R_BUFGCTRL2_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_1->>CLK_BUFG_R_BUFGCTRL6_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_2->>CLK_BUFG_R_BUFGCTRL10_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX2_3->>CLK_BUFG_R_BUFGCTRL14_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX2_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_0->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_1->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_2->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX30_3->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX30_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_0->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_1->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_2->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX31_3->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.078", + "0.089", + "0.201", + "0.224" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX31_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_0->>CLK_BUFG_R_BUFGCTRL3_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_1->>CLK_BUFG_R_BUFGCTRL7_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_2->>CLK_BUFG_R_BUFGCTRL11_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX3_3->>CLK_BUFG_R_BUFGCTRL15_S1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX3_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_0->>CLK_BUFG_R_BUFGCTRL0_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_1->>CLK_BUFG_R_BUFGCTRL4_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_2->>CLK_BUFG_R_BUFGCTRL8_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX4_3->>CLK_BUFG_R_BUFGCTRL12_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX4_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_0->>CLK_BUFG_R_BUFGCTRL1_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_1->>CLK_BUFG_R_BUFGCTRL5_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_2->>CLK_BUFG_R_BUFGCTRL9_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX5_3->>CLK_BUFG_R_BUFGCTRL13_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX5_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_0->>CLK_BUFG_R_BUFGCTRL2_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL2_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_1->>CLK_BUFG_R_BUFGCTRL6_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL6_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_2->>CLK_BUFG_R_BUFGCTRL10_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL10_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX6_3->>CLK_BUFG_R_BUFGCTRL14_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL14_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX6_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_0->>CLK_BUFG_R_BUFGCTRL3_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL3_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_1->>CLK_BUFG_R_BUFGCTRL7_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL7_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_2->>CLK_BUFG_R_BUFGCTRL11_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL11_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX7_3->>CLK_BUFG_R_BUFGCTRL15_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL15_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX7_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_0->>CLK_BUFG_R_BUFGCTRL0_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_1->>CLK_BUFG_R_BUFGCTRL4_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_2->>CLK_BUFG_R_BUFGCTRL8_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX8_3->>CLK_BUFG_R_BUFGCTRL12_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX8_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_0->>CLK_BUFG_R_BUFGCTRL1_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_0" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_1->>CLK_BUFG_R_BUFGCTRL5_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_1" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_2->>CLK_BUFG_R_BUFGCTRL9_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_2" }, "CLK_BUFG_TOP_R.CLK_BUFG_IMUX9_3->>CLK_BUFG_R_BUFGCTRL13_IGNORE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.025", + "0.028", + "0.064", + "0.071" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_IMUX9_3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT0->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT0" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT1->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT1" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT10->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT10" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT11->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT11" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT12->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT12" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT13->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT13" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT14->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT14" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.048", + "0.055", + "0.134", + "0.149" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT15->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT15" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT2->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT2" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT3->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT3" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT4->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT4" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT5->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT5" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT6->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT6" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT7->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT7" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT8->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT8" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_TOP_R.CLK_BUFG_R_FBG_OUT9->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.039", + "0.119", + "0.132" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_R_FBG_OUT9" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED0->>CLK_BUFG_BUFGCTRL0_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED0" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED1->>CLK_BUFG_BUFGCTRL0_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL0_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED1" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED10->>CLK_BUFG_BUFGCTRL5_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED10" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED11->>CLK_BUFG_BUFGCTRL5_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL5_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED11" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED12->>CLK_BUFG_BUFGCTRL6_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED12" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED13->>CLK_BUFG_BUFGCTRL6_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL6_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED13" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED14->>CLK_BUFG_BUFGCTRL7_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED14" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED15->>CLK_BUFG_BUFGCTRL7_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL7_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED15" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED16->>CLK_BUFG_BUFGCTRL8_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED16" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED17->>CLK_BUFG_BUFGCTRL8_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL8_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED17" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED18->>CLK_BUFG_BUFGCTRL9_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED18" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED19->>CLK_BUFG_BUFGCTRL9_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL9_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED19" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED2->>CLK_BUFG_BUFGCTRL1_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED2" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED20->>CLK_BUFG_BUFGCTRL10_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED20" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED21->>CLK_BUFG_BUFGCTRL10_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL10_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED21" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED22->>CLK_BUFG_BUFGCTRL11_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED22" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED23->>CLK_BUFG_BUFGCTRL11_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL11_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED23" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED24->>CLK_BUFG_BUFGCTRL12_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED24" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED25->>CLK_BUFG_BUFGCTRL12_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL12_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED25" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED26->>CLK_BUFG_BUFGCTRL13_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED26" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED27->>CLK_BUFG_BUFGCTRL13_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL13_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED27" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED28->>CLK_BUFG_BUFGCTRL14_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED28" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED29->>CLK_BUFG_BUFGCTRL14_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL14_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED29" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED3->>CLK_BUFG_BUFGCTRL1_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL1_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED3" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED30->>CLK_BUFG_BUFGCTRL15_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED30" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED31->>CLK_BUFG_BUFGCTRL15_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL15_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED31" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED4->>CLK_BUFG_BUFGCTRL2_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED4" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED5->>CLK_BUFG_BUFGCTRL2_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL2_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED5" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED6->>CLK_BUFG_BUFGCTRL3_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED6" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED7->>CLK_BUFG_BUFGCTRL3_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL3_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED7" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED8->>CLK_BUFG_BUFGCTRL4_I0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED8" }, "CLK_BUFG_TOP_R.CLK_BUFG_TOP_R_CK_MUXED9->>CLK_BUFG_BUFGCTRL4_I1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_BUFG_BUFGCTRL4_I1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.083", + "0.094", + "0.171", + "0.191" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_BUFG_TOP_R_CK_MUXED9" } }, @@ -2134,15 +8518,96 @@ "name": "X0Y0", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL0_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL0_CE1", - "I0": "CLK_BUFG_BUFGCTRL0_I0", - "I1": "CLK_BUFG_BUFGCTRL0_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL0_O", - "S0": "CLK_BUFG_R_BUFGCTRL0_S0", - "S1": "CLK_BUFG_R_BUFGCTRL0_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL0_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL0_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL0_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL0_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2152,15 +8617,96 @@ "name": "X0Y1", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL1_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL1_CE1", - "I0": "CLK_BUFG_BUFGCTRL1_I0", - "I1": "CLK_BUFG_BUFGCTRL1_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL1_O", - "S0": "CLK_BUFG_R_BUFGCTRL1_S0", - "S1": "CLK_BUFG_R_BUFGCTRL1_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL1_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL1_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL1_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL1_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2170,15 +8716,96 @@ "name": "X0Y2", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL2_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL2_CE1", - "I0": "CLK_BUFG_BUFGCTRL2_I0", - "I1": "CLK_BUFG_BUFGCTRL2_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL2_O", - "S0": "CLK_BUFG_R_BUFGCTRL2_S0", - "S1": "CLK_BUFG_R_BUFGCTRL2_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL2_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL2_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL2_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL2_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2188,15 +8815,96 @@ "name": "X0Y3", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL3_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL3_CE1", - "I0": "CLK_BUFG_BUFGCTRL3_I0", - "I1": "CLK_BUFG_BUFGCTRL3_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL3_O", - "S0": "CLK_BUFG_R_BUFGCTRL3_S0", - "S1": "CLK_BUFG_R_BUFGCTRL3_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL3_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL3_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL3_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL3_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2206,15 +8914,96 @@ "name": "X0Y4", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL4_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL4_CE1", - "I0": "CLK_BUFG_BUFGCTRL4_I0", - "I1": "CLK_BUFG_BUFGCTRL4_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL4_O", - "S0": "CLK_BUFG_R_BUFGCTRL4_S0", - "S1": "CLK_BUFG_R_BUFGCTRL4_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL4_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL4_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL4_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL4_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2224,15 +9013,96 @@ "name": "X0Y5", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL5_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL5_CE1", - "I0": "CLK_BUFG_BUFGCTRL5_I0", - "I1": "CLK_BUFG_BUFGCTRL5_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL5_O", - "S0": "CLK_BUFG_R_BUFGCTRL5_S0", - "S1": "CLK_BUFG_R_BUFGCTRL5_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL5_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL5_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL5_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL5_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2242,15 +9112,96 @@ "name": "X0Y6", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL6_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL6_CE1", - "I0": "CLK_BUFG_BUFGCTRL6_I0", - "I1": "CLK_BUFG_BUFGCTRL6_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL6_O", - "S0": "CLK_BUFG_R_BUFGCTRL6_S0", - "S1": "CLK_BUFG_R_BUFGCTRL6_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL6_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL6_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL6_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL6_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2260,15 +9211,96 @@ "name": "X0Y7", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL7_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL7_CE1", - "I0": "CLK_BUFG_BUFGCTRL7_I0", - "I1": "CLK_BUFG_BUFGCTRL7_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL7_O", - "S0": "CLK_BUFG_R_BUFGCTRL7_S0", - "S1": "CLK_BUFG_R_BUFGCTRL7_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL7_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL7_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL7_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL7_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2278,15 +9310,96 @@ "name": "X0Y8", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL8_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL8_CE1", - "I0": "CLK_BUFG_BUFGCTRL8_I0", - "I1": "CLK_BUFG_BUFGCTRL8_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL8_O", - "S0": "CLK_BUFG_R_BUFGCTRL8_S0", - "S1": "CLK_BUFG_R_BUFGCTRL8_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL8_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL8_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL8_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL8_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2296,15 +9409,96 @@ "name": "X0Y9", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL9_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL9_CE1", - "I0": "CLK_BUFG_BUFGCTRL9_I0", - "I1": "CLK_BUFG_BUFGCTRL9_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL9_O", - "S0": "CLK_BUFG_R_BUFGCTRL9_S0", - "S1": "CLK_BUFG_R_BUFGCTRL9_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL9_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL9_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL9_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL9_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2314,15 +9508,96 @@ "name": "X0Y10", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL10_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL10_CE1", - "I0": "CLK_BUFG_BUFGCTRL10_I0", - "I1": "CLK_BUFG_BUFGCTRL10_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL10_O", - "S0": "CLK_BUFG_R_BUFGCTRL10_S0", - "S1": "CLK_BUFG_R_BUFGCTRL10_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL10_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL10_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL10_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL10_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2332,15 +9607,96 @@ "name": "X0Y11", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL11_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL11_CE1", - "I0": "CLK_BUFG_BUFGCTRL11_I0", - "I1": "CLK_BUFG_BUFGCTRL11_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL11_O", - "S0": "CLK_BUFG_R_BUFGCTRL11_S0", - "S1": "CLK_BUFG_R_BUFGCTRL11_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL11_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL11_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL11_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL11_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2350,15 +9706,96 @@ "name": "X0Y12", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL12_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL12_CE1", - "I0": "CLK_BUFG_BUFGCTRL12_I0", - "I1": "CLK_BUFG_BUFGCTRL12_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL12_O", - "S0": "CLK_BUFG_R_BUFGCTRL12_S0", - "S1": "CLK_BUFG_R_BUFGCTRL12_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL12_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL12_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL12_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL12_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2368,15 +9805,96 @@ "name": "X0Y13", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL13_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL13_CE1", - "I0": "CLK_BUFG_BUFGCTRL13_I0", - "I1": "CLK_BUFG_BUFGCTRL13_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL13_O", - "S0": "CLK_BUFG_R_BUFGCTRL13_S0", - "S1": "CLK_BUFG_R_BUFGCTRL13_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL13_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL13_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL13_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL13_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2386,15 +9904,96 @@ "name": "X0Y14", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL14_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL14_CE1", - "I0": "CLK_BUFG_BUFGCTRL14_I0", - "I1": "CLK_BUFG_BUFGCTRL14_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL14_O", - "S0": "CLK_BUFG_R_BUFGCTRL14_S0", - "S1": "CLK_BUFG_R_BUFGCTRL14_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL14_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL14_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL14_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL14_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2404,15 +10003,96 @@ "name": "X0Y15", "prefix": "BUFGCTRL", "site_pins": { - "CE0": "CLK_BUFG_R_BUFGCTRL15_CE0", - "CE1": "CLK_BUFG_R_BUFGCTRL15_CE1", - "I0": "CLK_BUFG_BUFGCTRL15_I0", - "I1": "CLK_BUFG_BUFGCTRL15_I1", - "IGNORE0": "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "IGNORE1": "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "O": "CLK_BUFG_BUFGCTRL15_O", - "S0": "CLK_BUFG_R_BUFGCTRL15_S0", - "S1": "CLK_BUFG_R_BUFGCTRL15_S1" + "CE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_CE0" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_CE1" + }, + "I0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL15_I0" + }, + "I1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_BUFGCTRL15_I1" + }, + "IGNORE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE0" + }, + "IGNORE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_IGNORE1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_BUFG_BUFGCTRL15_O" + }, + "S0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_S0" + }, + "S1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_BUFG_R_BUFGCTRL15_S1" + } }, "type": "BUFGCTRL", "x_coord": 0, @@ -2420,1150 +10100,1750 @@ } ], "tile_type": "CLK_BUFG_TOP_R", - "wires": [ - "CLK_BUFG_BUFGCTRL0_I0", - "CLK_BUFG_BUFGCTRL0_I1", - "CLK_BUFG_BUFGCTRL0_O", - "CLK_BUFG_BUFGCTRL10_I0", - "CLK_BUFG_BUFGCTRL10_I1", - "CLK_BUFG_BUFGCTRL10_O", - "CLK_BUFG_BUFGCTRL11_I0", - "CLK_BUFG_BUFGCTRL11_I1", - "CLK_BUFG_BUFGCTRL11_O", - "CLK_BUFG_BUFGCTRL12_I0", - "CLK_BUFG_BUFGCTRL12_I1", - "CLK_BUFG_BUFGCTRL12_O", - "CLK_BUFG_BUFGCTRL13_I0", - "CLK_BUFG_BUFGCTRL13_I1", - "CLK_BUFG_BUFGCTRL13_O", - "CLK_BUFG_BUFGCTRL14_I0", - "CLK_BUFG_BUFGCTRL14_I1", - "CLK_BUFG_BUFGCTRL14_O", - "CLK_BUFG_BUFGCTRL15_I0", - "CLK_BUFG_BUFGCTRL15_I1", - "CLK_BUFG_BUFGCTRL15_O", - "CLK_BUFG_BUFGCTRL1_I0", - "CLK_BUFG_BUFGCTRL1_I1", - "CLK_BUFG_BUFGCTRL1_O", - "CLK_BUFG_BUFGCTRL2_I0", - "CLK_BUFG_BUFGCTRL2_I1", - "CLK_BUFG_BUFGCTRL2_O", - "CLK_BUFG_BUFGCTRL3_I0", - "CLK_BUFG_BUFGCTRL3_I1", - "CLK_BUFG_BUFGCTRL3_O", - "CLK_BUFG_BUFGCTRL4_I0", - "CLK_BUFG_BUFGCTRL4_I1", - "CLK_BUFG_BUFGCTRL4_O", - "CLK_BUFG_BUFGCTRL5_I0", - "CLK_BUFG_BUFGCTRL5_I1", - "CLK_BUFG_BUFGCTRL5_O", - "CLK_BUFG_BUFGCTRL6_I0", - "CLK_BUFG_BUFGCTRL6_I1", - "CLK_BUFG_BUFGCTRL6_O", - "CLK_BUFG_BUFGCTRL7_I0", - "CLK_BUFG_BUFGCTRL7_I1", - "CLK_BUFG_BUFGCTRL7_O", - "CLK_BUFG_BUFGCTRL8_I0", - "CLK_BUFG_BUFGCTRL8_I1", - "CLK_BUFG_BUFGCTRL8_O", - "CLK_BUFG_BUFGCTRL9_I0", - "CLK_BUFG_BUFGCTRL9_I1", - "CLK_BUFG_BUFGCTRL9_O", - "CLK_BUFG_CK_GCLK0", - "CLK_BUFG_CK_GCLK1", - "CLK_BUFG_CK_GCLK10", - "CLK_BUFG_CK_GCLK11", - "CLK_BUFG_CK_GCLK12", - "CLK_BUFG_CK_GCLK13", - "CLK_BUFG_CK_GCLK14", - "CLK_BUFG_CK_GCLK15", - "CLK_BUFG_CK_GCLK16", - "CLK_BUFG_CK_GCLK17", - "CLK_BUFG_CK_GCLK18", - "CLK_BUFG_CK_GCLK19", - "CLK_BUFG_CK_GCLK2", - "CLK_BUFG_CK_GCLK20", - "CLK_BUFG_CK_GCLK21", - "CLK_BUFG_CK_GCLK22", - "CLK_BUFG_CK_GCLK23", - "CLK_BUFG_CK_GCLK24", - "CLK_BUFG_CK_GCLK25", - "CLK_BUFG_CK_GCLK26", - "CLK_BUFG_CK_GCLK27", - "CLK_BUFG_CK_GCLK28", - "CLK_BUFG_CK_GCLK29", - "CLK_BUFG_CK_GCLK3", - "CLK_BUFG_CK_GCLK30", - "CLK_BUFG_CK_GCLK31", - "CLK_BUFG_CK_GCLK4", - "CLK_BUFG_CK_GCLK5", - "CLK_BUFG_CK_GCLK6", - "CLK_BUFG_CK_GCLK7", - "CLK_BUFG_CK_GCLK8", - "CLK_BUFG_CK_GCLK9", - "CLK_BUFG_IMUX0_0", - "CLK_BUFG_IMUX0_1", - "CLK_BUFG_IMUX0_2", - "CLK_BUFG_IMUX0_3", - "CLK_BUFG_IMUX10_0", - "CLK_BUFG_IMUX10_1", - "CLK_BUFG_IMUX10_2", - "CLK_BUFG_IMUX10_3", - "CLK_BUFG_IMUX11_0", - "CLK_BUFG_IMUX11_1", - "CLK_BUFG_IMUX11_2", - "CLK_BUFG_IMUX11_3", - "CLK_BUFG_IMUX12_0", - "CLK_BUFG_IMUX12_1", - "CLK_BUFG_IMUX12_2", - "CLK_BUFG_IMUX12_3", - "CLK_BUFG_IMUX13_0", - "CLK_BUFG_IMUX13_1", - "CLK_BUFG_IMUX13_2", - "CLK_BUFG_IMUX13_3", - "CLK_BUFG_IMUX14_0", - "CLK_BUFG_IMUX14_1", - "CLK_BUFG_IMUX14_2", - "CLK_BUFG_IMUX14_3", - "CLK_BUFG_IMUX15_0", - "CLK_BUFG_IMUX15_1", - "CLK_BUFG_IMUX15_2", - "CLK_BUFG_IMUX15_3", - "CLK_BUFG_IMUX16_0", - "CLK_BUFG_IMUX16_1", - "CLK_BUFG_IMUX16_2", - "CLK_BUFG_IMUX16_3", - "CLK_BUFG_IMUX17_0", - "CLK_BUFG_IMUX17_1", - "CLK_BUFG_IMUX17_2", - "CLK_BUFG_IMUX17_3", - "CLK_BUFG_IMUX18_0", - "CLK_BUFG_IMUX18_1", - "CLK_BUFG_IMUX18_2", - "CLK_BUFG_IMUX18_3", - "CLK_BUFG_IMUX19_0", - "CLK_BUFG_IMUX19_1", - "CLK_BUFG_IMUX19_2", - "CLK_BUFG_IMUX19_3", - "CLK_BUFG_IMUX1_0", - "CLK_BUFG_IMUX1_1", - "CLK_BUFG_IMUX1_2", - "CLK_BUFG_IMUX1_3", - "CLK_BUFG_IMUX20_0", - "CLK_BUFG_IMUX20_1", - "CLK_BUFG_IMUX20_2", - "CLK_BUFG_IMUX20_3", - "CLK_BUFG_IMUX21_0", - "CLK_BUFG_IMUX21_1", - "CLK_BUFG_IMUX21_2", - "CLK_BUFG_IMUX21_3", - "CLK_BUFG_IMUX22_0", - "CLK_BUFG_IMUX22_1", - "CLK_BUFG_IMUX22_2", - "CLK_BUFG_IMUX22_3", - "CLK_BUFG_IMUX23_0", - "CLK_BUFG_IMUX23_1", - "CLK_BUFG_IMUX23_2", - "CLK_BUFG_IMUX23_3", - "CLK_BUFG_IMUX24_0", - "CLK_BUFG_IMUX24_1", - "CLK_BUFG_IMUX24_2", - "CLK_BUFG_IMUX24_3", - "CLK_BUFG_IMUX25_0", - "CLK_BUFG_IMUX25_1", - "CLK_BUFG_IMUX25_2", - "CLK_BUFG_IMUX25_3", - "CLK_BUFG_IMUX26_0", - "CLK_BUFG_IMUX26_1", - "CLK_BUFG_IMUX26_2", - "CLK_BUFG_IMUX26_3", - "CLK_BUFG_IMUX27_0", - "CLK_BUFG_IMUX27_1", - "CLK_BUFG_IMUX27_2", - "CLK_BUFG_IMUX27_3", - "CLK_BUFG_IMUX28_0", - "CLK_BUFG_IMUX28_1", - "CLK_BUFG_IMUX28_2", - "CLK_BUFG_IMUX28_3", - "CLK_BUFG_IMUX29_0", - "CLK_BUFG_IMUX29_1", - "CLK_BUFG_IMUX29_2", - "CLK_BUFG_IMUX29_3", - "CLK_BUFG_IMUX2_0", - "CLK_BUFG_IMUX2_1", - "CLK_BUFG_IMUX2_2", - "CLK_BUFG_IMUX2_3", - "CLK_BUFG_IMUX30_0", - "CLK_BUFG_IMUX30_1", - "CLK_BUFG_IMUX30_2", - "CLK_BUFG_IMUX30_3", - "CLK_BUFG_IMUX31_0", - "CLK_BUFG_IMUX31_1", - "CLK_BUFG_IMUX31_2", - "CLK_BUFG_IMUX31_3", - "CLK_BUFG_IMUX32_0", - "CLK_BUFG_IMUX32_1", - "CLK_BUFG_IMUX32_2", - "CLK_BUFG_IMUX32_3", - "CLK_BUFG_IMUX33_0", - "CLK_BUFG_IMUX33_1", - "CLK_BUFG_IMUX33_2", - "CLK_BUFG_IMUX33_3", - "CLK_BUFG_IMUX34_0", - "CLK_BUFG_IMUX34_1", - "CLK_BUFG_IMUX34_2", - "CLK_BUFG_IMUX34_3", - "CLK_BUFG_IMUX35_0", - "CLK_BUFG_IMUX35_1", - "CLK_BUFG_IMUX35_2", - "CLK_BUFG_IMUX35_3", - "CLK_BUFG_IMUX36_0", - "CLK_BUFG_IMUX36_1", - "CLK_BUFG_IMUX36_2", - "CLK_BUFG_IMUX36_3", - "CLK_BUFG_IMUX37_0", - "CLK_BUFG_IMUX37_1", - "CLK_BUFG_IMUX37_2", - "CLK_BUFG_IMUX37_3", - "CLK_BUFG_IMUX38_0", - "CLK_BUFG_IMUX38_1", - "CLK_BUFG_IMUX38_2", - "CLK_BUFG_IMUX38_3", - "CLK_BUFG_IMUX39_0", - "CLK_BUFG_IMUX39_1", - "CLK_BUFG_IMUX39_2", - "CLK_BUFG_IMUX39_3", - "CLK_BUFG_IMUX3_0", - "CLK_BUFG_IMUX3_1", - "CLK_BUFG_IMUX3_2", - "CLK_BUFG_IMUX3_3", - "CLK_BUFG_IMUX40_0", - "CLK_BUFG_IMUX40_1", - "CLK_BUFG_IMUX40_2", - "CLK_BUFG_IMUX40_3", - "CLK_BUFG_IMUX41_0", - "CLK_BUFG_IMUX41_1", - "CLK_BUFG_IMUX41_2", - "CLK_BUFG_IMUX41_3", - "CLK_BUFG_IMUX42_0", - "CLK_BUFG_IMUX42_1", - "CLK_BUFG_IMUX42_2", - "CLK_BUFG_IMUX42_3", - "CLK_BUFG_IMUX43_0", - "CLK_BUFG_IMUX43_1", - "CLK_BUFG_IMUX43_2", - "CLK_BUFG_IMUX43_3", - "CLK_BUFG_IMUX44_0", - "CLK_BUFG_IMUX44_1", - "CLK_BUFG_IMUX44_2", - "CLK_BUFG_IMUX44_3", - "CLK_BUFG_IMUX45_0", - "CLK_BUFG_IMUX45_1", - "CLK_BUFG_IMUX45_2", - "CLK_BUFG_IMUX45_3", - "CLK_BUFG_IMUX46_0", - "CLK_BUFG_IMUX46_1", - "CLK_BUFG_IMUX46_2", - "CLK_BUFG_IMUX46_3", - "CLK_BUFG_IMUX47_0", - "CLK_BUFG_IMUX47_1", - "CLK_BUFG_IMUX47_2", - "CLK_BUFG_IMUX47_3", - "CLK_BUFG_IMUX4_0", - "CLK_BUFG_IMUX4_1", - "CLK_BUFG_IMUX4_2", - "CLK_BUFG_IMUX4_3", - "CLK_BUFG_IMUX5_0", - "CLK_BUFG_IMUX5_1", - "CLK_BUFG_IMUX5_2", - "CLK_BUFG_IMUX5_3", - "CLK_BUFG_IMUX6_0", - "CLK_BUFG_IMUX6_1", - "CLK_BUFG_IMUX6_2", - "CLK_BUFG_IMUX6_3", - "CLK_BUFG_IMUX7_0", - "CLK_BUFG_IMUX7_1", - "CLK_BUFG_IMUX7_2", - "CLK_BUFG_IMUX7_3", - "CLK_BUFG_IMUX8_0", - "CLK_BUFG_IMUX8_1", - "CLK_BUFG_IMUX8_2", - "CLK_BUFG_IMUX8_3", - "CLK_BUFG_IMUX9_0", - "CLK_BUFG_IMUX9_1", - "CLK_BUFG_IMUX9_2", - "CLK_BUFG_IMUX9_3", - "CLK_BUFG_LOGIC_OUTS_B0_0", - "CLK_BUFG_LOGIC_OUTS_B0_1", - "CLK_BUFG_LOGIC_OUTS_B0_2", - "CLK_BUFG_LOGIC_OUTS_B0_3", - "CLK_BUFG_LOGIC_OUTS_B10_0", - "CLK_BUFG_LOGIC_OUTS_B10_1", - "CLK_BUFG_LOGIC_OUTS_B10_2", - "CLK_BUFG_LOGIC_OUTS_B10_3", - "CLK_BUFG_LOGIC_OUTS_B11_0", - "CLK_BUFG_LOGIC_OUTS_B11_1", - "CLK_BUFG_LOGIC_OUTS_B11_2", - "CLK_BUFG_LOGIC_OUTS_B11_3", - "CLK_BUFG_LOGIC_OUTS_B12_0", - "CLK_BUFG_LOGIC_OUTS_B12_1", - "CLK_BUFG_LOGIC_OUTS_B12_2", - "CLK_BUFG_LOGIC_OUTS_B12_3", - "CLK_BUFG_LOGIC_OUTS_B13_0", - "CLK_BUFG_LOGIC_OUTS_B13_1", - "CLK_BUFG_LOGIC_OUTS_B13_2", - "CLK_BUFG_LOGIC_OUTS_B13_3", - "CLK_BUFG_LOGIC_OUTS_B14_0", - "CLK_BUFG_LOGIC_OUTS_B14_1", - "CLK_BUFG_LOGIC_OUTS_B14_2", - "CLK_BUFG_LOGIC_OUTS_B14_3", - "CLK_BUFG_LOGIC_OUTS_B15_0", - "CLK_BUFG_LOGIC_OUTS_B15_1", - "CLK_BUFG_LOGIC_OUTS_B15_2", - "CLK_BUFG_LOGIC_OUTS_B15_3", - "CLK_BUFG_LOGIC_OUTS_B16_0", - "CLK_BUFG_LOGIC_OUTS_B16_1", - "CLK_BUFG_LOGIC_OUTS_B16_2", - "CLK_BUFG_LOGIC_OUTS_B16_3", - "CLK_BUFG_LOGIC_OUTS_B17_0", - "CLK_BUFG_LOGIC_OUTS_B17_1", - "CLK_BUFG_LOGIC_OUTS_B17_2", - "CLK_BUFG_LOGIC_OUTS_B17_3", - "CLK_BUFG_LOGIC_OUTS_B18_0", - "CLK_BUFG_LOGIC_OUTS_B18_1", - "CLK_BUFG_LOGIC_OUTS_B18_2", - "CLK_BUFG_LOGIC_OUTS_B18_3", - "CLK_BUFG_LOGIC_OUTS_B19_0", - "CLK_BUFG_LOGIC_OUTS_B19_1", - "CLK_BUFG_LOGIC_OUTS_B19_2", - "CLK_BUFG_LOGIC_OUTS_B19_3", - "CLK_BUFG_LOGIC_OUTS_B1_0", - "CLK_BUFG_LOGIC_OUTS_B1_1", - "CLK_BUFG_LOGIC_OUTS_B1_2", - "CLK_BUFG_LOGIC_OUTS_B1_3", - "CLK_BUFG_LOGIC_OUTS_B20_0", - "CLK_BUFG_LOGIC_OUTS_B20_1", - "CLK_BUFG_LOGIC_OUTS_B20_2", - "CLK_BUFG_LOGIC_OUTS_B20_3", - "CLK_BUFG_LOGIC_OUTS_B21_0", - "CLK_BUFG_LOGIC_OUTS_B21_1", - "CLK_BUFG_LOGIC_OUTS_B21_2", - "CLK_BUFG_LOGIC_OUTS_B21_3", - "CLK_BUFG_LOGIC_OUTS_B22_0", - "CLK_BUFG_LOGIC_OUTS_B22_1", - "CLK_BUFG_LOGIC_OUTS_B22_2", - "CLK_BUFG_LOGIC_OUTS_B22_3", - "CLK_BUFG_LOGIC_OUTS_B23_0", - "CLK_BUFG_LOGIC_OUTS_B23_1", - "CLK_BUFG_LOGIC_OUTS_B23_2", - "CLK_BUFG_LOGIC_OUTS_B23_3", - "CLK_BUFG_LOGIC_OUTS_B2_0", - "CLK_BUFG_LOGIC_OUTS_B2_1", - "CLK_BUFG_LOGIC_OUTS_B2_2", - "CLK_BUFG_LOGIC_OUTS_B2_3", - "CLK_BUFG_LOGIC_OUTS_B3_0", - "CLK_BUFG_LOGIC_OUTS_B3_1", - "CLK_BUFG_LOGIC_OUTS_B3_2", - "CLK_BUFG_LOGIC_OUTS_B3_3", - "CLK_BUFG_LOGIC_OUTS_B4_0", - "CLK_BUFG_LOGIC_OUTS_B4_1", - "CLK_BUFG_LOGIC_OUTS_B4_2", - "CLK_BUFG_LOGIC_OUTS_B4_3", - "CLK_BUFG_LOGIC_OUTS_B5_0", - "CLK_BUFG_LOGIC_OUTS_B5_1", - "CLK_BUFG_LOGIC_OUTS_B5_2", - "CLK_BUFG_LOGIC_OUTS_B5_3", - "CLK_BUFG_LOGIC_OUTS_B6_0", - "CLK_BUFG_LOGIC_OUTS_B6_1", - "CLK_BUFG_LOGIC_OUTS_B6_2", - "CLK_BUFG_LOGIC_OUTS_B6_3", - "CLK_BUFG_LOGIC_OUTS_B7_0", - "CLK_BUFG_LOGIC_OUTS_B7_1", - "CLK_BUFG_LOGIC_OUTS_B7_2", - "CLK_BUFG_LOGIC_OUTS_B7_3", - "CLK_BUFG_LOGIC_OUTS_B8_0", - "CLK_BUFG_LOGIC_OUTS_B8_1", - "CLK_BUFG_LOGIC_OUTS_B8_2", - "CLK_BUFG_LOGIC_OUTS_B8_3", - "CLK_BUFG_LOGIC_OUTS_B9_0", - "CLK_BUFG_LOGIC_OUTS_B9_1", - "CLK_BUFG_LOGIC_OUTS_B9_2", - "CLK_BUFG_LOGIC_OUTS_B9_3", - "CLK_BUFG_R_BUFGCTRL0_CE0", - "CLK_BUFG_R_BUFGCTRL0_CE1", - "CLK_BUFG_R_BUFGCTRL0_IGNORE0", - "CLK_BUFG_R_BUFGCTRL0_IGNORE1", - "CLK_BUFG_R_BUFGCTRL0_S0", - "CLK_BUFG_R_BUFGCTRL0_S1", - "CLK_BUFG_R_BUFGCTRL10_CE0", - "CLK_BUFG_R_BUFGCTRL10_CE1", - "CLK_BUFG_R_BUFGCTRL10_IGNORE0", - "CLK_BUFG_R_BUFGCTRL10_IGNORE1", - "CLK_BUFG_R_BUFGCTRL10_S0", - "CLK_BUFG_R_BUFGCTRL10_S1", - "CLK_BUFG_R_BUFGCTRL11_CE0", - "CLK_BUFG_R_BUFGCTRL11_CE1", - "CLK_BUFG_R_BUFGCTRL11_IGNORE0", - "CLK_BUFG_R_BUFGCTRL11_IGNORE1", - "CLK_BUFG_R_BUFGCTRL11_S0", - "CLK_BUFG_R_BUFGCTRL11_S1", - "CLK_BUFG_R_BUFGCTRL12_CE0", - "CLK_BUFG_R_BUFGCTRL12_CE1", - "CLK_BUFG_R_BUFGCTRL12_IGNORE0", - "CLK_BUFG_R_BUFGCTRL12_IGNORE1", - "CLK_BUFG_R_BUFGCTRL12_S0", - "CLK_BUFG_R_BUFGCTRL12_S1", - "CLK_BUFG_R_BUFGCTRL13_CE0", - "CLK_BUFG_R_BUFGCTRL13_CE1", - "CLK_BUFG_R_BUFGCTRL13_IGNORE0", - "CLK_BUFG_R_BUFGCTRL13_IGNORE1", - "CLK_BUFG_R_BUFGCTRL13_S0", - "CLK_BUFG_R_BUFGCTRL13_S1", - "CLK_BUFG_R_BUFGCTRL14_CE0", - "CLK_BUFG_R_BUFGCTRL14_CE1", - "CLK_BUFG_R_BUFGCTRL14_IGNORE0", - "CLK_BUFG_R_BUFGCTRL14_IGNORE1", - "CLK_BUFG_R_BUFGCTRL14_S0", - "CLK_BUFG_R_BUFGCTRL14_S1", - "CLK_BUFG_R_BUFGCTRL15_CE0", - "CLK_BUFG_R_BUFGCTRL15_CE1", - "CLK_BUFG_R_BUFGCTRL15_IGNORE0", - "CLK_BUFG_R_BUFGCTRL15_IGNORE1", - "CLK_BUFG_R_BUFGCTRL15_S0", - "CLK_BUFG_R_BUFGCTRL15_S1", - "CLK_BUFG_R_BUFGCTRL1_CE0", - "CLK_BUFG_R_BUFGCTRL1_CE1", - "CLK_BUFG_R_BUFGCTRL1_IGNORE0", - "CLK_BUFG_R_BUFGCTRL1_IGNORE1", - "CLK_BUFG_R_BUFGCTRL1_S0", - "CLK_BUFG_R_BUFGCTRL1_S1", - "CLK_BUFG_R_BUFGCTRL2_CE0", - "CLK_BUFG_R_BUFGCTRL2_CE1", - "CLK_BUFG_R_BUFGCTRL2_IGNORE0", - "CLK_BUFG_R_BUFGCTRL2_IGNORE1", - "CLK_BUFG_R_BUFGCTRL2_S0", - "CLK_BUFG_R_BUFGCTRL2_S1", - "CLK_BUFG_R_BUFGCTRL3_CE0", - "CLK_BUFG_R_BUFGCTRL3_CE1", - "CLK_BUFG_R_BUFGCTRL3_IGNORE0", - "CLK_BUFG_R_BUFGCTRL3_IGNORE1", - "CLK_BUFG_R_BUFGCTRL3_S0", - "CLK_BUFG_R_BUFGCTRL3_S1", - "CLK_BUFG_R_BUFGCTRL4_CE0", - "CLK_BUFG_R_BUFGCTRL4_CE1", - "CLK_BUFG_R_BUFGCTRL4_IGNORE0", - "CLK_BUFG_R_BUFGCTRL4_IGNORE1", - "CLK_BUFG_R_BUFGCTRL4_S0", - "CLK_BUFG_R_BUFGCTRL4_S1", - "CLK_BUFG_R_BUFGCTRL5_CE0", - "CLK_BUFG_R_BUFGCTRL5_CE1", - "CLK_BUFG_R_BUFGCTRL5_IGNORE0", - "CLK_BUFG_R_BUFGCTRL5_IGNORE1", - "CLK_BUFG_R_BUFGCTRL5_S0", - "CLK_BUFG_R_BUFGCTRL5_S1", - "CLK_BUFG_R_BUFGCTRL6_CE0", - "CLK_BUFG_R_BUFGCTRL6_CE1", - "CLK_BUFG_R_BUFGCTRL6_IGNORE0", - "CLK_BUFG_R_BUFGCTRL6_IGNORE1", - "CLK_BUFG_R_BUFGCTRL6_S0", - "CLK_BUFG_R_BUFGCTRL6_S1", - "CLK_BUFG_R_BUFGCTRL7_CE0", - "CLK_BUFG_R_BUFGCTRL7_CE1", - "CLK_BUFG_R_BUFGCTRL7_IGNORE0", - "CLK_BUFG_R_BUFGCTRL7_IGNORE1", - "CLK_BUFG_R_BUFGCTRL7_S0", - "CLK_BUFG_R_BUFGCTRL7_S1", - "CLK_BUFG_R_BUFGCTRL8_CE0", - "CLK_BUFG_R_BUFGCTRL8_CE1", - "CLK_BUFG_R_BUFGCTRL8_IGNORE0", - "CLK_BUFG_R_BUFGCTRL8_IGNORE1", - "CLK_BUFG_R_BUFGCTRL8_S0", - "CLK_BUFG_R_BUFGCTRL8_S1", - "CLK_BUFG_R_BUFGCTRL9_CE0", - "CLK_BUFG_R_BUFGCTRL9_CE1", - "CLK_BUFG_R_BUFGCTRL9_IGNORE0", - "CLK_BUFG_R_BUFGCTRL9_IGNORE1", - "CLK_BUFG_R_BUFGCTRL9_S0", - "CLK_BUFG_R_BUFGCTRL9_S1", - "CLK_BUFG_R_CK_FB_TEST0_0", - "CLK_BUFG_R_CK_FB_TEST0_1", - "CLK_BUFG_R_CK_FB_TEST0_10", - "CLK_BUFG_R_CK_FB_TEST0_11", - "CLK_BUFG_R_CK_FB_TEST0_12", - "CLK_BUFG_R_CK_FB_TEST0_13", - "CLK_BUFG_R_CK_FB_TEST0_14", - "CLK_BUFG_R_CK_FB_TEST0_15", - "CLK_BUFG_R_CK_FB_TEST0_2", - "CLK_BUFG_R_CK_FB_TEST0_3", - "CLK_BUFG_R_CK_FB_TEST0_4", - "CLK_BUFG_R_CK_FB_TEST0_5", - "CLK_BUFG_R_CK_FB_TEST0_6", - "CLK_BUFG_R_CK_FB_TEST0_7", - "CLK_BUFG_R_CK_FB_TEST0_8", - "CLK_BUFG_R_CK_FB_TEST0_9", - "CLK_BUFG_R_CK_FB_TEST1_0", - "CLK_BUFG_R_CK_FB_TEST1_1", - "CLK_BUFG_R_CK_FB_TEST1_10", - "CLK_BUFG_R_CK_FB_TEST1_11", - "CLK_BUFG_R_CK_FB_TEST1_12", - "CLK_BUFG_R_CK_FB_TEST1_13", - "CLK_BUFG_R_CK_FB_TEST1_14", - "CLK_BUFG_R_CK_FB_TEST1_15", - "CLK_BUFG_R_CK_FB_TEST1_2", - "CLK_BUFG_R_CK_FB_TEST1_3", - "CLK_BUFG_R_CK_FB_TEST1_4", - "CLK_BUFG_R_CK_FB_TEST1_5", - "CLK_BUFG_R_CK_FB_TEST1_6", - "CLK_BUFG_R_CK_FB_TEST1_7", - "CLK_BUFG_R_CK_FB_TEST1_8", - "CLK_BUFG_R_CK_FB_TEST1_9", - "CLK_BUFG_R_FBG_OUT0", - "CLK_BUFG_R_FBG_OUT1", - "CLK_BUFG_R_FBG_OUT10", - "CLK_BUFG_R_FBG_OUT11", - "CLK_BUFG_R_FBG_OUT12", - "CLK_BUFG_R_FBG_OUT13", - "CLK_BUFG_R_FBG_OUT14", - "CLK_BUFG_R_FBG_OUT15", - "CLK_BUFG_R_FBG_OUT2", - "CLK_BUFG_R_FBG_OUT3", - "CLK_BUFG_R_FBG_OUT4", - "CLK_BUFG_R_FBG_OUT5", - "CLK_BUFG_R_FBG_OUT6", - "CLK_BUFG_R_FBG_OUT7", - "CLK_BUFG_R_FBG_OUT8", - "CLK_BUFG_R_FBG_OUT9", - "CLK_BUFG_TOP_R_CK_MUXED0", - "CLK_BUFG_TOP_R_CK_MUXED1", - "CLK_BUFG_TOP_R_CK_MUXED10", - "CLK_BUFG_TOP_R_CK_MUXED11", - "CLK_BUFG_TOP_R_CK_MUXED12", - "CLK_BUFG_TOP_R_CK_MUXED13", - "CLK_BUFG_TOP_R_CK_MUXED14", - "CLK_BUFG_TOP_R_CK_MUXED15", - "CLK_BUFG_TOP_R_CK_MUXED16", - "CLK_BUFG_TOP_R_CK_MUXED17", - "CLK_BUFG_TOP_R_CK_MUXED18", - "CLK_BUFG_TOP_R_CK_MUXED19", - "CLK_BUFG_TOP_R_CK_MUXED2", - "CLK_BUFG_TOP_R_CK_MUXED20", - "CLK_BUFG_TOP_R_CK_MUXED21", - "CLK_BUFG_TOP_R_CK_MUXED22", - "CLK_BUFG_TOP_R_CK_MUXED23", - "CLK_BUFG_TOP_R_CK_MUXED24", - "CLK_BUFG_TOP_R_CK_MUXED25", - "CLK_BUFG_TOP_R_CK_MUXED26", - "CLK_BUFG_TOP_R_CK_MUXED27", - "CLK_BUFG_TOP_R_CK_MUXED28", - "CLK_BUFG_TOP_R_CK_MUXED29", - "CLK_BUFG_TOP_R_CK_MUXED3", - "CLK_BUFG_TOP_R_CK_MUXED30", - "CLK_BUFG_TOP_R_CK_MUXED31", - "CLK_BUFG_TOP_R_CK_MUXED4", - "CLK_BUFG_TOP_R_CK_MUXED5", - "CLK_BUFG_TOP_R_CK_MUXED6", - "CLK_BUFG_TOP_R_CK_MUXED7", - "CLK_BUFG_TOP_R_CK_MUXED8", - "CLK_BUFG_TOP_R_CK_MUXED9", - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_BYP0_0", - "CLK_HROW_BYP0_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_BYP0_3", - "CLK_HROW_BYP1_0", - "CLK_HROW_BYP1_1", - "CLK_HROW_BYP1_2", - "CLK_HROW_BYP1_3", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_1", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_3", - "CLK_HROW_BYP3_0", - "CLK_HROW_BYP3_1", - "CLK_HROW_BYP3_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_BYP4_0", - "CLK_HROW_BYP4_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_BYP5_0", - "CLK_HROW_BYP5_1", - "CLK_HROW_BYP5_2", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP6_0", - "CLK_HROW_BYP6_1", - "CLK_HROW_BYP6_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_BYP7_0", - "CLK_HROW_BYP7_1", - "CLK_HROW_BYP7_2", - "CLK_HROW_BYP7_3", - "CLK_HROW_CLK0_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_CLK0_2", - "CLK_HROW_CLK0_3", - "CLK_HROW_CLK1_0", - "CLK_HROW_CLK1_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_CLK1_3", - "CLK_HROW_CTRL0_0", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CTRL0_2", - "CLK_HROW_CTRL0_3", - "CLK_HROW_CTRL1_0", - "CLK_HROW_CTRL1_1", - "CLK_HROW_CTRL1_2", - "CLK_HROW_CTRL1_3", - "CLK_HROW_EE2A0_0", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_EE2A0_3", - "CLK_HROW_EE2A1_0", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE2A1_2", - "CLK_HROW_EE2A1_3", - "CLK_HROW_EE2A2_0", - "CLK_HROW_EE2A2_1", - "CLK_HROW_EE2A2_2", - "CLK_HROW_EE2A2_3", - "CLK_HROW_EE2A3_0", - "CLK_HROW_EE2A3_1", - "CLK_HROW_EE2A3_2", - "CLK_HROW_EE2A3_3", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_EE4A0_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_EE4A0_2", - "CLK_HROW_EE4A0_3", - "CLK_HROW_EE4A1_0", - "CLK_HROW_EE4A1_1", - "CLK_HROW_EE4A1_2", - "CLK_HROW_EE4A1_3", - "CLK_HROW_EE4A2_0", - "CLK_HROW_EE4A2_1", - "CLK_HROW_EE4A2_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_EE4A3_0", - "CLK_HROW_EE4A3_1", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE4B0_0", - "CLK_HROW_EE4B0_1", - "CLK_HROW_EE4B0_2", - "CLK_HROW_EE4B0_3", - "CLK_HROW_EE4B1_0", - "CLK_HROW_EE4B1_1", - "CLK_HROW_EE4B1_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_EE4B2_0", - "CLK_HROW_EE4B2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_EE4B3_0", - "CLK_HROW_EE4B3_1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_EE4C0_0", - "CLK_HROW_EE4C0_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE4C0_3", - "CLK_HROW_EE4C1_0", - "CLK_HROW_EE4C1_1", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE4C1_3", - "CLK_HROW_EE4C2_0", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4C2_2", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4C3_0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_EE4C3_2", - "CLK_HROW_EE4C3_3", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_FAN0_0", - "CLK_HROW_FAN0_1", - "CLK_HROW_FAN0_2", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN1_0", - "CLK_HROW_FAN1_1", - "CLK_HROW_FAN1_2", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN2_0", - "CLK_HROW_FAN2_1", - "CLK_HROW_FAN2_2", - "CLK_HROW_FAN2_3", - "CLK_HROW_FAN3_0", - "CLK_HROW_FAN3_1", - "CLK_HROW_FAN3_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_FAN4_0", - "CLK_HROW_FAN4_1", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_3", - "CLK_HROW_FAN5_0", - "CLK_HROW_FAN5_1", - "CLK_HROW_FAN5_2", - "CLK_HROW_FAN5_3", - "CLK_HROW_FAN6_0", - "CLK_HROW_FAN6_1", - "CLK_HROW_FAN6_2", - "CLK_HROW_FAN6_3", - "CLK_HROW_FAN7_0", - "CLK_HROW_FAN7_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_FAN7_3", - "CLK_HROW_LH10_0", - "CLK_HROW_LH10_1", - "CLK_HROW_LH10_2", - "CLK_HROW_LH10_3", - "CLK_HROW_LH11_0", - "CLK_HROW_LH11_1", - "CLK_HROW_LH11_2", - "CLK_HROW_LH11_3", - "CLK_HROW_LH12_0", - "CLK_HROW_LH12_1", - "CLK_HROW_LH12_2", - "CLK_HROW_LH12_3", - "CLK_HROW_LH1_0", - "CLK_HROW_LH1_1", - "CLK_HROW_LH1_2", - "CLK_HROW_LH1_3", - "CLK_HROW_LH2_0", - "CLK_HROW_LH2_1", - "CLK_HROW_LH2_2", - "CLK_HROW_LH2_3", - "CLK_HROW_LH3_0", - "CLK_HROW_LH3_1", - "CLK_HROW_LH3_2", - "CLK_HROW_LH3_3", - "CLK_HROW_LH4_0", - "CLK_HROW_LH4_1", - "CLK_HROW_LH4_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LH5_0", - "CLK_HROW_LH5_1", - "CLK_HROW_LH5_2", - "CLK_HROW_LH5_3", - "CLK_HROW_LH6_0", - "CLK_HROW_LH6_1", - "CLK_HROW_LH6_2", - "CLK_HROW_LH6_3", - "CLK_HROW_LH7_0", - "CLK_HROW_LH7_1", - "CLK_HROW_LH7_2", - "CLK_HROW_LH7_3", - "CLK_HROW_LH8_0", - "CLK_HROW_LH8_1", - "CLK_HROW_LH8_2", - "CLK_HROW_LH8_3", - "CLK_HROW_LH9_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH9_2", - "CLK_HROW_LH9_3", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_NE2A0_0", - "CLK_HROW_NE2A0_1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A0_3", - "CLK_HROW_NE2A1_0", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NE2A1_2", - "CLK_HROW_NE2A1_3", - "CLK_HROW_NE2A2_0", - "CLK_HROW_NE2A2_1", - "CLK_HROW_NE2A2_2", - "CLK_HROW_NE2A2_3", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NE2A3_1", - "CLK_HROW_NE2A3_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_NE4C0_0", - "CLK_HROW_NE4C0_1", - "CLK_HROW_NE4C0_2", - "CLK_HROW_NE4C0_3", - "CLK_HROW_NE4C1_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_NE4C1_3", - "CLK_HROW_NE4C2_0", - "CLK_HROW_NE4C2_1", - "CLK_HROW_NE4C2_2", - "CLK_HROW_NE4C2_3", - "CLK_HROW_NE4C3_0", - "CLK_HROW_NE4C3_1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_NE4C3_3", - "CLK_HROW_NW2A0_0", - "CLK_HROW_NW2A0_1", - "CLK_HROW_NW2A0_2", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_NW2A1_2", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A2_0", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW2A2_3", - "CLK_HROW_NW2A3_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_NW2A3_2", - "CLK_HROW_NW2A3_3", - "CLK_HROW_NW4A0_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_NW4A0_3", - "CLK_HROW_NW4A1_0", - "CLK_HROW_NW4A1_1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_NW4A1_3", - "CLK_HROW_NW4A2_0", - "CLK_HROW_NW4A2_1", - "CLK_HROW_NW4A2_2", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A3_0", - "CLK_HROW_NW4A3_1", - "CLK_HROW_NW4A3_2", - "CLK_HROW_NW4A3_3", - "CLK_HROW_NW4END0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_NW4END0_3", - "CLK_HROW_NW4END1_0", - "CLK_HROW_NW4END1_1", - "CLK_HROW_NW4END1_2", - "CLK_HROW_NW4END1_3", - "CLK_HROW_NW4END2_0", - "CLK_HROW_NW4END2_1", - "CLK_HROW_NW4END2_2", - "CLK_HROW_NW4END2_3", - "CLK_HROW_NW4END3_0", - "CLK_HROW_NW4END3_1", - "CLK_HROW_NW4END3_2", - "CLK_HROW_NW4END3_3", - "CLK_HROW_SE2A0_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_SE2A0_3", - "CLK_HROW_SE2A1_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_SE2A1_2", - "CLK_HROW_SE2A1_3", - "CLK_HROW_SE2A2_0", - "CLK_HROW_SE2A2_1", - "CLK_HROW_SE2A2_2", - "CLK_HROW_SE2A2_3", - "CLK_HROW_SE2A3_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_SE2A3_2", - "CLK_HROW_SE2A3_3", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_SE4C0_0", - "CLK_HROW_SE4C0_1", - "CLK_HROW_SE4C0_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SE4C1_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_SE4C1_3", - "CLK_HROW_SE4C2_0", - "CLK_HROW_SE4C2_1", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SE4C2_3", - "CLK_HROW_SE4C3_0", - "CLK_HROW_SE4C3_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_SW2A0_0", - "CLK_HROW_SW2A0_1", - "CLK_HROW_SW2A0_2", - "CLK_HROW_SW2A0_3", - "CLK_HROW_SW2A1_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_SW2A1_3", - "CLK_HROW_SW2A2_0", - "CLK_HROW_SW2A2_1", - "CLK_HROW_SW2A2_2", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SW2A3_0", - "CLK_HROW_SW2A3_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_SW2A3_3", - "CLK_HROW_SW4A0_0", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_SW4A1_0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_SW4A1_2", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_1", - "CLK_HROW_SW4A2_2", - "CLK_HROW_SW4A2_3", - "CLK_HROW_SW4A3_0", - "CLK_HROW_SW4A3_1", - "CLK_HROW_SW4A3_2", - "CLK_HROW_SW4A3_3", - "CLK_HROW_SW4END0_0", - "CLK_HROW_SW4END0_1", - "CLK_HROW_SW4END0_2", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW4END1_0", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SW4END1_2", - "CLK_HROW_SW4END1_3", - "CLK_HROW_SW4END2_0", - "CLK_HROW_SW4END2_1", - "CLK_HROW_SW4END2_2", - "CLK_HROW_SW4END2_3", - "CLK_HROW_SW4END3_0", - "CLK_HROW_SW4END3_1", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_1", - "CLK_HROW_WL1END0_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_WL1END1_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_WL1END2_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WL1END3_0", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WL1END3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_WR1END0_0", - "CLK_HROW_WR1END0_1", - "CLK_HROW_WR1END0_2", - "CLK_HROW_WR1END0_3", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WR1END1_1", - "CLK_HROW_WR1END1_2", - "CLK_HROW_WR1END1_3", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WR1END2_1", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_WR1END3_2", - "CLK_HROW_WR1END3_3", - "CLK_HROW_WW2A0_0", - "CLK_HROW_WW2A0_1", - "CLK_HROW_WW2A0_2", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WW2A1_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_WW2A1_3", - "CLK_HROW_WW2A2_0", - "CLK_HROW_WW2A2_1", - "CLK_HROW_WW2A2_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_WW2A3_0", - "CLK_HROW_WW2A3_1", - "CLK_HROW_WW2A3_2", - "CLK_HROW_WW2A3_3", - "CLK_HROW_WW2END0_0", - "CLK_HROW_WW2END0_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_WW2END0_3", - "CLK_HROW_WW2END1_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_WW2END1_2", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW2END2_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW2END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_WW2END3_2", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW4A0_0", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4A0_2", - "CLK_HROW_WW4A0_3", - "CLK_HROW_WW4A1_0", - "CLK_HROW_WW4A1_1", - "CLK_HROW_WW4A1_2", - "CLK_HROW_WW4A1_3", - "CLK_HROW_WW4A2_0", - "CLK_HROW_WW4A2_1", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW4A2_3", - "CLK_HROW_WW4A3_0", - "CLK_HROW_WW4A3_1", - "CLK_HROW_WW4A3_2", - "CLK_HROW_WW4A3_3", - "CLK_HROW_WW4B0_0", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4B0_2", - "CLK_HROW_WW4B0_3", - "CLK_HROW_WW4B1_0", - "CLK_HROW_WW4B1_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_WW4B1_3", - "CLK_HROW_WW4B2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_WW4B2_2", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4B3_0", - "CLK_HROW_WW4B3_1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_WW4B3_3", - "CLK_HROW_WW4C0_0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_WW4C0_2", - "CLK_HROW_WW4C0_3", - "CLK_HROW_WW4C1_0", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WW4C1_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_WW4C2_0", - "CLK_HROW_WW4C2_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_WW4C2_3", - "CLK_HROW_WW4C3_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_WW4C3_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_WW4END0_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW4END0_2", - "CLK_HROW_WW4END0_3", - "CLK_HROW_WW4END1_0", - "CLK_HROW_WW4END1_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_WW4END1_3", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_WW4END2_3", - "CLK_HROW_WW4END3_0", - "CLK_HROW_WW4END3_1", - "CLK_HROW_WW4END3_2", - "CLK_HROW_WW4END3_3" - ] + "wires": { + "CLK_BUFG_BUFGCTRL0_I0": null, + "CLK_BUFG_BUFGCTRL0_I1": null, + "CLK_BUFG_BUFGCTRL0_O": null, + "CLK_BUFG_BUFGCTRL10_I0": null, + "CLK_BUFG_BUFGCTRL10_I1": null, + "CLK_BUFG_BUFGCTRL10_O": null, + "CLK_BUFG_BUFGCTRL11_I0": null, + "CLK_BUFG_BUFGCTRL11_I1": null, + "CLK_BUFG_BUFGCTRL11_O": null, + "CLK_BUFG_BUFGCTRL12_I0": null, + "CLK_BUFG_BUFGCTRL12_I1": null, + "CLK_BUFG_BUFGCTRL12_O": null, + "CLK_BUFG_BUFGCTRL13_I0": null, + "CLK_BUFG_BUFGCTRL13_I1": null, + "CLK_BUFG_BUFGCTRL13_O": null, + "CLK_BUFG_BUFGCTRL14_I0": null, + "CLK_BUFG_BUFGCTRL14_I1": null, + "CLK_BUFG_BUFGCTRL14_O": null, + "CLK_BUFG_BUFGCTRL15_I0": null, + "CLK_BUFG_BUFGCTRL15_I1": null, + "CLK_BUFG_BUFGCTRL15_O": null, + "CLK_BUFG_BUFGCTRL1_I0": null, + "CLK_BUFG_BUFGCTRL1_I1": null, + "CLK_BUFG_BUFGCTRL1_O": null, + "CLK_BUFG_BUFGCTRL2_I0": null, + "CLK_BUFG_BUFGCTRL2_I1": null, + "CLK_BUFG_BUFGCTRL2_O": null, + "CLK_BUFG_BUFGCTRL3_I0": null, + "CLK_BUFG_BUFGCTRL3_I1": null, + "CLK_BUFG_BUFGCTRL3_O": null, + "CLK_BUFG_BUFGCTRL4_I0": null, + "CLK_BUFG_BUFGCTRL4_I1": null, + "CLK_BUFG_BUFGCTRL4_O": null, + "CLK_BUFG_BUFGCTRL5_I0": null, + "CLK_BUFG_BUFGCTRL5_I1": null, + "CLK_BUFG_BUFGCTRL5_O": null, + "CLK_BUFG_BUFGCTRL6_I0": null, + "CLK_BUFG_BUFGCTRL6_I1": null, + "CLK_BUFG_BUFGCTRL6_O": null, + "CLK_BUFG_BUFGCTRL7_I0": null, + "CLK_BUFG_BUFGCTRL7_I1": null, + "CLK_BUFG_BUFGCTRL7_O": null, + "CLK_BUFG_BUFGCTRL8_I0": null, + "CLK_BUFG_BUFGCTRL8_I1": null, + "CLK_BUFG_BUFGCTRL8_O": null, + "CLK_BUFG_BUFGCTRL9_I0": null, + "CLK_BUFG_BUFGCTRL9_I1": null, + "CLK_BUFG_BUFGCTRL9_O": null, + "CLK_BUFG_CK_GCLK0": null, + "CLK_BUFG_CK_GCLK1": null, + "CLK_BUFG_CK_GCLK10": null, + "CLK_BUFG_CK_GCLK11": null, + "CLK_BUFG_CK_GCLK12": null, + "CLK_BUFG_CK_GCLK13": null, + "CLK_BUFG_CK_GCLK14": null, + "CLK_BUFG_CK_GCLK15": null, + "CLK_BUFG_CK_GCLK16": null, + "CLK_BUFG_CK_GCLK17": null, + "CLK_BUFG_CK_GCLK18": null, + "CLK_BUFG_CK_GCLK19": null, + "CLK_BUFG_CK_GCLK2": null, + "CLK_BUFG_CK_GCLK20": null, + "CLK_BUFG_CK_GCLK21": null, + "CLK_BUFG_CK_GCLK22": null, + "CLK_BUFG_CK_GCLK23": null, + "CLK_BUFG_CK_GCLK24": null, + "CLK_BUFG_CK_GCLK25": null, + "CLK_BUFG_CK_GCLK26": null, + "CLK_BUFG_CK_GCLK27": null, + "CLK_BUFG_CK_GCLK28": null, + "CLK_BUFG_CK_GCLK29": null, + "CLK_BUFG_CK_GCLK3": null, + "CLK_BUFG_CK_GCLK30": null, + "CLK_BUFG_CK_GCLK31": null, + "CLK_BUFG_CK_GCLK4": null, + "CLK_BUFG_CK_GCLK5": null, + "CLK_BUFG_CK_GCLK6": null, + "CLK_BUFG_CK_GCLK7": null, + "CLK_BUFG_CK_GCLK8": null, + "CLK_BUFG_CK_GCLK9": null, + "CLK_BUFG_IMUX0_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX0_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX10_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX11_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX12_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX13_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX14_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX15_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX16_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX17_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX18_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX19_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX1_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX20_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX21_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX22_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX23_3": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_0": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_1": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_2": { + "cap": "25.974", + "res": "0.000" + }, + "CLK_BUFG_IMUX24_3": { + "cap": "25.974", + "res": "0.000" + }, + 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"CLK_BUFG_R_BUFGCTRL14_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL14_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL14_S0": null, + "CLK_BUFG_R_BUFGCTRL14_S1": null, + "CLK_BUFG_R_BUFGCTRL15_CE0": null, + "CLK_BUFG_R_BUFGCTRL15_CE1": null, + "CLK_BUFG_R_BUFGCTRL15_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL15_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL15_S0": null, + "CLK_BUFG_R_BUFGCTRL15_S1": null, + "CLK_BUFG_R_BUFGCTRL1_CE0": null, + "CLK_BUFG_R_BUFGCTRL1_CE1": null, + "CLK_BUFG_R_BUFGCTRL1_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL1_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL1_S0": null, + "CLK_BUFG_R_BUFGCTRL1_S1": null, + "CLK_BUFG_R_BUFGCTRL2_CE0": null, + "CLK_BUFG_R_BUFGCTRL2_CE1": null, + "CLK_BUFG_R_BUFGCTRL2_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL2_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL2_S0": null, + "CLK_BUFG_R_BUFGCTRL2_S1": null, + "CLK_BUFG_R_BUFGCTRL3_CE0": null, + "CLK_BUFG_R_BUFGCTRL3_CE1": null, + "CLK_BUFG_R_BUFGCTRL3_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL3_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL3_S0": null, + "CLK_BUFG_R_BUFGCTRL3_S1": null, + "CLK_BUFG_R_BUFGCTRL4_CE0": null, + "CLK_BUFG_R_BUFGCTRL4_CE1": null, + "CLK_BUFG_R_BUFGCTRL4_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL4_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL4_S0": null, + "CLK_BUFG_R_BUFGCTRL4_S1": null, + "CLK_BUFG_R_BUFGCTRL5_CE0": null, + "CLK_BUFG_R_BUFGCTRL5_CE1": null, + "CLK_BUFG_R_BUFGCTRL5_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL5_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL5_S0": null, + "CLK_BUFG_R_BUFGCTRL5_S1": null, + "CLK_BUFG_R_BUFGCTRL6_CE0": null, + "CLK_BUFG_R_BUFGCTRL6_CE1": null, + "CLK_BUFG_R_BUFGCTRL6_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL6_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL6_S0": null, + "CLK_BUFG_R_BUFGCTRL6_S1": null, + "CLK_BUFG_R_BUFGCTRL7_CE0": null, + "CLK_BUFG_R_BUFGCTRL7_CE1": null, + "CLK_BUFG_R_BUFGCTRL7_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL7_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL7_S0": null, + "CLK_BUFG_R_BUFGCTRL7_S1": null, + "CLK_BUFG_R_BUFGCTRL8_CE0": null, + "CLK_BUFG_R_BUFGCTRL8_CE1": null, + "CLK_BUFG_R_BUFGCTRL8_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL8_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL8_S0": null, + "CLK_BUFG_R_BUFGCTRL8_S1": null, + "CLK_BUFG_R_BUFGCTRL9_CE0": null, + "CLK_BUFG_R_BUFGCTRL9_CE1": null, + "CLK_BUFG_R_BUFGCTRL9_IGNORE0": null, + "CLK_BUFG_R_BUFGCTRL9_IGNORE1": null, + "CLK_BUFG_R_BUFGCTRL9_S0": null, + "CLK_BUFG_R_BUFGCTRL9_S1": null, + "CLK_BUFG_R_CK_FB_TEST0_0": null, + "CLK_BUFG_R_CK_FB_TEST0_1": null, + "CLK_BUFG_R_CK_FB_TEST0_10": null, + "CLK_BUFG_R_CK_FB_TEST0_11": null, + "CLK_BUFG_R_CK_FB_TEST0_12": null, + "CLK_BUFG_R_CK_FB_TEST0_13": null, + "CLK_BUFG_R_CK_FB_TEST0_14": null, + "CLK_BUFG_R_CK_FB_TEST0_15": null, + "CLK_BUFG_R_CK_FB_TEST0_2": null, + "CLK_BUFG_R_CK_FB_TEST0_3": null, + "CLK_BUFG_R_CK_FB_TEST0_4": null, + "CLK_BUFG_R_CK_FB_TEST0_5": null, + "CLK_BUFG_R_CK_FB_TEST0_6": null, + "CLK_BUFG_R_CK_FB_TEST0_7": null, + "CLK_BUFG_R_CK_FB_TEST0_8": null, + "CLK_BUFG_R_CK_FB_TEST0_9": null, + "CLK_BUFG_R_CK_FB_TEST1_0": null, + "CLK_BUFG_R_CK_FB_TEST1_1": null, + "CLK_BUFG_R_CK_FB_TEST1_10": null, + "CLK_BUFG_R_CK_FB_TEST1_11": null, + "CLK_BUFG_R_CK_FB_TEST1_12": null, + "CLK_BUFG_R_CK_FB_TEST1_13": null, + "CLK_BUFG_R_CK_FB_TEST1_14": null, + "CLK_BUFG_R_CK_FB_TEST1_15": null, + "CLK_BUFG_R_CK_FB_TEST1_2": null, + "CLK_BUFG_R_CK_FB_TEST1_3": null, + "CLK_BUFG_R_CK_FB_TEST1_4": null, + "CLK_BUFG_R_CK_FB_TEST1_5": null, + "CLK_BUFG_R_CK_FB_TEST1_6": null, + "CLK_BUFG_R_CK_FB_TEST1_7": null, + "CLK_BUFG_R_CK_FB_TEST1_8": null, + "CLK_BUFG_R_CK_FB_TEST1_9": null, + "CLK_BUFG_R_FBG_OUT0": null, + "CLK_BUFG_R_FBG_OUT1": null, + "CLK_BUFG_R_FBG_OUT10": null, + "CLK_BUFG_R_FBG_OUT11": null, + "CLK_BUFG_R_FBG_OUT12": null, + "CLK_BUFG_R_FBG_OUT13": null, + "CLK_BUFG_R_FBG_OUT14": null, + "CLK_BUFG_R_FBG_OUT15": null, + "CLK_BUFG_R_FBG_OUT2": null, + "CLK_BUFG_R_FBG_OUT3": null, + "CLK_BUFG_R_FBG_OUT4": null, + "CLK_BUFG_R_FBG_OUT5": null, + "CLK_BUFG_R_FBG_OUT6": null, + "CLK_BUFG_R_FBG_OUT7": null, + "CLK_BUFG_R_FBG_OUT8": null, + "CLK_BUFG_R_FBG_OUT9": null, + "CLK_BUFG_TOP_R_CK_MUXED0": null, + "CLK_BUFG_TOP_R_CK_MUXED1": null, + "CLK_BUFG_TOP_R_CK_MUXED10": null, + "CLK_BUFG_TOP_R_CK_MUXED11": null, + "CLK_BUFG_TOP_R_CK_MUXED12": null, + "CLK_BUFG_TOP_R_CK_MUXED13": null, + "CLK_BUFG_TOP_R_CK_MUXED14": null, + "CLK_BUFG_TOP_R_CK_MUXED15": null, + "CLK_BUFG_TOP_R_CK_MUXED16": null, + "CLK_BUFG_TOP_R_CK_MUXED17": null, + "CLK_BUFG_TOP_R_CK_MUXED18": null, + "CLK_BUFG_TOP_R_CK_MUXED19": null, + "CLK_BUFG_TOP_R_CK_MUXED2": null, + "CLK_BUFG_TOP_R_CK_MUXED20": null, + "CLK_BUFG_TOP_R_CK_MUXED21": null, + "CLK_BUFG_TOP_R_CK_MUXED22": null, + "CLK_BUFG_TOP_R_CK_MUXED23": null, + "CLK_BUFG_TOP_R_CK_MUXED24": null, + "CLK_BUFG_TOP_R_CK_MUXED25": null, + "CLK_BUFG_TOP_R_CK_MUXED26": null, + "CLK_BUFG_TOP_R_CK_MUXED27": null, + "CLK_BUFG_TOP_R_CK_MUXED28": null, + "CLK_BUFG_TOP_R_CK_MUXED29": null, + "CLK_BUFG_TOP_R_CK_MUXED3": null, + "CLK_BUFG_TOP_R_CK_MUXED30": null, + "CLK_BUFG_TOP_R_CK_MUXED31": null, + "CLK_BUFG_TOP_R_CK_MUXED4": null, + "CLK_BUFG_TOP_R_CK_MUXED5": null, + "CLK_BUFG_TOP_R_CK_MUXED6": null, + "CLK_BUFG_TOP_R_CK_MUXED7": null, + "CLK_BUFG_TOP_R_CK_MUXED8": null, + "CLK_BUFG_TOP_R_CK_MUXED9": null, + "CLK_HROW_BLOCK_OUTS_B0_0": null, + "CLK_HROW_BLOCK_OUTS_B0_1": null, + "CLK_HROW_BLOCK_OUTS_B0_2": null, + "CLK_HROW_BLOCK_OUTS_B0_3": null, + "CLK_HROW_BLOCK_OUTS_B1_0": null, + "CLK_HROW_BLOCK_OUTS_B1_1": null, + "CLK_HROW_BLOCK_OUTS_B1_2": null, + "CLK_HROW_BLOCK_OUTS_B1_3": null, + "CLK_HROW_BLOCK_OUTS_B2_0": null, + "CLK_HROW_BLOCK_OUTS_B2_1": null, + "CLK_HROW_BLOCK_OUTS_B2_2": null, + "CLK_HROW_BLOCK_OUTS_B2_3": null, + "CLK_HROW_BLOCK_OUTS_B3_0": null, + "CLK_HROW_BLOCK_OUTS_B3_1": null, + "CLK_HROW_BLOCK_OUTS_B3_2": null, + "CLK_HROW_BLOCK_OUTS_B3_3": null, + "CLK_HROW_BYP0_0": null, + "CLK_HROW_BYP0_1": null, + "CLK_HROW_BYP0_2": null, + "CLK_HROW_BYP0_3": null, + "CLK_HROW_BYP1_0": null, + "CLK_HROW_BYP1_1": null, + "CLK_HROW_BYP1_2": null, + "CLK_HROW_BYP1_3": null, + "CLK_HROW_BYP2_0": null, + "CLK_HROW_BYP2_1": null, + "CLK_HROW_BYP2_2": null, + "CLK_HROW_BYP2_3": null, + "CLK_HROW_BYP3_0": null, + "CLK_HROW_BYP3_1": null, + "CLK_HROW_BYP3_2": null, + "CLK_HROW_BYP3_3": null, + "CLK_HROW_BYP4_0": null, + "CLK_HROW_BYP4_1": null, + "CLK_HROW_BYP4_2": null, + "CLK_HROW_BYP4_3": null, + "CLK_HROW_BYP5_0": null, + "CLK_HROW_BYP5_1": null, + "CLK_HROW_BYP5_2": null, + "CLK_HROW_BYP5_3": null, + "CLK_HROW_BYP6_0": null, + "CLK_HROW_BYP6_1": null, + "CLK_HROW_BYP6_2": null, + "CLK_HROW_BYP6_3": null, + "CLK_HROW_BYP7_0": null, + "CLK_HROW_BYP7_1": null, + "CLK_HROW_BYP7_2": null, + "CLK_HROW_BYP7_3": null, + "CLK_HROW_CLK0_0": { + "cap": "11.383", + "res": "0.000" + }, + "CLK_HROW_CLK0_1": { + "cap": "11.383", + "res": "0.000" + }, + "CLK_HROW_CLK0_2": { + "cap": "11.383", + "res": "0.000" + }, + "CLK_HROW_CLK0_3": { + "cap": "11.383", + "res": "0.000" + }, + "CLK_HROW_CLK1_0": { + "cap": "11.383", + "res": "0.000" + }, + "CLK_HROW_CLK1_1": { + "cap": "11.383", + "res": "0.000" + }, + "CLK_HROW_CLK1_2": { + "cap": "11.383", + "res": "0.000" + }, + "CLK_HROW_CLK1_3": { + "cap": "11.383", + "res": "0.000" + }, + "CLK_HROW_CTRL0_0": null, + "CLK_HROW_CTRL0_1": null, + "CLK_HROW_CTRL0_2": null, + "CLK_HROW_CTRL0_3": null, + "CLK_HROW_CTRL1_0": null, + "CLK_HROW_CTRL1_1": null, + "CLK_HROW_CTRL1_2": null, + "CLK_HROW_CTRL1_3": null, + "CLK_HROW_EE2A0_0": null, + "CLK_HROW_EE2A0_1": null, + "CLK_HROW_EE2A0_2": null, + "CLK_HROW_EE2A0_3": null, + "CLK_HROW_EE2A1_0": null, + "CLK_HROW_EE2A1_1": null, + "CLK_HROW_EE2A1_2": null, + "CLK_HROW_EE2A1_3": null, + "CLK_HROW_EE2A2_0": null, + "CLK_HROW_EE2A2_1": null, + "CLK_HROW_EE2A2_2": null, + "CLK_HROW_EE2A2_3": null, + "CLK_HROW_EE2A3_0": null, + "CLK_HROW_EE2A3_1": null, + "CLK_HROW_EE2A3_2": null, + "CLK_HROW_EE2A3_3": null, + "CLK_HROW_EE2BEG0_0": null, + "CLK_HROW_EE2BEG0_1": null, + "CLK_HROW_EE2BEG0_2": null, + "CLK_HROW_EE2BEG0_3": null, + "CLK_HROW_EE2BEG1_0": null, + "CLK_HROW_EE2BEG1_1": null, + "CLK_HROW_EE2BEG1_2": null, + "CLK_HROW_EE2BEG1_3": null, + "CLK_HROW_EE2BEG2_0": null, + "CLK_HROW_EE2BEG2_1": null, + "CLK_HROW_EE2BEG2_2": null, + "CLK_HROW_EE2BEG2_3": null, + "CLK_HROW_EE2BEG3_0": null, + "CLK_HROW_EE2BEG3_1": null, + "CLK_HROW_EE2BEG3_2": null, + "CLK_HROW_EE2BEG3_3": null, + "CLK_HROW_EE4A0_0": null, + "CLK_HROW_EE4A0_1": null, + "CLK_HROW_EE4A0_2": null, + "CLK_HROW_EE4A0_3": null, + "CLK_HROW_EE4A1_0": null, + "CLK_HROW_EE4A1_1": null, + "CLK_HROW_EE4A1_2": null, + "CLK_HROW_EE4A1_3": null, + "CLK_HROW_EE4A2_0": null, + "CLK_HROW_EE4A2_1": null, + "CLK_HROW_EE4A2_2": null, + "CLK_HROW_EE4A2_3": null, + "CLK_HROW_EE4A3_0": null, + "CLK_HROW_EE4A3_1": null, + "CLK_HROW_EE4A3_2": null, + "CLK_HROW_EE4A3_3": null, + "CLK_HROW_EE4B0_0": null, + "CLK_HROW_EE4B0_1": null, + "CLK_HROW_EE4B0_2": null, + "CLK_HROW_EE4B0_3": null, + "CLK_HROW_EE4B1_0": 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"CLK_HROW_EE4C1_3": null, + "CLK_HROW_EE4C2_0": null, + "CLK_HROW_EE4C2_1": null, + "CLK_HROW_EE4C2_2": null, + "CLK_HROW_EE4C2_3": null, + "CLK_HROW_EE4C3_0": null, + "CLK_HROW_EE4C3_1": null, + "CLK_HROW_EE4C3_2": null, + "CLK_HROW_EE4C3_3": null, + "CLK_HROW_EL1BEG0_0": null, + "CLK_HROW_EL1BEG0_1": null, + "CLK_HROW_EL1BEG0_2": null, + "CLK_HROW_EL1BEG0_3": null, + "CLK_HROW_EL1BEG1_0": null, + "CLK_HROW_EL1BEG1_1": null, + "CLK_HROW_EL1BEG1_2": null, + "CLK_HROW_EL1BEG1_3": null, + "CLK_HROW_EL1BEG2_0": null, + "CLK_HROW_EL1BEG2_1": null, + "CLK_HROW_EL1BEG2_2": null, + "CLK_HROW_EL1BEG2_3": null, + "CLK_HROW_EL1BEG3_0": null, + "CLK_HROW_EL1BEG3_1": null, + "CLK_HROW_EL1BEG3_2": null, + "CLK_HROW_EL1BEG3_3": null, + "CLK_HROW_ER1BEG0_0": null, + "CLK_HROW_ER1BEG0_1": null, + "CLK_HROW_ER1BEG0_2": null, + "CLK_HROW_ER1BEG0_3": null, + "CLK_HROW_ER1BEG1_0": null, + "CLK_HROW_ER1BEG1_1": null, + "CLK_HROW_ER1BEG1_2": null, + "CLK_HROW_ER1BEG1_3": null, + "CLK_HROW_ER1BEG2_0": null, + "CLK_HROW_ER1BEG2_1": null, + "CLK_HROW_ER1BEG2_2": null, + "CLK_HROW_ER1BEG2_3": null, + "CLK_HROW_ER1BEG3_0": null, + "CLK_HROW_ER1BEG3_1": null, + "CLK_HROW_ER1BEG3_2": null, + "CLK_HROW_ER1BEG3_3": null, + "CLK_HROW_FAN0_0": null, + "CLK_HROW_FAN0_1": null, + "CLK_HROW_FAN0_2": null, + "CLK_HROW_FAN0_3": null, + "CLK_HROW_FAN1_0": null, + "CLK_HROW_FAN1_1": null, + "CLK_HROW_FAN1_2": null, + "CLK_HROW_FAN1_3": null, + "CLK_HROW_FAN2_0": null, + "CLK_HROW_FAN2_1": null, + "CLK_HROW_FAN2_2": null, + "CLK_HROW_FAN2_3": null, + "CLK_HROW_FAN3_0": null, + "CLK_HROW_FAN3_1": null, + "CLK_HROW_FAN3_2": null, + "CLK_HROW_FAN3_3": null, + "CLK_HROW_FAN4_0": null, + "CLK_HROW_FAN4_1": null, + "CLK_HROW_FAN4_2": null, + "CLK_HROW_FAN4_3": null, + "CLK_HROW_FAN5_0": null, + "CLK_HROW_FAN5_1": null, + "CLK_HROW_FAN5_2": null, + "CLK_HROW_FAN5_3": null, + "CLK_HROW_FAN6_0": null, + "CLK_HROW_FAN6_1": null, + "CLK_HROW_FAN6_2": null, + "CLK_HROW_FAN6_3": null, + "CLK_HROW_FAN7_0": null, + "CLK_HROW_FAN7_1": null, + "CLK_HROW_FAN7_2": null, + "CLK_HROW_FAN7_3": null, + "CLK_HROW_LH10_0": null, + "CLK_HROW_LH10_1": null, + "CLK_HROW_LH10_2": null, + "CLK_HROW_LH10_3": null, + "CLK_HROW_LH11_0": null, + "CLK_HROW_LH11_1": null, + "CLK_HROW_LH11_2": null, + "CLK_HROW_LH11_3": null, + "CLK_HROW_LH12_0": null, + "CLK_HROW_LH12_1": null, + "CLK_HROW_LH12_2": null, + "CLK_HROW_LH12_3": null, + "CLK_HROW_LH1_0": null, + "CLK_HROW_LH1_1": null, + "CLK_HROW_LH1_2": null, + "CLK_HROW_LH1_3": null, + "CLK_HROW_LH2_0": null, + "CLK_HROW_LH2_1": null, + "CLK_HROW_LH2_2": null, + "CLK_HROW_LH2_3": null, + "CLK_HROW_LH3_0": null, + "CLK_HROW_LH3_1": null, + "CLK_HROW_LH3_2": null, + "CLK_HROW_LH3_3": null, + "CLK_HROW_LH4_0": null, + "CLK_HROW_LH4_1": null, + "CLK_HROW_LH4_2": null, + "CLK_HROW_LH4_3": null, + "CLK_HROW_LH5_0": null, + "CLK_HROW_LH5_1": null, + "CLK_HROW_LH5_2": null, + "CLK_HROW_LH5_3": null, + "CLK_HROW_LH6_0": null, + "CLK_HROW_LH6_1": null, + "CLK_HROW_LH6_2": null, + "CLK_HROW_LH6_3": null, + "CLK_HROW_LH7_0": null, + "CLK_HROW_LH7_1": null, + "CLK_HROW_LH7_2": null, + "CLK_HROW_LH7_3": null, + "CLK_HROW_LH8_0": null, + "CLK_HROW_LH8_1": null, + "CLK_HROW_LH8_2": null, + "CLK_HROW_LH8_3": null, + "CLK_HROW_LH9_0": null, + "CLK_HROW_LH9_1": null, + "CLK_HROW_LH9_2": null, + "CLK_HROW_LH9_3": null, + "CLK_HROW_MONITOR_N_0": null, + "CLK_HROW_MONITOR_N_1": null, + "CLK_HROW_MONITOR_N_2": null, + "CLK_HROW_MONITOR_N_3": null, + "CLK_HROW_MONITOR_P_0": null, + "CLK_HROW_MONITOR_P_1": null, + "CLK_HROW_MONITOR_P_2": null, + "CLK_HROW_MONITOR_P_3": null, + "CLK_HROW_NE2A0_0": null, + "CLK_HROW_NE2A0_1": null, + "CLK_HROW_NE2A0_2": null, + "CLK_HROW_NE2A0_3": null, + "CLK_HROW_NE2A1_0": null, + "CLK_HROW_NE2A1_1": null, + "CLK_HROW_NE2A1_2": null, + "CLK_HROW_NE2A1_3": null, + "CLK_HROW_NE2A2_0": null, + "CLK_HROW_NE2A2_1": null, + "CLK_HROW_NE2A2_2": null, + "CLK_HROW_NE2A2_3": null, + "CLK_HROW_NE2A3_0": null, + "CLK_HROW_NE2A3_1": null, + "CLK_HROW_NE2A3_2": null, + "CLK_HROW_NE2A3_3": null, + "CLK_HROW_NE4BEG0_0": null, + "CLK_HROW_NE4BEG0_1": null, + "CLK_HROW_NE4BEG0_2": null, + "CLK_HROW_NE4BEG0_3": null, + "CLK_HROW_NE4BEG1_0": null, + "CLK_HROW_NE4BEG1_1": null, + "CLK_HROW_NE4BEG1_2": null, + "CLK_HROW_NE4BEG1_3": null, + "CLK_HROW_NE4BEG2_0": null, + "CLK_HROW_NE4BEG2_1": null, + "CLK_HROW_NE4BEG2_2": null, + "CLK_HROW_NE4BEG2_3": null, + "CLK_HROW_NE4BEG3_0": null, + "CLK_HROW_NE4BEG3_1": null, + "CLK_HROW_NE4BEG3_2": null, + "CLK_HROW_NE4BEG3_3": null, + "CLK_HROW_NE4C0_0": null, + "CLK_HROW_NE4C0_1": null, + "CLK_HROW_NE4C0_2": null, + "CLK_HROW_NE4C0_3": null, + "CLK_HROW_NE4C1_0": null, + "CLK_HROW_NE4C1_1": null, + "CLK_HROW_NE4C1_2": null, + "CLK_HROW_NE4C1_3": null, + "CLK_HROW_NE4C2_0": null, + "CLK_HROW_NE4C2_1": null, + "CLK_HROW_NE4C2_2": null, + "CLK_HROW_NE4C2_3": null, + "CLK_HROW_NE4C3_0": null, + "CLK_HROW_NE4C3_1": null, + "CLK_HROW_NE4C3_2": null, + "CLK_HROW_NE4C3_3": null, + "CLK_HROW_NW2A0_0": null, + "CLK_HROW_NW2A0_1": null, + "CLK_HROW_NW2A0_2": null, + "CLK_HROW_NW2A0_3": null, + "CLK_HROW_NW2A1_0": null, + "CLK_HROW_NW2A1_1": null, + "CLK_HROW_NW2A1_2": null, + "CLK_HROW_NW2A1_3": null, + "CLK_HROW_NW2A2_0": null, + "CLK_HROW_NW2A2_1": null, + "CLK_HROW_NW2A2_2": null, + "CLK_HROW_NW2A2_3": null, + "CLK_HROW_NW2A3_0": null, + "CLK_HROW_NW2A3_1": null, + "CLK_HROW_NW2A3_2": null, + "CLK_HROW_NW2A3_3": null, + "CLK_HROW_NW4A0_0": null, + "CLK_HROW_NW4A0_1": null, + "CLK_HROW_NW4A0_2": null, + "CLK_HROW_NW4A0_3": null, + "CLK_HROW_NW4A1_0": null, + "CLK_HROW_NW4A1_1": null, + "CLK_HROW_NW4A1_2": null, + "CLK_HROW_NW4A1_3": null, + "CLK_HROW_NW4A2_0": null, + "CLK_HROW_NW4A2_1": null, + "CLK_HROW_NW4A2_2": null, + "CLK_HROW_NW4A2_3": null, + "CLK_HROW_NW4A3_0": null, + "CLK_HROW_NW4A3_1": null, + "CLK_HROW_NW4A3_2": null, + "CLK_HROW_NW4A3_3": null, + "CLK_HROW_NW4END0_0": null, + "CLK_HROW_NW4END0_1": null, + "CLK_HROW_NW4END0_2": null, + "CLK_HROW_NW4END0_3": null, + "CLK_HROW_NW4END1_0": null, + "CLK_HROW_NW4END1_1": null, + "CLK_HROW_NW4END1_2": null, + "CLK_HROW_NW4END1_3": null, + "CLK_HROW_NW4END2_0": null, + "CLK_HROW_NW4END2_1": null, + "CLK_HROW_NW4END2_2": null, + "CLK_HROW_NW4END2_3": null, + "CLK_HROW_NW4END3_0": null, + "CLK_HROW_NW4END3_1": null, + "CLK_HROW_NW4END3_2": null, + "CLK_HROW_NW4END3_3": null, + "CLK_HROW_SE2A0_0": null, + "CLK_HROW_SE2A0_1": null, + "CLK_HROW_SE2A0_2": null, + "CLK_HROW_SE2A0_3": null, + "CLK_HROW_SE2A1_0": null, + "CLK_HROW_SE2A1_1": null, + "CLK_HROW_SE2A1_2": null, + "CLK_HROW_SE2A1_3": null, + "CLK_HROW_SE2A2_0": null, + "CLK_HROW_SE2A2_1": null, + "CLK_HROW_SE2A2_2": null, + "CLK_HROW_SE2A2_3": null, + "CLK_HROW_SE2A3_0": null, + "CLK_HROW_SE2A3_1": null, + "CLK_HROW_SE2A3_2": null, + "CLK_HROW_SE2A3_3": null, + "CLK_HROW_SE4BEG0_0": null, + "CLK_HROW_SE4BEG0_1": null, + "CLK_HROW_SE4BEG0_2": null, + "CLK_HROW_SE4BEG0_3": null, + "CLK_HROW_SE4BEG1_0": null, + "CLK_HROW_SE4BEG1_1": null, + "CLK_HROW_SE4BEG1_2": null, + "CLK_HROW_SE4BEG1_3": null, + "CLK_HROW_SE4BEG2_0": null, + "CLK_HROW_SE4BEG2_1": null, + "CLK_HROW_SE4BEG2_2": null, + "CLK_HROW_SE4BEG2_3": null, + "CLK_HROW_SE4BEG3_0": null, + "CLK_HROW_SE4BEG3_1": null, + "CLK_HROW_SE4BEG3_2": null, + "CLK_HROW_SE4BEG3_3": null, + "CLK_HROW_SE4C0_0": null, + "CLK_HROW_SE4C0_1": null, + "CLK_HROW_SE4C0_2": null, + "CLK_HROW_SE4C0_3": null, + "CLK_HROW_SE4C1_0": null, + "CLK_HROW_SE4C1_1": null, + "CLK_HROW_SE4C1_2": null, + "CLK_HROW_SE4C1_3": null, + "CLK_HROW_SE4C2_0": null, + "CLK_HROW_SE4C2_1": null, + "CLK_HROW_SE4C2_2": null, + "CLK_HROW_SE4C2_3": null, + "CLK_HROW_SE4C3_0": null, + "CLK_HROW_SE4C3_1": null, + "CLK_HROW_SE4C3_2": null, + "CLK_HROW_SE4C3_3": null, + "CLK_HROW_SW2A0_0": null, + "CLK_HROW_SW2A0_1": null, + "CLK_HROW_SW2A0_2": null, + "CLK_HROW_SW2A0_3": null, + "CLK_HROW_SW2A1_0": null, + "CLK_HROW_SW2A1_1": null, + "CLK_HROW_SW2A1_2": null, + "CLK_HROW_SW2A1_3": null, + "CLK_HROW_SW2A2_0": null, + "CLK_HROW_SW2A2_1": null, + "CLK_HROW_SW2A2_2": null, + "CLK_HROW_SW2A2_3": null, + "CLK_HROW_SW2A3_0": null, + "CLK_HROW_SW2A3_1": null, + "CLK_HROW_SW2A3_2": null, + "CLK_HROW_SW2A3_3": null, + "CLK_HROW_SW4A0_0": null, + "CLK_HROW_SW4A0_1": null, + "CLK_HROW_SW4A0_2": null, + "CLK_HROW_SW4A0_3": null, + "CLK_HROW_SW4A1_0": null, + "CLK_HROW_SW4A1_1": null, + "CLK_HROW_SW4A1_2": null, + "CLK_HROW_SW4A1_3": null, + "CLK_HROW_SW4A2_0": null, + "CLK_HROW_SW4A2_1": null, + "CLK_HROW_SW4A2_2": null, + "CLK_HROW_SW4A2_3": null, + "CLK_HROW_SW4A3_0": null, + "CLK_HROW_SW4A3_1": null, + "CLK_HROW_SW4A3_2": null, + "CLK_HROW_SW4A3_3": null, + "CLK_HROW_SW4END0_0": null, + "CLK_HROW_SW4END0_1": null, + "CLK_HROW_SW4END0_2": null, + "CLK_HROW_SW4END0_3": null, + "CLK_HROW_SW4END1_0": null, + "CLK_HROW_SW4END1_1": null, + "CLK_HROW_SW4END1_2": null, + "CLK_HROW_SW4END1_3": null, + "CLK_HROW_SW4END2_0": null, + "CLK_HROW_SW4END2_1": null, + "CLK_HROW_SW4END2_2": null, + "CLK_HROW_SW4END2_3": null, + "CLK_HROW_SW4END3_0": null, + "CLK_HROW_SW4END3_1": null, + "CLK_HROW_SW4END3_2": null, + "CLK_HROW_SW4END3_3": null, + "CLK_HROW_WL1END0_0": null, + "CLK_HROW_WL1END0_1": null, + "CLK_HROW_WL1END0_2": null, + "CLK_HROW_WL1END0_3": null, + "CLK_HROW_WL1END1_0": null, + "CLK_HROW_WL1END1_1": null, + "CLK_HROW_WL1END1_2": null, + "CLK_HROW_WL1END1_3": null, + "CLK_HROW_WL1END2_0": null, + "CLK_HROW_WL1END2_1": null, + "CLK_HROW_WL1END2_2": null, + "CLK_HROW_WL1END2_3": null, + "CLK_HROW_WL1END3_0": null, + "CLK_HROW_WL1END3_1": null, + "CLK_HROW_WL1END3_2": null, + "CLK_HROW_WL1END3_3": null, + "CLK_HROW_WR1END0_0": null, + "CLK_HROW_WR1END0_1": null, + "CLK_HROW_WR1END0_2": null, + "CLK_HROW_WR1END0_3": null, + "CLK_HROW_WR1END1_0": null, + "CLK_HROW_WR1END1_1": null, + "CLK_HROW_WR1END1_2": null, + "CLK_HROW_WR1END1_3": null, + "CLK_HROW_WR1END2_0": null, + "CLK_HROW_WR1END2_1": null, + "CLK_HROW_WR1END2_2": null, + "CLK_HROW_WR1END2_3": null, + "CLK_HROW_WR1END3_0": null, + "CLK_HROW_WR1END3_1": null, + "CLK_HROW_WR1END3_2": null, + "CLK_HROW_WR1END3_3": null, + "CLK_HROW_WW2A0_0": null, + "CLK_HROW_WW2A0_1": null, + "CLK_HROW_WW2A0_2": null, + "CLK_HROW_WW2A0_3": null, + "CLK_HROW_WW2A1_0": null, + "CLK_HROW_WW2A1_1": null, + "CLK_HROW_WW2A1_2": null, + "CLK_HROW_WW2A1_3": null, + "CLK_HROW_WW2A2_0": null, + "CLK_HROW_WW2A2_1": null, + "CLK_HROW_WW2A2_2": null, + "CLK_HROW_WW2A2_3": null, + "CLK_HROW_WW2A3_0": null, + "CLK_HROW_WW2A3_1": null, + "CLK_HROW_WW2A3_2": null, + "CLK_HROW_WW2A3_3": null, + "CLK_HROW_WW2END0_0": null, + "CLK_HROW_WW2END0_1": null, + "CLK_HROW_WW2END0_2": null, + "CLK_HROW_WW2END0_3": null, + "CLK_HROW_WW2END1_0": null, + "CLK_HROW_WW2END1_1": null, + "CLK_HROW_WW2END1_2": null, + "CLK_HROW_WW2END1_3": null, + "CLK_HROW_WW2END2_0": null, + "CLK_HROW_WW2END2_1": null, + "CLK_HROW_WW2END2_2": null, + "CLK_HROW_WW2END2_3": null, + "CLK_HROW_WW2END3_0": null, + "CLK_HROW_WW2END3_1": null, + "CLK_HROW_WW2END3_2": null, + "CLK_HROW_WW2END3_3": null, + "CLK_HROW_WW4A0_0": null, + "CLK_HROW_WW4A0_1": null, + "CLK_HROW_WW4A0_2": null, + "CLK_HROW_WW4A0_3": null, + "CLK_HROW_WW4A1_0": null, + "CLK_HROW_WW4A1_1": null, + "CLK_HROW_WW4A1_2": null, + "CLK_HROW_WW4A1_3": null, + "CLK_HROW_WW4A2_0": null, + "CLK_HROW_WW4A2_1": null, + "CLK_HROW_WW4A2_2": null, + "CLK_HROW_WW4A2_3": null, + "CLK_HROW_WW4A3_0": null, + "CLK_HROW_WW4A3_1": null, + "CLK_HROW_WW4A3_2": null, + "CLK_HROW_WW4A3_3": null, + "CLK_HROW_WW4B0_0": null, + "CLK_HROW_WW4B0_1": null, + "CLK_HROW_WW4B0_2": null, + "CLK_HROW_WW4B0_3": null, + "CLK_HROW_WW4B1_0": null, + "CLK_HROW_WW4B1_1": null, + "CLK_HROW_WW4B1_2": null, + "CLK_HROW_WW4B1_3": null, + "CLK_HROW_WW4B2_0": null, + "CLK_HROW_WW4B2_1": null, + "CLK_HROW_WW4B2_2": null, + "CLK_HROW_WW4B2_3": null, + "CLK_HROW_WW4B3_0": null, + "CLK_HROW_WW4B3_1": null, + "CLK_HROW_WW4B3_2": null, + "CLK_HROW_WW4B3_3": null, + "CLK_HROW_WW4C0_0": null, + "CLK_HROW_WW4C0_1": null, + "CLK_HROW_WW4C0_2": null, + "CLK_HROW_WW4C0_3": null, + "CLK_HROW_WW4C1_0": null, + "CLK_HROW_WW4C1_1": null, + "CLK_HROW_WW4C1_2": null, + "CLK_HROW_WW4C1_3": null, + "CLK_HROW_WW4C2_0": null, + "CLK_HROW_WW4C2_1": null, + "CLK_HROW_WW4C2_2": null, + "CLK_HROW_WW4C2_3": null, + "CLK_HROW_WW4C3_0": null, + "CLK_HROW_WW4C3_1": null, + "CLK_HROW_WW4C3_2": null, + "CLK_HROW_WW4C3_3": null, + "CLK_HROW_WW4END0_0": null, + "CLK_HROW_WW4END0_1": null, + "CLK_HROW_WW4END0_2": null, + "CLK_HROW_WW4END0_3": null, + "CLK_HROW_WW4END1_0": null, + "CLK_HROW_WW4END1_1": null, + "CLK_HROW_WW4END1_2": null, + "CLK_HROW_WW4END1_3": null, + "CLK_HROW_WW4END2_0": null, + "CLK_HROW_WW4END2_1": null, + "CLK_HROW_WW4END2_2": null, + "CLK_HROW_WW4END2_3": null, + "CLK_HROW_WW4END3_0": null, + "CLK_HROW_WW4END3_1": null, + "CLK_HROW_WW4END3_2": null, + "CLK_HROW_WW4END3_3": null + } } diff --git a/kintex7/tile_type_CLK_FEED.json b/kintex7/tile_type_CLK_FEED.json index f9b8b57..d4e1f1b 100644 --- a/kintex7/tile_type_CLK_FEED.json +++ b/kintex7/tile_type_CLK_FEED.json @@ -2,260 +2,260 @@ "pips": {}, "sites": [], "tile_type": "CLK_FEED", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null + } } diff --git a/kintex7/tile_type_CLK_HROW_BOT_R.json b/kintex7/tile_type_CLK_HROW_BOT_R.json index 2cd154e..a79bb2d 100644 --- a/kintex7/tile_type_CLK_HROW_BOT_R.json +++ b/kintex7/tile_type_CLK_HROW_BOT_R.json @@ -2,19882 +2,78562 @@ "pips": { "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN0" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN1" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN10" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN11" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN12" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN13" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN14->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN14" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN15->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN15" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN16->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN16" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN17->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN17" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN18->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN18" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN19->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN19" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN2" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN20->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN20" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN21->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN21" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN22->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN22" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN23->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN23" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN24->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN24" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN25->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN25" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN26->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN26" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN27->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN27" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN28->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN28" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN29->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN29" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN3" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN30->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN30" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN31->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN31" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN4" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN5" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN6" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN7" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN8" }, "CLK_HROW_BOT_R.CLK_HROW_BOT_R_CK_BUFG_CASCIN9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.187", + "0.189", + "0.331", + "0.339" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCIN9" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT0" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT1" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT10" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT11" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT2" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT3" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT4" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT5" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT6" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT7" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT8" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT9" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP0" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP1" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP10" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP11" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP2" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP3" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP4" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP5" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP6" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP7" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP8" }, "CLK_HROW_BOT_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_L_TEST_IN" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_BOT_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BOT_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST" }, "CLK_HROW_BOT_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_R_TEST_IN" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L9" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R0" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R1" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R10" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R11" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R2" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R3" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R4" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R5" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R6" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R7" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R8" }, "CLK_HROW_BOT_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R9" }, "CLK_HROW_BOT_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK0_3" }, "CLK_HROW_BOT_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK0_4" }, "CLK_HROW_BOT_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK1_3" }, "CLK_HROW_BOT_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK1_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX0_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX0_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX10_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX10_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX11_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX11_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX1_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX1_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX2_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX2_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX3_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX3_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX4_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX4_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX5_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX5_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX6_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX6_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX7_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX7_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX8_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX8_4" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX9_3" }, "CLK_HROW_BOT_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX9_4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_BOT_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" } }, @@ -19886,9 +78566,36 @@ "name": "X0Y0", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L0", - "I": "CLK_HROW_CK_MUX_OUT_L0", - "O": "CLK_HROW_CK_HCLK_OUT_L0" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L0" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19898,9 +78605,36 @@ "name": "X0Y1", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L1", - "I": "CLK_HROW_CK_MUX_OUT_L1", - "O": "CLK_HROW_CK_HCLK_OUT_L1" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L1" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19910,9 +78644,36 @@ "name": "X0Y2", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L2", - "I": "CLK_HROW_CK_MUX_OUT_L2", - "O": "CLK_HROW_CK_HCLK_OUT_L2" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L2" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L2" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19922,9 +78683,36 @@ "name": "X0Y3", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L3", - "I": "CLK_HROW_CK_MUX_OUT_L3", - "O": "CLK_HROW_CK_HCLK_OUT_L3" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L3" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L3" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19934,9 +78722,36 @@ "name": "X0Y4", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L4", - "I": "CLK_HROW_CK_MUX_OUT_L4", - "O": "CLK_HROW_CK_HCLK_OUT_L4" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L4" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L4" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19946,9 +78761,36 @@ "name": "X0Y5", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L5", - "I": "CLK_HROW_CK_MUX_OUT_L5", - "O": "CLK_HROW_CK_HCLK_OUT_L5" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L5" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L5" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19958,9 +78800,36 @@ "name": "X0Y6", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L6", - "I": "CLK_HROW_CK_MUX_OUT_L6", - "O": "CLK_HROW_CK_HCLK_OUT_L6" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L6" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L6" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19970,9 +78839,36 @@ "name": "X0Y7", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L7", - "I": "CLK_HROW_CK_MUX_OUT_L7", - "O": "CLK_HROW_CK_HCLK_OUT_L7" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L7" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L7" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19982,9 +78878,36 @@ "name": "X0Y8", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L8", - "I": "CLK_HROW_CK_MUX_OUT_L8", - "O": "CLK_HROW_CK_HCLK_OUT_L8" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L8" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L8" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19994,9 +78917,36 @@ "name": "X0Y9", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L9", - "I": "CLK_HROW_CK_MUX_OUT_L9", - "O": "CLK_HROW_CK_HCLK_OUT_L9" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L9" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L9" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20006,9 +78956,36 @@ "name": "X0Y10", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L10", - "I": "CLK_HROW_CK_MUX_OUT_L10", - "O": "CLK_HROW_CK_HCLK_OUT_L10" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L10" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L10" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20018,9 +78995,36 @@ "name": "X0Y11", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L11", - "I": "CLK_HROW_CK_MUX_OUT_L11", - "O": "CLK_HROW_CK_HCLK_OUT_L11" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L11" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L11" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20030,9 +79034,36 @@ "name": "X1Y11", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R11", - "I": "CLK_HROW_CK_MUX_OUT_R11", - "O": "CLK_HROW_CK_HCLK_OUT_R11" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R11" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R11" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20042,9 +79073,36 @@ "name": "X1Y10", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R10", - "I": "CLK_HROW_CK_MUX_OUT_R10", - "O": "CLK_HROW_CK_HCLK_OUT_R10" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R10" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R10" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20054,9 +79112,36 @@ "name": "X1Y9", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R9", - "I": "CLK_HROW_CK_MUX_OUT_R9", - "O": "CLK_HROW_CK_HCLK_OUT_R9" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R9" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R9" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20066,9 +79151,36 @@ "name": "X1Y8", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R8", - "I": "CLK_HROW_CK_MUX_OUT_R8", - "O": "CLK_HROW_CK_HCLK_OUT_R8" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R8" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R8" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20078,9 +79190,36 @@ "name": "X1Y7", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R7", - "I": "CLK_HROW_CK_MUX_OUT_R7", - "O": "CLK_HROW_CK_HCLK_OUT_R7" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R7" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R7" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20090,9 +79229,36 @@ "name": "X1Y6", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R6", - "I": "CLK_HROW_CK_MUX_OUT_R6", - "O": "CLK_HROW_CK_HCLK_OUT_R6" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R6" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R6" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20102,9 +79268,36 @@ "name": "X1Y5", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R5", - "I": "CLK_HROW_CK_MUX_OUT_R5", - "O": "CLK_HROW_CK_HCLK_OUT_R5" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R5" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R5" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20114,9 +79307,36 @@ "name": "X1Y4", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R4", - "I": "CLK_HROW_CK_MUX_OUT_R4", - "O": "CLK_HROW_CK_HCLK_OUT_R4" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R4" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R4" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20126,9 +79346,36 @@ "name": "X1Y3", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R3", - "I": "CLK_HROW_CK_MUX_OUT_R3", - "O": "CLK_HROW_CK_HCLK_OUT_R3" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R3" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R3" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20138,9 +79385,36 @@ "name": "X1Y2", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R2", - "I": "CLK_HROW_CK_MUX_OUT_R2", - "O": "CLK_HROW_CK_HCLK_OUT_R2" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R2" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R2" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20150,9 +79424,36 @@ "name": "X1Y1", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R1", - "I": "CLK_HROW_CK_MUX_OUT_R1", - "O": "CLK_HROW_CK_HCLK_OUT_R1" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R1" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20162,9 +79463,36 @@ "name": "X1Y0", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R0", - "I": "CLK_HROW_CK_MUX_OUT_R0", - "O": "CLK_HROW_CK_HCLK_OUT_R0" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R0" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20172,2210 +79500,3410 @@ } ], "tile_type": "CLK_HROW_BOT_R", - "wires": [ - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_BLOCK_OUTS_B0_4", - "CLK_HROW_BLOCK_OUTS_B0_5", - "CLK_HROW_BLOCK_OUTS_B0_6", - "CLK_HROW_BLOCK_OUTS_B0_7", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_BLOCK_OUTS_B1_4", - "CLK_HROW_BLOCK_OUTS_B1_5", - "CLK_HROW_BLOCK_OUTS_B1_6", - "CLK_HROW_BLOCK_OUTS_B1_7", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B2_4", - "CLK_HROW_BLOCK_OUTS_B2_5", - "CLK_HROW_BLOCK_OUTS_B2_6", - "CLK_HROW_BLOCK_OUTS_B2_7", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_BLOCK_OUTS_B3_4", - "CLK_HROW_BLOCK_OUTS_B3_5", - "CLK_HROW_BLOCK_OUTS_B3_6", - "CLK_HROW_BLOCK_OUTS_B3_7", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN0", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN1", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN10", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN11", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN12", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN13", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN14", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN15", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN16", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN17", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN18", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN19", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN2", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN20", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN21", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN22", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN23", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN24", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN25", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN26", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN27", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN28", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN29", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN3", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN30", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN31", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN4", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN5", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN6", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN7", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN8", - "CLK_HROW_BOT_R_CK_BUFG_CASCIN9", - "CLK_HROW_BOT_R_CK_BUFG_CASCO0", - "CLK_HROW_BOT_R_CK_BUFG_CASCO1", - "CLK_HROW_BOT_R_CK_BUFG_CASCO10", - "CLK_HROW_BOT_R_CK_BUFG_CASCO11", - "CLK_HROW_BOT_R_CK_BUFG_CASCO12", - "CLK_HROW_BOT_R_CK_BUFG_CASCO13", - "CLK_HROW_BOT_R_CK_BUFG_CASCO14", - "CLK_HROW_BOT_R_CK_BUFG_CASCO15", - "CLK_HROW_BOT_R_CK_BUFG_CASCO16", - "CLK_HROW_BOT_R_CK_BUFG_CASCO17", - "CLK_HROW_BOT_R_CK_BUFG_CASCO18", - "CLK_HROW_BOT_R_CK_BUFG_CASCO19", - "CLK_HROW_BOT_R_CK_BUFG_CASCO2", - "CLK_HROW_BOT_R_CK_BUFG_CASCO20", - "CLK_HROW_BOT_R_CK_BUFG_CASCO21", - "CLK_HROW_BOT_R_CK_BUFG_CASCO22", - "CLK_HROW_BOT_R_CK_BUFG_CASCO23", - "CLK_HROW_BOT_R_CK_BUFG_CASCO24", - "CLK_HROW_BOT_R_CK_BUFG_CASCO25", - "CLK_HROW_BOT_R_CK_BUFG_CASCO26", - "CLK_HROW_BOT_R_CK_BUFG_CASCO27", - "CLK_HROW_BOT_R_CK_BUFG_CASCO28", - "CLK_HROW_BOT_R_CK_BUFG_CASCO29", - "CLK_HROW_BOT_R_CK_BUFG_CASCO3", - "CLK_HROW_BOT_R_CK_BUFG_CASCO30", - "CLK_HROW_BOT_R_CK_BUFG_CASCO31", - "CLK_HROW_BOT_R_CK_BUFG_CASCO4", - "CLK_HROW_BOT_R_CK_BUFG_CASCO5", - "CLK_HROW_BOT_R_CK_BUFG_CASCO6", - "CLK_HROW_BOT_R_CK_BUFG_CASCO7", - "CLK_HROW_BOT_R_CK_BUFG_CASCO8", - "CLK_HROW_BOT_R_CK_BUFG_CASCO9", - "CLK_HROW_BUFHCE_CE_L0", - "CLK_HROW_BUFHCE_CE_L1", - "CLK_HROW_BUFHCE_CE_L10", - "CLK_HROW_BUFHCE_CE_L11", - "CLK_HROW_BUFHCE_CE_L2", - "CLK_HROW_BUFHCE_CE_L3", - "CLK_HROW_BUFHCE_CE_L4", - "CLK_HROW_BUFHCE_CE_L5", - "CLK_HROW_BUFHCE_CE_L6", - "CLK_HROW_BUFHCE_CE_L7", - "CLK_HROW_BUFHCE_CE_L8", - "CLK_HROW_BUFHCE_CE_L9", - "CLK_HROW_BUFHCE_CE_R0", - "CLK_HROW_BUFHCE_CE_R1", - "CLK_HROW_BUFHCE_CE_R10", - "CLK_HROW_BUFHCE_CE_R11", - "CLK_HROW_BUFHCE_CE_R2", - "CLK_HROW_BUFHCE_CE_R3", - "CLK_HROW_BUFHCE_CE_R4", - "CLK_HROW_BUFHCE_CE_R5", - "CLK_HROW_BUFHCE_CE_R6", - "CLK_HROW_BUFHCE_CE_R7", - "CLK_HROW_BUFHCE_CE_R8", - "CLK_HROW_BUFHCE_CE_R9", - "CLK_HROW_BYP0_0", - "CLK_HROW_BYP0_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_BYP0_3", - "CLK_HROW_BYP0_4", - "CLK_HROW_BYP0_5", - "CLK_HROW_BYP0_6", - "CLK_HROW_BYP0_7", - "CLK_HROW_BYP1_0", - "CLK_HROW_BYP1_1", - "CLK_HROW_BYP1_2", - "CLK_HROW_BYP1_3", - "CLK_HROW_BYP1_4", - "CLK_HROW_BYP1_5", - "CLK_HROW_BYP1_6", - "CLK_HROW_BYP1_7", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_1", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_3", - "CLK_HROW_BYP2_4", - "CLK_HROW_BYP2_5", - "CLK_HROW_BYP2_6", - "CLK_HROW_BYP2_7", - "CLK_HROW_BYP3_0", - "CLK_HROW_BYP3_1", - "CLK_HROW_BYP3_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_BYP3_4", - "CLK_HROW_BYP3_5", - "CLK_HROW_BYP3_6", - "CLK_HROW_BYP3_7", - "CLK_HROW_BYP4_0", - "CLK_HROW_BYP4_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_BYP4_4", - "CLK_HROW_BYP4_5", - "CLK_HROW_BYP4_6", - "CLK_HROW_BYP4_7", - "CLK_HROW_BYP5_0", - "CLK_HROW_BYP5_1", - "CLK_HROW_BYP5_2", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP5_4", - "CLK_HROW_BYP5_5", - "CLK_HROW_BYP5_6", - "CLK_HROW_BYP5_7", - "CLK_HROW_BYP6_0", - "CLK_HROW_BYP6_1", - "CLK_HROW_BYP6_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_BYP6_4", - "CLK_HROW_BYP6_5", - "CLK_HROW_BYP6_6", - "CLK_HROW_BYP6_7", - "CLK_HROW_BYP7_0", - "CLK_HROW_BYP7_1", - "CLK_HROW_BYP7_2", - "CLK_HROW_BYP7_3", - "CLK_HROW_BYP7_4", - "CLK_HROW_BYP7_5", - "CLK_HROW_BYP7_6", - "CLK_HROW_BYP7_7", - "CLK_HROW_CE_INT_BOT0", - "CLK_HROW_CE_INT_BOT1", - "CLK_HROW_CE_INT_BOT10", - "CLK_HROW_CE_INT_BOT11", - "CLK_HROW_CE_INT_BOT2", - "CLK_HROW_CE_INT_BOT3", - "CLK_HROW_CE_INT_BOT4", - "CLK_HROW_CE_INT_BOT5", - "CLK_HROW_CE_INT_BOT6", - "CLK_HROW_CE_INT_BOT7", - "CLK_HROW_CE_INT_BOT8", - "CLK_HROW_CE_INT_BOT9", - "CLK_HROW_CE_INT_TOP0", - "CLK_HROW_CE_INT_TOP1", - "CLK_HROW_CE_INT_TOP10", - "CLK_HROW_CE_INT_TOP11", - "CLK_HROW_CE_INT_TOP2", - "CLK_HROW_CE_INT_TOP3", - "CLK_HROW_CE_INT_TOP4", - "CLK_HROW_CE_INT_TOP5", - "CLK_HROW_CE_INT_TOP6", - "CLK_HROW_CE_INT_TOP7", - "CLK_HROW_CE_INT_TOP8", - "CLK_HROW_CE_INT_TOP9", - "CLK_HROW_CK_BUFHCLK_L0", - "CLK_HROW_CK_BUFHCLK_L1", - "CLK_HROW_CK_BUFHCLK_L10", - "CLK_HROW_CK_BUFHCLK_L11", - "CLK_HROW_CK_BUFHCLK_L2", - "CLK_HROW_CK_BUFHCLK_L3", - "CLK_HROW_CK_BUFHCLK_L4", - "CLK_HROW_CK_BUFHCLK_L5", - "CLK_HROW_CK_BUFHCLK_L6", - "CLK_HROW_CK_BUFHCLK_L7", - "CLK_HROW_CK_BUFHCLK_L8", - "CLK_HROW_CK_BUFHCLK_L9", - "CLK_HROW_CK_BUFHCLK_R0", - "CLK_HROW_CK_BUFHCLK_R1", - "CLK_HROW_CK_BUFHCLK_R10", - "CLK_HROW_CK_BUFHCLK_R11", - "CLK_HROW_CK_BUFHCLK_R2", - "CLK_HROW_CK_BUFHCLK_R3", - "CLK_HROW_CK_BUFHCLK_R4", - "CLK_HROW_CK_BUFHCLK_R5", - "CLK_HROW_CK_BUFHCLK_R6", - "CLK_HROW_CK_BUFHCLK_R7", - "CLK_HROW_CK_BUFHCLK_R8", - "CLK_HROW_CK_BUFHCLK_R9", - "CLK_HROW_CK_BUFRCLK_L0", - "CLK_HROW_CK_BUFRCLK_L1", - "CLK_HROW_CK_BUFRCLK_L2", - "CLK_HROW_CK_BUFRCLK_L3", - "CLK_HROW_CK_BUFRCLK_R0", - "CLK_HROW_CK_BUFRCLK_R1", - "CLK_HROW_CK_BUFRCLK_R2", - "CLK_HROW_CK_BUFRCLK_R3", - "CLK_HROW_CK_GCLK_IN_TEST0", - "CLK_HROW_CK_GCLK_IN_TEST1", - "CLK_HROW_CK_GCLK_IN_TEST10", - "CLK_HROW_CK_GCLK_IN_TEST11", - "CLK_HROW_CK_GCLK_IN_TEST12", - "CLK_HROW_CK_GCLK_IN_TEST13", - "CLK_HROW_CK_GCLK_IN_TEST14", - "CLK_HROW_CK_GCLK_IN_TEST15", - "CLK_HROW_CK_GCLK_IN_TEST16", - "CLK_HROW_CK_GCLK_IN_TEST17", - "CLK_HROW_CK_GCLK_IN_TEST18", - "CLK_HROW_CK_GCLK_IN_TEST19", - "CLK_HROW_CK_GCLK_IN_TEST2", - "CLK_HROW_CK_GCLK_IN_TEST20", - "CLK_HROW_CK_GCLK_IN_TEST21", - "CLK_HROW_CK_GCLK_IN_TEST22", - "CLK_HROW_CK_GCLK_IN_TEST23", - "CLK_HROW_CK_GCLK_IN_TEST24", - "CLK_HROW_CK_GCLK_IN_TEST25", - "CLK_HROW_CK_GCLK_IN_TEST26", - "CLK_HROW_CK_GCLK_IN_TEST27", - "CLK_HROW_CK_GCLK_IN_TEST28", - "CLK_HROW_CK_GCLK_IN_TEST29", - "CLK_HROW_CK_GCLK_IN_TEST3", - "CLK_HROW_CK_GCLK_IN_TEST30", - "CLK_HROW_CK_GCLK_IN_TEST31", - "CLK_HROW_CK_GCLK_IN_TEST4", - "CLK_HROW_CK_GCLK_IN_TEST5", - "CLK_HROW_CK_GCLK_IN_TEST6", - "CLK_HROW_CK_GCLK_IN_TEST7", - "CLK_HROW_CK_GCLK_IN_TEST8", - "CLK_HROW_CK_GCLK_IN_TEST9", - "CLK_HROW_CK_GCLK_OUT_TEST0", - "CLK_HROW_CK_GCLK_OUT_TEST1", - "CLK_HROW_CK_GCLK_OUT_TEST10", - "CLK_HROW_CK_GCLK_OUT_TEST11", - "CLK_HROW_CK_GCLK_OUT_TEST12", - "CLK_HROW_CK_GCLK_OUT_TEST13", - "CLK_HROW_CK_GCLK_OUT_TEST14", - "CLK_HROW_CK_GCLK_OUT_TEST15", - "CLK_HROW_CK_GCLK_OUT_TEST16", - "CLK_HROW_CK_GCLK_OUT_TEST17", - "CLK_HROW_CK_GCLK_OUT_TEST18", - "CLK_HROW_CK_GCLK_OUT_TEST19", - "CLK_HROW_CK_GCLK_OUT_TEST2", - "CLK_HROW_CK_GCLK_OUT_TEST20", - "CLK_HROW_CK_GCLK_OUT_TEST21", - "CLK_HROW_CK_GCLK_OUT_TEST22", - "CLK_HROW_CK_GCLK_OUT_TEST23", - "CLK_HROW_CK_GCLK_OUT_TEST24", - "CLK_HROW_CK_GCLK_OUT_TEST25", - "CLK_HROW_CK_GCLK_OUT_TEST26", - "CLK_HROW_CK_GCLK_OUT_TEST27", - "CLK_HROW_CK_GCLK_OUT_TEST28", - "CLK_HROW_CK_GCLK_OUT_TEST29", - "CLK_HROW_CK_GCLK_OUT_TEST3", - "CLK_HROW_CK_GCLK_OUT_TEST30", - "CLK_HROW_CK_GCLK_OUT_TEST31", - "CLK_HROW_CK_GCLK_OUT_TEST4", - "CLK_HROW_CK_GCLK_OUT_TEST5", - "CLK_HROW_CK_GCLK_OUT_TEST6", - "CLK_HROW_CK_GCLK_OUT_TEST7", - "CLK_HROW_CK_GCLK_OUT_TEST8", - "CLK_HROW_CK_GCLK_OUT_TEST9", - "CLK_HROW_CK_GCLK_TEST0", - "CLK_HROW_CK_GCLK_TEST1", - "CLK_HROW_CK_GCLK_TEST10", - "CLK_HROW_CK_GCLK_TEST11", - "CLK_HROW_CK_GCLK_TEST12", - "CLK_HROW_CK_GCLK_TEST13", - "CLK_HROW_CK_GCLK_TEST14", - "CLK_HROW_CK_GCLK_TEST15", - "CLK_HROW_CK_GCLK_TEST16", - "CLK_HROW_CK_GCLK_TEST17", - "CLK_HROW_CK_GCLK_TEST18", - "CLK_HROW_CK_GCLK_TEST19", - "CLK_HROW_CK_GCLK_TEST2", - "CLK_HROW_CK_GCLK_TEST20", - "CLK_HROW_CK_GCLK_TEST21", - "CLK_HROW_CK_GCLK_TEST22", - "CLK_HROW_CK_GCLK_TEST23", - "CLK_HROW_CK_GCLK_TEST24", - "CLK_HROW_CK_GCLK_TEST25", - "CLK_HROW_CK_GCLK_TEST26", - "CLK_HROW_CK_GCLK_TEST27", - "CLK_HROW_CK_GCLK_TEST28", - "CLK_HROW_CK_GCLK_TEST29", - "CLK_HROW_CK_GCLK_TEST3", - "CLK_HROW_CK_GCLK_TEST30", - "CLK_HROW_CK_GCLK_TEST31", - "CLK_HROW_CK_GCLK_TEST4", - "CLK_HROW_CK_GCLK_TEST5", - "CLK_HROW_CK_GCLK_TEST6", - "CLK_HROW_CK_GCLK_TEST7", - "CLK_HROW_CK_GCLK_TEST8", - "CLK_HROW_CK_GCLK_TEST9", - "CLK_HROW_CK_GCLK_TEST_IN0", - "CLK_HROW_CK_GCLK_TEST_IN1", - "CLK_HROW_CK_GCLK_TEST_IN10", - "CLK_HROW_CK_GCLK_TEST_IN11", - "CLK_HROW_CK_GCLK_TEST_IN12", - "CLK_HROW_CK_GCLK_TEST_IN13", - "CLK_HROW_CK_GCLK_TEST_IN14", - "CLK_HROW_CK_GCLK_TEST_IN15", - "CLK_HROW_CK_GCLK_TEST_IN16", - "CLK_HROW_CK_GCLK_TEST_IN17", - "CLK_HROW_CK_GCLK_TEST_IN18", - "CLK_HROW_CK_GCLK_TEST_IN19", - "CLK_HROW_CK_GCLK_TEST_IN2", - "CLK_HROW_CK_GCLK_TEST_IN20", - "CLK_HROW_CK_GCLK_TEST_IN21", - "CLK_HROW_CK_GCLK_TEST_IN22", - "CLK_HROW_CK_GCLK_TEST_IN23", - "CLK_HROW_CK_GCLK_TEST_IN24", - "CLK_HROW_CK_GCLK_TEST_IN25", - "CLK_HROW_CK_GCLK_TEST_IN26", - "CLK_HROW_CK_GCLK_TEST_IN27", - "CLK_HROW_CK_GCLK_TEST_IN28", - "CLK_HROW_CK_GCLK_TEST_IN29", - "CLK_HROW_CK_GCLK_TEST_IN3", - "CLK_HROW_CK_GCLK_TEST_IN30", - "CLK_HROW_CK_GCLK_TEST_IN31", - "CLK_HROW_CK_GCLK_TEST_IN4", - "CLK_HROW_CK_GCLK_TEST_IN5", - "CLK_HROW_CK_GCLK_TEST_IN6", - "CLK_HROW_CK_GCLK_TEST_IN7", - "CLK_HROW_CK_GCLK_TEST_IN8", - "CLK_HROW_CK_GCLK_TEST_IN9", - "CLK_HROW_CK_GCLK_TEST_OUT0", - "CLK_HROW_CK_GCLK_TEST_OUT1", - "CLK_HROW_CK_GCLK_TEST_OUT10", - "CLK_HROW_CK_GCLK_TEST_OUT11", - "CLK_HROW_CK_GCLK_TEST_OUT12", - "CLK_HROW_CK_GCLK_TEST_OUT13", - "CLK_HROW_CK_GCLK_TEST_OUT14", - "CLK_HROW_CK_GCLK_TEST_OUT15", - "CLK_HROW_CK_GCLK_TEST_OUT16", - "CLK_HROW_CK_GCLK_TEST_OUT17", - "CLK_HROW_CK_GCLK_TEST_OUT18", - "CLK_HROW_CK_GCLK_TEST_OUT19", - "CLK_HROW_CK_GCLK_TEST_OUT2", - "CLK_HROW_CK_GCLK_TEST_OUT20", - "CLK_HROW_CK_GCLK_TEST_OUT21", - "CLK_HROW_CK_GCLK_TEST_OUT22", - "CLK_HROW_CK_GCLK_TEST_OUT23", - "CLK_HROW_CK_GCLK_TEST_OUT24", - "CLK_HROW_CK_GCLK_TEST_OUT25", - "CLK_HROW_CK_GCLK_TEST_OUT26", - "CLK_HROW_CK_GCLK_TEST_OUT27", - "CLK_HROW_CK_GCLK_TEST_OUT28", - "CLK_HROW_CK_GCLK_TEST_OUT29", - "CLK_HROW_CK_GCLK_TEST_OUT3", - "CLK_HROW_CK_GCLK_TEST_OUT30", - "CLK_HROW_CK_GCLK_TEST_OUT31", - "CLK_HROW_CK_GCLK_TEST_OUT4", - "CLK_HROW_CK_GCLK_TEST_OUT5", - "CLK_HROW_CK_GCLK_TEST_OUT6", - "CLK_HROW_CK_GCLK_TEST_OUT7", - "CLK_HROW_CK_GCLK_TEST_OUT8", - "CLK_HROW_CK_GCLK_TEST_OUT9", - "CLK_HROW_CK_HCLK_OUT_L0", - "CLK_HROW_CK_HCLK_OUT_L1", - "CLK_HROW_CK_HCLK_OUT_L10", - "CLK_HROW_CK_HCLK_OUT_L11", - "CLK_HROW_CK_HCLK_OUT_L2", - "CLK_HROW_CK_HCLK_OUT_L3", - "CLK_HROW_CK_HCLK_OUT_L4", - "CLK_HROW_CK_HCLK_OUT_L5", - "CLK_HROW_CK_HCLK_OUT_L6", - "CLK_HROW_CK_HCLK_OUT_L7", - "CLK_HROW_CK_HCLK_OUT_L8", - "CLK_HROW_CK_HCLK_OUT_L9", - "CLK_HROW_CK_HCLK_OUT_R0", - "CLK_HROW_CK_HCLK_OUT_R1", - "CLK_HROW_CK_HCLK_OUT_R10", - "CLK_HROW_CK_HCLK_OUT_R11", - "CLK_HROW_CK_HCLK_OUT_R2", - "CLK_HROW_CK_HCLK_OUT_R3", - "CLK_HROW_CK_HCLK_OUT_R4", - "CLK_HROW_CK_HCLK_OUT_R5", - "CLK_HROW_CK_HCLK_OUT_R6", - "CLK_HROW_CK_HCLK_OUT_R7", - "CLK_HROW_CK_HCLK_OUT_R8", - "CLK_HROW_CK_HCLK_OUT_R9", - "CLK_HROW_CK_INT_0_0", - "CLK_HROW_CK_INT_0_1", - "CLK_HROW_CK_INT_1_0", - "CLK_HROW_CK_INT_1_1", - "CLK_HROW_CK_IN_L0", - "CLK_HROW_CK_IN_L1", - "CLK_HROW_CK_IN_L10", - "CLK_HROW_CK_IN_L11", - "CLK_HROW_CK_IN_L12", - "CLK_HROW_CK_IN_L13", - "CLK_HROW_CK_IN_L2", - "CLK_HROW_CK_IN_L3", - "CLK_HROW_CK_IN_L4", - "CLK_HROW_CK_IN_L5", - "CLK_HROW_CK_IN_L6", - "CLK_HROW_CK_IN_L7", - "CLK_HROW_CK_IN_L8", - "CLK_HROW_CK_IN_L9", - "CLK_HROW_CK_IN_L_IN_TEST", - "CLK_HROW_CK_IN_L_OUT_TEST", - "CLK_HROW_CK_IN_L_TEST_IN", - "CLK_HROW_CK_IN_L_TEST_OUT", - "CLK_HROW_CK_IN_R0", - "CLK_HROW_CK_IN_R1", - "CLK_HROW_CK_IN_R10", - "CLK_HROW_CK_IN_R11", - "CLK_HROW_CK_IN_R12", - "CLK_HROW_CK_IN_R13", - "CLK_HROW_CK_IN_R2", - "CLK_HROW_CK_IN_R3", - "CLK_HROW_CK_IN_R4", - "CLK_HROW_CK_IN_R5", - "CLK_HROW_CK_IN_R6", - "CLK_HROW_CK_IN_R7", - "CLK_HROW_CK_IN_R8", - "CLK_HROW_CK_IN_R9", - "CLK_HROW_CK_IN_R_IN_TEST", - "CLK_HROW_CK_IN_R_OUT_TEST", - "CLK_HROW_CK_IN_R_TEST_IN", - "CLK_HROW_CK_IN_R_TEST_OUT", - "CLK_HROW_CK_MUX_OUT_L0", - "CLK_HROW_CK_MUX_OUT_L1", - "CLK_HROW_CK_MUX_OUT_L10", - "CLK_HROW_CK_MUX_OUT_L11", - "CLK_HROW_CK_MUX_OUT_L2", - "CLK_HROW_CK_MUX_OUT_L3", - "CLK_HROW_CK_MUX_OUT_L4", - "CLK_HROW_CK_MUX_OUT_L5", - "CLK_HROW_CK_MUX_OUT_L6", - "CLK_HROW_CK_MUX_OUT_L7", - "CLK_HROW_CK_MUX_OUT_L8", - "CLK_HROW_CK_MUX_OUT_L9", - "CLK_HROW_CK_MUX_OUT_R0", - "CLK_HROW_CK_MUX_OUT_R1", - "CLK_HROW_CK_MUX_OUT_R10", - "CLK_HROW_CK_MUX_OUT_R11", - "CLK_HROW_CK_MUX_OUT_R2", - "CLK_HROW_CK_MUX_OUT_R3", - "CLK_HROW_CK_MUX_OUT_R4", - "CLK_HROW_CK_MUX_OUT_R5", - "CLK_HROW_CK_MUX_OUT_R6", - "CLK_HROW_CK_MUX_OUT_R7", - "CLK_HROW_CK_MUX_OUT_R8", - "CLK_HROW_CK_MUX_OUT_R9", - "CLK_HROW_CLK0_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_CLK0_2", - "CLK_HROW_CLK0_3", - "CLK_HROW_CLK0_4", - "CLK_HROW_CLK0_5", - "CLK_HROW_CLK0_6", - "CLK_HROW_CLK0_7", - "CLK_HROW_CLK1_0", - "CLK_HROW_CLK1_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_CLK1_3", - "CLK_HROW_CLK1_4", - "CLK_HROW_CLK1_5", - "CLK_HROW_CLK1_6", - "CLK_HROW_CLK1_7", - "CLK_HROW_CTRL0_0", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CTRL0_2", - "CLK_HROW_CTRL0_3", - "CLK_HROW_CTRL0_4", - "CLK_HROW_CTRL0_5", - "CLK_HROW_CTRL0_6", - "CLK_HROW_CTRL0_7", - "CLK_HROW_CTRL1_0", - "CLK_HROW_CTRL1_1", - "CLK_HROW_CTRL1_2", - "CLK_HROW_CTRL1_3", - "CLK_HROW_CTRL1_4", - "CLK_HROW_CTRL1_5", - "CLK_HROW_CTRL1_6", - "CLK_HROW_CTRL1_7", - "CLK_HROW_EE2A0_0", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_EE2A0_3", - "CLK_HROW_EE2A0_4", - "CLK_HROW_EE2A0_5", - "CLK_HROW_EE2A0_6", - "CLK_HROW_EE2A0_7", - "CLK_HROW_EE2A1_0", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE2A1_2", - "CLK_HROW_EE2A1_3", - "CLK_HROW_EE2A1_4", - "CLK_HROW_EE2A1_5", - "CLK_HROW_EE2A1_6", - "CLK_HROW_EE2A1_7", - "CLK_HROW_EE2A2_0", - "CLK_HROW_EE2A2_1", - "CLK_HROW_EE2A2_2", - "CLK_HROW_EE2A2_3", - "CLK_HROW_EE2A2_4", - "CLK_HROW_EE2A2_5", - "CLK_HROW_EE2A2_6", - "CLK_HROW_EE2A2_7", - "CLK_HROW_EE2A3_0", - "CLK_HROW_EE2A3_1", - "CLK_HROW_EE2A3_2", - "CLK_HROW_EE2A3_3", - "CLK_HROW_EE2A3_4", - "CLK_HROW_EE2A3_5", - "CLK_HROW_EE2A3_6", - "CLK_HROW_EE2A3_7", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_EE2BEG0_4", - "CLK_HROW_EE2BEG0_5", - "CLK_HROW_EE2BEG0_6", - "CLK_HROW_EE2BEG0_7", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_EE2BEG1_4", - "CLK_HROW_EE2BEG1_5", - "CLK_HROW_EE2BEG1_6", - "CLK_HROW_EE2BEG1_7", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_EE2BEG2_4", - "CLK_HROW_EE2BEG2_5", - "CLK_HROW_EE2BEG2_6", - "CLK_HROW_EE2BEG2_7", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_EE2BEG3_4", - "CLK_HROW_EE2BEG3_5", - "CLK_HROW_EE2BEG3_6", - "CLK_HROW_EE2BEG3_7", - "CLK_HROW_EE4A0_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_EE4A0_2", - "CLK_HROW_EE4A0_3", - "CLK_HROW_EE4A0_4", - "CLK_HROW_EE4A0_5", - "CLK_HROW_EE4A0_6", - "CLK_HROW_EE4A0_7", - "CLK_HROW_EE4A1_0", - "CLK_HROW_EE4A1_1", - "CLK_HROW_EE4A1_2", - "CLK_HROW_EE4A1_3", - "CLK_HROW_EE4A1_4", - "CLK_HROW_EE4A1_5", - "CLK_HROW_EE4A1_6", - "CLK_HROW_EE4A1_7", - "CLK_HROW_EE4A2_0", - "CLK_HROW_EE4A2_1", - "CLK_HROW_EE4A2_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_EE4A2_4", - "CLK_HROW_EE4A2_5", - "CLK_HROW_EE4A2_6", - "CLK_HROW_EE4A2_7", - "CLK_HROW_EE4A3_0", - "CLK_HROW_EE4A3_1", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE4A3_4", - "CLK_HROW_EE4A3_5", - "CLK_HROW_EE4A3_6", - "CLK_HROW_EE4A3_7", - "CLK_HROW_EE4B0_0", - "CLK_HROW_EE4B0_1", - "CLK_HROW_EE4B0_2", - "CLK_HROW_EE4B0_3", - "CLK_HROW_EE4B0_4", - "CLK_HROW_EE4B0_5", - "CLK_HROW_EE4B0_6", - "CLK_HROW_EE4B0_7", - "CLK_HROW_EE4B1_0", - "CLK_HROW_EE4B1_1", - "CLK_HROW_EE4B1_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_EE4B1_4", - "CLK_HROW_EE4B1_5", - "CLK_HROW_EE4B1_6", - "CLK_HROW_EE4B1_7", - "CLK_HROW_EE4B2_0", - "CLK_HROW_EE4B2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_EE4B2_4", - "CLK_HROW_EE4B2_5", - "CLK_HROW_EE4B2_6", - "CLK_HROW_EE4B2_7", - "CLK_HROW_EE4B3_0", - "CLK_HROW_EE4B3_1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4B3_4", - "CLK_HROW_EE4B3_5", - "CLK_HROW_EE4B3_6", - "CLK_HROW_EE4B3_7", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_EE4BEG0_4", - "CLK_HROW_EE4BEG0_5", - "CLK_HROW_EE4BEG0_6", - "CLK_HROW_EE4BEG0_7", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_EE4BEG1_4", - "CLK_HROW_EE4BEG1_5", - "CLK_HROW_EE4BEG1_6", - "CLK_HROW_EE4BEG1_7", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_EE4BEG2_4", - "CLK_HROW_EE4BEG2_5", - "CLK_HROW_EE4BEG2_6", - "CLK_HROW_EE4BEG2_7", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_EE4BEG3_4", - "CLK_HROW_EE4BEG3_5", - "CLK_HROW_EE4BEG3_6", - "CLK_HROW_EE4BEG3_7", - "CLK_HROW_EE4C0_0", - "CLK_HROW_EE4C0_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE4C0_3", - "CLK_HROW_EE4C0_4", - "CLK_HROW_EE4C0_5", - "CLK_HROW_EE4C0_6", - "CLK_HROW_EE4C0_7", - "CLK_HROW_EE4C1_0", - "CLK_HROW_EE4C1_1", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE4C1_3", - "CLK_HROW_EE4C1_4", - "CLK_HROW_EE4C1_5", - "CLK_HROW_EE4C1_6", - "CLK_HROW_EE4C1_7", - "CLK_HROW_EE4C2_0", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4C2_2", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4C2_4", - "CLK_HROW_EE4C2_5", - "CLK_HROW_EE4C2_6", - "CLK_HROW_EE4C2_7", - "CLK_HROW_EE4C3_0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_EE4C3_2", - "CLK_HROW_EE4C3_3", - "CLK_HROW_EE4C3_4", - "CLK_HROW_EE4C3_5", - "CLK_HROW_EE4C3_6", - "CLK_HROW_EE4C3_7", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_EL1BEG0_4", - "CLK_HROW_EL1BEG0_5", - "CLK_HROW_EL1BEG0_6", - "CLK_HROW_EL1BEG0_7", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_EL1BEG1_4", - "CLK_HROW_EL1BEG1_5", - "CLK_HROW_EL1BEG1_6", - "CLK_HROW_EL1BEG1_7", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_EL1BEG2_4", - "CLK_HROW_EL1BEG2_5", - "CLK_HROW_EL1BEG2_6", - "CLK_HROW_EL1BEG2_7", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_EL1BEG3_4", - "CLK_HROW_EL1BEG3_5", - "CLK_HROW_EL1BEG3_6", - "CLK_HROW_EL1BEG3_7", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_ER1BEG0_4", - "CLK_HROW_ER1BEG0_5", - "CLK_HROW_ER1BEG0_6", - "CLK_HROW_ER1BEG0_7", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_ER1BEG1_4", - "CLK_HROW_ER1BEG1_5", - "CLK_HROW_ER1BEG1_6", - "CLK_HROW_ER1BEG1_7", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_ER1BEG2_4", - "CLK_HROW_ER1BEG2_5", - "CLK_HROW_ER1BEG2_6", - "CLK_HROW_ER1BEG2_7", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_ER1BEG3_4", - "CLK_HROW_ER1BEG3_5", - "CLK_HROW_ER1BEG3_6", - "CLK_HROW_ER1BEG3_7", - "CLK_HROW_FAN0_0", - "CLK_HROW_FAN0_1", - "CLK_HROW_FAN0_2", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN0_4", - "CLK_HROW_FAN0_5", - "CLK_HROW_FAN0_6", - "CLK_HROW_FAN0_7", - "CLK_HROW_FAN1_0", - "CLK_HROW_FAN1_1", - "CLK_HROW_FAN1_2", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN1_4", - "CLK_HROW_FAN1_5", - "CLK_HROW_FAN1_6", - "CLK_HROW_FAN1_7", - "CLK_HROW_FAN2_0", - "CLK_HROW_FAN2_1", - "CLK_HROW_FAN2_2", - "CLK_HROW_FAN2_3", - "CLK_HROW_FAN2_4", - "CLK_HROW_FAN2_5", - "CLK_HROW_FAN2_6", - "CLK_HROW_FAN2_7", - "CLK_HROW_FAN3_0", - "CLK_HROW_FAN3_1", - "CLK_HROW_FAN3_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_FAN3_4", - "CLK_HROW_FAN3_5", - "CLK_HROW_FAN3_6", - "CLK_HROW_FAN3_7", - "CLK_HROW_FAN4_0", - "CLK_HROW_FAN4_1", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_3", - "CLK_HROW_FAN4_4", - "CLK_HROW_FAN4_5", - "CLK_HROW_FAN4_6", - "CLK_HROW_FAN4_7", - "CLK_HROW_FAN5_0", - "CLK_HROW_FAN5_1", - "CLK_HROW_FAN5_2", - "CLK_HROW_FAN5_3", - "CLK_HROW_FAN5_4", - "CLK_HROW_FAN5_5", - "CLK_HROW_FAN5_6", - "CLK_HROW_FAN5_7", - "CLK_HROW_FAN6_0", - "CLK_HROW_FAN6_1", - "CLK_HROW_FAN6_2", - "CLK_HROW_FAN6_3", - "CLK_HROW_FAN6_4", - "CLK_HROW_FAN6_5", - "CLK_HROW_FAN6_6", - "CLK_HROW_FAN6_7", - "CLK_HROW_FAN7_0", - "CLK_HROW_FAN7_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_FAN7_3", - "CLK_HROW_FAN7_4", - "CLK_HROW_FAN7_5", - "CLK_HROW_FAN7_6", - "CLK_HROW_FAN7_7", - "CLK_HROW_IMUX0_0", - "CLK_HROW_IMUX0_1", - "CLK_HROW_IMUX0_2", - "CLK_HROW_IMUX0_3", - "CLK_HROW_IMUX0_4", - "CLK_HROW_IMUX0_5", - "CLK_HROW_IMUX0_6", - "CLK_HROW_IMUX0_7", - "CLK_HROW_IMUX10_0", - "CLK_HROW_IMUX10_1", - "CLK_HROW_IMUX10_2", - "CLK_HROW_IMUX10_3", - "CLK_HROW_IMUX10_4", - "CLK_HROW_IMUX10_5", - "CLK_HROW_IMUX10_6", - "CLK_HROW_IMUX10_7", - "CLK_HROW_IMUX11_0", - "CLK_HROW_IMUX11_1", - "CLK_HROW_IMUX11_2", - "CLK_HROW_IMUX11_3", - "CLK_HROW_IMUX11_4", - "CLK_HROW_IMUX11_5", - "CLK_HROW_IMUX11_6", - "CLK_HROW_IMUX11_7", - "CLK_HROW_IMUX12_0", - "CLK_HROW_IMUX12_1", - "CLK_HROW_IMUX12_2", - "CLK_HROW_IMUX12_3", - "CLK_HROW_IMUX12_4", - "CLK_HROW_IMUX12_5", - "CLK_HROW_IMUX12_6", - "CLK_HROW_IMUX12_7", - "CLK_HROW_IMUX13_0", - "CLK_HROW_IMUX13_1", - "CLK_HROW_IMUX13_2", - "CLK_HROW_IMUX13_3", - "CLK_HROW_IMUX13_4", - "CLK_HROW_IMUX13_5", - "CLK_HROW_IMUX13_6", - "CLK_HROW_IMUX13_7", - "CLK_HROW_IMUX14_0", - "CLK_HROW_IMUX14_1", - "CLK_HROW_IMUX14_2", - "CLK_HROW_IMUX14_3", - "CLK_HROW_IMUX14_4", - "CLK_HROW_IMUX14_5", - "CLK_HROW_IMUX14_6", - "CLK_HROW_IMUX14_7", - "CLK_HROW_IMUX15_0", - "CLK_HROW_IMUX15_1", - "CLK_HROW_IMUX15_2", - "CLK_HROW_IMUX15_3", - "CLK_HROW_IMUX15_4", - "CLK_HROW_IMUX15_5", - "CLK_HROW_IMUX15_6", - "CLK_HROW_IMUX15_7", - "CLK_HROW_IMUX16_0", - "CLK_HROW_IMUX16_1", - "CLK_HROW_IMUX16_2", - "CLK_HROW_IMUX16_3", - "CLK_HROW_IMUX16_4", - "CLK_HROW_IMUX16_5", - "CLK_HROW_IMUX16_6", - "CLK_HROW_IMUX16_7", - "CLK_HROW_IMUX17_0", - "CLK_HROW_IMUX17_1", - "CLK_HROW_IMUX17_2", - "CLK_HROW_IMUX17_3", - "CLK_HROW_IMUX17_4", - "CLK_HROW_IMUX17_5", - "CLK_HROW_IMUX17_6", - "CLK_HROW_IMUX17_7", - "CLK_HROW_IMUX18_0", - "CLK_HROW_IMUX18_1", - "CLK_HROW_IMUX18_2", - "CLK_HROW_IMUX18_3", - "CLK_HROW_IMUX18_4", - "CLK_HROW_IMUX18_5", - "CLK_HROW_IMUX18_6", - "CLK_HROW_IMUX18_7", - "CLK_HROW_IMUX19_0", - "CLK_HROW_IMUX19_1", - "CLK_HROW_IMUX19_2", - "CLK_HROW_IMUX19_3", - "CLK_HROW_IMUX19_4", - "CLK_HROW_IMUX19_5", - "CLK_HROW_IMUX19_6", - "CLK_HROW_IMUX19_7", - "CLK_HROW_IMUX1_0", - "CLK_HROW_IMUX1_1", - "CLK_HROW_IMUX1_2", - "CLK_HROW_IMUX1_3", - "CLK_HROW_IMUX1_4", - "CLK_HROW_IMUX1_5", - "CLK_HROW_IMUX1_6", - "CLK_HROW_IMUX1_7", - "CLK_HROW_IMUX20_0", - "CLK_HROW_IMUX20_1", - "CLK_HROW_IMUX20_2", - "CLK_HROW_IMUX20_3", - "CLK_HROW_IMUX20_4", - "CLK_HROW_IMUX20_5", - "CLK_HROW_IMUX20_6", - "CLK_HROW_IMUX20_7", - "CLK_HROW_IMUX21_0", - "CLK_HROW_IMUX21_1", - "CLK_HROW_IMUX21_2", - "CLK_HROW_IMUX21_3", - "CLK_HROW_IMUX21_4", - "CLK_HROW_IMUX21_5", - "CLK_HROW_IMUX21_6", - "CLK_HROW_IMUX21_7", - "CLK_HROW_IMUX22_0", - "CLK_HROW_IMUX22_1", - "CLK_HROW_IMUX22_2", - "CLK_HROW_IMUX22_3", - "CLK_HROW_IMUX22_4", - "CLK_HROW_IMUX22_5", - "CLK_HROW_IMUX22_6", - "CLK_HROW_IMUX22_7", - "CLK_HROW_IMUX23_0", - "CLK_HROW_IMUX23_1", - "CLK_HROW_IMUX23_2", - "CLK_HROW_IMUX23_3", - "CLK_HROW_IMUX23_4", - "CLK_HROW_IMUX23_5", - "CLK_HROW_IMUX23_6", - "CLK_HROW_IMUX23_7", - "CLK_HROW_IMUX24_0", - "CLK_HROW_IMUX24_1", - "CLK_HROW_IMUX24_2", - "CLK_HROW_IMUX24_3", - "CLK_HROW_IMUX24_4", - "CLK_HROW_IMUX24_5", - "CLK_HROW_IMUX24_6", - "CLK_HROW_IMUX24_7", - "CLK_HROW_IMUX25_0", - "CLK_HROW_IMUX25_1", - "CLK_HROW_IMUX25_2", - "CLK_HROW_IMUX25_3", - "CLK_HROW_IMUX25_4", - "CLK_HROW_IMUX25_5", - "CLK_HROW_IMUX25_6", - "CLK_HROW_IMUX25_7", - "CLK_HROW_IMUX26_0", - "CLK_HROW_IMUX26_1", - "CLK_HROW_IMUX26_2", - "CLK_HROW_IMUX26_3", - "CLK_HROW_IMUX26_4", - "CLK_HROW_IMUX26_5", - "CLK_HROW_IMUX26_6", - "CLK_HROW_IMUX26_7", - "CLK_HROW_IMUX27_0", - "CLK_HROW_IMUX27_1", - "CLK_HROW_IMUX27_2", - "CLK_HROW_IMUX27_3", - "CLK_HROW_IMUX27_4", - "CLK_HROW_IMUX27_5", - "CLK_HROW_IMUX27_6", - "CLK_HROW_IMUX27_7", - "CLK_HROW_IMUX28_0", - "CLK_HROW_IMUX28_1", - "CLK_HROW_IMUX28_2", - "CLK_HROW_IMUX28_3", - "CLK_HROW_IMUX28_4", - "CLK_HROW_IMUX28_5", - "CLK_HROW_IMUX28_6", - "CLK_HROW_IMUX28_7", - "CLK_HROW_IMUX29_0", - "CLK_HROW_IMUX29_1", - "CLK_HROW_IMUX29_2", - "CLK_HROW_IMUX29_3", - "CLK_HROW_IMUX29_4", - "CLK_HROW_IMUX29_5", - "CLK_HROW_IMUX29_6", - "CLK_HROW_IMUX29_7", - "CLK_HROW_IMUX2_0", - "CLK_HROW_IMUX2_1", - "CLK_HROW_IMUX2_2", - "CLK_HROW_IMUX2_3", - "CLK_HROW_IMUX2_4", - "CLK_HROW_IMUX2_5", - "CLK_HROW_IMUX2_6", - "CLK_HROW_IMUX2_7", - "CLK_HROW_IMUX30_0", - "CLK_HROW_IMUX30_1", - "CLK_HROW_IMUX30_2", - "CLK_HROW_IMUX30_3", - "CLK_HROW_IMUX30_4", - "CLK_HROW_IMUX30_5", - "CLK_HROW_IMUX30_6", - "CLK_HROW_IMUX30_7", - "CLK_HROW_IMUX31_0", - "CLK_HROW_IMUX31_1", - "CLK_HROW_IMUX31_2", - "CLK_HROW_IMUX31_3", - "CLK_HROW_IMUX31_4", - "CLK_HROW_IMUX31_5", - "CLK_HROW_IMUX31_6", - "CLK_HROW_IMUX31_7", - "CLK_HROW_IMUX32_0", - "CLK_HROW_IMUX32_1", - "CLK_HROW_IMUX32_2", - "CLK_HROW_IMUX32_3", - "CLK_HROW_IMUX32_4", - "CLK_HROW_IMUX32_5", - "CLK_HROW_IMUX32_6", - "CLK_HROW_IMUX32_7", - "CLK_HROW_IMUX33_0", - "CLK_HROW_IMUX33_1", - "CLK_HROW_IMUX33_2", - "CLK_HROW_IMUX33_3", - "CLK_HROW_IMUX33_4", - "CLK_HROW_IMUX33_5", - "CLK_HROW_IMUX33_6", - "CLK_HROW_IMUX33_7", - "CLK_HROW_IMUX34_0", - "CLK_HROW_IMUX34_1", - "CLK_HROW_IMUX34_2", - "CLK_HROW_IMUX34_3", - "CLK_HROW_IMUX34_4", - "CLK_HROW_IMUX34_5", - "CLK_HROW_IMUX34_6", - "CLK_HROW_IMUX34_7", - "CLK_HROW_IMUX35_0", - "CLK_HROW_IMUX35_1", - "CLK_HROW_IMUX35_2", - "CLK_HROW_IMUX35_3", - "CLK_HROW_IMUX35_4", - "CLK_HROW_IMUX35_5", - "CLK_HROW_IMUX35_6", - "CLK_HROW_IMUX35_7", - "CLK_HROW_IMUX36_0", - "CLK_HROW_IMUX36_1", - "CLK_HROW_IMUX36_2", - "CLK_HROW_IMUX36_3", - "CLK_HROW_IMUX36_4", - "CLK_HROW_IMUX36_5", - "CLK_HROW_IMUX36_6", - "CLK_HROW_IMUX36_7", - "CLK_HROW_IMUX37_0", - "CLK_HROW_IMUX37_1", - "CLK_HROW_IMUX37_2", - "CLK_HROW_IMUX37_3", - "CLK_HROW_IMUX37_4", - "CLK_HROW_IMUX37_5", - "CLK_HROW_IMUX37_6", - "CLK_HROW_IMUX37_7", - "CLK_HROW_IMUX38_0", - "CLK_HROW_IMUX38_1", - "CLK_HROW_IMUX38_2", - "CLK_HROW_IMUX38_3", - "CLK_HROW_IMUX38_4", - "CLK_HROW_IMUX38_5", - "CLK_HROW_IMUX38_6", - "CLK_HROW_IMUX38_7", - "CLK_HROW_IMUX39_0", - "CLK_HROW_IMUX39_1", - "CLK_HROW_IMUX39_2", - "CLK_HROW_IMUX39_3", - "CLK_HROW_IMUX39_4", - "CLK_HROW_IMUX39_5", - "CLK_HROW_IMUX39_6", - "CLK_HROW_IMUX39_7", - "CLK_HROW_IMUX3_0", - "CLK_HROW_IMUX3_1", - "CLK_HROW_IMUX3_2", - "CLK_HROW_IMUX3_3", - "CLK_HROW_IMUX3_4", - "CLK_HROW_IMUX3_5", - "CLK_HROW_IMUX3_6", - "CLK_HROW_IMUX3_7", - "CLK_HROW_IMUX40_0", - "CLK_HROW_IMUX40_1", - "CLK_HROW_IMUX40_2", - "CLK_HROW_IMUX40_3", - "CLK_HROW_IMUX40_4", - "CLK_HROW_IMUX40_5", - "CLK_HROW_IMUX40_6", - "CLK_HROW_IMUX40_7", - "CLK_HROW_IMUX41_0", - "CLK_HROW_IMUX41_1", - "CLK_HROW_IMUX41_2", - "CLK_HROW_IMUX41_3", - "CLK_HROW_IMUX41_4", - "CLK_HROW_IMUX41_5", - "CLK_HROW_IMUX41_6", - "CLK_HROW_IMUX41_7", - "CLK_HROW_IMUX42_0", - "CLK_HROW_IMUX42_1", - "CLK_HROW_IMUX42_2", - "CLK_HROW_IMUX42_3", - "CLK_HROW_IMUX42_4", - "CLK_HROW_IMUX42_5", - "CLK_HROW_IMUX42_6", - "CLK_HROW_IMUX42_7", - "CLK_HROW_IMUX43_0", - "CLK_HROW_IMUX43_1", - "CLK_HROW_IMUX43_2", - "CLK_HROW_IMUX43_3", - "CLK_HROW_IMUX43_4", - "CLK_HROW_IMUX43_5", - "CLK_HROW_IMUX43_6", - "CLK_HROW_IMUX43_7", - "CLK_HROW_IMUX44_0", - "CLK_HROW_IMUX44_1", - "CLK_HROW_IMUX44_2", - "CLK_HROW_IMUX44_3", - "CLK_HROW_IMUX44_4", - "CLK_HROW_IMUX44_5", - "CLK_HROW_IMUX44_6", - "CLK_HROW_IMUX44_7", - "CLK_HROW_IMUX45_0", - "CLK_HROW_IMUX45_1", - "CLK_HROW_IMUX45_2", - "CLK_HROW_IMUX45_3", - "CLK_HROW_IMUX45_4", - "CLK_HROW_IMUX45_5", - "CLK_HROW_IMUX45_6", - "CLK_HROW_IMUX45_7", - "CLK_HROW_IMUX46_0", - "CLK_HROW_IMUX46_1", - "CLK_HROW_IMUX46_2", - "CLK_HROW_IMUX46_3", - "CLK_HROW_IMUX46_4", - "CLK_HROW_IMUX46_5", - "CLK_HROW_IMUX46_6", - "CLK_HROW_IMUX46_7", - "CLK_HROW_IMUX47_0", - "CLK_HROW_IMUX47_1", - "CLK_HROW_IMUX47_2", - "CLK_HROW_IMUX47_3", - "CLK_HROW_IMUX47_4", - "CLK_HROW_IMUX47_5", - "CLK_HROW_IMUX47_6", - "CLK_HROW_IMUX47_7", - "CLK_HROW_IMUX4_0", - "CLK_HROW_IMUX4_1", - "CLK_HROW_IMUX4_2", - "CLK_HROW_IMUX4_3", - "CLK_HROW_IMUX4_4", - "CLK_HROW_IMUX4_5", - "CLK_HROW_IMUX4_6", - "CLK_HROW_IMUX4_7", - "CLK_HROW_IMUX5_0", - "CLK_HROW_IMUX5_1", - "CLK_HROW_IMUX5_2", - "CLK_HROW_IMUX5_3", - "CLK_HROW_IMUX5_4", - "CLK_HROW_IMUX5_5", - "CLK_HROW_IMUX5_6", - "CLK_HROW_IMUX5_7", - "CLK_HROW_IMUX6_0", - "CLK_HROW_IMUX6_1", - "CLK_HROW_IMUX6_2", - "CLK_HROW_IMUX6_3", - "CLK_HROW_IMUX6_4", - "CLK_HROW_IMUX6_5", - "CLK_HROW_IMUX6_6", - "CLK_HROW_IMUX6_7", - "CLK_HROW_IMUX7_0", - "CLK_HROW_IMUX7_1", - "CLK_HROW_IMUX7_2", - "CLK_HROW_IMUX7_3", - "CLK_HROW_IMUX7_4", - "CLK_HROW_IMUX7_5", - "CLK_HROW_IMUX7_6", - "CLK_HROW_IMUX7_7", - "CLK_HROW_IMUX8_0", - "CLK_HROW_IMUX8_1", - "CLK_HROW_IMUX8_2", - "CLK_HROW_IMUX8_3", - "CLK_HROW_IMUX8_4", - "CLK_HROW_IMUX8_5", - "CLK_HROW_IMUX8_6", - "CLK_HROW_IMUX8_7", - "CLK_HROW_IMUX9_0", - "CLK_HROW_IMUX9_1", - "CLK_HROW_IMUX9_2", - "CLK_HROW_IMUX9_3", - "CLK_HROW_IMUX9_4", - "CLK_HROW_IMUX9_5", - "CLK_HROW_IMUX9_6", - "CLK_HROW_IMUX9_7", - "CLK_HROW_LH10_0", - "CLK_HROW_LH10_1", - "CLK_HROW_LH10_2", - "CLK_HROW_LH10_3", - "CLK_HROW_LH10_4", - "CLK_HROW_LH10_5", - "CLK_HROW_LH10_6", - "CLK_HROW_LH10_7", - "CLK_HROW_LH11_0", - "CLK_HROW_LH11_1", - "CLK_HROW_LH11_2", - "CLK_HROW_LH11_3", - "CLK_HROW_LH11_4", - "CLK_HROW_LH11_5", - "CLK_HROW_LH11_6", - "CLK_HROW_LH11_7", - "CLK_HROW_LH12_0", - "CLK_HROW_LH12_1", - "CLK_HROW_LH12_2", - "CLK_HROW_LH12_3", - "CLK_HROW_LH12_4", - "CLK_HROW_LH12_5", - "CLK_HROW_LH12_6", - "CLK_HROW_LH12_7", - "CLK_HROW_LH1_0", - "CLK_HROW_LH1_1", - "CLK_HROW_LH1_2", - "CLK_HROW_LH1_3", - "CLK_HROW_LH1_4", - "CLK_HROW_LH1_5", - "CLK_HROW_LH1_6", - "CLK_HROW_LH1_7", - "CLK_HROW_LH2_0", - "CLK_HROW_LH2_1", - "CLK_HROW_LH2_2", - "CLK_HROW_LH2_3", - "CLK_HROW_LH2_4", - "CLK_HROW_LH2_5", - "CLK_HROW_LH2_6", - "CLK_HROW_LH2_7", - "CLK_HROW_LH3_0", - "CLK_HROW_LH3_1", - "CLK_HROW_LH3_2", - "CLK_HROW_LH3_3", - "CLK_HROW_LH3_4", - "CLK_HROW_LH3_5", - "CLK_HROW_LH3_6", - "CLK_HROW_LH3_7", - "CLK_HROW_LH4_0", - "CLK_HROW_LH4_1", - "CLK_HROW_LH4_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LH4_4", - "CLK_HROW_LH4_5", - "CLK_HROW_LH4_6", - "CLK_HROW_LH4_7", - "CLK_HROW_LH5_0", - "CLK_HROW_LH5_1", - "CLK_HROW_LH5_2", - "CLK_HROW_LH5_3", - "CLK_HROW_LH5_4", - "CLK_HROW_LH5_5", - "CLK_HROW_LH5_6", - "CLK_HROW_LH5_7", - "CLK_HROW_LH6_0", - "CLK_HROW_LH6_1", - "CLK_HROW_LH6_2", - "CLK_HROW_LH6_3", - "CLK_HROW_LH6_4", - "CLK_HROW_LH6_5", - "CLK_HROW_LH6_6", - "CLK_HROW_LH6_7", - "CLK_HROW_LH7_0", - "CLK_HROW_LH7_1", - "CLK_HROW_LH7_2", - "CLK_HROW_LH7_3", - "CLK_HROW_LH7_4", - "CLK_HROW_LH7_5", - "CLK_HROW_LH7_6", - "CLK_HROW_LH7_7", - "CLK_HROW_LH8_0", - "CLK_HROW_LH8_1", - "CLK_HROW_LH8_2", - "CLK_HROW_LH8_3", - "CLK_HROW_LH8_4", - "CLK_HROW_LH8_5", - "CLK_HROW_LH8_6", - "CLK_HROW_LH8_7", - "CLK_HROW_LH9_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH9_2", - "CLK_HROW_LH9_3", - "CLK_HROW_LH9_4", - "CLK_HROW_LH9_5", - "CLK_HROW_LH9_6", - "CLK_HROW_LH9_7", - "CLK_HROW_LOGIC_OUTS_B0_0", - "CLK_HROW_LOGIC_OUTS_B0_1", - "CLK_HROW_LOGIC_OUTS_B0_2", - "CLK_HROW_LOGIC_OUTS_B0_3", - "CLK_HROW_LOGIC_OUTS_B0_4", - "CLK_HROW_LOGIC_OUTS_B0_5", - "CLK_HROW_LOGIC_OUTS_B0_6", - "CLK_HROW_LOGIC_OUTS_B0_7", - "CLK_HROW_LOGIC_OUTS_B10_0", - "CLK_HROW_LOGIC_OUTS_B10_1", - "CLK_HROW_LOGIC_OUTS_B10_2", - "CLK_HROW_LOGIC_OUTS_B10_3", - "CLK_HROW_LOGIC_OUTS_B10_4", - "CLK_HROW_LOGIC_OUTS_B10_5", - "CLK_HROW_LOGIC_OUTS_B10_6", - "CLK_HROW_LOGIC_OUTS_B10_7", - "CLK_HROW_LOGIC_OUTS_B11_0", - "CLK_HROW_LOGIC_OUTS_B11_1", - "CLK_HROW_LOGIC_OUTS_B11_2", - "CLK_HROW_LOGIC_OUTS_B11_3", - "CLK_HROW_LOGIC_OUTS_B11_4", - "CLK_HROW_LOGIC_OUTS_B11_5", - "CLK_HROW_LOGIC_OUTS_B11_6", - "CLK_HROW_LOGIC_OUTS_B11_7", - "CLK_HROW_LOGIC_OUTS_B12_0", - "CLK_HROW_LOGIC_OUTS_B12_1", - "CLK_HROW_LOGIC_OUTS_B12_2", - "CLK_HROW_LOGIC_OUTS_B12_3", - "CLK_HROW_LOGIC_OUTS_B12_4", - "CLK_HROW_LOGIC_OUTS_B12_5", - "CLK_HROW_LOGIC_OUTS_B12_6", - "CLK_HROW_LOGIC_OUTS_B12_7", - "CLK_HROW_LOGIC_OUTS_B13_0", - "CLK_HROW_LOGIC_OUTS_B13_1", - "CLK_HROW_LOGIC_OUTS_B13_2", - "CLK_HROW_LOGIC_OUTS_B13_3", - "CLK_HROW_LOGIC_OUTS_B13_4", - "CLK_HROW_LOGIC_OUTS_B13_5", - "CLK_HROW_LOGIC_OUTS_B13_6", - "CLK_HROW_LOGIC_OUTS_B13_7", - "CLK_HROW_LOGIC_OUTS_B14_0", - "CLK_HROW_LOGIC_OUTS_B14_1", - "CLK_HROW_LOGIC_OUTS_B14_2", - "CLK_HROW_LOGIC_OUTS_B14_3", - "CLK_HROW_LOGIC_OUTS_B14_4", - "CLK_HROW_LOGIC_OUTS_B14_5", - "CLK_HROW_LOGIC_OUTS_B14_6", - "CLK_HROW_LOGIC_OUTS_B14_7", - "CLK_HROW_LOGIC_OUTS_B15_0", - "CLK_HROW_LOGIC_OUTS_B15_1", - "CLK_HROW_LOGIC_OUTS_B15_2", - "CLK_HROW_LOGIC_OUTS_B15_3", - "CLK_HROW_LOGIC_OUTS_B15_4", - "CLK_HROW_LOGIC_OUTS_B15_5", - "CLK_HROW_LOGIC_OUTS_B15_6", - "CLK_HROW_LOGIC_OUTS_B15_7", - "CLK_HROW_LOGIC_OUTS_B16_0", - "CLK_HROW_LOGIC_OUTS_B16_1", - "CLK_HROW_LOGIC_OUTS_B16_2", - "CLK_HROW_LOGIC_OUTS_B16_3", - "CLK_HROW_LOGIC_OUTS_B16_4", - "CLK_HROW_LOGIC_OUTS_B16_5", - "CLK_HROW_LOGIC_OUTS_B16_6", - "CLK_HROW_LOGIC_OUTS_B16_7", - "CLK_HROW_LOGIC_OUTS_B17_0", - "CLK_HROW_LOGIC_OUTS_B17_1", - "CLK_HROW_LOGIC_OUTS_B17_2", - "CLK_HROW_LOGIC_OUTS_B17_3", - "CLK_HROW_LOGIC_OUTS_B17_4", - "CLK_HROW_LOGIC_OUTS_B17_5", - "CLK_HROW_LOGIC_OUTS_B17_6", - "CLK_HROW_LOGIC_OUTS_B17_7", - "CLK_HROW_LOGIC_OUTS_B18_0", - "CLK_HROW_LOGIC_OUTS_B18_1", - "CLK_HROW_LOGIC_OUTS_B18_2", - "CLK_HROW_LOGIC_OUTS_B18_3", - "CLK_HROW_LOGIC_OUTS_B18_4", - "CLK_HROW_LOGIC_OUTS_B18_5", - "CLK_HROW_LOGIC_OUTS_B18_6", - "CLK_HROW_LOGIC_OUTS_B18_7", - "CLK_HROW_LOGIC_OUTS_B19_0", - "CLK_HROW_LOGIC_OUTS_B19_1", - "CLK_HROW_LOGIC_OUTS_B19_2", - "CLK_HROW_LOGIC_OUTS_B19_3", - "CLK_HROW_LOGIC_OUTS_B19_4", - "CLK_HROW_LOGIC_OUTS_B19_5", - "CLK_HROW_LOGIC_OUTS_B19_6", - "CLK_HROW_LOGIC_OUTS_B19_7", - "CLK_HROW_LOGIC_OUTS_B1_0", - "CLK_HROW_LOGIC_OUTS_B1_1", - "CLK_HROW_LOGIC_OUTS_B1_2", - "CLK_HROW_LOGIC_OUTS_B1_3", - "CLK_HROW_LOGIC_OUTS_B1_4", - "CLK_HROW_LOGIC_OUTS_B1_5", - "CLK_HROW_LOGIC_OUTS_B1_6", - "CLK_HROW_LOGIC_OUTS_B1_7", - "CLK_HROW_LOGIC_OUTS_B20_0", - "CLK_HROW_LOGIC_OUTS_B20_1", - "CLK_HROW_LOGIC_OUTS_B20_2", - "CLK_HROW_LOGIC_OUTS_B20_3", - "CLK_HROW_LOGIC_OUTS_B20_4", - "CLK_HROW_LOGIC_OUTS_B20_5", - "CLK_HROW_LOGIC_OUTS_B20_6", - "CLK_HROW_LOGIC_OUTS_B20_7", - "CLK_HROW_LOGIC_OUTS_B21_0", - "CLK_HROW_LOGIC_OUTS_B21_1", - "CLK_HROW_LOGIC_OUTS_B21_2", - "CLK_HROW_LOGIC_OUTS_B21_3", - "CLK_HROW_LOGIC_OUTS_B21_4", - "CLK_HROW_LOGIC_OUTS_B21_5", - "CLK_HROW_LOGIC_OUTS_B21_6", - "CLK_HROW_LOGIC_OUTS_B21_7", - "CLK_HROW_LOGIC_OUTS_B22_0", - "CLK_HROW_LOGIC_OUTS_B22_1", - "CLK_HROW_LOGIC_OUTS_B22_2", - "CLK_HROW_LOGIC_OUTS_B22_3", - "CLK_HROW_LOGIC_OUTS_B22_4", - "CLK_HROW_LOGIC_OUTS_B22_5", - "CLK_HROW_LOGIC_OUTS_B22_6", - "CLK_HROW_LOGIC_OUTS_B22_7", - "CLK_HROW_LOGIC_OUTS_B23_0", - "CLK_HROW_LOGIC_OUTS_B23_1", - "CLK_HROW_LOGIC_OUTS_B23_2", - "CLK_HROW_LOGIC_OUTS_B23_3", - "CLK_HROW_LOGIC_OUTS_B23_4", - "CLK_HROW_LOGIC_OUTS_B23_5", - "CLK_HROW_LOGIC_OUTS_B23_6", - "CLK_HROW_LOGIC_OUTS_B23_7", - "CLK_HROW_LOGIC_OUTS_B2_0", - "CLK_HROW_LOGIC_OUTS_B2_1", - "CLK_HROW_LOGIC_OUTS_B2_2", - "CLK_HROW_LOGIC_OUTS_B2_3", - "CLK_HROW_LOGIC_OUTS_B2_4", - "CLK_HROW_LOGIC_OUTS_B2_5", - "CLK_HROW_LOGIC_OUTS_B2_6", - "CLK_HROW_LOGIC_OUTS_B2_7", - "CLK_HROW_LOGIC_OUTS_B3_0", - "CLK_HROW_LOGIC_OUTS_B3_1", - "CLK_HROW_LOGIC_OUTS_B3_2", - "CLK_HROW_LOGIC_OUTS_B3_3", - "CLK_HROW_LOGIC_OUTS_B3_4", - "CLK_HROW_LOGIC_OUTS_B3_5", - "CLK_HROW_LOGIC_OUTS_B3_6", - "CLK_HROW_LOGIC_OUTS_B3_7", - "CLK_HROW_LOGIC_OUTS_B4_0", - "CLK_HROW_LOGIC_OUTS_B4_1", - "CLK_HROW_LOGIC_OUTS_B4_2", - "CLK_HROW_LOGIC_OUTS_B4_3", - "CLK_HROW_LOGIC_OUTS_B4_4", - "CLK_HROW_LOGIC_OUTS_B4_5", - "CLK_HROW_LOGIC_OUTS_B4_6", - "CLK_HROW_LOGIC_OUTS_B4_7", - "CLK_HROW_LOGIC_OUTS_B5_0", - "CLK_HROW_LOGIC_OUTS_B5_1", - "CLK_HROW_LOGIC_OUTS_B5_2", - "CLK_HROW_LOGIC_OUTS_B5_3", - "CLK_HROW_LOGIC_OUTS_B5_4", - "CLK_HROW_LOGIC_OUTS_B5_5", - "CLK_HROW_LOGIC_OUTS_B5_6", - "CLK_HROW_LOGIC_OUTS_B5_7", - "CLK_HROW_LOGIC_OUTS_B6_0", - "CLK_HROW_LOGIC_OUTS_B6_1", - "CLK_HROW_LOGIC_OUTS_B6_2", - "CLK_HROW_LOGIC_OUTS_B6_3", - "CLK_HROW_LOGIC_OUTS_B6_4", - "CLK_HROW_LOGIC_OUTS_B6_5", - "CLK_HROW_LOGIC_OUTS_B6_6", - "CLK_HROW_LOGIC_OUTS_B6_7", - "CLK_HROW_LOGIC_OUTS_B7_0", - "CLK_HROW_LOGIC_OUTS_B7_1", - "CLK_HROW_LOGIC_OUTS_B7_2", - "CLK_HROW_LOGIC_OUTS_B7_3", - "CLK_HROW_LOGIC_OUTS_B7_4", - "CLK_HROW_LOGIC_OUTS_B7_5", - "CLK_HROW_LOGIC_OUTS_B7_6", - "CLK_HROW_LOGIC_OUTS_B7_7", - "CLK_HROW_LOGIC_OUTS_B8_0", - "CLK_HROW_LOGIC_OUTS_B8_1", - "CLK_HROW_LOGIC_OUTS_B8_2", - "CLK_HROW_LOGIC_OUTS_B8_3", - "CLK_HROW_LOGIC_OUTS_B8_4", - "CLK_HROW_LOGIC_OUTS_B8_5", - "CLK_HROW_LOGIC_OUTS_B8_6", - "CLK_HROW_LOGIC_OUTS_B8_7", - "CLK_HROW_LOGIC_OUTS_B9_0", - "CLK_HROW_LOGIC_OUTS_B9_1", - "CLK_HROW_LOGIC_OUTS_B9_2", - "CLK_HROW_LOGIC_OUTS_B9_3", - "CLK_HROW_LOGIC_OUTS_B9_4", - "CLK_HROW_LOGIC_OUTS_B9_5", - "CLK_HROW_LOGIC_OUTS_B9_6", - "CLK_HROW_LOGIC_OUTS_B9_7", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_MONITOR_N_4", - "CLK_HROW_MONITOR_N_5", - "CLK_HROW_MONITOR_N_6", - "CLK_HROW_MONITOR_N_7", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_MONITOR_P_4", - "CLK_HROW_MONITOR_P_5", - "CLK_HROW_MONITOR_P_6", - "CLK_HROW_MONITOR_P_7", - "CLK_HROW_NE2A0_0", - "CLK_HROW_NE2A0_1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A0_3", - "CLK_HROW_NE2A0_4", - "CLK_HROW_NE2A0_5", - "CLK_HROW_NE2A0_6", - "CLK_HROW_NE2A0_7", - "CLK_HROW_NE2A1_0", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NE2A1_2", - "CLK_HROW_NE2A1_3", - "CLK_HROW_NE2A1_4", - "CLK_HROW_NE2A1_5", - "CLK_HROW_NE2A1_6", - "CLK_HROW_NE2A1_7", - "CLK_HROW_NE2A2_0", - "CLK_HROW_NE2A2_1", - "CLK_HROW_NE2A2_2", - "CLK_HROW_NE2A2_3", - "CLK_HROW_NE2A2_4", - "CLK_HROW_NE2A2_5", - "CLK_HROW_NE2A2_6", - "CLK_HROW_NE2A2_7", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NE2A3_1", - "CLK_HROW_NE2A3_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_NE2A3_4", - "CLK_HROW_NE2A3_5", - "CLK_HROW_NE2A3_6", - "CLK_HROW_NE2A3_7", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_NE4BEG0_4", - "CLK_HROW_NE4BEG0_5", - "CLK_HROW_NE4BEG0_6", - "CLK_HROW_NE4BEG0_7", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG1_4", - "CLK_HROW_NE4BEG1_5", - "CLK_HROW_NE4BEG1_6", - "CLK_HROW_NE4BEG1_7", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NE4BEG2_4", - "CLK_HROW_NE4BEG2_5", - "CLK_HROW_NE4BEG2_6", - "CLK_HROW_NE4BEG2_7", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_NE4BEG3_4", - "CLK_HROW_NE4BEG3_5", - "CLK_HROW_NE4BEG3_6", - "CLK_HROW_NE4BEG3_7", - "CLK_HROW_NE4C0_0", - "CLK_HROW_NE4C0_1", - "CLK_HROW_NE4C0_2", - "CLK_HROW_NE4C0_3", - "CLK_HROW_NE4C0_4", - "CLK_HROW_NE4C0_5", - "CLK_HROW_NE4C0_6", - "CLK_HROW_NE4C0_7", - "CLK_HROW_NE4C1_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_NE4C1_3", - "CLK_HROW_NE4C1_4", - "CLK_HROW_NE4C1_5", - "CLK_HROW_NE4C1_6", - "CLK_HROW_NE4C1_7", - "CLK_HROW_NE4C2_0", - "CLK_HROW_NE4C2_1", - "CLK_HROW_NE4C2_2", - "CLK_HROW_NE4C2_3", - "CLK_HROW_NE4C2_4", - "CLK_HROW_NE4C2_5", - "CLK_HROW_NE4C2_6", - "CLK_HROW_NE4C2_7", - "CLK_HROW_NE4C3_0", - "CLK_HROW_NE4C3_1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_NE4C3_3", - "CLK_HROW_NE4C3_4", - "CLK_HROW_NE4C3_5", - "CLK_HROW_NE4C3_6", - "CLK_HROW_NE4C3_7", - "CLK_HROW_NW2A0_0", - "CLK_HROW_NW2A0_1", - "CLK_HROW_NW2A0_2", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NW2A0_4", - "CLK_HROW_NW2A0_5", - "CLK_HROW_NW2A0_6", - "CLK_HROW_NW2A0_7", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_NW2A1_2", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A1_4", - "CLK_HROW_NW2A1_5", - "CLK_HROW_NW2A1_6", - "CLK_HROW_NW2A1_7", - "CLK_HROW_NW2A2_0", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW2A2_3", - "CLK_HROW_NW2A2_4", - "CLK_HROW_NW2A2_5", - "CLK_HROW_NW2A2_6", - "CLK_HROW_NW2A2_7", - "CLK_HROW_NW2A3_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_NW2A3_2", - "CLK_HROW_NW2A3_3", - "CLK_HROW_NW2A3_4", - "CLK_HROW_NW2A3_5", - "CLK_HROW_NW2A3_6", - "CLK_HROW_NW2A3_7", - "CLK_HROW_NW4A0_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_NW4A0_3", - "CLK_HROW_NW4A0_4", - "CLK_HROW_NW4A0_5", - "CLK_HROW_NW4A0_6", - "CLK_HROW_NW4A0_7", - "CLK_HROW_NW4A1_0", - "CLK_HROW_NW4A1_1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_NW4A1_3", - "CLK_HROW_NW4A1_4", - "CLK_HROW_NW4A1_5", - "CLK_HROW_NW4A1_6", - "CLK_HROW_NW4A1_7", - "CLK_HROW_NW4A2_0", - "CLK_HROW_NW4A2_1", - "CLK_HROW_NW4A2_2", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A2_4", - "CLK_HROW_NW4A2_5", - "CLK_HROW_NW4A2_6", - "CLK_HROW_NW4A2_7", - "CLK_HROW_NW4A3_0", - "CLK_HROW_NW4A3_1", - "CLK_HROW_NW4A3_2", - "CLK_HROW_NW4A3_3", - "CLK_HROW_NW4A3_4", - "CLK_HROW_NW4A3_5", - "CLK_HROW_NW4A3_6", - "CLK_HROW_NW4A3_7", - "CLK_HROW_NW4END0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_NW4END0_3", - "CLK_HROW_NW4END0_4", - "CLK_HROW_NW4END0_5", - "CLK_HROW_NW4END0_6", - "CLK_HROW_NW4END0_7", - "CLK_HROW_NW4END1_0", - "CLK_HROW_NW4END1_1", - "CLK_HROW_NW4END1_2", - "CLK_HROW_NW4END1_3", - "CLK_HROW_NW4END1_4", - "CLK_HROW_NW4END1_5", - "CLK_HROW_NW4END1_6", - "CLK_HROW_NW4END1_7", - "CLK_HROW_NW4END2_0", - "CLK_HROW_NW4END2_1", - "CLK_HROW_NW4END2_2", - "CLK_HROW_NW4END2_3", - "CLK_HROW_NW4END2_4", - "CLK_HROW_NW4END2_5", - "CLK_HROW_NW4END2_6", - "CLK_HROW_NW4END2_7", - "CLK_HROW_NW4END3_0", - "CLK_HROW_NW4END3_1", - "CLK_HROW_NW4END3_2", - "CLK_HROW_NW4END3_3", - "CLK_HROW_NW4END3_4", - "CLK_HROW_NW4END3_5", - "CLK_HROW_NW4END3_6", - "CLK_HROW_NW4END3_7", - "CLK_HROW_REFCK_EASTCLK0", - "CLK_HROW_REFCK_EASTCLK1", - "CLK_HROW_REFCK_WESTCLK0", - "CLK_HROW_REFCK_WESTCLK1", - "CLK_HROW_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK9", - "CLK_HROW_SE2A0_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_SE2A0_3", - "CLK_HROW_SE2A0_4", - "CLK_HROW_SE2A0_5", - "CLK_HROW_SE2A0_6", - "CLK_HROW_SE2A0_7", - "CLK_HROW_SE2A1_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_SE2A1_2", - "CLK_HROW_SE2A1_3", - "CLK_HROW_SE2A1_4", - "CLK_HROW_SE2A1_5", - "CLK_HROW_SE2A1_6", - "CLK_HROW_SE2A1_7", - "CLK_HROW_SE2A2_0", - "CLK_HROW_SE2A2_1", - "CLK_HROW_SE2A2_2", - "CLK_HROW_SE2A2_3", - "CLK_HROW_SE2A2_4", - "CLK_HROW_SE2A2_5", - "CLK_HROW_SE2A2_6", - "CLK_HROW_SE2A2_7", - "CLK_HROW_SE2A3_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_SE2A3_2", - "CLK_HROW_SE2A3_3", - "CLK_HROW_SE2A3_4", - "CLK_HROW_SE2A3_5", - "CLK_HROW_SE2A3_6", - "CLK_HROW_SE2A3_7", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_SE4BEG0_4", - "CLK_HROW_SE4BEG0_5", - "CLK_HROW_SE4BEG0_6", - "CLK_HROW_SE4BEG0_7", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_SE4BEG1_4", - "CLK_HROW_SE4BEG1_5", - "CLK_HROW_SE4BEG1_6", - "CLK_HROW_SE4BEG1_7", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_SE4BEG2_4", - "CLK_HROW_SE4BEG2_5", - "CLK_HROW_SE4BEG2_6", - "CLK_HROW_SE4BEG2_7", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_SE4BEG3_4", - "CLK_HROW_SE4BEG3_5", - "CLK_HROW_SE4BEG3_6", - "CLK_HROW_SE4BEG3_7", - "CLK_HROW_SE4C0_0", - "CLK_HROW_SE4C0_1", - "CLK_HROW_SE4C0_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_SE4C0_4", - "CLK_HROW_SE4C0_5", - "CLK_HROW_SE4C0_6", - "CLK_HROW_SE4C0_7", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SE4C1_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_SE4C1_3", - "CLK_HROW_SE4C1_4", - "CLK_HROW_SE4C1_5", - "CLK_HROW_SE4C1_6", - "CLK_HROW_SE4C1_7", - "CLK_HROW_SE4C2_0", - "CLK_HROW_SE4C2_1", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SE4C2_3", - "CLK_HROW_SE4C2_4", - "CLK_HROW_SE4C2_5", - "CLK_HROW_SE4C2_6", - "CLK_HROW_SE4C2_7", - "CLK_HROW_SE4C3_0", - "CLK_HROW_SE4C3_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_SE4C3_4", - "CLK_HROW_SE4C3_5", - "CLK_HROW_SE4C3_6", - "CLK_HROW_SE4C3_7", - "CLK_HROW_SW2A0_0", - "CLK_HROW_SW2A0_1", - "CLK_HROW_SW2A0_2", - "CLK_HROW_SW2A0_3", - "CLK_HROW_SW2A0_4", - "CLK_HROW_SW2A0_5", - "CLK_HROW_SW2A0_6", - "CLK_HROW_SW2A0_7", - "CLK_HROW_SW2A1_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_SW2A1_3", - "CLK_HROW_SW2A1_4", - "CLK_HROW_SW2A1_5", - "CLK_HROW_SW2A1_6", - "CLK_HROW_SW2A1_7", - "CLK_HROW_SW2A2_0", - "CLK_HROW_SW2A2_1", - "CLK_HROW_SW2A2_2", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SW2A2_4", - "CLK_HROW_SW2A2_5", - "CLK_HROW_SW2A2_6", - "CLK_HROW_SW2A2_7", - "CLK_HROW_SW2A3_0", - "CLK_HROW_SW2A3_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_SW2A3_3", - "CLK_HROW_SW2A3_4", - "CLK_HROW_SW2A3_5", - "CLK_HROW_SW2A3_6", - "CLK_HROW_SW2A3_7", - "CLK_HROW_SW4A0_0", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_SW4A0_4", - "CLK_HROW_SW4A0_5", - "CLK_HROW_SW4A0_6", - "CLK_HROW_SW4A0_7", - "CLK_HROW_SW4A1_0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_SW4A1_2", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A1_4", - "CLK_HROW_SW4A1_5", - "CLK_HROW_SW4A1_6", - "CLK_HROW_SW4A1_7", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_1", - "CLK_HROW_SW4A2_2", - "CLK_HROW_SW4A2_3", - "CLK_HROW_SW4A2_4", - "CLK_HROW_SW4A2_5", - "CLK_HROW_SW4A2_6", - "CLK_HROW_SW4A2_7", - "CLK_HROW_SW4A3_0", - "CLK_HROW_SW4A3_1", - "CLK_HROW_SW4A3_2", - "CLK_HROW_SW4A3_3", - "CLK_HROW_SW4A3_4", - "CLK_HROW_SW4A3_5", - "CLK_HROW_SW4A3_6", - "CLK_HROW_SW4A3_7", - "CLK_HROW_SW4END0_0", - "CLK_HROW_SW4END0_1", - "CLK_HROW_SW4END0_2", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW4END0_4", - "CLK_HROW_SW4END0_5", - "CLK_HROW_SW4END0_6", - "CLK_HROW_SW4END0_7", - "CLK_HROW_SW4END1_0", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SW4END1_2", - "CLK_HROW_SW4END1_3", - "CLK_HROW_SW4END1_4", - "CLK_HROW_SW4END1_5", - "CLK_HROW_SW4END1_6", - "CLK_HROW_SW4END1_7", - "CLK_HROW_SW4END2_0", - "CLK_HROW_SW4END2_1", - "CLK_HROW_SW4END2_2", - "CLK_HROW_SW4END2_3", - "CLK_HROW_SW4END2_4", - "CLK_HROW_SW4END2_5", - "CLK_HROW_SW4END2_6", - "CLK_HROW_SW4END2_7", - "CLK_HROW_SW4END3_0", - "CLK_HROW_SW4END3_1", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_SW4END3_4", - "CLK_HROW_SW4END3_5", - "CLK_HROW_SW4END3_6", - "CLK_HROW_SW4END3_7", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_1", - "CLK_HROW_WL1END0_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_WL1END0_4", - "CLK_HROW_WL1END0_5", - "CLK_HROW_WL1END0_6", - "CLK_HROW_WL1END0_7", - "CLK_HROW_WL1END1_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_WL1END1_4", - "CLK_HROW_WL1END1_5", - "CLK_HROW_WL1END1_6", - "CLK_HROW_WL1END1_7", - "CLK_HROW_WL1END2_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WL1END2_4", - "CLK_HROW_WL1END2_5", - "CLK_HROW_WL1END2_6", - "CLK_HROW_WL1END2_7", - "CLK_HROW_WL1END3_0", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WL1END3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_WL1END3_4", - "CLK_HROW_WL1END3_5", - "CLK_HROW_WL1END3_6", - "CLK_HROW_WL1END3_7", - "CLK_HROW_WR1END0_0", - "CLK_HROW_WR1END0_1", - "CLK_HROW_WR1END0_2", - "CLK_HROW_WR1END0_3", - "CLK_HROW_WR1END0_4", - "CLK_HROW_WR1END0_5", - "CLK_HROW_WR1END0_6", - "CLK_HROW_WR1END0_7", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WR1END1_1", - "CLK_HROW_WR1END1_2", - "CLK_HROW_WR1END1_3", - "CLK_HROW_WR1END1_4", - "CLK_HROW_WR1END1_5", - "CLK_HROW_WR1END1_6", - "CLK_HROW_WR1END1_7", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WR1END2_1", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WR1END2_4", - "CLK_HROW_WR1END2_5", - "CLK_HROW_WR1END2_6", - "CLK_HROW_WR1END2_7", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_WR1END3_2", - "CLK_HROW_WR1END3_3", - "CLK_HROW_WR1END3_4", - "CLK_HROW_WR1END3_5", - "CLK_HROW_WR1END3_6", - "CLK_HROW_WR1END3_7", - "CLK_HROW_WW2A0_0", - "CLK_HROW_WW2A0_1", - "CLK_HROW_WW2A0_2", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW2A0_4", - "CLK_HROW_WW2A0_5", - "CLK_HROW_WW2A0_6", - "CLK_HROW_WW2A0_7", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WW2A1_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_WW2A1_3", - "CLK_HROW_WW2A1_4", - "CLK_HROW_WW2A1_5", - "CLK_HROW_WW2A1_6", - "CLK_HROW_WW2A1_7", - "CLK_HROW_WW2A2_0", - "CLK_HROW_WW2A2_1", - "CLK_HROW_WW2A2_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_WW2A2_4", - "CLK_HROW_WW2A2_5", - "CLK_HROW_WW2A2_6", - "CLK_HROW_WW2A2_7", - "CLK_HROW_WW2A3_0", - "CLK_HROW_WW2A3_1", - "CLK_HROW_WW2A3_2", - "CLK_HROW_WW2A3_3", - "CLK_HROW_WW2A3_4", - "CLK_HROW_WW2A3_5", - "CLK_HROW_WW2A3_6", - "CLK_HROW_WW2A3_7", - "CLK_HROW_WW2END0_0", - "CLK_HROW_WW2END0_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_WW2END0_3", - "CLK_HROW_WW2END0_4", - "CLK_HROW_WW2END0_5", - "CLK_HROW_WW2END0_6", - "CLK_HROW_WW2END0_7", - "CLK_HROW_WW2END1_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_WW2END1_2", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW2END1_4", - "CLK_HROW_WW2END1_5", - "CLK_HROW_WW2END1_6", - "CLK_HROW_WW2END1_7", - "CLK_HROW_WW2END2_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW2END2_4", - "CLK_HROW_WW2END2_5", - "CLK_HROW_WW2END2_6", - "CLK_HROW_WW2END2_7", - "CLK_HROW_WW2END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_WW2END3_2", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW2END3_4", - "CLK_HROW_WW2END3_5", - "CLK_HROW_WW2END3_6", - "CLK_HROW_WW2END3_7", - "CLK_HROW_WW4A0_0", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4A0_2", - "CLK_HROW_WW4A0_3", - "CLK_HROW_WW4A0_4", - "CLK_HROW_WW4A0_5", - "CLK_HROW_WW4A0_6", - "CLK_HROW_WW4A0_7", - "CLK_HROW_WW4A1_0", - "CLK_HROW_WW4A1_1", - "CLK_HROW_WW4A1_2", - "CLK_HROW_WW4A1_3", - "CLK_HROW_WW4A1_4", - "CLK_HROW_WW4A1_5", - "CLK_HROW_WW4A1_6", - "CLK_HROW_WW4A1_7", - "CLK_HROW_WW4A2_0", - "CLK_HROW_WW4A2_1", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW4A2_3", - "CLK_HROW_WW4A2_4", - "CLK_HROW_WW4A2_5", - "CLK_HROW_WW4A2_6", - "CLK_HROW_WW4A2_7", - "CLK_HROW_WW4A3_0", - "CLK_HROW_WW4A3_1", - "CLK_HROW_WW4A3_2", - "CLK_HROW_WW4A3_3", - "CLK_HROW_WW4A3_4", - "CLK_HROW_WW4A3_5", - "CLK_HROW_WW4A3_6", - "CLK_HROW_WW4A3_7", - "CLK_HROW_WW4B0_0", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4B0_2", - "CLK_HROW_WW4B0_3", - "CLK_HROW_WW4B0_4", - "CLK_HROW_WW4B0_5", - "CLK_HROW_WW4B0_6", - "CLK_HROW_WW4B0_7", - "CLK_HROW_WW4B1_0", - "CLK_HROW_WW4B1_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_WW4B1_3", - "CLK_HROW_WW4B1_4", - "CLK_HROW_WW4B1_5", - "CLK_HROW_WW4B1_6", - "CLK_HROW_WW4B1_7", - "CLK_HROW_WW4B2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_WW4B2_2", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4B2_4", - "CLK_HROW_WW4B2_5", - "CLK_HROW_WW4B2_6", - "CLK_HROW_WW4B2_7", - "CLK_HROW_WW4B3_0", - "CLK_HROW_WW4B3_1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_WW4B3_3", - "CLK_HROW_WW4B3_4", - "CLK_HROW_WW4B3_5", - "CLK_HROW_WW4B3_6", - "CLK_HROW_WW4B3_7", - "CLK_HROW_WW4C0_0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_WW4C0_2", - "CLK_HROW_WW4C0_3", - "CLK_HROW_WW4C0_4", - "CLK_HROW_WW4C0_5", - "CLK_HROW_WW4C0_6", - "CLK_HROW_WW4C0_7", - "CLK_HROW_WW4C1_0", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WW4C1_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_WW4C1_4", - "CLK_HROW_WW4C1_5", - "CLK_HROW_WW4C1_6", - "CLK_HROW_WW4C1_7", - "CLK_HROW_WW4C2_0", - "CLK_HROW_WW4C2_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_WW4C2_3", - "CLK_HROW_WW4C2_4", - "CLK_HROW_WW4C2_5", - "CLK_HROW_WW4C2_6", - "CLK_HROW_WW4C2_7", - "CLK_HROW_WW4C3_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_WW4C3_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_WW4C3_4", - "CLK_HROW_WW4C3_5", - "CLK_HROW_WW4C3_6", - "CLK_HROW_WW4C3_7", - "CLK_HROW_WW4END0_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW4END0_2", - "CLK_HROW_WW4END0_3", - "CLK_HROW_WW4END0_4", - "CLK_HROW_WW4END0_5", - "CLK_HROW_WW4END0_6", - "CLK_HROW_WW4END0_7", - "CLK_HROW_WW4END1_0", - "CLK_HROW_WW4END1_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_WW4END1_3", - "CLK_HROW_WW4END1_4", - "CLK_HROW_WW4END1_5", - "CLK_HROW_WW4END1_6", - "CLK_HROW_WW4END1_7", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_WW4END2_3", - "CLK_HROW_WW4END2_4", - "CLK_HROW_WW4END2_5", - "CLK_HROW_WW4END2_6", - "CLK_HROW_WW4END2_7", - "CLK_HROW_WW4END3_0", - "CLK_HROW_WW4END3_1", - "CLK_HROW_WW4END3_2", - "CLK_HROW_WW4END3_3", - "CLK_HROW_WW4END3_4", - "CLK_HROW_WW4END3_5", - "CLK_HROW_WW4END3_6", - "CLK_HROW_WW4END3_7" - ] + "wires": { + "CLK_HROW_BLOCK_OUTS_B0_0": null, + "CLK_HROW_BLOCK_OUTS_B0_1": null, + "CLK_HROW_BLOCK_OUTS_B0_2": null, + "CLK_HROW_BLOCK_OUTS_B0_3": null, + "CLK_HROW_BLOCK_OUTS_B0_4": null, + "CLK_HROW_BLOCK_OUTS_B0_5": null, + "CLK_HROW_BLOCK_OUTS_B0_6": null, + "CLK_HROW_BLOCK_OUTS_B0_7": null, + "CLK_HROW_BLOCK_OUTS_B1_0": null, + "CLK_HROW_BLOCK_OUTS_B1_1": null, + "CLK_HROW_BLOCK_OUTS_B1_2": null, + "CLK_HROW_BLOCK_OUTS_B1_3": null, + "CLK_HROW_BLOCK_OUTS_B1_4": null, + "CLK_HROW_BLOCK_OUTS_B1_5": null, + "CLK_HROW_BLOCK_OUTS_B1_6": null, + "CLK_HROW_BLOCK_OUTS_B1_7": null, + "CLK_HROW_BLOCK_OUTS_B2_0": null, + "CLK_HROW_BLOCK_OUTS_B2_1": null, + "CLK_HROW_BLOCK_OUTS_B2_2": null, + "CLK_HROW_BLOCK_OUTS_B2_3": null, + "CLK_HROW_BLOCK_OUTS_B2_4": null, + "CLK_HROW_BLOCK_OUTS_B2_5": null, + "CLK_HROW_BLOCK_OUTS_B2_6": null, + "CLK_HROW_BLOCK_OUTS_B2_7": null, + "CLK_HROW_BLOCK_OUTS_B3_0": null, + "CLK_HROW_BLOCK_OUTS_B3_1": null, + "CLK_HROW_BLOCK_OUTS_B3_2": null, + "CLK_HROW_BLOCK_OUTS_B3_3": null, + "CLK_HROW_BLOCK_OUTS_B3_4": null, + "CLK_HROW_BLOCK_OUTS_B3_5": null, + "CLK_HROW_BLOCK_OUTS_B3_6": null, + "CLK_HROW_BLOCK_OUTS_B3_7": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN0": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN1": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN10": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN11": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN12": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN13": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN14": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN15": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN16": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN17": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN18": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN19": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN2": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN20": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN21": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN22": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN23": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN24": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN25": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN26": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN27": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN28": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN29": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN3": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN30": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN31": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN4": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN5": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN6": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN7": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN8": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCIN9": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO0": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO1": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO10": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO11": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO12": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO13": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO14": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO15": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO16": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO17": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO18": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO19": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO2": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO20": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO21": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO22": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO23": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO24": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO25": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO26": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO27": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO28": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO29": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO3": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO30": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO31": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO4": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO5": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO6": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO7": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO8": null, + "CLK_HROW_BOT_R_CK_BUFG_CASCO9": null, + "CLK_HROW_BUFHCE_CE_L0": null, + "CLK_HROW_BUFHCE_CE_L1": null, + "CLK_HROW_BUFHCE_CE_L10": null, + "CLK_HROW_BUFHCE_CE_L11": null, + "CLK_HROW_BUFHCE_CE_L2": null, + "CLK_HROW_BUFHCE_CE_L3": null, + "CLK_HROW_BUFHCE_CE_L4": null, + "CLK_HROW_BUFHCE_CE_L5": null, + "CLK_HROW_BUFHCE_CE_L6": null, + "CLK_HROW_BUFHCE_CE_L7": null, + "CLK_HROW_BUFHCE_CE_L8": null, + "CLK_HROW_BUFHCE_CE_L9": null, + "CLK_HROW_BUFHCE_CE_R0": null, + "CLK_HROW_BUFHCE_CE_R1": null, + "CLK_HROW_BUFHCE_CE_R10": null, + "CLK_HROW_BUFHCE_CE_R11": null, + "CLK_HROW_BUFHCE_CE_R2": null, + "CLK_HROW_BUFHCE_CE_R3": null, + "CLK_HROW_BUFHCE_CE_R4": null, + "CLK_HROW_BUFHCE_CE_R5": null, + "CLK_HROW_BUFHCE_CE_R6": null, + "CLK_HROW_BUFHCE_CE_R7": null, + "CLK_HROW_BUFHCE_CE_R8": null, + "CLK_HROW_BUFHCE_CE_R9": null, + "CLK_HROW_BYP0_0": null, + "CLK_HROW_BYP0_1": null, + "CLK_HROW_BYP0_2": null, + "CLK_HROW_BYP0_3": null, + "CLK_HROW_BYP0_4": null, + "CLK_HROW_BYP0_5": null, + "CLK_HROW_BYP0_6": null, + "CLK_HROW_BYP0_7": null, + "CLK_HROW_BYP1_0": null, + "CLK_HROW_BYP1_1": null, + "CLK_HROW_BYP1_2": null, + "CLK_HROW_BYP1_3": null, + "CLK_HROW_BYP1_4": null, + "CLK_HROW_BYP1_5": null, + "CLK_HROW_BYP1_6": null, + "CLK_HROW_BYP1_7": null, + "CLK_HROW_BYP2_0": null, + "CLK_HROW_BYP2_1": null, + "CLK_HROW_BYP2_2": null, + "CLK_HROW_BYP2_3": null, + "CLK_HROW_BYP2_4": null, + "CLK_HROW_BYP2_5": null, + "CLK_HROW_BYP2_6": null, + "CLK_HROW_BYP2_7": null, + "CLK_HROW_BYP3_0": null, + "CLK_HROW_BYP3_1": null, + "CLK_HROW_BYP3_2": null, + "CLK_HROW_BYP3_3": null, + "CLK_HROW_BYP3_4": null, + "CLK_HROW_BYP3_5": null, + "CLK_HROW_BYP3_6": null, + "CLK_HROW_BYP3_7": null, + "CLK_HROW_BYP4_0": null, + "CLK_HROW_BYP4_1": null, + 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"CLK_HROW_WW2A3_3": null, + "CLK_HROW_WW2A3_4": null, + "CLK_HROW_WW2A3_5": null, + "CLK_HROW_WW2A3_6": null, + "CLK_HROW_WW2A3_7": null, + "CLK_HROW_WW2END0_0": null, + "CLK_HROW_WW2END0_1": null, + "CLK_HROW_WW2END0_2": null, + "CLK_HROW_WW2END0_3": null, + "CLK_HROW_WW2END0_4": null, + "CLK_HROW_WW2END0_5": null, + "CLK_HROW_WW2END0_6": null, + "CLK_HROW_WW2END0_7": null, + "CLK_HROW_WW2END1_0": null, + "CLK_HROW_WW2END1_1": null, + "CLK_HROW_WW2END1_2": null, + "CLK_HROW_WW2END1_3": null, + "CLK_HROW_WW2END1_4": null, + "CLK_HROW_WW2END1_5": null, + "CLK_HROW_WW2END1_6": null, + "CLK_HROW_WW2END1_7": null, + "CLK_HROW_WW2END2_0": null, + "CLK_HROW_WW2END2_1": null, + "CLK_HROW_WW2END2_2": null, + "CLK_HROW_WW2END2_3": null, + "CLK_HROW_WW2END2_4": null, + "CLK_HROW_WW2END2_5": null, + "CLK_HROW_WW2END2_6": null, + "CLK_HROW_WW2END2_7": null, + "CLK_HROW_WW2END3_0": null, + "CLK_HROW_WW2END3_1": null, + "CLK_HROW_WW2END3_2": null, + "CLK_HROW_WW2END3_3": null, + "CLK_HROW_WW2END3_4": null, + "CLK_HROW_WW2END3_5": null, + "CLK_HROW_WW2END3_6": null, + "CLK_HROW_WW2END3_7": null, + "CLK_HROW_WW4A0_0": null, + "CLK_HROW_WW4A0_1": null, + "CLK_HROW_WW4A0_2": null, + "CLK_HROW_WW4A0_3": null, + "CLK_HROW_WW4A0_4": null, + "CLK_HROW_WW4A0_5": null, + "CLK_HROW_WW4A0_6": null, + "CLK_HROW_WW4A0_7": null, + "CLK_HROW_WW4A1_0": null, + "CLK_HROW_WW4A1_1": null, + "CLK_HROW_WW4A1_2": null, + "CLK_HROW_WW4A1_3": null, + "CLK_HROW_WW4A1_4": null, + "CLK_HROW_WW4A1_5": null, + "CLK_HROW_WW4A1_6": null, + "CLK_HROW_WW4A1_7": null, + "CLK_HROW_WW4A2_0": null, + "CLK_HROW_WW4A2_1": null, + "CLK_HROW_WW4A2_2": null, + "CLK_HROW_WW4A2_3": null, + "CLK_HROW_WW4A2_4": null, + "CLK_HROW_WW4A2_5": null, + "CLK_HROW_WW4A2_6": null, + "CLK_HROW_WW4A2_7": null, + "CLK_HROW_WW4A3_0": null, + "CLK_HROW_WW4A3_1": null, + "CLK_HROW_WW4A3_2": null, + "CLK_HROW_WW4A3_3": null, + "CLK_HROW_WW4A3_4": null, + "CLK_HROW_WW4A3_5": null, + "CLK_HROW_WW4A3_6": null, + "CLK_HROW_WW4A3_7": null, + "CLK_HROW_WW4B0_0": null, + "CLK_HROW_WW4B0_1": null, + "CLK_HROW_WW4B0_2": null, + "CLK_HROW_WW4B0_3": null, + "CLK_HROW_WW4B0_4": null, + "CLK_HROW_WW4B0_5": null, + "CLK_HROW_WW4B0_6": null, + "CLK_HROW_WW4B0_7": null, + "CLK_HROW_WW4B1_0": null, + "CLK_HROW_WW4B1_1": null, + "CLK_HROW_WW4B1_2": null, + "CLK_HROW_WW4B1_3": null, + "CLK_HROW_WW4B1_4": null, + "CLK_HROW_WW4B1_5": null, + "CLK_HROW_WW4B1_6": null, + "CLK_HROW_WW4B1_7": null, + "CLK_HROW_WW4B2_0": null, + "CLK_HROW_WW4B2_1": null, + "CLK_HROW_WW4B2_2": null, + "CLK_HROW_WW4B2_3": null, + "CLK_HROW_WW4B2_4": null, + "CLK_HROW_WW4B2_5": null, + "CLK_HROW_WW4B2_6": null, + "CLK_HROW_WW4B2_7": null, + "CLK_HROW_WW4B3_0": null, + "CLK_HROW_WW4B3_1": null, + "CLK_HROW_WW4B3_2": null, + "CLK_HROW_WW4B3_3": null, + "CLK_HROW_WW4B3_4": null, + "CLK_HROW_WW4B3_5": null, + "CLK_HROW_WW4B3_6": null, + "CLK_HROW_WW4B3_7": null, + "CLK_HROW_WW4C0_0": null, + "CLK_HROW_WW4C0_1": null, + "CLK_HROW_WW4C0_2": null, + "CLK_HROW_WW4C0_3": null, + "CLK_HROW_WW4C0_4": null, + "CLK_HROW_WW4C0_5": null, + "CLK_HROW_WW4C0_6": null, + "CLK_HROW_WW4C0_7": null, + "CLK_HROW_WW4C1_0": null, + "CLK_HROW_WW4C1_1": null, + "CLK_HROW_WW4C1_2": null, + "CLK_HROW_WW4C1_3": null, + "CLK_HROW_WW4C1_4": null, + "CLK_HROW_WW4C1_5": null, + "CLK_HROW_WW4C1_6": null, + "CLK_HROW_WW4C1_7": null, + "CLK_HROW_WW4C2_0": null, + "CLK_HROW_WW4C2_1": null, + "CLK_HROW_WW4C2_2": null, + "CLK_HROW_WW4C2_3": null, + "CLK_HROW_WW4C2_4": null, + "CLK_HROW_WW4C2_5": null, + "CLK_HROW_WW4C2_6": null, + "CLK_HROW_WW4C2_7": null, + "CLK_HROW_WW4C3_0": null, + "CLK_HROW_WW4C3_1": null, + "CLK_HROW_WW4C3_2": null, + "CLK_HROW_WW4C3_3": null, + "CLK_HROW_WW4C3_4": null, + "CLK_HROW_WW4C3_5": null, + "CLK_HROW_WW4C3_6": null, + "CLK_HROW_WW4C3_7": null, + "CLK_HROW_WW4END0_0": null, + "CLK_HROW_WW4END0_1": null, + "CLK_HROW_WW4END0_2": null, + "CLK_HROW_WW4END0_3": null, + "CLK_HROW_WW4END0_4": null, + "CLK_HROW_WW4END0_5": null, + "CLK_HROW_WW4END0_6": null, + "CLK_HROW_WW4END0_7": null, + "CLK_HROW_WW4END1_0": null, + "CLK_HROW_WW4END1_1": null, + "CLK_HROW_WW4END1_2": null, + "CLK_HROW_WW4END1_3": null, + "CLK_HROW_WW4END1_4": null, + "CLK_HROW_WW4END1_5": null, + "CLK_HROW_WW4END1_6": null, + "CLK_HROW_WW4END1_7": null, + "CLK_HROW_WW4END2_0": null, + "CLK_HROW_WW4END2_1": null, + "CLK_HROW_WW4END2_2": null, + "CLK_HROW_WW4END2_3": null, + "CLK_HROW_WW4END2_4": null, + "CLK_HROW_WW4END2_5": null, + "CLK_HROW_WW4END2_6": null, + "CLK_HROW_WW4END2_7": null, + "CLK_HROW_WW4END3_0": null, + "CLK_HROW_WW4END3_1": null, + "CLK_HROW_WW4END3_2": null, + "CLK_HROW_WW4END3_3": null, + "CLK_HROW_WW4END3_4": null, + "CLK_HROW_WW4END3_5": null, + "CLK_HROW_WW4END3_6": null, + "CLK_HROW_WW4END3_7": null + } } diff --git a/kintex7/tile_type_CLK_HROW_TOP_R.json b/kintex7/tile_type_CLK_HROW_TOP_R.json index c2c6384..f71b63a 100644 --- a/kintex7/tile_type_CLK_HROW_TOP_R.json +++ b/kintex7/tile_type_CLK_HROW_TOP_R.json @@ -2,19882 +2,78562 @@ "pips": { "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT0->>CLK_HROW_BUFHCE_CE_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT0" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT1->>CLK_HROW_BUFHCE_CE_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT1" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT10->>CLK_HROW_BUFHCE_CE_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT10" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT11->>CLK_HROW_BUFHCE_CE_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT11" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT2->>CLK_HROW_BUFHCE_CE_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT2" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT3->>CLK_HROW_BUFHCE_CE_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT3" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT4->>CLK_HROW_BUFHCE_CE_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT4" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT5->>CLK_HROW_BUFHCE_CE_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT5" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT6->>CLK_HROW_BUFHCE_CE_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT6" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT7->>CLK_HROW_BUFHCE_CE_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT7" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT8->>CLK_HROW_BUFHCE_CE_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT8" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_BOT9->>CLK_HROW_BUFHCE_CE_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_BOT9" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP0->>CLK_HROW_BUFHCE_CE_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP0" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP1->>CLK_HROW_BUFHCE_CE_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP1" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP10->>CLK_HROW_BUFHCE_CE_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP10" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP11->>CLK_HROW_BUFHCE_CE_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP11" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP2->>CLK_HROW_BUFHCE_CE_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP2" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP3->>CLK_HROW_BUFHCE_CE_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP3" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP4->>CLK_HROW_BUFHCE_CE_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP4" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP5->>CLK_HROW_BUFHCE_CE_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP5" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP6->>CLK_HROW_BUFHCE_CE_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP6" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP7->>CLK_HROW_BUFHCE_CE_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP7" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP8->>CLK_HROW_BUFHCE_CE_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP8" }, "CLK_HROW_TOP_R.CLK_HROW_CE_INT_TOP9->>CLK_HROW_BUFHCE_CE_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_BUFHCE_CE_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.020", + "0.023", + "0.046", + "0.052" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CE_INT_TOP9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_BUFRCLK_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.146", + "0.165", + "0.348", + "0.388" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_BUFRCLK_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST0->CLK_HROW_CK_GCLK_TEST_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST1->CLK_HROW_CK_GCLK_TEST_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST10->CLK_HROW_CK_GCLK_TEST_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST11->CLK_HROW_CK_GCLK_TEST_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST12->CLK_HROW_CK_GCLK_TEST_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST13->CLK_HROW_CK_GCLK_TEST_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST14->CLK_HROW_CK_GCLK_TEST_IN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST14" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST15->CLK_HROW_CK_GCLK_TEST_IN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST15" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST16->CLK_HROW_CK_GCLK_TEST_IN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST16" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST17->CLK_HROW_CK_GCLK_TEST_IN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST17" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST18->CLK_HROW_CK_GCLK_TEST_IN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST18" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST19->CLK_HROW_CK_GCLK_TEST_IN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST19" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST2->CLK_HROW_CK_GCLK_TEST_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST20->CLK_HROW_CK_GCLK_TEST_IN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST20" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST21->CLK_HROW_CK_GCLK_TEST_IN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST21" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST22->CLK_HROW_CK_GCLK_TEST_IN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST22" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST23->CLK_HROW_CK_GCLK_TEST_IN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST23" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST24->CLK_HROW_CK_GCLK_TEST_IN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST24" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST25->CLK_HROW_CK_GCLK_TEST_IN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST25" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST26->CLK_HROW_CK_GCLK_TEST_IN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST26" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST27->CLK_HROW_CK_GCLK_TEST_IN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST27" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST28->CLK_HROW_CK_GCLK_TEST_IN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST28" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST29->CLK_HROW_CK_GCLK_TEST_IN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST29" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST3->CLK_HROW_CK_GCLK_TEST_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST30->CLK_HROW_CK_GCLK_TEST_IN30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST30" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST31->CLK_HROW_CK_GCLK_TEST_IN31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST31" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST4->CLK_HROW_CK_GCLK_TEST_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST5->CLK_HROW_CK_GCLK_TEST_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST6->CLK_HROW_CK_GCLK_TEST_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST7->CLK_HROW_CK_GCLK_TEST_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST8->CLK_HROW_CK_GCLK_TEST_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_IN_TEST9->CLK_HROW_CK_GCLK_TEST_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_TEST_IN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_IN_TEST9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT0->CLK_HROW_CK_GCLK_OUT_TEST0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT1->CLK_HROW_CK_GCLK_OUT_TEST1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT10->CLK_HROW_CK_GCLK_OUT_TEST10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT11->CLK_HROW_CK_GCLK_OUT_TEST11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT12->CLK_HROW_CK_GCLK_OUT_TEST12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT13->CLK_HROW_CK_GCLK_OUT_TEST13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT14->CLK_HROW_CK_GCLK_OUT_TEST14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT14" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT15->CLK_HROW_CK_GCLK_OUT_TEST15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT15" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT16->CLK_HROW_CK_GCLK_OUT_TEST16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT16" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT17->CLK_HROW_CK_GCLK_OUT_TEST17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT17" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT18->CLK_HROW_CK_GCLK_OUT_TEST18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT18" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT19->CLK_HROW_CK_GCLK_OUT_TEST19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT19" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT2->CLK_HROW_CK_GCLK_OUT_TEST2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT20->CLK_HROW_CK_GCLK_OUT_TEST20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT20" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT21->CLK_HROW_CK_GCLK_OUT_TEST21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT21" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT22->CLK_HROW_CK_GCLK_OUT_TEST22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT22" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT23->CLK_HROW_CK_GCLK_OUT_TEST23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT23" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT24->CLK_HROW_CK_GCLK_OUT_TEST24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT24" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT25->CLK_HROW_CK_GCLK_OUT_TEST25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT25" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT26->CLK_HROW_CK_GCLK_OUT_TEST26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT26" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT27->CLK_HROW_CK_GCLK_OUT_TEST27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT27" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT28->CLK_HROW_CK_GCLK_OUT_TEST28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT28" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT29->CLK_HROW_CK_GCLK_OUT_TEST29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT29" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT3->CLK_HROW_CK_GCLK_OUT_TEST3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT30->CLK_HROW_CK_GCLK_OUT_TEST30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT30" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT31->CLK_HROW_CK_GCLK_OUT_TEST31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT31" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT4->CLK_HROW_CK_GCLK_OUT_TEST4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT5->CLK_HROW_CK_GCLK_OUT_TEST5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT6->CLK_HROW_CK_GCLK_OUT_TEST6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT7->CLK_HROW_CK_GCLK_OUT_TEST7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT8->CLK_HROW_CK_GCLK_OUT_TEST8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_GCLK_TEST_OUT9->CLK_HROW_CK_GCLK_OUT_TEST9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_GCLK_OUT_TEST9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_GCLK_TEST_OUT9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L0->>CLK_HROW_CK_BUFHCLK_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L1->>CLK_HROW_CK_BUFHCLK_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L10->>CLK_HROW_CK_BUFHCLK_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L11->>CLK_HROW_CK_BUFHCLK_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L2->>CLK_HROW_CK_BUFHCLK_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L3->>CLK_HROW_CK_BUFHCLK_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L4->>CLK_HROW_CK_BUFHCLK_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L5->>CLK_HROW_CK_BUFHCLK_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L6->>CLK_HROW_CK_BUFHCLK_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L7->>CLK_HROW_CK_BUFHCLK_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L8->>CLK_HROW_CK_BUFHCLK_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_L9->>CLK_HROW_CK_BUFHCLK_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R0->>CLK_HROW_CK_BUFHCLK_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R1->>CLK_HROW_CK_BUFHCLK_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R10->>CLK_HROW_CK_BUFHCLK_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R11->>CLK_HROW_CK_BUFHCLK_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R2->>CLK_HROW_CK_BUFHCLK_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R3->>CLK_HROW_CK_BUFHCLK_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R4->>CLK_HROW_CK_BUFHCLK_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R5->>CLK_HROW_CK_BUFHCLK_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R6->>CLK_HROW_CK_BUFHCLK_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R7->>CLK_HROW_CK_BUFHCLK_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R8->>CLK_HROW_CK_BUFHCLK_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_HCLK_OUT_R9->>CLK_HROW_CK_BUFHCLK_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "dst_wire": "CLK_HROW_CK_BUFHCLK_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.120" + ], + "in_cap": null, + "res": null + }, "src_wire": "CLK_HROW_CK_HCLK_OUT_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_0_1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_0_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_INT_1_1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.155", + "0.175", + "0.381", + "0.425" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_INT_1_1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_OUT_TEST->CLK_HROW_CK_IN_L_TEST_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_L_TEST_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_L_OUT_TEST" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_L_TEST_IN->CLK_HROW_CK_IN_L_IN_TEST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_L_IN_TEST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_L_TEST_IN" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R0->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R1->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R10->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R11->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R12->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R12" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R13->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R13" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R2->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R3->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R4->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R5->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R6->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R7->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R8->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.014", + "0.023", + "0.298", + "0.326" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.130", + "0.135", + "0.425", + "0.430" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_IN_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_OUT_TEST->CLK_HROW_CK_IN_R_TEST_OUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_R_TEST_OUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_R_OUT_TEST" }, "CLK_HROW_TOP_R.CLK_HROW_CK_IN_R_TEST_IN->CLK_HROW_CK_IN_R_IN_TEST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_IN_R_IN_TEST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CK_IN_R_TEST_IN" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L0->>CLK_HROW_CK_HCLK_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L1->>CLK_HROW_CK_HCLK_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L10->>CLK_HROW_CK_HCLK_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L11->>CLK_HROW_CK_HCLK_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L2->>CLK_HROW_CK_HCLK_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L3->>CLK_HROW_CK_HCLK_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L4->>CLK_HROW_CK_HCLK_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L5->>CLK_HROW_CK_HCLK_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L6->>CLK_HROW_CK_HCLK_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L7->>CLK_HROW_CK_HCLK_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L8->>CLK_HROW_CK_HCLK_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_L9->>CLK_HROW_CK_HCLK_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_L9" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R0->>CLK_HROW_CK_HCLK_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R0" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R1->>CLK_HROW_CK_HCLK_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R1" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R10->>CLK_HROW_CK_HCLK_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R10" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R11->>CLK_HROW_CK_HCLK_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R11" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R2->>CLK_HROW_CK_HCLK_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R2" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R3->>CLK_HROW_CK_HCLK_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R3" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R4->>CLK_HROW_CK_HCLK_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R4" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R5->>CLK_HROW_CK_HCLK_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R5" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R6->>CLK_HROW_CK_HCLK_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R6" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R7->>CLK_HROW_CK_HCLK_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R7" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R8->>CLK_HROW_CK_HCLK_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R8" }, "CLK_HROW_TOP_R.CLK_HROW_CK_MUX_OUT_R9->>CLK_HROW_CK_HCLK_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_HCLK_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.023", + "0.045", + "0.066", + "0.103" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CLK_HROW_CK_MUX_OUT_R9" }, "CLK_HROW_TOP_R.CLK_HROW_CLK0_3->CLK_HROW_CK_INT_0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK0_3" }, "CLK_HROW_TOP_R.CLK_HROW_CLK0_4->CLK_HROW_CK_INT_1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK0_4" }, "CLK_HROW_TOP_R.CLK_HROW_CLK1_3->CLK_HROW_CK_INT_0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK1_3" }, "CLK_HROW_TOP_R.CLK_HROW_CLK1_4->CLK_HROW_CK_INT_1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CK_INT_1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_CLK1_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX0_3->CLK_HROW_CE_INT_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX0_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX0_4->CLK_HROW_CE_INT_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX0_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX10_3->CLK_HROW_CE_INT_BOT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX10_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX10_4->CLK_HROW_CE_INT_TOP10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX10_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX11_3->CLK_HROW_CE_INT_BOT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX11_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX11_4->CLK_HROW_CE_INT_TOP11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX11_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX1_3->CLK_HROW_CE_INT_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX1_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX1_4->CLK_HROW_CE_INT_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX1_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX2_3->CLK_HROW_CE_INT_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX2_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX2_4->CLK_HROW_CE_INT_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX2_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX3_3->CLK_HROW_CE_INT_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX3_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX3_4->CLK_HROW_CE_INT_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX3_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX4_3->CLK_HROW_CE_INT_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX4_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX4_4->CLK_HROW_CE_INT_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX4_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX5_3->CLK_HROW_CE_INT_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX5_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX5_4->CLK_HROW_CE_INT_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX5_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX6_3->CLK_HROW_CE_INT_BOT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX6_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX6_4->CLK_HROW_CE_INT_TOP6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX6_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX7_3->CLK_HROW_CE_INT_BOT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX7_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX7_4->CLK_HROW_CE_INT_TOP7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX7_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX8_3->CLK_HROW_CE_INT_BOT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX8_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX8_4->CLK_HROW_CE_INT_TOP8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX8_4" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX9_3->CLK_HROW_CE_INT_BOT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_BOT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX9_3" }, "CLK_HROW_TOP_R.CLK_HROW_IMUX9_4->CLK_HROW_CE_INT_TOP9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CLK_HROW_CE_INT_TOP9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CLK_HROW_IMUX9_4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK0->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK0" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK1->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK1" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK10->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK10" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK11->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK11" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK12->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK12" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK13->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK13" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK14->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK14" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK15->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK15" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK16->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK16" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK17->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK17" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK18->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK18" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK19->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK19" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK2->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK2" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK20->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK20" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK21->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK21" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK22->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK22" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK23->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK23" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK24->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK24" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK25->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK25" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK26->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK26" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK27->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK27" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK28->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK28" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK29->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK29" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK3->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK3" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK30->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK30" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK31->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK31" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK4->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK4" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK5->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK5" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK6->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK6" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK7->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK7" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK8->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK8" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_L9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_L9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_R_CK_GCLK9->>CLK_HROW_CK_MUX_OUT_R9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_CK_MUX_OUT_R9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.122", + "0.138", + "0.297", + "0.331" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_R_CK_GCLK9" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN0->>CLK_HROW_TOP_R_CK_BUFG_CASCO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN0" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN1->>CLK_HROW_TOP_R_CK_BUFG_CASCO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN1" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN10->>CLK_HROW_TOP_R_CK_BUFG_CASCO10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN10" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN11->>CLK_HROW_TOP_R_CK_BUFG_CASCO11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN11" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN12->>CLK_HROW_TOP_R_CK_BUFG_CASCO12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN12" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN13->>CLK_HROW_TOP_R_CK_BUFG_CASCO13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN13" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN14->>CLK_HROW_TOP_R_CK_BUFG_CASCO14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN14" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN15->>CLK_HROW_TOP_R_CK_BUFG_CASCO15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN15" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN16->>CLK_HROW_TOP_R_CK_BUFG_CASCO16": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO16", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN16" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN17->>CLK_HROW_TOP_R_CK_BUFG_CASCO17": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO17", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN17" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN18->>CLK_HROW_TOP_R_CK_BUFG_CASCO18": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO18", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN18" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN19->>CLK_HROW_TOP_R_CK_BUFG_CASCO19": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO19", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN19" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN2->>CLK_HROW_TOP_R_CK_BUFG_CASCO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN2" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN20->>CLK_HROW_TOP_R_CK_BUFG_CASCO20": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO20", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN20" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN21->>CLK_HROW_TOP_R_CK_BUFG_CASCO21": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO21", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN21" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN22->>CLK_HROW_TOP_R_CK_BUFG_CASCO22": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO22", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN22" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN23->>CLK_HROW_TOP_R_CK_BUFG_CASCO23": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO23", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN23" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN24->>CLK_HROW_TOP_R_CK_BUFG_CASCO24": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO24", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN24" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN25->>CLK_HROW_TOP_R_CK_BUFG_CASCO25": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO25", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN25" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN26->>CLK_HROW_TOP_R_CK_BUFG_CASCO26": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO26", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN26" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN27->>CLK_HROW_TOP_R_CK_BUFG_CASCO27": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO27", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN27" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN28->>CLK_HROW_TOP_R_CK_BUFG_CASCO28": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO28", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN28" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN29->>CLK_HROW_TOP_R_CK_BUFG_CASCO29": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO29", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN29" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN3->>CLK_HROW_TOP_R_CK_BUFG_CASCO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN3" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN30->>CLK_HROW_TOP_R_CK_BUFG_CASCO30": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO30", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN30" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN31->>CLK_HROW_TOP_R_CK_BUFG_CASCO31": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO31", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN31" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN4->>CLK_HROW_TOP_R_CK_BUFG_CASCO4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN4" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN5->>CLK_HROW_TOP_R_CK_BUFG_CASCO5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN5" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN6->>CLK_HROW_TOP_R_CK_BUFG_CASCO6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN6" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN7->>CLK_HROW_TOP_R_CK_BUFG_CASCO7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN7" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN8->>CLK_HROW_TOP_R_CK_BUFG_CASCO8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN8" }, "CLK_HROW_TOP_R.CLK_HROW_TOP_R_CK_BUFG_CASCIN9->>CLK_HROW_TOP_R_CK_BUFG_CASCO9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCO9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.197", + "0.200", + "0.215", + "0.237" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CLK_HROW_TOP_R_CK_BUFG_CASCIN9" } }, @@ -19886,9 +78566,36 @@ "name": "X0Y0", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L0", - "I": "CLK_HROW_CK_MUX_OUT_L0", - "O": "CLK_HROW_CK_HCLK_OUT_L0" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L0" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19898,9 +78605,36 @@ "name": "X0Y1", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L1", - "I": "CLK_HROW_CK_MUX_OUT_L1", - "O": "CLK_HROW_CK_HCLK_OUT_L1" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L1" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19910,9 +78644,36 @@ "name": "X0Y2", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L2", - "I": "CLK_HROW_CK_MUX_OUT_L2", - "O": "CLK_HROW_CK_HCLK_OUT_L2" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L2" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L2" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19922,9 +78683,36 @@ "name": "X0Y3", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L3", - "I": "CLK_HROW_CK_MUX_OUT_L3", - "O": "CLK_HROW_CK_HCLK_OUT_L3" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L3" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L3" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19934,9 +78722,36 @@ "name": "X0Y4", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L4", - "I": "CLK_HROW_CK_MUX_OUT_L4", - "O": "CLK_HROW_CK_HCLK_OUT_L4" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L4" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L4" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L4" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19946,9 +78761,36 @@ "name": "X0Y5", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L5", - "I": "CLK_HROW_CK_MUX_OUT_L5", - "O": "CLK_HROW_CK_HCLK_OUT_L5" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L5" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L5" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L5" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19958,9 +78800,36 @@ "name": "X0Y6", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L6", - "I": "CLK_HROW_CK_MUX_OUT_L6", - "O": "CLK_HROW_CK_HCLK_OUT_L6" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L6" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L6" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L6" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19970,9 +78839,36 @@ "name": "X0Y7", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L7", - "I": "CLK_HROW_CK_MUX_OUT_L7", - "O": "CLK_HROW_CK_HCLK_OUT_L7" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L7" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L7" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L7" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19982,9 +78878,36 @@ "name": "X0Y8", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L8", - "I": "CLK_HROW_CK_MUX_OUT_L8", - "O": "CLK_HROW_CK_HCLK_OUT_L8" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L8" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L8" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L8" + } }, "type": "BUFHCE", "x_coord": 0, @@ -19994,9 +78917,36 @@ "name": "X0Y9", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L9", - "I": "CLK_HROW_CK_MUX_OUT_L9", - "O": "CLK_HROW_CK_HCLK_OUT_L9" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L9" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L9" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L9" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20006,9 +78956,36 @@ "name": "X0Y10", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L10", - "I": "CLK_HROW_CK_MUX_OUT_L10", - "O": "CLK_HROW_CK_HCLK_OUT_L10" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L10" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L10" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L10" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20018,9 +78995,36 @@ "name": "X0Y11", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_L11", - "I": "CLK_HROW_CK_MUX_OUT_L11", - "O": "CLK_HROW_CK_HCLK_OUT_L11" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_L11" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_L11" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_L11" + } }, "type": "BUFHCE", "x_coord": 0, @@ -20030,9 +79034,36 @@ "name": "X1Y11", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R11", - "I": "CLK_HROW_CK_MUX_OUT_R11", - "O": "CLK_HROW_CK_HCLK_OUT_R11" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R11" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R11" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R11" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20042,9 +79073,36 @@ "name": "X1Y10", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R10", - "I": "CLK_HROW_CK_MUX_OUT_R10", - "O": "CLK_HROW_CK_HCLK_OUT_R10" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R10" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R10" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R10" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20054,9 +79112,36 @@ "name": "X1Y9", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R9", - "I": "CLK_HROW_CK_MUX_OUT_R9", - "O": "CLK_HROW_CK_HCLK_OUT_R9" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R9" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R9" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R9" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20066,9 +79151,36 @@ "name": "X1Y8", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R8", - "I": "CLK_HROW_CK_MUX_OUT_R8", - "O": "CLK_HROW_CK_HCLK_OUT_R8" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R8" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R8" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R8" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20078,9 +79190,36 @@ "name": "X1Y7", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R7", - "I": "CLK_HROW_CK_MUX_OUT_R7", - "O": "CLK_HROW_CK_HCLK_OUT_R7" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R7" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R7" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R7" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20090,9 +79229,36 @@ "name": "X1Y6", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R6", - "I": "CLK_HROW_CK_MUX_OUT_R6", - "O": "CLK_HROW_CK_HCLK_OUT_R6" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R6" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R6" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R6" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20102,9 +79268,36 @@ "name": "X1Y5", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R5", - "I": "CLK_HROW_CK_MUX_OUT_R5", - "O": "CLK_HROW_CK_HCLK_OUT_R5" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R5" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R5" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R5" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20114,9 +79307,36 @@ "name": "X1Y4", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R4", - "I": "CLK_HROW_CK_MUX_OUT_R4", - "O": "CLK_HROW_CK_HCLK_OUT_R4" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R4" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R4" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R4" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20126,9 +79346,36 @@ "name": "X1Y3", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R3", - "I": "CLK_HROW_CK_MUX_OUT_R3", - "O": "CLK_HROW_CK_HCLK_OUT_R3" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R3" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R3" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20138,9 +79385,36 @@ "name": "X1Y2", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R2", - "I": "CLK_HROW_CK_MUX_OUT_R2", - "O": "CLK_HROW_CK_HCLK_OUT_R2" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R2" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R2" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20150,9 +79424,36 @@ "name": "X1Y1", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R1", - "I": "CLK_HROW_CK_MUX_OUT_R1", - "O": "CLK_HROW_CK_HCLK_OUT_R1" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R1" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20162,9 +79463,36 @@ "name": "X1Y0", "prefix": "BUFHCE", "site_pins": { - "CE": "CLK_HROW_BUFHCE_CE_R0", - "I": "CLK_HROW_CK_MUX_OUT_R0", - "O": "CLK_HROW_CK_HCLK_OUT_R0" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_BUFHCE_CE_R0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_HROW_CK_MUX_OUT_R0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_HROW_CK_HCLK_OUT_R0" + } }, "type": "BUFHCE", "x_coord": 1, @@ -20172,2210 +79500,3410 @@ } ], "tile_type": "CLK_HROW_TOP_R", - "wires": [ - "CLK_HROW_BLOCK_OUTS_B0_0", - "CLK_HROW_BLOCK_OUTS_B0_1", - "CLK_HROW_BLOCK_OUTS_B0_2", - "CLK_HROW_BLOCK_OUTS_B0_3", - "CLK_HROW_BLOCK_OUTS_B0_4", - "CLK_HROW_BLOCK_OUTS_B0_5", - "CLK_HROW_BLOCK_OUTS_B0_6", - "CLK_HROW_BLOCK_OUTS_B0_7", - "CLK_HROW_BLOCK_OUTS_B1_0", - "CLK_HROW_BLOCK_OUTS_B1_1", - "CLK_HROW_BLOCK_OUTS_B1_2", - "CLK_HROW_BLOCK_OUTS_B1_3", - "CLK_HROW_BLOCK_OUTS_B1_4", - "CLK_HROW_BLOCK_OUTS_B1_5", - "CLK_HROW_BLOCK_OUTS_B1_6", - "CLK_HROW_BLOCK_OUTS_B1_7", - "CLK_HROW_BLOCK_OUTS_B2_0", - "CLK_HROW_BLOCK_OUTS_B2_1", - "CLK_HROW_BLOCK_OUTS_B2_2", - "CLK_HROW_BLOCK_OUTS_B2_3", - "CLK_HROW_BLOCK_OUTS_B2_4", - "CLK_HROW_BLOCK_OUTS_B2_5", - "CLK_HROW_BLOCK_OUTS_B2_6", - "CLK_HROW_BLOCK_OUTS_B2_7", - "CLK_HROW_BLOCK_OUTS_B3_0", - "CLK_HROW_BLOCK_OUTS_B3_1", - "CLK_HROW_BLOCK_OUTS_B3_2", - "CLK_HROW_BLOCK_OUTS_B3_3", - "CLK_HROW_BLOCK_OUTS_B3_4", - "CLK_HROW_BLOCK_OUTS_B3_5", - "CLK_HROW_BLOCK_OUTS_B3_6", - "CLK_HROW_BLOCK_OUTS_B3_7", - "CLK_HROW_BUFHCE_CE_L0", - "CLK_HROW_BUFHCE_CE_L1", - "CLK_HROW_BUFHCE_CE_L10", - "CLK_HROW_BUFHCE_CE_L11", - "CLK_HROW_BUFHCE_CE_L2", - "CLK_HROW_BUFHCE_CE_L3", - "CLK_HROW_BUFHCE_CE_L4", - "CLK_HROW_BUFHCE_CE_L5", - "CLK_HROW_BUFHCE_CE_L6", - "CLK_HROW_BUFHCE_CE_L7", - "CLK_HROW_BUFHCE_CE_L8", - "CLK_HROW_BUFHCE_CE_L9", - "CLK_HROW_BUFHCE_CE_R0", - "CLK_HROW_BUFHCE_CE_R1", - "CLK_HROW_BUFHCE_CE_R10", - "CLK_HROW_BUFHCE_CE_R11", - "CLK_HROW_BUFHCE_CE_R2", - "CLK_HROW_BUFHCE_CE_R3", - "CLK_HROW_BUFHCE_CE_R4", - "CLK_HROW_BUFHCE_CE_R5", - "CLK_HROW_BUFHCE_CE_R6", - "CLK_HROW_BUFHCE_CE_R7", - "CLK_HROW_BUFHCE_CE_R8", - "CLK_HROW_BUFHCE_CE_R9", - "CLK_HROW_BYP0_0", - "CLK_HROW_BYP0_1", - "CLK_HROW_BYP0_2", - "CLK_HROW_BYP0_3", - "CLK_HROW_BYP0_4", - "CLK_HROW_BYP0_5", - "CLK_HROW_BYP0_6", - "CLK_HROW_BYP0_7", - "CLK_HROW_BYP1_0", - "CLK_HROW_BYP1_1", - "CLK_HROW_BYP1_2", - "CLK_HROW_BYP1_3", - "CLK_HROW_BYP1_4", - "CLK_HROW_BYP1_5", - "CLK_HROW_BYP1_6", - "CLK_HROW_BYP1_7", - "CLK_HROW_BYP2_0", - "CLK_HROW_BYP2_1", - "CLK_HROW_BYP2_2", - "CLK_HROW_BYP2_3", - "CLK_HROW_BYP2_4", - "CLK_HROW_BYP2_5", - "CLK_HROW_BYP2_6", - "CLK_HROW_BYP2_7", - "CLK_HROW_BYP3_0", - "CLK_HROW_BYP3_1", - "CLK_HROW_BYP3_2", - "CLK_HROW_BYP3_3", - "CLK_HROW_BYP3_4", - "CLK_HROW_BYP3_5", - "CLK_HROW_BYP3_6", - "CLK_HROW_BYP3_7", - "CLK_HROW_BYP4_0", - "CLK_HROW_BYP4_1", - "CLK_HROW_BYP4_2", - "CLK_HROW_BYP4_3", - "CLK_HROW_BYP4_4", - "CLK_HROW_BYP4_5", - "CLK_HROW_BYP4_6", - "CLK_HROW_BYP4_7", - "CLK_HROW_BYP5_0", - "CLK_HROW_BYP5_1", - "CLK_HROW_BYP5_2", - "CLK_HROW_BYP5_3", - "CLK_HROW_BYP5_4", - "CLK_HROW_BYP5_5", - "CLK_HROW_BYP5_6", - "CLK_HROW_BYP5_7", - "CLK_HROW_BYP6_0", - "CLK_HROW_BYP6_1", - "CLK_HROW_BYP6_2", - "CLK_HROW_BYP6_3", - "CLK_HROW_BYP6_4", - "CLK_HROW_BYP6_5", - "CLK_HROW_BYP6_6", - "CLK_HROW_BYP6_7", - "CLK_HROW_BYP7_0", - "CLK_HROW_BYP7_1", - "CLK_HROW_BYP7_2", - "CLK_HROW_BYP7_3", - "CLK_HROW_BYP7_4", - "CLK_HROW_BYP7_5", - "CLK_HROW_BYP7_6", - "CLK_HROW_BYP7_7", - "CLK_HROW_CE_INT_BOT0", - "CLK_HROW_CE_INT_BOT1", - "CLK_HROW_CE_INT_BOT10", - "CLK_HROW_CE_INT_BOT11", - "CLK_HROW_CE_INT_BOT2", - "CLK_HROW_CE_INT_BOT3", - "CLK_HROW_CE_INT_BOT4", - "CLK_HROW_CE_INT_BOT5", - "CLK_HROW_CE_INT_BOT6", - "CLK_HROW_CE_INT_BOT7", - "CLK_HROW_CE_INT_BOT8", - "CLK_HROW_CE_INT_BOT9", - "CLK_HROW_CE_INT_TOP0", - "CLK_HROW_CE_INT_TOP1", - "CLK_HROW_CE_INT_TOP10", - "CLK_HROW_CE_INT_TOP11", - "CLK_HROW_CE_INT_TOP2", - "CLK_HROW_CE_INT_TOP3", - "CLK_HROW_CE_INT_TOP4", - "CLK_HROW_CE_INT_TOP5", - "CLK_HROW_CE_INT_TOP6", - "CLK_HROW_CE_INT_TOP7", - "CLK_HROW_CE_INT_TOP8", - "CLK_HROW_CE_INT_TOP9", - "CLK_HROW_CK_BUFHCLK_L0", - "CLK_HROW_CK_BUFHCLK_L1", - "CLK_HROW_CK_BUFHCLK_L10", - "CLK_HROW_CK_BUFHCLK_L11", - "CLK_HROW_CK_BUFHCLK_L2", - "CLK_HROW_CK_BUFHCLK_L3", - "CLK_HROW_CK_BUFHCLK_L4", - "CLK_HROW_CK_BUFHCLK_L5", - "CLK_HROW_CK_BUFHCLK_L6", - "CLK_HROW_CK_BUFHCLK_L7", - "CLK_HROW_CK_BUFHCLK_L8", - "CLK_HROW_CK_BUFHCLK_L9", - "CLK_HROW_CK_BUFHCLK_R0", - "CLK_HROW_CK_BUFHCLK_R1", - "CLK_HROW_CK_BUFHCLK_R10", - "CLK_HROW_CK_BUFHCLK_R11", - "CLK_HROW_CK_BUFHCLK_R2", - "CLK_HROW_CK_BUFHCLK_R3", - "CLK_HROW_CK_BUFHCLK_R4", - "CLK_HROW_CK_BUFHCLK_R5", - "CLK_HROW_CK_BUFHCLK_R6", - "CLK_HROW_CK_BUFHCLK_R7", - "CLK_HROW_CK_BUFHCLK_R8", - "CLK_HROW_CK_BUFHCLK_R9", - "CLK_HROW_CK_BUFRCLK_L0", - "CLK_HROW_CK_BUFRCLK_L1", - "CLK_HROW_CK_BUFRCLK_L2", - "CLK_HROW_CK_BUFRCLK_L3", - "CLK_HROW_CK_BUFRCLK_R0", - "CLK_HROW_CK_BUFRCLK_R1", - "CLK_HROW_CK_BUFRCLK_R2", - "CLK_HROW_CK_BUFRCLK_R3", - "CLK_HROW_CK_GCLK_IN_TEST0", - "CLK_HROW_CK_GCLK_IN_TEST1", - "CLK_HROW_CK_GCLK_IN_TEST10", - "CLK_HROW_CK_GCLK_IN_TEST11", - "CLK_HROW_CK_GCLK_IN_TEST12", - "CLK_HROW_CK_GCLK_IN_TEST13", - "CLK_HROW_CK_GCLK_IN_TEST14", - "CLK_HROW_CK_GCLK_IN_TEST15", - "CLK_HROW_CK_GCLK_IN_TEST16", - "CLK_HROW_CK_GCLK_IN_TEST17", - "CLK_HROW_CK_GCLK_IN_TEST18", - "CLK_HROW_CK_GCLK_IN_TEST19", - "CLK_HROW_CK_GCLK_IN_TEST2", - "CLK_HROW_CK_GCLK_IN_TEST20", - "CLK_HROW_CK_GCLK_IN_TEST21", - "CLK_HROW_CK_GCLK_IN_TEST22", - "CLK_HROW_CK_GCLK_IN_TEST23", - "CLK_HROW_CK_GCLK_IN_TEST24", - "CLK_HROW_CK_GCLK_IN_TEST25", - "CLK_HROW_CK_GCLK_IN_TEST26", - "CLK_HROW_CK_GCLK_IN_TEST27", - "CLK_HROW_CK_GCLK_IN_TEST28", - "CLK_HROW_CK_GCLK_IN_TEST29", - "CLK_HROW_CK_GCLK_IN_TEST3", - "CLK_HROW_CK_GCLK_IN_TEST30", - "CLK_HROW_CK_GCLK_IN_TEST31", - "CLK_HROW_CK_GCLK_IN_TEST4", - "CLK_HROW_CK_GCLK_IN_TEST5", - "CLK_HROW_CK_GCLK_IN_TEST6", - "CLK_HROW_CK_GCLK_IN_TEST7", - "CLK_HROW_CK_GCLK_IN_TEST8", - "CLK_HROW_CK_GCLK_IN_TEST9", - "CLK_HROW_CK_GCLK_OUT_TEST0", - "CLK_HROW_CK_GCLK_OUT_TEST1", - "CLK_HROW_CK_GCLK_OUT_TEST10", - "CLK_HROW_CK_GCLK_OUT_TEST11", - "CLK_HROW_CK_GCLK_OUT_TEST12", - "CLK_HROW_CK_GCLK_OUT_TEST13", - "CLK_HROW_CK_GCLK_OUT_TEST14", - "CLK_HROW_CK_GCLK_OUT_TEST15", - "CLK_HROW_CK_GCLK_OUT_TEST16", - "CLK_HROW_CK_GCLK_OUT_TEST17", - "CLK_HROW_CK_GCLK_OUT_TEST18", - "CLK_HROW_CK_GCLK_OUT_TEST19", - "CLK_HROW_CK_GCLK_OUT_TEST2", - "CLK_HROW_CK_GCLK_OUT_TEST20", - "CLK_HROW_CK_GCLK_OUT_TEST21", - "CLK_HROW_CK_GCLK_OUT_TEST22", - "CLK_HROW_CK_GCLK_OUT_TEST23", - "CLK_HROW_CK_GCLK_OUT_TEST24", - "CLK_HROW_CK_GCLK_OUT_TEST25", - "CLK_HROW_CK_GCLK_OUT_TEST26", - "CLK_HROW_CK_GCLK_OUT_TEST27", - "CLK_HROW_CK_GCLK_OUT_TEST28", - "CLK_HROW_CK_GCLK_OUT_TEST29", - "CLK_HROW_CK_GCLK_OUT_TEST3", - "CLK_HROW_CK_GCLK_OUT_TEST30", - "CLK_HROW_CK_GCLK_OUT_TEST31", - "CLK_HROW_CK_GCLK_OUT_TEST4", - "CLK_HROW_CK_GCLK_OUT_TEST5", - "CLK_HROW_CK_GCLK_OUT_TEST6", - "CLK_HROW_CK_GCLK_OUT_TEST7", - "CLK_HROW_CK_GCLK_OUT_TEST8", - "CLK_HROW_CK_GCLK_OUT_TEST9", - "CLK_HROW_CK_GCLK_TEST0", - "CLK_HROW_CK_GCLK_TEST1", - "CLK_HROW_CK_GCLK_TEST10", - "CLK_HROW_CK_GCLK_TEST11", - "CLK_HROW_CK_GCLK_TEST12", - "CLK_HROW_CK_GCLK_TEST13", - "CLK_HROW_CK_GCLK_TEST14", - "CLK_HROW_CK_GCLK_TEST15", - "CLK_HROW_CK_GCLK_TEST16", - "CLK_HROW_CK_GCLK_TEST17", - "CLK_HROW_CK_GCLK_TEST18", - "CLK_HROW_CK_GCLK_TEST19", - "CLK_HROW_CK_GCLK_TEST2", - "CLK_HROW_CK_GCLK_TEST20", - "CLK_HROW_CK_GCLK_TEST21", - "CLK_HROW_CK_GCLK_TEST22", - "CLK_HROW_CK_GCLK_TEST23", - "CLK_HROW_CK_GCLK_TEST24", - "CLK_HROW_CK_GCLK_TEST25", - "CLK_HROW_CK_GCLK_TEST26", - "CLK_HROW_CK_GCLK_TEST27", - "CLK_HROW_CK_GCLK_TEST28", - "CLK_HROW_CK_GCLK_TEST29", - "CLK_HROW_CK_GCLK_TEST3", - "CLK_HROW_CK_GCLK_TEST30", - "CLK_HROW_CK_GCLK_TEST31", - "CLK_HROW_CK_GCLK_TEST4", - "CLK_HROW_CK_GCLK_TEST5", - "CLK_HROW_CK_GCLK_TEST6", - "CLK_HROW_CK_GCLK_TEST7", - "CLK_HROW_CK_GCLK_TEST8", - "CLK_HROW_CK_GCLK_TEST9", - "CLK_HROW_CK_GCLK_TEST_IN0", - "CLK_HROW_CK_GCLK_TEST_IN1", - "CLK_HROW_CK_GCLK_TEST_IN10", - "CLK_HROW_CK_GCLK_TEST_IN11", - "CLK_HROW_CK_GCLK_TEST_IN12", - "CLK_HROW_CK_GCLK_TEST_IN13", - "CLK_HROW_CK_GCLK_TEST_IN14", - "CLK_HROW_CK_GCLK_TEST_IN15", - "CLK_HROW_CK_GCLK_TEST_IN16", - "CLK_HROW_CK_GCLK_TEST_IN17", - "CLK_HROW_CK_GCLK_TEST_IN18", - "CLK_HROW_CK_GCLK_TEST_IN19", - "CLK_HROW_CK_GCLK_TEST_IN2", - "CLK_HROW_CK_GCLK_TEST_IN20", - "CLK_HROW_CK_GCLK_TEST_IN21", - "CLK_HROW_CK_GCLK_TEST_IN22", - "CLK_HROW_CK_GCLK_TEST_IN23", - "CLK_HROW_CK_GCLK_TEST_IN24", - "CLK_HROW_CK_GCLK_TEST_IN25", - "CLK_HROW_CK_GCLK_TEST_IN26", - "CLK_HROW_CK_GCLK_TEST_IN27", - "CLK_HROW_CK_GCLK_TEST_IN28", - "CLK_HROW_CK_GCLK_TEST_IN29", - "CLK_HROW_CK_GCLK_TEST_IN3", - "CLK_HROW_CK_GCLK_TEST_IN30", - "CLK_HROW_CK_GCLK_TEST_IN31", - "CLK_HROW_CK_GCLK_TEST_IN4", - "CLK_HROW_CK_GCLK_TEST_IN5", - "CLK_HROW_CK_GCLK_TEST_IN6", - "CLK_HROW_CK_GCLK_TEST_IN7", - "CLK_HROW_CK_GCLK_TEST_IN8", - "CLK_HROW_CK_GCLK_TEST_IN9", - "CLK_HROW_CK_GCLK_TEST_OUT0", - "CLK_HROW_CK_GCLK_TEST_OUT1", - "CLK_HROW_CK_GCLK_TEST_OUT10", - "CLK_HROW_CK_GCLK_TEST_OUT11", - "CLK_HROW_CK_GCLK_TEST_OUT12", - "CLK_HROW_CK_GCLK_TEST_OUT13", - "CLK_HROW_CK_GCLK_TEST_OUT14", - "CLK_HROW_CK_GCLK_TEST_OUT15", - "CLK_HROW_CK_GCLK_TEST_OUT16", - "CLK_HROW_CK_GCLK_TEST_OUT17", - "CLK_HROW_CK_GCLK_TEST_OUT18", - "CLK_HROW_CK_GCLK_TEST_OUT19", - "CLK_HROW_CK_GCLK_TEST_OUT2", - "CLK_HROW_CK_GCLK_TEST_OUT20", - "CLK_HROW_CK_GCLK_TEST_OUT21", - "CLK_HROW_CK_GCLK_TEST_OUT22", - "CLK_HROW_CK_GCLK_TEST_OUT23", - "CLK_HROW_CK_GCLK_TEST_OUT24", - "CLK_HROW_CK_GCLK_TEST_OUT25", - "CLK_HROW_CK_GCLK_TEST_OUT26", - "CLK_HROW_CK_GCLK_TEST_OUT27", - "CLK_HROW_CK_GCLK_TEST_OUT28", - "CLK_HROW_CK_GCLK_TEST_OUT29", - "CLK_HROW_CK_GCLK_TEST_OUT3", - "CLK_HROW_CK_GCLK_TEST_OUT30", - "CLK_HROW_CK_GCLK_TEST_OUT31", - "CLK_HROW_CK_GCLK_TEST_OUT4", - "CLK_HROW_CK_GCLK_TEST_OUT5", - "CLK_HROW_CK_GCLK_TEST_OUT6", - "CLK_HROW_CK_GCLK_TEST_OUT7", - "CLK_HROW_CK_GCLK_TEST_OUT8", - "CLK_HROW_CK_GCLK_TEST_OUT9", - "CLK_HROW_CK_HCLK_OUT_L0", - "CLK_HROW_CK_HCLK_OUT_L1", - "CLK_HROW_CK_HCLK_OUT_L10", - "CLK_HROW_CK_HCLK_OUT_L11", - "CLK_HROW_CK_HCLK_OUT_L2", - "CLK_HROW_CK_HCLK_OUT_L3", - "CLK_HROW_CK_HCLK_OUT_L4", - "CLK_HROW_CK_HCLK_OUT_L5", - "CLK_HROW_CK_HCLK_OUT_L6", - "CLK_HROW_CK_HCLK_OUT_L7", - "CLK_HROW_CK_HCLK_OUT_L8", - "CLK_HROW_CK_HCLK_OUT_L9", - "CLK_HROW_CK_HCLK_OUT_R0", - "CLK_HROW_CK_HCLK_OUT_R1", - "CLK_HROW_CK_HCLK_OUT_R10", - "CLK_HROW_CK_HCLK_OUT_R11", - "CLK_HROW_CK_HCLK_OUT_R2", - "CLK_HROW_CK_HCLK_OUT_R3", - "CLK_HROW_CK_HCLK_OUT_R4", - "CLK_HROW_CK_HCLK_OUT_R5", - "CLK_HROW_CK_HCLK_OUT_R6", - "CLK_HROW_CK_HCLK_OUT_R7", - "CLK_HROW_CK_HCLK_OUT_R8", - "CLK_HROW_CK_HCLK_OUT_R9", - "CLK_HROW_CK_INT_0_0", - "CLK_HROW_CK_INT_0_1", - "CLK_HROW_CK_INT_1_0", - "CLK_HROW_CK_INT_1_1", - "CLK_HROW_CK_IN_L0", - "CLK_HROW_CK_IN_L1", - "CLK_HROW_CK_IN_L10", - "CLK_HROW_CK_IN_L11", - "CLK_HROW_CK_IN_L12", - "CLK_HROW_CK_IN_L13", - "CLK_HROW_CK_IN_L2", - "CLK_HROW_CK_IN_L3", - "CLK_HROW_CK_IN_L4", - "CLK_HROW_CK_IN_L5", - "CLK_HROW_CK_IN_L6", - "CLK_HROW_CK_IN_L7", - "CLK_HROW_CK_IN_L8", - "CLK_HROW_CK_IN_L9", - "CLK_HROW_CK_IN_L_IN_TEST", - "CLK_HROW_CK_IN_L_OUT_TEST", - "CLK_HROW_CK_IN_L_TEST_IN", - "CLK_HROW_CK_IN_L_TEST_OUT", - "CLK_HROW_CK_IN_R0", - "CLK_HROW_CK_IN_R1", - "CLK_HROW_CK_IN_R10", - "CLK_HROW_CK_IN_R11", - "CLK_HROW_CK_IN_R12", - "CLK_HROW_CK_IN_R13", - "CLK_HROW_CK_IN_R2", - "CLK_HROW_CK_IN_R3", - "CLK_HROW_CK_IN_R4", - "CLK_HROW_CK_IN_R5", - "CLK_HROW_CK_IN_R6", - "CLK_HROW_CK_IN_R7", - "CLK_HROW_CK_IN_R8", - "CLK_HROW_CK_IN_R9", - "CLK_HROW_CK_IN_R_IN_TEST", - "CLK_HROW_CK_IN_R_OUT_TEST", - "CLK_HROW_CK_IN_R_TEST_IN", - "CLK_HROW_CK_IN_R_TEST_OUT", - "CLK_HROW_CK_MUX_OUT_L0", - "CLK_HROW_CK_MUX_OUT_L1", - "CLK_HROW_CK_MUX_OUT_L10", - "CLK_HROW_CK_MUX_OUT_L11", - "CLK_HROW_CK_MUX_OUT_L2", - "CLK_HROW_CK_MUX_OUT_L3", - "CLK_HROW_CK_MUX_OUT_L4", - "CLK_HROW_CK_MUX_OUT_L5", - "CLK_HROW_CK_MUX_OUT_L6", - "CLK_HROW_CK_MUX_OUT_L7", - "CLK_HROW_CK_MUX_OUT_L8", - "CLK_HROW_CK_MUX_OUT_L9", - "CLK_HROW_CK_MUX_OUT_R0", - "CLK_HROW_CK_MUX_OUT_R1", - "CLK_HROW_CK_MUX_OUT_R10", - "CLK_HROW_CK_MUX_OUT_R11", - "CLK_HROW_CK_MUX_OUT_R2", - "CLK_HROW_CK_MUX_OUT_R3", - "CLK_HROW_CK_MUX_OUT_R4", - "CLK_HROW_CK_MUX_OUT_R5", - "CLK_HROW_CK_MUX_OUT_R6", - "CLK_HROW_CK_MUX_OUT_R7", - "CLK_HROW_CK_MUX_OUT_R8", - "CLK_HROW_CK_MUX_OUT_R9", - "CLK_HROW_CLK0_0", - "CLK_HROW_CLK0_1", - "CLK_HROW_CLK0_2", - "CLK_HROW_CLK0_3", - "CLK_HROW_CLK0_4", - "CLK_HROW_CLK0_5", - "CLK_HROW_CLK0_6", - "CLK_HROW_CLK0_7", - "CLK_HROW_CLK1_0", - "CLK_HROW_CLK1_1", - "CLK_HROW_CLK1_2", - "CLK_HROW_CLK1_3", - "CLK_HROW_CLK1_4", - "CLK_HROW_CLK1_5", - "CLK_HROW_CLK1_6", - "CLK_HROW_CLK1_7", - "CLK_HROW_CTRL0_0", - "CLK_HROW_CTRL0_1", - "CLK_HROW_CTRL0_2", - "CLK_HROW_CTRL0_3", - "CLK_HROW_CTRL0_4", - "CLK_HROW_CTRL0_5", - "CLK_HROW_CTRL0_6", - "CLK_HROW_CTRL0_7", - "CLK_HROW_CTRL1_0", - "CLK_HROW_CTRL1_1", - "CLK_HROW_CTRL1_2", - "CLK_HROW_CTRL1_3", - "CLK_HROW_CTRL1_4", - "CLK_HROW_CTRL1_5", - "CLK_HROW_CTRL1_6", - "CLK_HROW_CTRL1_7", - "CLK_HROW_EE2A0_0", - "CLK_HROW_EE2A0_1", - "CLK_HROW_EE2A0_2", - "CLK_HROW_EE2A0_3", - "CLK_HROW_EE2A0_4", - "CLK_HROW_EE2A0_5", - "CLK_HROW_EE2A0_6", - "CLK_HROW_EE2A0_7", - "CLK_HROW_EE2A1_0", - "CLK_HROW_EE2A1_1", - "CLK_HROW_EE2A1_2", - "CLK_HROW_EE2A1_3", - "CLK_HROW_EE2A1_4", - "CLK_HROW_EE2A1_5", - "CLK_HROW_EE2A1_6", - "CLK_HROW_EE2A1_7", - "CLK_HROW_EE2A2_0", - "CLK_HROW_EE2A2_1", - "CLK_HROW_EE2A2_2", - "CLK_HROW_EE2A2_3", - "CLK_HROW_EE2A2_4", - "CLK_HROW_EE2A2_5", - "CLK_HROW_EE2A2_6", - "CLK_HROW_EE2A2_7", - "CLK_HROW_EE2A3_0", - "CLK_HROW_EE2A3_1", - "CLK_HROW_EE2A3_2", - "CLK_HROW_EE2A3_3", - "CLK_HROW_EE2A3_4", - "CLK_HROW_EE2A3_5", - "CLK_HROW_EE2A3_6", - "CLK_HROW_EE2A3_7", - "CLK_HROW_EE2BEG0_0", - "CLK_HROW_EE2BEG0_1", - "CLK_HROW_EE2BEG0_2", - "CLK_HROW_EE2BEG0_3", - "CLK_HROW_EE2BEG0_4", - "CLK_HROW_EE2BEG0_5", - "CLK_HROW_EE2BEG0_6", - "CLK_HROW_EE2BEG0_7", - "CLK_HROW_EE2BEG1_0", - "CLK_HROW_EE2BEG1_1", - "CLK_HROW_EE2BEG1_2", - "CLK_HROW_EE2BEG1_3", - "CLK_HROW_EE2BEG1_4", - "CLK_HROW_EE2BEG1_5", - "CLK_HROW_EE2BEG1_6", - "CLK_HROW_EE2BEG1_7", - "CLK_HROW_EE2BEG2_0", - "CLK_HROW_EE2BEG2_1", - "CLK_HROW_EE2BEG2_2", - "CLK_HROW_EE2BEG2_3", - "CLK_HROW_EE2BEG2_4", - "CLK_HROW_EE2BEG2_5", - "CLK_HROW_EE2BEG2_6", - "CLK_HROW_EE2BEG2_7", - "CLK_HROW_EE2BEG3_0", - "CLK_HROW_EE2BEG3_1", - "CLK_HROW_EE2BEG3_2", - "CLK_HROW_EE2BEG3_3", - "CLK_HROW_EE2BEG3_4", - "CLK_HROW_EE2BEG3_5", - "CLK_HROW_EE2BEG3_6", - "CLK_HROW_EE2BEG3_7", - "CLK_HROW_EE4A0_0", - "CLK_HROW_EE4A0_1", - "CLK_HROW_EE4A0_2", - "CLK_HROW_EE4A0_3", - "CLK_HROW_EE4A0_4", - "CLK_HROW_EE4A0_5", - "CLK_HROW_EE4A0_6", - "CLK_HROW_EE4A0_7", - "CLK_HROW_EE4A1_0", - "CLK_HROW_EE4A1_1", - "CLK_HROW_EE4A1_2", - "CLK_HROW_EE4A1_3", - "CLK_HROW_EE4A1_4", - "CLK_HROW_EE4A1_5", - "CLK_HROW_EE4A1_6", - "CLK_HROW_EE4A1_7", - "CLK_HROW_EE4A2_0", - "CLK_HROW_EE4A2_1", - "CLK_HROW_EE4A2_2", - "CLK_HROW_EE4A2_3", - "CLK_HROW_EE4A2_4", - "CLK_HROW_EE4A2_5", - "CLK_HROW_EE4A2_6", - "CLK_HROW_EE4A2_7", - "CLK_HROW_EE4A3_0", - "CLK_HROW_EE4A3_1", - "CLK_HROW_EE4A3_2", - "CLK_HROW_EE4A3_3", - "CLK_HROW_EE4A3_4", - "CLK_HROW_EE4A3_5", - "CLK_HROW_EE4A3_6", - "CLK_HROW_EE4A3_7", - "CLK_HROW_EE4B0_0", - "CLK_HROW_EE4B0_1", - "CLK_HROW_EE4B0_2", - "CLK_HROW_EE4B0_3", - "CLK_HROW_EE4B0_4", - "CLK_HROW_EE4B0_5", - "CLK_HROW_EE4B0_6", - "CLK_HROW_EE4B0_7", - "CLK_HROW_EE4B1_0", - "CLK_HROW_EE4B1_1", - "CLK_HROW_EE4B1_2", - "CLK_HROW_EE4B1_3", - "CLK_HROW_EE4B1_4", - "CLK_HROW_EE4B1_5", - "CLK_HROW_EE4B1_6", - "CLK_HROW_EE4B1_7", - "CLK_HROW_EE4B2_0", - "CLK_HROW_EE4B2_1", - "CLK_HROW_EE4B2_2", - "CLK_HROW_EE4B2_3", - "CLK_HROW_EE4B2_4", - "CLK_HROW_EE4B2_5", - "CLK_HROW_EE4B2_6", - "CLK_HROW_EE4B2_7", - "CLK_HROW_EE4B3_0", - "CLK_HROW_EE4B3_1", - "CLK_HROW_EE4B3_2", - "CLK_HROW_EE4B3_3", - "CLK_HROW_EE4B3_4", - "CLK_HROW_EE4B3_5", - "CLK_HROW_EE4B3_6", - "CLK_HROW_EE4B3_7", - "CLK_HROW_EE4BEG0_0", - "CLK_HROW_EE4BEG0_1", - "CLK_HROW_EE4BEG0_2", - "CLK_HROW_EE4BEG0_3", - "CLK_HROW_EE4BEG0_4", - "CLK_HROW_EE4BEG0_5", - "CLK_HROW_EE4BEG0_6", - "CLK_HROW_EE4BEG0_7", - "CLK_HROW_EE4BEG1_0", - "CLK_HROW_EE4BEG1_1", - "CLK_HROW_EE4BEG1_2", - "CLK_HROW_EE4BEG1_3", - "CLK_HROW_EE4BEG1_4", - "CLK_HROW_EE4BEG1_5", - "CLK_HROW_EE4BEG1_6", - "CLK_HROW_EE4BEG1_7", - "CLK_HROW_EE4BEG2_0", - "CLK_HROW_EE4BEG2_1", - "CLK_HROW_EE4BEG2_2", - "CLK_HROW_EE4BEG2_3", - "CLK_HROW_EE4BEG2_4", - "CLK_HROW_EE4BEG2_5", - "CLK_HROW_EE4BEG2_6", - "CLK_HROW_EE4BEG2_7", - "CLK_HROW_EE4BEG3_0", - "CLK_HROW_EE4BEG3_1", - "CLK_HROW_EE4BEG3_2", - "CLK_HROW_EE4BEG3_3", - "CLK_HROW_EE4BEG3_4", - "CLK_HROW_EE4BEG3_5", - "CLK_HROW_EE4BEG3_6", - "CLK_HROW_EE4BEG3_7", - "CLK_HROW_EE4C0_0", - "CLK_HROW_EE4C0_1", - "CLK_HROW_EE4C0_2", - "CLK_HROW_EE4C0_3", - "CLK_HROW_EE4C0_4", - "CLK_HROW_EE4C0_5", - "CLK_HROW_EE4C0_6", - "CLK_HROW_EE4C0_7", - "CLK_HROW_EE4C1_0", - "CLK_HROW_EE4C1_1", - "CLK_HROW_EE4C1_2", - "CLK_HROW_EE4C1_3", - "CLK_HROW_EE4C1_4", - "CLK_HROW_EE4C1_5", - "CLK_HROW_EE4C1_6", - "CLK_HROW_EE4C1_7", - "CLK_HROW_EE4C2_0", - "CLK_HROW_EE4C2_1", - "CLK_HROW_EE4C2_2", - "CLK_HROW_EE4C2_3", - "CLK_HROW_EE4C2_4", - "CLK_HROW_EE4C2_5", - "CLK_HROW_EE4C2_6", - "CLK_HROW_EE4C2_7", - "CLK_HROW_EE4C3_0", - "CLK_HROW_EE4C3_1", - "CLK_HROW_EE4C3_2", - "CLK_HROW_EE4C3_3", - "CLK_HROW_EE4C3_4", - "CLK_HROW_EE4C3_5", - "CLK_HROW_EE4C3_6", - "CLK_HROW_EE4C3_7", - "CLK_HROW_EL1BEG0_0", - "CLK_HROW_EL1BEG0_1", - "CLK_HROW_EL1BEG0_2", - "CLK_HROW_EL1BEG0_3", - "CLK_HROW_EL1BEG0_4", - "CLK_HROW_EL1BEG0_5", - "CLK_HROW_EL1BEG0_6", - "CLK_HROW_EL1BEG0_7", - "CLK_HROW_EL1BEG1_0", - "CLK_HROW_EL1BEG1_1", - "CLK_HROW_EL1BEG1_2", - "CLK_HROW_EL1BEG1_3", - "CLK_HROW_EL1BEG1_4", - "CLK_HROW_EL1BEG1_5", - "CLK_HROW_EL1BEG1_6", - "CLK_HROW_EL1BEG1_7", - "CLK_HROW_EL1BEG2_0", - "CLK_HROW_EL1BEG2_1", - "CLK_HROW_EL1BEG2_2", - "CLK_HROW_EL1BEG2_3", - "CLK_HROW_EL1BEG2_4", - "CLK_HROW_EL1BEG2_5", - "CLK_HROW_EL1BEG2_6", - "CLK_HROW_EL1BEG2_7", - "CLK_HROW_EL1BEG3_0", - "CLK_HROW_EL1BEG3_1", - "CLK_HROW_EL1BEG3_2", - "CLK_HROW_EL1BEG3_3", - "CLK_HROW_EL1BEG3_4", - "CLK_HROW_EL1BEG3_5", - "CLK_HROW_EL1BEG3_6", - "CLK_HROW_EL1BEG3_7", - "CLK_HROW_ER1BEG0_0", - "CLK_HROW_ER1BEG0_1", - "CLK_HROW_ER1BEG0_2", - "CLK_HROW_ER1BEG0_3", - "CLK_HROW_ER1BEG0_4", - "CLK_HROW_ER1BEG0_5", - "CLK_HROW_ER1BEG0_6", - "CLK_HROW_ER1BEG0_7", - "CLK_HROW_ER1BEG1_0", - "CLK_HROW_ER1BEG1_1", - "CLK_HROW_ER1BEG1_2", - "CLK_HROW_ER1BEG1_3", - "CLK_HROW_ER1BEG1_4", - "CLK_HROW_ER1BEG1_5", - "CLK_HROW_ER1BEG1_6", - "CLK_HROW_ER1BEG1_7", - "CLK_HROW_ER1BEG2_0", - "CLK_HROW_ER1BEG2_1", - "CLK_HROW_ER1BEG2_2", - "CLK_HROW_ER1BEG2_3", - "CLK_HROW_ER1BEG2_4", - "CLK_HROW_ER1BEG2_5", - "CLK_HROW_ER1BEG2_6", - "CLK_HROW_ER1BEG2_7", - "CLK_HROW_ER1BEG3_0", - "CLK_HROW_ER1BEG3_1", - "CLK_HROW_ER1BEG3_2", - "CLK_HROW_ER1BEG3_3", - "CLK_HROW_ER1BEG3_4", - "CLK_HROW_ER1BEG3_5", - "CLK_HROW_ER1BEG3_6", - "CLK_HROW_ER1BEG3_7", - "CLK_HROW_FAN0_0", - "CLK_HROW_FAN0_1", - "CLK_HROW_FAN0_2", - "CLK_HROW_FAN0_3", - "CLK_HROW_FAN0_4", - "CLK_HROW_FAN0_5", - "CLK_HROW_FAN0_6", - "CLK_HROW_FAN0_7", - "CLK_HROW_FAN1_0", - "CLK_HROW_FAN1_1", - "CLK_HROW_FAN1_2", - "CLK_HROW_FAN1_3", - "CLK_HROW_FAN1_4", - "CLK_HROW_FAN1_5", - "CLK_HROW_FAN1_6", - "CLK_HROW_FAN1_7", - "CLK_HROW_FAN2_0", - "CLK_HROW_FAN2_1", - "CLK_HROW_FAN2_2", - "CLK_HROW_FAN2_3", - "CLK_HROW_FAN2_4", - "CLK_HROW_FAN2_5", - "CLK_HROW_FAN2_6", - "CLK_HROW_FAN2_7", - "CLK_HROW_FAN3_0", - "CLK_HROW_FAN3_1", - "CLK_HROW_FAN3_2", - "CLK_HROW_FAN3_3", - "CLK_HROW_FAN3_4", - "CLK_HROW_FAN3_5", - "CLK_HROW_FAN3_6", - "CLK_HROW_FAN3_7", - "CLK_HROW_FAN4_0", - "CLK_HROW_FAN4_1", - "CLK_HROW_FAN4_2", - "CLK_HROW_FAN4_3", - "CLK_HROW_FAN4_4", - "CLK_HROW_FAN4_5", - "CLK_HROW_FAN4_6", - "CLK_HROW_FAN4_7", - "CLK_HROW_FAN5_0", - "CLK_HROW_FAN5_1", - "CLK_HROW_FAN5_2", - "CLK_HROW_FAN5_3", - "CLK_HROW_FAN5_4", - "CLK_HROW_FAN5_5", - "CLK_HROW_FAN5_6", - "CLK_HROW_FAN5_7", - "CLK_HROW_FAN6_0", - "CLK_HROW_FAN6_1", - "CLK_HROW_FAN6_2", - "CLK_HROW_FAN6_3", - "CLK_HROW_FAN6_4", - "CLK_HROW_FAN6_5", - "CLK_HROW_FAN6_6", - "CLK_HROW_FAN6_7", - "CLK_HROW_FAN7_0", - "CLK_HROW_FAN7_1", - "CLK_HROW_FAN7_2", - "CLK_HROW_FAN7_3", - "CLK_HROW_FAN7_4", - "CLK_HROW_FAN7_5", - "CLK_HROW_FAN7_6", - "CLK_HROW_FAN7_7", - "CLK_HROW_IMUX0_0", - "CLK_HROW_IMUX0_1", - "CLK_HROW_IMUX0_2", - "CLK_HROW_IMUX0_3", - "CLK_HROW_IMUX0_4", - "CLK_HROW_IMUX0_5", - "CLK_HROW_IMUX0_6", - "CLK_HROW_IMUX0_7", - "CLK_HROW_IMUX10_0", - "CLK_HROW_IMUX10_1", - "CLK_HROW_IMUX10_2", - "CLK_HROW_IMUX10_3", - "CLK_HROW_IMUX10_4", - "CLK_HROW_IMUX10_5", - "CLK_HROW_IMUX10_6", - "CLK_HROW_IMUX10_7", - "CLK_HROW_IMUX11_0", - "CLK_HROW_IMUX11_1", - "CLK_HROW_IMUX11_2", - "CLK_HROW_IMUX11_3", - "CLK_HROW_IMUX11_4", - "CLK_HROW_IMUX11_5", - "CLK_HROW_IMUX11_6", - "CLK_HROW_IMUX11_7", - "CLK_HROW_IMUX12_0", - "CLK_HROW_IMUX12_1", - "CLK_HROW_IMUX12_2", - "CLK_HROW_IMUX12_3", - "CLK_HROW_IMUX12_4", - "CLK_HROW_IMUX12_5", - "CLK_HROW_IMUX12_6", - "CLK_HROW_IMUX12_7", - "CLK_HROW_IMUX13_0", - "CLK_HROW_IMUX13_1", - "CLK_HROW_IMUX13_2", - "CLK_HROW_IMUX13_3", - "CLK_HROW_IMUX13_4", - "CLK_HROW_IMUX13_5", - "CLK_HROW_IMUX13_6", - "CLK_HROW_IMUX13_7", - "CLK_HROW_IMUX14_0", - "CLK_HROW_IMUX14_1", - "CLK_HROW_IMUX14_2", - "CLK_HROW_IMUX14_3", - "CLK_HROW_IMUX14_4", - "CLK_HROW_IMUX14_5", - "CLK_HROW_IMUX14_6", - "CLK_HROW_IMUX14_7", - "CLK_HROW_IMUX15_0", - "CLK_HROW_IMUX15_1", - "CLK_HROW_IMUX15_2", - "CLK_HROW_IMUX15_3", - "CLK_HROW_IMUX15_4", - "CLK_HROW_IMUX15_5", - "CLK_HROW_IMUX15_6", - "CLK_HROW_IMUX15_7", - "CLK_HROW_IMUX16_0", - "CLK_HROW_IMUX16_1", - "CLK_HROW_IMUX16_2", - "CLK_HROW_IMUX16_3", - "CLK_HROW_IMUX16_4", - "CLK_HROW_IMUX16_5", - "CLK_HROW_IMUX16_6", - "CLK_HROW_IMUX16_7", - "CLK_HROW_IMUX17_0", - "CLK_HROW_IMUX17_1", - "CLK_HROW_IMUX17_2", - "CLK_HROW_IMUX17_3", - "CLK_HROW_IMUX17_4", - "CLK_HROW_IMUX17_5", - "CLK_HROW_IMUX17_6", - "CLK_HROW_IMUX17_7", - "CLK_HROW_IMUX18_0", - "CLK_HROW_IMUX18_1", - "CLK_HROW_IMUX18_2", - "CLK_HROW_IMUX18_3", - "CLK_HROW_IMUX18_4", - "CLK_HROW_IMUX18_5", - "CLK_HROW_IMUX18_6", - "CLK_HROW_IMUX18_7", - "CLK_HROW_IMUX19_0", - "CLK_HROW_IMUX19_1", - "CLK_HROW_IMUX19_2", - "CLK_HROW_IMUX19_3", - "CLK_HROW_IMUX19_4", - "CLK_HROW_IMUX19_5", - "CLK_HROW_IMUX19_6", - "CLK_HROW_IMUX19_7", - "CLK_HROW_IMUX1_0", - "CLK_HROW_IMUX1_1", - "CLK_HROW_IMUX1_2", - "CLK_HROW_IMUX1_3", - "CLK_HROW_IMUX1_4", - "CLK_HROW_IMUX1_5", - "CLK_HROW_IMUX1_6", - "CLK_HROW_IMUX1_7", - "CLK_HROW_IMUX20_0", - "CLK_HROW_IMUX20_1", - "CLK_HROW_IMUX20_2", - "CLK_HROW_IMUX20_3", - "CLK_HROW_IMUX20_4", - "CLK_HROW_IMUX20_5", - "CLK_HROW_IMUX20_6", - "CLK_HROW_IMUX20_7", - "CLK_HROW_IMUX21_0", - "CLK_HROW_IMUX21_1", - "CLK_HROW_IMUX21_2", - "CLK_HROW_IMUX21_3", - "CLK_HROW_IMUX21_4", - "CLK_HROW_IMUX21_5", - "CLK_HROW_IMUX21_6", - "CLK_HROW_IMUX21_7", - "CLK_HROW_IMUX22_0", - "CLK_HROW_IMUX22_1", - "CLK_HROW_IMUX22_2", - "CLK_HROW_IMUX22_3", - "CLK_HROW_IMUX22_4", - "CLK_HROW_IMUX22_5", - "CLK_HROW_IMUX22_6", - "CLK_HROW_IMUX22_7", - "CLK_HROW_IMUX23_0", - "CLK_HROW_IMUX23_1", - "CLK_HROW_IMUX23_2", - "CLK_HROW_IMUX23_3", - "CLK_HROW_IMUX23_4", - "CLK_HROW_IMUX23_5", - "CLK_HROW_IMUX23_6", - "CLK_HROW_IMUX23_7", - "CLK_HROW_IMUX24_0", - "CLK_HROW_IMUX24_1", - "CLK_HROW_IMUX24_2", - "CLK_HROW_IMUX24_3", - "CLK_HROW_IMUX24_4", - "CLK_HROW_IMUX24_5", - "CLK_HROW_IMUX24_6", - "CLK_HROW_IMUX24_7", - "CLK_HROW_IMUX25_0", - "CLK_HROW_IMUX25_1", - "CLK_HROW_IMUX25_2", - "CLK_HROW_IMUX25_3", - "CLK_HROW_IMUX25_4", - "CLK_HROW_IMUX25_5", - "CLK_HROW_IMUX25_6", - "CLK_HROW_IMUX25_7", - "CLK_HROW_IMUX26_0", - "CLK_HROW_IMUX26_1", - "CLK_HROW_IMUX26_2", - "CLK_HROW_IMUX26_3", - "CLK_HROW_IMUX26_4", - "CLK_HROW_IMUX26_5", - "CLK_HROW_IMUX26_6", - "CLK_HROW_IMUX26_7", - "CLK_HROW_IMUX27_0", - "CLK_HROW_IMUX27_1", - "CLK_HROW_IMUX27_2", - "CLK_HROW_IMUX27_3", - "CLK_HROW_IMUX27_4", - "CLK_HROW_IMUX27_5", - "CLK_HROW_IMUX27_6", - "CLK_HROW_IMUX27_7", - "CLK_HROW_IMUX28_0", - "CLK_HROW_IMUX28_1", - "CLK_HROW_IMUX28_2", - "CLK_HROW_IMUX28_3", - "CLK_HROW_IMUX28_4", - "CLK_HROW_IMUX28_5", - "CLK_HROW_IMUX28_6", - "CLK_HROW_IMUX28_7", - "CLK_HROW_IMUX29_0", - "CLK_HROW_IMUX29_1", - "CLK_HROW_IMUX29_2", - "CLK_HROW_IMUX29_3", - "CLK_HROW_IMUX29_4", - "CLK_HROW_IMUX29_5", - "CLK_HROW_IMUX29_6", - "CLK_HROW_IMUX29_7", - "CLK_HROW_IMUX2_0", - "CLK_HROW_IMUX2_1", - "CLK_HROW_IMUX2_2", - "CLK_HROW_IMUX2_3", - "CLK_HROW_IMUX2_4", - "CLK_HROW_IMUX2_5", - "CLK_HROW_IMUX2_6", - "CLK_HROW_IMUX2_7", - "CLK_HROW_IMUX30_0", - "CLK_HROW_IMUX30_1", - "CLK_HROW_IMUX30_2", - "CLK_HROW_IMUX30_3", - "CLK_HROW_IMUX30_4", - "CLK_HROW_IMUX30_5", - "CLK_HROW_IMUX30_6", - "CLK_HROW_IMUX30_7", - "CLK_HROW_IMUX31_0", - "CLK_HROW_IMUX31_1", - "CLK_HROW_IMUX31_2", - "CLK_HROW_IMUX31_3", - "CLK_HROW_IMUX31_4", - "CLK_HROW_IMUX31_5", - "CLK_HROW_IMUX31_6", - "CLK_HROW_IMUX31_7", - "CLK_HROW_IMUX32_0", - "CLK_HROW_IMUX32_1", - "CLK_HROW_IMUX32_2", - "CLK_HROW_IMUX32_3", - "CLK_HROW_IMUX32_4", - "CLK_HROW_IMUX32_5", - "CLK_HROW_IMUX32_6", - "CLK_HROW_IMUX32_7", - "CLK_HROW_IMUX33_0", - "CLK_HROW_IMUX33_1", - "CLK_HROW_IMUX33_2", - "CLK_HROW_IMUX33_3", - "CLK_HROW_IMUX33_4", - "CLK_HROW_IMUX33_5", - "CLK_HROW_IMUX33_6", - "CLK_HROW_IMUX33_7", - "CLK_HROW_IMUX34_0", - "CLK_HROW_IMUX34_1", - "CLK_HROW_IMUX34_2", - "CLK_HROW_IMUX34_3", - "CLK_HROW_IMUX34_4", - "CLK_HROW_IMUX34_5", - "CLK_HROW_IMUX34_6", - "CLK_HROW_IMUX34_7", - "CLK_HROW_IMUX35_0", - "CLK_HROW_IMUX35_1", - "CLK_HROW_IMUX35_2", - "CLK_HROW_IMUX35_3", - "CLK_HROW_IMUX35_4", - "CLK_HROW_IMUX35_5", - "CLK_HROW_IMUX35_6", - "CLK_HROW_IMUX35_7", - "CLK_HROW_IMUX36_0", - "CLK_HROW_IMUX36_1", - "CLK_HROW_IMUX36_2", - "CLK_HROW_IMUX36_3", - "CLK_HROW_IMUX36_4", - "CLK_HROW_IMUX36_5", - "CLK_HROW_IMUX36_6", - "CLK_HROW_IMUX36_7", - "CLK_HROW_IMUX37_0", - "CLK_HROW_IMUX37_1", - "CLK_HROW_IMUX37_2", - "CLK_HROW_IMUX37_3", - "CLK_HROW_IMUX37_4", - "CLK_HROW_IMUX37_5", - "CLK_HROW_IMUX37_6", - "CLK_HROW_IMUX37_7", - "CLK_HROW_IMUX38_0", - "CLK_HROW_IMUX38_1", - "CLK_HROW_IMUX38_2", - "CLK_HROW_IMUX38_3", - "CLK_HROW_IMUX38_4", - "CLK_HROW_IMUX38_5", - "CLK_HROW_IMUX38_6", - "CLK_HROW_IMUX38_7", - "CLK_HROW_IMUX39_0", - "CLK_HROW_IMUX39_1", - "CLK_HROW_IMUX39_2", - "CLK_HROW_IMUX39_3", - "CLK_HROW_IMUX39_4", - "CLK_HROW_IMUX39_5", - "CLK_HROW_IMUX39_6", - "CLK_HROW_IMUX39_7", - "CLK_HROW_IMUX3_0", - "CLK_HROW_IMUX3_1", - "CLK_HROW_IMUX3_2", - "CLK_HROW_IMUX3_3", - "CLK_HROW_IMUX3_4", - "CLK_HROW_IMUX3_5", - "CLK_HROW_IMUX3_6", - "CLK_HROW_IMUX3_7", - "CLK_HROW_IMUX40_0", - "CLK_HROW_IMUX40_1", - "CLK_HROW_IMUX40_2", - "CLK_HROW_IMUX40_3", - "CLK_HROW_IMUX40_4", - "CLK_HROW_IMUX40_5", - "CLK_HROW_IMUX40_6", - "CLK_HROW_IMUX40_7", - "CLK_HROW_IMUX41_0", - "CLK_HROW_IMUX41_1", - "CLK_HROW_IMUX41_2", - "CLK_HROW_IMUX41_3", - "CLK_HROW_IMUX41_4", - "CLK_HROW_IMUX41_5", - "CLK_HROW_IMUX41_6", - "CLK_HROW_IMUX41_7", - "CLK_HROW_IMUX42_0", - "CLK_HROW_IMUX42_1", - "CLK_HROW_IMUX42_2", - "CLK_HROW_IMUX42_3", - "CLK_HROW_IMUX42_4", - "CLK_HROW_IMUX42_5", - "CLK_HROW_IMUX42_6", - "CLK_HROW_IMUX42_7", - "CLK_HROW_IMUX43_0", - "CLK_HROW_IMUX43_1", - "CLK_HROW_IMUX43_2", - "CLK_HROW_IMUX43_3", - "CLK_HROW_IMUX43_4", - "CLK_HROW_IMUX43_5", - "CLK_HROW_IMUX43_6", - "CLK_HROW_IMUX43_7", - "CLK_HROW_IMUX44_0", - "CLK_HROW_IMUX44_1", - "CLK_HROW_IMUX44_2", - "CLK_HROW_IMUX44_3", - "CLK_HROW_IMUX44_4", - "CLK_HROW_IMUX44_5", - "CLK_HROW_IMUX44_6", - "CLK_HROW_IMUX44_7", - "CLK_HROW_IMUX45_0", - "CLK_HROW_IMUX45_1", - "CLK_HROW_IMUX45_2", - "CLK_HROW_IMUX45_3", - "CLK_HROW_IMUX45_4", - "CLK_HROW_IMUX45_5", - "CLK_HROW_IMUX45_6", - "CLK_HROW_IMUX45_7", - "CLK_HROW_IMUX46_0", - "CLK_HROW_IMUX46_1", - "CLK_HROW_IMUX46_2", - "CLK_HROW_IMUX46_3", - "CLK_HROW_IMUX46_4", - "CLK_HROW_IMUX46_5", - "CLK_HROW_IMUX46_6", - "CLK_HROW_IMUX46_7", - "CLK_HROW_IMUX47_0", - "CLK_HROW_IMUX47_1", - "CLK_HROW_IMUX47_2", - "CLK_HROW_IMUX47_3", - "CLK_HROW_IMUX47_4", - "CLK_HROW_IMUX47_5", - "CLK_HROW_IMUX47_6", - "CLK_HROW_IMUX47_7", - "CLK_HROW_IMUX4_0", - "CLK_HROW_IMUX4_1", - "CLK_HROW_IMUX4_2", - "CLK_HROW_IMUX4_3", - "CLK_HROW_IMUX4_4", - "CLK_HROW_IMUX4_5", - "CLK_HROW_IMUX4_6", - "CLK_HROW_IMUX4_7", - "CLK_HROW_IMUX5_0", - "CLK_HROW_IMUX5_1", - "CLK_HROW_IMUX5_2", - "CLK_HROW_IMUX5_3", - "CLK_HROW_IMUX5_4", - "CLK_HROW_IMUX5_5", - "CLK_HROW_IMUX5_6", - "CLK_HROW_IMUX5_7", - "CLK_HROW_IMUX6_0", - "CLK_HROW_IMUX6_1", - "CLK_HROW_IMUX6_2", - "CLK_HROW_IMUX6_3", - "CLK_HROW_IMUX6_4", - "CLK_HROW_IMUX6_5", - "CLK_HROW_IMUX6_6", - "CLK_HROW_IMUX6_7", - "CLK_HROW_IMUX7_0", - "CLK_HROW_IMUX7_1", - "CLK_HROW_IMUX7_2", - "CLK_HROW_IMUX7_3", - "CLK_HROW_IMUX7_4", - "CLK_HROW_IMUX7_5", - "CLK_HROW_IMUX7_6", - "CLK_HROW_IMUX7_7", - "CLK_HROW_IMUX8_0", - "CLK_HROW_IMUX8_1", - "CLK_HROW_IMUX8_2", - "CLK_HROW_IMUX8_3", - "CLK_HROW_IMUX8_4", - "CLK_HROW_IMUX8_5", - "CLK_HROW_IMUX8_6", - "CLK_HROW_IMUX8_7", - "CLK_HROW_IMUX9_0", - "CLK_HROW_IMUX9_1", - "CLK_HROW_IMUX9_2", - "CLK_HROW_IMUX9_3", - "CLK_HROW_IMUX9_4", - "CLK_HROW_IMUX9_5", - "CLK_HROW_IMUX9_6", - "CLK_HROW_IMUX9_7", - "CLK_HROW_LH10_0", - "CLK_HROW_LH10_1", - "CLK_HROW_LH10_2", - "CLK_HROW_LH10_3", - "CLK_HROW_LH10_4", - "CLK_HROW_LH10_5", - "CLK_HROW_LH10_6", - "CLK_HROW_LH10_7", - "CLK_HROW_LH11_0", - "CLK_HROW_LH11_1", - "CLK_HROW_LH11_2", - "CLK_HROW_LH11_3", - "CLK_HROW_LH11_4", - "CLK_HROW_LH11_5", - "CLK_HROW_LH11_6", - "CLK_HROW_LH11_7", - "CLK_HROW_LH12_0", - "CLK_HROW_LH12_1", - "CLK_HROW_LH12_2", - "CLK_HROW_LH12_3", - "CLK_HROW_LH12_4", - "CLK_HROW_LH12_5", - "CLK_HROW_LH12_6", - "CLK_HROW_LH12_7", - "CLK_HROW_LH1_0", - "CLK_HROW_LH1_1", - "CLK_HROW_LH1_2", - "CLK_HROW_LH1_3", - "CLK_HROW_LH1_4", - "CLK_HROW_LH1_5", - "CLK_HROW_LH1_6", - "CLK_HROW_LH1_7", - "CLK_HROW_LH2_0", - "CLK_HROW_LH2_1", - "CLK_HROW_LH2_2", - "CLK_HROW_LH2_3", - "CLK_HROW_LH2_4", - "CLK_HROW_LH2_5", - "CLK_HROW_LH2_6", - "CLK_HROW_LH2_7", - "CLK_HROW_LH3_0", - "CLK_HROW_LH3_1", - "CLK_HROW_LH3_2", - "CLK_HROW_LH3_3", - "CLK_HROW_LH3_4", - "CLK_HROW_LH3_5", - "CLK_HROW_LH3_6", - "CLK_HROW_LH3_7", - "CLK_HROW_LH4_0", - "CLK_HROW_LH4_1", - "CLK_HROW_LH4_2", - "CLK_HROW_LH4_3", - "CLK_HROW_LH4_4", - "CLK_HROW_LH4_5", - "CLK_HROW_LH4_6", - "CLK_HROW_LH4_7", - "CLK_HROW_LH5_0", - "CLK_HROW_LH5_1", - "CLK_HROW_LH5_2", - "CLK_HROW_LH5_3", - "CLK_HROW_LH5_4", - "CLK_HROW_LH5_5", - "CLK_HROW_LH5_6", - "CLK_HROW_LH5_7", - "CLK_HROW_LH6_0", - "CLK_HROW_LH6_1", - "CLK_HROW_LH6_2", - "CLK_HROW_LH6_3", - "CLK_HROW_LH6_4", - "CLK_HROW_LH6_5", - "CLK_HROW_LH6_6", - "CLK_HROW_LH6_7", - "CLK_HROW_LH7_0", - "CLK_HROW_LH7_1", - "CLK_HROW_LH7_2", - "CLK_HROW_LH7_3", - "CLK_HROW_LH7_4", - "CLK_HROW_LH7_5", - "CLK_HROW_LH7_6", - "CLK_HROW_LH7_7", - "CLK_HROW_LH8_0", - "CLK_HROW_LH8_1", - "CLK_HROW_LH8_2", - "CLK_HROW_LH8_3", - "CLK_HROW_LH8_4", - "CLK_HROW_LH8_5", - "CLK_HROW_LH8_6", - "CLK_HROW_LH8_7", - "CLK_HROW_LH9_0", - "CLK_HROW_LH9_1", - "CLK_HROW_LH9_2", - "CLK_HROW_LH9_3", - "CLK_HROW_LH9_4", - "CLK_HROW_LH9_5", - "CLK_HROW_LH9_6", - "CLK_HROW_LH9_7", - "CLK_HROW_LOGIC_OUTS_B0_0", - "CLK_HROW_LOGIC_OUTS_B0_1", - "CLK_HROW_LOGIC_OUTS_B0_2", - "CLK_HROW_LOGIC_OUTS_B0_3", - "CLK_HROW_LOGIC_OUTS_B0_4", - "CLK_HROW_LOGIC_OUTS_B0_5", - "CLK_HROW_LOGIC_OUTS_B0_6", - "CLK_HROW_LOGIC_OUTS_B0_7", - "CLK_HROW_LOGIC_OUTS_B10_0", - "CLK_HROW_LOGIC_OUTS_B10_1", - "CLK_HROW_LOGIC_OUTS_B10_2", - "CLK_HROW_LOGIC_OUTS_B10_3", - "CLK_HROW_LOGIC_OUTS_B10_4", - "CLK_HROW_LOGIC_OUTS_B10_5", - "CLK_HROW_LOGIC_OUTS_B10_6", - "CLK_HROW_LOGIC_OUTS_B10_7", - "CLK_HROW_LOGIC_OUTS_B11_0", - "CLK_HROW_LOGIC_OUTS_B11_1", - "CLK_HROW_LOGIC_OUTS_B11_2", - "CLK_HROW_LOGIC_OUTS_B11_3", - "CLK_HROW_LOGIC_OUTS_B11_4", - "CLK_HROW_LOGIC_OUTS_B11_5", - "CLK_HROW_LOGIC_OUTS_B11_6", - "CLK_HROW_LOGIC_OUTS_B11_7", - "CLK_HROW_LOGIC_OUTS_B12_0", - "CLK_HROW_LOGIC_OUTS_B12_1", - "CLK_HROW_LOGIC_OUTS_B12_2", - "CLK_HROW_LOGIC_OUTS_B12_3", - "CLK_HROW_LOGIC_OUTS_B12_4", - "CLK_HROW_LOGIC_OUTS_B12_5", - "CLK_HROW_LOGIC_OUTS_B12_6", - "CLK_HROW_LOGIC_OUTS_B12_7", - "CLK_HROW_LOGIC_OUTS_B13_0", - "CLK_HROW_LOGIC_OUTS_B13_1", - "CLK_HROW_LOGIC_OUTS_B13_2", - "CLK_HROW_LOGIC_OUTS_B13_3", - "CLK_HROW_LOGIC_OUTS_B13_4", - "CLK_HROW_LOGIC_OUTS_B13_5", - "CLK_HROW_LOGIC_OUTS_B13_6", - "CLK_HROW_LOGIC_OUTS_B13_7", - "CLK_HROW_LOGIC_OUTS_B14_0", - "CLK_HROW_LOGIC_OUTS_B14_1", - "CLK_HROW_LOGIC_OUTS_B14_2", - "CLK_HROW_LOGIC_OUTS_B14_3", - "CLK_HROW_LOGIC_OUTS_B14_4", - "CLK_HROW_LOGIC_OUTS_B14_5", - "CLK_HROW_LOGIC_OUTS_B14_6", - "CLK_HROW_LOGIC_OUTS_B14_7", - "CLK_HROW_LOGIC_OUTS_B15_0", - "CLK_HROW_LOGIC_OUTS_B15_1", - "CLK_HROW_LOGIC_OUTS_B15_2", - "CLK_HROW_LOGIC_OUTS_B15_3", - "CLK_HROW_LOGIC_OUTS_B15_4", - "CLK_HROW_LOGIC_OUTS_B15_5", - "CLK_HROW_LOGIC_OUTS_B15_6", - "CLK_HROW_LOGIC_OUTS_B15_7", - "CLK_HROW_LOGIC_OUTS_B16_0", - "CLK_HROW_LOGIC_OUTS_B16_1", - "CLK_HROW_LOGIC_OUTS_B16_2", - "CLK_HROW_LOGIC_OUTS_B16_3", - "CLK_HROW_LOGIC_OUTS_B16_4", - "CLK_HROW_LOGIC_OUTS_B16_5", - "CLK_HROW_LOGIC_OUTS_B16_6", - "CLK_HROW_LOGIC_OUTS_B16_7", - "CLK_HROW_LOGIC_OUTS_B17_0", - "CLK_HROW_LOGIC_OUTS_B17_1", - "CLK_HROW_LOGIC_OUTS_B17_2", - "CLK_HROW_LOGIC_OUTS_B17_3", - "CLK_HROW_LOGIC_OUTS_B17_4", - "CLK_HROW_LOGIC_OUTS_B17_5", - "CLK_HROW_LOGIC_OUTS_B17_6", - "CLK_HROW_LOGIC_OUTS_B17_7", - "CLK_HROW_LOGIC_OUTS_B18_0", - "CLK_HROW_LOGIC_OUTS_B18_1", - "CLK_HROW_LOGIC_OUTS_B18_2", - "CLK_HROW_LOGIC_OUTS_B18_3", - "CLK_HROW_LOGIC_OUTS_B18_4", - "CLK_HROW_LOGIC_OUTS_B18_5", - "CLK_HROW_LOGIC_OUTS_B18_6", - "CLK_HROW_LOGIC_OUTS_B18_7", - "CLK_HROW_LOGIC_OUTS_B19_0", - "CLK_HROW_LOGIC_OUTS_B19_1", - "CLK_HROW_LOGIC_OUTS_B19_2", - "CLK_HROW_LOGIC_OUTS_B19_3", - "CLK_HROW_LOGIC_OUTS_B19_4", - "CLK_HROW_LOGIC_OUTS_B19_5", - "CLK_HROW_LOGIC_OUTS_B19_6", - "CLK_HROW_LOGIC_OUTS_B19_7", - "CLK_HROW_LOGIC_OUTS_B1_0", - "CLK_HROW_LOGIC_OUTS_B1_1", - "CLK_HROW_LOGIC_OUTS_B1_2", - "CLK_HROW_LOGIC_OUTS_B1_3", - "CLK_HROW_LOGIC_OUTS_B1_4", - "CLK_HROW_LOGIC_OUTS_B1_5", - "CLK_HROW_LOGIC_OUTS_B1_6", - "CLK_HROW_LOGIC_OUTS_B1_7", - "CLK_HROW_LOGIC_OUTS_B20_0", - "CLK_HROW_LOGIC_OUTS_B20_1", - "CLK_HROW_LOGIC_OUTS_B20_2", - "CLK_HROW_LOGIC_OUTS_B20_3", - "CLK_HROW_LOGIC_OUTS_B20_4", - "CLK_HROW_LOGIC_OUTS_B20_5", - "CLK_HROW_LOGIC_OUTS_B20_6", - "CLK_HROW_LOGIC_OUTS_B20_7", - "CLK_HROW_LOGIC_OUTS_B21_0", - "CLK_HROW_LOGIC_OUTS_B21_1", - "CLK_HROW_LOGIC_OUTS_B21_2", - "CLK_HROW_LOGIC_OUTS_B21_3", - "CLK_HROW_LOGIC_OUTS_B21_4", - "CLK_HROW_LOGIC_OUTS_B21_5", - "CLK_HROW_LOGIC_OUTS_B21_6", - "CLK_HROW_LOGIC_OUTS_B21_7", - "CLK_HROW_LOGIC_OUTS_B22_0", - "CLK_HROW_LOGIC_OUTS_B22_1", - "CLK_HROW_LOGIC_OUTS_B22_2", - "CLK_HROW_LOGIC_OUTS_B22_3", - "CLK_HROW_LOGIC_OUTS_B22_4", - "CLK_HROW_LOGIC_OUTS_B22_5", - "CLK_HROW_LOGIC_OUTS_B22_6", - "CLK_HROW_LOGIC_OUTS_B22_7", - "CLK_HROW_LOGIC_OUTS_B23_0", - "CLK_HROW_LOGIC_OUTS_B23_1", - "CLK_HROW_LOGIC_OUTS_B23_2", - "CLK_HROW_LOGIC_OUTS_B23_3", - "CLK_HROW_LOGIC_OUTS_B23_4", - "CLK_HROW_LOGIC_OUTS_B23_5", - "CLK_HROW_LOGIC_OUTS_B23_6", - "CLK_HROW_LOGIC_OUTS_B23_7", - "CLK_HROW_LOGIC_OUTS_B2_0", - "CLK_HROW_LOGIC_OUTS_B2_1", - "CLK_HROW_LOGIC_OUTS_B2_2", - "CLK_HROW_LOGIC_OUTS_B2_3", - "CLK_HROW_LOGIC_OUTS_B2_4", - "CLK_HROW_LOGIC_OUTS_B2_5", - "CLK_HROW_LOGIC_OUTS_B2_6", - "CLK_HROW_LOGIC_OUTS_B2_7", - "CLK_HROW_LOGIC_OUTS_B3_0", - "CLK_HROW_LOGIC_OUTS_B3_1", - "CLK_HROW_LOGIC_OUTS_B3_2", - "CLK_HROW_LOGIC_OUTS_B3_3", - "CLK_HROW_LOGIC_OUTS_B3_4", - "CLK_HROW_LOGIC_OUTS_B3_5", - "CLK_HROW_LOGIC_OUTS_B3_6", - "CLK_HROW_LOGIC_OUTS_B3_7", - "CLK_HROW_LOGIC_OUTS_B4_0", - "CLK_HROW_LOGIC_OUTS_B4_1", - "CLK_HROW_LOGIC_OUTS_B4_2", - "CLK_HROW_LOGIC_OUTS_B4_3", - "CLK_HROW_LOGIC_OUTS_B4_4", - "CLK_HROW_LOGIC_OUTS_B4_5", - "CLK_HROW_LOGIC_OUTS_B4_6", - "CLK_HROW_LOGIC_OUTS_B4_7", - "CLK_HROW_LOGIC_OUTS_B5_0", - "CLK_HROW_LOGIC_OUTS_B5_1", - "CLK_HROW_LOGIC_OUTS_B5_2", - "CLK_HROW_LOGIC_OUTS_B5_3", - "CLK_HROW_LOGIC_OUTS_B5_4", - "CLK_HROW_LOGIC_OUTS_B5_5", - "CLK_HROW_LOGIC_OUTS_B5_6", - "CLK_HROW_LOGIC_OUTS_B5_7", - "CLK_HROW_LOGIC_OUTS_B6_0", - "CLK_HROW_LOGIC_OUTS_B6_1", - "CLK_HROW_LOGIC_OUTS_B6_2", - "CLK_HROW_LOGIC_OUTS_B6_3", - "CLK_HROW_LOGIC_OUTS_B6_4", - "CLK_HROW_LOGIC_OUTS_B6_5", - "CLK_HROW_LOGIC_OUTS_B6_6", - "CLK_HROW_LOGIC_OUTS_B6_7", - "CLK_HROW_LOGIC_OUTS_B7_0", - "CLK_HROW_LOGIC_OUTS_B7_1", - "CLK_HROW_LOGIC_OUTS_B7_2", - "CLK_HROW_LOGIC_OUTS_B7_3", - "CLK_HROW_LOGIC_OUTS_B7_4", - "CLK_HROW_LOGIC_OUTS_B7_5", - "CLK_HROW_LOGIC_OUTS_B7_6", - "CLK_HROW_LOGIC_OUTS_B7_7", - "CLK_HROW_LOGIC_OUTS_B8_0", - "CLK_HROW_LOGIC_OUTS_B8_1", - "CLK_HROW_LOGIC_OUTS_B8_2", - "CLK_HROW_LOGIC_OUTS_B8_3", - "CLK_HROW_LOGIC_OUTS_B8_4", - "CLK_HROW_LOGIC_OUTS_B8_5", - "CLK_HROW_LOGIC_OUTS_B8_6", - "CLK_HROW_LOGIC_OUTS_B8_7", - "CLK_HROW_LOGIC_OUTS_B9_0", - "CLK_HROW_LOGIC_OUTS_B9_1", - "CLK_HROW_LOGIC_OUTS_B9_2", - "CLK_HROW_LOGIC_OUTS_B9_3", - "CLK_HROW_LOGIC_OUTS_B9_4", - "CLK_HROW_LOGIC_OUTS_B9_5", - "CLK_HROW_LOGIC_OUTS_B9_6", - "CLK_HROW_LOGIC_OUTS_B9_7", - "CLK_HROW_MONITOR_N_0", - "CLK_HROW_MONITOR_N_1", - "CLK_HROW_MONITOR_N_2", - "CLK_HROW_MONITOR_N_3", - "CLK_HROW_MONITOR_N_4", - "CLK_HROW_MONITOR_N_5", - "CLK_HROW_MONITOR_N_6", - "CLK_HROW_MONITOR_N_7", - "CLK_HROW_MONITOR_P_0", - "CLK_HROW_MONITOR_P_1", - "CLK_HROW_MONITOR_P_2", - "CLK_HROW_MONITOR_P_3", - "CLK_HROW_MONITOR_P_4", - "CLK_HROW_MONITOR_P_5", - "CLK_HROW_MONITOR_P_6", - "CLK_HROW_MONITOR_P_7", - "CLK_HROW_NE2A0_0", - "CLK_HROW_NE2A0_1", - "CLK_HROW_NE2A0_2", - "CLK_HROW_NE2A0_3", - "CLK_HROW_NE2A0_4", - "CLK_HROW_NE2A0_5", - "CLK_HROW_NE2A0_6", - "CLK_HROW_NE2A0_7", - "CLK_HROW_NE2A1_0", - "CLK_HROW_NE2A1_1", - "CLK_HROW_NE2A1_2", - "CLK_HROW_NE2A1_3", - "CLK_HROW_NE2A1_4", - "CLK_HROW_NE2A1_5", - "CLK_HROW_NE2A1_6", - "CLK_HROW_NE2A1_7", - "CLK_HROW_NE2A2_0", - "CLK_HROW_NE2A2_1", - "CLK_HROW_NE2A2_2", - "CLK_HROW_NE2A2_3", - "CLK_HROW_NE2A2_4", - "CLK_HROW_NE2A2_5", - "CLK_HROW_NE2A2_6", - "CLK_HROW_NE2A2_7", - "CLK_HROW_NE2A3_0", - "CLK_HROW_NE2A3_1", - "CLK_HROW_NE2A3_2", - "CLK_HROW_NE2A3_3", - "CLK_HROW_NE2A3_4", - "CLK_HROW_NE2A3_5", - "CLK_HROW_NE2A3_6", - "CLK_HROW_NE2A3_7", - "CLK_HROW_NE4BEG0_0", - "CLK_HROW_NE4BEG0_1", - "CLK_HROW_NE4BEG0_2", - "CLK_HROW_NE4BEG0_3", - "CLK_HROW_NE4BEG0_4", - "CLK_HROW_NE4BEG0_5", - "CLK_HROW_NE4BEG0_6", - "CLK_HROW_NE4BEG0_7", - "CLK_HROW_NE4BEG1_0", - "CLK_HROW_NE4BEG1_1", - "CLK_HROW_NE4BEG1_2", - "CLK_HROW_NE4BEG1_3", - "CLK_HROW_NE4BEG1_4", - "CLK_HROW_NE4BEG1_5", - "CLK_HROW_NE4BEG1_6", - "CLK_HROW_NE4BEG1_7", - "CLK_HROW_NE4BEG2_0", - "CLK_HROW_NE4BEG2_1", - "CLK_HROW_NE4BEG2_2", - "CLK_HROW_NE4BEG2_3", - "CLK_HROW_NE4BEG2_4", - "CLK_HROW_NE4BEG2_5", - "CLK_HROW_NE4BEG2_6", - "CLK_HROW_NE4BEG2_7", - "CLK_HROW_NE4BEG3_0", - "CLK_HROW_NE4BEG3_1", - "CLK_HROW_NE4BEG3_2", - "CLK_HROW_NE4BEG3_3", - "CLK_HROW_NE4BEG3_4", - "CLK_HROW_NE4BEG3_5", - "CLK_HROW_NE4BEG3_6", - "CLK_HROW_NE4BEG3_7", - "CLK_HROW_NE4C0_0", - "CLK_HROW_NE4C0_1", - "CLK_HROW_NE4C0_2", - "CLK_HROW_NE4C0_3", - "CLK_HROW_NE4C0_4", - "CLK_HROW_NE4C0_5", - "CLK_HROW_NE4C0_6", - "CLK_HROW_NE4C0_7", - "CLK_HROW_NE4C1_0", - "CLK_HROW_NE4C1_1", - "CLK_HROW_NE4C1_2", - "CLK_HROW_NE4C1_3", - "CLK_HROW_NE4C1_4", - "CLK_HROW_NE4C1_5", - "CLK_HROW_NE4C1_6", - "CLK_HROW_NE4C1_7", - "CLK_HROW_NE4C2_0", - "CLK_HROW_NE4C2_1", - "CLK_HROW_NE4C2_2", - "CLK_HROW_NE4C2_3", - "CLK_HROW_NE4C2_4", - "CLK_HROW_NE4C2_5", - "CLK_HROW_NE4C2_6", - "CLK_HROW_NE4C2_7", - "CLK_HROW_NE4C3_0", - "CLK_HROW_NE4C3_1", - "CLK_HROW_NE4C3_2", - "CLK_HROW_NE4C3_3", - "CLK_HROW_NE4C3_4", - "CLK_HROW_NE4C3_5", - "CLK_HROW_NE4C3_6", - "CLK_HROW_NE4C3_7", - "CLK_HROW_NW2A0_0", - "CLK_HROW_NW2A0_1", - "CLK_HROW_NW2A0_2", - "CLK_HROW_NW2A0_3", - "CLK_HROW_NW2A0_4", - "CLK_HROW_NW2A0_5", - "CLK_HROW_NW2A0_6", - "CLK_HROW_NW2A0_7", - "CLK_HROW_NW2A1_0", - "CLK_HROW_NW2A1_1", - "CLK_HROW_NW2A1_2", - "CLK_HROW_NW2A1_3", - "CLK_HROW_NW2A1_4", - "CLK_HROW_NW2A1_5", - "CLK_HROW_NW2A1_6", - "CLK_HROW_NW2A1_7", - "CLK_HROW_NW2A2_0", - "CLK_HROW_NW2A2_1", - "CLK_HROW_NW2A2_2", - "CLK_HROW_NW2A2_3", - "CLK_HROW_NW2A2_4", - "CLK_HROW_NW2A2_5", - "CLK_HROW_NW2A2_6", - "CLK_HROW_NW2A2_7", - "CLK_HROW_NW2A3_0", - "CLK_HROW_NW2A3_1", - "CLK_HROW_NW2A3_2", - "CLK_HROW_NW2A3_3", - "CLK_HROW_NW2A3_4", - "CLK_HROW_NW2A3_5", - "CLK_HROW_NW2A3_6", - "CLK_HROW_NW2A3_7", - "CLK_HROW_NW4A0_0", - "CLK_HROW_NW4A0_1", - "CLK_HROW_NW4A0_2", - "CLK_HROW_NW4A0_3", - "CLK_HROW_NW4A0_4", - "CLK_HROW_NW4A0_5", - "CLK_HROW_NW4A0_6", - "CLK_HROW_NW4A0_7", - "CLK_HROW_NW4A1_0", - "CLK_HROW_NW4A1_1", - "CLK_HROW_NW4A1_2", - "CLK_HROW_NW4A1_3", - "CLK_HROW_NW4A1_4", - "CLK_HROW_NW4A1_5", - "CLK_HROW_NW4A1_6", - "CLK_HROW_NW4A1_7", - "CLK_HROW_NW4A2_0", - "CLK_HROW_NW4A2_1", - "CLK_HROW_NW4A2_2", - "CLK_HROW_NW4A2_3", - "CLK_HROW_NW4A2_4", - "CLK_HROW_NW4A2_5", - "CLK_HROW_NW4A2_6", - "CLK_HROW_NW4A2_7", - "CLK_HROW_NW4A3_0", - "CLK_HROW_NW4A3_1", - "CLK_HROW_NW4A3_2", - "CLK_HROW_NW4A3_3", - "CLK_HROW_NW4A3_4", - "CLK_HROW_NW4A3_5", - "CLK_HROW_NW4A3_6", - "CLK_HROW_NW4A3_7", - "CLK_HROW_NW4END0_0", - "CLK_HROW_NW4END0_1", - "CLK_HROW_NW4END0_2", - "CLK_HROW_NW4END0_3", - "CLK_HROW_NW4END0_4", - "CLK_HROW_NW4END0_5", - "CLK_HROW_NW4END0_6", - "CLK_HROW_NW4END0_7", - "CLK_HROW_NW4END1_0", - "CLK_HROW_NW4END1_1", - "CLK_HROW_NW4END1_2", - "CLK_HROW_NW4END1_3", - "CLK_HROW_NW4END1_4", - "CLK_HROW_NW4END1_5", - "CLK_HROW_NW4END1_6", - "CLK_HROW_NW4END1_7", - "CLK_HROW_NW4END2_0", - "CLK_HROW_NW4END2_1", - "CLK_HROW_NW4END2_2", - "CLK_HROW_NW4END2_3", - "CLK_HROW_NW4END2_4", - "CLK_HROW_NW4END2_5", - "CLK_HROW_NW4END2_6", - "CLK_HROW_NW4END2_7", - "CLK_HROW_NW4END3_0", - "CLK_HROW_NW4END3_1", - "CLK_HROW_NW4END3_2", - "CLK_HROW_NW4END3_3", - "CLK_HROW_NW4END3_4", - "CLK_HROW_NW4END3_5", - "CLK_HROW_NW4END3_6", - "CLK_HROW_NW4END3_7", - "CLK_HROW_REFCK_EASTCLK0", - "CLK_HROW_REFCK_EASTCLK1", - "CLK_HROW_REFCK_WESTCLK0", - "CLK_HROW_REFCK_WESTCLK1", - "CLK_HROW_R_CK_GCLK0", - "CLK_HROW_R_CK_GCLK1", - "CLK_HROW_R_CK_GCLK10", - "CLK_HROW_R_CK_GCLK11", - "CLK_HROW_R_CK_GCLK12", - "CLK_HROW_R_CK_GCLK13", - "CLK_HROW_R_CK_GCLK14", - "CLK_HROW_R_CK_GCLK15", - "CLK_HROW_R_CK_GCLK16", - "CLK_HROW_R_CK_GCLK17", - "CLK_HROW_R_CK_GCLK18", - "CLK_HROW_R_CK_GCLK19", - "CLK_HROW_R_CK_GCLK2", - "CLK_HROW_R_CK_GCLK20", - "CLK_HROW_R_CK_GCLK21", - "CLK_HROW_R_CK_GCLK22", - "CLK_HROW_R_CK_GCLK23", - "CLK_HROW_R_CK_GCLK24", - "CLK_HROW_R_CK_GCLK25", - "CLK_HROW_R_CK_GCLK26", - "CLK_HROW_R_CK_GCLK27", - "CLK_HROW_R_CK_GCLK28", - "CLK_HROW_R_CK_GCLK29", - "CLK_HROW_R_CK_GCLK3", - "CLK_HROW_R_CK_GCLK30", - "CLK_HROW_R_CK_GCLK31", - "CLK_HROW_R_CK_GCLK4", - "CLK_HROW_R_CK_GCLK5", - "CLK_HROW_R_CK_GCLK6", - "CLK_HROW_R_CK_GCLK7", - "CLK_HROW_R_CK_GCLK8", - "CLK_HROW_R_CK_GCLK9", - "CLK_HROW_SE2A0_0", - "CLK_HROW_SE2A0_1", - "CLK_HROW_SE2A0_2", - "CLK_HROW_SE2A0_3", - "CLK_HROW_SE2A0_4", - "CLK_HROW_SE2A0_5", - "CLK_HROW_SE2A0_6", - "CLK_HROW_SE2A0_7", - "CLK_HROW_SE2A1_0", - "CLK_HROW_SE2A1_1", - "CLK_HROW_SE2A1_2", - "CLK_HROW_SE2A1_3", - "CLK_HROW_SE2A1_4", - "CLK_HROW_SE2A1_5", - "CLK_HROW_SE2A1_6", - "CLK_HROW_SE2A1_7", - "CLK_HROW_SE2A2_0", - "CLK_HROW_SE2A2_1", - "CLK_HROW_SE2A2_2", - "CLK_HROW_SE2A2_3", - "CLK_HROW_SE2A2_4", - "CLK_HROW_SE2A2_5", - "CLK_HROW_SE2A2_6", - "CLK_HROW_SE2A2_7", - "CLK_HROW_SE2A3_0", - "CLK_HROW_SE2A3_1", - "CLK_HROW_SE2A3_2", - "CLK_HROW_SE2A3_3", - "CLK_HROW_SE2A3_4", - "CLK_HROW_SE2A3_5", - "CLK_HROW_SE2A3_6", - "CLK_HROW_SE2A3_7", - "CLK_HROW_SE4BEG0_0", - "CLK_HROW_SE4BEG0_1", - "CLK_HROW_SE4BEG0_2", - "CLK_HROW_SE4BEG0_3", - "CLK_HROW_SE4BEG0_4", - "CLK_HROW_SE4BEG0_5", - "CLK_HROW_SE4BEG0_6", - "CLK_HROW_SE4BEG0_7", - "CLK_HROW_SE4BEG1_0", - "CLK_HROW_SE4BEG1_1", - "CLK_HROW_SE4BEG1_2", - "CLK_HROW_SE4BEG1_3", - "CLK_HROW_SE4BEG1_4", - "CLK_HROW_SE4BEG1_5", - "CLK_HROW_SE4BEG1_6", - "CLK_HROW_SE4BEG1_7", - "CLK_HROW_SE4BEG2_0", - "CLK_HROW_SE4BEG2_1", - "CLK_HROW_SE4BEG2_2", - "CLK_HROW_SE4BEG2_3", - "CLK_HROW_SE4BEG2_4", - "CLK_HROW_SE4BEG2_5", - "CLK_HROW_SE4BEG2_6", - "CLK_HROW_SE4BEG2_7", - "CLK_HROW_SE4BEG3_0", - "CLK_HROW_SE4BEG3_1", - "CLK_HROW_SE4BEG3_2", - "CLK_HROW_SE4BEG3_3", - "CLK_HROW_SE4BEG3_4", - "CLK_HROW_SE4BEG3_5", - "CLK_HROW_SE4BEG3_6", - "CLK_HROW_SE4BEG3_7", - "CLK_HROW_SE4C0_0", - "CLK_HROW_SE4C0_1", - "CLK_HROW_SE4C0_2", - "CLK_HROW_SE4C0_3", - "CLK_HROW_SE4C0_4", - "CLK_HROW_SE4C0_5", - "CLK_HROW_SE4C0_6", - "CLK_HROW_SE4C0_7", - "CLK_HROW_SE4C1_0", - "CLK_HROW_SE4C1_1", - "CLK_HROW_SE4C1_2", - "CLK_HROW_SE4C1_3", - "CLK_HROW_SE4C1_4", - "CLK_HROW_SE4C1_5", - "CLK_HROW_SE4C1_6", - "CLK_HROW_SE4C1_7", - "CLK_HROW_SE4C2_0", - "CLK_HROW_SE4C2_1", - "CLK_HROW_SE4C2_2", - "CLK_HROW_SE4C2_3", - "CLK_HROW_SE4C2_4", - "CLK_HROW_SE4C2_5", - "CLK_HROW_SE4C2_6", - "CLK_HROW_SE4C2_7", - "CLK_HROW_SE4C3_0", - "CLK_HROW_SE4C3_1", - "CLK_HROW_SE4C3_2", - "CLK_HROW_SE4C3_3", - "CLK_HROW_SE4C3_4", - "CLK_HROW_SE4C3_5", - "CLK_HROW_SE4C3_6", - "CLK_HROW_SE4C3_7", - "CLK_HROW_SW2A0_0", - "CLK_HROW_SW2A0_1", - "CLK_HROW_SW2A0_2", - "CLK_HROW_SW2A0_3", - "CLK_HROW_SW2A0_4", - "CLK_HROW_SW2A0_5", - "CLK_HROW_SW2A0_6", - "CLK_HROW_SW2A0_7", - "CLK_HROW_SW2A1_0", - "CLK_HROW_SW2A1_1", - "CLK_HROW_SW2A1_2", - "CLK_HROW_SW2A1_3", - "CLK_HROW_SW2A1_4", - "CLK_HROW_SW2A1_5", - "CLK_HROW_SW2A1_6", - "CLK_HROW_SW2A1_7", - "CLK_HROW_SW2A2_0", - "CLK_HROW_SW2A2_1", - "CLK_HROW_SW2A2_2", - "CLK_HROW_SW2A2_3", - "CLK_HROW_SW2A2_4", - "CLK_HROW_SW2A2_5", - "CLK_HROW_SW2A2_6", - "CLK_HROW_SW2A2_7", - "CLK_HROW_SW2A3_0", - "CLK_HROW_SW2A3_1", - "CLK_HROW_SW2A3_2", - "CLK_HROW_SW2A3_3", - "CLK_HROW_SW2A3_4", - "CLK_HROW_SW2A3_5", - "CLK_HROW_SW2A3_6", - "CLK_HROW_SW2A3_7", - "CLK_HROW_SW4A0_0", - "CLK_HROW_SW4A0_1", - "CLK_HROW_SW4A0_2", - "CLK_HROW_SW4A0_3", - "CLK_HROW_SW4A0_4", - "CLK_HROW_SW4A0_5", - "CLK_HROW_SW4A0_6", - "CLK_HROW_SW4A0_7", - "CLK_HROW_SW4A1_0", - "CLK_HROW_SW4A1_1", - "CLK_HROW_SW4A1_2", - "CLK_HROW_SW4A1_3", - "CLK_HROW_SW4A1_4", - "CLK_HROW_SW4A1_5", - "CLK_HROW_SW4A1_6", - "CLK_HROW_SW4A1_7", - "CLK_HROW_SW4A2_0", - "CLK_HROW_SW4A2_1", - "CLK_HROW_SW4A2_2", - "CLK_HROW_SW4A2_3", - "CLK_HROW_SW4A2_4", - "CLK_HROW_SW4A2_5", - "CLK_HROW_SW4A2_6", - "CLK_HROW_SW4A2_7", - "CLK_HROW_SW4A3_0", - "CLK_HROW_SW4A3_1", - "CLK_HROW_SW4A3_2", - "CLK_HROW_SW4A3_3", - "CLK_HROW_SW4A3_4", - "CLK_HROW_SW4A3_5", - "CLK_HROW_SW4A3_6", - "CLK_HROW_SW4A3_7", - "CLK_HROW_SW4END0_0", - "CLK_HROW_SW4END0_1", - "CLK_HROW_SW4END0_2", - "CLK_HROW_SW4END0_3", - "CLK_HROW_SW4END0_4", - "CLK_HROW_SW4END0_5", - "CLK_HROW_SW4END0_6", - "CLK_HROW_SW4END0_7", - "CLK_HROW_SW4END1_0", - "CLK_HROW_SW4END1_1", - "CLK_HROW_SW4END1_2", - "CLK_HROW_SW4END1_3", - "CLK_HROW_SW4END1_4", - "CLK_HROW_SW4END1_5", - "CLK_HROW_SW4END1_6", - "CLK_HROW_SW4END1_7", - "CLK_HROW_SW4END2_0", - "CLK_HROW_SW4END2_1", - "CLK_HROW_SW4END2_2", - "CLK_HROW_SW4END2_3", - "CLK_HROW_SW4END2_4", - "CLK_HROW_SW4END2_5", - "CLK_HROW_SW4END2_6", - "CLK_HROW_SW4END2_7", - "CLK_HROW_SW4END3_0", - "CLK_HROW_SW4END3_1", - "CLK_HROW_SW4END3_2", - "CLK_HROW_SW4END3_3", - "CLK_HROW_SW4END3_4", - "CLK_HROW_SW4END3_5", - "CLK_HROW_SW4END3_6", - "CLK_HROW_SW4END3_7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN0", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN1", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN10", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN11", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN12", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN13", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN14", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN15", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN16", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN17", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN18", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN19", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN2", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN20", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN21", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN22", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN23", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN24", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN25", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN26", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN27", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN28", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN29", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN3", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN30", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN31", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN4", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN5", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN6", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN7", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN8", - "CLK_HROW_TOP_R_CK_BUFG_CASCIN9", - "CLK_HROW_TOP_R_CK_BUFG_CASCO0", - "CLK_HROW_TOP_R_CK_BUFG_CASCO1", - "CLK_HROW_TOP_R_CK_BUFG_CASCO10", - "CLK_HROW_TOP_R_CK_BUFG_CASCO11", - "CLK_HROW_TOP_R_CK_BUFG_CASCO12", - "CLK_HROW_TOP_R_CK_BUFG_CASCO13", - "CLK_HROW_TOP_R_CK_BUFG_CASCO14", - "CLK_HROW_TOP_R_CK_BUFG_CASCO15", - "CLK_HROW_TOP_R_CK_BUFG_CASCO16", - "CLK_HROW_TOP_R_CK_BUFG_CASCO17", - "CLK_HROW_TOP_R_CK_BUFG_CASCO18", - "CLK_HROW_TOP_R_CK_BUFG_CASCO19", - "CLK_HROW_TOP_R_CK_BUFG_CASCO2", - "CLK_HROW_TOP_R_CK_BUFG_CASCO20", - "CLK_HROW_TOP_R_CK_BUFG_CASCO21", - "CLK_HROW_TOP_R_CK_BUFG_CASCO22", - "CLK_HROW_TOP_R_CK_BUFG_CASCO23", - "CLK_HROW_TOP_R_CK_BUFG_CASCO24", - "CLK_HROW_TOP_R_CK_BUFG_CASCO25", - "CLK_HROW_TOP_R_CK_BUFG_CASCO26", - "CLK_HROW_TOP_R_CK_BUFG_CASCO27", - "CLK_HROW_TOP_R_CK_BUFG_CASCO28", - "CLK_HROW_TOP_R_CK_BUFG_CASCO29", - "CLK_HROW_TOP_R_CK_BUFG_CASCO3", - "CLK_HROW_TOP_R_CK_BUFG_CASCO30", - "CLK_HROW_TOP_R_CK_BUFG_CASCO31", - "CLK_HROW_TOP_R_CK_BUFG_CASCO4", - "CLK_HROW_TOP_R_CK_BUFG_CASCO5", - "CLK_HROW_TOP_R_CK_BUFG_CASCO6", - "CLK_HROW_TOP_R_CK_BUFG_CASCO7", - "CLK_HROW_TOP_R_CK_BUFG_CASCO8", - "CLK_HROW_TOP_R_CK_BUFG_CASCO9", - "CLK_HROW_WL1END0_0", - "CLK_HROW_WL1END0_1", - "CLK_HROW_WL1END0_2", - "CLK_HROW_WL1END0_3", - "CLK_HROW_WL1END0_4", - "CLK_HROW_WL1END0_5", - "CLK_HROW_WL1END0_6", - "CLK_HROW_WL1END0_7", - "CLK_HROW_WL1END1_0", - "CLK_HROW_WL1END1_1", - "CLK_HROW_WL1END1_2", - "CLK_HROW_WL1END1_3", - "CLK_HROW_WL1END1_4", - "CLK_HROW_WL1END1_5", - "CLK_HROW_WL1END1_6", - "CLK_HROW_WL1END1_7", - "CLK_HROW_WL1END2_0", - "CLK_HROW_WL1END2_1", - "CLK_HROW_WL1END2_2", - "CLK_HROW_WL1END2_3", - "CLK_HROW_WL1END2_4", - "CLK_HROW_WL1END2_5", - "CLK_HROW_WL1END2_6", - "CLK_HROW_WL1END2_7", - "CLK_HROW_WL1END3_0", - "CLK_HROW_WL1END3_1", - "CLK_HROW_WL1END3_2", - "CLK_HROW_WL1END3_3", - "CLK_HROW_WL1END3_4", - "CLK_HROW_WL1END3_5", - "CLK_HROW_WL1END3_6", - "CLK_HROW_WL1END3_7", - "CLK_HROW_WR1END0_0", - "CLK_HROW_WR1END0_1", - "CLK_HROW_WR1END0_2", - "CLK_HROW_WR1END0_3", - "CLK_HROW_WR1END0_4", - "CLK_HROW_WR1END0_5", - "CLK_HROW_WR1END0_6", - "CLK_HROW_WR1END0_7", - "CLK_HROW_WR1END1_0", - "CLK_HROW_WR1END1_1", - "CLK_HROW_WR1END1_2", - "CLK_HROW_WR1END1_3", - "CLK_HROW_WR1END1_4", - "CLK_HROW_WR1END1_5", - "CLK_HROW_WR1END1_6", - "CLK_HROW_WR1END1_7", - "CLK_HROW_WR1END2_0", - "CLK_HROW_WR1END2_1", - "CLK_HROW_WR1END2_2", - "CLK_HROW_WR1END2_3", - "CLK_HROW_WR1END2_4", - "CLK_HROW_WR1END2_5", - "CLK_HROW_WR1END2_6", - "CLK_HROW_WR1END2_7", - "CLK_HROW_WR1END3_0", - "CLK_HROW_WR1END3_1", - "CLK_HROW_WR1END3_2", - "CLK_HROW_WR1END3_3", - "CLK_HROW_WR1END3_4", - "CLK_HROW_WR1END3_5", - "CLK_HROW_WR1END3_6", - "CLK_HROW_WR1END3_7", - "CLK_HROW_WW2A0_0", - "CLK_HROW_WW2A0_1", - "CLK_HROW_WW2A0_2", - "CLK_HROW_WW2A0_3", - "CLK_HROW_WW2A0_4", - "CLK_HROW_WW2A0_5", - "CLK_HROW_WW2A0_6", - "CLK_HROW_WW2A0_7", - "CLK_HROW_WW2A1_0", - "CLK_HROW_WW2A1_1", - "CLK_HROW_WW2A1_2", - "CLK_HROW_WW2A1_3", - "CLK_HROW_WW2A1_4", - "CLK_HROW_WW2A1_5", - "CLK_HROW_WW2A1_6", - "CLK_HROW_WW2A1_7", - "CLK_HROW_WW2A2_0", - "CLK_HROW_WW2A2_1", - "CLK_HROW_WW2A2_2", - "CLK_HROW_WW2A2_3", - "CLK_HROW_WW2A2_4", - "CLK_HROW_WW2A2_5", - "CLK_HROW_WW2A2_6", - "CLK_HROW_WW2A2_7", - "CLK_HROW_WW2A3_0", - "CLK_HROW_WW2A3_1", - "CLK_HROW_WW2A3_2", - "CLK_HROW_WW2A3_3", - "CLK_HROW_WW2A3_4", - "CLK_HROW_WW2A3_5", - "CLK_HROW_WW2A3_6", - "CLK_HROW_WW2A3_7", - "CLK_HROW_WW2END0_0", - "CLK_HROW_WW2END0_1", - "CLK_HROW_WW2END0_2", - "CLK_HROW_WW2END0_3", - "CLK_HROW_WW2END0_4", - "CLK_HROW_WW2END0_5", - "CLK_HROW_WW2END0_6", - "CLK_HROW_WW2END0_7", - "CLK_HROW_WW2END1_0", - "CLK_HROW_WW2END1_1", - "CLK_HROW_WW2END1_2", - "CLK_HROW_WW2END1_3", - "CLK_HROW_WW2END1_4", - "CLK_HROW_WW2END1_5", - "CLK_HROW_WW2END1_6", - "CLK_HROW_WW2END1_7", - "CLK_HROW_WW2END2_0", - "CLK_HROW_WW2END2_1", - "CLK_HROW_WW2END2_2", - "CLK_HROW_WW2END2_3", - "CLK_HROW_WW2END2_4", - "CLK_HROW_WW2END2_5", - "CLK_HROW_WW2END2_6", - "CLK_HROW_WW2END2_7", - "CLK_HROW_WW2END3_0", - "CLK_HROW_WW2END3_1", - "CLK_HROW_WW2END3_2", - "CLK_HROW_WW2END3_3", - "CLK_HROW_WW2END3_4", - "CLK_HROW_WW2END3_5", - "CLK_HROW_WW2END3_6", - "CLK_HROW_WW2END3_7", - "CLK_HROW_WW4A0_0", - "CLK_HROW_WW4A0_1", - "CLK_HROW_WW4A0_2", - "CLK_HROW_WW4A0_3", - "CLK_HROW_WW4A0_4", - "CLK_HROW_WW4A0_5", - "CLK_HROW_WW4A0_6", - "CLK_HROW_WW4A0_7", - "CLK_HROW_WW4A1_0", - "CLK_HROW_WW4A1_1", - "CLK_HROW_WW4A1_2", - "CLK_HROW_WW4A1_3", - "CLK_HROW_WW4A1_4", - "CLK_HROW_WW4A1_5", - "CLK_HROW_WW4A1_6", - "CLK_HROW_WW4A1_7", - "CLK_HROW_WW4A2_0", - "CLK_HROW_WW4A2_1", - "CLK_HROW_WW4A2_2", - "CLK_HROW_WW4A2_3", - "CLK_HROW_WW4A2_4", - "CLK_HROW_WW4A2_5", - "CLK_HROW_WW4A2_6", - "CLK_HROW_WW4A2_7", - "CLK_HROW_WW4A3_0", - "CLK_HROW_WW4A3_1", - "CLK_HROW_WW4A3_2", - "CLK_HROW_WW4A3_3", - "CLK_HROW_WW4A3_4", - "CLK_HROW_WW4A3_5", - "CLK_HROW_WW4A3_6", - "CLK_HROW_WW4A3_7", - "CLK_HROW_WW4B0_0", - "CLK_HROW_WW4B0_1", - "CLK_HROW_WW4B0_2", - "CLK_HROW_WW4B0_3", - "CLK_HROW_WW4B0_4", - "CLK_HROW_WW4B0_5", - "CLK_HROW_WW4B0_6", - "CLK_HROW_WW4B0_7", - "CLK_HROW_WW4B1_0", - "CLK_HROW_WW4B1_1", - "CLK_HROW_WW4B1_2", - "CLK_HROW_WW4B1_3", - "CLK_HROW_WW4B1_4", - "CLK_HROW_WW4B1_5", - "CLK_HROW_WW4B1_6", - "CLK_HROW_WW4B1_7", - "CLK_HROW_WW4B2_0", - "CLK_HROW_WW4B2_1", - "CLK_HROW_WW4B2_2", - "CLK_HROW_WW4B2_3", - "CLK_HROW_WW4B2_4", - "CLK_HROW_WW4B2_5", - "CLK_HROW_WW4B2_6", - "CLK_HROW_WW4B2_7", - "CLK_HROW_WW4B3_0", - "CLK_HROW_WW4B3_1", - "CLK_HROW_WW4B3_2", - "CLK_HROW_WW4B3_3", - "CLK_HROW_WW4B3_4", - "CLK_HROW_WW4B3_5", - "CLK_HROW_WW4B3_6", - "CLK_HROW_WW4B3_7", - "CLK_HROW_WW4C0_0", - "CLK_HROW_WW4C0_1", - "CLK_HROW_WW4C0_2", - "CLK_HROW_WW4C0_3", - "CLK_HROW_WW4C0_4", - "CLK_HROW_WW4C0_5", - "CLK_HROW_WW4C0_6", - "CLK_HROW_WW4C0_7", - "CLK_HROW_WW4C1_0", - "CLK_HROW_WW4C1_1", - "CLK_HROW_WW4C1_2", - "CLK_HROW_WW4C1_3", - "CLK_HROW_WW4C1_4", - "CLK_HROW_WW4C1_5", - "CLK_HROW_WW4C1_6", - "CLK_HROW_WW4C1_7", - "CLK_HROW_WW4C2_0", - "CLK_HROW_WW4C2_1", - "CLK_HROW_WW4C2_2", - "CLK_HROW_WW4C2_3", - "CLK_HROW_WW4C2_4", - "CLK_HROW_WW4C2_5", - "CLK_HROW_WW4C2_6", - "CLK_HROW_WW4C2_7", - "CLK_HROW_WW4C3_0", - "CLK_HROW_WW4C3_1", - "CLK_HROW_WW4C3_2", - "CLK_HROW_WW4C3_3", - "CLK_HROW_WW4C3_4", - "CLK_HROW_WW4C3_5", - "CLK_HROW_WW4C3_6", - "CLK_HROW_WW4C3_7", - "CLK_HROW_WW4END0_0", - "CLK_HROW_WW4END0_1", - "CLK_HROW_WW4END0_2", - "CLK_HROW_WW4END0_3", - "CLK_HROW_WW4END0_4", - "CLK_HROW_WW4END0_5", - "CLK_HROW_WW4END0_6", - "CLK_HROW_WW4END0_7", - "CLK_HROW_WW4END1_0", - "CLK_HROW_WW4END1_1", - "CLK_HROW_WW4END1_2", - "CLK_HROW_WW4END1_3", - "CLK_HROW_WW4END1_4", - "CLK_HROW_WW4END1_5", - "CLK_HROW_WW4END1_6", - "CLK_HROW_WW4END1_7", - "CLK_HROW_WW4END2_0", - "CLK_HROW_WW4END2_1", - "CLK_HROW_WW4END2_2", - "CLK_HROW_WW4END2_3", - "CLK_HROW_WW4END2_4", - "CLK_HROW_WW4END2_5", - "CLK_HROW_WW4END2_6", - "CLK_HROW_WW4END2_7", - "CLK_HROW_WW4END3_0", - "CLK_HROW_WW4END3_1", - "CLK_HROW_WW4END3_2", - "CLK_HROW_WW4END3_3", - "CLK_HROW_WW4END3_4", - "CLK_HROW_WW4END3_5", - "CLK_HROW_WW4END3_6", - "CLK_HROW_WW4END3_7" - ] + "wires": { + "CLK_HROW_BLOCK_OUTS_B0_0": null, + "CLK_HROW_BLOCK_OUTS_B0_1": null, + "CLK_HROW_BLOCK_OUTS_B0_2": null, + "CLK_HROW_BLOCK_OUTS_B0_3": null, + "CLK_HROW_BLOCK_OUTS_B0_4": null, + "CLK_HROW_BLOCK_OUTS_B0_5": null, + "CLK_HROW_BLOCK_OUTS_B0_6": null, + "CLK_HROW_BLOCK_OUTS_B0_7": null, + "CLK_HROW_BLOCK_OUTS_B1_0": null, + "CLK_HROW_BLOCK_OUTS_B1_1": null, + "CLK_HROW_BLOCK_OUTS_B1_2": null, + "CLK_HROW_BLOCK_OUTS_B1_3": null, + "CLK_HROW_BLOCK_OUTS_B1_4": null, + "CLK_HROW_BLOCK_OUTS_B1_5": null, + "CLK_HROW_BLOCK_OUTS_B1_6": null, + "CLK_HROW_BLOCK_OUTS_B1_7": null, + "CLK_HROW_BLOCK_OUTS_B2_0": null, + "CLK_HROW_BLOCK_OUTS_B2_1": null, + "CLK_HROW_BLOCK_OUTS_B2_2": null, + "CLK_HROW_BLOCK_OUTS_B2_3": null, + "CLK_HROW_BLOCK_OUTS_B2_4": null, + "CLK_HROW_BLOCK_OUTS_B2_5": null, + "CLK_HROW_BLOCK_OUTS_B2_6": null, + "CLK_HROW_BLOCK_OUTS_B2_7": null, + "CLK_HROW_BLOCK_OUTS_B3_0": null, + "CLK_HROW_BLOCK_OUTS_B3_1": null, + "CLK_HROW_BLOCK_OUTS_B3_2": null, + "CLK_HROW_BLOCK_OUTS_B3_3": null, + "CLK_HROW_BLOCK_OUTS_B3_4": null, + "CLK_HROW_BLOCK_OUTS_B3_5": null, + "CLK_HROW_BLOCK_OUTS_B3_6": null, + "CLK_HROW_BLOCK_OUTS_B3_7": null, + "CLK_HROW_BUFHCE_CE_L0": null, + "CLK_HROW_BUFHCE_CE_L1": null, + "CLK_HROW_BUFHCE_CE_L10": null, + "CLK_HROW_BUFHCE_CE_L11": null, + "CLK_HROW_BUFHCE_CE_L2": null, + "CLK_HROW_BUFHCE_CE_L3": null, + "CLK_HROW_BUFHCE_CE_L4": null, + "CLK_HROW_BUFHCE_CE_L5": null, + "CLK_HROW_BUFHCE_CE_L6": null, + "CLK_HROW_BUFHCE_CE_L7": null, + "CLK_HROW_BUFHCE_CE_L8": null, + "CLK_HROW_BUFHCE_CE_L9": null, + "CLK_HROW_BUFHCE_CE_R0": null, + "CLK_HROW_BUFHCE_CE_R1": null, + "CLK_HROW_BUFHCE_CE_R10": null, + "CLK_HROW_BUFHCE_CE_R11": null, + "CLK_HROW_BUFHCE_CE_R2": null, + "CLK_HROW_BUFHCE_CE_R3": null, + "CLK_HROW_BUFHCE_CE_R4": null, + "CLK_HROW_BUFHCE_CE_R5": null, + "CLK_HROW_BUFHCE_CE_R6": null, + "CLK_HROW_BUFHCE_CE_R7": null, + "CLK_HROW_BUFHCE_CE_R8": null, + "CLK_HROW_BUFHCE_CE_R9": null, + "CLK_HROW_BYP0_0": null, + "CLK_HROW_BYP0_1": null, + "CLK_HROW_BYP0_2": null, + "CLK_HROW_BYP0_3": null, + "CLK_HROW_BYP0_4": null, + "CLK_HROW_BYP0_5": null, + "CLK_HROW_BYP0_6": null, + "CLK_HROW_BYP0_7": null, + "CLK_HROW_BYP1_0": null, + "CLK_HROW_BYP1_1": null, + "CLK_HROW_BYP1_2": null, + "CLK_HROW_BYP1_3": null, + "CLK_HROW_BYP1_4": null, + "CLK_HROW_BYP1_5": null, + "CLK_HROW_BYP1_6": null, + "CLK_HROW_BYP1_7": null, + "CLK_HROW_BYP2_0": null, + "CLK_HROW_BYP2_1": null, + "CLK_HROW_BYP2_2": null, + "CLK_HROW_BYP2_3": null, + "CLK_HROW_BYP2_4": null, + "CLK_HROW_BYP2_5": null, + "CLK_HROW_BYP2_6": null, + "CLK_HROW_BYP2_7": null, + "CLK_HROW_BYP3_0": null, + "CLK_HROW_BYP3_1": null, + "CLK_HROW_BYP3_2": null, + "CLK_HROW_BYP3_3": null, + "CLK_HROW_BYP3_4": null, + "CLK_HROW_BYP3_5": null, + "CLK_HROW_BYP3_6": null, + "CLK_HROW_BYP3_7": null, + "CLK_HROW_BYP4_0": null, + "CLK_HROW_BYP4_1": null, + "CLK_HROW_BYP4_2": null, + "CLK_HROW_BYP4_3": null, + "CLK_HROW_BYP4_4": null, + "CLK_HROW_BYP4_5": null, + "CLK_HROW_BYP4_6": null, + "CLK_HROW_BYP4_7": null, + "CLK_HROW_BYP5_0": null, + "CLK_HROW_BYP5_1": null, + "CLK_HROW_BYP5_2": null, + "CLK_HROW_BYP5_3": null, + "CLK_HROW_BYP5_4": null, + "CLK_HROW_BYP5_5": null, + "CLK_HROW_BYP5_6": null, + "CLK_HROW_BYP5_7": null, + "CLK_HROW_BYP6_0": null, + "CLK_HROW_BYP6_1": null, + "CLK_HROW_BYP6_2": null, + "CLK_HROW_BYP6_3": null, + "CLK_HROW_BYP6_4": null, + "CLK_HROW_BYP6_5": null, + "CLK_HROW_BYP6_6": null, + "CLK_HROW_BYP6_7": null, + "CLK_HROW_BYP7_0": null, + "CLK_HROW_BYP7_1": null, + "CLK_HROW_BYP7_2": null, + "CLK_HROW_BYP7_3": null, + "CLK_HROW_BYP7_4": null, + "CLK_HROW_BYP7_5": null, + "CLK_HROW_BYP7_6": null, + "CLK_HROW_BYP7_7": null, + "CLK_HROW_CE_INT_BOT0": null, + "CLK_HROW_CE_INT_BOT1": null, + "CLK_HROW_CE_INT_BOT10": null, + "CLK_HROW_CE_INT_BOT11": null, + "CLK_HROW_CE_INT_BOT2": null, + "CLK_HROW_CE_INT_BOT3": null, + "CLK_HROW_CE_INT_BOT4": null, + "CLK_HROW_CE_INT_BOT5": null, + "CLK_HROW_CE_INT_BOT6": null, + "CLK_HROW_CE_INT_BOT7": null, + "CLK_HROW_CE_INT_BOT8": null, + "CLK_HROW_CE_INT_BOT9": null, + "CLK_HROW_CE_INT_TOP0": null, + "CLK_HROW_CE_INT_TOP1": null, + "CLK_HROW_CE_INT_TOP10": null, + "CLK_HROW_CE_INT_TOP11": null, + "CLK_HROW_CE_INT_TOP2": null, + "CLK_HROW_CE_INT_TOP3": null, + "CLK_HROW_CE_INT_TOP4": null, + "CLK_HROW_CE_INT_TOP5": null, + "CLK_HROW_CE_INT_TOP6": null, + "CLK_HROW_CE_INT_TOP7": null, + "CLK_HROW_CE_INT_TOP8": null, + "CLK_HROW_CE_INT_TOP9": null, + "CLK_HROW_CK_BUFHCLK_L0": null, + "CLK_HROW_CK_BUFHCLK_L1": null, + "CLK_HROW_CK_BUFHCLK_L10": null, + "CLK_HROW_CK_BUFHCLK_L11": null, + "CLK_HROW_CK_BUFHCLK_L2": null, + "CLK_HROW_CK_BUFHCLK_L3": null, + "CLK_HROW_CK_BUFHCLK_L4": null, + "CLK_HROW_CK_BUFHCLK_L5": null, + "CLK_HROW_CK_BUFHCLK_L6": null, + "CLK_HROW_CK_BUFHCLK_L7": null, + "CLK_HROW_CK_BUFHCLK_L8": null, + "CLK_HROW_CK_BUFHCLK_L9": null, + "CLK_HROW_CK_BUFHCLK_R0": null, + "CLK_HROW_CK_BUFHCLK_R1": null, + "CLK_HROW_CK_BUFHCLK_R10": null, + "CLK_HROW_CK_BUFHCLK_R11": null, + "CLK_HROW_CK_BUFHCLK_R2": null, + "CLK_HROW_CK_BUFHCLK_R3": null, + "CLK_HROW_CK_BUFHCLK_R4": null, + "CLK_HROW_CK_BUFHCLK_R5": null, + "CLK_HROW_CK_BUFHCLK_R6": null, + "CLK_HROW_CK_BUFHCLK_R7": null, + "CLK_HROW_CK_BUFHCLK_R8": null, + "CLK_HROW_CK_BUFHCLK_R9": null, + "CLK_HROW_CK_BUFRCLK_L0": null, + "CLK_HROW_CK_BUFRCLK_L1": null, + "CLK_HROW_CK_BUFRCLK_L2": null, + "CLK_HROW_CK_BUFRCLK_L3": null, + "CLK_HROW_CK_BUFRCLK_R0": null, + "CLK_HROW_CK_BUFRCLK_R1": null, + "CLK_HROW_CK_BUFRCLK_R2": null, + "CLK_HROW_CK_BUFRCLK_R3": null, + "CLK_HROW_CK_GCLK_IN_TEST0": null, + "CLK_HROW_CK_GCLK_IN_TEST1": null, + "CLK_HROW_CK_GCLK_IN_TEST10": null, + "CLK_HROW_CK_GCLK_IN_TEST11": null, + "CLK_HROW_CK_GCLK_IN_TEST12": null, + "CLK_HROW_CK_GCLK_IN_TEST13": null, + "CLK_HROW_CK_GCLK_IN_TEST14": null, + "CLK_HROW_CK_GCLK_IN_TEST15": null, + "CLK_HROW_CK_GCLK_IN_TEST16": null, + "CLK_HROW_CK_GCLK_IN_TEST17": null, + "CLK_HROW_CK_GCLK_IN_TEST18": null, + "CLK_HROW_CK_GCLK_IN_TEST19": null, + "CLK_HROW_CK_GCLK_IN_TEST2": null, + "CLK_HROW_CK_GCLK_IN_TEST20": null, + "CLK_HROW_CK_GCLK_IN_TEST21": null, + "CLK_HROW_CK_GCLK_IN_TEST22": null, + "CLK_HROW_CK_GCLK_IN_TEST23": null, + "CLK_HROW_CK_GCLK_IN_TEST24": null, + "CLK_HROW_CK_GCLK_IN_TEST25": null, + "CLK_HROW_CK_GCLK_IN_TEST26": null, + "CLK_HROW_CK_GCLK_IN_TEST27": null, + "CLK_HROW_CK_GCLK_IN_TEST28": null, + "CLK_HROW_CK_GCLK_IN_TEST29": null, + "CLK_HROW_CK_GCLK_IN_TEST3": null, + "CLK_HROW_CK_GCLK_IN_TEST30": null, + "CLK_HROW_CK_GCLK_IN_TEST31": null, + "CLK_HROW_CK_GCLK_IN_TEST4": null, + "CLK_HROW_CK_GCLK_IN_TEST5": null, + "CLK_HROW_CK_GCLK_IN_TEST6": null, + "CLK_HROW_CK_GCLK_IN_TEST7": null, + "CLK_HROW_CK_GCLK_IN_TEST8": null, + "CLK_HROW_CK_GCLK_IN_TEST9": null, + "CLK_HROW_CK_GCLK_OUT_TEST0": null, + "CLK_HROW_CK_GCLK_OUT_TEST1": null, + "CLK_HROW_CK_GCLK_OUT_TEST10": null, + "CLK_HROW_CK_GCLK_OUT_TEST11": null, + "CLK_HROW_CK_GCLK_OUT_TEST12": null, + "CLK_HROW_CK_GCLK_OUT_TEST13": null, + "CLK_HROW_CK_GCLK_OUT_TEST14": null, + "CLK_HROW_CK_GCLK_OUT_TEST15": null, + "CLK_HROW_CK_GCLK_OUT_TEST16": null, + "CLK_HROW_CK_GCLK_OUT_TEST17": null, + "CLK_HROW_CK_GCLK_OUT_TEST18": null, + "CLK_HROW_CK_GCLK_OUT_TEST19": null, + "CLK_HROW_CK_GCLK_OUT_TEST2": null, + "CLK_HROW_CK_GCLK_OUT_TEST20": null, + "CLK_HROW_CK_GCLK_OUT_TEST21": null, + "CLK_HROW_CK_GCLK_OUT_TEST22": null, + "CLK_HROW_CK_GCLK_OUT_TEST23": null, + "CLK_HROW_CK_GCLK_OUT_TEST24": null, + "CLK_HROW_CK_GCLK_OUT_TEST25": null, + "CLK_HROW_CK_GCLK_OUT_TEST26": null, + "CLK_HROW_CK_GCLK_OUT_TEST27": null, + "CLK_HROW_CK_GCLK_OUT_TEST28": null, + "CLK_HROW_CK_GCLK_OUT_TEST29": null, + "CLK_HROW_CK_GCLK_OUT_TEST3": null, + "CLK_HROW_CK_GCLK_OUT_TEST30": null, + "CLK_HROW_CK_GCLK_OUT_TEST31": null, + "CLK_HROW_CK_GCLK_OUT_TEST4": null, + "CLK_HROW_CK_GCLK_OUT_TEST5": null, + "CLK_HROW_CK_GCLK_OUT_TEST6": null, + "CLK_HROW_CK_GCLK_OUT_TEST7": null, + "CLK_HROW_CK_GCLK_OUT_TEST8": null, + "CLK_HROW_CK_GCLK_OUT_TEST9": null, + "CLK_HROW_CK_GCLK_TEST0": null, + "CLK_HROW_CK_GCLK_TEST1": null, + "CLK_HROW_CK_GCLK_TEST10": null, + "CLK_HROW_CK_GCLK_TEST11": null, + "CLK_HROW_CK_GCLK_TEST12": null, + "CLK_HROW_CK_GCLK_TEST13": null, + "CLK_HROW_CK_GCLK_TEST14": null, + "CLK_HROW_CK_GCLK_TEST15": null, + "CLK_HROW_CK_GCLK_TEST16": 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"CLK_HROW_R_CK_GCLK31": null, + "CLK_HROW_R_CK_GCLK4": null, + "CLK_HROW_R_CK_GCLK5": null, + "CLK_HROW_R_CK_GCLK6": null, + "CLK_HROW_R_CK_GCLK7": null, + "CLK_HROW_R_CK_GCLK8": null, + "CLK_HROW_R_CK_GCLK9": null, + "CLK_HROW_SE2A0_0": null, + "CLK_HROW_SE2A0_1": null, + "CLK_HROW_SE2A0_2": null, + "CLK_HROW_SE2A0_3": null, + "CLK_HROW_SE2A0_4": null, + "CLK_HROW_SE2A0_5": null, + "CLK_HROW_SE2A0_6": null, + "CLK_HROW_SE2A0_7": null, + "CLK_HROW_SE2A1_0": null, + "CLK_HROW_SE2A1_1": null, + "CLK_HROW_SE2A1_2": null, + "CLK_HROW_SE2A1_3": null, + "CLK_HROW_SE2A1_4": null, + "CLK_HROW_SE2A1_5": null, + "CLK_HROW_SE2A1_6": null, + "CLK_HROW_SE2A1_7": null, + "CLK_HROW_SE2A2_0": null, + "CLK_HROW_SE2A2_1": null, + "CLK_HROW_SE2A2_2": null, + "CLK_HROW_SE2A2_3": null, + "CLK_HROW_SE2A2_4": null, + "CLK_HROW_SE2A2_5": null, + "CLK_HROW_SE2A2_6": null, + "CLK_HROW_SE2A2_7": null, + "CLK_HROW_SE2A3_0": null, + "CLK_HROW_SE2A3_1": null, + "CLK_HROW_SE2A3_2": null, + "CLK_HROW_SE2A3_3": null, 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"CLK_HROW_SW2A0_0": null, + "CLK_HROW_SW2A0_1": null, + "CLK_HROW_SW2A0_2": null, + "CLK_HROW_SW2A0_3": null, + "CLK_HROW_SW2A0_4": null, + "CLK_HROW_SW2A0_5": null, + "CLK_HROW_SW2A0_6": null, + "CLK_HROW_SW2A0_7": null, + "CLK_HROW_SW2A1_0": null, + "CLK_HROW_SW2A1_1": null, + "CLK_HROW_SW2A1_2": null, + "CLK_HROW_SW2A1_3": null, + "CLK_HROW_SW2A1_4": null, + "CLK_HROW_SW2A1_5": null, + "CLK_HROW_SW2A1_6": null, + "CLK_HROW_SW2A1_7": null, + "CLK_HROW_SW2A2_0": null, + "CLK_HROW_SW2A2_1": null, + "CLK_HROW_SW2A2_2": null, + "CLK_HROW_SW2A2_3": null, + "CLK_HROW_SW2A2_4": null, + "CLK_HROW_SW2A2_5": null, + "CLK_HROW_SW2A2_6": null, + "CLK_HROW_SW2A2_7": null, + "CLK_HROW_SW2A3_0": null, + "CLK_HROW_SW2A3_1": null, + "CLK_HROW_SW2A3_2": null, + "CLK_HROW_SW2A3_3": null, + "CLK_HROW_SW2A3_4": null, + "CLK_HROW_SW2A3_5": null, + "CLK_HROW_SW2A3_6": null, + "CLK_HROW_SW2A3_7": null, + "CLK_HROW_SW4A0_0": null, + "CLK_HROW_SW4A0_1": null, + "CLK_HROW_SW4A0_2": null, + "CLK_HROW_SW4A0_3": null, + "CLK_HROW_SW4A0_4": null, + "CLK_HROW_SW4A0_5": null, + "CLK_HROW_SW4A0_6": null, + "CLK_HROW_SW4A0_7": null, + "CLK_HROW_SW4A1_0": null, + "CLK_HROW_SW4A1_1": null, + "CLK_HROW_SW4A1_2": null, + "CLK_HROW_SW4A1_3": null, + "CLK_HROW_SW4A1_4": null, + "CLK_HROW_SW4A1_5": null, + "CLK_HROW_SW4A1_6": null, + "CLK_HROW_SW4A1_7": null, + "CLK_HROW_SW4A2_0": null, + "CLK_HROW_SW4A2_1": null, + "CLK_HROW_SW4A2_2": null, + "CLK_HROW_SW4A2_3": null, + "CLK_HROW_SW4A2_4": null, + "CLK_HROW_SW4A2_5": null, + "CLK_HROW_SW4A2_6": null, + "CLK_HROW_SW4A2_7": null, + "CLK_HROW_SW4A3_0": null, + "CLK_HROW_SW4A3_1": null, + "CLK_HROW_SW4A3_2": null, + "CLK_HROW_SW4A3_3": null, + "CLK_HROW_SW4A3_4": null, + "CLK_HROW_SW4A3_5": null, + "CLK_HROW_SW4A3_6": null, + "CLK_HROW_SW4A3_7": null, + "CLK_HROW_SW4END0_0": null, + "CLK_HROW_SW4END0_1": null, + "CLK_HROW_SW4END0_2": null, + "CLK_HROW_SW4END0_3": null, + "CLK_HROW_SW4END0_4": null, + "CLK_HROW_SW4END0_5": null, + "CLK_HROW_SW4END0_6": null, + "CLK_HROW_SW4END0_7": null, + "CLK_HROW_SW4END1_0": null, + "CLK_HROW_SW4END1_1": null, + "CLK_HROW_SW4END1_2": null, + "CLK_HROW_SW4END1_3": null, + "CLK_HROW_SW4END1_4": null, + "CLK_HROW_SW4END1_5": null, + "CLK_HROW_SW4END1_6": null, + "CLK_HROW_SW4END1_7": null, + "CLK_HROW_SW4END2_0": null, + "CLK_HROW_SW4END2_1": null, + "CLK_HROW_SW4END2_2": null, + "CLK_HROW_SW4END2_3": null, + "CLK_HROW_SW4END2_4": null, + "CLK_HROW_SW4END2_5": null, + "CLK_HROW_SW4END2_6": null, + "CLK_HROW_SW4END2_7": null, + "CLK_HROW_SW4END3_0": null, + "CLK_HROW_SW4END3_1": null, + "CLK_HROW_SW4END3_2": null, + "CLK_HROW_SW4END3_3": null, + "CLK_HROW_SW4END3_4": null, + "CLK_HROW_SW4END3_5": null, + "CLK_HROW_SW4END3_6": null, + "CLK_HROW_SW4END3_7": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN0": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN1": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN10": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN11": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN12": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN13": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN14": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN15": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN16": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN17": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN18": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN19": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN2": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN20": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN21": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN22": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN23": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN24": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN25": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN26": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN27": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN28": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN29": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN3": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN30": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN31": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN4": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN5": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN6": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN7": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN8": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCIN9": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO0": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO1": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO10": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO11": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO12": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO13": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO14": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO15": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO16": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO17": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO18": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO19": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO2": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO20": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO21": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO22": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO23": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO24": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO25": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO26": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO27": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO28": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO29": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO3": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO30": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO31": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO4": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO5": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO6": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO7": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO8": null, + "CLK_HROW_TOP_R_CK_BUFG_CASCO9": null, + "CLK_HROW_WL1END0_0": null, + "CLK_HROW_WL1END0_1": null, + "CLK_HROW_WL1END0_2": null, + "CLK_HROW_WL1END0_3": null, + "CLK_HROW_WL1END0_4": null, + "CLK_HROW_WL1END0_5": null, + "CLK_HROW_WL1END0_6": null, + "CLK_HROW_WL1END0_7": null, + "CLK_HROW_WL1END1_0": null, + "CLK_HROW_WL1END1_1": null, + "CLK_HROW_WL1END1_2": null, + "CLK_HROW_WL1END1_3": null, + "CLK_HROW_WL1END1_4": null, + "CLK_HROW_WL1END1_5": null, + "CLK_HROW_WL1END1_6": null, + "CLK_HROW_WL1END1_7": null, + "CLK_HROW_WL1END2_0": null, + "CLK_HROW_WL1END2_1": null, + "CLK_HROW_WL1END2_2": null, + "CLK_HROW_WL1END2_3": null, + "CLK_HROW_WL1END2_4": null, + "CLK_HROW_WL1END2_5": null, + "CLK_HROW_WL1END2_6": null, + "CLK_HROW_WL1END2_7": null, + "CLK_HROW_WL1END3_0": null, + "CLK_HROW_WL1END3_1": null, + "CLK_HROW_WL1END3_2": null, + "CLK_HROW_WL1END3_3": null, + "CLK_HROW_WL1END3_4": null, + "CLK_HROW_WL1END3_5": null, + "CLK_HROW_WL1END3_6": null, + "CLK_HROW_WL1END3_7": null, + "CLK_HROW_WR1END0_0": null, + "CLK_HROW_WR1END0_1": null, + "CLK_HROW_WR1END0_2": null, + "CLK_HROW_WR1END0_3": null, + "CLK_HROW_WR1END0_4": null, + "CLK_HROW_WR1END0_5": null, + "CLK_HROW_WR1END0_6": null, + "CLK_HROW_WR1END0_7": null, + "CLK_HROW_WR1END1_0": null, + "CLK_HROW_WR1END1_1": null, + "CLK_HROW_WR1END1_2": null, + "CLK_HROW_WR1END1_3": null, + "CLK_HROW_WR1END1_4": null, + "CLK_HROW_WR1END1_5": null, + "CLK_HROW_WR1END1_6": null, + "CLK_HROW_WR1END1_7": null, + "CLK_HROW_WR1END2_0": null, + "CLK_HROW_WR1END2_1": null, + "CLK_HROW_WR1END2_2": null, + "CLK_HROW_WR1END2_3": null, + "CLK_HROW_WR1END2_4": null, + "CLK_HROW_WR1END2_5": null, + "CLK_HROW_WR1END2_6": null, + "CLK_HROW_WR1END2_7": null, + "CLK_HROW_WR1END3_0": null, + "CLK_HROW_WR1END3_1": null, + "CLK_HROW_WR1END3_2": null, + "CLK_HROW_WR1END3_3": null, + "CLK_HROW_WR1END3_4": null, + "CLK_HROW_WR1END3_5": null, + "CLK_HROW_WR1END3_6": null, + "CLK_HROW_WR1END3_7": null, + "CLK_HROW_WW2A0_0": null, + "CLK_HROW_WW2A0_1": null, + "CLK_HROW_WW2A0_2": null, + "CLK_HROW_WW2A0_3": null, + "CLK_HROW_WW2A0_4": null, + "CLK_HROW_WW2A0_5": null, + "CLK_HROW_WW2A0_6": null, + "CLK_HROW_WW2A0_7": null, + "CLK_HROW_WW2A1_0": null, + "CLK_HROW_WW2A1_1": null, + "CLK_HROW_WW2A1_2": null, + "CLK_HROW_WW2A1_3": null, + "CLK_HROW_WW2A1_4": null, + "CLK_HROW_WW2A1_5": null, + "CLK_HROW_WW2A1_6": null, + "CLK_HROW_WW2A1_7": null, + "CLK_HROW_WW2A2_0": null, + "CLK_HROW_WW2A2_1": null, + "CLK_HROW_WW2A2_2": null, + "CLK_HROW_WW2A2_3": null, + "CLK_HROW_WW2A2_4": null, + "CLK_HROW_WW2A2_5": null, + "CLK_HROW_WW2A2_6": null, + "CLK_HROW_WW2A2_7": null, + "CLK_HROW_WW2A3_0": null, + "CLK_HROW_WW2A3_1": null, + "CLK_HROW_WW2A3_2": null, + "CLK_HROW_WW2A3_3": null, + "CLK_HROW_WW2A3_4": null, + "CLK_HROW_WW2A3_5": null, + "CLK_HROW_WW2A3_6": null, + "CLK_HROW_WW2A3_7": null, + "CLK_HROW_WW2END0_0": null, + "CLK_HROW_WW2END0_1": null, + "CLK_HROW_WW2END0_2": null, + "CLK_HROW_WW2END0_3": null, + "CLK_HROW_WW2END0_4": null, + "CLK_HROW_WW2END0_5": null, + "CLK_HROW_WW2END0_6": null, + "CLK_HROW_WW2END0_7": null, + "CLK_HROW_WW2END1_0": null, + "CLK_HROW_WW2END1_1": null, + "CLK_HROW_WW2END1_2": null, + "CLK_HROW_WW2END1_3": null, + "CLK_HROW_WW2END1_4": null, + "CLK_HROW_WW2END1_5": null, + "CLK_HROW_WW2END1_6": null, + "CLK_HROW_WW2END1_7": null, + "CLK_HROW_WW2END2_0": null, + "CLK_HROW_WW2END2_1": null, + "CLK_HROW_WW2END2_2": null, + "CLK_HROW_WW2END2_3": null, + "CLK_HROW_WW2END2_4": null, + "CLK_HROW_WW2END2_5": null, + "CLK_HROW_WW2END2_6": null, + "CLK_HROW_WW2END2_7": null, + "CLK_HROW_WW2END3_0": null, + "CLK_HROW_WW2END3_1": null, + "CLK_HROW_WW2END3_2": null, + "CLK_HROW_WW2END3_3": null, + "CLK_HROW_WW2END3_4": null, + "CLK_HROW_WW2END3_5": null, + "CLK_HROW_WW2END3_6": null, + "CLK_HROW_WW2END3_7": null, + "CLK_HROW_WW4A0_0": null, + "CLK_HROW_WW4A0_1": null, + "CLK_HROW_WW4A0_2": null, + "CLK_HROW_WW4A0_3": null, + "CLK_HROW_WW4A0_4": null, + "CLK_HROW_WW4A0_5": null, + "CLK_HROW_WW4A0_6": null, + "CLK_HROW_WW4A0_7": null, + "CLK_HROW_WW4A1_0": null, + "CLK_HROW_WW4A1_1": null, + "CLK_HROW_WW4A1_2": null, + "CLK_HROW_WW4A1_3": null, + "CLK_HROW_WW4A1_4": null, + "CLK_HROW_WW4A1_5": null, + "CLK_HROW_WW4A1_6": null, + "CLK_HROW_WW4A1_7": null, + "CLK_HROW_WW4A2_0": null, + "CLK_HROW_WW4A2_1": null, + "CLK_HROW_WW4A2_2": null, + "CLK_HROW_WW4A2_3": null, + "CLK_HROW_WW4A2_4": null, + "CLK_HROW_WW4A2_5": null, + "CLK_HROW_WW4A2_6": null, + "CLK_HROW_WW4A2_7": null, + "CLK_HROW_WW4A3_0": null, + "CLK_HROW_WW4A3_1": null, + "CLK_HROW_WW4A3_2": null, + "CLK_HROW_WW4A3_3": null, + "CLK_HROW_WW4A3_4": null, + "CLK_HROW_WW4A3_5": null, + "CLK_HROW_WW4A3_6": null, + "CLK_HROW_WW4A3_7": null, + "CLK_HROW_WW4B0_0": null, + "CLK_HROW_WW4B0_1": null, + "CLK_HROW_WW4B0_2": null, + "CLK_HROW_WW4B0_3": null, + "CLK_HROW_WW4B0_4": null, + "CLK_HROW_WW4B0_5": null, + "CLK_HROW_WW4B0_6": null, + "CLK_HROW_WW4B0_7": null, + "CLK_HROW_WW4B1_0": null, + "CLK_HROW_WW4B1_1": null, + "CLK_HROW_WW4B1_2": null, + "CLK_HROW_WW4B1_3": null, + "CLK_HROW_WW4B1_4": null, + "CLK_HROW_WW4B1_5": null, + "CLK_HROW_WW4B1_6": null, + "CLK_HROW_WW4B1_7": null, + "CLK_HROW_WW4B2_0": null, + "CLK_HROW_WW4B2_1": null, + "CLK_HROW_WW4B2_2": null, + "CLK_HROW_WW4B2_3": null, + "CLK_HROW_WW4B2_4": null, + "CLK_HROW_WW4B2_5": null, + "CLK_HROW_WW4B2_6": null, + "CLK_HROW_WW4B2_7": null, + "CLK_HROW_WW4B3_0": null, + "CLK_HROW_WW4B3_1": null, + "CLK_HROW_WW4B3_2": null, + "CLK_HROW_WW4B3_3": null, + "CLK_HROW_WW4B3_4": null, + "CLK_HROW_WW4B3_5": null, + "CLK_HROW_WW4B3_6": null, + "CLK_HROW_WW4B3_7": null, + "CLK_HROW_WW4C0_0": null, + "CLK_HROW_WW4C0_1": null, + "CLK_HROW_WW4C0_2": null, + "CLK_HROW_WW4C0_3": null, + "CLK_HROW_WW4C0_4": null, + "CLK_HROW_WW4C0_5": null, + "CLK_HROW_WW4C0_6": null, + "CLK_HROW_WW4C0_7": null, + "CLK_HROW_WW4C1_0": null, + "CLK_HROW_WW4C1_1": null, + "CLK_HROW_WW4C1_2": null, + "CLK_HROW_WW4C1_3": null, + "CLK_HROW_WW4C1_4": null, + "CLK_HROW_WW4C1_5": null, + "CLK_HROW_WW4C1_6": null, + "CLK_HROW_WW4C1_7": null, + "CLK_HROW_WW4C2_0": null, + "CLK_HROW_WW4C2_1": null, + "CLK_HROW_WW4C2_2": null, + "CLK_HROW_WW4C2_3": null, + "CLK_HROW_WW4C2_4": null, + "CLK_HROW_WW4C2_5": null, + "CLK_HROW_WW4C2_6": null, + "CLK_HROW_WW4C2_7": null, + "CLK_HROW_WW4C3_0": null, + "CLK_HROW_WW4C3_1": null, + "CLK_HROW_WW4C3_2": null, + "CLK_HROW_WW4C3_3": null, + "CLK_HROW_WW4C3_4": null, + "CLK_HROW_WW4C3_5": null, + "CLK_HROW_WW4C3_6": null, + "CLK_HROW_WW4C3_7": null, + "CLK_HROW_WW4END0_0": null, + "CLK_HROW_WW4END0_1": null, + "CLK_HROW_WW4END0_2": null, + "CLK_HROW_WW4END0_3": null, + "CLK_HROW_WW4END0_4": null, + "CLK_HROW_WW4END0_5": null, + "CLK_HROW_WW4END0_6": null, + "CLK_HROW_WW4END0_7": null, + "CLK_HROW_WW4END1_0": null, + "CLK_HROW_WW4END1_1": null, + "CLK_HROW_WW4END1_2": null, + "CLK_HROW_WW4END1_3": null, + "CLK_HROW_WW4END1_4": null, + "CLK_HROW_WW4END1_5": null, + "CLK_HROW_WW4END1_6": null, + "CLK_HROW_WW4END1_7": null, + "CLK_HROW_WW4END2_0": null, + "CLK_HROW_WW4END2_1": null, + "CLK_HROW_WW4END2_2": null, + "CLK_HROW_WW4END2_3": null, + "CLK_HROW_WW4END2_4": null, + "CLK_HROW_WW4END2_5": null, + "CLK_HROW_WW4END2_6": null, + "CLK_HROW_WW4END2_7": null, + "CLK_HROW_WW4END3_0": null, + "CLK_HROW_WW4END3_1": null, + "CLK_HROW_WW4END3_2": null, + "CLK_HROW_WW4END3_3": null, + "CLK_HROW_WW4END3_4": null, + "CLK_HROW_WW4END3_5": null, + "CLK_HROW_WW4END3_6": null, + "CLK_HROW_WW4END3_7": null + } } diff --git a/kintex7/tile_type_CLK_MTBF2.json b/kintex7/tile_type_CLK_MTBF2.json index 20b28cb..cf44fa7 100644 --- a/kintex7/tile_type_CLK_MTBF2.json +++ b/kintex7/tile_type_CLK_MTBF2.json @@ -2,364 +2,364 @@ "pips": {}, "sites": [], "tile_type": "CLK_MTBF2", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3", - "CLK_MTBF2_CLK", - "CLK_MTBF2_DIN", - "CLK_MTBF2_EN", - "CLK_MTBF2_Q0B", - "CLK_MTBF2_Q1B", - "CLK_MTBF2_Q2B", - "CLK_MTBF2_Q3B", - "CLK_MTBF2_Q4B", - "CLK_MTBF2_Q5B", - "CLK_MTBF2_Q6B", - "CLK_MTBF2_Q7B", - "CLK_MTBF2_RESET", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP7_0", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK1_0", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX9_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS9_0" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null, + "CLK_MTBF2_CLK": null, + "CLK_MTBF2_DIN": null, + "CLK_MTBF2_EN": null, + "CLK_MTBF2_Q0B": null, + "CLK_MTBF2_Q1B": null, + "CLK_MTBF2_Q2B": null, + "CLK_MTBF2_Q3B": null, + "CLK_MTBF2_Q4B": null, + "CLK_MTBF2_Q5B": null, + "CLK_MTBF2_Q6B": null, + "CLK_MTBF2_Q7B": null, + "CLK_MTBF2_RESET": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_CLK0_0": null, + "CLK_PMV_CLK1_0": null, + "CLK_PMV_CTRL0_0": null, + "CLK_PMV_CTRL1_0": null, + "CLK_PMV_FAN0_0": null, + "CLK_PMV_FAN1_0": null, + "CLK_PMV_FAN2_0": null, + "CLK_PMV_FAN3_0": null, + "CLK_PMV_FAN4_0": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX17_0": null, + "CLK_PMV_IMUX18_0": null, + "CLK_PMV_IMUX19_0": null, + "CLK_PMV_IMUX1_0": null, + "CLK_PMV_IMUX20_0": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_LOGIC_OUTS0_0": null, + "CLK_PMV_LOGIC_OUTS10_0": null, + "CLK_PMV_LOGIC_OUTS11_0": null, + "CLK_PMV_LOGIC_OUTS12_0": null, + "CLK_PMV_LOGIC_OUTS13_0": null, + "CLK_PMV_LOGIC_OUTS14_0": null, + "CLK_PMV_LOGIC_OUTS15_0": null, + "CLK_PMV_LOGIC_OUTS16_0": null, + "CLK_PMV_LOGIC_OUTS17_0": null, + "CLK_PMV_LOGIC_OUTS18_0": null, + "CLK_PMV_LOGIC_OUTS19_0": null, + "CLK_PMV_LOGIC_OUTS1_0": null, + "CLK_PMV_LOGIC_OUTS20_0": null, + "CLK_PMV_LOGIC_OUTS21_0": null, + "CLK_PMV_LOGIC_OUTS22_0": null, + "CLK_PMV_LOGIC_OUTS23_0": null, + "CLK_PMV_LOGIC_OUTS2_0": null, + "CLK_PMV_LOGIC_OUTS3_0": null, + "CLK_PMV_LOGIC_OUTS4_0": null, + "CLK_PMV_LOGIC_OUTS5_0": null, + "CLK_PMV_LOGIC_OUTS6_0": null, + "CLK_PMV_LOGIC_OUTS7_0": null, + "CLK_PMV_LOGIC_OUTS8_0": null, + "CLK_PMV_LOGIC_OUTS9_0": null + } } diff --git a/kintex7/tile_type_CLK_PMV.json b/kintex7/tile_type_CLK_PMV.json index fdb92ec..35d034c 100644 --- a/kintex7/tile_type_CLK_PMV.json +++ b/kintex7/tile_type_CLK_PMV.json @@ -2,1670 +2,1670 @@ "pips": {}, "sites": [], "tile_type": "CLK_PMV", - "wires": [ - "CLK_PMV_A0", - "CLK_PMV_A1", - "CLK_PMV_A2", - "CLK_PMV_A3", - "CLK_PMV_A4", - "CLK_PMV_A5", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP0_1", - "CLK_PMV_BYP0_2", - "CLK_PMV_BYP0_3", - "CLK_PMV_BYP0_4", - "CLK_PMV_BYP0_5", - "CLK_PMV_BYP0_6", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP1_1", - "CLK_PMV_BYP1_2", - "CLK_PMV_BYP1_3", - "CLK_PMV_BYP1_4", - "CLK_PMV_BYP1_5", - "CLK_PMV_BYP1_6", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP2_1", - "CLK_PMV_BYP2_2", - "CLK_PMV_BYP2_3", - "CLK_PMV_BYP2_4", - "CLK_PMV_BYP2_5", - "CLK_PMV_BYP2_6", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP3_1", - "CLK_PMV_BYP3_2", - "CLK_PMV_BYP3_3", - "CLK_PMV_BYP3_4", - "CLK_PMV_BYP3_5", - "CLK_PMV_BYP3_6", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP4_1", - "CLK_PMV_BYP4_2", - "CLK_PMV_BYP4_3", - "CLK_PMV_BYP4_4", - "CLK_PMV_BYP4_5", - "CLK_PMV_BYP4_6", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP5_1", - "CLK_PMV_BYP5_2", - "CLK_PMV_BYP5_3", - "CLK_PMV_BYP5_4", - "CLK_PMV_BYP5_5", - "CLK_PMV_BYP5_6", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP6_1", - "CLK_PMV_BYP6_2", - "CLK_PMV_BYP6_3", - "CLK_PMV_BYP6_4", - "CLK_PMV_BYP6_5", - "CLK_PMV_BYP6_6", - "CLK_PMV_BYP7_0", - "CLK_PMV_BYP7_1", - "CLK_PMV_BYP7_2", - "CLK_PMV_BYP7_3", - "CLK_PMV_BYP7_4", - "CLK_PMV_BYP7_5", - "CLK_PMV_BYP7_6", - "CLK_PMV_CK_BUFG_CASC0", - "CLK_PMV_CK_BUFG_CASC1", - "CLK_PMV_CK_BUFG_CASC10", - "CLK_PMV_CK_BUFG_CASC11", - "CLK_PMV_CK_BUFG_CASC12", - "CLK_PMV_CK_BUFG_CASC13", - "CLK_PMV_CK_BUFG_CASC14", - "CLK_PMV_CK_BUFG_CASC15", - "CLK_PMV_CK_BUFG_CASC16", - "CLK_PMV_CK_BUFG_CASC17", - "CLK_PMV_CK_BUFG_CASC18", - "CLK_PMV_CK_BUFG_CASC19", - "CLK_PMV_CK_BUFG_CASC2", - "CLK_PMV_CK_BUFG_CASC20", - "CLK_PMV_CK_BUFG_CASC21", - "CLK_PMV_CK_BUFG_CASC22", - "CLK_PMV_CK_BUFG_CASC23", - "CLK_PMV_CK_BUFG_CASC24", - "CLK_PMV_CK_BUFG_CASC25", - "CLK_PMV_CK_BUFG_CASC26", - "CLK_PMV_CK_BUFG_CASC27", - "CLK_PMV_CK_BUFG_CASC28", - "CLK_PMV_CK_BUFG_CASC29", - "CLK_PMV_CK_BUFG_CASC3", - "CLK_PMV_CK_BUFG_CASC30", - "CLK_PMV_CK_BUFG_CASC31", - "CLK_PMV_CK_BUFG_CASC4", - "CLK_PMV_CK_BUFG_CASC5", - "CLK_PMV_CK_BUFG_CASC6", - "CLK_PMV_CK_BUFG_CASC7", - "CLK_PMV_CK_BUFG_CASC8", - "CLK_PMV_CK_BUFG_CASC9", - "CLK_PMV_CK_GCLK0", - "CLK_PMV_CK_GCLK1", - "CLK_PMV_CK_GCLK10", - "CLK_PMV_CK_GCLK11", - "CLK_PMV_CK_GCLK12", - "CLK_PMV_CK_GCLK13", - "CLK_PMV_CK_GCLK14", - "CLK_PMV_CK_GCLK15", - "CLK_PMV_CK_GCLK16", - "CLK_PMV_CK_GCLK17", - "CLK_PMV_CK_GCLK18", - "CLK_PMV_CK_GCLK19", - "CLK_PMV_CK_GCLK2", - "CLK_PMV_CK_GCLK20", - "CLK_PMV_CK_GCLK21", - "CLK_PMV_CK_GCLK22", - "CLK_PMV_CK_GCLK23", - "CLK_PMV_CK_GCLK24", - "CLK_PMV_CK_GCLK25", - "CLK_PMV_CK_GCLK26", - "CLK_PMV_CK_GCLK27", - "CLK_PMV_CK_GCLK28", - "CLK_PMV_CK_GCLK29", - "CLK_PMV_CK_GCLK3", - "CLK_PMV_CK_GCLK30", - "CLK_PMV_CK_GCLK31", - "CLK_PMV_CK_GCLK4", - "CLK_PMV_CK_GCLK5", - "CLK_PMV_CK_GCLK6", - "CLK_PMV_CK_GCLK7", - "CLK_PMV_CK_GCLK8", - "CLK_PMV_CK_GCLK9", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK0_1", - "CLK_PMV_CLK0_2", - "CLK_PMV_CLK0_3", - "CLK_PMV_CLK0_4", - "CLK_PMV_CLK0_5", - "CLK_PMV_CLK0_6", - "CLK_PMV_CLK1_0", - "CLK_PMV_CLK1_1", - "CLK_PMV_CLK1_2", - "CLK_PMV_CLK1_3", - "CLK_PMV_CLK1_4", - "CLK_PMV_CLK1_5", - "CLK_PMV_CLK1_6", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL0_1", - "CLK_PMV_CTRL0_2", - "CLK_PMV_CTRL0_3", - "CLK_PMV_CTRL0_4", - "CLK_PMV_CTRL0_5", - "CLK_PMV_CTRL0_6", - "CLK_PMV_CTRL1_0", - "CLK_PMV_CTRL1_1", - "CLK_PMV_CTRL1_2", - "CLK_PMV_CTRL1_3", - "CLK_PMV_CTRL1_4", - "CLK_PMV_CTRL1_5", - "CLK_PMV_CTRL1_6", - "CLK_PMV_EE2A0_0", - "CLK_PMV_EE2A0_1", - "CLK_PMV_EE2A0_2", - "CLK_PMV_EE2A0_3", - "CLK_PMV_EE2A0_4", - "CLK_PMV_EE2A0_5", - "CLK_PMV_EE2A0_6", - "CLK_PMV_EE2A1_0", - "CLK_PMV_EE2A1_1", - "CLK_PMV_EE2A1_2", - "CLK_PMV_EE2A1_3", - "CLK_PMV_EE2A1_4", - "CLK_PMV_EE2A1_5", - "CLK_PMV_EE2A1_6", - "CLK_PMV_EE2A2_0", - "CLK_PMV_EE2A2_1", - "CLK_PMV_EE2A2_2", - "CLK_PMV_EE2A2_3", - "CLK_PMV_EE2A2_4", - "CLK_PMV_EE2A2_5", - "CLK_PMV_EE2A2_6", - "CLK_PMV_EE2A3_0", - "CLK_PMV_EE2A3_1", - "CLK_PMV_EE2A3_2", - "CLK_PMV_EE2A3_3", - "CLK_PMV_EE2A3_4", - "CLK_PMV_EE2A3_5", - "CLK_PMV_EE2A3_6", - "CLK_PMV_EE2BEG0_0", - "CLK_PMV_EE2BEG0_1", - "CLK_PMV_EE2BEG0_2", - "CLK_PMV_EE2BEG0_3", - "CLK_PMV_EE2BEG0_4", - "CLK_PMV_EE2BEG0_5", - "CLK_PMV_EE2BEG0_6", - "CLK_PMV_EE2BEG1_0", - "CLK_PMV_EE2BEG1_1", - "CLK_PMV_EE2BEG1_2", - "CLK_PMV_EE2BEG1_3", - "CLK_PMV_EE2BEG1_4", - "CLK_PMV_EE2BEG1_5", - "CLK_PMV_EE2BEG1_6", - "CLK_PMV_EE2BEG2_0", - "CLK_PMV_EE2BEG2_1", - "CLK_PMV_EE2BEG2_2", - "CLK_PMV_EE2BEG2_3", - "CLK_PMV_EE2BEG2_4", - "CLK_PMV_EE2BEG2_5", - "CLK_PMV_EE2BEG2_6", - "CLK_PMV_EE2BEG3_0", - "CLK_PMV_EE2BEG3_1", - "CLK_PMV_EE2BEG3_2", - "CLK_PMV_EE2BEG3_3", - "CLK_PMV_EE2BEG3_4", - "CLK_PMV_EE2BEG3_5", - "CLK_PMV_EE2BEG3_6", - "CLK_PMV_EE4A0_0", - "CLK_PMV_EE4A0_1", - "CLK_PMV_EE4A0_2", - "CLK_PMV_EE4A0_3", - "CLK_PMV_EE4A0_4", - "CLK_PMV_EE4A0_5", - "CLK_PMV_EE4A0_6", - "CLK_PMV_EE4A1_0", - "CLK_PMV_EE4A1_1", - "CLK_PMV_EE4A1_2", - "CLK_PMV_EE4A1_3", - "CLK_PMV_EE4A1_4", - "CLK_PMV_EE4A1_5", - "CLK_PMV_EE4A1_6", - "CLK_PMV_EE4A2_0", - "CLK_PMV_EE4A2_1", - "CLK_PMV_EE4A2_2", - "CLK_PMV_EE4A2_3", - "CLK_PMV_EE4A2_4", - "CLK_PMV_EE4A2_5", - "CLK_PMV_EE4A2_6", - "CLK_PMV_EE4A3_0", - "CLK_PMV_EE4A3_1", - "CLK_PMV_EE4A3_2", - "CLK_PMV_EE4A3_3", - "CLK_PMV_EE4A3_4", - "CLK_PMV_EE4A3_5", - "CLK_PMV_EE4A3_6", - "CLK_PMV_EE4B0_0", - "CLK_PMV_EE4B0_1", - "CLK_PMV_EE4B0_2", - "CLK_PMV_EE4B0_3", - "CLK_PMV_EE4B0_4", - "CLK_PMV_EE4B0_5", - "CLK_PMV_EE4B0_6", - "CLK_PMV_EE4B1_0", - "CLK_PMV_EE4B1_1", - "CLK_PMV_EE4B1_2", - "CLK_PMV_EE4B1_3", - "CLK_PMV_EE4B1_4", - "CLK_PMV_EE4B1_5", - "CLK_PMV_EE4B1_6", - "CLK_PMV_EE4B2_0", - "CLK_PMV_EE4B2_1", - "CLK_PMV_EE4B2_2", - "CLK_PMV_EE4B2_3", - "CLK_PMV_EE4B2_4", - "CLK_PMV_EE4B2_5", - "CLK_PMV_EE4B2_6", - "CLK_PMV_EE4B3_0", - "CLK_PMV_EE4B3_1", - "CLK_PMV_EE4B3_2", - "CLK_PMV_EE4B3_3", - "CLK_PMV_EE4B3_4", - "CLK_PMV_EE4B3_5", - "CLK_PMV_EE4B3_6", - "CLK_PMV_EE4BEG0_0", - "CLK_PMV_EE4BEG0_1", - "CLK_PMV_EE4BEG0_2", - "CLK_PMV_EE4BEG0_3", - "CLK_PMV_EE4BEG0_4", - "CLK_PMV_EE4BEG0_5", - "CLK_PMV_EE4BEG0_6", - "CLK_PMV_EE4BEG1_0", - "CLK_PMV_EE4BEG1_1", - "CLK_PMV_EE4BEG1_2", - "CLK_PMV_EE4BEG1_3", - "CLK_PMV_EE4BEG1_4", - "CLK_PMV_EE4BEG1_5", - "CLK_PMV_EE4BEG1_6", - "CLK_PMV_EE4BEG2_0", - "CLK_PMV_EE4BEG2_1", - "CLK_PMV_EE4BEG2_2", - "CLK_PMV_EE4BEG2_3", - "CLK_PMV_EE4BEG2_4", - "CLK_PMV_EE4BEG2_5", - "CLK_PMV_EE4BEG2_6", - "CLK_PMV_EE4BEG3_0", - "CLK_PMV_EE4BEG3_1", - "CLK_PMV_EE4BEG3_2", - "CLK_PMV_EE4BEG3_3", - "CLK_PMV_EE4BEG3_4", - "CLK_PMV_EE4BEG3_5", - "CLK_PMV_EE4BEG3_6", - "CLK_PMV_EE4C0_0", - "CLK_PMV_EE4C0_1", - "CLK_PMV_EE4C0_2", - "CLK_PMV_EE4C0_3", - "CLK_PMV_EE4C0_4", - "CLK_PMV_EE4C0_5", - "CLK_PMV_EE4C0_6", - "CLK_PMV_EE4C1_0", - "CLK_PMV_EE4C1_1", - "CLK_PMV_EE4C1_2", - "CLK_PMV_EE4C1_3", - "CLK_PMV_EE4C1_4", - "CLK_PMV_EE4C1_5", - "CLK_PMV_EE4C1_6", - "CLK_PMV_EE4C2_0", - "CLK_PMV_EE4C2_1", - "CLK_PMV_EE4C2_2", - "CLK_PMV_EE4C2_3", - "CLK_PMV_EE4C2_4", - "CLK_PMV_EE4C2_5", - "CLK_PMV_EE4C2_6", - "CLK_PMV_EE4C3_0", - "CLK_PMV_EE4C3_1", - "CLK_PMV_EE4C3_2", - "CLK_PMV_EE4C3_3", - "CLK_PMV_EE4C3_4", - "CLK_PMV_EE4C3_5", - "CLK_PMV_EE4C3_6", - "CLK_PMV_EL1BEG0_0", - "CLK_PMV_EL1BEG0_1", - "CLK_PMV_EL1BEG0_2", - "CLK_PMV_EL1BEG0_3", - "CLK_PMV_EL1BEG0_4", - "CLK_PMV_EL1BEG0_5", - "CLK_PMV_EL1BEG0_6", - "CLK_PMV_EL1BEG1_0", - "CLK_PMV_EL1BEG1_1", - "CLK_PMV_EL1BEG1_2", - "CLK_PMV_EL1BEG1_3", - "CLK_PMV_EL1BEG1_4", - "CLK_PMV_EL1BEG1_5", - "CLK_PMV_EL1BEG1_6", - "CLK_PMV_EL1BEG2_0", - "CLK_PMV_EL1BEG2_1", - "CLK_PMV_EL1BEG2_2", - "CLK_PMV_EL1BEG2_3", - "CLK_PMV_EL1BEG2_4", - "CLK_PMV_EL1BEG2_5", - "CLK_PMV_EL1BEG2_6", - "CLK_PMV_EL1BEG3_0", - "CLK_PMV_EL1BEG3_1", - "CLK_PMV_EL1BEG3_2", - "CLK_PMV_EL1BEG3_3", - "CLK_PMV_EL1BEG3_4", - "CLK_PMV_EL1BEG3_5", - "CLK_PMV_EL1BEG3_6", - "CLK_PMV_EN", - "CLK_PMV_ER1BEG0_0", - "CLK_PMV_ER1BEG0_1", - "CLK_PMV_ER1BEG0_2", - "CLK_PMV_ER1BEG0_3", - "CLK_PMV_ER1BEG0_4", - "CLK_PMV_ER1BEG0_5", - "CLK_PMV_ER1BEG0_6", - "CLK_PMV_ER1BEG1_0", - "CLK_PMV_ER1BEG1_1", - "CLK_PMV_ER1BEG1_2", - "CLK_PMV_ER1BEG1_3", - "CLK_PMV_ER1BEG1_4", - "CLK_PMV_ER1BEG1_5", - "CLK_PMV_ER1BEG1_6", - "CLK_PMV_ER1BEG2_0", - "CLK_PMV_ER1BEG2_1", - "CLK_PMV_ER1BEG2_2", - "CLK_PMV_ER1BEG2_3", - "CLK_PMV_ER1BEG2_4", - "CLK_PMV_ER1BEG2_5", - "CLK_PMV_ER1BEG2_6", - "CLK_PMV_ER1BEG3_0", - "CLK_PMV_ER1BEG3_1", - "CLK_PMV_ER1BEG3_2", - "CLK_PMV_ER1BEG3_3", - "CLK_PMV_ER1BEG3_4", - "CLK_PMV_ER1BEG3_5", - "CLK_PMV_ER1BEG3_6", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN0_1", - "CLK_PMV_FAN0_2", - "CLK_PMV_FAN0_3", - "CLK_PMV_FAN0_4", - "CLK_PMV_FAN0_5", - "CLK_PMV_FAN0_6", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN1_1", - "CLK_PMV_FAN1_2", - "CLK_PMV_FAN1_3", - "CLK_PMV_FAN1_4", - "CLK_PMV_FAN1_5", - "CLK_PMV_FAN1_6", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN2_1", - "CLK_PMV_FAN2_2", - "CLK_PMV_FAN2_3", - "CLK_PMV_FAN2_4", - "CLK_PMV_FAN2_5", - "CLK_PMV_FAN2_6", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN3_1", - "CLK_PMV_FAN3_2", - "CLK_PMV_FAN3_3", - "CLK_PMV_FAN3_4", - "CLK_PMV_FAN3_5", - "CLK_PMV_FAN3_6", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN4_1", - "CLK_PMV_FAN4_2", - "CLK_PMV_FAN4_3", - "CLK_PMV_FAN4_4", - "CLK_PMV_FAN4_5", - "CLK_PMV_FAN4_6", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN5_1", - "CLK_PMV_FAN5_2", - "CLK_PMV_FAN5_3", - "CLK_PMV_FAN5_4", - "CLK_PMV_FAN5_5", - "CLK_PMV_FAN5_6", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN6_1", - "CLK_PMV_FAN6_2", - "CLK_PMV_FAN6_3", - "CLK_PMV_FAN6_4", - "CLK_PMV_FAN6_5", - "CLK_PMV_FAN6_6", - "CLK_PMV_FAN7_0", - "CLK_PMV_FAN7_1", - "CLK_PMV_FAN7_2", - "CLK_PMV_FAN7_3", - "CLK_PMV_FAN7_4", - "CLK_PMV_FAN7_5", - "CLK_PMV_FAN7_6", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX0_1", - "CLK_PMV_IMUX0_2", - "CLK_PMV_IMUX0_3", - "CLK_PMV_IMUX0_4", - "CLK_PMV_IMUX0_5", - "CLK_PMV_IMUX0_6", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX10_1", - "CLK_PMV_IMUX10_2", - "CLK_PMV_IMUX10_3", - "CLK_PMV_IMUX10_4", - "CLK_PMV_IMUX10_5", - "CLK_PMV_IMUX10_6", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX11_1", - "CLK_PMV_IMUX11_2", - "CLK_PMV_IMUX11_3", - "CLK_PMV_IMUX11_4", - "CLK_PMV_IMUX11_5", - "CLK_PMV_IMUX11_6", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX12_1", - "CLK_PMV_IMUX12_2", - "CLK_PMV_IMUX12_3", - "CLK_PMV_IMUX12_4", - "CLK_PMV_IMUX12_5", - "CLK_PMV_IMUX12_6", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX13_1", - "CLK_PMV_IMUX13_2", - "CLK_PMV_IMUX13_3", - "CLK_PMV_IMUX13_4", - "CLK_PMV_IMUX13_5", - "CLK_PMV_IMUX13_6", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX14_1", - "CLK_PMV_IMUX14_2", - "CLK_PMV_IMUX14_3", - "CLK_PMV_IMUX14_4", - "CLK_PMV_IMUX14_5", - "CLK_PMV_IMUX14_6", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX15_1", - "CLK_PMV_IMUX15_2", - "CLK_PMV_IMUX15_3", - "CLK_PMV_IMUX15_4", - "CLK_PMV_IMUX15_5", - "CLK_PMV_IMUX15_6", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX16_1", - "CLK_PMV_IMUX16_2", - "CLK_PMV_IMUX16_3", - "CLK_PMV_IMUX16_4", - "CLK_PMV_IMUX16_5", - "CLK_PMV_IMUX16_6", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX17_1", - "CLK_PMV_IMUX17_2", - "CLK_PMV_IMUX17_3", - "CLK_PMV_IMUX17_4", - "CLK_PMV_IMUX17_5", - "CLK_PMV_IMUX17_6", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX18_1", - "CLK_PMV_IMUX18_2", - "CLK_PMV_IMUX18_3", - "CLK_PMV_IMUX18_4", - "CLK_PMV_IMUX18_5", - "CLK_PMV_IMUX18_6", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX19_1", - "CLK_PMV_IMUX19_2", - "CLK_PMV_IMUX19_3", - "CLK_PMV_IMUX19_4", - "CLK_PMV_IMUX19_5", - "CLK_PMV_IMUX19_6", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX1_1", - "CLK_PMV_IMUX1_2", - "CLK_PMV_IMUX1_3", - "CLK_PMV_IMUX1_4", - "CLK_PMV_IMUX1_5", - "CLK_PMV_IMUX1_6", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX20_1", - "CLK_PMV_IMUX20_2", - "CLK_PMV_IMUX20_3", - "CLK_PMV_IMUX20_4", - "CLK_PMV_IMUX20_5", - "CLK_PMV_IMUX20_6", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX21_1", - "CLK_PMV_IMUX21_2", - "CLK_PMV_IMUX21_3", - "CLK_PMV_IMUX21_4", - "CLK_PMV_IMUX21_5", - "CLK_PMV_IMUX21_6", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX22_1", - "CLK_PMV_IMUX22_2", - "CLK_PMV_IMUX22_3", - "CLK_PMV_IMUX22_4", - "CLK_PMV_IMUX22_5", - "CLK_PMV_IMUX22_6", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX23_1", - "CLK_PMV_IMUX23_2", - "CLK_PMV_IMUX23_3", - "CLK_PMV_IMUX23_4", - "CLK_PMV_IMUX23_5", - "CLK_PMV_IMUX23_6", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX24_1", - "CLK_PMV_IMUX24_2", - "CLK_PMV_IMUX24_3", - "CLK_PMV_IMUX24_4", - "CLK_PMV_IMUX24_5", - "CLK_PMV_IMUX24_6", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX25_1", - "CLK_PMV_IMUX25_2", - "CLK_PMV_IMUX25_3", - "CLK_PMV_IMUX25_4", - "CLK_PMV_IMUX25_5", - "CLK_PMV_IMUX25_6", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX26_1", - "CLK_PMV_IMUX26_2", - "CLK_PMV_IMUX26_3", - "CLK_PMV_IMUX26_4", - "CLK_PMV_IMUX26_5", - "CLK_PMV_IMUX26_6", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX27_1", - "CLK_PMV_IMUX27_2", - "CLK_PMV_IMUX27_3", - "CLK_PMV_IMUX27_4", - "CLK_PMV_IMUX27_5", - "CLK_PMV_IMUX27_6", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX28_1", - "CLK_PMV_IMUX28_2", - "CLK_PMV_IMUX28_3", - "CLK_PMV_IMUX28_4", - "CLK_PMV_IMUX28_5", - "CLK_PMV_IMUX28_6", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX29_1", - "CLK_PMV_IMUX29_2", - "CLK_PMV_IMUX29_3", - "CLK_PMV_IMUX29_4", - "CLK_PMV_IMUX29_5", - "CLK_PMV_IMUX29_6", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX2_1", - "CLK_PMV_IMUX2_2", - "CLK_PMV_IMUX2_3", - "CLK_PMV_IMUX2_4", - "CLK_PMV_IMUX2_5", - "CLK_PMV_IMUX2_6", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX30_1", - "CLK_PMV_IMUX30_2", - "CLK_PMV_IMUX30_3", - "CLK_PMV_IMUX30_4", - "CLK_PMV_IMUX30_5", - "CLK_PMV_IMUX30_6", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX31_1", - "CLK_PMV_IMUX31_2", - "CLK_PMV_IMUX31_3", - "CLK_PMV_IMUX31_4", - "CLK_PMV_IMUX31_5", - "CLK_PMV_IMUX31_6", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX32_1", - "CLK_PMV_IMUX32_2", - "CLK_PMV_IMUX32_3", - "CLK_PMV_IMUX32_4", - "CLK_PMV_IMUX32_5", - "CLK_PMV_IMUX32_6", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX33_1", - "CLK_PMV_IMUX33_2", - "CLK_PMV_IMUX33_3", - "CLK_PMV_IMUX33_4", - "CLK_PMV_IMUX33_5", - "CLK_PMV_IMUX33_6", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX34_1", - "CLK_PMV_IMUX34_2", - "CLK_PMV_IMUX34_3", - "CLK_PMV_IMUX34_4", - "CLK_PMV_IMUX34_5", - "CLK_PMV_IMUX34_6", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX35_1", - "CLK_PMV_IMUX35_2", - "CLK_PMV_IMUX35_3", - "CLK_PMV_IMUX35_4", - "CLK_PMV_IMUX35_5", - "CLK_PMV_IMUX35_6", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX36_1", - "CLK_PMV_IMUX36_2", - "CLK_PMV_IMUX36_3", - "CLK_PMV_IMUX36_4", - "CLK_PMV_IMUX36_5", - "CLK_PMV_IMUX36_6", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX37_1", - "CLK_PMV_IMUX37_2", - "CLK_PMV_IMUX37_3", - "CLK_PMV_IMUX37_4", - "CLK_PMV_IMUX37_5", - "CLK_PMV_IMUX37_6", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX38_1", - "CLK_PMV_IMUX38_2", - "CLK_PMV_IMUX38_3", - "CLK_PMV_IMUX38_4", - "CLK_PMV_IMUX38_5", - "CLK_PMV_IMUX38_6", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX39_1", - "CLK_PMV_IMUX39_2", - "CLK_PMV_IMUX39_3", - "CLK_PMV_IMUX39_4", - "CLK_PMV_IMUX39_5", - "CLK_PMV_IMUX39_6", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX3_1", - "CLK_PMV_IMUX3_2", - "CLK_PMV_IMUX3_3", - "CLK_PMV_IMUX3_4", - "CLK_PMV_IMUX3_5", - "CLK_PMV_IMUX3_6", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX40_1", - "CLK_PMV_IMUX40_2", - "CLK_PMV_IMUX40_3", - "CLK_PMV_IMUX40_4", - "CLK_PMV_IMUX40_5", - "CLK_PMV_IMUX40_6", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX41_1", - "CLK_PMV_IMUX41_2", - "CLK_PMV_IMUX41_3", - "CLK_PMV_IMUX41_4", - "CLK_PMV_IMUX41_5", - "CLK_PMV_IMUX41_6", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX42_1", - "CLK_PMV_IMUX42_2", - "CLK_PMV_IMUX42_3", - "CLK_PMV_IMUX42_4", - "CLK_PMV_IMUX42_5", - "CLK_PMV_IMUX42_6", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX43_1", - "CLK_PMV_IMUX43_2", - "CLK_PMV_IMUX43_3", - "CLK_PMV_IMUX43_4", - "CLK_PMV_IMUX43_5", - "CLK_PMV_IMUX43_6", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX44_1", - "CLK_PMV_IMUX44_2", - "CLK_PMV_IMUX44_3", - "CLK_PMV_IMUX44_4", - "CLK_PMV_IMUX44_5", - "CLK_PMV_IMUX44_6", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX45_1", - "CLK_PMV_IMUX45_2", - "CLK_PMV_IMUX45_3", - "CLK_PMV_IMUX45_4", - "CLK_PMV_IMUX45_5", - "CLK_PMV_IMUX45_6", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX46_1", - "CLK_PMV_IMUX46_2", - "CLK_PMV_IMUX46_3", - "CLK_PMV_IMUX46_4", - "CLK_PMV_IMUX46_5", - "CLK_PMV_IMUX46_6", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX47_1", - "CLK_PMV_IMUX47_2", - "CLK_PMV_IMUX47_3", - "CLK_PMV_IMUX47_4", - "CLK_PMV_IMUX47_5", - "CLK_PMV_IMUX47_6", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX4_1", - "CLK_PMV_IMUX4_2", - "CLK_PMV_IMUX4_3", - "CLK_PMV_IMUX4_4", - "CLK_PMV_IMUX4_5", - "CLK_PMV_IMUX4_6", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX5_1", - "CLK_PMV_IMUX5_2", - "CLK_PMV_IMUX5_3", - "CLK_PMV_IMUX5_4", - "CLK_PMV_IMUX5_5", - "CLK_PMV_IMUX5_6", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX6_1", - "CLK_PMV_IMUX6_2", - "CLK_PMV_IMUX6_3", - "CLK_PMV_IMUX6_4", - "CLK_PMV_IMUX6_5", - "CLK_PMV_IMUX6_6", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX7_1", - "CLK_PMV_IMUX7_2", - "CLK_PMV_IMUX7_3", - "CLK_PMV_IMUX7_4", - "CLK_PMV_IMUX7_5", - "CLK_PMV_IMUX7_6", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX8_1", - "CLK_PMV_IMUX8_2", - "CLK_PMV_IMUX8_3", - "CLK_PMV_IMUX8_4", - "CLK_PMV_IMUX8_5", - "CLK_PMV_IMUX8_6", - "CLK_PMV_IMUX9_0", - "CLK_PMV_IMUX9_1", - "CLK_PMV_IMUX9_2", - "CLK_PMV_IMUX9_3", - "CLK_PMV_IMUX9_4", - "CLK_PMV_IMUX9_5", - "CLK_PMV_IMUX9_6", - "CLK_PMV_LH10_0", - "CLK_PMV_LH10_1", - "CLK_PMV_LH10_2", - "CLK_PMV_LH10_3", - "CLK_PMV_LH10_4", - "CLK_PMV_LH10_5", - "CLK_PMV_LH10_6", - "CLK_PMV_LH11_0", - "CLK_PMV_LH11_1", - "CLK_PMV_LH11_2", - "CLK_PMV_LH11_3", - "CLK_PMV_LH11_4", - "CLK_PMV_LH11_5", - "CLK_PMV_LH11_6", - "CLK_PMV_LH12_0", - "CLK_PMV_LH12_1", - "CLK_PMV_LH12_2", - "CLK_PMV_LH12_3", - "CLK_PMV_LH12_4", - "CLK_PMV_LH12_5", - "CLK_PMV_LH12_6", - "CLK_PMV_LH1_0", - "CLK_PMV_LH1_1", - "CLK_PMV_LH1_2", - "CLK_PMV_LH1_3", - "CLK_PMV_LH1_4", - "CLK_PMV_LH1_5", - "CLK_PMV_LH1_6", - "CLK_PMV_LH2_0", - "CLK_PMV_LH2_1", - "CLK_PMV_LH2_2", - "CLK_PMV_LH2_3", - "CLK_PMV_LH2_4", - "CLK_PMV_LH2_5", - "CLK_PMV_LH2_6", - "CLK_PMV_LH3_0", - "CLK_PMV_LH3_1", - "CLK_PMV_LH3_2", - "CLK_PMV_LH3_3", - "CLK_PMV_LH3_4", - "CLK_PMV_LH3_5", - "CLK_PMV_LH3_6", - "CLK_PMV_LH4_0", - "CLK_PMV_LH4_1", - "CLK_PMV_LH4_2", - "CLK_PMV_LH4_3", - "CLK_PMV_LH4_4", - "CLK_PMV_LH4_5", - "CLK_PMV_LH4_6", - "CLK_PMV_LH5_0", - "CLK_PMV_LH5_1", - "CLK_PMV_LH5_2", - "CLK_PMV_LH5_3", - "CLK_PMV_LH5_4", - "CLK_PMV_LH5_5", - "CLK_PMV_LH5_6", - "CLK_PMV_LH6_0", - "CLK_PMV_LH6_1", - "CLK_PMV_LH6_2", - "CLK_PMV_LH6_3", - "CLK_PMV_LH6_4", - "CLK_PMV_LH6_5", - "CLK_PMV_LH6_6", - "CLK_PMV_LH7_0", - "CLK_PMV_LH7_1", - "CLK_PMV_LH7_2", - "CLK_PMV_LH7_3", - "CLK_PMV_LH7_4", - "CLK_PMV_LH7_5", - "CLK_PMV_LH7_6", - "CLK_PMV_LH8_0", - "CLK_PMV_LH8_1", - "CLK_PMV_LH8_2", - "CLK_PMV_LH8_3", - "CLK_PMV_LH8_4", - "CLK_PMV_LH8_5", - "CLK_PMV_LH8_6", - "CLK_PMV_LH9_0", - "CLK_PMV_LH9_1", - "CLK_PMV_LH9_2", - "CLK_PMV_LH9_3", - "CLK_PMV_LH9_4", - "CLK_PMV_LH9_5", - "CLK_PMV_LH9_6", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS0_1", - "CLK_PMV_LOGIC_OUTS0_2", - "CLK_PMV_LOGIC_OUTS0_3", - "CLK_PMV_LOGIC_OUTS0_4", - "CLK_PMV_LOGIC_OUTS0_5", - "CLK_PMV_LOGIC_OUTS0_6", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS10_1", - "CLK_PMV_LOGIC_OUTS10_2", - "CLK_PMV_LOGIC_OUTS10_3", - "CLK_PMV_LOGIC_OUTS10_4", - "CLK_PMV_LOGIC_OUTS10_5", - "CLK_PMV_LOGIC_OUTS10_6", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS11_1", - "CLK_PMV_LOGIC_OUTS11_2", - "CLK_PMV_LOGIC_OUTS11_3", - "CLK_PMV_LOGIC_OUTS11_4", - "CLK_PMV_LOGIC_OUTS11_5", - "CLK_PMV_LOGIC_OUTS11_6", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS12_1", - "CLK_PMV_LOGIC_OUTS12_2", - "CLK_PMV_LOGIC_OUTS12_3", - "CLK_PMV_LOGIC_OUTS12_4", - "CLK_PMV_LOGIC_OUTS12_5", - "CLK_PMV_LOGIC_OUTS12_6", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS13_1", - "CLK_PMV_LOGIC_OUTS13_2", - "CLK_PMV_LOGIC_OUTS13_3", - "CLK_PMV_LOGIC_OUTS13_4", - "CLK_PMV_LOGIC_OUTS13_5", - "CLK_PMV_LOGIC_OUTS13_6", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS14_1", - "CLK_PMV_LOGIC_OUTS14_2", - "CLK_PMV_LOGIC_OUTS14_3", - "CLK_PMV_LOGIC_OUTS14_4", - "CLK_PMV_LOGIC_OUTS14_5", - "CLK_PMV_LOGIC_OUTS14_6", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS15_1", - "CLK_PMV_LOGIC_OUTS15_2", - "CLK_PMV_LOGIC_OUTS15_3", - "CLK_PMV_LOGIC_OUTS15_4", - "CLK_PMV_LOGIC_OUTS15_5", - "CLK_PMV_LOGIC_OUTS15_6", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS16_1", - "CLK_PMV_LOGIC_OUTS16_2", - "CLK_PMV_LOGIC_OUTS16_3", - "CLK_PMV_LOGIC_OUTS16_4", - "CLK_PMV_LOGIC_OUTS16_5", - "CLK_PMV_LOGIC_OUTS16_6", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS17_1", - "CLK_PMV_LOGIC_OUTS17_2", - "CLK_PMV_LOGIC_OUTS17_3", - "CLK_PMV_LOGIC_OUTS17_4", - "CLK_PMV_LOGIC_OUTS17_5", - "CLK_PMV_LOGIC_OUTS17_6", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS18_1", - "CLK_PMV_LOGIC_OUTS18_2", - "CLK_PMV_LOGIC_OUTS18_3", - "CLK_PMV_LOGIC_OUTS18_4", - "CLK_PMV_LOGIC_OUTS18_5", - "CLK_PMV_LOGIC_OUTS18_6", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS19_1", - "CLK_PMV_LOGIC_OUTS19_2", - "CLK_PMV_LOGIC_OUTS19_3", - "CLK_PMV_LOGIC_OUTS19_4", - "CLK_PMV_LOGIC_OUTS19_5", - "CLK_PMV_LOGIC_OUTS19_6", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS1_1", - "CLK_PMV_LOGIC_OUTS1_2", - "CLK_PMV_LOGIC_OUTS1_3", - "CLK_PMV_LOGIC_OUTS1_4", - "CLK_PMV_LOGIC_OUTS1_5", - "CLK_PMV_LOGIC_OUTS1_6", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS20_1", - "CLK_PMV_LOGIC_OUTS20_2", - "CLK_PMV_LOGIC_OUTS20_3", - "CLK_PMV_LOGIC_OUTS20_4", - "CLK_PMV_LOGIC_OUTS20_5", - "CLK_PMV_LOGIC_OUTS20_6", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS21_1", - "CLK_PMV_LOGIC_OUTS21_2", - "CLK_PMV_LOGIC_OUTS21_3", - "CLK_PMV_LOGIC_OUTS21_4", - "CLK_PMV_LOGIC_OUTS21_5", - "CLK_PMV_LOGIC_OUTS21_6", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS22_1", - "CLK_PMV_LOGIC_OUTS22_2", - "CLK_PMV_LOGIC_OUTS22_3", - "CLK_PMV_LOGIC_OUTS22_4", - "CLK_PMV_LOGIC_OUTS22_5", - "CLK_PMV_LOGIC_OUTS22_6", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS23_1", - "CLK_PMV_LOGIC_OUTS23_2", - "CLK_PMV_LOGIC_OUTS23_3", - "CLK_PMV_LOGIC_OUTS23_4", - "CLK_PMV_LOGIC_OUTS23_5", - "CLK_PMV_LOGIC_OUTS23_6", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS2_1", - "CLK_PMV_LOGIC_OUTS2_2", - "CLK_PMV_LOGIC_OUTS2_3", - "CLK_PMV_LOGIC_OUTS2_4", - "CLK_PMV_LOGIC_OUTS2_5", - "CLK_PMV_LOGIC_OUTS2_6", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS3_1", - "CLK_PMV_LOGIC_OUTS3_2", - "CLK_PMV_LOGIC_OUTS3_3", - "CLK_PMV_LOGIC_OUTS3_4", - "CLK_PMV_LOGIC_OUTS3_5", - "CLK_PMV_LOGIC_OUTS3_6", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS4_1", - "CLK_PMV_LOGIC_OUTS4_2", - "CLK_PMV_LOGIC_OUTS4_3", - "CLK_PMV_LOGIC_OUTS4_4", - "CLK_PMV_LOGIC_OUTS4_5", - "CLK_PMV_LOGIC_OUTS4_6", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS5_1", - "CLK_PMV_LOGIC_OUTS5_2", - "CLK_PMV_LOGIC_OUTS5_3", - "CLK_PMV_LOGIC_OUTS5_4", - "CLK_PMV_LOGIC_OUTS5_5", - "CLK_PMV_LOGIC_OUTS5_6", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS6_1", - "CLK_PMV_LOGIC_OUTS6_2", - "CLK_PMV_LOGIC_OUTS6_3", - "CLK_PMV_LOGIC_OUTS6_4", - "CLK_PMV_LOGIC_OUTS6_5", - "CLK_PMV_LOGIC_OUTS6_6", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS7_1", - "CLK_PMV_LOGIC_OUTS7_2", - "CLK_PMV_LOGIC_OUTS7_3", - "CLK_PMV_LOGIC_OUTS7_4", - "CLK_PMV_LOGIC_OUTS7_5", - "CLK_PMV_LOGIC_OUTS7_6", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS8_1", - "CLK_PMV_LOGIC_OUTS8_2", - "CLK_PMV_LOGIC_OUTS8_3", - "CLK_PMV_LOGIC_OUTS8_4", - "CLK_PMV_LOGIC_OUTS8_5", - "CLK_PMV_LOGIC_OUTS8_6", - "CLK_PMV_LOGIC_OUTS9_0", - "CLK_PMV_LOGIC_OUTS9_1", - "CLK_PMV_LOGIC_OUTS9_2", - "CLK_PMV_LOGIC_OUTS9_3", - "CLK_PMV_LOGIC_OUTS9_4", - "CLK_PMV_LOGIC_OUTS9_5", - "CLK_PMV_LOGIC_OUTS9_6", - "CLK_PMV_MONITOR_N_0", - "CLK_PMV_MONITOR_N_1", - "CLK_PMV_MONITOR_N_2", - "CLK_PMV_MONITOR_N_3", - "CLK_PMV_MONITOR_N_4", - "CLK_PMV_MONITOR_N_5", - "CLK_PMV_MONITOR_N_6", - "CLK_PMV_MONITOR_P_0", - "CLK_PMV_MONITOR_P_1", - "CLK_PMV_MONITOR_P_2", - "CLK_PMV_MONITOR_P_3", - "CLK_PMV_MONITOR_P_4", - "CLK_PMV_MONITOR_P_5", - "CLK_PMV_MONITOR_P_6", - "CLK_PMV_NE2A0_0", - "CLK_PMV_NE2A0_1", - "CLK_PMV_NE2A0_2", - "CLK_PMV_NE2A0_3", - "CLK_PMV_NE2A0_4", - "CLK_PMV_NE2A0_5", - "CLK_PMV_NE2A0_6", - "CLK_PMV_NE2A1_0", - "CLK_PMV_NE2A1_1", - "CLK_PMV_NE2A1_2", - "CLK_PMV_NE2A1_3", - "CLK_PMV_NE2A1_4", - "CLK_PMV_NE2A1_5", - "CLK_PMV_NE2A1_6", - "CLK_PMV_NE2A2_0", - "CLK_PMV_NE2A2_1", - "CLK_PMV_NE2A2_2", - "CLK_PMV_NE2A2_3", - "CLK_PMV_NE2A2_4", - "CLK_PMV_NE2A2_5", - "CLK_PMV_NE2A2_6", - "CLK_PMV_NE2A3_0", - "CLK_PMV_NE2A3_1", - "CLK_PMV_NE2A3_2", - "CLK_PMV_NE2A3_3", - "CLK_PMV_NE2A3_4", - "CLK_PMV_NE2A3_5", - "CLK_PMV_NE2A3_6", - "CLK_PMV_NE4BEG0_0", - "CLK_PMV_NE4BEG0_1", - "CLK_PMV_NE4BEG0_2", - "CLK_PMV_NE4BEG0_3", - "CLK_PMV_NE4BEG0_4", - "CLK_PMV_NE4BEG0_5", - "CLK_PMV_NE4BEG0_6", - "CLK_PMV_NE4BEG1_0", - "CLK_PMV_NE4BEG1_1", - "CLK_PMV_NE4BEG1_2", - "CLK_PMV_NE4BEG1_3", - "CLK_PMV_NE4BEG1_4", - "CLK_PMV_NE4BEG1_5", - "CLK_PMV_NE4BEG1_6", - "CLK_PMV_NE4BEG2_0", - "CLK_PMV_NE4BEG2_1", - "CLK_PMV_NE4BEG2_2", - "CLK_PMV_NE4BEG2_3", - "CLK_PMV_NE4BEG2_4", - "CLK_PMV_NE4BEG2_5", - "CLK_PMV_NE4BEG2_6", - "CLK_PMV_NE4BEG3_0", - "CLK_PMV_NE4BEG3_1", - "CLK_PMV_NE4BEG3_2", - "CLK_PMV_NE4BEG3_3", - "CLK_PMV_NE4BEG3_4", - "CLK_PMV_NE4BEG3_5", - "CLK_PMV_NE4BEG3_6", - "CLK_PMV_NE4C0_0", - "CLK_PMV_NE4C0_1", - "CLK_PMV_NE4C0_2", - "CLK_PMV_NE4C0_3", - "CLK_PMV_NE4C0_4", - "CLK_PMV_NE4C0_5", - "CLK_PMV_NE4C0_6", - "CLK_PMV_NE4C1_0", - "CLK_PMV_NE4C1_1", - "CLK_PMV_NE4C1_2", - "CLK_PMV_NE4C1_3", - "CLK_PMV_NE4C1_4", - "CLK_PMV_NE4C1_5", - "CLK_PMV_NE4C1_6", - "CLK_PMV_NE4C2_0", - "CLK_PMV_NE4C2_1", - "CLK_PMV_NE4C2_2", - "CLK_PMV_NE4C2_3", - "CLK_PMV_NE4C2_4", - "CLK_PMV_NE4C2_5", - "CLK_PMV_NE4C2_6", - "CLK_PMV_NE4C3_0", - "CLK_PMV_NE4C3_1", - "CLK_PMV_NE4C3_2", - "CLK_PMV_NE4C3_3", - "CLK_PMV_NE4C3_4", - "CLK_PMV_NE4C3_5", - "CLK_PMV_NE4C3_6", - "CLK_PMV_NW2A0_0", - "CLK_PMV_NW2A0_1", - "CLK_PMV_NW2A0_2", - "CLK_PMV_NW2A0_3", - "CLK_PMV_NW2A0_4", - "CLK_PMV_NW2A0_5", - "CLK_PMV_NW2A0_6", - "CLK_PMV_NW2A1_0", - "CLK_PMV_NW2A1_1", - "CLK_PMV_NW2A1_2", - "CLK_PMV_NW2A1_3", - "CLK_PMV_NW2A1_4", - "CLK_PMV_NW2A1_5", - "CLK_PMV_NW2A1_6", - "CLK_PMV_NW2A2_0", - "CLK_PMV_NW2A2_1", - "CLK_PMV_NW2A2_2", - "CLK_PMV_NW2A2_3", - "CLK_PMV_NW2A2_4", - "CLK_PMV_NW2A2_5", - "CLK_PMV_NW2A2_6", - "CLK_PMV_NW2A3_0", - "CLK_PMV_NW2A3_1", - "CLK_PMV_NW2A3_2", - "CLK_PMV_NW2A3_3", - "CLK_PMV_NW2A3_4", - "CLK_PMV_NW2A3_5", - "CLK_PMV_NW2A3_6", - "CLK_PMV_NW4A0_0", - "CLK_PMV_NW4A0_1", - "CLK_PMV_NW4A0_2", - "CLK_PMV_NW4A0_3", - "CLK_PMV_NW4A0_4", - "CLK_PMV_NW4A0_5", - "CLK_PMV_NW4A0_6", - "CLK_PMV_NW4A1_0", - "CLK_PMV_NW4A1_1", - "CLK_PMV_NW4A1_2", - "CLK_PMV_NW4A1_3", - "CLK_PMV_NW4A1_4", - "CLK_PMV_NW4A1_5", - "CLK_PMV_NW4A1_6", - "CLK_PMV_NW4A2_0", - "CLK_PMV_NW4A2_1", - "CLK_PMV_NW4A2_2", - "CLK_PMV_NW4A2_3", - "CLK_PMV_NW4A2_4", - "CLK_PMV_NW4A2_5", - "CLK_PMV_NW4A2_6", - "CLK_PMV_NW4A3_0", - "CLK_PMV_NW4A3_1", - "CLK_PMV_NW4A3_2", - "CLK_PMV_NW4A3_3", - "CLK_PMV_NW4A3_4", - "CLK_PMV_NW4A3_5", - "CLK_PMV_NW4A3_6", - "CLK_PMV_NW4END0_0", - "CLK_PMV_NW4END0_1", - "CLK_PMV_NW4END0_2", - "CLK_PMV_NW4END0_3", - "CLK_PMV_NW4END0_4", - "CLK_PMV_NW4END0_5", - "CLK_PMV_NW4END0_6", - "CLK_PMV_NW4END1_0", - "CLK_PMV_NW4END1_1", - "CLK_PMV_NW4END1_2", - "CLK_PMV_NW4END1_3", - "CLK_PMV_NW4END1_4", - "CLK_PMV_NW4END1_5", - "CLK_PMV_NW4END1_6", - "CLK_PMV_NW4END2_0", - "CLK_PMV_NW4END2_1", - "CLK_PMV_NW4END2_2", - "CLK_PMV_NW4END2_3", - "CLK_PMV_NW4END2_4", - "CLK_PMV_NW4END2_5", - "CLK_PMV_NW4END2_6", - "CLK_PMV_NW4END3_0", - "CLK_PMV_NW4END3_1", - "CLK_PMV_NW4END3_2", - "CLK_PMV_NW4END3_3", - "CLK_PMV_NW4END3_4", - "CLK_PMV_NW4END3_5", - "CLK_PMV_NW4END3_6", - "CLK_PMV_O", - "CLK_PMV_ODIV2", - "CLK_PMV_ODIV4", - "CLK_PMV_R_CK_BUFG_CASC0", - "CLK_PMV_R_CK_BUFG_CASC1", - "CLK_PMV_R_CK_BUFG_CASC10", - "CLK_PMV_R_CK_BUFG_CASC11", - "CLK_PMV_R_CK_BUFG_CASC12", - "CLK_PMV_R_CK_BUFG_CASC13", - "CLK_PMV_R_CK_BUFG_CASC14", - "CLK_PMV_R_CK_BUFG_CASC15", - "CLK_PMV_R_CK_BUFG_CASC16", - "CLK_PMV_R_CK_BUFG_CASC17", - "CLK_PMV_R_CK_BUFG_CASC18", - "CLK_PMV_R_CK_BUFG_CASC19", - "CLK_PMV_R_CK_BUFG_CASC2", - "CLK_PMV_R_CK_BUFG_CASC20", - "CLK_PMV_R_CK_BUFG_CASC21", - "CLK_PMV_R_CK_BUFG_CASC22", - "CLK_PMV_R_CK_BUFG_CASC23", - "CLK_PMV_R_CK_BUFG_CASC24", - "CLK_PMV_R_CK_BUFG_CASC25", - "CLK_PMV_R_CK_BUFG_CASC26", - "CLK_PMV_R_CK_BUFG_CASC27", - "CLK_PMV_R_CK_BUFG_CASC28", - "CLK_PMV_R_CK_BUFG_CASC29", - "CLK_PMV_R_CK_BUFG_CASC3", - "CLK_PMV_R_CK_BUFG_CASC30", - "CLK_PMV_R_CK_BUFG_CASC31", - "CLK_PMV_R_CK_BUFG_CASC4", - "CLK_PMV_R_CK_BUFG_CASC5", - "CLK_PMV_R_CK_BUFG_CASC6", - "CLK_PMV_R_CK_BUFG_CASC7", - "CLK_PMV_R_CK_BUFG_CASC8", - "CLK_PMV_R_CK_BUFG_CASC9", - "CLK_PMV_R_CK_GCLK0", - "CLK_PMV_R_CK_GCLK1", - "CLK_PMV_R_CK_GCLK10", - "CLK_PMV_R_CK_GCLK11", - "CLK_PMV_R_CK_GCLK12", - "CLK_PMV_R_CK_GCLK13", - "CLK_PMV_R_CK_GCLK14", - "CLK_PMV_R_CK_GCLK15", - "CLK_PMV_R_CK_GCLK16", - "CLK_PMV_R_CK_GCLK17", - "CLK_PMV_R_CK_GCLK18", - "CLK_PMV_R_CK_GCLK19", - "CLK_PMV_R_CK_GCLK2", - "CLK_PMV_R_CK_GCLK20", - "CLK_PMV_R_CK_GCLK21", - "CLK_PMV_R_CK_GCLK22", - "CLK_PMV_R_CK_GCLK23", - "CLK_PMV_R_CK_GCLK24", - "CLK_PMV_R_CK_GCLK25", - "CLK_PMV_R_CK_GCLK26", - "CLK_PMV_R_CK_GCLK27", - "CLK_PMV_R_CK_GCLK28", - "CLK_PMV_R_CK_GCLK29", - "CLK_PMV_R_CK_GCLK3", - "CLK_PMV_R_CK_GCLK30", - "CLK_PMV_R_CK_GCLK31", - "CLK_PMV_R_CK_GCLK4", - "CLK_PMV_R_CK_GCLK5", - "CLK_PMV_R_CK_GCLK6", - "CLK_PMV_R_CK_GCLK7", - "CLK_PMV_R_CK_GCLK8", - "CLK_PMV_R_CK_GCLK9", - "CLK_PMV_SE2A0_0", - "CLK_PMV_SE2A0_1", - "CLK_PMV_SE2A0_2", - "CLK_PMV_SE2A0_3", - "CLK_PMV_SE2A0_4", - "CLK_PMV_SE2A0_5", - "CLK_PMV_SE2A0_6", - "CLK_PMV_SE2A1_0", - "CLK_PMV_SE2A1_1", - "CLK_PMV_SE2A1_2", - "CLK_PMV_SE2A1_3", - "CLK_PMV_SE2A1_4", - "CLK_PMV_SE2A1_5", - "CLK_PMV_SE2A1_6", - "CLK_PMV_SE2A2_0", - "CLK_PMV_SE2A2_1", - "CLK_PMV_SE2A2_2", - "CLK_PMV_SE2A2_3", - "CLK_PMV_SE2A2_4", - "CLK_PMV_SE2A2_5", - "CLK_PMV_SE2A2_6", - "CLK_PMV_SE2A3_0", - "CLK_PMV_SE2A3_1", - "CLK_PMV_SE2A3_2", - "CLK_PMV_SE2A3_3", - "CLK_PMV_SE2A3_4", - "CLK_PMV_SE2A3_5", - "CLK_PMV_SE2A3_6", - "CLK_PMV_SE4BEG0_0", - "CLK_PMV_SE4BEG0_1", - "CLK_PMV_SE4BEG0_2", - "CLK_PMV_SE4BEG0_3", - "CLK_PMV_SE4BEG0_4", - "CLK_PMV_SE4BEG0_5", - "CLK_PMV_SE4BEG0_6", - "CLK_PMV_SE4BEG1_0", - "CLK_PMV_SE4BEG1_1", - "CLK_PMV_SE4BEG1_2", - "CLK_PMV_SE4BEG1_3", - "CLK_PMV_SE4BEG1_4", - "CLK_PMV_SE4BEG1_5", - "CLK_PMV_SE4BEG1_6", - "CLK_PMV_SE4BEG2_0", - "CLK_PMV_SE4BEG2_1", - "CLK_PMV_SE4BEG2_2", - "CLK_PMV_SE4BEG2_3", - "CLK_PMV_SE4BEG2_4", - "CLK_PMV_SE4BEG2_5", - "CLK_PMV_SE4BEG2_6", - "CLK_PMV_SE4BEG3_0", - "CLK_PMV_SE4BEG3_1", - "CLK_PMV_SE4BEG3_2", - "CLK_PMV_SE4BEG3_3", - "CLK_PMV_SE4BEG3_4", - "CLK_PMV_SE4BEG3_5", - "CLK_PMV_SE4BEG3_6", - "CLK_PMV_SE4C0_0", - "CLK_PMV_SE4C0_1", - "CLK_PMV_SE4C0_2", - "CLK_PMV_SE4C0_3", - "CLK_PMV_SE4C0_4", - "CLK_PMV_SE4C0_5", - "CLK_PMV_SE4C0_6", - "CLK_PMV_SE4C1_0", - "CLK_PMV_SE4C1_1", - "CLK_PMV_SE4C1_2", - "CLK_PMV_SE4C1_3", - "CLK_PMV_SE4C1_4", - "CLK_PMV_SE4C1_5", - "CLK_PMV_SE4C1_6", - "CLK_PMV_SE4C2_0", - "CLK_PMV_SE4C2_1", - "CLK_PMV_SE4C2_2", - "CLK_PMV_SE4C2_3", - "CLK_PMV_SE4C2_4", - "CLK_PMV_SE4C2_5", - "CLK_PMV_SE4C2_6", - "CLK_PMV_SE4C3_0", - "CLK_PMV_SE4C3_1", - "CLK_PMV_SE4C3_2", - "CLK_PMV_SE4C3_3", - "CLK_PMV_SE4C3_4", - "CLK_PMV_SE4C3_5", - "CLK_PMV_SE4C3_6", - "CLK_PMV_SW2A0_0", - "CLK_PMV_SW2A0_1", - "CLK_PMV_SW2A0_2", - "CLK_PMV_SW2A0_3", - "CLK_PMV_SW2A0_4", - "CLK_PMV_SW2A0_5", - "CLK_PMV_SW2A0_6", - "CLK_PMV_SW2A1_0", - "CLK_PMV_SW2A1_1", - "CLK_PMV_SW2A1_2", - "CLK_PMV_SW2A1_3", - "CLK_PMV_SW2A1_4", - "CLK_PMV_SW2A1_5", - "CLK_PMV_SW2A1_6", - "CLK_PMV_SW2A2_0", - "CLK_PMV_SW2A2_1", - "CLK_PMV_SW2A2_2", - "CLK_PMV_SW2A2_3", - "CLK_PMV_SW2A2_4", - "CLK_PMV_SW2A2_5", - "CLK_PMV_SW2A2_6", - "CLK_PMV_SW2A3_0", - "CLK_PMV_SW2A3_1", - "CLK_PMV_SW2A3_2", - "CLK_PMV_SW2A3_3", - "CLK_PMV_SW2A3_4", - "CLK_PMV_SW2A3_5", - "CLK_PMV_SW2A3_6", - "CLK_PMV_SW4A0_0", - "CLK_PMV_SW4A0_1", - "CLK_PMV_SW4A0_2", - "CLK_PMV_SW4A0_3", - "CLK_PMV_SW4A0_4", - "CLK_PMV_SW4A0_5", - "CLK_PMV_SW4A0_6", - "CLK_PMV_SW4A1_0", - "CLK_PMV_SW4A1_1", - "CLK_PMV_SW4A1_2", - "CLK_PMV_SW4A1_3", - "CLK_PMV_SW4A1_4", - "CLK_PMV_SW4A1_5", - "CLK_PMV_SW4A1_6", - "CLK_PMV_SW4A2_0", - "CLK_PMV_SW4A2_1", - "CLK_PMV_SW4A2_2", - "CLK_PMV_SW4A2_3", - "CLK_PMV_SW4A2_4", - "CLK_PMV_SW4A2_5", - "CLK_PMV_SW4A2_6", - "CLK_PMV_SW4A3_0", - "CLK_PMV_SW4A3_1", - "CLK_PMV_SW4A3_2", - "CLK_PMV_SW4A3_3", - "CLK_PMV_SW4A3_4", - "CLK_PMV_SW4A3_5", - "CLK_PMV_SW4A3_6", - "CLK_PMV_SW4END0_0", - "CLK_PMV_SW4END0_1", - "CLK_PMV_SW4END0_2", - "CLK_PMV_SW4END0_3", - "CLK_PMV_SW4END0_4", - "CLK_PMV_SW4END0_5", - "CLK_PMV_SW4END0_6", - "CLK_PMV_SW4END1_0", - "CLK_PMV_SW4END1_1", - "CLK_PMV_SW4END1_2", - "CLK_PMV_SW4END1_3", - "CLK_PMV_SW4END1_4", - "CLK_PMV_SW4END1_5", - "CLK_PMV_SW4END1_6", - "CLK_PMV_SW4END2_0", - "CLK_PMV_SW4END2_1", - "CLK_PMV_SW4END2_2", - "CLK_PMV_SW4END2_3", - "CLK_PMV_SW4END2_4", - "CLK_PMV_SW4END2_5", - "CLK_PMV_SW4END2_6", - "CLK_PMV_SW4END3_0", - "CLK_PMV_SW4END3_1", - "CLK_PMV_SW4END3_2", - "CLK_PMV_SW4END3_3", - "CLK_PMV_SW4END3_4", - "CLK_PMV_SW4END3_5", - "CLK_PMV_SW4END3_6", - "CLK_PMV_WL1END0_0", - "CLK_PMV_WL1END0_1", - "CLK_PMV_WL1END0_2", - "CLK_PMV_WL1END0_3", - "CLK_PMV_WL1END0_4", - "CLK_PMV_WL1END0_5", - "CLK_PMV_WL1END0_6", - "CLK_PMV_WL1END1_0", - "CLK_PMV_WL1END1_1", - "CLK_PMV_WL1END1_2", - "CLK_PMV_WL1END1_3", - "CLK_PMV_WL1END1_4", - "CLK_PMV_WL1END1_5", - "CLK_PMV_WL1END1_6", - "CLK_PMV_WL1END2_0", - "CLK_PMV_WL1END2_1", - "CLK_PMV_WL1END2_2", - "CLK_PMV_WL1END2_3", - "CLK_PMV_WL1END2_4", - "CLK_PMV_WL1END2_5", - "CLK_PMV_WL1END2_6", - "CLK_PMV_WL1END3_0", - "CLK_PMV_WL1END3_1", - "CLK_PMV_WL1END3_2", - "CLK_PMV_WL1END3_3", - "CLK_PMV_WL1END3_4", - "CLK_PMV_WL1END3_5", - "CLK_PMV_WL1END3_6", - "CLK_PMV_WR1END0_0", - "CLK_PMV_WR1END0_1", - "CLK_PMV_WR1END0_2", - "CLK_PMV_WR1END0_3", - "CLK_PMV_WR1END0_4", - "CLK_PMV_WR1END0_5", - "CLK_PMV_WR1END0_6", - "CLK_PMV_WR1END1_0", - "CLK_PMV_WR1END1_1", - "CLK_PMV_WR1END1_2", - "CLK_PMV_WR1END1_3", - "CLK_PMV_WR1END1_4", - "CLK_PMV_WR1END1_5", - "CLK_PMV_WR1END1_6", - "CLK_PMV_WR1END2_0", - "CLK_PMV_WR1END2_1", - "CLK_PMV_WR1END2_2", - "CLK_PMV_WR1END2_3", - "CLK_PMV_WR1END2_4", - "CLK_PMV_WR1END2_5", - "CLK_PMV_WR1END2_6", - "CLK_PMV_WR1END3_0", - "CLK_PMV_WR1END3_1", - "CLK_PMV_WR1END3_2", - "CLK_PMV_WR1END3_3", - "CLK_PMV_WR1END3_4", - "CLK_PMV_WR1END3_5", - "CLK_PMV_WR1END3_6", - "CLK_PMV_WW2A0_0", - "CLK_PMV_WW2A0_1", - "CLK_PMV_WW2A0_2", - "CLK_PMV_WW2A0_3", - "CLK_PMV_WW2A0_4", - "CLK_PMV_WW2A0_5", - "CLK_PMV_WW2A0_6", - "CLK_PMV_WW2A1_0", - "CLK_PMV_WW2A1_1", - "CLK_PMV_WW2A1_2", - "CLK_PMV_WW2A1_3", - "CLK_PMV_WW2A1_4", - "CLK_PMV_WW2A1_5", - "CLK_PMV_WW2A1_6", - "CLK_PMV_WW2A2_0", - "CLK_PMV_WW2A2_1", - "CLK_PMV_WW2A2_2", - "CLK_PMV_WW2A2_3", - "CLK_PMV_WW2A2_4", - "CLK_PMV_WW2A2_5", - "CLK_PMV_WW2A2_6", - "CLK_PMV_WW2A3_0", - "CLK_PMV_WW2A3_1", - "CLK_PMV_WW2A3_2", - "CLK_PMV_WW2A3_3", - "CLK_PMV_WW2A3_4", - "CLK_PMV_WW2A3_5", - "CLK_PMV_WW2A3_6", - "CLK_PMV_WW2END0_0", - "CLK_PMV_WW2END0_1", - "CLK_PMV_WW2END0_2", - "CLK_PMV_WW2END0_3", - "CLK_PMV_WW2END0_4", - "CLK_PMV_WW2END0_5", - "CLK_PMV_WW2END0_6", - "CLK_PMV_WW2END1_0", - "CLK_PMV_WW2END1_1", - "CLK_PMV_WW2END1_2", - "CLK_PMV_WW2END1_3", - "CLK_PMV_WW2END1_4", - "CLK_PMV_WW2END1_5", - "CLK_PMV_WW2END1_6", - "CLK_PMV_WW2END2_0", - "CLK_PMV_WW2END2_1", - "CLK_PMV_WW2END2_2", - "CLK_PMV_WW2END2_3", - "CLK_PMV_WW2END2_4", - "CLK_PMV_WW2END2_5", - "CLK_PMV_WW2END2_6", - "CLK_PMV_WW2END3_0", - "CLK_PMV_WW2END3_1", - "CLK_PMV_WW2END3_2", - "CLK_PMV_WW2END3_3", - "CLK_PMV_WW2END3_4", - "CLK_PMV_WW2END3_5", - "CLK_PMV_WW2END3_6", - "CLK_PMV_WW4A0_0", - "CLK_PMV_WW4A0_1", - "CLK_PMV_WW4A0_2", - "CLK_PMV_WW4A0_3", - "CLK_PMV_WW4A0_4", - "CLK_PMV_WW4A0_5", - "CLK_PMV_WW4A0_6", - "CLK_PMV_WW4A1_0", - "CLK_PMV_WW4A1_1", - "CLK_PMV_WW4A1_2", - "CLK_PMV_WW4A1_3", - "CLK_PMV_WW4A1_4", - "CLK_PMV_WW4A1_5", - "CLK_PMV_WW4A1_6", - "CLK_PMV_WW4A2_0", - "CLK_PMV_WW4A2_1", - "CLK_PMV_WW4A2_2", - "CLK_PMV_WW4A2_3", - "CLK_PMV_WW4A2_4", - "CLK_PMV_WW4A2_5", - "CLK_PMV_WW4A2_6", - "CLK_PMV_WW4A3_0", - "CLK_PMV_WW4A3_1", - "CLK_PMV_WW4A3_2", - "CLK_PMV_WW4A3_3", - "CLK_PMV_WW4A3_4", - "CLK_PMV_WW4A3_5", - "CLK_PMV_WW4A3_6", - "CLK_PMV_WW4B0_0", - "CLK_PMV_WW4B0_1", - "CLK_PMV_WW4B0_2", - "CLK_PMV_WW4B0_3", - "CLK_PMV_WW4B0_4", - "CLK_PMV_WW4B0_5", - "CLK_PMV_WW4B0_6", - "CLK_PMV_WW4B1_0", - "CLK_PMV_WW4B1_1", - "CLK_PMV_WW4B1_2", - "CLK_PMV_WW4B1_3", - "CLK_PMV_WW4B1_4", - "CLK_PMV_WW4B1_5", - "CLK_PMV_WW4B1_6", - "CLK_PMV_WW4B2_0", - "CLK_PMV_WW4B2_1", - "CLK_PMV_WW4B2_2", - "CLK_PMV_WW4B2_3", - "CLK_PMV_WW4B2_4", - "CLK_PMV_WW4B2_5", - "CLK_PMV_WW4B2_6", - "CLK_PMV_WW4B3_0", - "CLK_PMV_WW4B3_1", - "CLK_PMV_WW4B3_2", - "CLK_PMV_WW4B3_3", - "CLK_PMV_WW4B3_4", - "CLK_PMV_WW4B3_5", - "CLK_PMV_WW4B3_6", - "CLK_PMV_WW4C0_0", - "CLK_PMV_WW4C0_1", - "CLK_PMV_WW4C0_2", - "CLK_PMV_WW4C0_3", - "CLK_PMV_WW4C0_4", - "CLK_PMV_WW4C0_5", - "CLK_PMV_WW4C0_6", - "CLK_PMV_WW4C1_0", - "CLK_PMV_WW4C1_1", - "CLK_PMV_WW4C1_2", - "CLK_PMV_WW4C1_3", - "CLK_PMV_WW4C1_4", - "CLK_PMV_WW4C1_5", - "CLK_PMV_WW4C1_6", - "CLK_PMV_WW4C2_0", - "CLK_PMV_WW4C2_1", - "CLK_PMV_WW4C2_2", - "CLK_PMV_WW4C2_3", - "CLK_PMV_WW4C2_4", - "CLK_PMV_WW4C2_5", - "CLK_PMV_WW4C2_6", - "CLK_PMV_WW4C3_0", - "CLK_PMV_WW4C3_1", - "CLK_PMV_WW4C3_2", - "CLK_PMV_WW4C3_3", - "CLK_PMV_WW4C3_4", - "CLK_PMV_WW4C3_5", - "CLK_PMV_WW4C3_6", - "CLK_PMV_WW4END0_0", - "CLK_PMV_WW4END0_1", - "CLK_PMV_WW4END0_2", - "CLK_PMV_WW4END0_3", - "CLK_PMV_WW4END0_4", - "CLK_PMV_WW4END0_5", - "CLK_PMV_WW4END0_6", - "CLK_PMV_WW4END1_0", - "CLK_PMV_WW4END1_1", - "CLK_PMV_WW4END1_2", - "CLK_PMV_WW4END1_3", - "CLK_PMV_WW4END1_4", - "CLK_PMV_WW4END1_5", - "CLK_PMV_WW4END1_6", - "CLK_PMV_WW4END2_0", - "CLK_PMV_WW4END2_1", - "CLK_PMV_WW4END2_2", - "CLK_PMV_WW4END2_3", - "CLK_PMV_WW4END2_4", - "CLK_PMV_WW4END2_5", - "CLK_PMV_WW4END2_6", - "CLK_PMV_WW4END3_0", - "CLK_PMV_WW4END3_1", - "CLK_PMV_WW4END3_2", - "CLK_PMV_WW4END3_3", - "CLK_PMV_WW4END3_4", - "CLK_PMV_WW4END3_5", - "CLK_PMV_WW4END3_6" - ] + "wires": { + "CLK_PMV_A0": null, + "CLK_PMV_A1": null, + "CLK_PMV_A2": null, + "CLK_PMV_A3": null, + "CLK_PMV_A4": null, + "CLK_PMV_A5": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP0_1": null, + "CLK_PMV_BYP0_2": null, + "CLK_PMV_BYP0_3": null, + "CLK_PMV_BYP0_4": null, + "CLK_PMV_BYP0_5": null, + "CLK_PMV_BYP0_6": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP1_1": null, + "CLK_PMV_BYP1_2": null, + "CLK_PMV_BYP1_3": null, + "CLK_PMV_BYP1_4": null, + "CLK_PMV_BYP1_5": null, + "CLK_PMV_BYP1_6": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP2_1": null, + "CLK_PMV_BYP2_2": null, + "CLK_PMV_BYP2_3": null, + "CLK_PMV_BYP2_4": null, + "CLK_PMV_BYP2_5": null, + "CLK_PMV_BYP2_6": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP3_1": null, + "CLK_PMV_BYP3_2": null, + "CLK_PMV_BYP3_3": null, + "CLK_PMV_BYP3_4": null, + "CLK_PMV_BYP3_5": null, + "CLK_PMV_BYP3_6": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP4_1": null, + "CLK_PMV_BYP4_2": null, + "CLK_PMV_BYP4_3": null, + "CLK_PMV_BYP4_4": null, + "CLK_PMV_BYP4_5": null, + "CLK_PMV_BYP4_6": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP5_1": null, + "CLK_PMV_BYP5_2": null, + "CLK_PMV_BYP5_3": null, + "CLK_PMV_BYP5_4": null, + "CLK_PMV_BYP5_5": null, + "CLK_PMV_BYP5_6": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP6_1": null, + "CLK_PMV_BYP6_2": null, + "CLK_PMV_BYP6_3": null, + "CLK_PMV_BYP6_4": null, + "CLK_PMV_BYP6_5": null, + "CLK_PMV_BYP6_6": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_BYP7_1": null, + "CLK_PMV_BYP7_2": null, + "CLK_PMV_BYP7_3": null, + "CLK_PMV_BYP7_4": null, + "CLK_PMV_BYP7_5": null, + "CLK_PMV_BYP7_6": null, + "CLK_PMV_CK_BUFG_CASC0": null, + "CLK_PMV_CK_BUFG_CASC1": null, + "CLK_PMV_CK_BUFG_CASC10": null, + "CLK_PMV_CK_BUFG_CASC11": null, + "CLK_PMV_CK_BUFG_CASC12": null, + "CLK_PMV_CK_BUFG_CASC13": null, + "CLK_PMV_CK_BUFG_CASC14": null, + "CLK_PMV_CK_BUFG_CASC15": null, + "CLK_PMV_CK_BUFG_CASC16": null, + "CLK_PMV_CK_BUFG_CASC17": null, + "CLK_PMV_CK_BUFG_CASC18": null, + "CLK_PMV_CK_BUFG_CASC19": null, + "CLK_PMV_CK_BUFG_CASC2": null, + "CLK_PMV_CK_BUFG_CASC20": null, + "CLK_PMV_CK_BUFG_CASC21": null, + "CLK_PMV_CK_BUFG_CASC22": null, + "CLK_PMV_CK_BUFG_CASC23": null, + "CLK_PMV_CK_BUFG_CASC24": null, + "CLK_PMV_CK_BUFG_CASC25": null, + "CLK_PMV_CK_BUFG_CASC26": null, + "CLK_PMV_CK_BUFG_CASC27": null, + "CLK_PMV_CK_BUFG_CASC28": null, + "CLK_PMV_CK_BUFG_CASC29": null, + "CLK_PMV_CK_BUFG_CASC3": null, + "CLK_PMV_CK_BUFG_CASC30": null, + "CLK_PMV_CK_BUFG_CASC31": null, + "CLK_PMV_CK_BUFG_CASC4": null, + "CLK_PMV_CK_BUFG_CASC5": null, + "CLK_PMV_CK_BUFG_CASC6": null, + "CLK_PMV_CK_BUFG_CASC7": null, + "CLK_PMV_CK_BUFG_CASC8": null, + "CLK_PMV_CK_BUFG_CASC9": null, + "CLK_PMV_CK_GCLK0": null, + "CLK_PMV_CK_GCLK1": null, + "CLK_PMV_CK_GCLK10": null, + "CLK_PMV_CK_GCLK11": null, + "CLK_PMV_CK_GCLK12": null, + "CLK_PMV_CK_GCLK13": null, + "CLK_PMV_CK_GCLK14": null, + "CLK_PMV_CK_GCLK15": null, + "CLK_PMV_CK_GCLK16": null, + "CLK_PMV_CK_GCLK17": null, + "CLK_PMV_CK_GCLK18": null, + "CLK_PMV_CK_GCLK19": null, + "CLK_PMV_CK_GCLK2": null, + "CLK_PMV_CK_GCLK20": null, + "CLK_PMV_CK_GCLK21": null, + "CLK_PMV_CK_GCLK22": null, + "CLK_PMV_CK_GCLK23": null, + "CLK_PMV_CK_GCLK24": null, + "CLK_PMV_CK_GCLK25": null, + "CLK_PMV_CK_GCLK26": null, + "CLK_PMV_CK_GCLK27": null, + "CLK_PMV_CK_GCLK28": null, + "CLK_PMV_CK_GCLK29": null, + "CLK_PMV_CK_GCLK3": null, + "CLK_PMV_CK_GCLK30": null, + "CLK_PMV_CK_GCLK31": null, + "CLK_PMV_CK_GCLK4": null, + "CLK_PMV_CK_GCLK5": null, + "CLK_PMV_CK_GCLK6": null, + "CLK_PMV_CK_GCLK7": null, + "CLK_PMV_CK_GCLK8": null, + "CLK_PMV_CK_GCLK9": null, + "CLK_PMV_CLK0_0": null, + "CLK_PMV_CLK0_1": null, + "CLK_PMV_CLK0_2": null, + "CLK_PMV_CLK0_3": null, + "CLK_PMV_CLK0_4": null, + "CLK_PMV_CLK0_5": null, + "CLK_PMV_CLK0_6": null, + "CLK_PMV_CLK1_0": null, + "CLK_PMV_CLK1_1": null, + "CLK_PMV_CLK1_2": null, + "CLK_PMV_CLK1_3": null, + "CLK_PMV_CLK1_4": null, + "CLK_PMV_CLK1_5": null, + "CLK_PMV_CLK1_6": null, + "CLK_PMV_CTRL0_0": null, + "CLK_PMV_CTRL0_1": null, + "CLK_PMV_CTRL0_2": null, + "CLK_PMV_CTRL0_3": null, + "CLK_PMV_CTRL0_4": null, + "CLK_PMV_CTRL0_5": null, + "CLK_PMV_CTRL0_6": null, + "CLK_PMV_CTRL1_0": null, + "CLK_PMV_CTRL1_1": null, + "CLK_PMV_CTRL1_2": null, + "CLK_PMV_CTRL1_3": null, + "CLK_PMV_CTRL1_4": null, + "CLK_PMV_CTRL1_5": null, + "CLK_PMV_CTRL1_6": null, + "CLK_PMV_EE2A0_0": null, + "CLK_PMV_EE2A0_1": null, + "CLK_PMV_EE2A0_2": null, + "CLK_PMV_EE2A0_3": null, + "CLK_PMV_EE2A0_4": null, + "CLK_PMV_EE2A0_5": null, + "CLK_PMV_EE2A0_6": null, + "CLK_PMV_EE2A1_0": null, + "CLK_PMV_EE2A1_1": null, + "CLK_PMV_EE2A1_2": null, + "CLK_PMV_EE2A1_3": null, + "CLK_PMV_EE2A1_4": null, + "CLK_PMV_EE2A1_5": null, + "CLK_PMV_EE2A1_6": null, + "CLK_PMV_EE2A2_0": null, + "CLK_PMV_EE2A2_1": null, + "CLK_PMV_EE2A2_2": null, + "CLK_PMV_EE2A2_3": null, + "CLK_PMV_EE2A2_4": null, + "CLK_PMV_EE2A2_5": null, + "CLK_PMV_EE2A2_6": null, + "CLK_PMV_EE2A3_0": null, + "CLK_PMV_EE2A3_1": null, + "CLK_PMV_EE2A3_2": null, + "CLK_PMV_EE2A3_3": null, + "CLK_PMV_EE2A3_4": null, + "CLK_PMV_EE2A3_5": null, + "CLK_PMV_EE2A3_6": null, + "CLK_PMV_EE2BEG0_0": null, + "CLK_PMV_EE2BEG0_1": null, + "CLK_PMV_EE2BEG0_2": null, + "CLK_PMV_EE2BEG0_3": null, + "CLK_PMV_EE2BEG0_4": null, + "CLK_PMV_EE2BEG0_5": null, + "CLK_PMV_EE2BEG0_6": null, + "CLK_PMV_EE2BEG1_0": null, + "CLK_PMV_EE2BEG1_1": null, + "CLK_PMV_EE2BEG1_2": null, + "CLK_PMV_EE2BEG1_3": null, + "CLK_PMV_EE2BEG1_4": null, + "CLK_PMV_EE2BEG1_5": null, + "CLK_PMV_EE2BEG1_6": null, + "CLK_PMV_EE2BEG2_0": null, + "CLK_PMV_EE2BEG2_1": null, + "CLK_PMV_EE2BEG2_2": null, + "CLK_PMV_EE2BEG2_3": null, + "CLK_PMV_EE2BEG2_4": null, + "CLK_PMV_EE2BEG2_5": null, + "CLK_PMV_EE2BEG2_6": null, + "CLK_PMV_EE2BEG3_0": null, + "CLK_PMV_EE2BEG3_1": null, + "CLK_PMV_EE2BEG3_2": null, + "CLK_PMV_EE2BEG3_3": null, + "CLK_PMV_EE2BEG3_4": null, + "CLK_PMV_EE2BEG3_5": null, + "CLK_PMV_EE2BEG3_6": null, + "CLK_PMV_EE4A0_0": null, + "CLK_PMV_EE4A0_1": null, + "CLK_PMV_EE4A0_2": null, + "CLK_PMV_EE4A0_3": null, + "CLK_PMV_EE4A0_4": null, + "CLK_PMV_EE4A0_5": null, + "CLK_PMV_EE4A0_6": null, + "CLK_PMV_EE4A1_0": null, + "CLK_PMV_EE4A1_1": null, + "CLK_PMV_EE4A1_2": null, + "CLK_PMV_EE4A1_3": null, + "CLK_PMV_EE4A1_4": null, + "CLK_PMV_EE4A1_5": null, + "CLK_PMV_EE4A1_6": null, + "CLK_PMV_EE4A2_0": null, + "CLK_PMV_EE4A2_1": null, + "CLK_PMV_EE4A2_2": null, + "CLK_PMV_EE4A2_3": null, + "CLK_PMV_EE4A2_4": null, + "CLK_PMV_EE4A2_5": null, + "CLK_PMV_EE4A2_6": null, + "CLK_PMV_EE4A3_0": null, + "CLK_PMV_EE4A3_1": null, + "CLK_PMV_EE4A3_2": null, + "CLK_PMV_EE4A3_3": null, + "CLK_PMV_EE4A3_4": null, + "CLK_PMV_EE4A3_5": null, + "CLK_PMV_EE4A3_6": null, + "CLK_PMV_EE4B0_0": null, + "CLK_PMV_EE4B0_1": null, + "CLK_PMV_EE4B0_2": null, + "CLK_PMV_EE4B0_3": null, + "CLK_PMV_EE4B0_4": null, + "CLK_PMV_EE4B0_5": null, + "CLK_PMV_EE4B0_6": null, + "CLK_PMV_EE4B1_0": null, + "CLK_PMV_EE4B1_1": null, + "CLK_PMV_EE4B1_2": null, + "CLK_PMV_EE4B1_3": null, + "CLK_PMV_EE4B1_4": null, + "CLK_PMV_EE4B1_5": null, + "CLK_PMV_EE4B1_6": null, + "CLK_PMV_EE4B2_0": null, + "CLK_PMV_EE4B2_1": null, + "CLK_PMV_EE4B2_2": null, + "CLK_PMV_EE4B2_3": null, + "CLK_PMV_EE4B2_4": null, + "CLK_PMV_EE4B2_5": null, + "CLK_PMV_EE4B2_6": null, + "CLK_PMV_EE4B3_0": null, + "CLK_PMV_EE4B3_1": null, + "CLK_PMV_EE4B3_2": null, + "CLK_PMV_EE4B3_3": null, + "CLK_PMV_EE4B3_4": null, + "CLK_PMV_EE4B3_5": null, + "CLK_PMV_EE4B3_6": null, + "CLK_PMV_EE4BEG0_0": null, + "CLK_PMV_EE4BEG0_1": null, + "CLK_PMV_EE4BEG0_2": null, + "CLK_PMV_EE4BEG0_3": null, + "CLK_PMV_EE4BEG0_4": null, + "CLK_PMV_EE4BEG0_5": null, + "CLK_PMV_EE4BEG0_6": null, + "CLK_PMV_EE4BEG1_0": null, + "CLK_PMV_EE4BEG1_1": null, + "CLK_PMV_EE4BEG1_2": null, + "CLK_PMV_EE4BEG1_3": null, + "CLK_PMV_EE4BEG1_4": null, + "CLK_PMV_EE4BEG1_5": null, + "CLK_PMV_EE4BEG1_6": null, + "CLK_PMV_EE4BEG2_0": null, + "CLK_PMV_EE4BEG2_1": null, + "CLK_PMV_EE4BEG2_2": null, + "CLK_PMV_EE4BEG2_3": null, + "CLK_PMV_EE4BEG2_4": null, + "CLK_PMV_EE4BEG2_5": null, + "CLK_PMV_EE4BEG2_6": null, + "CLK_PMV_EE4BEG3_0": null, + "CLK_PMV_EE4BEG3_1": null, + "CLK_PMV_EE4BEG3_2": null, + "CLK_PMV_EE4BEG3_3": null, + "CLK_PMV_EE4BEG3_4": null, + "CLK_PMV_EE4BEG3_5": null, + "CLK_PMV_EE4BEG3_6": null, + "CLK_PMV_EE4C0_0": null, + "CLK_PMV_EE4C0_1": null, + "CLK_PMV_EE4C0_2": null, + "CLK_PMV_EE4C0_3": null, + "CLK_PMV_EE4C0_4": null, + "CLK_PMV_EE4C0_5": null, + "CLK_PMV_EE4C0_6": null, + "CLK_PMV_EE4C1_0": null, + "CLK_PMV_EE4C1_1": null, + "CLK_PMV_EE4C1_2": null, + "CLK_PMV_EE4C1_3": null, + "CLK_PMV_EE4C1_4": null, + "CLK_PMV_EE4C1_5": null, + "CLK_PMV_EE4C1_6": null, + "CLK_PMV_EE4C2_0": null, + "CLK_PMV_EE4C2_1": null, + "CLK_PMV_EE4C2_2": null, + "CLK_PMV_EE4C2_3": null, + "CLK_PMV_EE4C2_4": null, + "CLK_PMV_EE4C2_5": null, + "CLK_PMV_EE4C2_6": null, + "CLK_PMV_EE4C3_0": null, + "CLK_PMV_EE4C3_1": null, + "CLK_PMV_EE4C3_2": null, + "CLK_PMV_EE4C3_3": null, + "CLK_PMV_EE4C3_4": null, + "CLK_PMV_EE4C3_5": null, + "CLK_PMV_EE4C3_6": null, + "CLK_PMV_EL1BEG0_0": null, + "CLK_PMV_EL1BEG0_1": null, + "CLK_PMV_EL1BEG0_2": null, + "CLK_PMV_EL1BEG0_3": null, + "CLK_PMV_EL1BEG0_4": null, + "CLK_PMV_EL1BEG0_5": null, + "CLK_PMV_EL1BEG0_6": null, + "CLK_PMV_EL1BEG1_0": null, + "CLK_PMV_EL1BEG1_1": null, + "CLK_PMV_EL1BEG1_2": null, + "CLK_PMV_EL1BEG1_3": null, + "CLK_PMV_EL1BEG1_4": null, + "CLK_PMV_EL1BEG1_5": null, + "CLK_PMV_EL1BEG1_6": null, + "CLK_PMV_EL1BEG2_0": null, + "CLK_PMV_EL1BEG2_1": null, + "CLK_PMV_EL1BEG2_2": null, + "CLK_PMV_EL1BEG2_3": null, + "CLK_PMV_EL1BEG2_4": null, + "CLK_PMV_EL1BEG2_5": null, + "CLK_PMV_EL1BEG2_6": null, + "CLK_PMV_EL1BEG3_0": null, + "CLK_PMV_EL1BEG3_1": null, + "CLK_PMV_EL1BEG3_2": null, + "CLK_PMV_EL1BEG3_3": null, + "CLK_PMV_EL1BEG3_4": null, + "CLK_PMV_EL1BEG3_5": null, + "CLK_PMV_EL1BEG3_6": null, + "CLK_PMV_EN": null, + "CLK_PMV_ER1BEG0_0": null, + "CLK_PMV_ER1BEG0_1": null, + "CLK_PMV_ER1BEG0_2": null, + "CLK_PMV_ER1BEG0_3": null, + "CLK_PMV_ER1BEG0_4": null, + "CLK_PMV_ER1BEG0_5": null, + "CLK_PMV_ER1BEG0_6": null, + "CLK_PMV_ER1BEG1_0": null, + "CLK_PMV_ER1BEG1_1": null, + "CLK_PMV_ER1BEG1_2": null, + "CLK_PMV_ER1BEG1_3": null, + "CLK_PMV_ER1BEG1_4": null, + "CLK_PMV_ER1BEG1_5": null, + "CLK_PMV_ER1BEG1_6": null, + "CLK_PMV_ER1BEG2_0": null, + "CLK_PMV_ER1BEG2_1": null, + "CLK_PMV_ER1BEG2_2": null, + "CLK_PMV_ER1BEG2_3": null, + "CLK_PMV_ER1BEG2_4": null, + "CLK_PMV_ER1BEG2_5": null, + "CLK_PMV_ER1BEG2_6": null, + "CLK_PMV_ER1BEG3_0": null, + "CLK_PMV_ER1BEG3_1": null, + "CLK_PMV_ER1BEG3_2": null, + "CLK_PMV_ER1BEG3_3": null, + "CLK_PMV_ER1BEG3_4": null, + "CLK_PMV_ER1BEG3_5": null, + "CLK_PMV_ER1BEG3_6": null, + "CLK_PMV_FAN0_0": null, + "CLK_PMV_FAN0_1": null, + "CLK_PMV_FAN0_2": null, + "CLK_PMV_FAN0_3": null, + "CLK_PMV_FAN0_4": null, + "CLK_PMV_FAN0_5": null, + "CLK_PMV_FAN0_6": null, + "CLK_PMV_FAN1_0": null, + "CLK_PMV_FAN1_1": null, + "CLK_PMV_FAN1_2": null, + "CLK_PMV_FAN1_3": null, + "CLK_PMV_FAN1_4": null, + "CLK_PMV_FAN1_5": null, + "CLK_PMV_FAN1_6": null, + "CLK_PMV_FAN2_0": null, + "CLK_PMV_FAN2_1": null, + "CLK_PMV_FAN2_2": null, + "CLK_PMV_FAN2_3": null, + "CLK_PMV_FAN2_4": null, + "CLK_PMV_FAN2_5": null, + "CLK_PMV_FAN2_6": null, + "CLK_PMV_FAN3_0": null, + "CLK_PMV_FAN3_1": null, + "CLK_PMV_FAN3_2": null, + "CLK_PMV_FAN3_3": null, + "CLK_PMV_FAN3_4": null, + "CLK_PMV_FAN3_5": null, + "CLK_PMV_FAN3_6": null, + "CLK_PMV_FAN4_0": null, + "CLK_PMV_FAN4_1": null, + "CLK_PMV_FAN4_2": null, + "CLK_PMV_FAN4_3": null, + "CLK_PMV_FAN4_4": null, + "CLK_PMV_FAN4_5": null, + "CLK_PMV_FAN4_6": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN5_1": null, + "CLK_PMV_FAN5_2": null, + "CLK_PMV_FAN5_3": null, + "CLK_PMV_FAN5_4": null, + "CLK_PMV_FAN5_5": null, + "CLK_PMV_FAN5_6": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN6_1": null, + "CLK_PMV_FAN6_2": null, + "CLK_PMV_FAN6_3": null, + "CLK_PMV_FAN6_4": null, + "CLK_PMV_FAN6_5": null, + "CLK_PMV_FAN6_6": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_FAN7_1": null, + "CLK_PMV_FAN7_2": null, + "CLK_PMV_FAN7_3": null, + "CLK_PMV_FAN7_4": null, + "CLK_PMV_FAN7_5": null, + "CLK_PMV_FAN7_6": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX0_1": null, + "CLK_PMV_IMUX0_2": null, + "CLK_PMV_IMUX0_3": null, + "CLK_PMV_IMUX0_4": null, + "CLK_PMV_IMUX0_5": null, + "CLK_PMV_IMUX0_6": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX10_1": null, + "CLK_PMV_IMUX10_2": null, + "CLK_PMV_IMUX10_3": null, + "CLK_PMV_IMUX10_4": null, + "CLK_PMV_IMUX10_5": null, + "CLK_PMV_IMUX10_6": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX11_1": null, + "CLK_PMV_IMUX11_2": null, + "CLK_PMV_IMUX11_3": null, + "CLK_PMV_IMUX11_4": null, + "CLK_PMV_IMUX11_5": null, + "CLK_PMV_IMUX11_6": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX12_1": null, + "CLK_PMV_IMUX12_2": null, + "CLK_PMV_IMUX12_3": null, + "CLK_PMV_IMUX12_4": null, + "CLK_PMV_IMUX12_5": null, + "CLK_PMV_IMUX12_6": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX13_1": null, + "CLK_PMV_IMUX13_2": null, + "CLK_PMV_IMUX13_3": null, + "CLK_PMV_IMUX13_4": null, + "CLK_PMV_IMUX13_5": null, + "CLK_PMV_IMUX13_6": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX14_1": null, + "CLK_PMV_IMUX14_2": null, + "CLK_PMV_IMUX14_3": null, + "CLK_PMV_IMUX14_4": null, + "CLK_PMV_IMUX14_5": null, + "CLK_PMV_IMUX14_6": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX15_1": null, + "CLK_PMV_IMUX15_2": null, + "CLK_PMV_IMUX15_3": null, + "CLK_PMV_IMUX15_4": null, + "CLK_PMV_IMUX15_5": null, + "CLK_PMV_IMUX15_6": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX16_1": null, + "CLK_PMV_IMUX16_2": null, + "CLK_PMV_IMUX16_3": null, + "CLK_PMV_IMUX16_4": null, + "CLK_PMV_IMUX16_5": null, + "CLK_PMV_IMUX16_6": null, + "CLK_PMV_IMUX17_0": null, + "CLK_PMV_IMUX17_1": null, + "CLK_PMV_IMUX17_2": null, + "CLK_PMV_IMUX17_3": null, + "CLK_PMV_IMUX17_4": null, + "CLK_PMV_IMUX17_5": null, + "CLK_PMV_IMUX17_6": null, + "CLK_PMV_IMUX18_0": null, + "CLK_PMV_IMUX18_1": null, + "CLK_PMV_IMUX18_2": null, + "CLK_PMV_IMUX18_3": null, + "CLK_PMV_IMUX18_4": null, + "CLK_PMV_IMUX18_5": null, + "CLK_PMV_IMUX18_6": null, + "CLK_PMV_IMUX19_0": null, + "CLK_PMV_IMUX19_1": null, + "CLK_PMV_IMUX19_2": null, + "CLK_PMV_IMUX19_3": null, + "CLK_PMV_IMUX19_4": null, + "CLK_PMV_IMUX19_5": null, + "CLK_PMV_IMUX19_6": null, + "CLK_PMV_IMUX1_0": null, + "CLK_PMV_IMUX1_1": null, + "CLK_PMV_IMUX1_2": null, + "CLK_PMV_IMUX1_3": null, + "CLK_PMV_IMUX1_4": null, + "CLK_PMV_IMUX1_5": null, + "CLK_PMV_IMUX1_6": null, + "CLK_PMV_IMUX20_0": null, + "CLK_PMV_IMUX20_1": null, + "CLK_PMV_IMUX20_2": null, + "CLK_PMV_IMUX20_3": null, + "CLK_PMV_IMUX20_4": null, + "CLK_PMV_IMUX20_5": null, + "CLK_PMV_IMUX20_6": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX21_1": null, + "CLK_PMV_IMUX21_2": null, + "CLK_PMV_IMUX21_3": null, + "CLK_PMV_IMUX21_4": null, + "CLK_PMV_IMUX21_5": null, + "CLK_PMV_IMUX21_6": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX22_1": null, + "CLK_PMV_IMUX22_2": null, + "CLK_PMV_IMUX22_3": null, + "CLK_PMV_IMUX22_4": null, + "CLK_PMV_IMUX22_5": null, + "CLK_PMV_IMUX22_6": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX23_1": null, + "CLK_PMV_IMUX23_2": null, + "CLK_PMV_IMUX23_3": null, + "CLK_PMV_IMUX23_4": null, + "CLK_PMV_IMUX23_5": null, + "CLK_PMV_IMUX23_6": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX24_1": null, + "CLK_PMV_IMUX24_2": null, + "CLK_PMV_IMUX24_3": null, + "CLK_PMV_IMUX24_4": null, + "CLK_PMV_IMUX24_5": null, + "CLK_PMV_IMUX24_6": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX25_1": null, + "CLK_PMV_IMUX25_2": null, + "CLK_PMV_IMUX25_3": null, + "CLK_PMV_IMUX25_4": null, + "CLK_PMV_IMUX25_5": null, + "CLK_PMV_IMUX25_6": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX26_1": null, + "CLK_PMV_IMUX26_2": null, + "CLK_PMV_IMUX26_3": null, + "CLK_PMV_IMUX26_4": null, + "CLK_PMV_IMUX26_5": null, + "CLK_PMV_IMUX26_6": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX27_1": null, + "CLK_PMV_IMUX27_2": null, + "CLK_PMV_IMUX27_3": null, + "CLK_PMV_IMUX27_4": null, + "CLK_PMV_IMUX27_5": null, + "CLK_PMV_IMUX27_6": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX28_1": null, + "CLK_PMV_IMUX28_2": null, + "CLK_PMV_IMUX28_3": null, + "CLK_PMV_IMUX28_4": null, + "CLK_PMV_IMUX28_5": null, + "CLK_PMV_IMUX28_6": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX29_1": null, + "CLK_PMV_IMUX29_2": null, + "CLK_PMV_IMUX29_3": null, + "CLK_PMV_IMUX29_4": null, + "CLK_PMV_IMUX29_5": null, + "CLK_PMV_IMUX29_6": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX2_1": null, + "CLK_PMV_IMUX2_2": null, + "CLK_PMV_IMUX2_3": null, + "CLK_PMV_IMUX2_4": null, + "CLK_PMV_IMUX2_5": null, + "CLK_PMV_IMUX2_6": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX30_1": null, + "CLK_PMV_IMUX30_2": null, + "CLK_PMV_IMUX30_3": null, + "CLK_PMV_IMUX30_4": null, + "CLK_PMV_IMUX30_5": null, + "CLK_PMV_IMUX30_6": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX31_1": null, + "CLK_PMV_IMUX31_2": null, + "CLK_PMV_IMUX31_3": null, + "CLK_PMV_IMUX31_4": null, + "CLK_PMV_IMUX31_5": null, + "CLK_PMV_IMUX31_6": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX32_1": null, + "CLK_PMV_IMUX32_2": null, + "CLK_PMV_IMUX32_3": null, + "CLK_PMV_IMUX32_4": null, + "CLK_PMV_IMUX32_5": null, + "CLK_PMV_IMUX32_6": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX33_1": null, + "CLK_PMV_IMUX33_2": null, + "CLK_PMV_IMUX33_3": null, + "CLK_PMV_IMUX33_4": null, + "CLK_PMV_IMUX33_5": null, + "CLK_PMV_IMUX33_6": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX34_1": null, + "CLK_PMV_IMUX34_2": null, + "CLK_PMV_IMUX34_3": null, + "CLK_PMV_IMUX34_4": null, + "CLK_PMV_IMUX34_5": null, + "CLK_PMV_IMUX34_6": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX35_1": null, + "CLK_PMV_IMUX35_2": null, + "CLK_PMV_IMUX35_3": null, + "CLK_PMV_IMUX35_4": null, + "CLK_PMV_IMUX35_5": null, + "CLK_PMV_IMUX35_6": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX36_1": null, + "CLK_PMV_IMUX36_2": null, + "CLK_PMV_IMUX36_3": null, + "CLK_PMV_IMUX36_4": null, + "CLK_PMV_IMUX36_5": null, + "CLK_PMV_IMUX36_6": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX37_1": null, + "CLK_PMV_IMUX37_2": null, + "CLK_PMV_IMUX37_3": null, + "CLK_PMV_IMUX37_4": null, + "CLK_PMV_IMUX37_5": null, + "CLK_PMV_IMUX37_6": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX38_1": null, + "CLK_PMV_IMUX38_2": null, + "CLK_PMV_IMUX38_3": null, + "CLK_PMV_IMUX38_4": null, + "CLK_PMV_IMUX38_5": null, + "CLK_PMV_IMUX38_6": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX39_1": null, + "CLK_PMV_IMUX39_2": null, + "CLK_PMV_IMUX39_3": null, + "CLK_PMV_IMUX39_4": null, + "CLK_PMV_IMUX39_5": null, + "CLK_PMV_IMUX39_6": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX3_1": null, + "CLK_PMV_IMUX3_2": null, + "CLK_PMV_IMUX3_3": null, + "CLK_PMV_IMUX3_4": null, + "CLK_PMV_IMUX3_5": null, + "CLK_PMV_IMUX3_6": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX40_1": null, + "CLK_PMV_IMUX40_2": null, + "CLK_PMV_IMUX40_3": null, + "CLK_PMV_IMUX40_4": null, + "CLK_PMV_IMUX40_5": null, + "CLK_PMV_IMUX40_6": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX41_1": null, + "CLK_PMV_IMUX41_2": null, + "CLK_PMV_IMUX41_3": null, + "CLK_PMV_IMUX41_4": null, + "CLK_PMV_IMUX41_5": null, + "CLK_PMV_IMUX41_6": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX42_1": null, + "CLK_PMV_IMUX42_2": null, + "CLK_PMV_IMUX42_3": null, + "CLK_PMV_IMUX42_4": null, + "CLK_PMV_IMUX42_5": null, + "CLK_PMV_IMUX42_6": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX43_1": null, + "CLK_PMV_IMUX43_2": null, + "CLK_PMV_IMUX43_3": null, + "CLK_PMV_IMUX43_4": null, + "CLK_PMV_IMUX43_5": null, + "CLK_PMV_IMUX43_6": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX44_1": null, + "CLK_PMV_IMUX44_2": null, + "CLK_PMV_IMUX44_3": null, + "CLK_PMV_IMUX44_4": null, + "CLK_PMV_IMUX44_5": null, + "CLK_PMV_IMUX44_6": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX45_1": null, + "CLK_PMV_IMUX45_2": null, + "CLK_PMV_IMUX45_3": null, + "CLK_PMV_IMUX45_4": null, + "CLK_PMV_IMUX45_5": null, + "CLK_PMV_IMUX45_6": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX46_1": null, + "CLK_PMV_IMUX46_2": null, + "CLK_PMV_IMUX46_3": null, + "CLK_PMV_IMUX46_4": null, + "CLK_PMV_IMUX46_5": null, + "CLK_PMV_IMUX46_6": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX47_1": null, + "CLK_PMV_IMUX47_2": null, + "CLK_PMV_IMUX47_3": null, + "CLK_PMV_IMUX47_4": null, + "CLK_PMV_IMUX47_5": null, + "CLK_PMV_IMUX47_6": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX4_1": null, + "CLK_PMV_IMUX4_2": null, + "CLK_PMV_IMUX4_3": null, + "CLK_PMV_IMUX4_4": null, + "CLK_PMV_IMUX4_5": null, + "CLK_PMV_IMUX4_6": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX5_1": null, + "CLK_PMV_IMUX5_2": null, + "CLK_PMV_IMUX5_3": null, + "CLK_PMV_IMUX5_4": null, + "CLK_PMV_IMUX5_5": null, + "CLK_PMV_IMUX5_6": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX6_1": null, + "CLK_PMV_IMUX6_2": null, + "CLK_PMV_IMUX6_3": null, + "CLK_PMV_IMUX6_4": null, + "CLK_PMV_IMUX6_5": null, + "CLK_PMV_IMUX6_6": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX7_1": null, + "CLK_PMV_IMUX7_2": null, + "CLK_PMV_IMUX7_3": null, + "CLK_PMV_IMUX7_4": null, + "CLK_PMV_IMUX7_5": null, + "CLK_PMV_IMUX7_6": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX8_1": null, + "CLK_PMV_IMUX8_2": null, + "CLK_PMV_IMUX8_3": null, + "CLK_PMV_IMUX8_4": null, + "CLK_PMV_IMUX8_5": null, + "CLK_PMV_IMUX8_6": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_IMUX9_1": null, + "CLK_PMV_IMUX9_2": null, + "CLK_PMV_IMUX9_3": null, + "CLK_PMV_IMUX9_4": null, + "CLK_PMV_IMUX9_5": null, + "CLK_PMV_IMUX9_6": null, + "CLK_PMV_LH10_0": null, + "CLK_PMV_LH10_1": null, + "CLK_PMV_LH10_2": null, + "CLK_PMV_LH10_3": null, + "CLK_PMV_LH10_4": null, + "CLK_PMV_LH10_5": null, + "CLK_PMV_LH10_6": null, + "CLK_PMV_LH11_0": null, + "CLK_PMV_LH11_1": null, + "CLK_PMV_LH11_2": null, + "CLK_PMV_LH11_3": null, + "CLK_PMV_LH11_4": null, + "CLK_PMV_LH11_5": null, + "CLK_PMV_LH11_6": null, + "CLK_PMV_LH12_0": null, + "CLK_PMV_LH12_1": null, + "CLK_PMV_LH12_2": null, + "CLK_PMV_LH12_3": null, + "CLK_PMV_LH12_4": null, + "CLK_PMV_LH12_5": null, + "CLK_PMV_LH12_6": null, + "CLK_PMV_LH1_0": null, + "CLK_PMV_LH1_1": null, + "CLK_PMV_LH1_2": null, + "CLK_PMV_LH1_3": null, + "CLK_PMV_LH1_4": null, + "CLK_PMV_LH1_5": null, + "CLK_PMV_LH1_6": null, + "CLK_PMV_LH2_0": null, + "CLK_PMV_LH2_1": null, + "CLK_PMV_LH2_2": null, + "CLK_PMV_LH2_3": null, + "CLK_PMV_LH2_4": null, + "CLK_PMV_LH2_5": null, + "CLK_PMV_LH2_6": null, + "CLK_PMV_LH3_0": null, + "CLK_PMV_LH3_1": null, + "CLK_PMV_LH3_2": null, + "CLK_PMV_LH3_3": null, + "CLK_PMV_LH3_4": null, + "CLK_PMV_LH3_5": null, + "CLK_PMV_LH3_6": null, + "CLK_PMV_LH4_0": null, + "CLK_PMV_LH4_1": null, + "CLK_PMV_LH4_2": null, + "CLK_PMV_LH4_3": null, + "CLK_PMV_LH4_4": null, + "CLK_PMV_LH4_5": null, + "CLK_PMV_LH4_6": null, + "CLK_PMV_LH5_0": null, + "CLK_PMV_LH5_1": null, + "CLK_PMV_LH5_2": null, + "CLK_PMV_LH5_3": null, + "CLK_PMV_LH5_4": null, + "CLK_PMV_LH5_5": null, + "CLK_PMV_LH5_6": null, + "CLK_PMV_LH6_0": null, + "CLK_PMV_LH6_1": null, + "CLK_PMV_LH6_2": null, + "CLK_PMV_LH6_3": null, + "CLK_PMV_LH6_4": null, + "CLK_PMV_LH6_5": null, + "CLK_PMV_LH6_6": null, + "CLK_PMV_LH7_0": null, + "CLK_PMV_LH7_1": null, + "CLK_PMV_LH7_2": null, + "CLK_PMV_LH7_3": null, + "CLK_PMV_LH7_4": null, + "CLK_PMV_LH7_5": null, + "CLK_PMV_LH7_6": null, + "CLK_PMV_LH8_0": null, + "CLK_PMV_LH8_1": null, + "CLK_PMV_LH8_2": null, + "CLK_PMV_LH8_3": null, + "CLK_PMV_LH8_4": null, + "CLK_PMV_LH8_5": null, + "CLK_PMV_LH8_6": null, + "CLK_PMV_LH9_0": null, + "CLK_PMV_LH9_1": null, + "CLK_PMV_LH9_2": null, + "CLK_PMV_LH9_3": null, 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null, + "CLK_PMV_MONITOR_P_0": null, + "CLK_PMV_MONITOR_P_1": null, + "CLK_PMV_MONITOR_P_2": null, + "CLK_PMV_MONITOR_P_3": null, + "CLK_PMV_MONITOR_P_4": null, + "CLK_PMV_MONITOR_P_5": null, + "CLK_PMV_MONITOR_P_6": null, + "CLK_PMV_NE2A0_0": null, + "CLK_PMV_NE2A0_1": null, + "CLK_PMV_NE2A0_2": null, + "CLK_PMV_NE2A0_3": null, + "CLK_PMV_NE2A0_4": null, + "CLK_PMV_NE2A0_5": null, + "CLK_PMV_NE2A0_6": null, + "CLK_PMV_NE2A1_0": null, + "CLK_PMV_NE2A1_1": null, + "CLK_PMV_NE2A1_2": null, + "CLK_PMV_NE2A1_3": null, + "CLK_PMV_NE2A1_4": null, + "CLK_PMV_NE2A1_5": null, + "CLK_PMV_NE2A1_6": null, + "CLK_PMV_NE2A2_0": null, + "CLK_PMV_NE2A2_1": null, + "CLK_PMV_NE2A2_2": null, + "CLK_PMV_NE2A2_3": null, + "CLK_PMV_NE2A2_4": null, + "CLK_PMV_NE2A2_5": null, + "CLK_PMV_NE2A2_6": null, + "CLK_PMV_NE2A3_0": null, + "CLK_PMV_NE2A3_1": null, + "CLK_PMV_NE2A3_2": null, + "CLK_PMV_NE2A3_3": null, + "CLK_PMV_NE2A3_4": null, + "CLK_PMV_NE2A3_5": null, + "CLK_PMV_NE2A3_6": null, + "CLK_PMV_NE4BEG0_0": null, + "CLK_PMV_NE4BEG0_1": null, + "CLK_PMV_NE4BEG0_2": null, + "CLK_PMV_NE4BEG0_3": null, + "CLK_PMV_NE4BEG0_4": null, + "CLK_PMV_NE4BEG0_5": null, + "CLK_PMV_NE4BEG0_6": null, + "CLK_PMV_NE4BEG1_0": null, + "CLK_PMV_NE4BEG1_1": null, + "CLK_PMV_NE4BEG1_2": null, + "CLK_PMV_NE4BEG1_3": null, + "CLK_PMV_NE4BEG1_4": null, + "CLK_PMV_NE4BEG1_5": null, + "CLK_PMV_NE4BEG1_6": null, + "CLK_PMV_NE4BEG2_0": null, + "CLK_PMV_NE4BEG2_1": null, + "CLK_PMV_NE4BEG2_2": null, + "CLK_PMV_NE4BEG2_3": null, + "CLK_PMV_NE4BEG2_4": null, + "CLK_PMV_NE4BEG2_5": null, + "CLK_PMV_NE4BEG2_6": null, + "CLK_PMV_NE4BEG3_0": null, + "CLK_PMV_NE4BEG3_1": null, + "CLK_PMV_NE4BEG3_2": null, + "CLK_PMV_NE4BEG3_3": null, + "CLK_PMV_NE4BEG3_4": null, + "CLK_PMV_NE4BEG3_5": null, + "CLK_PMV_NE4BEG3_6": null, + "CLK_PMV_NE4C0_0": null, + "CLK_PMV_NE4C0_1": null, + "CLK_PMV_NE4C0_2": null, + "CLK_PMV_NE4C0_3": null, + "CLK_PMV_NE4C0_4": null, + "CLK_PMV_NE4C0_5": null, + "CLK_PMV_NE4C0_6": null, + "CLK_PMV_NE4C1_0": null, + "CLK_PMV_NE4C1_1": null, + "CLK_PMV_NE4C1_2": null, + "CLK_PMV_NE4C1_3": null, + "CLK_PMV_NE4C1_4": null, + "CLK_PMV_NE4C1_5": null, + "CLK_PMV_NE4C1_6": null, + "CLK_PMV_NE4C2_0": null, + "CLK_PMV_NE4C2_1": null, + "CLK_PMV_NE4C2_2": null, + "CLK_PMV_NE4C2_3": null, + "CLK_PMV_NE4C2_4": null, + "CLK_PMV_NE4C2_5": null, + "CLK_PMV_NE4C2_6": null, + "CLK_PMV_NE4C3_0": null, + "CLK_PMV_NE4C3_1": null, + "CLK_PMV_NE4C3_2": null, + "CLK_PMV_NE4C3_3": null, + "CLK_PMV_NE4C3_4": null, + "CLK_PMV_NE4C3_5": null, + "CLK_PMV_NE4C3_6": null, + "CLK_PMV_NW2A0_0": null, + "CLK_PMV_NW2A0_1": null, + "CLK_PMV_NW2A0_2": null, + "CLK_PMV_NW2A0_3": null, + "CLK_PMV_NW2A0_4": null, + "CLK_PMV_NW2A0_5": null, + "CLK_PMV_NW2A0_6": null, + "CLK_PMV_NW2A1_0": null, + "CLK_PMV_NW2A1_1": null, + "CLK_PMV_NW2A1_2": null, + "CLK_PMV_NW2A1_3": null, + "CLK_PMV_NW2A1_4": null, + "CLK_PMV_NW2A1_5": null, + "CLK_PMV_NW2A1_6": null, + "CLK_PMV_NW2A2_0": null, + "CLK_PMV_NW2A2_1": null, + "CLK_PMV_NW2A2_2": null, + "CLK_PMV_NW2A2_3": null, + "CLK_PMV_NW2A2_4": null, + "CLK_PMV_NW2A2_5": null, + "CLK_PMV_NW2A2_6": null, + "CLK_PMV_NW2A3_0": null, + "CLK_PMV_NW2A3_1": null, + "CLK_PMV_NW2A3_2": null, + "CLK_PMV_NW2A3_3": null, + "CLK_PMV_NW2A3_4": null, + "CLK_PMV_NW2A3_5": null, + "CLK_PMV_NW2A3_6": null, + "CLK_PMV_NW4A0_0": null, + "CLK_PMV_NW4A0_1": null, + "CLK_PMV_NW4A0_2": null, + "CLK_PMV_NW4A0_3": null, + "CLK_PMV_NW4A0_4": null, + "CLK_PMV_NW4A0_5": null, + "CLK_PMV_NW4A0_6": null, + "CLK_PMV_NW4A1_0": null, + "CLK_PMV_NW4A1_1": null, + "CLK_PMV_NW4A1_2": null, + "CLK_PMV_NW4A1_3": null, + "CLK_PMV_NW4A1_4": null, + "CLK_PMV_NW4A1_5": null, + "CLK_PMV_NW4A1_6": null, + "CLK_PMV_NW4A2_0": null, + "CLK_PMV_NW4A2_1": null, + "CLK_PMV_NW4A2_2": null, + "CLK_PMV_NW4A2_3": null, + "CLK_PMV_NW4A2_4": null, + "CLK_PMV_NW4A2_5": null, + "CLK_PMV_NW4A2_6": null, + "CLK_PMV_NW4A3_0": null, + "CLK_PMV_NW4A3_1": null, + "CLK_PMV_NW4A3_2": null, + "CLK_PMV_NW4A3_3": null, + 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"CLK_PMV_R_CK_BUFG_CASC1": null, + "CLK_PMV_R_CK_BUFG_CASC10": null, + "CLK_PMV_R_CK_BUFG_CASC11": null, + "CLK_PMV_R_CK_BUFG_CASC12": null, + "CLK_PMV_R_CK_BUFG_CASC13": null, + "CLK_PMV_R_CK_BUFG_CASC14": null, + "CLK_PMV_R_CK_BUFG_CASC15": null, + "CLK_PMV_R_CK_BUFG_CASC16": null, + "CLK_PMV_R_CK_BUFG_CASC17": null, + "CLK_PMV_R_CK_BUFG_CASC18": null, + "CLK_PMV_R_CK_BUFG_CASC19": null, + "CLK_PMV_R_CK_BUFG_CASC2": null, + "CLK_PMV_R_CK_BUFG_CASC20": null, + "CLK_PMV_R_CK_BUFG_CASC21": null, + "CLK_PMV_R_CK_BUFG_CASC22": null, + "CLK_PMV_R_CK_BUFG_CASC23": null, + "CLK_PMV_R_CK_BUFG_CASC24": null, + "CLK_PMV_R_CK_BUFG_CASC25": null, + "CLK_PMV_R_CK_BUFG_CASC26": null, + "CLK_PMV_R_CK_BUFG_CASC27": null, + "CLK_PMV_R_CK_BUFG_CASC28": null, + "CLK_PMV_R_CK_BUFG_CASC29": null, + "CLK_PMV_R_CK_BUFG_CASC3": null, + "CLK_PMV_R_CK_BUFG_CASC30": null, + "CLK_PMV_R_CK_BUFG_CASC31": null, + "CLK_PMV_R_CK_BUFG_CASC4": null, + "CLK_PMV_R_CK_BUFG_CASC5": null, + "CLK_PMV_R_CK_BUFG_CASC6": null, + "CLK_PMV_R_CK_BUFG_CASC7": null, + "CLK_PMV_R_CK_BUFG_CASC8": null, + "CLK_PMV_R_CK_BUFG_CASC9": null, + "CLK_PMV_R_CK_GCLK0": null, + "CLK_PMV_R_CK_GCLK1": null, + "CLK_PMV_R_CK_GCLK10": null, + "CLK_PMV_R_CK_GCLK11": null, + "CLK_PMV_R_CK_GCLK12": null, + "CLK_PMV_R_CK_GCLK13": null, + "CLK_PMV_R_CK_GCLK14": null, + "CLK_PMV_R_CK_GCLK15": null, + "CLK_PMV_R_CK_GCLK16": null, + "CLK_PMV_R_CK_GCLK17": null, + "CLK_PMV_R_CK_GCLK18": null, + "CLK_PMV_R_CK_GCLK19": null, + "CLK_PMV_R_CK_GCLK2": null, + "CLK_PMV_R_CK_GCLK20": null, + "CLK_PMV_R_CK_GCLK21": null, + "CLK_PMV_R_CK_GCLK22": null, + "CLK_PMV_R_CK_GCLK23": null, + "CLK_PMV_R_CK_GCLK24": null, + "CLK_PMV_R_CK_GCLK25": null, + "CLK_PMV_R_CK_GCLK26": null, + "CLK_PMV_R_CK_GCLK27": null, + "CLK_PMV_R_CK_GCLK28": null, + "CLK_PMV_R_CK_GCLK29": null, + "CLK_PMV_R_CK_GCLK3": null, + "CLK_PMV_R_CK_GCLK30": null, + "CLK_PMV_R_CK_GCLK31": null, + "CLK_PMV_R_CK_GCLK4": null, + "CLK_PMV_R_CK_GCLK5": null, + "CLK_PMV_R_CK_GCLK6": null, + "CLK_PMV_R_CK_GCLK7": null, + "CLK_PMV_R_CK_GCLK8": null, + "CLK_PMV_R_CK_GCLK9": null, + "CLK_PMV_SE2A0_0": null, + "CLK_PMV_SE2A0_1": null, + "CLK_PMV_SE2A0_2": null, + "CLK_PMV_SE2A0_3": null, + "CLK_PMV_SE2A0_4": null, + "CLK_PMV_SE2A0_5": null, + "CLK_PMV_SE2A0_6": null, + "CLK_PMV_SE2A1_0": null, + "CLK_PMV_SE2A1_1": null, + "CLK_PMV_SE2A1_2": null, + "CLK_PMV_SE2A1_3": null, + "CLK_PMV_SE2A1_4": null, + "CLK_PMV_SE2A1_5": null, + "CLK_PMV_SE2A1_6": null, + "CLK_PMV_SE2A2_0": null, + "CLK_PMV_SE2A2_1": null, + "CLK_PMV_SE2A2_2": null, + "CLK_PMV_SE2A2_3": null, + "CLK_PMV_SE2A2_4": null, + "CLK_PMV_SE2A2_5": null, + "CLK_PMV_SE2A2_6": null, + "CLK_PMV_SE2A3_0": null, + "CLK_PMV_SE2A3_1": null, + "CLK_PMV_SE2A3_2": null, + "CLK_PMV_SE2A3_3": null, + "CLK_PMV_SE2A3_4": null, + "CLK_PMV_SE2A3_5": null, + "CLK_PMV_SE2A3_6": null, + "CLK_PMV_SE4BEG0_0": null, + "CLK_PMV_SE4BEG0_1": null, + "CLK_PMV_SE4BEG0_2": null, + "CLK_PMV_SE4BEG0_3": null, + "CLK_PMV_SE4BEG0_4": null, + "CLK_PMV_SE4BEG0_5": null, + "CLK_PMV_SE4BEG0_6": null, + "CLK_PMV_SE4BEG1_0": null, + "CLK_PMV_SE4BEG1_1": null, + "CLK_PMV_SE4BEG1_2": null, + "CLK_PMV_SE4BEG1_3": null, + "CLK_PMV_SE4BEG1_4": null, + "CLK_PMV_SE4BEG1_5": null, + "CLK_PMV_SE4BEG1_6": null, + "CLK_PMV_SE4BEG2_0": null, + "CLK_PMV_SE4BEG2_1": null, + "CLK_PMV_SE4BEG2_2": null, + "CLK_PMV_SE4BEG2_3": null, + "CLK_PMV_SE4BEG2_4": null, + "CLK_PMV_SE4BEG2_5": null, + "CLK_PMV_SE4BEG2_6": null, + "CLK_PMV_SE4BEG3_0": null, + "CLK_PMV_SE4BEG3_1": null, + "CLK_PMV_SE4BEG3_2": null, + "CLK_PMV_SE4BEG3_3": null, + "CLK_PMV_SE4BEG3_4": null, + "CLK_PMV_SE4BEG3_5": null, + "CLK_PMV_SE4BEG3_6": null, + "CLK_PMV_SE4C0_0": null, + "CLK_PMV_SE4C0_1": null, + "CLK_PMV_SE4C0_2": null, + "CLK_PMV_SE4C0_3": null, + "CLK_PMV_SE4C0_4": null, + "CLK_PMV_SE4C0_5": null, + "CLK_PMV_SE4C0_6": null, + "CLK_PMV_SE4C1_0": null, + "CLK_PMV_SE4C1_1": null, + "CLK_PMV_SE4C1_2": null, + "CLK_PMV_SE4C1_3": null, + "CLK_PMV_SE4C1_4": null, + "CLK_PMV_SE4C1_5": null, + "CLK_PMV_SE4C1_6": null, + "CLK_PMV_SE4C2_0": null, + "CLK_PMV_SE4C2_1": null, + "CLK_PMV_SE4C2_2": null, + "CLK_PMV_SE4C2_3": null, + "CLK_PMV_SE4C2_4": null, + "CLK_PMV_SE4C2_5": null, + "CLK_PMV_SE4C2_6": null, + "CLK_PMV_SE4C3_0": null, + "CLK_PMV_SE4C3_1": null, + "CLK_PMV_SE4C3_2": null, + "CLK_PMV_SE4C3_3": null, + "CLK_PMV_SE4C3_4": null, + "CLK_PMV_SE4C3_5": null, + "CLK_PMV_SE4C3_6": null, + "CLK_PMV_SW2A0_0": null, + "CLK_PMV_SW2A0_1": null, + "CLK_PMV_SW2A0_2": null, + "CLK_PMV_SW2A0_3": null, + "CLK_PMV_SW2A0_4": null, + "CLK_PMV_SW2A0_5": null, + "CLK_PMV_SW2A0_6": null, + "CLK_PMV_SW2A1_0": null, + "CLK_PMV_SW2A1_1": null, + "CLK_PMV_SW2A1_2": null, + "CLK_PMV_SW2A1_3": null, + "CLK_PMV_SW2A1_4": null, + "CLK_PMV_SW2A1_5": null, + "CLK_PMV_SW2A1_6": null, + "CLK_PMV_SW2A2_0": null, + "CLK_PMV_SW2A2_1": null, + "CLK_PMV_SW2A2_2": null, + "CLK_PMV_SW2A2_3": null, + "CLK_PMV_SW2A2_4": null, + "CLK_PMV_SW2A2_5": null, + "CLK_PMV_SW2A2_6": null, + "CLK_PMV_SW2A3_0": null, + "CLK_PMV_SW2A3_1": null, + "CLK_PMV_SW2A3_2": null, + "CLK_PMV_SW2A3_3": null, + "CLK_PMV_SW2A3_4": null, + "CLK_PMV_SW2A3_5": null, + "CLK_PMV_SW2A3_6": null, + "CLK_PMV_SW4A0_0": null, + "CLK_PMV_SW4A0_1": null, + "CLK_PMV_SW4A0_2": null, + "CLK_PMV_SW4A0_3": null, + "CLK_PMV_SW4A0_4": null, + "CLK_PMV_SW4A0_5": null, + "CLK_PMV_SW4A0_6": null, + "CLK_PMV_SW4A1_0": null, + "CLK_PMV_SW4A1_1": null, + "CLK_PMV_SW4A1_2": null, + "CLK_PMV_SW4A1_3": null, + "CLK_PMV_SW4A1_4": null, + "CLK_PMV_SW4A1_5": null, + "CLK_PMV_SW4A1_6": null, + "CLK_PMV_SW4A2_0": null, + "CLK_PMV_SW4A2_1": null, + "CLK_PMV_SW4A2_2": null, + "CLK_PMV_SW4A2_3": null, + "CLK_PMV_SW4A2_4": null, + "CLK_PMV_SW4A2_5": null, + "CLK_PMV_SW4A2_6": null, + "CLK_PMV_SW4A3_0": null, + "CLK_PMV_SW4A3_1": null, + "CLK_PMV_SW4A3_2": null, + "CLK_PMV_SW4A3_3": null, + "CLK_PMV_SW4A3_4": null, + "CLK_PMV_SW4A3_5": null, + "CLK_PMV_SW4A3_6": null, + "CLK_PMV_SW4END0_0": null, + "CLK_PMV_SW4END0_1": null, + "CLK_PMV_SW4END0_2": null, + "CLK_PMV_SW4END0_3": null, + "CLK_PMV_SW4END0_4": null, + "CLK_PMV_SW4END0_5": null, + "CLK_PMV_SW4END0_6": null, + "CLK_PMV_SW4END1_0": null, + "CLK_PMV_SW4END1_1": null, + "CLK_PMV_SW4END1_2": null, + "CLK_PMV_SW4END1_3": null, + "CLK_PMV_SW4END1_4": null, + "CLK_PMV_SW4END1_5": null, + "CLK_PMV_SW4END1_6": null, + "CLK_PMV_SW4END2_0": null, + "CLK_PMV_SW4END2_1": null, + "CLK_PMV_SW4END2_2": null, + "CLK_PMV_SW4END2_3": null, + "CLK_PMV_SW4END2_4": null, + "CLK_PMV_SW4END2_5": null, + "CLK_PMV_SW4END2_6": null, + "CLK_PMV_SW4END3_0": null, + "CLK_PMV_SW4END3_1": null, + "CLK_PMV_SW4END3_2": null, + "CLK_PMV_SW4END3_3": null, + "CLK_PMV_SW4END3_4": null, + "CLK_PMV_SW4END3_5": null, + "CLK_PMV_SW4END3_6": null, + "CLK_PMV_WL1END0_0": null, + "CLK_PMV_WL1END0_1": null, + "CLK_PMV_WL1END0_2": null, + "CLK_PMV_WL1END0_3": null, + "CLK_PMV_WL1END0_4": null, + "CLK_PMV_WL1END0_5": null, + "CLK_PMV_WL1END0_6": null, + "CLK_PMV_WL1END1_0": null, + "CLK_PMV_WL1END1_1": null, + "CLK_PMV_WL1END1_2": null, + "CLK_PMV_WL1END1_3": null, + "CLK_PMV_WL1END1_4": null, + "CLK_PMV_WL1END1_5": null, + "CLK_PMV_WL1END1_6": null, + "CLK_PMV_WL1END2_0": null, + "CLK_PMV_WL1END2_1": null, + "CLK_PMV_WL1END2_2": null, + "CLK_PMV_WL1END2_3": null, + "CLK_PMV_WL1END2_4": null, + "CLK_PMV_WL1END2_5": null, + "CLK_PMV_WL1END2_6": null, + "CLK_PMV_WL1END3_0": null, + "CLK_PMV_WL1END3_1": null, + "CLK_PMV_WL1END3_2": null, + "CLK_PMV_WL1END3_3": null, + "CLK_PMV_WL1END3_4": null, + "CLK_PMV_WL1END3_5": null, + "CLK_PMV_WL1END3_6": null, + "CLK_PMV_WR1END0_0": null, + "CLK_PMV_WR1END0_1": null, + "CLK_PMV_WR1END0_2": null, + "CLK_PMV_WR1END0_3": null, + "CLK_PMV_WR1END0_4": null, + "CLK_PMV_WR1END0_5": null, + "CLK_PMV_WR1END0_6": null, + "CLK_PMV_WR1END1_0": null, + "CLK_PMV_WR1END1_1": null, + "CLK_PMV_WR1END1_2": null, + "CLK_PMV_WR1END1_3": null, + "CLK_PMV_WR1END1_4": null, + "CLK_PMV_WR1END1_5": null, + "CLK_PMV_WR1END1_6": null, + "CLK_PMV_WR1END2_0": null, + "CLK_PMV_WR1END2_1": null, + "CLK_PMV_WR1END2_2": null, + "CLK_PMV_WR1END2_3": null, + "CLK_PMV_WR1END2_4": null, + "CLK_PMV_WR1END2_5": null, + "CLK_PMV_WR1END2_6": null, + "CLK_PMV_WR1END3_0": null, + "CLK_PMV_WR1END3_1": null, + "CLK_PMV_WR1END3_2": null, + "CLK_PMV_WR1END3_3": null, + "CLK_PMV_WR1END3_4": null, + "CLK_PMV_WR1END3_5": null, + "CLK_PMV_WR1END3_6": null, + "CLK_PMV_WW2A0_0": null, + "CLK_PMV_WW2A0_1": null, + "CLK_PMV_WW2A0_2": null, + "CLK_PMV_WW2A0_3": null, + "CLK_PMV_WW2A0_4": null, + "CLK_PMV_WW2A0_5": null, + "CLK_PMV_WW2A0_6": null, + "CLK_PMV_WW2A1_0": null, + "CLK_PMV_WW2A1_1": null, + "CLK_PMV_WW2A1_2": null, + "CLK_PMV_WW2A1_3": null, + "CLK_PMV_WW2A1_4": null, + "CLK_PMV_WW2A1_5": null, + "CLK_PMV_WW2A1_6": null, + "CLK_PMV_WW2A2_0": null, + "CLK_PMV_WW2A2_1": null, + "CLK_PMV_WW2A2_2": null, + "CLK_PMV_WW2A2_3": null, + "CLK_PMV_WW2A2_4": null, + "CLK_PMV_WW2A2_5": null, + "CLK_PMV_WW2A2_6": null, + "CLK_PMV_WW2A3_0": null, + "CLK_PMV_WW2A3_1": null, + "CLK_PMV_WW2A3_2": null, + "CLK_PMV_WW2A3_3": null, + "CLK_PMV_WW2A3_4": null, + "CLK_PMV_WW2A3_5": null, + "CLK_PMV_WW2A3_6": null, + "CLK_PMV_WW2END0_0": null, + "CLK_PMV_WW2END0_1": null, + "CLK_PMV_WW2END0_2": null, + "CLK_PMV_WW2END0_3": null, + "CLK_PMV_WW2END0_4": null, + "CLK_PMV_WW2END0_5": null, + "CLK_PMV_WW2END0_6": null, + "CLK_PMV_WW2END1_0": null, + "CLK_PMV_WW2END1_1": null, + "CLK_PMV_WW2END1_2": null, + "CLK_PMV_WW2END1_3": null, + "CLK_PMV_WW2END1_4": null, + "CLK_PMV_WW2END1_5": null, + "CLK_PMV_WW2END1_6": null, + "CLK_PMV_WW2END2_0": null, + "CLK_PMV_WW2END2_1": null, + "CLK_PMV_WW2END2_2": null, + "CLK_PMV_WW2END2_3": null, + "CLK_PMV_WW2END2_4": null, + "CLK_PMV_WW2END2_5": null, + "CLK_PMV_WW2END2_6": null, + "CLK_PMV_WW2END3_0": null, + "CLK_PMV_WW2END3_1": null, + "CLK_PMV_WW2END3_2": null, + "CLK_PMV_WW2END3_3": null, + "CLK_PMV_WW2END3_4": null, + "CLK_PMV_WW2END3_5": null, + "CLK_PMV_WW2END3_6": null, + "CLK_PMV_WW4A0_0": null, + "CLK_PMV_WW4A0_1": null, + "CLK_PMV_WW4A0_2": null, + "CLK_PMV_WW4A0_3": null, + "CLK_PMV_WW4A0_4": null, + "CLK_PMV_WW4A0_5": null, + "CLK_PMV_WW4A0_6": null, + "CLK_PMV_WW4A1_0": null, + "CLK_PMV_WW4A1_1": null, + "CLK_PMV_WW4A1_2": null, + "CLK_PMV_WW4A1_3": null, + "CLK_PMV_WW4A1_4": null, + "CLK_PMV_WW4A1_5": null, + "CLK_PMV_WW4A1_6": null, + "CLK_PMV_WW4A2_0": null, + "CLK_PMV_WW4A2_1": null, + "CLK_PMV_WW4A2_2": null, + "CLK_PMV_WW4A2_3": null, + "CLK_PMV_WW4A2_4": null, + "CLK_PMV_WW4A2_5": null, + "CLK_PMV_WW4A2_6": null, + "CLK_PMV_WW4A3_0": null, + "CLK_PMV_WW4A3_1": null, + "CLK_PMV_WW4A3_2": null, + "CLK_PMV_WW4A3_3": null, + "CLK_PMV_WW4A3_4": null, + "CLK_PMV_WW4A3_5": null, + "CLK_PMV_WW4A3_6": null, + "CLK_PMV_WW4B0_0": null, + "CLK_PMV_WW4B0_1": null, + "CLK_PMV_WW4B0_2": null, + "CLK_PMV_WW4B0_3": null, + "CLK_PMV_WW4B0_4": null, + "CLK_PMV_WW4B0_5": null, + "CLK_PMV_WW4B0_6": null, + "CLK_PMV_WW4B1_0": null, + "CLK_PMV_WW4B1_1": null, + "CLK_PMV_WW4B1_2": null, + "CLK_PMV_WW4B1_3": null, + "CLK_PMV_WW4B1_4": null, + "CLK_PMV_WW4B1_5": null, + "CLK_PMV_WW4B1_6": null, + "CLK_PMV_WW4B2_0": null, + "CLK_PMV_WW4B2_1": null, + "CLK_PMV_WW4B2_2": null, + "CLK_PMV_WW4B2_3": null, + "CLK_PMV_WW4B2_4": null, + "CLK_PMV_WW4B2_5": null, + "CLK_PMV_WW4B2_6": null, + "CLK_PMV_WW4B3_0": null, + "CLK_PMV_WW4B3_1": null, + "CLK_PMV_WW4B3_2": null, + "CLK_PMV_WW4B3_3": null, + "CLK_PMV_WW4B3_4": null, + "CLK_PMV_WW4B3_5": null, + "CLK_PMV_WW4B3_6": null, + "CLK_PMV_WW4C0_0": null, + "CLK_PMV_WW4C0_1": null, + "CLK_PMV_WW4C0_2": null, + "CLK_PMV_WW4C0_3": null, + "CLK_PMV_WW4C0_4": null, + "CLK_PMV_WW4C0_5": null, + "CLK_PMV_WW4C0_6": null, + "CLK_PMV_WW4C1_0": null, + "CLK_PMV_WW4C1_1": null, + "CLK_PMV_WW4C1_2": null, + "CLK_PMV_WW4C1_3": null, + "CLK_PMV_WW4C1_4": null, + "CLK_PMV_WW4C1_5": null, + "CLK_PMV_WW4C1_6": null, + "CLK_PMV_WW4C2_0": null, + "CLK_PMV_WW4C2_1": null, + "CLK_PMV_WW4C2_2": null, + "CLK_PMV_WW4C2_3": null, + "CLK_PMV_WW4C2_4": null, + "CLK_PMV_WW4C2_5": null, + "CLK_PMV_WW4C2_6": null, + "CLK_PMV_WW4C3_0": null, + "CLK_PMV_WW4C3_1": null, + "CLK_PMV_WW4C3_2": null, + "CLK_PMV_WW4C3_3": null, + "CLK_PMV_WW4C3_4": null, + "CLK_PMV_WW4C3_5": null, + "CLK_PMV_WW4C3_6": null, + "CLK_PMV_WW4END0_0": null, + "CLK_PMV_WW4END0_1": null, + "CLK_PMV_WW4END0_2": null, + "CLK_PMV_WW4END0_3": null, + "CLK_PMV_WW4END0_4": null, + "CLK_PMV_WW4END0_5": null, + "CLK_PMV_WW4END0_6": null, + "CLK_PMV_WW4END1_0": null, + "CLK_PMV_WW4END1_1": null, + "CLK_PMV_WW4END1_2": null, + "CLK_PMV_WW4END1_3": null, + "CLK_PMV_WW4END1_4": null, + "CLK_PMV_WW4END1_5": null, + "CLK_PMV_WW4END1_6": null, + "CLK_PMV_WW4END2_0": null, + "CLK_PMV_WW4END2_1": null, + "CLK_PMV_WW4END2_2": null, + "CLK_PMV_WW4END2_3": null, + "CLK_PMV_WW4END2_4": null, + "CLK_PMV_WW4END2_5": null, + "CLK_PMV_WW4END2_6": null, + "CLK_PMV_WW4END3_0": null, + "CLK_PMV_WW4END3_1": null, + "CLK_PMV_WW4END3_2": null, + "CLK_PMV_WW4END3_3": null, + "CLK_PMV_WW4END3_4": null, + "CLK_PMV_WW4END3_5": null, + "CLK_PMV_WW4END3_6": null + } } diff --git a/kintex7/tile_type_CLK_PMV2.json b/kintex7/tile_type_CLK_PMV2.json index 71957cc..db16457 100644 --- a/kintex7/tile_type_CLK_PMV2.json +++ b/kintex7/tile_type_CLK_PMV2.json @@ -5,13 +5,76 @@ "name": "X0Y0", "prefix": "PMV", "site_pins": { - "A0": "CLK_PMV2_A0", - "A1": "CLK_PMV2_A1", - "A2": "CLK_PMV2_A2", - "EN": "CLK_PMV2_EN", - "O": "CLK_PMV2_O", - "ODIV2": "CLK_PMV2_ODIV2", - "ODIV4": "CLK_PMV2_ODIV4" + "A0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_PMV2_A0" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_PMV2_A1" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_PMV2_A2" + }, + "EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CLK_PMV2_EN" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_PMV2_O" + }, + "ODIV2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_PMV2_ODIV2" + }, + "ODIV4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CLK_PMV2_ODIV4" + } }, "type": "PMV2", "x_coord": 0, @@ -19,359 +82,359 @@ } ], "tile_type": "CLK_PMV2", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3", - "CLK_PMV2_A0", - "CLK_PMV2_A1", - "CLK_PMV2_A2", - "CLK_PMV2_EN", - "CLK_PMV2_O", - "CLK_PMV2_ODIV2", - "CLK_PMV2_ODIV4", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP7_0", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK1_0", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX9_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS9_0" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null, + "CLK_PMV2_A0": null, + "CLK_PMV2_A1": null, + "CLK_PMV2_A2": null, + "CLK_PMV2_EN": null, + "CLK_PMV2_O": null, + "CLK_PMV2_ODIV2": null, + "CLK_PMV2_ODIV4": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_CLK0_0": null, + "CLK_PMV_CLK1_0": null, + "CLK_PMV_CTRL0_0": null, + "CLK_PMV_CTRL1_0": null, + "CLK_PMV_FAN0_0": null, + "CLK_PMV_FAN1_0": null, + "CLK_PMV_FAN2_0": null, + "CLK_PMV_FAN3_0": null, + "CLK_PMV_FAN4_0": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX17_0": null, + "CLK_PMV_IMUX18_0": null, + "CLK_PMV_IMUX19_0": null, + "CLK_PMV_IMUX1_0": null, + "CLK_PMV_IMUX20_0": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_LOGIC_OUTS0_0": null, + "CLK_PMV_LOGIC_OUTS10_0": null, + "CLK_PMV_LOGIC_OUTS11_0": null, + "CLK_PMV_LOGIC_OUTS12_0": null, + "CLK_PMV_LOGIC_OUTS13_0": null, + "CLK_PMV_LOGIC_OUTS14_0": null, + "CLK_PMV_LOGIC_OUTS15_0": null, + "CLK_PMV_LOGIC_OUTS16_0": null, + "CLK_PMV_LOGIC_OUTS17_0": null, + "CLK_PMV_LOGIC_OUTS18_0": null, + "CLK_PMV_LOGIC_OUTS19_0": null, + "CLK_PMV_LOGIC_OUTS1_0": null, + "CLK_PMV_LOGIC_OUTS20_0": null, + "CLK_PMV_LOGIC_OUTS21_0": null, + "CLK_PMV_LOGIC_OUTS22_0": null, + "CLK_PMV_LOGIC_OUTS23_0": null, + "CLK_PMV_LOGIC_OUTS2_0": null, + "CLK_PMV_LOGIC_OUTS3_0": null, + "CLK_PMV_LOGIC_OUTS4_0": null, + "CLK_PMV_LOGIC_OUTS5_0": null, + "CLK_PMV_LOGIC_OUTS6_0": null, + "CLK_PMV_LOGIC_OUTS7_0": null, + "CLK_PMV_LOGIC_OUTS8_0": null, + "CLK_PMV_LOGIC_OUTS9_0": null + } } diff --git a/kintex7/tile_type_CLK_PMV2_SVT.json b/kintex7/tile_type_CLK_PMV2_SVT.json index cc63563..ab9442d 100644 --- a/kintex7/tile_type_CLK_PMV2_SVT.json +++ b/kintex7/tile_type_CLK_PMV2_SVT.json @@ -2,359 +2,359 @@ "pips": {}, "sites": [], "tile_type": "CLK_PMV2_SVT", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3", - "CLK_PMV2_A0", - "CLK_PMV2_A1", - "CLK_PMV2_A2", - "CLK_PMV2_EN", - "CLK_PMV2_O", - "CLK_PMV2_ODIV2", - "CLK_PMV2_ODIV4", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP7_0", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK1_0", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX9_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS9_0" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null, + "CLK_PMV2_A0": null, + "CLK_PMV2_A1": null, + "CLK_PMV2_A2": null, + "CLK_PMV2_EN": null, + "CLK_PMV2_O": null, + "CLK_PMV2_ODIV2": null, + "CLK_PMV2_ODIV4": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_CLK0_0": null, + "CLK_PMV_CLK1_0": null, + "CLK_PMV_CTRL0_0": null, + "CLK_PMV_CTRL1_0": null, + "CLK_PMV_FAN0_0": null, + "CLK_PMV_FAN1_0": null, + "CLK_PMV_FAN2_0": null, + "CLK_PMV_FAN3_0": null, + "CLK_PMV_FAN4_0": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX17_0": null, + "CLK_PMV_IMUX18_0": null, + "CLK_PMV_IMUX19_0": null, + "CLK_PMV_IMUX1_0": null, + "CLK_PMV_IMUX20_0": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_LOGIC_OUTS0_0": null, + "CLK_PMV_LOGIC_OUTS10_0": null, + "CLK_PMV_LOGIC_OUTS11_0": null, + "CLK_PMV_LOGIC_OUTS12_0": null, + "CLK_PMV_LOGIC_OUTS13_0": null, + "CLK_PMV_LOGIC_OUTS14_0": null, + "CLK_PMV_LOGIC_OUTS15_0": null, + "CLK_PMV_LOGIC_OUTS16_0": null, + "CLK_PMV_LOGIC_OUTS17_0": null, + "CLK_PMV_LOGIC_OUTS18_0": null, + "CLK_PMV_LOGIC_OUTS19_0": null, + "CLK_PMV_LOGIC_OUTS1_0": null, + "CLK_PMV_LOGIC_OUTS20_0": null, + "CLK_PMV_LOGIC_OUTS21_0": null, + "CLK_PMV_LOGIC_OUTS22_0": null, + "CLK_PMV_LOGIC_OUTS23_0": null, + "CLK_PMV_LOGIC_OUTS2_0": null, + "CLK_PMV_LOGIC_OUTS3_0": null, + "CLK_PMV_LOGIC_OUTS4_0": null, + "CLK_PMV_LOGIC_OUTS5_0": null, + "CLK_PMV_LOGIC_OUTS6_0": null, + "CLK_PMV_LOGIC_OUTS7_0": null, + "CLK_PMV_LOGIC_OUTS8_0": null, + "CLK_PMV_LOGIC_OUTS9_0": null + } } diff --git a/kintex7/tile_type_CLK_PMVIOB.json b/kintex7/tile_type_CLK_PMVIOB.json index b51a015..2b494ef 100644 --- a/kintex7/tile_type_CLK_PMVIOB.json +++ b/kintex7/tile_type_CLK_PMVIOB.json @@ -2,358 +2,358 @@ "pips": {}, "sites": [], "tile_type": "CLK_PMVIOB", - "wires": [ - "CLK_FEED_CK_BUFG_CASC0", - "CLK_FEED_CK_BUFG_CASC1", - "CLK_FEED_CK_BUFG_CASC10", - "CLK_FEED_CK_BUFG_CASC11", - "CLK_FEED_CK_BUFG_CASC12", - "CLK_FEED_CK_BUFG_CASC13", - "CLK_FEED_CK_BUFG_CASC14", - "CLK_FEED_CK_BUFG_CASC15", - "CLK_FEED_CK_BUFG_CASC16", - "CLK_FEED_CK_BUFG_CASC17", - "CLK_FEED_CK_BUFG_CASC18", - "CLK_FEED_CK_BUFG_CASC19", - "CLK_FEED_CK_BUFG_CASC2", - "CLK_FEED_CK_BUFG_CASC20", - "CLK_FEED_CK_BUFG_CASC21", - "CLK_FEED_CK_BUFG_CASC22", - "CLK_FEED_CK_BUFG_CASC23", - "CLK_FEED_CK_BUFG_CASC24", - "CLK_FEED_CK_BUFG_CASC25", - "CLK_FEED_CK_BUFG_CASC26", - "CLK_FEED_CK_BUFG_CASC27", - "CLK_FEED_CK_BUFG_CASC28", - "CLK_FEED_CK_BUFG_CASC29", - "CLK_FEED_CK_BUFG_CASC3", - "CLK_FEED_CK_BUFG_CASC30", - "CLK_FEED_CK_BUFG_CASC31", - "CLK_FEED_CK_BUFG_CASC4", - "CLK_FEED_CK_BUFG_CASC5", - "CLK_FEED_CK_BUFG_CASC6", - "CLK_FEED_CK_BUFG_CASC7", - "CLK_FEED_CK_BUFG_CASC8", - "CLK_FEED_CK_BUFG_CASC9", - "CLK_FEED_CK_GCLK0", - "CLK_FEED_CK_GCLK1", - "CLK_FEED_CK_GCLK10", - "CLK_FEED_CK_GCLK11", - "CLK_FEED_CK_GCLK12", - "CLK_FEED_CK_GCLK13", - "CLK_FEED_CK_GCLK14", - "CLK_FEED_CK_GCLK15", - "CLK_FEED_CK_GCLK16", - "CLK_FEED_CK_GCLK17", - "CLK_FEED_CK_GCLK18", - "CLK_FEED_CK_GCLK19", - "CLK_FEED_CK_GCLK2", - "CLK_FEED_CK_GCLK20", - "CLK_FEED_CK_GCLK21", - "CLK_FEED_CK_GCLK22", - "CLK_FEED_CK_GCLK23", - "CLK_FEED_CK_GCLK24", - "CLK_FEED_CK_GCLK25", - "CLK_FEED_CK_GCLK26", - "CLK_FEED_CK_GCLK27", - "CLK_FEED_CK_GCLK28", - "CLK_FEED_CK_GCLK29", - "CLK_FEED_CK_GCLK3", - "CLK_FEED_CK_GCLK30", - "CLK_FEED_CK_GCLK31", - "CLK_FEED_CK_GCLK4", - "CLK_FEED_CK_GCLK5", - "CLK_FEED_CK_GCLK6", - "CLK_FEED_CK_GCLK7", - "CLK_FEED_CK_GCLK8", - "CLK_FEED_CK_GCLK9", - "CLK_FEED_EE2A0", - "CLK_FEED_EE2A1", - "CLK_FEED_EE2A2", - "CLK_FEED_EE2A3", - "CLK_FEED_EE2BEG0", - "CLK_FEED_EE2BEG1", - "CLK_FEED_EE2BEG2", - "CLK_FEED_EE2BEG3", - "CLK_FEED_EE4A0", - "CLK_FEED_EE4A1", - "CLK_FEED_EE4A2", - "CLK_FEED_EE4A3", - "CLK_FEED_EE4B0", - "CLK_FEED_EE4B1", - "CLK_FEED_EE4B2", - "CLK_FEED_EE4B3", - "CLK_FEED_EE4BEG0", - "CLK_FEED_EE4BEG1", - "CLK_FEED_EE4BEG2", - "CLK_FEED_EE4BEG3", - "CLK_FEED_EE4C0", - "CLK_FEED_EE4C1", - "CLK_FEED_EE4C2", - "CLK_FEED_EE4C3", - "CLK_FEED_EL1BEG0", - "CLK_FEED_EL1BEG1", - "CLK_FEED_EL1BEG2", - "CLK_FEED_EL1BEG3", - "CLK_FEED_ER1BEG0", - "CLK_FEED_ER1BEG1", - "CLK_FEED_ER1BEG2", - "CLK_FEED_ER1BEG3", - "CLK_FEED_LH1", - "CLK_FEED_LH10", - "CLK_FEED_LH11", - "CLK_FEED_LH12", - "CLK_FEED_LH2", - "CLK_FEED_LH3", - "CLK_FEED_LH4", - "CLK_FEED_LH5", - "CLK_FEED_LH6", - "CLK_FEED_LH7", - "CLK_FEED_LH8", - "CLK_FEED_LH9", - "CLK_FEED_MONITOR_N", - "CLK_FEED_MONITOR_P", - "CLK_FEED_NE2A0", - "CLK_FEED_NE2A1", - "CLK_FEED_NE2A2", - "CLK_FEED_NE2A3", - "CLK_FEED_NE4BEG0", - "CLK_FEED_NE4BEG1", - "CLK_FEED_NE4BEG2", - "CLK_FEED_NE4BEG3", - "CLK_FEED_NE4C0", - "CLK_FEED_NE4C1", - "CLK_FEED_NE4C2", - "CLK_FEED_NE4C3", - "CLK_FEED_NW2A0", - "CLK_FEED_NW2A1", - "CLK_FEED_NW2A2", - "CLK_FEED_NW2A3", - "CLK_FEED_NW4A0", - "CLK_FEED_NW4A1", - "CLK_FEED_NW4A2", - "CLK_FEED_NW4A3", - "CLK_FEED_NW4END0", - "CLK_FEED_NW4END1", - "CLK_FEED_NW4END2", - "CLK_FEED_NW4END3", - "CLK_FEED_R_CK_BUFG_CASC0", - "CLK_FEED_R_CK_BUFG_CASC1", - "CLK_FEED_R_CK_BUFG_CASC10", - "CLK_FEED_R_CK_BUFG_CASC11", - "CLK_FEED_R_CK_BUFG_CASC12", - "CLK_FEED_R_CK_BUFG_CASC13", - "CLK_FEED_R_CK_BUFG_CASC14", - "CLK_FEED_R_CK_BUFG_CASC15", - "CLK_FEED_R_CK_BUFG_CASC16", - "CLK_FEED_R_CK_BUFG_CASC17", - "CLK_FEED_R_CK_BUFG_CASC18", - "CLK_FEED_R_CK_BUFG_CASC19", - "CLK_FEED_R_CK_BUFG_CASC2", - "CLK_FEED_R_CK_BUFG_CASC20", - "CLK_FEED_R_CK_BUFG_CASC21", - "CLK_FEED_R_CK_BUFG_CASC22", - "CLK_FEED_R_CK_BUFG_CASC23", - "CLK_FEED_R_CK_BUFG_CASC24", - "CLK_FEED_R_CK_BUFG_CASC25", - "CLK_FEED_R_CK_BUFG_CASC26", - "CLK_FEED_R_CK_BUFG_CASC27", - "CLK_FEED_R_CK_BUFG_CASC28", - "CLK_FEED_R_CK_BUFG_CASC29", - "CLK_FEED_R_CK_BUFG_CASC3", - "CLK_FEED_R_CK_BUFG_CASC30", - "CLK_FEED_R_CK_BUFG_CASC31", - "CLK_FEED_R_CK_BUFG_CASC4", - "CLK_FEED_R_CK_BUFG_CASC5", - "CLK_FEED_R_CK_BUFG_CASC6", - "CLK_FEED_R_CK_BUFG_CASC7", - "CLK_FEED_R_CK_BUFG_CASC8", - "CLK_FEED_R_CK_BUFG_CASC9", - "CLK_FEED_R_CK_GCLK0", - "CLK_FEED_R_CK_GCLK1", - "CLK_FEED_R_CK_GCLK10", - "CLK_FEED_R_CK_GCLK11", - "CLK_FEED_R_CK_GCLK12", - "CLK_FEED_R_CK_GCLK13", - "CLK_FEED_R_CK_GCLK14", - "CLK_FEED_R_CK_GCLK15", - "CLK_FEED_R_CK_GCLK16", - "CLK_FEED_R_CK_GCLK17", - "CLK_FEED_R_CK_GCLK18", - "CLK_FEED_R_CK_GCLK19", - "CLK_FEED_R_CK_GCLK2", - "CLK_FEED_R_CK_GCLK20", - "CLK_FEED_R_CK_GCLK21", - "CLK_FEED_R_CK_GCLK22", - "CLK_FEED_R_CK_GCLK23", - "CLK_FEED_R_CK_GCLK24", - "CLK_FEED_R_CK_GCLK25", - "CLK_FEED_R_CK_GCLK26", - "CLK_FEED_R_CK_GCLK27", - "CLK_FEED_R_CK_GCLK28", - "CLK_FEED_R_CK_GCLK29", - "CLK_FEED_R_CK_GCLK3", - "CLK_FEED_R_CK_GCLK30", - "CLK_FEED_R_CK_GCLK31", - "CLK_FEED_R_CK_GCLK4", - "CLK_FEED_R_CK_GCLK5", - "CLK_FEED_R_CK_GCLK6", - "CLK_FEED_R_CK_GCLK7", - "CLK_FEED_R_CK_GCLK8", - "CLK_FEED_R_CK_GCLK9", - "CLK_FEED_SE2A0", - "CLK_FEED_SE2A1", - "CLK_FEED_SE2A2", - "CLK_FEED_SE2A3", - "CLK_FEED_SE4BEG0", - "CLK_FEED_SE4BEG1", - "CLK_FEED_SE4BEG2", - "CLK_FEED_SE4BEG3", - "CLK_FEED_SE4C0", - "CLK_FEED_SE4C1", - "CLK_FEED_SE4C2", - "CLK_FEED_SE4C3", - "CLK_FEED_SW2A0", - "CLK_FEED_SW2A1", - "CLK_FEED_SW2A2", - "CLK_FEED_SW2A3", - "CLK_FEED_SW4A0", - "CLK_FEED_SW4A1", - "CLK_FEED_SW4A2", - "CLK_FEED_SW4A3", - "CLK_FEED_SW4END0", - "CLK_FEED_SW4END1", - "CLK_FEED_SW4END2", - "CLK_FEED_SW4END3", - "CLK_FEED_WL1END0", - "CLK_FEED_WL1END1", - "CLK_FEED_WL1END2", - "CLK_FEED_WL1END3", - "CLK_FEED_WR1END0", - "CLK_FEED_WR1END1", - "CLK_FEED_WR1END2", - "CLK_FEED_WR1END3", - "CLK_FEED_WW2A0", - "CLK_FEED_WW2A1", - "CLK_FEED_WW2A2", - "CLK_FEED_WW2A3", - "CLK_FEED_WW2END0", - "CLK_FEED_WW2END1", - "CLK_FEED_WW2END2", - "CLK_FEED_WW2END3", - "CLK_FEED_WW4A0", - "CLK_FEED_WW4A1", - "CLK_FEED_WW4A2", - "CLK_FEED_WW4A3", - "CLK_FEED_WW4B0", - "CLK_FEED_WW4B1", - "CLK_FEED_WW4B2", - "CLK_FEED_WW4B3", - "CLK_FEED_WW4C0", - "CLK_FEED_WW4C1", - "CLK_FEED_WW4C2", - "CLK_FEED_WW4C3", - "CLK_FEED_WW4END0", - "CLK_FEED_WW4END1", - "CLK_FEED_WW4END2", - "CLK_FEED_WW4END3", - "CLK_PMVIOB_A0", - "CLK_PMVIOB_A1", - "CLK_PMVIOB_EN", - "CLK_PMVIOB_O", - "CLK_PMVIOB_ODIV2", - "CLK_PMVIOB_ODIV4", - "CLK_PMV_BYP0_0", - "CLK_PMV_BYP1_0", - "CLK_PMV_BYP2_0", - "CLK_PMV_BYP3_0", - "CLK_PMV_BYP4_0", - "CLK_PMV_BYP5_0", - "CLK_PMV_BYP6_0", - "CLK_PMV_BYP7_0", - "CLK_PMV_CLK0_0", - "CLK_PMV_CLK1_0", - "CLK_PMV_CTRL0_0", - "CLK_PMV_CTRL1_0", - "CLK_PMV_FAN0_0", - "CLK_PMV_FAN1_0", - "CLK_PMV_FAN2_0", - "CLK_PMV_FAN3_0", - "CLK_PMV_FAN4_0", - "CLK_PMV_FAN5_0", - "CLK_PMV_FAN6_0", - "CLK_PMV_FAN7_0", - "CLK_PMV_IMUX0_0", - "CLK_PMV_IMUX10_0", - "CLK_PMV_IMUX11_0", - "CLK_PMV_IMUX12_0", - "CLK_PMV_IMUX13_0", - "CLK_PMV_IMUX14_0", - "CLK_PMV_IMUX15_0", - "CLK_PMV_IMUX16_0", - "CLK_PMV_IMUX17_0", - "CLK_PMV_IMUX18_0", - "CLK_PMV_IMUX19_0", - "CLK_PMV_IMUX1_0", - "CLK_PMV_IMUX20_0", - "CLK_PMV_IMUX21_0", - "CLK_PMV_IMUX22_0", - "CLK_PMV_IMUX23_0", - "CLK_PMV_IMUX24_0", - "CLK_PMV_IMUX25_0", - "CLK_PMV_IMUX26_0", - "CLK_PMV_IMUX27_0", - "CLK_PMV_IMUX28_0", - "CLK_PMV_IMUX29_0", - "CLK_PMV_IMUX2_0", - "CLK_PMV_IMUX30_0", - "CLK_PMV_IMUX31_0", - "CLK_PMV_IMUX32_0", - "CLK_PMV_IMUX33_0", - "CLK_PMV_IMUX34_0", - "CLK_PMV_IMUX35_0", - "CLK_PMV_IMUX36_0", - "CLK_PMV_IMUX37_0", - "CLK_PMV_IMUX38_0", - "CLK_PMV_IMUX39_0", - "CLK_PMV_IMUX3_0", - "CLK_PMV_IMUX40_0", - "CLK_PMV_IMUX41_0", - "CLK_PMV_IMUX42_0", - "CLK_PMV_IMUX43_0", - "CLK_PMV_IMUX44_0", - "CLK_PMV_IMUX45_0", - "CLK_PMV_IMUX46_0", - "CLK_PMV_IMUX47_0", - "CLK_PMV_IMUX4_0", - "CLK_PMV_IMUX5_0", - "CLK_PMV_IMUX6_0", - "CLK_PMV_IMUX7_0", - "CLK_PMV_IMUX8_0", - "CLK_PMV_IMUX9_0", - "CLK_PMV_LOGIC_OUTS0_0", - "CLK_PMV_LOGIC_OUTS10_0", - "CLK_PMV_LOGIC_OUTS11_0", - "CLK_PMV_LOGIC_OUTS12_0", - "CLK_PMV_LOGIC_OUTS13_0", - "CLK_PMV_LOGIC_OUTS14_0", - "CLK_PMV_LOGIC_OUTS15_0", - "CLK_PMV_LOGIC_OUTS16_0", - "CLK_PMV_LOGIC_OUTS17_0", - "CLK_PMV_LOGIC_OUTS18_0", - "CLK_PMV_LOGIC_OUTS19_0", - "CLK_PMV_LOGIC_OUTS1_0", - "CLK_PMV_LOGIC_OUTS20_0", - "CLK_PMV_LOGIC_OUTS21_0", - "CLK_PMV_LOGIC_OUTS22_0", - "CLK_PMV_LOGIC_OUTS23_0", - "CLK_PMV_LOGIC_OUTS2_0", - "CLK_PMV_LOGIC_OUTS3_0", - "CLK_PMV_LOGIC_OUTS4_0", - "CLK_PMV_LOGIC_OUTS5_0", - "CLK_PMV_LOGIC_OUTS6_0", - "CLK_PMV_LOGIC_OUTS7_0", - "CLK_PMV_LOGIC_OUTS8_0", - "CLK_PMV_LOGIC_OUTS9_0" - ] + "wires": { + "CLK_FEED_CK_BUFG_CASC0": null, + "CLK_FEED_CK_BUFG_CASC1": null, + "CLK_FEED_CK_BUFG_CASC10": null, + "CLK_FEED_CK_BUFG_CASC11": null, + "CLK_FEED_CK_BUFG_CASC12": null, + "CLK_FEED_CK_BUFG_CASC13": null, + "CLK_FEED_CK_BUFG_CASC14": null, + "CLK_FEED_CK_BUFG_CASC15": null, + "CLK_FEED_CK_BUFG_CASC16": null, + "CLK_FEED_CK_BUFG_CASC17": null, + "CLK_FEED_CK_BUFG_CASC18": null, + "CLK_FEED_CK_BUFG_CASC19": null, + "CLK_FEED_CK_BUFG_CASC2": null, + "CLK_FEED_CK_BUFG_CASC20": null, + "CLK_FEED_CK_BUFG_CASC21": null, + "CLK_FEED_CK_BUFG_CASC22": null, + "CLK_FEED_CK_BUFG_CASC23": null, + "CLK_FEED_CK_BUFG_CASC24": null, + "CLK_FEED_CK_BUFG_CASC25": null, + "CLK_FEED_CK_BUFG_CASC26": null, + "CLK_FEED_CK_BUFG_CASC27": null, + "CLK_FEED_CK_BUFG_CASC28": null, + "CLK_FEED_CK_BUFG_CASC29": null, + "CLK_FEED_CK_BUFG_CASC3": null, + "CLK_FEED_CK_BUFG_CASC30": null, + "CLK_FEED_CK_BUFG_CASC31": null, + "CLK_FEED_CK_BUFG_CASC4": null, + "CLK_FEED_CK_BUFG_CASC5": null, + "CLK_FEED_CK_BUFG_CASC6": null, + "CLK_FEED_CK_BUFG_CASC7": null, + "CLK_FEED_CK_BUFG_CASC8": null, + "CLK_FEED_CK_BUFG_CASC9": null, + "CLK_FEED_CK_GCLK0": null, + "CLK_FEED_CK_GCLK1": null, + "CLK_FEED_CK_GCLK10": null, + "CLK_FEED_CK_GCLK11": null, + "CLK_FEED_CK_GCLK12": null, + "CLK_FEED_CK_GCLK13": null, + "CLK_FEED_CK_GCLK14": null, + "CLK_FEED_CK_GCLK15": null, + "CLK_FEED_CK_GCLK16": null, + "CLK_FEED_CK_GCLK17": null, + "CLK_FEED_CK_GCLK18": null, + "CLK_FEED_CK_GCLK19": null, + "CLK_FEED_CK_GCLK2": null, + "CLK_FEED_CK_GCLK20": null, + "CLK_FEED_CK_GCLK21": null, + "CLK_FEED_CK_GCLK22": null, + "CLK_FEED_CK_GCLK23": null, + "CLK_FEED_CK_GCLK24": null, + "CLK_FEED_CK_GCLK25": null, + "CLK_FEED_CK_GCLK26": null, + "CLK_FEED_CK_GCLK27": null, + "CLK_FEED_CK_GCLK28": null, + "CLK_FEED_CK_GCLK29": null, + "CLK_FEED_CK_GCLK3": null, + "CLK_FEED_CK_GCLK30": null, + "CLK_FEED_CK_GCLK31": null, + "CLK_FEED_CK_GCLK4": null, + "CLK_FEED_CK_GCLK5": null, + "CLK_FEED_CK_GCLK6": null, + "CLK_FEED_CK_GCLK7": null, + "CLK_FEED_CK_GCLK8": null, + "CLK_FEED_CK_GCLK9": null, + "CLK_FEED_EE2A0": null, + "CLK_FEED_EE2A1": null, + "CLK_FEED_EE2A2": null, + "CLK_FEED_EE2A3": null, + "CLK_FEED_EE2BEG0": null, + "CLK_FEED_EE2BEG1": null, + "CLK_FEED_EE2BEG2": null, + "CLK_FEED_EE2BEG3": null, + "CLK_FEED_EE4A0": null, + "CLK_FEED_EE4A1": null, + "CLK_FEED_EE4A2": null, + "CLK_FEED_EE4A3": null, + "CLK_FEED_EE4B0": null, + "CLK_FEED_EE4B1": null, + "CLK_FEED_EE4B2": null, + "CLK_FEED_EE4B3": null, + "CLK_FEED_EE4BEG0": null, + "CLK_FEED_EE4BEG1": null, + "CLK_FEED_EE4BEG2": null, + "CLK_FEED_EE4BEG3": null, + "CLK_FEED_EE4C0": null, + "CLK_FEED_EE4C1": null, + "CLK_FEED_EE4C2": null, + "CLK_FEED_EE4C3": null, + "CLK_FEED_EL1BEG0": null, + "CLK_FEED_EL1BEG1": null, + "CLK_FEED_EL1BEG2": null, + "CLK_FEED_EL1BEG3": null, + "CLK_FEED_ER1BEG0": null, + "CLK_FEED_ER1BEG1": null, + "CLK_FEED_ER1BEG2": null, + "CLK_FEED_ER1BEG3": null, + "CLK_FEED_LH1": null, + "CLK_FEED_LH10": null, + "CLK_FEED_LH11": null, + "CLK_FEED_LH12": null, + "CLK_FEED_LH2": null, + "CLK_FEED_LH3": null, + "CLK_FEED_LH4": null, + "CLK_FEED_LH5": null, + "CLK_FEED_LH6": null, + "CLK_FEED_LH7": null, + "CLK_FEED_LH8": null, + "CLK_FEED_LH9": null, + "CLK_FEED_MONITOR_N": null, + "CLK_FEED_MONITOR_P": null, + "CLK_FEED_NE2A0": null, + "CLK_FEED_NE2A1": null, + "CLK_FEED_NE2A2": null, + "CLK_FEED_NE2A3": null, + "CLK_FEED_NE4BEG0": null, + "CLK_FEED_NE4BEG1": null, + "CLK_FEED_NE4BEG2": null, + "CLK_FEED_NE4BEG3": null, + "CLK_FEED_NE4C0": null, + "CLK_FEED_NE4C1": null, + "CLK_FEED_NE4C2": null, + "CLK_FEED_NE4C3": null, + "CLK_FEED_NW2A0": null, + "CLK_FEED_NW2A1": null, + "CLK_FEED_NW2A2": null, + "CLK_FEED_NW2A3": null, + "CLK_FEED_NW4A0": null, + "CLK_FEED_NW4A1": null, + "CLK_FEED_NW4A2": null, + "CLK_FEED_NW4A3": null, + "CLK_FEED_NW4END0": null, + "CLK_FEED_NW4END1": null, + "CLK_FEED_NW4END2": null, + "CLK_FEED_NW4END3": null, + "CLK_FEED_R_CK_BUFG_CASC0": null, + "CLK_FEED_R_CK_BUFG_CASC1": null, + "CLK_FEED_R_CK_BUFG_CASC10": null, + "CLK_FEED_R_CK_BUFG_CASC11": null, + "CLK_FEED_R_CK_BUFG_CASC12": null, + "CLK_FEED_R_CK_BUFG_CASC13": null, + "CLK_FEED_R_CK_BUFG_CASC14": null, + "CLK_FEED_R_CK_BUFG_CASC15": null, + "CLK_FEED_R_CK_BUFG_CASC16": null, + "CLK_FEED_R_CK_BUFG_CASC17": null, + "CLK_FEED_R_CK_BUFG_CASC18": null, + "CLK_FEED_R_CK_BUFG_CASC19": null, + "CLK_FEED_R_CK_BUFG_CASC2": null, + "CLK_FEED_R_CK_BUFG_CASC20": null, + "CLK_FEED_R_CK_BUFG_CASC21": null, + "CLK_FEED_R_CK_BUFG_CASC22": null, + "CLK_FEED_R_CK_BUFG_CASC23": null, + "CLK_FEED_R_CK_BUFG_CASC24": null, + "CLK_FEED_R_CK_BUFG_CASC25": null, + "CLK_FEED_R_CK_BUFG_CASC26": null, + "CLK_FEED_R_CK_BUFG_CASC27": null, + "CLK_FEED_R_CK_BUFG_CASC28": null, + "CLK_FEED_R_CK_BUFG_CASC29": null, + "CLK_FEED_R_CK_BUFG_CASC3": null, + "CLK_FEED_R_CK_BUFG_CASC30": null, + "CLK_FEED_R_CK_BUFG_CASC31": null, + "CLK_FEED_R_CK_BUFG_CASC4": null, + "CLK_FEED_R_CK_BUFG_CASC5": null, + "CLK_FEED_R_CK_BUFG_CASC6": null, + "CLK_FEED_R_CK_BUFG_CASC7": null, + "CLK_FEED_R_CK_BUFG_CASC8": null, + "CLK_FEED_R_CK_BUFG_CASC9": null, + "CLK_FEED_R_CK_GCLK0": null, + "CLK_FEED_R_CK_GCLK1": null, + "CLK_FEED_R_CK_GCLK10": null, + "CLK_FEED_R_CK_GCLK11": null, + "CLK_FEED_R_CK_GCLK12": null, + "CLK_FEED_R_CK_GCLK13": null, + "CLK_FEED_R_CK_GCLK14": null, + "CLK_FEED_R_CK_GCLK15": null, + "CLK_FEED_R_CK_GCLK16": null, + "CLK_FEED_R_CK_GCLK17": null, + "CLK_FEED_R_CK_GCLK18": null, + "CLK_FEED_R_CK_GCLK19": null, + "CLK_FEED_R_CK_GCLK2": null, + "CLK_FEED_R_CK_GCLK20": null, + "CLK_FEED_R_CK_GCLK21": null, + "CLK_FEED_R_CK_GCLK22": null, + "CLK_FEED_R_CK_GCLK23": null, + "CLK_FEED_R_CK_GCLK24": null, + "CLK_FEED_R_CK_GCLK25": null, + "CLK_FEED_R_CK_GCLK26": null, + "CLK_FEED_R_CK_GCLK27": null, + "CLK_FEED_R_CK_GCLK28": null, + "CLK_FEED_R_CK_GCLK29": null, + "CLK_FEED_R_CK_GCLK3": null, + "CLK_FEED_R_CK_GCLK30": null, + "CLK_FEED_R_CK_GCLK31": null, + "CLK_FEED_R_CK_GCLK4": null, + "CLK_FEED_R_CK_GCLK5": null, + "CLK_FEED_R_CK_GCLK6": null, + "CLK_FEED_R_CK_GCLK7": null, + "CLK_FEED_R_CK_GCLK8": null, + "CLK_FEED_R_CK_GCLK9": null, + "CLK_FEED_SE2A0": null, + "CLK_FEED_SE2A1": null, + "CLK_FEED_SE2A2": null, + "CLK_FEED_SE2A3": null, + "CLK_FEED_SE4BEG0": null, + "CLK_FEED_SE4BEG1": null, + "CLK_FEED_SE4BEG2": null, + "CLK_FEED_SE4BEG3": null, + "CLK_FEED_SE4C0": null, + "CLK_FEED_SE4C1": null, + "CLK_FEED_SE4C2": null, + "CLK_FEED_SE4C3": null, + "CLK_FEED_SW2A0": null, + "CLK_FEED_SW2A1": null, + "CLK_FEED_SW2A2": null, + "CLK_FEED_SW2A3": null, + "CLK_FEED_SW4A0": null, + "CLK_FEED_SW4A1": null, + "CLK_FEED_SW4A2": null, + "CLK_FEED_SW4A3": null, + "CLK_FEED_SW4END0": null, + "CLK_FEED_SW4END1": null, + "CLK_FEED_SW4END2": null, + "CLK_FEED_SW4END3": null, + "CLK_FEED_WL1END0": null, + "CLK_FEED_WL1END1": null, + "CLK_FEED_WL1END2": null, + "CLK_FEED_WL1END3": null, + "CLK_FEED_WR1END0": null, + "CLK_FEED_WR1END1": null, + "CLK_FEED_WR1END2": null, + "CLK_FEED_WR1END3": null, + "CLK_FEED_WW2A0": null, + "CLK_FEED_WW2A1": null, + "CLK_FEED_WW2A2": null, + "CLK_FEED_WW2A3": null, + "CLK_FEED_WW2END0": null, + "CLK_FEED_WW2END1": null, + "CLK_FEED_WW2END2": null, + "CLK_FEED_WW2END3": null, + "CLK_FEED_WW4A0": null, + "CLK_FEED_WW4A1": null, + "CLK_FEED_WW4A2": null, + "CLK_FEED_WW4A3": null, + "CLK_FEED_WW4B0": null, + "CLK_FEED_WW4B1": null, + "CLK_FEED_WW4B2": null, + "CLK_FEED_WW4B3": null, + "CLK_FEED_WW4C0": null, + "CLK_FEED_WW4C1": null, + "CLK_FEED_WW4C2": null, + "CLK_FEED_WW4C3": null, + "CLK_FEED_WW4END0": null, + "CLK_FEED_WW4END1": null, + "CLK_FEED_WW4END2": null, + "CLK_FEED_WW4END3": null, + "CLK_PMVIOB_A0": null, + "CLK_PMVIOB_A1": null, + "CLK_PMVIOB_EN": null, + "CLK_PMVIOB_O": null, + "CLK_PMVIOB_ODIV2": null, + "CLK_PMVIOB_ODIV4": null, + "CLK_PMV_BYP0_0": null, + "CLK_PMV_BYP1_0": null, + "CLK_PMV_BYP2_0": null, + "CLK_PMV_BYP3_0": null, + "CLK_PMV_BYP4_0": null, + "CLK_PMV_BYP5_0": null, + "CLK_PMV_BYP6_0": null, + "CLK_PMV_BYP7_0": null, + "CLK_PMV_CLK0_0": null, + "CLK_PMV_CLK1_0": null, + "CLK_PMV_CTRL0_0": null, + "CLK_PMV_CTRL1_0": null, + "CLK_PMV_FAN0_0": null, + "CLK_PMV_FAN1_0": null, + "CLK_PMV_FAN2_0": null, + "CLK_PMV_FAN3_0": null, + "CLK_PMV_FAN4_0": null, + "CLK_PMV_FAN5_0": null, + "CLK_PMV_FAN6_0": null, + "CLK_PMV_FAN7_0": null, + "CLK_PMV_IMUX0_0": null, + "CLK_PMV_IMUX10_0": null, + "CLK_PMV_IMUX11_0": null, + "CLK_PMV_IMUX12_0": null, + "CLK_PMV_IMUX13_0": null, + "CLK_PMV_IMUX14_0": null, + "CLK_PMV_IMUX15_0": null, + "CLK_PMV_IMUX16_0": null, + "CLK_PMV_IMUX17_0": null, + "CLK_PMV_IMUX18_0": null, + "CLK_PMV_IMUX19_0": null, + "CLK_PMV_IMUX1_0": null, + "CLK_PMV_IMUX20_0": null, + "CLK_PMV_IMUX21_0": null, + "CLK_PMV_IMUX22_0": null, + "CLK_PMV_IMUX23_0": null, + "CLK_PMV_IMUX24_0": null, + "CLK_PMV_IMUX25_0": null, + "CLK_PMV_IMUX26_0": null, + "CLK_PMV_IMUX27_0": null, + "CLK_PMV_IMUX28_0": null, + "CLK_PMV_IMUX29_0": null, + "CLK_PMV_IMUX2_0": null, + "CLK_PMV_IMUX30_0": null, + "CLK_PMV_IMUX31_0": null, + "CLK_PMV_IMUX32_0": null, + "CLK_PMV_IMUX33_0": null, + "CLK_PMV_IMUX34_0": null, + "CLK_PMV_IMUX35_0": null, + "CLK_PMV_IMUX36_0": null, + "CLK_PMV_IMUX37_0": null, + "CLK_PMV_IMUX38_0": null, + "CLK_PMV_IMUX39_0": null, + "CLK_PMV_IMUX3_0": null, + "CLK_PMV_IMUX40_0": null, + "CLK_PMV_IMUX41_0": null, + "CLK_PMV_IMUX42_0": null, + "CLK_PMV_IMUX43_0": null, + "CLK_PMV_IMUX44_0": null, + "CLK_PMV_IMUX45_0": null, + "CLK_PMV_IMUX46_0": null, + "CLK_PMV_IMUX47_0": null, + "CLK_PMV_IMUX4_0": null, + "CLK_PMV_IMUX5_0": null, + "CLK_PMV_IMUX6_0": null, + "CLK_PMV_IMUX7_0": null, + "CLK_PMV_IMUX8_0": null, + "CLK_PMV_IMUX9_0": null, + "CLK_PMV_LOGIC_OUTS0_0": null, + "CLK_PMV_LOGIC_OUTS10_0": null, + "CLK_PMV_LOGIC_OUTS11_0": null, + "CLK_PMV_LOGIC_OUTS12_0": null, + "CLK_PMV_LOGIC_OUTS13_0": null, + "CLK_PMV_LOGIC_OUTS14_0": null, + "CLK_PMV_LOGIC_OUTS15_0": null, + "CLK_PMV_LOGIC_OUTS16_0": null, + "CLK_PMV_LOGIC_OUTS17_0": null, + "CLK_PMV_LOGIC_OUTS18_0": null, + "CLK_PMV_LOGIC_OUTS19_0": null, + "CLK_PMV_LOGIC_OUTS1_0": null, + "CLK_PMV_LOGIC_OUTS20_0": null, + "CLK_PMV_LOGIC_OUTS21_0": null, + "CLK_PMV_LOGIC_OUTS22_0": null, + "CLK_PMV_LOGIC_OUTS23_0": null, + "CLK_PMV_LOGIC_OUTS2_0": null, + "CLK_PMV_LOGIC_OUTS3_0": null, + "CLK_PMV_LOGIC_OUTS4_0": null, + "CLK_PMV_LOGIC_OUTS5_0": null, + "CLK_PMV_LOGIC_OUTS6_0": null, + "CLK_PMV_LOGIC_OUTS7_0": null, + "CLK_PMV_LOGIC_OUTS8_0": null, + "CLK_PMV_LOGIC_OUTS9_0": null + } } diff --git a/kintex7/tile_type_CLK_TERM.json b/kintex7/tile_type_CLK_TERM.json index 5bf23c2..40014e1 100644 --- a/kintex7/tile_type_CLK_TERM.json +++ b/kintex7/tile_type_CLK_TERM.json @@ -2,70 +2,70 @@ "pips": {}, "sites": [], "tile_type": "CLK_TERM", - "wires": [ - "CLK_TERM_GCLK0", - "CLK_TERM_GCLK1", - "CLK_TERM_GCLK10", - "CLK_TERM_GCLK11", - "CLK_TERM_GCLK12", - "CLK_TERM_GCLK13", - "CLK_TERM_GCLK14", - "CLK_TERM_GCLK15", - "CLK_TERM_GCLK16", - "CLK_TERM_GCLK17", - "CLK_TERM_GCLK18", - "CLK_TERM_GCLK19", - "CLK_TERM_GCLK2", - "CLK_TERM_GCLK20", - "CLK_TERM_GCLK21", - "CLK_TERM_GCLK22", - "CLK_TERM_GCLK23", - "CLK_TERM_GCLK24", - "CLK_TERM_GCLK25", - "CLK_TERM_GCLK26", - "CLK_TERM_GCLK27", - "CLK_TERM_GCLK28", - "CLK_TERM_GCLK29", - "CLK_TERM_GCLK3", - "CLK_TERM_GCLK30", - "CLK_TERM_GCLK31", - "CLK_TERM_GCLK4", - "CLK_TERM_GCLK5", - "CLK_TERM_GCLK6", - "CLK_TERM_GCLK7", - "CLK_TERM_GCLK8", - "CLK_TERM_GCLK9", - "CLK_TERM_R_GCLK0", - "CLK_TERM_R_GCLK1", - "CLK_TERM_R_GCLK10", - "CLK_TERM_R_GCLK11", - "CLK_TERM_R_GCLK12", - "CLK_TERM_R_GCLK13", - "CLK_TERM_R_GCLK14", - "CLK_TERM_R_GCLK15", - "CLK_TERM_R_GCLK16", - "CLK_TERM_R_GCLK17", - "CLK_TERM_R_GCLK18", - "CLK_TERM_R_GCLK19", - "CLK_TERM_R_GCLK2", - "CLK_TERM_R_GCLK20", - "CLK_TERM_R_GCLK21", - "CLK_TERM_R_GCLK22", - "CLK_TERM_R_GCLK23", - "CLK_TERM_R_GCLK24", - "CLK_TERM_R_GCLK25", - "CLK_TERM_R_GCLK26", - "CLK_TERM_R_GCLK27", - "CLK_TERM_R_GCLK28", - "CLK_TERM_R_GCLK29", - "CLK_TERM_R_GCLK3", - "CLK_TERM_R_GCLK30", - "CLK_TERM_R_GCLK31", - "CLK_TERM_R_GCLK4", - "CLK_TERM_R_GCLK5", - "CLK_TERM_R_GCLK6", - "CLK_TERM_R_GCLK7", - "CLK_TERM_R_GCLK8", - "CLK_TERM_R_GCLK9" - ] + "wires": { + "CLK_TERM_GCLK0": null, + "CLK_TERM_GCLK1": null, + "CLK_TERM_GCLK10": null, + "CLK_TERM_GCLK11": null, + "CLK_TERM_GCLK12": null, + "CLK_TERM_GCLK13": null, + "CLK_TERM_GCLK14": null, + "CLK_TERM_GCLK15": null, + "CLK_TERM_GCLK16": null, + "CLK_TERM_GCLK17": null, + "CLK_TERM_GCLK18": null, + "CLK_TERM_GCLK19": null, + "CLK_TERM_GCLK2": null, + "CLK_TERM_GCLK20": null, + "CLK_TERM_GCLK21": null, + "CLK_TERM_GCLK22": null, + "CLK_TERM_GCLK23": null, + "CLK_TERM_GCLK24": null, + "CLK_TERM_GCLK25": null, + "CLK_TERM_GCLK26": null, + "CLK_TERM_GCLK27": null, + "CLK_TERM_GCLK28": null, + "CLK_TERM_GCLK29": null, + "CLK_TERM_GCLK3": null, + "CLK_TERM_GCLK30": null, + "CLK_TERM_GCLK31": null, + "CLK_TERM_GCLK4": null, + "CLK_TERM_GCLK5": null, + "CLK_TERM_GCLK6": null, + "CLK_TERM_GCLK7": null, + "CLK_TERM_GCLK8": null, + "CLK_TERM_GCLK9": null, + "CLK_TERM_R_GCLK0": null, + "CLK_TERM_R_GCLK1": null, + "CLK_TERM_R_GCLK10": null, + "CLK_TERM_R_GCLK11": null, + "CLK_TERM_R_GCLK12": null, + "CLK_TERM_R_GCLK13": null, + "CLK_TERM_R_GCLK14": null, + "CLK_TERM_R_GCLK15": null, + "CLK_TERM_R_GCLK16": null, + "CLK_TERM_R_GCLK17": null, + "CLK_TERM_R_GCLK18": null, + "CLK_TERM_R_GCLK19": null, + "CLK_TERM_R_GCLK2": null, + "CLK_TERM_R_GCLK20": null, + "CLK_TERM_R_GCLK21": null, + "CLK_TERM_R_GCLK22": null, + "CLK_TERM_R_GCLK23": null, + "CLK_TERM_R_GCLK24": null, + "CLK_TERM_R_GCLK25": null, + "CLK_TERM_R_GCLK26": null, + "CLK_TERM_R_GCLK27": null, + "CLK_TERM_R_GCLK28": null, + "CLK_TERM_R_GCLK29": null, + "CLK_TERM_R_GCLK3": null, + "CLK_TERM_R_GCLK30": null, + "CLK_TERM_R_GCLK31": null, + "CLK_TERM_R_GCLK4": null, + "CLK_TERM_R_GCLK5": null, + "CLK_TERM_R_GCLK6": null, + "CLK_TERM_R_GCLK7": null, + "CLK_TERM_R_GCLK8": null, + "CLK_TERM_R_GCLK9": null + } } diff --git a/kintex7/tile_type_CMT_FIFO_L.json b/kintex7/tile_type_CMT_FIFO_L.json index 6aaea8a..f58722b 100644 --- a/kintex7/tile_type_CMT_FIFO_L.json +++ b/kintex7/tile_type_CMT_FIFO_L.json @@ -2,1948 +2,5006 @@ "pips": { "CMT_FIFO_L.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_WRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK0_6" }, "CMT_FIFO_L.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK0_7" }, "CMT_FIFO_L.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK1_6" }, "CMT_FIFO_L.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_RDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK1_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D04", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_1->CMT_OUT_FIFO_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D01", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX21_9->CMT_OUT_FIFO_D71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D00", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_1->CMT_IN_FIFO_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D00", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_0->CMT_IN_FIFO_D02": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D02", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_3->CMT_IN_FIFO_D32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D03", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX38_9->CMT_OUT_FIFO_D73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D02", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D01", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D03", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_11->CMT_IN_FIFO_D93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D05", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D07", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_WREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_9" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D06", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_0" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_1" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_10" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_11" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_2" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_3" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_4" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_5->CMT_OUT_FIFO_D56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_5" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_6" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_RDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_7" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_8" }, "CMT_FIFO_L.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_9" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_RDCLK" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_RDENABLE" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_WRCLK" }, "CMT_FIFO_L.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_WRENABLE" }, "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY" }, "CMT_FIFO_L.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_ALMOSTFULL" }, "CMT_FIFO_L.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_EMPTY" }, "CMT_FIFO_L.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_FULL" }, "CMT_FIFO_L.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q00" }, "CMT_FIFO_L.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q01" }, "CMT_FIFO_L.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q02" }, "CMT_FIFO_L.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q03" }, "CMT_FIFO_L.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q04" }, "CMT_FIFO_L.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q05" }, "CMT_FIFO_L.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q06" }, "CMT_FIFO_L.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q07" }, "CMT_FIFO_L.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q10" }, "CMT_FIFO_L.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q11" }, "CMT_FIFO_L.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q12" }, "CMT_FIFO_L.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q13" }, "CMT_FIFO_L.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q14" }, "CMT_FIFO_L.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q15" }, "CMT_FIFO_L.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q16" }, "CMT_FIFO_L.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q17" }, "CMT_FIFO_L.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q20" }, "CMT_FIFO_L.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q21" }, "CMT_FIFO_L.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q22" }, "CMT_FIFO_L.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q23" }, "CMT_FIFO_L.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q24" }, "CMT_FIFO_L.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q25" }, "CMT_FIFO_L.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q26" }, "CMT_FIFO_L.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q27" }, "CMT_FIFO_L.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q30" }, "CMT_FIFO_L.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q31" }, "CMT_FIFO_L.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q32" }, "CMT_FIFO_L.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q33" }, "CMT_FIFO_L.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q34" }, "CMT_FIFO_L.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q35" }, "CMT_FIFO_L.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q36" }, "CMT_FIFO_L.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q37" }, "CMT_FIFO_L.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q40" }, "CMT_FIFO_L.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q41" }, "CMT_FIFO_L.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q42" }, "CMT_FIFO_L.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q43" }, "CMT_FIFO_L.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q44" }, "CMT_FIFO_L.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q45" }, "CMT_FIFO_L.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q46" }, "CMT_FIFO_L.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q47" }, "CMT_FIFO_L.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q50" }, "CMT_FIFO_L.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q51" }, "CMT_FIFO_L.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q52" }, "CMT_FIFO_L.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q53" }, "CMT_FIFO_L.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q54" }, "CMT_FIFO_L.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q55" }, "CMT_FIFO_L.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q56" }, "CMT_FIFO_L.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q57" }, "CMT_FIFO_L.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q60" }, "CMT_FIFO_L.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q61" }, "CMT_FIFO_L.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q62" }, "CMT_FIFO_L.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q63" }, "CMT_FIFO_L.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q64" }, "CMT_FIFO_L.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q65" }, "CMT_FIFO_L.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q66" }, "CMT_FIFO_L.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q67" }, "CMT_FIFO_L.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q70" }, "CMT_FIFO_L.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q71" }, "CMT_FIFO_L.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q72" }, "CMT_FIFO_L.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q73" }, "CMT_FIFO_L.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q74" }, "CMT_FIFO_L.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q75" }, "CMT_FIFO_L.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q76" }, "CMT_FIFO_L.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q77" }, "CMT_FIFO_L.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q80" }, "CMT_FIFO_L.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q81" }, "CMT_FIFO_L.CMT_IN_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q82" }, "CMT_FIFO_L.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q83" }, "CMT_FIFO_L.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q84" }, "CMT_FIFO_L.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q85" }, "CMT_FIFO_L.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q86" }, "CMT_FIFO_L.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q87" }, "CMT_FIFO_L.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q90" }, "CMT_FIFO_L.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q91" }, "CMT_FIFO_L.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q92" }, "CMT_FIFO_L.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q93" }, "CMT_FIFO_L.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q94" }, "CMT_FIFO_L.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q95" }, "CMT_FIFO_L.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q96" }, "CMT_FIFO_L.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q97" }, "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY" }, "CMT_FIFO_L.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_ALMOSTFULL" }, "CMT_FIFO_L.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_EMPTY" }, "CMT_FIFO_L.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_FULL" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q00" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q01" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q02" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q03" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q10" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q11" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q12" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q13" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q20" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q21" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q22" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q23" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q30" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q31" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q32" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q33" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q40" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q41" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q42" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q43" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q50" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q51" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q52" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q53" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q54" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q55" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q56" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q57" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q60" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q61" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q62" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q63" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q64" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q65" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q66" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q67" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q70" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q71" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q72" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q73" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q80" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q81" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q82" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q83" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q90" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q91" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q92" }, "CMT_FIFO_L.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q93" } }, @@ -1952,155 +5010,1496 @@ "name": "X0Y0", "prefix": "OUT_FIFO", "site_pins": { - "ALMOSTEMPTY": "CMT_OUT_FIFO_ALMOSTEMPTY", - "ALMOSTFULL": "CMT_OUT_FIFO_ALMOSTFULL", - "D00": "CMT_OUT_FIFO_D00", - "D01": "CMT_OUT_FIFO_D01", - "D02": "CMT_OUT_FIFO_D02", - "D03": "CMT_OUT_FIFO_D03", - "D04": "CMT_OUT_FIFO_D04", - "D05": "CMT_OUT_FIFO_D05", - "D06": "CMT_OUT_FIFO_D06", - "D07": "CMT_OUT_FIFO_D07", - "D10": "CMT_OUT_FIFO_D10", - "D11": "CMT_OUT_FIFO_D11", - "D12": "CMT_OUT_FIFO_D12", - "D13": "CMT_OUT_FIFO_D13", - "D14": "CMT_OUT_FIFO_D14", - "D15": "CMT_OUT_FIFO_D15", - "D16": "CMT_OUT_FIFO_D16", - "D17": "CMT_OUT_FIFO_D17", - "D20": "CMT_OUT_FIFO_D20", - "D21": "CMT_OUT_FIFO_D21", - "D22": "CMT_OUT_FIFO_D22", - "D23": "CMT_OUT_FIFO_D23", - "D24": "CMT_OUT_FIFO_D24", - "D25": "CMT_OUT_FIFO_D25", - "D26": "CMT_OUT_FIFO_D26", - "D27": "CMT_OUT_FIFO_D27", - "D30": "CMT_OUT_FIFO_D30", - "D31": "CMT_OUT_FIFO_D31", - "D32": "CMT_OUT_FIFO_D32", - "D33": "CMT_OUT_FIFO_D33", - "D34": "CMT_OUT_FIFO_D34", - "D35": "CMT_OUT_FIFO_D35", - "D36": "CMT_OUT_FIFO_D36", - "D37": "CMT_OUT_FIFO_D37", - "D40": "CMT_OUT_FIFO_D40", - "D41": "CMT_OUT_FIFO_D41", - "D42": "CMT_OUT_FIFO_D42", - "D43": "CMT_OUT_FIFO_D43", - "D44": "CMT_OUT_FIFO_D44", - "D45": "CMT_OUT_FIFO_D45", - "D46": "CMT_OUT_FIFO_D46", - "D47": "CMT_OUT_FIFO_D47", - "D50": "CMT_OUT_FIFO_D50", - "D51": "CMT_OUT_FIFO_D51", - "D52": "CMT_OUT_FIFO_D52", - "D53": "CMT_OUT_FIFO_D53", - "D54": "CMT_OUT_FIFO_D54", - "D55": "CMT_OUT_FIFO_D55", - "D56": "CMT_OUT_FIFO_D56", - "D57": "CMT_OUT_FIFO_D57", - "D60": "CMT_OUT_FIFO_D60", - "D61": "CMT_OUT_FIFO_D61", - "D62": "CMT_OUT_FIFO_D62", - "D63": "CMT_OUT_FIFO_D63", - "D64": "CMT_OUT_FIFO_D64", - "D65": "CMT_OUT_FIFO_D65", - "D66": "CMT_OUT_FIFO_D66", - "D67": "CMT_OUT_FIFO_D67", - "D70": "CMT_OUT_FIFO_D70", - "D71": "CMT_OUT_FIFO_D71", - "D72": "CMT_OUT_FIFO_D72", - "D73": "CMT_OUT_FIFO_D73", - "D74": "CMT_OUT_FIFO_D74", - "D75": "CMT_OUT_FIFO_D75", - "D76": "CMT_OUT_FIFO_D76", - "D77": "CMT_OUT_FIFO_D77", - "D80": "CMT_OUT_FIFO_D80", - "D81": "CMT_OUT_FIFO_D81", - "D82": "CMT_OUT_FIFO_D82", - "D83": "CMT_OUT_FIFO_D83", - "D84": "CMT_OUT_FIFO_D84", - "D85": "CMT_OUT_FIFO_D85", - "D86": "CMT_OUT_FIFO_D86", - "D87": "CMT_OUT_FIFO_D87", - "D90": "CMT_OUT_FIFO_D90", - "D91": "CMT_OUT_FIFO_D91", - "D92": "CMT_OUT_FIFO_D92", - "D93": "CMT_OUT_FIFO_D93", - "D94": "CMT_OUT_FIFO_D94", - "D95": "CMT_OUT_FIFO_D95", - "D96": "CMT_OUT_FIFO_D96", - "D97": "CMT_OUT_FIFO_D97", - "EMPTY": "CMT_OUT_FIFO_EMPTY", - "FULL": "CMT_OUT_FIFO_FULL", - "Q00": "CMT_OUT_FIFO_Q00", - "Q01": "CMT_OUT_FIFO_Q01", - "Q02": "CMT_OUT_FIFO_Q02", - "Q03": "CMT_OUT_FIFO_Q03", - "Q10": "CMT_OUT_FIFO_Q10", - "Q11": "CMT_OUT_FIFO_Q11", - "Q12": "CMT_OUT_FIFO_Q12", - "Q13": "CMT_OUT_FIFO_Q13", - "Q20": "CMT_OUT_FIFO_Q20", - "Q21": "CMT_OUT_FIFO_Q21", - "Q22": "CMT_OUT_FIFO_Q22", - "Q23": "CMT_OUT_FIFO_Q23", - "Q30": "CMT_OUT_FIFO_Q30", - "Q31": "CMT_OUT_FIFO_Q31", - "Q32": "CMT_OUT_FIFO_Q32", - "Q33": "CMT_OUT_FIFO_Q33", - "Q40": "CMT_OUT_FIFO_Q40", - "Q41": "CMT_OUT_FIFO_Q41", - "Q42": "CMT_OUT_FIFO_Q42", - "Q43": "CMT_OUT_FIFO_Q43", - "Q50": "CMT_OUT_FIFO_Q50", - "Q51": "CMT_OUT_FIFO_Q51", - "Q52": "CMT_OUT_FIFO_Q52", - "Q53": "CMT_OUT_FIFO_Q53", - "Q54": "CMT_OUT_FIFO_Q54", - "Q55": "CMT_OUT_FIFO_Q55", - "Q56": "CMT_OUT_FIFO_Q56", - "Q57": "CMT_OUT_FIFO_Q57", - "Q60": "CMT_OUT_FIFO_Q60", - "Q61": "CMT_OUT_FIFO_Q61", - "Q62": "CMT_OUT_FIFO_Q62", - "Q63": "CMT_OUT_FIFO_Q63", - "Q64": "CMT_OUT_FIFO_Q64", - "Q65": "CMT_OUT_FIFO_Q65", - "Q66": "CMT_OUT_FIFO_Q66", - "Q67": "CMT_OUT_FIFO_Q67", - "Q70": "CMT_OUT_FIFO_Q70", - "Q71": "CMT_OUT_FIFO_Q71", - "Q72": "CMT_OUT_FIFO_Q72", - "Q73": "CMT_OUT_FIFO_Q73", - "Q80": "CMT_OUT_FIFO_Q80", - "Q81": "CMT_OUT_FIFO_Q81", - "Q82": "CMT_OUT_FIFO_Q82", - "Q83": "CMT_OUT_FIFO_Q83", - "Q90": "CMT_OUT_FIFO_Q90", - "Q91": "CMT_OUT_FIFO_Q91", - "Q92": "CMT_OUT_FIFO_Q92", - "Q93": "CMT_OUT_FIFO_Q93", - "RDCLK": "CMT_OUT_FIFO_RDCLK", - "RDEN": "CMT_OUT_FIFO_RDEN", - "RESET": "CMT_OUT_FIFO_RESET", - "SCANENB": "CMT_OUT_FIFO_SCANENB", - "SCANIN0": "CMT_OUT_FIFO_SCANIN0", - "SCANIN1": "CMT_OUT_FIFO_SCANIN1", - "SCANIN2": "CMT_OUT_FIFO_SCANIN2", - "SCANIN3": "CMT_OUT_FIFO_SCANIN3", - "SCANOUT0": "CMT_OUT_FIFO_SCANOUT0", - "SCANOUT1": "CMT_OUT_FIFO_SCANOUT1", - "SCANOUT2": "CMT_OUT_FIFO_SCANOUT2", - "SCANOUT3": "CMT_OUT_FIFO_SCANOUT3", - "TESTMODEB": "CMT_OUT_FIFO_TESTMODEB", - "TESTREADDISB": "CMT_OUT_FIFO_TESTREADDISB", - "TESTWRITEDISB": "CMT_OUT_FIFO_TESTWRITEDISB", - "WRCLK": "CMT_OUT_FIFO_WRCLK", - "WREN": "CMT_OUT_FIFO_WREN" + "ALMOSTEMPTY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_OUT_FIFO_ALMOSTEMPTY" + }, + "ALMOSTFULL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_OUT_FIFO_ALMOSTFULL" + }, + "D00": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D00" + }, + "D01": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D01" + }, + "D02": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D02" + }, + "D03": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D03" + }, + "D04": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D04" + }, + "D05": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D05" + }, + "D06": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D06" + }, + "D07": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D07" + }, + "D10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D10" + }, + "D11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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"CMT_FIFO_EE2A3_1", - "CMT_FIFO_EE2A3_10", - "CMT_FIFO_EE2A3_11", - "CMT_FIFO_EE2A3_2", - "CMT_FIFO_EE2A3_3", - "CMT_FIFO_EE2A3_4", - "CMT_FIFO_EE2A3_5", - "CMT_FIFO_EE2A3_6", - "CMT_FIFO_EE2A3_7", - "CMT_FIFO_EE2A3_8", - "CMT_FIFO_EE2A3_9", - "CMT_FIFO_EE2BEG0_0", - "CMT_FIFO_EE2BEG0_1", - "CMT_FIFO_EE2BEG0_10", - "CMT_FIFO_EE2BEG0_11", - "CMT_FIFO_EE2BEG0_2", - "CMT_FIFO_EE2BEG0_3", - "CMT_FIFO_EE2BEG0_4", - "CMT_FIFO_EE2BEG0_5", - "CMT_FIFO_EE2BEG0_6", - "CMT_FIFO_EE2BEG0_7", - "CMT_FIFO_EE2BEG0_8", - "CMT_FIFO_EE2BEG0_9", - "CMT_FIFO_EE2BEG1_0", - "CMT_FIFO_EE2BEG1_1", - "CMT_FIFO_EE2BEG1_10", - "CMT_FIFO_EE2BEG1_11", - "CMT_FIFO_EE2BEG1_2", - "CMT_FIFO_EE2BEG1_3", - "CMT_FIFO_EE2BEG1_4", - "CMT_FIFO_EE2BEG1_5", - "CMT_FIFO_EE2BEG1_6", - "CMT_FIFO_EE2BEG1_7", - "CMT_FIFO_EE2BEG1_8", - "CMT_FIFO_EE2BEG1_9", - "CMT_FIFO_EE2BEG2_0", - "CMT_FIFO_EE2BEG2_1", - "CMT_FIFO_EE2BEG2_10", - "CMT_FIFO_EE2BEG2_11", - "CMT_FIFO_EE2BEG2_2", - "CMT_FIFO_EE2BEG2_3", - "CMT_FIFO_EE2BEG2_4", - "CMT_FIFO_EE2BEG2_5", - "CMT_FIFO_EE2BEG2_6", - "CMT_FIFO_EE2BEG2_7", - "CMT_FIFO_EE2BEG2_8", - "CMT_FIFO_EE2BEG2_9", - "CMT_FIFO_EE2BEG3_0", - "CMT_FIFO_EE2BEG3_1", - "CMT_FIFO_EE2BEG3_10", - "CMT_FIFO_EE2BEG3_11", - "CMT_FIFO_EE2BEG3_2", - "CMT_FIFO_EE2BEG3_3", - "CMT_FIFO_EE2BEG3_4", - "CMT_FIFO_EE2BEG3_5", - "CMT_FIFO_EE2BEG3_6", - "CMT_FIFO_EE2BEG3_7", - "CMT_FIFO_EE2BEG3_8", - "CMT_FIFO_EE2BEG3_9", - "CMT_FIFO_EE4A0_0", - "CMT_FIFO_EE4A0_1", - "CMT_FIFO_EE4A0_10", - "CMT_FIFO_EE4A0_11", - "CMT_FIFO_EE4A0_2", - "CMT_FIFO_EE4A0_3", - "CMT_FIFO_EE4A0_4", - "CMT_FIFO_EE4A0_5", - "CMT_FIFO_EE4A0_6", - "CMT_FIFO_EE4A0_7", - "CMT_FIFO_EE4A0_8", - "CMT_FIFO_EE4A0_9", - "CMT_FIFO_EE4A1_0", - "CMT_FIFO_EE4A1_1", - "CMT_FIFO_EE4A1_10", - "CMT_FIFO_EE4A1_11", - "CMT_FIFO_EE4A1_2", - "CMT_FIFO_EE4A1_3", - "CMT_FIFO_EE4A1_4", - "CMT_FIFO_EE4A1_5", - "CMT_FIFO_EE4A1_6", - "CMT_FIFO_EE4A1_7", - "CMT_FIFO_EE4A1_8", - "CMT_FIFO_EE4A1_9", - "CMT_FIFO_EE4A2_0", - "CMT_FIFO_EE4A2_1", - "CMT_FIFO_EE4A2_10", - "CMT_FIFO_EE4A2_11", - "CMT_FIFO_EE4A2_2", - "CMT_FIFO_EE4A2_3", - "CMT_FIFO_EE4A2_4", - "CMT_FIFO_EE4A2_5", - "CMT_FIFO_EE4A2_6", - "CMT_FIFO_EE4A2_7", - "CMT_FIFO_EE4A2_8", - "CMT_FIFO_EE4A2_9", - "CMT_FIFO_EE4A3_0", - "CMT_FIFO_EE4A3_1", - "CMT_FIFO_EE4A3_10", - "CMT_FIFO_EE4A3_11", - "CMT_FIFO_EE4A3_2", - "CMT_FIFO_EE4A3_3", - "CMT_FIFO_EE4A3_4", - "CMT_FIFO_EE4A3_5", - "CMT_FIFO_EE4A3_6", - "CMT_FIFO_EE4A3_7", - "CMT_FIFO_EE4A3_8", - "CMT_FIFO_EE4A3_9", - "CMT_FIFO_EE4B0_0", - "CMT_FIFO_EE4B0_1", - "CMT_FIFO_EE4B0_10", - "CMT_FIFO_EE4B0_11", - "CMT_FIFO_EE4B0_2", - "CMT_FIFO_EE4B0_3", - "CMT_FIFO_EE4B0_4", - "CMT_FIFO_EE4B0_5", - "CMT_FIFO_EE4B0_6", - "CMT_FIFO_EE4B0_7", - "CMT_FIFO_EE4B0_8", - "CMT_FIFO_EE4B0_9", - "CMT_FIFO_EE4B1_0", - "CMT_FIFO_EE4B1_1", - "CMT_FIFO_EE4B1_10", - "CMT_FIFO_EE4B1_11", - "CMT_FIFO_EE4B1_2", - "CMT_FIFO_EE4B1_3", - "CMT_FIFO_EE4B1_4", - "CMT_FIFO_EE4B1_5", - "CMT_FIFO_EE4B1_6", - "CMT_FIFO_EE4B1_7", - "CMT_FIFO_EE4B1_8", - "CMT_FIFO_EE4B1_9", - "CMT_FIFO_EE4B2_0", - "CMT_FIFO_EE4B2_1", - "CMT_FIFO_EE4B2_10", - "CMT_FIFO_EE4B2_11", - "CMT_FIFO_EE4B2_2", - "CMT_FIFO_EE4B2_3", - "CMT_FIFO_EE4B2_4", - "CMT_FIFO_EE4B2_5", - "CMT_FIFO_EE4B2_6", - "CMT_FIFO_EE4B2_7", - "CMT_FIFO_EE4B2_8", - "CMT_FIFO_EE4B2_9", - "CMT_FIFO_EE4B3_0", - "CMT_FIFO_EE4B3_1", - "CMT_FIFO_EE4B3_10", - "CMT_FIFO_EE4B3_11", - "CMT_FIFO_EE4B3_2", - "CMT_FIFO_EE4B3_3", - "CMT_FIFO_EE4B3_4", - "CMT_FIFO_EE4B3_5", - "CMT_FIFO_EE4B3_6", - "CMT_FIFO_EE4B3_7", - "CMT_FIFO_EE4B3_8", - "CMT_FIFO_EE4B3_9", - "CMT_FIFO_EE4BEG0_0", - "CMT_FIFO_EE4BEG0_1", - "CMT_FIFO_EE4BEG0_10", - "CMT_FIFO_EE4BEG0_11", - "CMT_FIFO_EE4BEG0_2", - "CMT_FIFO_EE4BEG0_3", - "CMT_FIFO_EE4BEG0_4", - "CMT_FIFO_EE4BEG0_5", - "CMT_FIFO_EE4BEG0_6", - "CMT_FIFO_EE4BEG0_7", - "CMT_FIFO_EE4BEG0_8", - "CMT_FIFO_EE4BEG0_9", - "CMT_FIFO_EE4BEG1_0", - "CMT_FIFO_EE4BEG1_1", - "CMT_FIFO_EE4BEG1_10", - "CMT_FIFO_EE4BEG1_11", - "CMT_FIFO_EE4BEG1_2", - "CMT_FIFO_EE4BEG1_3", - "CMT_FIFO_EE4BEG1_4", - "CMT_FIFO_EE4BEG1_5", - "CMT_FIFO_EE4BEG1_6", - "CMT_FIFO_EE4BEG1_7", - "CMT_FIFO_EE4BEG1_8", - "CMT_FIFO_EE4BEG1_9", - "CMT_FIFO_EE4BEG2_0", - "CMT_FIFO_EE4BEG2_1", - "CMT_FIFO_EE4BEG2_10", - "CMT_FIFO_EE4BEG2_11", - "CMT_FIFO_EE4BEG2_2", - "CMT_FIFO_EE4BEG2_3", - "CMT_FIFO_EE4BEG2_4", - "CMT_FIFO_EE4BEG2_5", - "CMT_FIFO_EE4BEG2_6", - "CMT_FIFO_EE4BEG2_7", - "CMT_FIFO_EE4BEG2_8", - "CMT_FIFO_EE4BEG2_9", - "CMT_FIFO_EE4BEG3_0", - "CMT_FIFO_EE4BEG3_1", - "CMT_FIFO_EE4BEG3_10", - "CMT_FIFO_EE4BEG3_11", - "CMT_FIFO_EE4BEG3_2", - "CMT_FIFO_EE4BEG3_3", - "CMT_FIFO_EE4BEG3_4", - "CMT_FIFO_EE4BEG3_5", - "CMT_FIFO_EE4BEG3_6", - "CMT_FIFO_EE4BEG3_7", - "CMT_FIFO_EE4BEG3_8", - "CMT_FIFO_EE4BEG3_9", - "CMT_FIFO_EE4C0_0", - "CMT_FIFO_EE4C0_1", - "CMT_FIFO_EE4C0_10", - "CMT_FIFO_EE4C0_11", - "CMT_FIFO_EE4C0_2", - "CMT_FIFO_EE4C0_3", - "CMT_FIFO_EE4C0_4", - "CMT_FIFO_EE4C0_5", - "CMT_FIFO_EE4C0_6", - "CMT_FIFO_EE4C0_7", - "CMT_FIFO_EE4C0_8", - "CMT_FIFO_EE4C0_9", - "CMT_FIFO_EE4C1_0", - "CMT_FIFO_EE4C1_1", - "CMT_FIFO_EE4C1_10", - "CMT_FIFO_EE4C1_11", - "CMT_FIFO_EE4C1_2", - "CMT_FIFO_EE4C1_3", - "CMT_FIFO_EE4C1_4", - "CMT_FIFO_EE4C1_5", - "CMT_FIFO_EE4C1_6", - "CMT_FIFO_EE4C1_7", - "CMT_FIFO_EE4C1_8", - "CMT_FIFO_EE4C1_9", - "CMT_FIFO_EE4C2_0", - "CMT_FIFO_EE4C2_1", - "CMT_FIFO_EE4C2_10", - "CMT_FIFO_EE4C2_11", - "CMT_FIFO_EE4C2_2", - "CMT_FIFO_EE4C2_3", - "CMT_FIFO_EE4C2_4", - "CMT_FIFO_EE4C2_5", - "CMT_FIFO_EE4C2_6", - "CMT_FIFO_EE4C2_7", - "CMT_FIFO_EE4C2_8", - "CMT_FIFO_EE4C2_9", - "CMT_FIFO_EE4C3_0", - "CMT_FIFO_EE4C3_1", - "CMT_FIFO_EE4C3_10", - "CMT_FIFO_EE4C3_11", - "CMT_FIFO_EE4C3_2", - "CMT_FIFO_EE4C3_3", - "CMT_FIFO_EE4C3_4", - "CMT_FIFO_EE4C3_5", - "CMT_FIFO_EE4C3_6", - "CMT_FIFO_EE4C3_7", - "CMT_FIFO_EE4C3_8", - "CMT_FIFO_EE4C3_9", - "CMT_FIFO_EL1BEG0_0", - "CMT_FIFO_EL1BEG0_1", - "CMT_FIFO_EL1BEG0_10", - "CMT_FIFO_EL1BEG0_11", - "CMT_FIFO_EL1BEG0_2", - "CMT_FIFO_EL1BEG0_3", - "CMT_FIFO_EL1BEG0_4", - "CMT_FIFO_EL1BEG0_5", - "CMT_FIFO_EL1BEG0_6", - "CMT_FIFO_EL1BEG0_7", - "CMT_FIFO_EL1BEG0_8", - "CMT_FIFO_EL1BEG0_9", - "CMT_FIFO_EL1BEG1_0", - "CMT_FIFO_EL1BEG1_1", - "CMT_FIFO_EL1BEG1_10", - "CMT_FIFO_EL1BEG1_11", - "CMT_FIFO_EL1BEG1_2", - "CMT_FIFO_EL1BEG1_3", - "CMT_FIFO_EL1BEG1_4", - "CMT_FIFO_EL1BEG1_5", - "CMT_FIFO_EL1BEG1_6", - "CMT_FIFO_EL1BEG1_7", - "CMT_FIFO_EL1BEG1_8", - "CMT_FIFO_EL1BEG1_9", - "CMT_FIFO_EL1BEG2_0", - "CMT_FIFO_EL1BEG2_1", - "CMT_FIFO_EL1BEG2_10", - "CMT_FIFO_EL1BEG2_11", - "CMT_FIFO_EL1BEG2_2", - "CMT_FIFO_EL1BEG2_3", - "CMT_FIFO_EL1BEG2_4", - "CMT_FIFO_EL1BEG2_5", - "CMT_FIFO_EL1BEG2_6", - "CMT_FIFO_EL1BEG2_7", - "CMT_FIFO_EL1BEG2_8", - "CMT_FIFO_EL1BEG2_9", - "CMT_FIFO_EL1BEG3_0", - "CMT_FIFO_EL1BEG3_1", - "CMT_FIFO_EL1BEG3_10", - "CMT_FIFO_EL1BEG3_11", - "CMT_FIFO_EL1BEG3_2", - "CMT_FIFO_EL1BEG3_3", - "CMT_FIFO_EL1BEG3_4", - "CMT_FIFO_EL1BEG3_5", - "CMT_FIFO_EL1BEG3_6", - "CMT_FIFO_EL1BEG3_7", - "CMT_FIFO_EL1BEG3_8", - "CMT_FIFO_EL1BEG3_9", - "CMT_FIFO_ER1BEG0_0", - "CMT_FIFO_ER1BEG0_1", - "CMT_FIFO_ER1BEG0_10", - "CMT_FIFO_ER1BEG0_11", - "CMT_FIFO_ER1BEG0_2", - "CMT_FIFO_ER1BEG0_3", - "CMT_FIFO_ER1BEG0_4", - "CMT_FIFO_ER1BEG0_5", - "CMT_FIFO_ER1BEG0_6", - "CMT_FIFO_ER1BEG0_7", - "CMT_FIFO_ER1BEG0_8", - "CMT_FIFO_ER1BEG0_9", - "CMT_FIFO_ER1BEG1_0", - "CMT_FIFO_ER1BEG1_1", - "CMT_FIFO_ER1BEG1_10", - "CMT_FIFO_ER1BEG1_11", - "CMT_FIFO_ER1BEG1_2", - "CMT_FIFO_ER1BEG1_3", - "CMT_FIFO_ER1BEG1_4", - "CMT_FIFO_ER1BEG1_5", - "CMT_FIFO_ER1BEG1_6", - "CMT_FIFO_ER1BEG1_7", - "CMT_FIFO_ER1BEG1_8", - "CMT_FIFO_ER1BEG1_9", - "CMT_FIFO_ER1BEG2_0", - "CMT_FIFO_ER1BEG2_1", - "CMT_FIFO_ER1BEG2_10", - "CMT_FIFO_ER1BEG2_11", - "CMT_FIFO_ER1BEG2_2", - "CMT_FIFO_ER1BEG2_3", - "CMT_FIFO_ER1BEG2_4", - "CMT_FIFO_ER1BEG2_5", - "CMT_FIFO_ER1BEG2_6", - "CMT_FIFO_ER1BEG2_7", - "CMT_FIFO_ER1BEG2_8", - "CMT_FIFO_ER1BEG2_9", - "CMT_FIFO_ER1BEG3_0", - "CMT_FIFO_ER1BEG3_1", - "CMT_FIFO_ER1BEG3_10", - "CMT_FIFO_ER1BEG3_11", - "CMT_FIFO_ER1BEG3_2", - "CMT_FIFO_ER1BEG3_3", - "CMT_FIFO_ER1BEG3_4", - "CMT_FIFO_ER1BEG3_5", - "CMT_FIFO_ER1BEG3_6", - "CMT_FIFO_ER1BEG3_7", - "CMT_FIFO_ER1BEG3_8", - "CMT_FIFO_ER1BEG3_9", - "CMT_FIFO_LH10_0", - "CMT_FIFO_LH10_1", - "CMT_FIFO_LH10_10", - "CMT_FIFO_LH10_11", - "CMT_FIFO_LH10_2", - "CMT_FIFO_LH10_3", - "CMT_FIFO_LH10_4", - "CMT_FIFO_LH10_5", - "CMT_FIFO_LH10_6", - "CMT_FIFO_LH10_7", - "CMT_FIFO_LH10_8", - "CMT_FIFO_LH10_9", - "CMT_FIFO_LH11_0", - "CMT_FIFO_LH11_1", - "CMT_FIFO_LH11_10", - "CMT_FIFO_LH11_11", - "CMT_FIFO_LH11_2", - "CMT_FIFO_LH11_3", - "CMT_FIFO_LH11_4", - "CMT_FIFO_LH11_5", - "CMT_FIFO_LH11_6", - "CMT_FIFO_LH11_7", - "CMT_FIFO_LH11_8", - "CMT_FIFO_LH11_9", - "CMT_FIFO_LH12_0", - "CMT_FIFO_LH12_1", - "CMT_FIFO_LH12_10", - "CMT_FIFO_LH12_11", - "CMT_FIFO_LH12_2", - "CMT_FIFO_LH12_3", - "CMT_FIFO_LH12_4", - "CMT_FIFO_LH12_5", - "CMT_FIFO_LH12_6", - "CMT_FIFO_LH12_7", - "CMT_FIFO_LH12_8", - "CMT_FIFO_LH12_9", - "CMT_FIFO_LH1_0", - "CMT_FIFO_LH1_1", - "CMT_FIFO_LH1_10", - "CMT_FIFO_LH1_11", - "CMT_FIFO_LH1_2", - "CMT_FIFO_LH1_3", - "CMT_FIFO_LH1_4", - "CMT_FIFO_LH1_5", - "CMT_FIFO_LH1_6", - "CMT_FIFO_LH1_7", - "CMT_FIFO_LH1_8", - "CMT_FIFO_LH1_9", - "CMT_FIFO_LH2_0", - "CMT_FIFO_LH2_1", - "CMT_FIFO_LH2_10", - "CMT_FIFO_LH2_11", - "CMT_FIFO_LH2_2", - "CMT_FIFO_LH2_3", - "CMT_FIFO_LH2_4", - "CMT_FIFO_LH2_5", - "CMT_FIFO_LH2_6", - "CMT_FIFO_LH2_7", - "CMT_FIFO_LH2_8", - "CMT_FIFO_LH2_9", - "CMT_FIFO_LH3_0", - "CMT_FIFO_LH3_1", - "CMT_FIFO_LH3_10", - "CMT_FIFO_LH3_11", - "CMT_FIFO_LH3_2", - "CMT_FIFO_LH3_3", - "CMT_FIFO_LH3_4", - "CMT_FIFO_LH3_5", - "CMT_FIFO_LH3_6", - "CMT_FIFO_LH3_7", - "CMT_FIFO_LH3_8", - "CMT_FIFO_LH3_9", - "CMT_FIFO_LH4_0", - "CMT_FIFO_LH4_1", - "CMT_FIFO_LH4_10", - "CMT_FIFO_LH4_11", - "CMT_FIFO_LH4_2", - "CMT_FIFO_LH4_3", - "CMT_FIFO_LH4_4", - "CMT_FIFO_LH4_5", - "CMT_FIFO_LH4_6", - "CMT_FIFO_LH4_7", - "CMT_FIFO_LH4_8", - "CMT_FIFO_LH4_9", - "CMT_FIFO_LH5_0", - "CMT_FIFO_LH5_1", - "CMT_FIFO_LH5_10", - "CMT_FIFO_LH5_11", - "CMT_FIFO_LH5_2", - "CMT_FIFO_LH5_3", - "CMT_FIFO_LH5_4", - "CMT_FIFO_LH5_5", - "CMT_FIFO_LH5_6", - "CMT_FIFO_LH5_7", - "CMT_FIFO_LH5_8", - "CMT_FIFO_LH5_9", - "CMT_FIFO_LH6_0", - "CMT_FIFO_LH6_1", - "CMT_FIFO_LH6_10", - "CMT_FIFO_LH6_11", - "CMT_FIFO_LH6_2", - "CMT_FIFO_LH6_3", - "CMT_FIFO_LH6_4", - "CMT_FIFO_LH6_5", - "CMT_FIFO_LH6_6", - "CMT_FIFO_LH6_7", - "CMT_FIFO_LH6_8", - "CMT_FIFO_LH6_9", - "CMT_FIFO_LH7_0", - "CMT_FIFO_LH7_1", - "CMT_FIFO_LH7_10", - "CMT_FIFO_LH7_11", - "CMT_FIFO_LH7_2", - "CMT_FIFO_LH7_3", - "CMT_FIFO_LH7_4", - "CMT_FIFO_LH7_5", - "CMT_FIFO_LH7_6", - "CMT_FIFO_LH7_7", - "CMT_FIFO_LH7_8", - "CMT_FIFO_LH7_9", - "CMT_FIFO_LH8_0", - "CMT_FIFO_LH8_1", - "CMT_FIFO_LH8_10", - "CMT_FIFO_LH8_11", - "CMT_FIFO_LH8_2", - "CMT_FIFO_LH8_3", - "CMT_FIFO_LH8_4", - "CMT_FIFO_LH8_5", - "CMT_FIFO_LH8_6", - "CMT_FIFO_LH8_7", - "CMT_FIFO_LH8_8", - "CMT_FIFO_LH8_9", - "CMT_FIFO_LH9_0", - "CMT_FIFO_LH9_1", - "CMT_FIFO_LH9_10", - "CMT_FIFO_LH9_11", - "CMT_FIFO_LH9_2", - "CMT_FIFO_LH9_3", - "CMT_FIFO_LH9_4", - "CMT_FIFO_LH9_5", - "CMT_FIFO_LH9_6", - "CMT_FIFO_LH9_7", - "CMT_FIFO_LH9_8", - "CMT_FIFO_LH9_9", - "CMT_FIFO_L_BYP0_0", - "CMT_FIFO_L_BYP0_1", - "CMT_FIFO_L_BYP0_10", - "CMT_FIFO_L_BYP0_11", - "CMT_FIFO_L_BYP0_2", - "CMT_FIFO_L_BYP0_3", - "CMT_FIFO_L_BYP0_4", - "CMT_FIFO_L_BYP0_5", - "CMT_FIFO_L_BYP0_6", - "CMT_FIFO_L_BYP0_7", - "CMT_FIFO_L_BYP0_8", - "CMT_FIFO_L_BYP0_9", - "CMT_FIFO_L_BYP1_0", - "CMT_FIFO_L_BYP1_1", - "CMT_FIFO_L_BYP1_10", - "CMT_FIFO_L_BYP1_11", - "CMT_FIFO_L_BYP1_2", - "CMT_FIFO_L_BYP1_3", - "CMT_FIFO_L_BYP1_4", - "CMT_FIFO_L_BYP1_5", - "CMT_FIFO_L_BYP1_6", - "CMT_FIFO_L_BYP1_7", - "CMT_FIFO_L_BYP1_8", - "CMT_FIFO_L_BYP1_9", - "CMT_FIFO_L_BYP2_0", - "CMT_FIFO_L_BYP2_1", - "CMT_FIFO_L_BYP2_10", - "CMT_FIFO_L_BYP2_11", - "CMT_FIFO_L_BYP2_2", - "CMT_FIFO_L_BYP2_3", - "CMT_FIFO_L_BYP2_4", - "CMT_FIFO_L_BYP2_5", - "CMT_FIFO_L_BYP2_6", - "CMT_FIFO_L_BYP2_7", - "CMT_FIFO_L_BYP2_8", - "CMT_FIFO_L_BYP2_9", - "CMT_FIFO_L_BYP3_0", - "CMT_FIFO_L_BYP3_1", - "CMT_FIFO_L_BYP3_10", - "CMT_FIFO_L_BYP3_11", - "CMT_FIFO_L_BYP3_2", - "CMT_FIFO_L_BYP3_3", - "CMT_FIFO_L_BYP3_4", - "CMT_FIFO_L_BYP3_5", - "CMT_FIFO_L_BYP3_6", - "CMT_FIFO_L_BYP3_7", - "CMT_FIFO_L_BYP3_8", - "CMT_FIFO_L_BYP3_9", - "CMT_FIFO_L_BYP4_0", - "CMT_FIFO_L_BYP4_1", - "CMT_FIFO_L_BYP4_10", - "CMT_FIFO_L_BYP4_11", - "CMT_FIFO_L_BYP4_2", - "CMT_FIFO_L_BYP4_3", - "CMT_FIFO_L_BYP4_4", - "CMT_FIFO_L_BYP4_5", - "CMT_FIFO_L_BYP4_6", - "CMT_FIFO_L_BYP4_7", - "CMT_FIFO_L_BYP4_8", - "CMT_FIFO_L_BYP4_9", - "CMT_FIFO_L_BYP5_0", - "CMT_FIFO_L_BYP5_1", - "CMT_FIFO_L_BYP5_10", - "CMT_FIFO_L_BYP5_11", - "CMT_FIFO_L_BYP5_2", - "CMT_FIFO_L_BYP5_3", - "CMT_FIFO_L_BYP5_4", - "CMT_FIFO_L_BYP5_5", - "CMT_FIFO_L_BYP5_6", - "CMT_FIFO_L_BYP5_7", - "CMT_FIFO_L_BYP5_8", - "CMT_FIFO_L_BYP5_9", - "CMT_FIFO_L_BYP6_0", - "CMT_FIFO_L_BYP6_1", - "CMT_FIFO_L_BYP6_10", - "CMT_FIFO_L_BYP6_11", - "CMT_FIFO_L_BYP6_2", - "CMT_FIFO_L_BYP6_3", - "CMT_FIFO_L_BYP6_4", - "CMT_FIFO_L_BYP6_5", - "CMT_FIFO_L_BYP6_6", - "CMT_FIFO_L_BYP6_7", - "CMT_FIFO_L_BYP6_8", - "CMT_FIFO_L_BYP6_9", - "CMT_FIFO_L_BYP7_0", - "CMT_FIFO_L_BYP7_1", - "CMT_FIFO_L_BYP7_10", - "CMT_FIFO_L_BYP7_11", - "CMT_FIFO_L_BYP7_2", - "CMT_FIFO_L_BYP7_3", - "CMT_FIFO_L_BYP7_4", - "CMT_FIFO_L_BYP7_5", - "CMT_FIFO_L_BYP7_6", - "CMT_FIFO_L_BYP7_7", - "CMT_FIFO_L_BYP7_8", - "CMT_FIFO_L_BYP7_9", - "CMT_FIFO_L_CLK0_0", - "CMT_FIFO_L_CLK0_1", - "CMT_FIFO_L_CLK0_10", - "CMT_FIFO_L_CLK0_11", - "CMT_FIFO_L_CLK0_2", - "CMT_FIFO_L_CLK0_3", - "CMT_FIFO_L_CLK0_4", - "CMT_FIFO_L_CLK0_5", - "CMT_FIFO_L_CLK0_6", - "CMT_FIFO_L_CLK0_7", - "CMT_FIFO_L_CLK0_8", - "CMT_FIFO_L_CLK0_9", - "CMT_FIFO_L_CLK1_0", - "CMT_FIFO_L_CLK1_1", - "CMT_FIFO_L_CLK1_10", - "CMT_FIFO_L_CLK1_11", - "CMT_FIFO_L_CLK1_2", - "CMT_FIFO_L_CLK1_3", - "CMT_FIFO_L_CLK1_4", - "CMT_FIFO_L_CLK1_5", - "CMT_FIFO_L_CLK1_6", - "CMT_FIFO_L_CLK1_7", - "CMT_FIFO_L_CLK1_8", - "CMT_FIFO_L_CLK1_9", - "CMT_FIFO_L_CTRL0_0", - "CMT_FIFO_L_CTRL0_1", - "CMT_FIFO_L_CTRL0_10", - "CMT_FIFO_L_CTRL0_11", - "CMT_FIFO_L_CTRL0_2", - "CMT_FIFO_L_CTRL0_3", - "CMT_FIFO_L_CTRL0_4", - "CMT_FIFO_L_CTRL0_5", - "CMT_FIFO_L_CTRL0_6", - "CMT_FIFO_L_CTRL0_7", - "CMT_FIFO_L_CTRL0_8", - "CMT_FIFO_L_CTRL0_9", - "CMT_FIFO_L_CTRL1_0", - "CMT_FIFO_L_CTRL1_1", - "CMT_FIFO_L_CTRL1_10", - "CMT_FIFO_L_CTRL1_11", - "CMT_FIFO_L_CTRL1_2", - "CMT_FIFO_L_CTRL1_3", - "CMT_FIFO_L_CTRL1_4", - "CMT_FIFO_L_CTRL1_5", - "CMT_FIFO_L_CTRL1_6", - "CMT_FIFO_L_CTRL1_7", - "CMT_FIFO_L_CTRL1_8", - "CMT_FIFO_L_CTRL1_9", - "CMT_FIFO_L_FAN0_0", - "CMT_FIFO_L_FAN0_1", - "CMT_FIFO_L_FAN0_10", - "CMT_FIFO_L_FAN0_11", - "CMT_FIFO_L_FAN0_2", - "CMT_FIFO_L_FAN0_3", - "CMT_FIFO_L_FAN0_4", - "CMT_FIFO_L_FAN0_5", - "CMT_FIFO_L_FAN0_6", - "CMT_FIFO_L_FAN0_7", - "CMT_FIFO_L_FAN0_8", - "CMT_FIFO_L_FAN0_9", - "CMT_FIFO_L_FAN1_0", - "CMT_FIFO_L_FAN1_1", - "CMT_FIFO_L_FAN1_10", - "CMT_FIFO_L_FAN1_11", - "CMT_FIFO_L_FAN1_2", - "CMT_FIFO_L_FAN1_3", - "CMT_FIFO_L_FAN1_4", - "CMT_FIFO_L_FAN1_5", - "CMT_FIFO_L_FAN1_6", - "CMT_FIFO_L_FAN1_7", - "CMT_FIFO_L_FAN1_8", - "CMT_FIFO_L_FAN1_9", - "CMT_FIFO_L_FAN2_0", - "CMT_FIFO_L_FAN2_1", - "CMT_FIFO_L_FAN2_10", - "CMT_FIFO_L_FAN2_11", - "CMT_FIFO_L_FAN2_2", - "CMT_FIFO_L_FAN2_3", - "CMT_FIFO_L_FAN2_4", - "CMT_FIFO_L_FAN2_5", - "CMT_FIFO_L_FAN2_6", - "CMT_FIFO_L_FAN2_7", - "CMT_FIFO_L_FAN2_8", - "CMT_FIFO_L_FAN2_9", - "CMT_FIFO_L_FAN3_0", - "CMT_FIFO_L_FAN3_1", - "CMT_FIFO_L_FAN3_10", - "CMT_FIFO_L_FAN3_11", - "CMT_FIFO_L_FAN3_2", - "CMT_FIFO_L_FAN3_3", - "CMT_FIFO_L_FAN3_4", - "CMT_FIFO_L_FAN3_5", - "CMT_FIFO_L_FAN3_6", - "CMT_FIFO_L_FAN3_7", - "CMT_FIFO_L_FAN3_8", - "CMT_FIFO_L_FAN3_9", - "CMT_FIFO_L_FAN4_0", - "CMT_FIFO_L_FAN4_1", - "CMT_FIFO_L_FAN4_10", - "CMT_FIFO_L_FAN4_11", - "CMT_FIFO_L_FAN4_2", - "CMT_FIFO_L_FAN4_3", - "CMT_FIFO_L_FAN4_4", - "CMT_FIFO_L_FAN4_5", - "CMT_FIFO_L_FAN4_6", - "CMT_FIFO_L_FAN4_7", - "CMT_FIFO_L_FAN4_8", - "CMT_FIFO_L_FAN4_9", - "CMT_FIFO_L_FAN5_0", - "CMT_FIFO_L_FAN5_1", - "CMT_FIFO_L_FAN5_10", - "CMT_FIFO_L_FAN5_11", - "CMT_FIFO_L_FAN5_2", - "CMT_FIFO_L_FAN5_3", - "CMT_FIFO_L_FAN5_4", - "CMT_FIFO_L_FAN5_5", - "CMT_FIFO_L_FAN5_6", - "CMT_FIFO_L_FAN5_7", - "CMT_FIFO_L_FAN5_8", - "CMT_FIFO_L_FAN5_9", - "CMT_FIFO_L_FAN6_0", - "CMT_FIFO_L_FAN6_1", - "CMT_FIFO_L_FAN6_10", - "CMT_FIFO_L_FAN6_11", - "CMT_FIFO_L_FAN6_2", - "CMT_FIFO_L_FAN6_3", - "CMT_FIFO_L_FAN6_4", - "CMT_FIFO_L_FAN6_5", - "CMT_FIFO_L_FAN6_6", - "CMT_FIFO_L_FAN6_7", - "CMT_FIFO_L_FAN6_8", - "CMT_FIFO_L_FAN6_9", - "CMT_FIFO_L_FAN7_0", - "CMT_FIFO_L_FAN7_1", - "CMT_FIFO_L_FAN7_10", - "CMT_FIFO_L_FAN7_11", - "CMT_FIFO_L_FAN7_2", - "CMT_FIFO_L_FAN7_3", - "CMT_FIFO_L_FAN7_4", - "CMT_FIFO_L_FAN7_5", - "CMT_FIFO_L_FAN7_6", - "CMT_FIFO_L_FAN7_7", - "CMT_FIFO_L_FAN7_8", - "CMT_FIFO_L_FAN7_9", - "CMT_FIFO_L_IMUX0_0", - "CMT_FIFO_L_IMUX0_1", - "CMT_FIFO_L_IMUX0_10", - "CMT_FIFO_L_IMUX0_11", - "CMT_FIFO_L_IMUX0_2", - "CMT_FIFO_L_IMUX0_3", - "CMT_FIFO_L_IMUX0_4", - "CMT_FIFO_L_IMUX0_5", - "CMT_FIFO_L_IMUX0_6", - "CMT_FIFO_L_IMUX0_7", - "CMT_FIFO_L_IMUX0_8", - "CMT_FIFO_L_IMUX0_9", - "CMT_FIFO_L_IMUX10_0", - "CMT_FIFO_L_IMUX10_1", - "CMT_FIFO_L_IMUX10_10", - "CMT_FIFO_L_IMUX10_11", - "CMT_FIFO_L_IMUX10_2", - "CMT_FIFO_L_IMUX10_3", - "CMT_FIFO_L_IMUX10_4", - "CMT_FIFO_L_IMUX10_5", - "CMT_FIFO_L_IMUX10_6", - "CMT_FIFO_L_IMUX10_7", - "CMT_FIFO_L_IMUX10_8", - "CMT_FIFO_L_IMUX10_9", - "CMT_FIFO_L_IMUX11_0", - "CMT_FIFO_L_IMUX11_1", - "CMT_FIFO_L_IMUX11_10", - "CMT_FIFO_L_IMUX11_11", - "CMT_FIFO_L_IMUX11_2", - "CMT_FIFO_L_IMUX11_3", - "CMT_FIFO_L_IMUX11_4", - "CMT_FIFO_L_IMUX11_5", - "CMT_FIFO_L_IMUX11_6", - "CMT_FIFO_L_IMUX11_7", - "CMT_FIFO_L_IMUX11_8", - "CMT_FIFO_L_IMUX11_9", - "CMT_FIFO_L_IMUX12_0", - "CMT_FIFO_L_IMUX12_1", - "CMT_FIFO_L_IMUX12_10", - "CMT_FIFO_L_IMUX12_11", - "CMT_FIFO_L_IMUX12_2", - "CMT_FIFO_L_IMUX12_3", - "CMT_FIFO_L_IMUX12_4", - "CMT_FIFO_L_IMUX12_5", - "CMT_FIFO_L_IMUX12_6", - "CMT_FIFO_L_IMUX12_7", - "CMT_FIFO_L_IMUX12_8", - "CMT_FIFO_L_IMUX12_9", - "CMT_FIFO_L_IMUX13_0", - "CMT_FIFO_L_IMUX13_1", - "CMT_FIFO_L_IMUX13_10", - "CMT_FIFO_L_IMUX13_11", - "CMT_FIFO_L_IMUX13_2", - "CMT_FIFO_L_IMUX13_3", - "CMT_FIFO_L_IMUX13_4", - "CMT_FIFO_L_IMUX13_5", - "CMT_FIFO_L_IMUX13_6", - "CMT_FIFO_L_IMUX13_7", - "CMT_FIFO_L_IMUX13_8", - "CMT_FIFO_L_IMUX13_9", - "CMT_FIFO_L_IMUX14_0", - "CMT_FIFO_L_IMUX14_1", - "CMT_FIFO_L_IMUX14_10", - "CMT_FIFO_L_IMUX14_11", - "CMT_FIFO_L_IMUX14_2", - "CMT_FIFO_L_IMUX14_3", - "CMT_FIFO_L_IMUX14_4", - "CMT_FIFO_L_IMUX14_5", - "CMT_FIFO_L_IMUX14_6", - "CMT_FIFO_L_IMUX14_7", - "CMT_FIFO_L_IMUX14_8", - "CMT_FIFO_L_IMUX14_9", - "CMT_FIFO_L_IMUX15_0", - "CMT_FIFO_L_IMUX15_1", - "CMT_FIFO_L_IMUX15_10", - "CMT_FIFO_L_IMUX15_11", - "CMT_FIFO_L_IMUX15_2", - "CMT_FIFO_L_IMUX15_3", - "CMT_FIFO_L_IMUX15_4", - "CMT_FIFO_L_IMUX15_5", - "CMT_FIFO_L_IMUX15_6", - "CMT_FIFO_L_IMUX15_7", - "CMT_FIFO_L_IMUX15_8", - "CMT_FIFO_L_IMUX15_9", - "CMT_FIFO_L_IMUX16_0", - "CMT_FIFO_L_IMUX16_1", - "CMT_FIFO_L_IMUX16_10", - "CMT_FIFO_L_IMUX16_11", - "CMT_FIFO_L_IMUX16_2", - "CMT_FIFO_L_IMUX16_3", - "CMT_FIFO_L_IMUX16_4", - "CMT_FIFO_L_IMUX16_5", - "CMT_FIFO_L_IMUX16_6", - "CMT_FIFO_L_IMUX16_7", - "CMT_FIFO_L_IMUX16_8", - "CMT_FIFO_L_IMUX16_9", - "CMT_FIFO_L_IMUX17_0", - "CMT_FIFO_L_IMUX17_1", - "CMT_FIFO_L_IMUX17_10", - "CMT_FIFO_L_IMUX17_11", - "CMT_FIFO_L_IMUX17_2", - "CMT_FIFO_L_IMUX17_3", - "CMT_FIFO_L_IMUX17_4", - "CMT_FIFO_L_IMUX17_5", - "CMT_FIFO_L_IMUX17_6", - "CMT_FIFO_L_IMUX17_7", - "CMT_FIFO_L_IMUX17_8", - "CMT_FIFO_L_IMUX17_9", - "CMT_FIFO_L_IMUX18_0", - "CMT_FIFO_L_IMUX18_1", - "CMT_FIFO_L_IMUX18_10", - "CMT_FIFO_L_IMUX18_11", - "CMT_FIFO_L_IMUX18_2", - "CMT_FIFO_L_IMUX18_3", - "CMT_FIFO_L_IMUX18_4", - "CMT_FIFO_L_IMUX18_5", - "CMT_FIFO_L_IMUX18_6", - "CMT_FIFO_L_IMUX18_7", - "CMT_FIFO_L_IMUX18_8", - "CMT_FIFO_L_IMUX18_9", - "CMT_FIFO_L_IMUX19_0", - "CMT_FIFO_L_IMUX19_1", - "CMT_FIFO_L_IMUX19_10", - "CMT_FIFO_L_IMUX19_11", - "CMT_FIFO_L_IMUX19_2", - "CMT_FIFO_L_IMUX19_3", - "CMT_FIFO_L_IMUX19_4", - "CMT_FIFO_L_IMUX19_5", - "CMT_FIFO_L_IMUX19_6", - "CMT_FIFO_L_IMUX19_7", - "CMT_FIFO_L_IMUX19_8", - "CMT_FIFO_L_IMUX19_9", - "CMT_FIFO_L_IMUX1_0", - "CMT_FIFO_L_IMUX1_1", - "CMT_FIFO_L_IMUX1_10", - "CMT_FIFO_L_IMUX1_11", - "CMT_FIFO_L_IMUX1_2", - "CMT_FIFO_L_IMUX1_3", - "CMT_FIFO_L_IMUX1_4", - "CMT_FIFO_L_IMUX1_5", - "CMT_FIFO_L_IMUX1_6", - "CMT_FIFO_L_IMUX1_7", - "CMT_FIFO_L_IMUX1_8", - "CMT_FIFO_L_IMUX1_9", - "CMT_FIFO_L_IMUX20_0", - "CMT_FIFO_L_IMUX20_1", - "CMT_FIFO_L_IMUX20_10", - "CMT_FIFO_L_IMUX20_11", - "CMT_FIFO_L_IMUX20_2", - "CMT_FIFO_L_IMUX20_3", - "CMT_FIFO_L_IMUX20_4", - "CMT_FIFO_L_IMUX20_5", - "CMT_FIFO_L_IMUX20_6", - "CMT_FIFO_L_IMUX20_7", - "CMT_FIFO_L_IMUX20_8", - "CMT_FIFO_L_IMUX20_9", - "CMT_FIFO_L_IMUX21_0", - "CMT_FIFO_L_IMUX21_1", - "CMT_FIFO_L_IMUX21_10", - "CMT_FIFO_L_IMUX21_11", - "CMT_FIFO_L_IMUX21_2", - "CMT_FIFO_L_IMUX21_3", - "CMT_FIFO_L_IMUX21_4", - "CMT_FIFO_L_IMUX21_5", - "CMT_FIFO_L_IMUX21_6", - "CMT_FIFO_L_IMUX21_7", - "CMT_FIFO_L_IMUX21_8", - "CMT_FIFO_L_IMUX21_9", - "CMT_FIFO_L_IMUX22_0", - "CMT_FIFO_L_IMUX22_1", - "CMT_FIFO_L_IMUX22_10", - "CMT_FIFO_L_IMUX22_11", - "CMT_FIFO_L_IMUX22_2", - "CMT_FIFO_L_IMUX22_3", - "CMT_FIFO_L_IMUX22_4", - "CMT_FIFO_L_IMUX22_5", - "CMT_FIFO_L_IMUX22_6", - "CMT_FIFO_L_IMUX22_7", - "CMT_FIFO_L_IMUX22_8", - "CMT_FIFO_L_IMUX22_9", - "CMT_FIFO_L_IMUX23_0", - "CMT_FIFO_L_IMUX23_1", - "CMT_FIFO_L_IMUX23_10", - "CMT_FIFO_L_IMUX23_11", - "CMT_FIFO_L_IMUX23_2", - "CMT_FIFO_L_IMUX23_3", - "CMT_FIFO_L_IMUX23_4", - "CMT_FIFO_L_IMUX23_5", - "CMT_FIFO_L_IMUX23_6", - "CMT_FIFO_L_IMUX23_7", - "CMT_FIFO_L_IMUX23_8", - "CMT_FIFO_L_IMUX23_9", - "CMT_FIFO_L_IMUX24_0", - "CMT_FIFO_L_IMUX24_1", - "CMT_FIFO_L_IMUX24_10", - "CMT_FIFO_L_IMUX24_11", - "CMT_FIFO_L_IMUX24_2", - "CMT_FIFO_L_IMUX24_3", - "CMT_FIFO_L_IMUX24_4", - "CMT_FIFO_L_IMUX24_5", - "CMT_FIFO_L_IMUX24_6", - "CMT_FIFO_L_IMUX24_7", - "CMT_FIFO_L_IMUX24_8", - "CMT_FIFO_L_IMUX24_9", - "CMT_FIFO_L_IMUX25_0", - "CMT_FIFO_L_IMUX25_1", - "CMT_FIFO_L_IMUX25_10", - "CMT_FIFO_L_IMUX25_11", - "CMT_FIFO_L_IMUX25_2", - "CMT_FIFO_L_IMUX25_3", - "CMT_FIFO_L_IMUX25_4", - "CMT_FIFO_L_IMUX25_5", - "CMT_FIFO_L_IMUX25_6", - "CMT_FIFO_L_IMUX25_7", - "CMT_FIFO_L_IMUX25_8", - "CMT_FIFO_L_IMUX25_9", - "CMT_FIFO_L_IMUX26_0", - "CMT_FIFO_L_IMUX26_1", - "CMT_FIFO_L_IMUX26_10", - "CMT_FIFO_L_IMUX26_11", - "CMT_FIFO_L_IMUX26_2", - "CMT_FIFO_L_IMUX26_3", - "CMT_FIFO_L_IMUX26_4", - "CMT_FIFO_L_IMUX26_5", - "CMT_FIFO_L_IMUX26_6", - "CMT_FIFO_L_IMUX26_7", - "CMT_FIFO_L_IMUX26_8", - "CMT_FIFO_L_IMUX26_9", - "CMT_FIFO_L_IMUX27_0", - "CMT_FIFO_L_IMUX27_1", - "CMT_FIFO_L_IMUX27_10", - "CMT_FIFO_L_IMUX27_11", - "CMT_FIFO_L_IMUX27_2", - "CMT_FIFO_L_IMUX27_3", - "CMT_FIFO_L_IMUX27_4", - "CMT_FIFO_L_IMUX27_5", - "CMT_FIFO_L_IMUX27_6", - "CMT_FIFO_L_IMUX27_7", - "CMT_FIFO_L_IMUX27_8", - "CMT_FIFO_L_IMUX27_9", - "CMT_FIFO_L_IMUX28_0", - "CMT_FIFO_L_IMUX28_1", - "CMT_FIFO_L_IMUX28_10", - "CMT_FIFO_L_IMUX28_11", - "CMT_FIFO_L_IMUX28_2", - "CMT_FIFO_L_IMUX28_3", - "CMT_FIFO_L_IMUX28_4", - "CMT_FIFO_L_IMUX28_5", - "CMT_FIFO_L_IMUX28_6", - "CMT_FIFO_L_IMUX28_7", - "CMT_FIFO_L_IMUX28_8", - "CMT_FIFO_L_IMUX28_9", - "CMT_FIFO_L_IMUX29_0", - "CMT_FIFO_L_IMUX29_1", - "CMT_FIFO_L_IMUX29_10", - "CMT_FIFO_L_IMUX29_11", - "CMT_FIFO_L_IMUX29_2", - "CMT_FIFO_L_IMUX29_3", - "CMT_FIFO_L_IMUX29_4", - "CMT_FIFO_L_IMUX29_5", - "CMT_FIFO_L_IMUX29_6", - "CMT_FIFO_L_IMUX29_7", - "CMT_FIFO_L_IMUX29_8", - "CMT_FIFO_L_IMUX29_9", - "CMT_FIFO_L_IMUX2_0", - "CMT_FIFO_L_IMUX2_1", - "CMT_FIFO_L_IMUX2_10", - "CMT_FIFO_L_IMUX2_11", - "CMT_FIFO_L_IMUX2_2", - "CMT_FIFO_L_IMUX2_3", - "CMT_FIFO_L_IMUX2_4", - "CMT_FIFO_L_IMUX2_5", - "CMT_FIFO_L_IMUX2_6", - "CMT_FIFO_L_IMUX2_7", - "CMT_FIFO_L_IMUX2_8", - "CMT_FIFO_L_IMUX2_9", - "CMT_FIFO_L_IMUX30_0", - "CMT_FIFO_L_IMUX30_1", - "CMT_FIFO_L_IMUX30_10", - "CMT_FIFO_L_IMUX30_11", - "CMT_FIFO_L_IMUX30_2", - "CMT_FIFO_L_IMUX30_3", - "CMT_FIFO_L_IMUX30_4", - "CMT_FIFO_L_IMUX30_5", - "CMT_FIFO_L_IMUX30_6", - "CMT_FIFO_L_IMUX30_7", - "CMT_FIFO_L_IMUX30_8", - "CMT_FIFO_L_IMUX30_9", - "CMT_FIFO_L_IMUX31_0", - "CMT_FIFO_L_IMUX31_1", - "CMT_FIFO_L_IMUX31_10", - "CMT_FIFO_L_IMUX31_11", - "CMT_FIFO_L_IMUX31_2", - "CMT_FIFO_L_IMUX31_3", - "CMT_FIFO_L_IMUX31_4", - "CMT_FIFO_L_IMUX31_5", - "CMT_FIFO_L_IMUX31_6", - "CMT_FIFO_L_IMUX31_7", - "CMT_FIFO_L_IMUX31_8", - "CMT_FIFO_L_IMUX31_9", - "CMT_FIFO_L_IMUX32_0", - "CMT_FIFO_L_IMUX32_1", - "CMT_FIFO_L_IMUX32_10", - "CMT_FIFO_L_IMUX32_11", - "CMT_FIFO_L_IMUX32_2", - "CMT_FIFO_L_IMUX32_3", - "CMT_FIFO_L_IMUX32_4", - "CMT_FIFO_L_IMUX32_5", - "CMT_FIFO_L_IMUX32_6", - "CMT_FIFO_L_IMUX32_7", - "CMT_FIFO_L_IMUX32_8", - "CMT_FIFO_L_IMUX32_9", - "CMT_FIFO_L_IMUX33_0", - "CMT_FIFO_L_IMUX33_1", - "CMT_FIFO_L_IMUX33_10", - "CMT_FIFO_L_IMUX33_11", - "CMT_FIFO_L_IMUX33_2", - "CMT_FIFO_L_IMUX33_3", - "CMT_FIFO_L_IMUX33_4", - "CMT_FIFO_L_IMUX33_5", - "CMT_FIFO_L_IMUX33_6", - "CMT_FIFO_L_IMUX33_7", - "CMT_FIFO_L_IMUX33_8", - "CMT_FIFO_L_IMUX33_9", - "CMT_FIFO_L_IMUX34_0", - "CMT_FIFO_L_IMUX34_1", - "CMT_FIFO_L_IMUX34_10", - "CMT_FIFO_L_IMUX34_11", - "CMT_FIFO_L_IMUX34_2", - "CMT_FIFO_L_IMUX34_3", - "CMT_FIFO_L_IMUX34_4", - "CMT_FIFO_L_IMUX34_5", - "CMT_FIFO_L_IMUX34_6", - "CMT_FIFO_L_IMUX34_7", - "CMT_FIFO_L_IMUX34_8", - "CMT_FIFO_L_IMUX34_9", - "CMT_FIFO_L_IMUX35_0", - "CMT_FIFO_L_IMUX35_1", - "CMT_FIFO_L_IMUX35_10", - "CMT_FIFO_L_IMUX35_11", - "CMT_FIFO_L_IMUX35_2", - "CMT_FIFO_L_IMUX35_3", - "CMT_FIFO_L_IMUX35_4", - "CMT_FIFO_L_IMUX35_5", - "CMT_FIFO_L_IMUX35_6", - "CMT_FIFO_L_IMUX35_7", - "CMT_FIFO_L_IMUX35_8", - "CMT_FIFO_L_IMUX35_9", - "CMT_FIFO_L_IMUX36_0", - "CMT_FIFO_L_IMUX36_1", - "CMT_FIFO_L_IMUX36_10", - "CMT_FIFO_L_IMUX36_11", - "CMT_FIFO_L_IMUX36_2", - "CMT_FIFO_L_IMUX36_3", - "CMT_FIFO_L_IMUX36_4", - "CMT_FIFO_L_IMUX36_5", - "CMT_FIFO_L_IMUX36_6", - "CMT_FIFO_L_IMUX36_7", - "CMT_FIFO_L_IMUX36_8", - "CMT_FIFO_L_IMUX36_9", - "CMT_FIFO_L_IMUX37_0", - "CMT_FIFO_L_IMUX37_1", - "CMT_FIFO_L_IMUX37_10", - "CMT_FIFO_L_IMUX37_11", - "CMT_FIFO_L_IMUX37_2", - "CMT_FIFO_L_IMUX37_3", - "CMT_FIFO_L_IMUX37_4", - "CMT_FIFO_L_IMUX37_5", - "CMT_FIFO_L_IMUX37_6", - "CMT_FIFO_L_IMUX37_7", - "CMT_FIFO_L_IMUX37_8", - "CMT_FIFO_L_IMUX37_9", - "CMT_FIFO_L_IMUX38_0", - "CMT_FIFO_L_IMUX38_1", - "CMT_FIFO_L_IMUX38_10", - "CMT_FIFO_L_IMUX38_11", - "CMT_FIFO_L_IMUX38_2", - "CMT_FIFO_L_IMUX38_3", - "CMT_FIFO_L_IMUX38_4", - "CMT_FIFO_L_IMUX38_5", - "CMT_FIFO_L_IMUX38_6", - "CMT_FIFO_L_IMUX38_7", - "CMT_FIFO_L_IMUX38_8", - "CMT_FIFO_L_IMUX38_9", - "CMT_FIFO_L_IMUX39_0", - "CMT_FIFO_L_IMUX39_1", - "CMT_FIFO_L_IMUX39_10", - "CMT_FIFO_L_IMUX39_11", - "CMT_FIFO_L_IMUX39_2", - "CMT_FIFO_L_IMUX39_3", - "CMT_FIFO_L_IMUX39_4", - "CMT_FIFO_L_IMUX39_5", - "CMT_FIFO_L_IMUX39_6", - "CMT_FIFO_L_IMUX39_7", - "CMT_FIFO_L_IMUX39_8", - "CMT_FIFO_L_IMUX39_9", - "CMT_FIFO_L_IMUX3_0", - "CMT_FIFO_L_IMUX3_1", - "CMT_FIFO_L_IMUX3_10", - "CMT_FIFO_L_IMUX3_11", - "CMT_FIFO_L_IMUX3_2", - "CMT_FIFO_L_IMUX3_3", - "CMT_FIFO_L_IMUX3_4", - "CMT_FIFO_L_IMUX3_5", - "CMT_FIFO_L_IMUX3_6", - "CMT_FIFO_L_IMUX3_7", - "CMT_FIFO_L_IMUX3_8", - "CMT_FIFO_L_IMUX3_9", - "CMT_FIFO_L_IMUX40_0", - "CMT_FIFO_L_IMUX40_1", - "CMT_FIFO_L_IMUX40_10", - "CMT_FIFO_L_IMUX40_11", - "CMT_FIFO_L_IMUX40_2", - "CMT_FIFO_L_IMUX40_3", - "CMT_FIFO_L_IMUX40_4", - "CMT_FIFO_L_IMUX40_5", - "CMT_FIFO_L_IMUX40_6", - "CMT_FIFO_L_IMUX40_7", - "CMT_FIFO_L_IMUX40_8", - "CMT_FIFO_L_IMUX40_9", - "CMT_FIFO_L_IMUX41_0", - "CMT_FIFO_L_IMUX41_1", - "CMT_FIFO_L_IMUX41_10", - "CMT_FIFO_L_IMUX41_11", - "CMT_FIFO_L_IMUX41_2", - "CMT_FIFO_L_IMUX41_3", - "CMT_FIFO_L_IMUX41_4", - "CMT_FIFO_L_IMUX41_5", - "CMT_FIFO_L_IMUX41_6", - "CMT_FIFO_L_IMUX41_7", - "CMT_FIFO_L_IMUX41_8", - "CMT_FIFO_L_IMUX41_9", - "CMT_FIFO_L_IMUX42_0", - "CMT_FIFO_L_IMUX42_1", - "CMT_FIFO_L_IMUX42_10", - "CMT_FIFO_L_IMUX42_11", - "CMT_FIFO_L_IMUX42_2", - "CMT_FIFO_L_IMUX42_3", - "CMT_FIFO_L_IMUX42_4", - "CMT_FIFO_L_IMUX42_5", - "CMT_FIFO_L_IMUX42_6", - "CMT_FIFO_L_IMUX42_7", - "CMT_FIFO_L_IMUX42_8", - "CMT_FIFO_L_IMUX42_9", - "CMT_FIFO_L_IMUX43_0", - "CMT_FIFO_L_IMUX43_1", - "CMT_FIFO_L_IMUX43_10", - "CMT_FIFO_L_IMUX43_11", - "CMT_FIFO_L_IMUX43_2", - "CMT_FIFO_L_IMUX43_3", - "CMT_FIFO_L_IMUX43_4", - "CMT_FIFO_L_IMUX43_5", - "CMT_FIFO_L_IMUX43_6", - "CMT_FIFO_L_IMUX43_7", - "CMT_FIFO_L_IMUX43_8", - "CMT_FIFO_L_IMUX43_9", - "CMT_FIFO_L_IMUX44_0", - "CMT_FIFO_L_IMUX44_1", - "CMT_FIFO_L_IMUX44_10", - "CMT_FIFO_L_IMUX44_11", - "CMT_FIFO_L_IMUX44_2", - "CMT_FIFO_L_IMUX44_3", - "CMT_FIFO_L_IMUX44_4", - "CMT_FIFO_L_IMUX44_5", - "CMT_FIFO_L_IMUX44_6", - "CMT_FIFO_L_IMUX44_7", - "CMT_FIFO_L_IMUX44_8", - "CMT_FIFO_L_IMUX44_9", - "CMT_FIFO_L_IMUX45_0", - "CMT_FIFO_L_IMUX45_1", - "CMT_FIFO_L_IMUX45_10", - "CMT_FIFO_L_IMUX45_11", - "CMT_FIFO_L_IMUX45_2", - "CMT_FIFO_L_IMUX45_3", - "CMT_FIFO_L_IMUX45_4", - "CMT_FIFO_L_IMUX45_5", - "CMT_FIFO_L_IMUX45_6", - "CMT_FIFO_L_IMUX45_7", - "CMT_FIFO_L_IMUX45_8", - "CMT_FIFO_L_IMUX45_9", - "CMT_FIFO_L_IMUX46_0", - "CMT_FIFO_L_IMUX46_1", - "CMT_FIFO_L_IMUX46_10", - "CMT_FIFO_L_IMUX46_11", - "CMT_FIFO_L_IMUX46_2", - "CMT_FIFO_L_IMUX46_3", - "CMT_FIFO_L_IMUX46_4", - "CMT_FIFO_L_IMUX46_5", - "CMT_FIFO_L_IMUX46_6", - "CMT_FIFO_L_IMUX46_7", - "CMT_FIFO_L_IMUX46_8", - "CMT_FIFO_L_IMUX46_9", - "CMT_FIFO_L_IMUX47_0", - "CMT_FIFO_L_IMUX47_1", - "CMT_FIFO_L_IMUX47_10", - "CMT_FIFO_L_IMUX47_11", - "CMT_FIFO_L_IMUX47_2", - "CMT_FIFO_L_IMUX47_3", - "CMT_FIFO_L_IMUX47_4", - "CMT_FIFO_L_IMUX47_5", - "CMT_FIFO_L_IMUX47_6", - "CMT_FIFO_L_IMUX47_7", - "CMT_FIFO_L_IMUX47_8", - "CMT_FIFO_L_IMUX47_9", - "CMT_FIFO_L_IMUX4_0", - "CMT_FIFO_L_IMUX4_1", - "CMT_FIFO_L_IMUX4_10", - "CMT_FIFO_L_IMUX4_11", - "CMT_FIFO_L_IMUX4_2", - "CMT_FIFO_L_IMUX4_3", - "CMT_FIFO_L_IMUX4_4", - "CMT_FIFO_L_IMUX4_5", - "CMT_FIFO_L_IMUX4_6", - "CMT_FIFO_L_IMUX4_7", - "CMT_FIFO_L_IMUX4_8", - "CMT_FIFO_L_IMUX4_9", - "CMT_FIFO_L_IMUX5_0", - "CMT_FIFO_L_IMUX5_1", - "CMT_FIFO_L_IMUX5_10", - "CMT_FIFO_L_IMUX5_11", - "CMT_FIFO_L_IMUX5_2", - "CMT_FIFO_L_IMUX5_3", - "CMT_FIFO_L_IMUX5_4", - "CMT_FIFO_L_IMUX5_5", - "CMT_FIFO_L_IMUX5_6", - "CMT_FIFO_L_IMUX5_7", - "CMT_FIFO_L_IMUX5_8", - "CMT_FIFO_L_IMUX5_9", - "CMT_FIFO_L_IMUX6_0", - "CMT_FIFO_L_IMUX6_1", - "CMT_FIFO_L_IMUX6_10", - "CMT_FIFO_L_IMUX6_11", - "CMT_FIFO_L_IMUX6_2", - "CMT_FIFO_L_IMUX6_3", - "CMT_FIFO_L_IMUX6_4", - "CMT_FIFO_L_IMUX6_5", - "CMT_FIFO_L_IMUX6_6", - "CMT_FIFO_L_IMUX6_7", - "CMT_FIFO_L_IMUX6_8", - "CMT_FIFO_L_IMUX6_9", - "CMT_FIFO_L_IMUX7_0", - "CMT_FIFO_L_IMUX7_1", - "CMT_FIFO_L_IMUX7_10", - "CMT_FIFO_L_IMUX7_11", - "CMT_FIFO_L_IMUX7_2", - "CMT_FIFO_L_IMUX7_3", - "CMT_FIFO_L_IMUX7_4", - "CMT_FIFO_L_IMUX7_5", - "CMT_FIFO_L_IMUX7_6", - "CMT_FIFO_L_IMUX7_7", - "CMT_FIFO_L_IMUX7_8", - "CMT_FIFO_L_IMUX7_9", - "CMT_FIFO_L_IMUX8_0", - "CMT_FIFO_L_IMUX8_1", - "CMT_FIFO_L_IMUX8_10", - "CMT_FIFO_L_IMUX8_11", - "CMT_FIFO_L_IMUX8_2", - "CMT_FIFO_L_IMUX8_3", - "CMT_FIFO_L_IMUX8_4", - "CMT_FIFO_L_IMUX8_5", - "CMT_FIFO_L_IMUX8_6", - "CMT_FIFO_L_IMUX8_7", - "CMT_FIFO_L_IMUX8_8", - "CMT_FIFO_L_IMUX8_9", - "CMT_FIFO_L_IMUX9_0", - "CMT_FIFO_L_IMUX9_1", - "CMT_FIFO_L_IMUX9_10", - "CMT_FIFO_L_IMUX9_11", - "CMT_FIFO_L_IMUX9_2", - "CMT_FIFO_L_IMUX9_3", - "CMT_FIFO_L_IMUX9_4", - "CMT_FIFO_L_IMUX9_5", - "CMT_FIFO_L_IMUX9_6", - "CMT_FIFO_L_IMUX9_7", - "CMT_FIFO_L_IMUX9_8", - "CMT_FIFO_L_IMUX9_9", - "CMT_FIFO_L_LOGIC_OUTS0_0", - "CMT_FIFO_L_LOGIC_OUTS0_1", - "CMT_FIFO_L_LOGIC_OUTS0_10", - "CMT_FIFO_L_LOGIC_OUTS0_11", - "CMT_FIFO_L_LOGIC_OUTS0_2", - "CMT_FIFO_L_LOGIC_OUTS0_3", - "CMT_FIFO_L_LOGIC_OUTS0_4", - "CMT_FIFO_L_LOGIC_OUTS0_5", - "CMT_FIFO_L_LOGIC_OUTS0_6", - "CMT_FIFO_L_LOGIC_OUTS0_7", - "CMT_FIFO_L_LOGIC_OUTS0_8", - "CMT_FIFO_L_LOGIC_OUTS0_9", - "CMT_FIFO_L_LOGIC_OUTS10_0", - "CMT_FIFO_L_LOGIC_OUTS10_1", - "CMT_FIFO_L_LOGIC_OUTS10_10", - "CMT_FIFO_L_LOGIC_OUTS10_11", - "CMT_FIFO_L_LOGIC_OUTS10_2", - "CMT_FIFO_L_LOGIC_OUTS10_3", - "CMT_FIFO_L_LOGIC_OUTS10_4", - "CMT_FIFO_L_LOGIC_OUTS10_5", - "CMT_FIFO_L_LOGIC_OUTS10_6", - "CMT_FIFO_L_LOGIC_OUTS10_7", - "CMT_FIFO_L_LOGIC_OUTS10_8", - "CMT_FIFO_L_LOGIC_OUTS10_9", - "CMT_FIFO_L_LOGIC_OUTS11_0", - "CMT_FIFO_L_LOGIC_OUTS11_1", - "CMT_FIFO_L_LOGIC_OUTS11_10", - "CMT_FIFO_L_LOGIC_OUTS11_11", - "CMT_FIFO_L_LOGIC_OUTS11_2", - "CMT_FIFO_L_LOGIC_OUTS11_3", - "CMT_FIFO_L_LOGIC_OUTS11_4", - "CMT_FIFO_L_LOGIC_OUTS11_5", - "CMT_FIFO_L_LOGIC_OUTS11_6", - "CMT_FIFO_L_LOGIC_OUTS11_7", - "CMT_FIFO_L_LOGIC_OUTS11_8", - "CMT_FIFO_L_LOGIC_OUTS11_9", - "CMT_FIFO_L_LOGIC_OUTS12_0", - "CMT_FIFO_L_LOGIC_OUTS12_1", - "CMT_FIFO_L_LOGIC_OUTS12_10", - "CMT_FIFO_L_LOGIC_OUTS12_11", - "CMT_FIFO_L_LOGIC_OUTS12_2", - "CMT_FIFO_L_LOGIC_OUTS12_3", - "CMT_FIFO_L_LOGIC_OUTS12_4", - "CMT_FIFO_L_LOGIC_OUTS12_5", - "CMT_FIFO_L_LOGIC_OUTS12_6", - "CMT_FIFO_L_LOGIC_OUTS12_7", - "CMT_FIFO_L_LOGIC_OUTS12_8", - "CMT_FIFO_L_LOGIC_OUTS12_9", - "CMT_FIFO_L_LOGIC_OUTS13_0", - "CMT_FIFO_L_LOGIC_OUTS13_1", - "CMT_FIFO_L_LOGIC_OUTS13_10", - "CMT_FIFO_L_LOGIC_OUTS13_11", - "CMT_FIFO_L_LOGIC_OUTS13_2", - "CMT_FIFO_L_LOGIC_OUTS13_3", - "CMT_FIFO_L_LOGIC_OUTS13_4", - "CMT_FIFO_L_LOGIC_OUTS13_5", - "CMT_FIFO_L_LOGIC_OUTS13_6", - "CMT_FIFO_L_LOGIC_OUTS13_7", - "CMT_FIFO_L_LOGIC_OUTS13_8", - "CMT_FIFO_L_LOGIC_OUTS13_9", - "CMT_FIFO_L_LOGIC_OUTS14_0", - "CMT_FIFO_L_LOGIC_OUTS14_1", - "CMT_FIFO_L_LOGIC_OUTS14_10", - "CMT_FIFO_L_LOGIC_OUTS14_11", - "CMT_FIFO_L_LOGIC_OUTS14_2", - "CMT_FIFO_L_LOGIC_OUTS14_3", - "CMT_FIFO_L_LOGIC_OUTS14_4", - "CMT_FIFO_L_LOGIC_OUTS14_5", - "CMT_FIFO_L_LOGIC_OUTS14_6", - "CMT_FIFO_L_LOGIC_OUTS14_7", - "CMT_FIFO_L_LOGIC_OUTS14_8", - "CMT_FIFO_L_LOGIC_OUTS14_9", - "CMT_FIFO_L_LOGIC_OUTS15_0", - "CMT_FIFO_L_LOGIC_OUTS15_1", - "CMT_FIFO_L_LOGIC_OUTS15_10", - "CMT_FIFO_L_LOGIC_OUTS15_11", - "CMT_FIFO_L_LOGIC_OUTS15_2", - "CMT_FIFO_L_LOGIC_OUTS15_3", - "CMT_FIFO_L_LOGIC_OUTS15_4", - "CMT_FIFO_L_LOGIC_OUTS15_5", - "CMT_FIFO_L_LOGIC_OUTS15_6", - "CMT_FIFO_L_LOGIC_OUTS15_7", - "CMT_FIFO_L_LOGIC_OUTS15_8", - "CMT_FIFO_L_LOGIC_OUTS15_9", - "CMT_FIFO_L_LOGIC_OUTS16_0", - "CMT_FIFO_L_LOGIC_OUTS16_1", - "CMT_FIFO_L_LOGIC_OUTS16_10", - "CMT_FIFO_L_LOGIC_OUTS16_11", - "CMT_FIFO_L_LOGIC_OUTS16_2", - "CMT_FIFO_L_LOGIC_OUTS16_3", - "CMT_FIFO_L_LOGIC_OUTS16_4", - "CMT_FIFO_L_LOGIC_OUTS16_5", - "CMT_FIFO_L_LOGIC_OUTS16_6", - "CMT_FIFO_L_LOGIC_OUTS16_7", - "CMT_FIFO_L_LOGIC_OUTS16_8", - "CMT_FIFO_L_LOGIC_OUTS16_9", - "CMT_FIFO_L_LOGIC_OUTS17_0", - "CMT_FIFO_L_LOGIC_OUTS17_1", - "CMT_FIFO_L_LOGIC_OUTS17_10", - "CMT_FIFO_L_LOGIC_OUTS17_11", - "CMT_FIFO_L_LOGIC_OUTS17_2", - "CMT_FIFO_L_LOGIC_OUTS17_3", - "CMT_FIFO_L_LOGIC_OUTS17_4", - "CMT_FIFO_L_LOGIC_OUTS17_5", - "CMT_FIFO_L_LOGIC_OUTS17_6", - "CMT_FIFO_L_LOGIC_OUTS17_7", - "CMT_FIFO_L_LOGIC_OUTS17_8", - "CMT_FIFO_L_LOGIC_OUTS17_9", - "CMT_FIFO_L_LOGIC_OUTS18_0", - "CMT_FIFO_L_LOGIC_OUTS18_1", - "CMT_FIFO_L_LOGIC_OUTS18_10", - "CMT_FIFO_L_LOGIC_OUTS18_11", - "CMT_FIFO_L_LOGIC_OUTS18_2", - "CMT_FIFO_L_LOGIC_OUTS18_3", - "CMT_FIFO_L_LOGIC_OUTS18_4", - "CMT_FIFO_L_LOGIC_OUTS18_5", - "CMT_FIFO_L_LOGIC_OUTS18_6", - "CMT_FIFO_L_LOGIC_OUTS18_7", - "CMT_FIFO_L_LOGIC_OUTS18_8", - "CMT_FIFO_L_LOGIC_OUTS18_9", - "CMT_FIFO_L_LOGIC_OUTS19_0", - "CMT_FIFO_L_LOGIC_OUTS19_1", - "CMT_FIFO_L_LOGIC_OUTS19_10", - "CMT_FIFO_L_LOGIC_OUTS19_11", - "CMT_FIFO_L_LOGIC_OUTS19_2", - "CMT_FIFO_L_LOGIC_OUTS19_3", - "CMT_FIFO_L_LOGIC_OUTS19_4", - "CMT_FIFO_L_LOGIC_OUTS19_5", - "CMT_FIFO_L_LOGIC_OUTS19_6", - "CMT_FIFO_L_LOGIC_OUTS19_7", - "CMT_FIFO_L_LOGIC_OUTS19_8", - "CMT_FIFO_L_LOGIC_OUTS19_9", - "CMT_FIFO_L_LOGIC_OUTS1_0", - "CMT_FIFO_L_LOGIC_OUTS1_1", - "CMT_FIFO_L_LOGIC_OUTS1_10", - "CMT_FIFO_L_LOGIC_OUTS1_11", - "CMT_FIFO_L_LOGIC_OUTS1_2", - "CMT_FIFO_L_LOGIC_OUTS1_3", - "CMT_FIFO_L_LOGIC_OUTS1_4", - "CMT_FIFO_L_LOGIC_OUTS1_5", - "CMT_FIFO_L_LOGIC_OUTS1_6", - "CMT_FIFO_L_LOGIC_OUTS1_7", - "CMT_FIFO_L_LOGIC_OUTS1_8", - "CMT_FIFO_L_LOGIC_OUTS1_9", - "CMT_FIFO_L_LOGIC_OUTS20_0", - "CMT_FIFO_L_LOGIC_OUTS20_1", - "CMT_FIFO_L_LOGIC_OUTS20_10", - "CMT_FIFO_L_LOGIC_OUTS20_11", - "CMT_FIFO_L_LOGIC_OUTS20_2", - "CMT_FIFO_L_LOGIC_OUTS20_3", - "CMT_FIFO_L_LOGIC_OUTS20_4", - "CMT_FIFO_L_LOGIC_OUTS20_5", - "CMT_FIFO_L_LOGIC_OUTS20_6", - "CMT_FIFO_L_LOGIC_OUTS20_7", - "CMT_FIFO_L_LOGIC_OUTS20_8", - "CMT_FIFO_L_LOGIC_OUTS20_9", - "CMT_FIFO_L_LOGIC_OUTS21_0", - "CMT_FIFO_L_LOGIC_OUTS21_1", - "CMT_FIFO_L_LOGIC_OUTS21_10", - "CMT_FIFO_L_LOGIC_OUTS21_11", - "CMT_FIFO_L_LOGIC_OUTS21_2", - "CMT_FIFO_L_LOGIC_OUTS21_3", - "CMT_FIFO_L_LOGIC_OUTS21_4", - "CMT_FIFO_L_LOGIC_OUTS21_5", - "CMT_FIFO_L_LOGIC_OUTS21_6", - "CMT_FIFO_L_LOGIC_OUTS21_7", - "CMT_FIFO_L_LOGIC_OUTS21_8", - "CMT_FIFO_L_LOGIC_OUTS21_9", - "CMT_FIFO_L_LOGIC_OUTS22_0", - "CMT_FIFO_L_LOGIC_OUTS22_1", - "CMT_FIFO_L_LOGIC_OUTS22_10", - "CMT_FIFO_L_LOGIC_OUTS22_11", - "CMT_FIFO_L_LOGIC_OUTS22_2", - "CMT_FIFO_L_LOGIC_OUTS22_3", - "CMT_FIFO_L_LOGIC_OUTS22_4", - "CMT_FIFO_L_LOGIC_OUTS22_5", - "CMT_FIFO_L_LOGIC_OUTS22_6", - "CMT_FIFO_L_LOGIC_OUTS22_7", - "CMT_FIFO_L_LOGIC_OUTS22_8", - "CMT_FIFO_L_LOGIC_OUTS22_9", - "CMT_FIFO_L_LOGIC_OUTS23_0", - "CMT_FIFO_L_LOGIC_OUTS23_1", - "CMT_FIFO_L_LOGIC_OUTS23_10", - "CMT_FIFO_L_LOGIC_OUTS23_11", - "CMT_FIFO_L_LOGIC_OUTS23_2", - "CMT_FIFO_L_LOGIC_OUTS23_3", - "CMT_FIFO_L_LOGIC_OUTS23_4", - "CMT_FIFO_L_LOGIC_OUTS23_5", - "CMT_FIFO_L_LOGIC_OUTS23_6", - "CMT_FIFO_L_LOGIC_OUTS23_7", - "CMT_FIFO_L_LOGIC_OUTS23_8", - "CMT_FIFO_L_LOGIC_OUTS23_9", - "CMT_FIFO_L_LOGIC_OUTS2_0", - "CMT_FIFO_L_LOGIC_OUTS2_1", - "CMT_FIFO_L_LOGIC_OUTS2_10", - "CMT_FIFO_L_LOGIC_OUTS2_11", - "CMT_FIFO_L_LOGIC_OUTS2_2", - "CMT_FIFO_L_LOGIC_OUTS2_3", - "CMT_FIFO_L_LOGIC_OUTS2_4", - "CMT_FIFO_L_LOGIC_OUTS2_5", - "CMT_FIFO_L_LOGIC_OUTS2_6", - "CMT_FIFO_L_LOGIC_OUTS2_7", - "CMT_FIFO_L_LOGIC_OUTS2_8", - "CMT_FIFO_L_LOGIC_OUTS2_9", - "CMT_FIFO_L_LOGIC_OUTS3_0", - "CMT_FIFO_L_LOGIC_OUTS3_1", - "CMT_FIFO_L_LOGIC_OUTS3_10", - "CMT_FIFO_L_LOGIC_OUTS3_11", - "CMT_FIFO_L_LOGIC_OUTS3_2", - "CMT_FIFO_L_LOGIC_OUTS3_3", - "CMT_FIFO_L_LOGIC_OUTS3_4", - "CMT_FIFO_L_LOGIC_OUTS3_5", - "CMT_FIFO_L_LOGIC_OUTS3_6", - "CMT_FIFO_L_LOGIC_OUTS3_7", - "CMT_FIFO_L_LOGIC_OUTS3_8", - "CMT_FIFO_L_LOGIC_OUTS3_9", - "CMT_FIFO_L_LOGIC_OUTS4_0", - "CMT_FIFO_L_LOGIC_OUTS4_1", - "CMT_FIFO_L_LOGIC_OUTS4_10", - "CMT_FIFO_L_LOGIC_OUTS4_11", - "CMT_FIFO_L_LOGIC_OUTS4_2", - "CMT_FIFO_L_LOGIC_OUTS4_3", - "CMT_FIFO_L_LOGIC_OUTS4_4", - "CMT_FIFO_L_LOGIC_OUTS4_5", - "CMT_FIFO_L_LOGIC_OUTS4_6", - "CMT_FIFO_L_LOGIC_OUTS4_7", - "CMT_FIFO_L_LOGIC_OUTS4_8", - "CMT_FIFO_L_LOGIC_OUTS4_9", - "CMT_FIFO_L_LOGIC_OUTS5_0", - "CMT_FIFO_L_LOGIC_OUTS5_1", - "CMT_FIFO_L_LOGIC_OUTS5_10", - "CMT_FIFO_L_LOGIC_OUTS5_11", - "CMT_FIFO_L_LOGIC_OUTS5_2", - "CMT_FIFO_L_LOGIC_OUTS5_3", - "CMT_FIFO_L_LOGIC_OUTS5_4", - "CMT_FIFO_L_LOGIC_OUTS5_5", - "CMT_FIFO_L_LOGIC_OUTS5_6", - "CMT_FIFO_L_LOGIC_OUTS5_7", - "CMT_FIFO_L_LOGIC_OUTS5_8", - "CMT_FIFO_L_LOGIC_OUTS5_9", - "CMT_FIFO_L_LOGIC_OUTS6_0", - "CMT_FIFO_L_LOGIC_OUTS6_1", - "CMT_FIFO_L_LOGIC_OUTS6_10", - "CMT_FIFO_L_LOGIC_OUTS6_11", - "CMT_FIFO_L_LOGIC_OUTS6_2", - "CMT_FIFO_L_LOGIC_OUTS6_3", - "CMT_FIFO_L_LOGIC_OUTS6_4", - "CMT_FIFO_L_LOGIC_OUTS6_5", - "CMT_FIFO_L_LOGIC_OUTS6_6", - "CMT_FIFO_L_LOGIC_OUTS6_7", - "CMT_FIFO_L_LOGIC_OUTS6_8", - "CMT_FIFO_L_LOGIC_OUTS6_9", - "CMT_FIFO_L_LOGIC_OUTS7_0", - "CMT_FIFO_L_LOGIC_OUTS7_1", - "CMT_FIFO_L_LOGIC_OUTS7_10", - "CMT_FIFO_L_LOGIC_OUTS7_11", - "CMT_FIFO_L_LOGIC_OUTS7_2", - "CMT_FIFO_L_LOGIC_OUTS7_3", - "CMT_FIFO_L_LOGIC_OUTS7_4", - "CMT_FIFO_L_LOGIC_OUTS7_5", - "CMT_FIFO_L_LOGIC_OUTS7_6", - "CMT_FIFO_L_LOGIC_OUTS7_7", - "CMT_FIFO_L_LOGIC_OUTS7_8", - "CMT_FIFO_L_LOGIC_OUTS7_9", - "CMT_FIFO_L_LOGIC_OUTS8_0", - "CMT_FIFO_L_LOGIC_OUTS8_1", - "CMT_FIFO_L_LOGIC_OUTS8_10", - "CMT_FIFO_L_LOGIC_OUTS8_11", - "CMT_FIFO_L_LOGIC_OUTS8_2", - "CMT_FIFO_L_LOGIC_OUTS8_3", - "CMT_FIFO_L_LOGIC_OUTS8_4", - "CMT_FIFO_L_LOGIC_OUTS8_5", - "CMT_FIFO_L_LOGIC_OUTS8_6", - "CMT_FIFO_L_LOGIC_OUTS8_7", - "CMT_FIFO_L_LOGIC_OUTS8_8", - "CMT_FIFO_L_LOGIC_OUTS8_9", - "CMT_FIFO_L_LOGIC_OUTS9_0", - "CMT_FIFO_L_LOGIC_OUTS9_1", - "CMT_FIFO_L_LOGIC_OUTS9_10", - "CMT_FIFO_L_LOGIC_OUTS9_11", - "CMT_FIFO_L_LOGIC_OUTS9_2", - "CMT_FIFO_L_LOGIC_OUTS9_3", - "CMT_FIFO_L_LOGIC_OUTS9_4", - "CMT_FIFO_L_LOGIC_OUTS9_5", - "CMT_FIFO_L_LOGIC_OUTS9_6", - "CMT_FIFO_L_LOGIC_OUTS9_7", - "CMT_FIFO_L_LOGIC_OUTS9_8", - "CMT_FIFO_L_LOGIC_OUTS9_9", - "CMT_FIFO_L_PHASER_RDCLK", - "CMT_FIFO_L_PHASER_RDENABLE", - "CMT_FIFO_L_PHASER_WRCLK", - "CMT_FIFO_L_PHASER_WRENABLE", - "CMT_FIFO_MONITOR_N_0", - "CMT_FIFO_MONITOR_N_1", - "CMT_FIFO_MONITOR_N_10", - "CMT_FIFO_MONITOR_N_11", - "CMT_FIFO_MONITOR_N_2", - "CMT_FIFO_MONITOR_N_3", - "CMT_FIFO_MONITOR_N_4", - "CMT_FIFO_MONITOR_N_5", - "CMT_FIFO_MONITOR_N_6", - "CMT_FIFO_MONITOR_N_7", - "CMT_FIFO_MONITOR_N_8", - "CMT_FIFO_MONITOR_N_9", - "CMT_FIFO_MONITOR_P_0", - "CMT_FIFO_MONITOR_P_1", - "CMT_FIFO_MONITOR_P_10", - "CMT_FIFO_MONITOR_P_11", - "CMT_FIFO_MONITOR_P_2", - "CMT_FIFO_MONITOR_P_3", - "CMT_FIFO_MONITOR_P_4", - "CMT_FIFO_MONITOR_P_5", - "CMT_FIFO_MONITOR_P_6", - "CMT_FIFO_MONITOR_P_7", - "CMT_FIFO_MONITOR_P_8", - "CMT_FIFO_MONITOR_P_9", - "CMT_FIFO_NE2A0_0", - "CMT_FIFO_NE2A0_1", - "CMT_FIFO_NE2A0_10", - "CMT_FIFO_NE2A0_11", - "CMT_FIFO_NE2A0_2", - "CMT_FIFO_NE2A0_3", - "CMT_FIFO_NE2A0_4", - "CMT_FIFO_NE2A0_5", - "CMT_FIFO_NE2A0_6", - "CMT_FIFO_NE2A0_7", - "CMT_FIFO_NE2A0_8", - "CMT_FIFO_NE2A0_9", - "CMT_FIFO_NE2A1_0", - "CMT_FIFO_NE2A1_1", - "CMT_FIFO_NE2A1_10", - "CMT_FIFO_NE2A1_11", - "CMT_FIFO_NE2A1_2", - "CMT_FIFO_NE2A1_3", - "CMT_FIFO_NE2A1_4", - "CMT_FIFO_NE2A1_5", - "CMT_FIFO_NE2A1_6", - "CMT_FIFO_NE2A1_7", - "CMT_FIFO_NE2A1_8", - "CMT_FIFO_NE2A1_9", - "CMT_FIFO_NE2A2_0", - "CMT_FIFO_NE2A2_1", - "CMT_FIFO_NE2A2_10", - "CMT_FIFO_NE2A2_11", - "CMT_FIFO_NE2A2_2", - "CMT_FIFO_NE2A2_3", - "CMT_FIFO_NE2A2_4", - "CMT_FIFO_NE2A2_5", - "CMT_FIFO_NE2A2_6", - "CMT_FIFO_NE2A2_7", - "CMT_FIFO_NE2A2_8", - "CMT_FIFO_NE2A2_9", - "CMT_FIFO_NE2A3_0", - "CMT_FIFO_NE2A3_1", - "CMT_FIFO_NE2A3_10", - "CMT_FIFO_NE2A3_11", - "CMT_FIFO_NE2A3_2", - "CMT_FIFO_NE2A3_3", - "CMT_FIFO_NE2A3_4", - "CMT_FIFO_NE2A3_5", - "CMT_FIFO_NE2A3_6", - "CMT_FIFO_NE2A3_7", - "CMT_FIFO_NE2A3_8", - "CMT_FIFO_NE2A3_9", - "CMT_FIFO_NE4BEG0_0", - "CMT_FIFO_NE4BEG0_1", - "CMT_FIFO_NE4BEG0_10", - "CMT_FIFO_NE4BEG0_11", - "CMT_FIFO_NE4BEG0_2", - "CMT_FIFO_NE4BEG0_3", - "CMT_FIFO_NE4BEG0_4", - "CMT_FIFO_NE4BEG0_5", - "CMT_FIFO_NE4BEG0_6", - "CMT_FIFO_NE4BEG0_7", - "CMT_FIFO_NE4BEG0_8", - "CMT_FIFO_NE4BEG0_9", - "CMT_FIFO_NE4BEG1_0", - "CMT_FIFO_NE4BEG1_1", - "CMT_FIFO_NE4BEG1_10", - "CMT_FIFO_NE4BEG1_11", - "CMT_FIFO_NE4BEG1_2", - "CMT_FIFO_NE4BEG1_3", - "CMT_FIFO_NE4BEG1_4", - "CMT_FIFO_NE4BEG1_5", - "CMT_FIFO_NE4BEG1_6", - "CMT_FIFO_NE4BEG1_7", - "CMT_FIFO_NE4BEG1_8", - "CMT_FIFO_NE4BEG1_9", - "CMT_FIFO_NE4BEG2_0", - "CMT_FIFO_NE4BEG2_1", - "CMT_FIFO_NE4BEG2_10", - "CMT_FIFO_NE4BEG2_11", - "CMT_FIFO_NE4BEG2_2", - "CMT_FIFO_NE4BEG2_3", - "CMT_FIFO_NE4BEG2_4", - "CMT_FIFO_NE4BEG2_5", - "CMT_FIFO_NE4BEG2_6", - "CMT_FIFO_NE4BEG2_7", - "CMT_FIFO_NE4BEG2_8", - "CMT_FIFO_NE4BEG2_9", - "CMT_FIFO_NE4BEG3_0", - "CMT_FIFO_NE4BEG3_1", - "CMT_FIFO_NE4BEG3_10", - "CMT_FIFO_NE4BEG3_11", - "CMT_FIFO_NE4BEG3_2", - "CMT_FIFO_NE4BEG3_3", - "CMT_FIFO_NE4BEG3_4", - "CMT_FIFO_NE4BEG3_5", - "CMT_FIFO_NE4BEG3_6", - "CMT_FIFO_NE4BEG3_7", - "CMT_FIFO_NE4BEG3_8", - "CMT_FIFO_NE4BEG3_9", - "CMT_FIFO_NE4C0_0", - "CMT_FIFO_NE4C0_1", - "CMT_FIFO_NE4C0_10", - "CMT_FIFO_NE4C0_11", - "CMT_FIFO_NE4C0_2", - "CMT_FIFO_NE4C0_3", - "CMT_FIFO_NE4C0_4", - "CMT_FIFO_NE4C0_5", - "CMT_FIFO_NE4C0_6", - "CMT_FIFO_NE4C0_7", - "CMT_FIFO_NE4C0_8", - "CMT_FIFO_NE4C0_9", - "CMT_FIFO_NE4C1_0", - "CMT_FIFO_NE4C1_1", - "CMT_FIFO_NE4C1_10", - "CMT_FIFO_NE4C1_11", - "CMT_FIFO_NE4C1_2", - "CMT_FIFO_NE4C1_3", - "CMT_FIFO_NE4C1_4", - "CMT_FIFO_NE4C1_5", - "CMT_FIFO_NE4C1_6", - "CMT_FIFO_NE4C1_7", - "CMT_FIFO_NE4C1_8", - "CMT_FIFO_NE4C1_9", - "CMT_FIFO_NE4C2_0", - "CMT_FIFO_NE4C2_1", - "CMT_FIFO_NE4C2_10", - "CMT_FIFO_NE4C2_11", - "CMT_FIFO_NE4C2_2", - "CMT_FIFO_NE4C2_3", - "CMT_FIFO_NE4C2_4", - "CMT_FIFO_NE4C2_5", - "CMT_FIFO_NE4C2_6", - "CMT_FIFO_NE4C2_7", - "CMT_FIFO_NE4C2_8", - "CMT_FIFO_NE4C2_9", - "CMT_FIFO_NE4C3_0", - "CMT_FIFO_NE4C3_1", - "CMT_FIFO_NE4C3_10", - "CMT_FIFO_NE4C3_11", - "CMT_FIFO_NE4C3_2", - "CMT_FIFO_NE4C3_3", - "CMT_FIFO_NE4C3_4", - "CMT_FIFO_NE4C3_5", - "CMT_FIFO_NE4C3_6", - "CMT_FIFO_NE4C3_7", - "CMT_FIFO_NE4C3_8", - "CMT_FIFO_NE4C3_9", - "CMT_FIFO_NW2A0_0", - "CMT_FIFO_NW2A0_1", - "CMT_FIFO_NW2A0_10", - "CMT_FIFO_NW2A0_11", - "CMT_FIFO_NW2A0_2", - "CMT_FIFO_NW2A0_3", - "CMT_FIFO_NW2A0_4", - "CMT_FIFO_NW2A0_5", - "CMT_FIFO_NW2A0_6", - "CMT_FIFO_NW2A0_7", - "CMT_FIFO_NW2A0_8", - "CMT_FIFO_NW2A0_9", - "CMT_FIFO_NW2A1_0", - "CMT_FIFO_NW2A1_1", - "CMT_FIFO_NW2A1_10", - "CMT_FIFO_NW2A1_11", - "CMT_FIFO_NW2A1_2", - "CMT_FIFO_NW2A1_3", - "CMT_FIFO_NW2A1_4", - "CMT_FIFO_NW2A1_5", - "CMT_FIFO_NW2A1_6", - "CMT_FIFO_NW2A1_7", - "CMT_FIFO_NW2A1_8", - "CMT_FIFO_NW2A1_9", - "CMT_FIFO_NW2A2_0", - "CMT_FIFO_NW2A2_1", - "CMT_FIFO_NW2A2_10", - "CMT_FIFO_NW2A2_11", - "CMT_FIFO_NW2A2_2", - "CMT_FIFO_NW2A2_3", - "CMT_FIFO_NW2A2_4", - "CMT_FIFO_NW2A2_5", - "CMT_FIFO_NW2A2_6", - "CMT_FIFO_NW2A2_7", - "CMT_FIFO_NW2A2_8", - "CMT_FIFO_NW2A2_9", - "CMT_FIFO_NW2A3_0", - "CMT_FIFO_NW2A3_1", - "CMT_FIFO_NW2A3_10", - "CMT_FIFO_NW2A3_11", - "CMT_FIFO_NW2A3_2", - "CMT_FIFO_NW2A3_3", - "CMT_FIFO_NW2A3_4", - "CMT_FIFO_NW2A3_5", - "CMT_FIFO_NW2A3_6", - "CMT_FIFO_NW2A3_7", - "CMT_FIFO_NW2A3_8", - "CMT_FIFO_NW2A3_9", - "CMT_FIFO_NW4A0_0", - "CMT_FIFO_NW4A0_1", - "CMT_FIFO_NW4A0_10", - "CMT_FIFO_NW4A0_11", - "CMT_FIFO_NW4A0_2", - "CMT_FIFO_NW4A0_3", - "CMT_FIFO_NW4A0_4", - "CMT_FIFO_NW4A0_5", - "CMT_FIFO_NW4A0_6", - "CMT_FIFO_NW4A0_7", - "CMT_FIFO_NW4A0_8", - "CMT_FIFO_NW4A0_9", - "CMT_FIFO_NW4A1_0", - "CMT_FIFO_NW4A1_1", - "CMT_FIFO_NW4A1_10", - "CMT_FIFO_NW4A1_11", - "CMT_FIFO_NW4A1_2", - "CMT_FIFO_NW4A1_3", - "CMT_FIFO_NW4A1_4", - "CMT_FIFO_NW4A1_5", - "CMT_FIFO_NW4A1_6", - "CMT_FIFO_NW4A1_7", - "CMT_FIFO_NW4A1_8", - "CMT_FIFO_NW4A1_9", - "CMT_FIFO_NW4A2_0", - "CMT_FIFO_NW4A2_1", - "CMT_FIFO_NW4A2_10", - "CMT_FIFO_NW4A2_11", - "CMT_FIFO_NW4A2_2", - "CMT_FIFO_NW4A2_3", - "CMT_FIFO_NW4A2_4", - "CMT_FIFO_NW4A2_5", - "CMT_FIFO_NW4A2_6", - "CMT_FIFO_NW4A2_7", - "CMT_FIFO_NW4A2_8", - "CMT_FIFO_NW4A2_9", - "CMT_FIFO_NW4A3_0", - "CMT_FIFO_NW4A3_1", - "CMT_FIFO_NW4A3_10", - "CMT_FIFO_NW4A3_11", - "CMT_FIFO_NW4A3_2", - "CMT_FIFO_NW4A3_3", - "CMT_FIFO_NW4A3_4", - "CMT_FIFO_NW4A3_5", - "CMT_FIFO_NW4A3_6", - "CMT_FIFO_NW4A3_7", - "CMT_FIFO_NW4A3_8", - "CMT_FIFO_NW4A3_9", - "CMT_FIFO_NW4END0_0", - "CMT_FIFO_NW4END0_1", - "CMT_FIFO_NW4END0_10", - "CMT_FIFO_NW4END0_11", - "CMT_FIFO_NW4END0_2", - "CMT_FIFO_NW4END0_3", - "CMT_FIFO_NW4END0_4", - "CMT_FIFO_NW4END0_5", - "CMT_FIFO_NW4END0_6", - "CMT_FIFO_NW4END0_7", - "CMT_FIFO_NW4END0_8", - "CMT_FIFO_NW4END0_9", - "CMT_FIFO_NW4END1_0", - "CMT_FIFO_NW4END1_1", - "CMT_FIFO_NW4END1_10", - "CMT_FIFO_NW4END1_11", - "CMT_FIFO_NW4END1_2", - "CMT_FIFO_NW4END1_3", - "CMT_FIFO_NW4END1_4", - "CMT_FIFO_NW4END1_5", - "CMT_FIFO_NW4END1_6", - "CMT_FIFO_NW4END1_7", - "CMT_FIFO_NW4END1_8", - "CMT_FIFO_NW4END1_9", - "CMT_FIFO_NW4END2_0", - "CMT_FIFO_NW4END2_1", - "CMT_FIFO_NW4END2_10", - "CMT_FIFO_NW4END2_11", - "CMT_FIFO_NW4END2_2", - "CMT_FIFO_NW4END2_3", - "CMT_FIFO_NW4END2_4", - "CMT_FIFO_NW4END2_5", - "CMT_FIFO_NW4END2_6", - "CMT_FIFO_NW4END2_7", - "CMT_FIFO_NW4END2_8", - "CMT_FIFO_NW4END2_9", - "CMT_FIFO_NW4END3_0", - "CMT_FIFO_NW4END3_1", - "CMT_FIFO_NW4END3_10", - "CMT_FIFO_NW4END3_11", - "CMT_FIFO_NW4END3_2", - "CMT_FIFO_NW4END3_3", - "CMT_FIFO_NW4END3_4", - "CMT_FIFO_NW4END3_5", - "CMT_FIFO_NW4END3_6", - "CMT_FIFO_NW4END3_7", - "CMT_FIFO_NW4END3_8", - "CMT_FIFO_NW4END3_9", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", - "CMT_FIFO_PHASER_TO_IO_ICLK_0", - "CMT_FIFO_PHASER_TO_IO_ICLK_1", - "CMT_FIFO_PHASER_TO_IO_ICLK_10", - "CMT_FIFO_PHASER_TO_IO_ICLK_11", - "CMT_FIFO_PHASER_TO_IO_ICLK_2", - "CMT_FIFO_PHASER_TO_IO_ICLK_3", - "CMT_FIFO_PHASER_TO_IO_ICLK_4", - "CMT_FIFO_PHASER_TO_IO_ICLK_5", - "CMT_FIFO_PHASER_TO_IO_ICLK_6", - "CMT_FIFO_PHASER_TO_IO_ICLK_7", - "CMT_FIFO_PHASER_TO_IO_ICLK_8", - "CMT_FIFO_PHASER_TO_IO_ICLK_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_1", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_10", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_2", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_3", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_8", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_9", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", - "CMT_FIFO_SE2A0_0", - "CMT_FIFO_SE2A0_1", - "CMT_FIFO_SE2A0_10", - "CMT_FIFO_SE2A0_11", - "CMT_FIFO_SE2A0_2", - "CMT_FIFO_SE2A0_3", - "CMT_FIFO_SE2A0_4", - "CMT_FIFO_SE2A0_5", - "CMT_FIFO_SE2A0_6", - "CMT_FIFO_SE2A0_7", - "CMT_FIFO_SE2A0_8", - "CMT_FIFO_SE2A0_9", - "CMT_FIFO_SE2A1_0", - "CMT_FIFO_SE2A1_1", - "CMT_FIFO_SE2A1_10", - "CMT_FIFO_SE2A1_11", - "CMT_FIFO_SE2A1_2", - "CMT_FIFO_SE2A1_3", - "CMT_FIFO_SE2A1_4", - "CMT_FIFO_SE2A1_5", - "CMT_FIFO_SE2A1_6", - "CMT_FIFO_SE2A1_7", - "CMT_FIFO_SE2A1_8", - "CMT_FIFO_SE2A1_9", - "CMT_FIFO_SE2A2_0", - "CMT_FIFO_SE2A2_1", - "CMT_FIFO_SE2A2_10", - "CMT_FIFO_SE2A2_11", - "CMT_FIFO_SE2A2_2", - "CMT_FIFO_SE2A2_3", - "CMT_FIFO_SE2A2_4", - "CMT_FIFO_SE2A2_5", - "CMT_FIFO_SE2A2_6", - "CMT_FIFO_SE2A2_7", - "CMT_FIFO_SE2A2_8", - "CMT_FIFO_SE2A2_9", - "CMT_FIFO_SE2A3_0", - "CMT_FIFO_SE2A3_1", - "CMT_FIFO_SE2A3_10", - "CMT_FIFO_SE2A3_11", - "CMT_FIFO_SE2A3_2", - "CMT_FIFO_SE2A3_3", - "CMT_FIFO_SE2A3_4", - "CMT_FIFO_SE2A3_5", - "CMT_FIFO_SE2A3_6", - "CMT_FIFO_SE2A3_7", - "CMT_FIFO_SE2A3_8", - "CMT_FIFO_SE2A3_9", - "CMT_FIFO_SE4BEG0_0", - "CMT_FIFO_SE4BEG0_1", - "CMT_FIFO_SE4BEG0_10", - "CMT_FIFO_SE4BEG0_11", - "CMT_FIFO_SE4BEG0_2", - "CMT_FIFO_SE4BEG0_3", - "CMT_FIFO_SE4BEG0_4", - "CMT_FIFO_SE4BEG0_5", - "CMT_FIFO_SE4BEG0_6", - "CMT_FIFO_SE4BEG0_7", - "CMT_FIFO_SE4BEG0_8", - "CMT_FIFO_SE4BEG0_9", - "CMT_FIFO_SE4BEG1_0", - "CMT_FIFO_SE4BEG1_1", - "CMT_FIFO_SE4BEG1_10", - "CMT_FIFO_SE4BEG1_11", - "CMT_FIFO_SE4BEG1_2", - "CMT_FIFO_SE4BEG1_3", - "CMT_FIFO_SE4BEG1_4", - "CMT_FIFO_SE4BEG1_5", - "CMT_FIFO_SE4BEG1_6", - "CMT_FIFO_SE4BEG1_7", - "CMT_FIFO_SE4BEG1_8", - "CMT_FIFO_SE4BEG1_9", - "CMT_FIFO_SE4BEG2_0", - "CMT_FIFO_SE4BEG2_1", - "CMT_FIFO_SE4BEG2_10", - "CMT_FIFO_SE4BEG2_11", - "CMT_FIFO_SE4BEG2_2", - "CMT_FIFO_SE4BEG2_3", - "CMT_FIFO_SE4BEG2_4", - "CMT_FIFO_SE4BEG2_5", - "CMT_FIFO_SE4BEG2_6", - "CMT_FIFO_SE4BEG2_7", - "CMT_FIFO_SE4BEG2_8", - "CMT_FIFO_SE4BEG2_9", - "CMT_FIFO_SE4BEG3_0", - "CMT_FIFO_SE4BEG3_1", - "CMT_FIFO_SE4BEG3_10", - "CMT_FIFO_SE4BEG3_11", - "CMT_FIFO_SE4BEG3_2", - "CMT_FIFO_SE4BEG3_3", - "CMT_FIFO_SE4BEG3_4", - "CMT_FIFO_SE4BEG3_5", - "CMT_FIFO_SE4BEG3_6", - "CMT_FIFO_SE4BEG3_7", - "CMT_FIFO_SE4BEG3_8", - "CMT_FIFO_SE4BEG3_9", - "CMT_FIFO_SE4C0_0", - "CMT_FIFO_SE4C0_1", - "CMT_FIFO_SE4C0_10", - "CMT_FIFO_SE4C0_11", - "CMT_FIFO_SE4C0_2", - "CMT_FIFO_SE4C0_3", - "CMT_FIFO_SE4C0_4", - "CMT_FIFO_SE4C0_5", - "CMT_FIFO_SE4C0_6", - "CMT_FIFO_SE4C0_7", - "CMT_FIFO_SE4C0_8", - "CMT_FIFO_SE4C0_9", - "CMT_FIFO_SE4C1_0", - "CMT_FIFO_SE4C1_1", - "CMT_FIFO_SE4C1_10", - "CMT_FIFO_SE4C1_11", - "CMT_FIFO_SE4C1_2", - "CMT_FIFO_SE4C1_3", - "CMT_FIFO_SE4C1_4", - "CMT_FIFO_SE4C1_5", - "CMT_FIFO_SE4C1_6", - "CMT_FIFO_SE4C1_7", - "CMT_FIFO_SE4C1_8", - "CMT_FIFO_SE4C1_9", - "CMT_FIFO_SE4C2_0", - "CMT_FIFO_SE4C2_1", - "CMT_FIFO_SE4C2_10", - "CMT_FIFO_SE4C2_11", - "CMT_FIFO_SE4C2_2", - "CMT_FIFO_SE4C2_3", - "CMT_FIFO_SE4C2_4", - "CMT_FIFO_SE4C2_5", - "CMT_FIFO_SE4C2_6", - "CMT_FIFO_SE4C2_7", - "CMT_FIFO_SE4C2_8", - "CMT_FIFO_SE4C2_9", - "CMT_FIFO_SE4C3_0", - "CMT_FIFO_SE4C3_1", - "CMT_FIFO_SE4C3_10", - "CMT_FIFO_SE4C3_11", - "CMT_FIFO_SE4C3_2", - "CMT_FIFO_SE4C3_3", - "CMT_FIFO_SE4C3_4", - "CMT_FIFO_SE4C3_5", - "CMT_FIFO_SE4C3_6", - "CMT_FIFO_SE4C3_7", - "CMT_FIFO_SE4C3_8", - "CMT_FIFO_SE4C3_9", - "CMT_FIFO_SW2A0_0", - "CMT_FIFO_SW2A0_1", - "CMT_FIFO_SW2A0_10", - "CMT_FIFO_SW2A0_11", - "CMT_FIFO_SW2A0_2", - "CMT_FIFO_SW2A0_3", - "CMT_FIFO_SW2A0_4", - "CMT_FIFO_SW2A0_5", - "CMT_FIFO_SW2A0_6", - "CMT_FIFO_SW2A0_7", - "CMT_FIFO_SW2A0_8", - "CMT_FIFO_SW2A0_9", - "CMT_FIFO_SW2A1_0", - "CMT_FIFO_SW2A1_1", - "CMT_FIFO_SW2A1_10", - "CMT_FIFO_SW2A1_11", - "CMT_FIFO_SW2A1_2", - "CMT_FIFO_SW2A1_3", - "CMT_FIFO_SW2A1_4", - "CMT_FIFO_SW2A1_5", - "CMT_FIFO_SW2A1_6", - "CMT_FIFO_SW2A1_7", - "CMT_FIFO_SW2A1_8", - "CMT_FIFO_SW2A1_9", - "CMT_FIFO_SW2A2_0", - "CMT_FIFO_SW2A2_1", - "CMT_FIFO_SW2A2_10", - "CMT_FIFO_SW2A2_11", - "CMT_FIFO_SW2A2_2", - "CMT_FIFO_SW2A2_3", - "CMT_FIFO_SW2A2_4", - "CMT_FIFO_SW2A2_5", - "CMT_FIFO_SW2A2_6", - "CMT_FIFO_SW2A2_7", - "CMT_FIFO_SW2A2_8", - "CMT_FIFO_SW2A2_9", - "CMT_FIFO_SW2A3_0", - "CMT_FIFO_SW2A3_1", - "CMT_FIFO_SW2A3_10", - "CMT_FIFO_SW2A3_11", - "CMT_FIFO_SW2A3_2", - "CMT_FIFO_SW2A3_3", - "CMT_FIFO_SW2A3_4", - "CMT_FIFO_SW2A3_5", - "CMT_FIFO_SW2A3_6", - "CMT_FIFO_SW2A3_7", - "CMT_FIFO_SW2A3_8", - "CMT_FIFO_SW2A3_9", - "CMT_FIFO_SW4A0_0", - "CMT_FIFO_SW4A0_1", - "CMT_FIFO_SW4A0_10", - "CMT_FIFO_SW4A0_11", - "CMT_FIFO_SW4A0_2", - "CMT_FIFO_SW4A0_3", - "CMT_FIFO_SW4A0_4", - "CMT_FIFO_SW4A0_5", - "CMT_FIFO_SW4A0_6", - "CMT_FIFO_SW4A0_7", - "CMT_FIFO_SW4A0_8", - "CMT_FIFO_SW4A0_9", - "CMT_FIFO_SW4A1_0", - "CMT_FIFO_SW4A1_1", - "CMT_FIFO_SW4A1_10", - "CMT_FIFO_SW4A1_11", - "CMT_FIFO_SW4A1_2", - "CMT_FIFO_SW4A1_3", - "CMT_FIFO_SW4A1_4", - "CMT_FIFO_SW4A1_5", - "CMT_FIFO_SW4A1_6", - "CMT_FIFO_SW4A1_7", - "CMT_FIFO_SW4A1_8", - "CMT_FIFO_SW4A1_9", - "CMT_FIFO_SW4A2_0", - "CMT_FIFO_SW4A2_1", - "CMT_FIFO_SW4A2_10", - "CMT_FIFO_SW4A2_11", - "CMT_FIFO_SW4A2_2", - "CMT_FIFO_SW4A2_3", - "CMT_FIFO_SW4A2_4", - "CMT_FIFO_SW4A2_5", - "CMT_FIFO_SW4A2_6", - "CMT_FIFO_SW4A2_7", - "CMT_FIFO_SW4A2_8", - "CMT_FIFO_SW4A2_9", - "CMT_FIFO_SW4A3_0", - "CMT_FIFO_SW4A3_1", - "CMT_FIFO_SW4A3_10", - "CMT_FIFO_SW4A3_11", - "CMT_FIFO_SW4A3_2", - "CMT_FIFO_SW4A3_3", - "CMT_FIFO_SW4A3_4", - "CMT_FIFO_SW4A3_5", - "CMT_FIFO_SW4A3_6", - "CMT_FIFO_SW4A3_7", - "CMT_FIFO_SW4A3_8", - "CMT_FIFO_SW4A3_9", - "CMT_FIFO_SW4END0_0", - "CMT_FIFO_SW4END0_1", - "CMT_FIFO_SW4END0_10", - "CMT_FIFO_SW4END0_11", - "CMT_FIFO_SW4END0_2", - "CMT_FIFO_SW4END0_3", - "CMT_FIFO_SW4END0_4", - "CMT_FIFO_SW4END0_5", - "CMT_FIFO_SW4END0_6", - "CMT_FIFO_SW4END0_7", - "CMT_FIFO_SW4END0_8", - "CMT_FIFO_SW4END0_9", - "CMT_FIFO_SW4END1_0", - "CMT_FIFO_SW4END1_1", - "CMT_FIFO_SW4END1_10", - "CMT_FIFO_SW4END1_11", - "CMT_FIFO_SW4END1_2", - "CMT_FIFO_SW4END1_3", - "CMT_FIFO_SW4END1_4", - "CMT_FIFO_SW4END1_5", - "CMT_FIFO_SW4END1_6", - "CMT_FIFO_SW4END1_7", - "CMT_FIFO_SW4END1_8", - "CMT_FIFO_SW4END1_9", - "CMT_FIFO_SW4END2_0", - "CMT_FIFO_SW4END2_1", - "CMT_FIFO_SW4END2_10", - "CMT_FIFO_SW4END2_11", - "CMT_FIFO_SW4END2_2", - "CMT_FIFO_SW4END2_3", - "CMT_FIFO_SW4END2_4", - "CMT_FIFO_SW4END2_5", - "CMT_FIFO_SW4END2_6", - "CMT_FIFO_SW4END2_7", - "CMT_FIFO_SW4END2_8", - "CMT_FIFO_SW4END2_9", - "CMT_FIFO_SW4END3_0", - "CMT_FIFO_SW4END3_1", - "CMT_FIFO_SW4END3_10", - "CMT_FIFO_SW4END3_11", - "CMT_FIFO_SW4END3_2", - "CMT_FIFO_SW4END3_3", - "CMT_FIFO_SW4END3_4", - "CMT_FIFO_SW4END3_5", - "CMT_FIFO_SW4END3_6", - "CMT_FIFO_SW4END3_7", - "CMT_FIFO_SW4END3_8", - "CMT_FIFO_SW4END3_9", - "CMT_FIFO_WL1END0_0", - "CMT_FIFO_WL1END0_1", - "CMT_FIFO_WL1END0_10", - "CMT_FIFO_WL1END0_11", - "CMT_FIFO_WL1END0_2", - "CMT_FIFO_WL1END0_3", - "CMT_FIFO_WL1END0_4", - "CMT_FIFO_WL1END0_5", - "CMT_FIFO_WL1END0_6", - "CMT_FIFO_WL1END0_7", - "CMT_FIFO_WL1END0_8", - "CMT_FIFO_WL1END0_9", - "CMT_FIFO_WL1END1_0", - "CMT_FIFO_WL1END1_1", - "CMT_FIFO_WL1END1_10", - "CMT_FIFO_WL1END1_11", - "CMT_FIFO_WL1END1_2", - "CMT_FIFO_WL1END1_3", - "CMT_FIFO_WL1END1_4", - "CMT_FIFO_WL1END1_5", - "CMT_FIFO_WL1END1_6", - "CMT_FIFO_WL1END1_7", - "CMT_FIFO_WL1END1_8", - "CMT_FIFO_WL1END1_9", - "CMT_FIFO_WL1END2_0", - "CMT_FIFO_WL1END2_1", - "CMT_FIFO_WL1END2_10", - "CMT_FIFO_WL1END2_11", - "CMT_FIFO_WL1END2_2", - "CMT_FIFO_WL1END2_3", - "CMT_FIFO_WL1END2_4", - "CMT_FIFO_WL1END2_5", - "CMT_FIFO_WL1END2_6", - "CMT_FIFO_WL1END2_7", - "CMT_FIFO_WL1END2_8", - "CMT_FIFO_WL1END2_9", - "CMT_FIFO_WL1END3_0", - "CMT_FIFO_WL1END3_1", - "CMT_FIFO_WL1END3_10", - "CMT_FIFO_WL1END3_11", - "CMT_FIFO_WL1END3_2", - "CMT_FIFO_WL1END3_3", - "CMT_FIFO_WL1END3_4", - "CMT_FIFO_WL1END3_5", - "CMT_FIFO_WL1END3_6", - "CMT_FIFO_WL1END3_7", - "CMT_FIFO_WL1END3_8", - "CMT_FIFO_WL1END3_9", - "CMT_FIFO_WR1END0_0", - "CMT_FIFO_WR1END0_1", - "CMT_FIFO_WR1END0_10", - "CMT_FIFO_WR1END0_11", - "CMT_FIFO_WR1END0_2", - "CMT_FIFO_WR1END0_3", - "CMT_FIFO_WR1END0_4", - "CMT_FIFO_WR1END0_5", - "CMT_FIFO_WR1END0_6", - "CMT_FIFO_WR1END0_7", - "CMT_FIFO_WR1END0_8", - "CMT_FIFO_WR1END0_9", - "CMT_FIFO_WR1END1_0", - "CMT_FIFO_WR1END1_1", - "CMT_FIFO_WR1END1_10", - "CMT_FIFO_WR1END1_11", - "CMT_FIFO_WR1END1_2", - "CMT_FIFO_WR1END1_3", - "CMT_FIFO_WR1END1_4", - "CMT_FIFO_WR1END1_5", - "CMT_FIFO_WR1END1_6", - "CMT_FIFO_WR1END1_7", - "CMT_FIFO_WR1END1_8", - "CMT_FIFO_WR1END1_9", - "CMT_FIFO_WR1END2_0", - "CMT_FIFO_WR1END2_1", - "CMT_FIFO_WR1END2_10", - "CMT_FIFO_WR1END2_11", - "CMT_FIFO_WR1END2_2", - "CMT_FIFO_WR1END2_3", - "CMT_FIFO_WR1END2_4", - "CMT_FIFO_WR1END2_5", - "CMT_FIFO_WR1END2_6", - "CMT_FIFO_WR1END2_7", - "CMT_FIFO_WR1END2_8", - "CMT_FIFO_WR1END2_9", - "CMT_FIFO_WR1END3_0", - "CMT_FIFO_WR1END3_1", - "CMT_FIFO_WR1END3_10", - "CMT_FIFO_WR1END3_11", - "CMT_FIFO_WR1END3_2", - "CMT_FIFO_WR1END3_3", - "CMT_FIFO_WR1END3_4", - "CMT_FIFO_WR1END3_5", - "CMT_FIFO_WR1END3_6", - "CMT_FIFO_WR1END3_7", - "CMT_FIFO_WR1END3_8", - "CMT_FIFO_WR1END3_9", - "CMT_FIFO_WW2A0_0", - "CMT_FIFO_WW2A0_1", - "CMT_FIFO_WW2A0_10", - "CMT_FIFO_WW2A0_11", - "CMT_FIFO_WW2A0_2", - "CMT_FIFO_WW2A0_3", - "CMT_FIFO_WW2A0_4", - "CMT_FIFO_WW2A0_5", - "CMT_FIFO_WW2A0_6", - "CMT_FIFO_WW2A0_7", - "CMT_FIFO_WW2A0_8", - "CMT_FIFO_WW2A0_9", - "CMT_FIFO_WW2A1_0", - "CMT_FIFO_WW2A1_1", - "CMT_FIFO_WW2A1_10", - "CMT_FIFO_WW2A1_11", - "CMT_FIFO_WW2A1_2", - "CMT_FIFO_WW2A1_3", - "CMT_FIFO_WW2A1_4", - "CMT_FIFO_WW2A1_5", - "CMT_FIFO_WW2A1_6", - "CMT_FIFO_WW2A1_7", - "CMT_FIFO_WW2A1_8", - "CMT_FIFO_WW2A1_9", - "CMT_FIFO_WW2A2_0", - "CMT_FIFO_WW2A2_1", - "CMT_FIFO_WW2A2_10", - "CMT_FIFO_WW2A2_11", - "CMT_FIFO_WW2A2_2", - "CMT_FIFO_WW2A2_3", - "CMT_FIFO_WW2A2_4", - "CMT_FIFO_WW2A2_5", - "CMT_FIFO_WW2A2_6", - "CMT_FIFO_WW2A2_7", - "CMT_FIFO_WW2A2_8", - "CMT_FIFO_WW2A2_9", - "CMT_FIFO_WW2A3_0", - "CMT_FIFO_WW2A3_1", - "CMT_FIFO_WW2A3_10", - "CMT_FIFO_WW2A3_11", - "CMT_FIFO_WW2A3_2", - "CMT_FIFO_WW2A3_3", - "CMT_FIFO_WW2A3_4", - "CMT_FIFO_WW2A3_5", - "CMT_FIFO_WW2A3_6", - "CMT_FIFO_WW2A3_7", - "CMT_FIFO_WW2A3_8", - "CMT_FIFO_WW2A3_9", - "CMT_FIFO_WW2END0_0", - "CMT_FIFO_WW2END0_1", - "CMT_FIFO_WW2END0_10", - "CMT_FIFO_WW2END0_11", - "CMT_FIFO_WW2END0_2", - "CMT_FIFO_WW2END0_3", - "CMT_FIFO_WW2END0_4", - "CMT_FIFO_WW2END0_5", - "CMT_FIFO_WW2END0_6", - "CMT_FIFO_WW2END0_7", - "CMT_FIFO_WW2END0_8", - "CMT_FIFO_WW2END0_9", - "CMT_FIFO_WW2END1_0", - "CMT_FIFO_WW2END1_1", - "CMT_FIFO_WW2END1_10", - "CMT_FIFO_WW2END1_11", - "CMT_FIFO_WW2END1_2", - "CMT_FIFO_WW2END1_3", - "CMT_FIFO_WW2END1_4", - "CMT_FIFO_WW2END1_5", - "CMT_FIFO_WW2END1_6", - "CMT_FIFO_WW2END1_7", - "CMT_FIFO_WW2END1_8", - "CMT_FIFO_WW2END1_9", - "CMT_FIFO_WW2END2_0", - "CMT_FIFO_WW2END2_1", - "CMT_FIFO_WW2END2_10", - "CMT_FIFO_WW2END2_11", - "CMT_FIFO_WW2END2_2", - "CMT_FIFO_WW2END2_3", - "CMT_FIFO_WW2END2_4", - "CMT_FIFO_WW2END2_5", - "CMT_FIFO_WW2END2_6", - "CMT_FIFO_WW2END2_7", - "CMT_FIFO_WW2END2_8", - "CMT_FIFO_WW2END2_9", - "CMT_FIFO_WW2END3_0", - "CMT_FIFO_WW2END3_1", - "CMT_FIFO_WW2END3_10", - "CMT_FIFO_WW2END3_11", - "CMT_FIFO_WW2END3_2", - "CMT_FIFO_WW2END3_3", - "CMT_FIFO_WW2END3_4", - "CMT_FIFO_WW2END3_5", - "CMT_FIFO_WW2END3_6", - "CMT_FIFO_WW2END3_7", - "CMT_FIFO_WW2END3_8", - "CMT_FIFO_WW2END3_9", - "CMT_FIFO_WW4A0_0", - "CMT_FIFO_WW4A0_1", - "CMT_FIFO_WW4A0_10", - "CMT_FIFO_WW4A0_11", - "CMT_FIFO_WW4A0_2", - "CMT_FIFO_WW4A0_3", - "CMT_FIFO_WW4A0_4", - "CMT_FIFO_WW4A0_5", - "CMT_FIFO_WW4A0_6", - "CMT_FIFO_WW4A0_7", - "CMT_FIFO_WW4A0_8", - "CMT_FIFO_WW4A0_9", - "CMT_FIFO_WW4A1_0", - "CMT_FIFO_WW4A1_1", - "CMT_FIFO_WW4A1_10", - "CMT_FIFO_WW4A1_11", - "CMT_FIFO_WW4A1_2", - "CMT_FIFO_WW4A1_3", - "CMT_FIFO_WW4A1_4", - "CMT_FIFO_WW4A1_5", - "CMT_FIFO_WW4A1_6", - "CMT_FIFO_WW4A1_7", - "CMT_FIFO_WW4A1_8", - "CMT_FIFO_WW4A1_9", - "CMT_FIFO_WW4A2_0", - "CMT_FIFO_WW4A2_1", - "CMT_FIFO_WW4A2_10", - "CMT_FIFO_WW4A2_11", - "CMT_FIFO_WW4A2_2", - "CMT_FIFO_WW4A2_3", - "CMT_FIFO_WW4A2_4", - "CMT_FIFO_WW4A2_5", - "CMT_FIFO_WW4A2_6", - "CMT_FIFO_WW4A2_7", - "CMT_FIFO_WW4A2_8", - "CMT_FIFO_WW4A2_9", - "CMT_FIFO_WW4A3_0", - "CMT_FIFO_WW4A3_1", - "CMT_FIFO_WW4A3_10", - "CMT_FIFO_WW4A3_11", - "CMT_FIFO_WW4A3_2", - "CMT_FIFO_WW4A3_3", - "CMT_FIFO_WW4A3_4", - "CMT_FIFO_WW4A3_5", - "CMT_FIFO_WW4A3_6", - "CMT_FIFO_WW4A3_7", - "CMT_FIFO_WW4A3_8", - "CMT_FIFO_WW4A3_9", - "CMT_FIFO_WW4B0_0", - "CMT_FIFO_WW4B0_1", - "CMT_FIFO_WW4B0_10", - "CMT_FIFO_WW4B0_11", - "CMT_FIFO_WW4B0_2", - "CMT_FIFO_WW4B0_3", - "CMT_FIFO_WW4B0_4", - "CMT_FIFO_WW4B0_5", - "CMT_FIFO_WW4B0_6", - "CMT_FIFO_WW4B0_7", - "CMT_FIFO_WW4B0_8", - "CMT_FIFO_WW4B0_9", - "CMT_FIFO_WW4B1_0", - "CMT_FIFO_WW4B1_1", - "CMT_FIFO_WW4B1_10", - "CMT_FIFO_WW4B1_11", - "CMT_FIFO_WW4B1_2", - "CMT_FIFO_WW4B1_3", - "CMT_FIFO_WW4B1_4", - "CMT_FIFO_WW4B1_5", - "CMT_FIFO_WW4B1_6", - "CMT_FIFO_WW4B1_7", - "CMT_FIFO_WW4B1_8", - "CMT_FIFO_WW4B1_9", - "CMT_FIFO_WW4B2_0", - "CMT_FIFO_WW4B2_1", - "CMT_FIFO_WW4B2_10", - "CMT_FIFO_WW4B2_11", - "CMT_FIFO_WW4B2_2", - "CMT_FIFO_WW4B2_3", - "CMT_FIFO_WW4B2_4", - "CMT_FIFO_WW4B2_5", - "CMT_FIFO_WW4B2_6", - "CMT_FIFO_WW4B2_7", - "CMT_FIFO_WW4B2_8", - "CMT_FIFO_WW4B2_9", - "CMT_FIFO_WW4B3_0", - "CMT_FIFO_WW4B3_1", - "CMT_FIFO_WW4B3_10", - "CMT_FIFO_WW4B3_11", - "CMT_FIFO_WW4B3_2", - "CMT_FIFO_WW4B3_3", - "CMT_FIFO_WW4B3_4", - "CMT_FIFO_WW4B3_5", - "CMT_FIFO_WW4B3_6", - "CMT_FIFO_WW4B3_7", - "CMT_FIFO_WW4B3_8", - "CMT_FIFO_WW4B3_9", - "CMT_FIFO_WW4C0_0", - "CMT_FIFO_WW4C0_1", - "CMT_FIFO_WW4C0_10", - "CMT_FIFO_WW4C0_11", - "CMT_FIFO_WW4C0_2", - "CMT_FIFO_WW4C0_3", - "CMT_FIFO_WW4C0_4", - "CMT_FIFO_WW4C0_5", - "CMT_FIFO_WW4C0_6", - "CMT_FIFO_WW4C0_7", - "CMT_FIFO_WW4C0_8", - "CMT_FIFO_WW4C0_9", - "CMT_FIFO_WW4C1_0", - "CMT_FIFO_WW4C1_1", - "CMT_FIFO_WW4C1_10", - "CMT_FIFO_WW4C1_11", - "CMT_FIFO_WW4C1_2", - "CMT_FIFO_WW4C1_3", - "CMT_FIFO_WW4C1_4", - "CMT_FIFO_WW4C1_5", - "CMT_FIFO_WW4C1_6", - "CMT_FIFO_WW4C1_7", - "CMT_FIFO_WW4C1_8", - "CMT_FIFO_WW4C1_9", - "CMT_FIFO_WW4C2_0", - "CMT_FIFO_WW4C2_1", - "CMT_FIFO_WW4C2_10", - "CMT_FIFO_WW4C2_11", - "CMT_FIFO_WW4C2_2", - "CMT_FIFO_WW4C2_3", - "CMT_FIFO_WW4C2_4", - "CMT_FIFO_WW4C2_5", - "CMT_FIFO_WW4C2_6", - "CMT_FIFO_WW4C2_7", - "CMT_FIFO_WW4C2_8", - "CMT_FIFO_WW4C2_9", - "CMT_FIFO_WW4C3_0", - "CMT_FIFO_WW4C3_1", - "CMT_FIFO_WW4C3_10", - "CMT_FIFO_WW4C3_11", - "CMT_FIFO_WW4C3_2", - "CMT_FIFO_WW4C3_3", - "CMT_FIFO_WW4C3_4", - "CMT_FIFO_WW4C3_5", - "CMT_FIFO_WW4C3_6", - "CMT_FIFO_WW4C3_7", - "CMT_FIFO_WW4C3_8", - "CMT_FIFO_WW4C3_9", - "CMT_FIFO_WW4END0_0", - "CMT_FIFO_WW4END0_1", - "CMT_FIFO_WW4END0_10", - "CMT_FIFO_WW4END0_11", - "CMT_FIFO_WW4END0_2", - "CMT_FIFO_WW4END0_3", - "CMT_FIFO_WW4END0_4", - "CMT_FIFO_WW4END0_5", - "CMT_FIFO_WW4END0_6", - "CMT_FIFO_WW4END0_7", - "CMT_FIFO_WW4END0_8", - "CMT_FIFO_WW4END0_9", - "CMT_FIFO_WW4END1_0", - "CMT_FIFO_WW4END1_1", - "CMT_FIFO_WW4END1_10", - "CMT_FIFO_WW4END1_11", - "CMT_FIFO_WW4END1_2", - "CMT_FIFO_WW4END1_3", - "CMT_FIFO_WW4END1_4", - "CMT_FIFO_WW4END1_5", - "CMT_FIFO_WW4END1_6", - "CMT_FIFO_WW4END1_7", - "CMT_FIFO_WW4END1_8", - "CMT_FIFO_WW4END1_9", - "CMT_FIFO_WW4END2_0", - "CMT_FIFO_WW4END2_1", - "CMT_FIFO_WW4END2_10", - "CMT_FIFO_WW4END2_11", - "CMT_FIFO_WW4END2_2", - "CMT_FIFO_WW4END2_3", - "CMT_FIFO_WW4END2_4", - "CMT_FIFO_WW4END2_5", - "CMT_FIFO_WW4END2_6", - "CMT_FIFO_WW4END2_7", - "CMT_FIFO_WW4END2_8", - "CMT_FIFO_WW4END2_9", - "CMT_FIFO_WW4END3_0", - "CMT_FIFO_WW4END3_1", - "CMT_FIFO_WW4END3_10", - "CMT_FIFO_WW4END3_11", - "CMT_FIFO_WW4END3_2", - "CMT_FIFO_WW4END3_3", - "CMT_FIFO_WW4END3_4", - "CMT_FIFO_WW4END3_5", - "CMT_FIFO_WW4END3_6", - "CMT_FIFO_WW4END3_7", - "CMT_FIFO_WW4END3_8", - "CMT_FIFO_WW4END3_9", - "CMT_IN_FIFO_ALMOSTEMPTY", - "CMT_IN_FIFO_ALMOSTFULL", - "CMT_IN_FIFO_D00", - "CMT_IN_FIFO_D01", - "CMT_IN_FIFO_D02", - "CMT_IN_FIFO_D03", - "CMT_IN_FIFO_D10", - "CMT_IN_FIFO_D11", - "CMT_IN_FIFO_D12", - "CMT_IN_FIFO_D13", - "CMT_IN_FIFO_D20", - "CMT_IN_FIFO_D21", - "CMT_IN_FIFO_D22", - "CMT_IN_FIFO_D23", - "CMT_IN_FIFO_D30", - "CMT_IN_FIFO_D31", - "CMT_IN_FIFO_D32", - "CMT_IN_FIFO_D33", - "CMT_IN_FIFO_D40", - "CMT_IN_FIFO_D41", - "CMT_IN_FIFO_D42", - "CMT_IN_FIFO_D43", - "CMT_IN_FIFO_D50", - "CMT_IN_FIFO_D51", - "CMT_IN_FIFO_D52", - "CMT_IN_FIFO_D53", - "CMT_IN_FIFO_D54", - "CMT_IN_FIFO_D55", - "CMT_IN_FIFO_D56", - "CMT_IN_FIFO_D57", - "CMT_IN_FIFO_D60", - "CMT_IN_FIFO_D61", - "CMT_IN_FIFO_D62", - "CMT_IN_FIFO_D63", - "CMT_IN_FIFO_D64", - "CMT_IN_FIFO_D65", - "CMT_IN_FIFO_D66", - "CMT_IN_FIFO_D67", - "CMT_IN_FIFO_D70", - "CMT_IN_FIFO_D71", - "CMT_IN_FIFO_D72", - "CMT_IN_FIFO_D73", - "CMT_IN_FIFO_D80", - "CMT_IN_FIFO_D81", - "CMT_IN_FIFO_D82", - "CMT_IN_FIFO_D83", - "CMT_IN_FIFO_D90", - "CMT_IN_FIFO_D91", - "CMT_IN_FIFO_D92", - "CMT_IN_FIFO_D93", - "CMT_IN_FIFO_EMPTY", - "CMT_IN_FIFO_FULL", - "CMT_IN_FIFO_Q00", - "CMT_IN_FIFO_Q01", - "CMT_IN_FIFO_Q02", - "CMT_IN_FIFO_Q03", - "CMT_IN_FIFO_Q04", - "CMT_IN_FIFO_Q05", - "CMT_IN_FIFO_Q06", - "CMT_IN_FIFO_Q07", - "CMT_IN_FIFO_Q10", - "CMT_IN_FIFO_Q11", - "CMT_IN_FIFO_Q12", - "CMT_IN_FIFO_Q13", - "CMT_IN_FIFO_Q14", - "CMT_IN_FIFO_Q15", - "CMT_IN_FIFO_Q16", - "CMT_IN_FIFO_Q17", - "CMT_IN_FIFO_Q20", - "CMT_IN_FIFO_Q21", - "CMT_IN_FIFO_Q22", - "CMT_IN_FIFO_Q23", - "CMT_IN_FIFO_Q24", - "CMT_IN_FIFO_Q25", - "CMT_IN_FIFO_Q26", - "CMT_IN_FIFO_Q27", - "CMT_IN_FIFO_Q30", - "CMT_IN_FIFO_Q31", - "CMT_IN_FIFO_Q32", - "CMT_IN_FIFO_Q33", - "CMT_IN_FIFO_Q34", - "CMT_IN_FIFO_Q35", - "CMT_IN_FIFO_Q36", - "CMT_IN_FIFO_Q37", - "CMT_IN_FIFO_Q40", - "CMT_IN_FIFO_Q41", - "CMT_IN_FIFO_Q42", - "CMT_IN_FIFO_Q43", - "CMT_IN_FIFO_Q44", - "CMT_IN_FIFO_Q45", - "CMT_IN_FIFO_Q46", - "CMT_IN_FIFO_Q47", - "CMT_IN_FIFO_Q50", - "CMT_IN_FIFO_Q51", - "CMT_IN_FIFO_Q52", - "CMT_IN_FIFO_Q53", - "CMT_IN_FIFO_Q54", - "CMT_IN_FIFO_Q55", - "CMT_IN_FIFO_Q56", - "CMT_IN_FIFO_Q57", - "CMT_IN_FIFO_Q60", - "CMT_IN_FIFO_Q61", - "CMT_IN_FIFO_Q62", - "CMT_IN_FIFO_Q63", - "CMT_IN_FIFO_Q64", - "CMT_IN_FIFO_Q65", - "CMT_IN_FIFO_Q66", - "CMT_IN_FIFO_Q67", - "CMT_IN_FIFO_Q70", - "CMT_IN_FIFO_Q71", - "CMT_IN_FIFO_Q72", - "CMT_IN_FIFO_Q73", - "CMT_IN_FIFO_Q74", - "CMT_IN_FIFO_Q75", - "CMT_IN_FIFO_Q76", - "CMT_IN_FIFO_Q77", - "CMT_IN_FIFO_Q80", - "CMT_IN_FIFO_Q81", - "CMT_IN_FIFO_Q82", - "CMT_IN_FIFO_Q83", - "CMT_IN_FIFO_Q84", - "CMT_IN_FIFO_Q85", - "CMT_IN_FIFO_Q86", - "CMT_IN_FIFO_Q87", - "CMT_IN_FIFO_Q90", - "CMT_IN_FIFO_Q91", - "CMT_IN_FIFO_Q92", - "CMT_IN_FIFO_Q93", - "CMT_IN_FIFO_Q94", - "CMT_IN_FIFO_Q95", - "CMT_IN_FIFO_Q96", - "CMT_IN_FIFO_Q97", - "CMT_IN_FIFO_RDCLK", - "CMT_IN_FIFO_RDEN", - "CMT_IN_FIFO_RESET", - "CMT_IN_FIFO_SCANENB", - "CMT_IN_FIFO_SCANIN0", - "CMT_IN_FIFO_SCANIN1", - "CMT_IN_FIFO_SCANIN2", - "CMT_IN_FIFO_SCANIN3", - "CMT_IN_FIFO_SCANOUT0", - "CMT_IN_FIFO_SCANOUT1", - "CMT_IN_FIFO_SCANOUT2", - "CMT_IN_FIFO_SCANOUT3", - "CMT_IN_FIFO_TESTMODEB", - "CMT_IN_FIFO_TESTREADDISB", - "CMT_IN_FIFO_TESTWRITEDISB", - "CMT_IN_FIFO_WRCLK", - "CMT_IN_FIFO_WREN", - "CMT_OUT_FIFO_ALMOSTEMPTY", - "CMT_OUT_FIFO_ALMOSTFULL", - "CMT_OUT_FIFO_D00", - "CMT_OUT_FIFO_D01", - "CMT_OUT_FIFO_D02", - "CMT_OUT_FIFO_D03", - "CMT_OUT_FIFO_D04", - "CMT_OUT_FIFO_D05", - "CMT_OUT_FIFO_D06", - "CMT_OUT_FIFO_D07", - "CMT_OUT_FIFO_D10", - "CMT_OUT_FIFO_D11", - "CMT_OUT_FIFO_D12", - "CMT_OUT_FIFO_D13", - "CMT_OUT_FIFO_D14", - "CMT_OUT_FIFO_D15", - "CMT_OUT_FIFO_D16", - "CMT_OUT_FIFO_D17", - "CMT_OUT_FIFO_D20", - "CMT_OUT_FIFO_D21", - "CMT_OUT_FIFO_D22", - "CMT_OUT_FIFO_D23", - "CMT_OUT_FIFO_D24", - "CMT_OUT_FIFO_D25", - "CMT_OUT_FIFO_D26", - "CMT_OUT_FIFO_D27", - "CMT_OUT_FIFO_D30", - "CMT_OUT_FIFO_D31", - "CMT_OUT_FIFO_D32", - "CMT_OUT_FIFO_D33", - "CMT_OUT_FIFO_D34", - "CMT_OUT_FIFO_D35", - "CMT_OUT_FIFO_D36", - "CMT_OUT_FIFO_D37", - "CMT_OUT_FIFO_D40", - "CMT_OUT_FIFO_D41", - "CMT_OUT_FIFO_D42", - "CMT_OUT_FIFO_D43", - "CMT_OUT_FIFO_D44", - "CMT_OUT_FIFO_D45", - "CMT_OUT_FIFO_D46", - "CMT_OUT_FIFO_D47", - "CMT_OUT_FIFO_D50", - "CMT_OUT_FIFO_D51", - "CMT_OUT_FIFO_D52", - "CMT_OUT_FIFO_D53", - "CMT_OUT_FIFO_D54", - "CMT_OUT_FIFO_D55", - "CMT_OUT_FIFO_D56", - "CMT_OUT_FIFO_D57", - "CMT_OUT_FIFO_D60", - "CMT_OUT_FIFO_D61", - "CMT_OUT_FIFO_D62", - "CMT_OUT_FIFO_D63", - "CMT_OUT_FIFO_D64", - "CMT_OUT_FIFO_D65", - "CMT_OUT_FIFO_D66", - "CMT_OUT_FIFO_D67", - "CMT_OUT_FIFO_D70", - "CMT_OUT_FIFO_D71", - "CMT_OUT_FIFO_D72", - "CMT_OUT_FIFO_D73", - "CMT_OUT_FIFO_D74", - "CMT_OUT_FIFO_D75", - "CMT_OUT_FIFO_D76", - "CMT_OUT_FIFO_D77", - "CMT_OUT_FIFO_D80", - "CMT_OUT_FIFO_D81", - "CMT_OUT_FIFO_D82", - "CMT_OUT_FIFO_D83", - "CMT_OUT_FIFO_D84", - "CMT_OUT_FIFO_D85", - "CMT_OUT_FIFO_D86", - "CMT_OUT_FIFO_D87", - "CMT_OUT_FIFO_D90", - "CMT_OUT_FIFO_D91", - "CMT_OUT_FIFO_D92", - "CMT_OUT_FIFO_D93", - "CMT_OUT_FIFO_D94", - "CMT_OUT_FIFO_D95", - "CMT_OUT_FIFO_D96", - "CMT_OUT_FIFO_D97", - "CMT_OUT_FIFO_EMPTY", - "CMT_OUT_FIFO_FULL", - "CMT_OUT_FIFO_Q00", - "CMT_OUT_FIFO_Q01", - "CMT_OUT_FIFO_Q02", - "CMT_OUT_FIFO_Q03", - "CMT_OUT_FIFO_Q10", - "CMT_OUT_FIFO_Q11", - "CMT_OUT_FIFO_Q12", - "CMT_OUT_FIFO_Q13", - "CMT_OUT_FIFO_Q20", - "CMT_OUT_FIFO_Q21", - "CMT_OUT_FIFO_Q22", - "CMT_OUT_FIFO_Q23", - "CMT_OUT_FIFO_Q30", - "CMT_OUT_FIFO_Q31", - "CMT_OUT_FIFO_Q32", - "CMT_OUT_FIFO_Q33", - "CMT_OUT_FIFO_Q40", - "CMT_OUT_FIFO_Q41", - "CMT_OUT_FIFO_Q42", - "CMT_OUT_FIFO_Q43", - "CMT_OUT_FIFO_Q50", - "CMT_OUT_FIFO_Q51", - "CMT_OUT_FIFO_Q52", - "CMT_OUT_FIFO_Q53", - "CMT_OUT_FIFO_Q54", - "CMT_OUT_FIFO_Q55", - "CMT_OUT_FIFO_Q56", - "CMT_OUT_FIFO_Q57", - "CMT_OUT_FIFO_Q60", - "CMT_OUT_FIFO_Q61", - "CMT_OUT_FIFO_Q62", - "CMT_OUT_FIFO_Q63", - "CMT_OUT_FIFO_Q64", - "CMT_OUT_FIFO_Q65", - "CMT_OUT_FIFO_Q66", - "CMT_OUT_FIFO_Q67", - "CMT_OUT_FIFO_Q70", - "CMT_OUT_FIFO_Q71", - "CMT_OUT_FIFO_Q72", - "CMT_OUT_FIFO_Q73", - "CMT_OUT_FIFO_Q80", - "CMT_OUT_FIFO_Q81", - "CMT_OUT_FIFO_Q82", - "CMT_OUT_FIFO_Q83", - "CMT_OUT_FIFO_Q90", - "CMT_OUT_FIFO_Q91", - "CMT_OUT_FIFO_Q92", - "CMT_OUT_FIFO_Q93", - "CMT_OUT_FIFO_RDCLK", - "CMT_OUT_FIFO_RDEN", - "CMT_OUT_FIFO_RESET", - "CMT_OUT_FIFO_SCANENB", - "CMT_OUT_FIFO_SCANIN0", - "CMT_OUT_FIFO_SCANIN1", - "CMT_OUT_FIFO_SCANIN2", - "CMT_OUT_FIFO_SCANIN3", - "CMT_OUT_FIFO_SCANOUT0", - "CMT_OUT_FIFO_SCANOUT1", - "CMT_OUT_FIFO_SCANOUT2", - "CMT_OUT_FIFO_SCANOUT3", - "CMT_OUT_FIFO_TESTMODEB", - "CMT_OUT_FIFO_TESTREADDISB", - "CMT_OUT_FIFO_TESTWRITEDISB", - "CMT_OUT_FIFO_WRCLK", - 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+ "CMT_IN_FIFO_TESTREADDISB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_IN_FIFO_TESTWRITEDISB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_IN_FIFO_WRCLK": { + "cap": "9.585", + "res": "0.000" + }, + "CMT_IN_FIFO_WREN": { + "cap": "0.825", + "res": "0.000" + }, + "CMT_OUT_FIFO_ALMOSTEMPTY": { + "cap": "6.850", + "res": "0.000" + }, + "CMT_OUT_FIFO_ALMOSTFULL": { + "cap": "6.850", + "res": "0.000" + }, + "CMT_OUT_FIFO_D00": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D01": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D02": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D03": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D04": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D05": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D06": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D07": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D10": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D11": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D12": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D13": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D14": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D15": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D16": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D17": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D20": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D21": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D22": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D23": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D24": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D25": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D26": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D27": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D30": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D31": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D32": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D33": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D34": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D35": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D36": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D37": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D40": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D41": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D42": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D43": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D44": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D45": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D46": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D47": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D50": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D51": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D52": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D53": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D54": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D55": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D56": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D57": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D60": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D61": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D62": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D63": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D64": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D65": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D66": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D67": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D70": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D71": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D72": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D73": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D74": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D75": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D76": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D77": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D80": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D81": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D82": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D83": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D84": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D85": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D86": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D87": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D90": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D91": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D92": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D93": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D94": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D95": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D96": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D97": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_EMPTY": { + "cap": "6.850", + "res": "0.000" + }, + "CMT_OUT_FIFO_FULL": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q00": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q01": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q02": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q03": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q10": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q11": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q12": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q13": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q20": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q21": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q22": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q23": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q30": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q31": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q32": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q33": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q40": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q41": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q42": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q43": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q50": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q51": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q52": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q53": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q54": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q55": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q56": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q57": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q60": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q61": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q62": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q63": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q64": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q65": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q66": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q67": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q70": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q71": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q72": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q73": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q80": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q81": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q82": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q83": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q90": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q91": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q92": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q93": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_RDCLK": { + "cap": "9.585", + "res": "0.000" + }, + "CMT_OUT_FIFO_RDEN": { + "cap": "4.293", + "res": "0.000" + }, + "CMT_OUT_FIFO_RESET": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANENB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN0": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN1": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN2": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN3": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT0": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT1": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT2": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT3": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_TESTMODEB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_TESTREADDISB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_TESTWRITEDISB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_WRCLK": { + "cap": "9.585", + "res": "0.000" + }, + "CMT_OUT_FIFO_WREN": { + "cap": "1.649", + "res": "0.000" + }, + "FIFO_DQS_IOTOPHASER_1": null, + "FIFO_DQS_IOTOPHASER_11": null, + "FIFO_DQS_IOTOPHASER_2": null, + "FIFO_DQS_IOTOPHASER_22": null, + "FIFO_DQS_IOTOPHASER_3": null, + "FIFO_DQS_IOTOPHASER_33": null, + "FIFO_DQS_IOTOPHASER_4": null, + "FIFO_DQS_IOTOPHASER_44": null, + "FIFO_DQS_IOTOPHASER_5": null, + "FIFO_DQS_IOTOPHASER_55": null, + "FIFO_DQS_IOTOPHASER_6": null, + "FIFO_DQS_IOTOPHASER_66": null + } } diff --git a/kintex7/tile_type_CMT_FIFO_R.json b/kintex7/tile_type_CMT_FIFO_R.json index e5b6437..0e79972 100644 --- a/kintex7/tile_type_CMT_FIFO_R.json +++ b/kintex7/tile_type_CMT_FIFO_R.json @@ -2,1948 +2,5006 @@ "pips": { "CMT_FIFO_R.CMT_FIFO_L_CLK0_6->CMT_OUT_FIFO_WRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_WRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK0_6" }, "CMT_FIFO_R.CMT_FIFO_L_CLK0_7->CMT_OUT_FIFO_RDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK0_7" }, "CMT_FIFO_R.CMT_FIFO_L_CLK1_6->CMT_IN_FIFO_WRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK1_6" }, "CMT_FIFO_R.CMT_FIFO_L_CLK1_7->CMT_IN_FIFO_RDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_RDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_CLK1_7" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_0->CMT_OUT_FIFO_D04": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D04", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_1->CMT_OUT_FIFO_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_10->CMT_OUT_FIFO_D84": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D84", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_11->CMT_OUT_FIFO_D94": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D94", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_2->CMT_OUT_FIFO_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_3->CMT_OUT_FIFO_D34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_4->CMT_OUT_FIFO_D44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_5->CMT_OUT_FIFO_D54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_8->CMT_OUT_FIFO_D64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX12_9->CMT_OUT_FIFO_D74": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D74", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX12_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_0->CMT_OUT_FIFO_D01": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D01", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_1->CMT_OUT_FIFO_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_10->CMT_OUT_FIFO_D81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_11->CMT_OUT_FIFO_D91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_2->CMT_OUT_FIFO_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_3->CMT_OUT_FIFO_D31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_4->CMT_OUT_FIFO_D41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_5->CMT_OUT_FIFO_D51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_8->CMT_OUT_FIFO_D61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX21_9->CMT_OUT_FIFO_D71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX21_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_0->CMT_IN_FIFO_D00": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D00", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_1->CMT_IN_FIFO_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_10->CMT_IN_FIFO_D80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_11->CMT_IN_FIFO_D90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_2->CMT_IN_FIFO_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_3->CMT_IN_FIFO_D30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_4->CMT_IN_FIFO_D40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_5->CMT_IN_FIFO_D50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_6->CMT_IN_FIFO_D54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_6" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_7->CMT_IN_FIFO_D64": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D64", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_7" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_8->CMT_IN_FIFO_D60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX26_9->CMT_IN_FIFO_D70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX26_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_0->CMT_OUT_FIFO_D00": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D00", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_1->CMT_OUT_FIFO_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_10->CMT_OUT_FIFO_D80": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D80", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_11->CMT_OUT_FIFO_D90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_2->CMT_OUT_FIFO_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_3->CMT_OUT_FIFO_D30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_4->CMT_OUT_FIFO_D40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_5->CMT_OUT_FIFO_D50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_8->CMT_OUT_FIFO_D60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX28_9->CMT_OUT_FIFO_D70": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D70", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX28_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_0->CMT_IN_FIFO_D02": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D02", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_1->CMT_IN_FIFO_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_10->CMT_IN_FIFO_D82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_11->CMT_IN_FIFO_D92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_2->CMT_IN_FIFO_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_3->CMT_IN_FIFO_D32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_4->CMT_IN_FIFO_D42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_5->CMT_IN_FIFO_D52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_6->CMT_IN_FIFO_D56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_6" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_7->CMT_IN_FIFO_D66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_7" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_8->CMT_IN_FIFO_D62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX36_9->CMT_IN_FIFO_D72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX36_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_0->CMT_OUT_FIFO_D03": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D03", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_1->CMT_OUT_FIFO_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_10->CMT_OUT_FIFO_D83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_11->CMT_OUT_FIFO_D93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_2->CMT_OUT_FIFO_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_3->CMT_OUT_FIFO_D33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_4->CMT_OUT_FIFO_D43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_5->CMT_OUT_FIFO_D53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_8->CMT_OUT_FIFO_D63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX38_9->CMT_OUT_FIFO_D73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX38_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_0->CMT_OUT_FIFO_D02": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D02", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_1->CMT_OUT_FIFO_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_10->CMT_OUT_FIFO_D82": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D82", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_11->CMT_OUT_FIFO_D92": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D92", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_2->CMT_OUT_FIFO_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_3->CMT_OUT_FIFO_D32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_4->CMT_OUT_FIFO_D42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_5->CMT_OUT_FIFO_D52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_8->CMT_OUT_FIFO_D62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX39_9->CMT_OUT_FIFO_D72": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D72", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX39_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_0->CMT_IN_FIFO_D01": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D01", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_1->CMT_IN_FIFO_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_10->CMT_IN_FIFO_D81": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D81", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_11->CMT_IN_FIFO_D91": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D91", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_2->CMT_IN_FIFO_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_3->CMT_IN_FIFO_D31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_4->CMT_IN_FIFO_D41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_5->CMT_IN_FIFO_D51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_6->CMT_IN_FIFO_D55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_6" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_7->CMT_IN_FIFO_D65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_7" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_8->CMT_IN_FIFO_D61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX40_9->CMT_IN_FIFO_D71": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D71", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX40_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_0->CMT_IN_FIFO_D03": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D03", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_1->CMT_IN_FIFO_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_10->CMT_IN_FIFO_D83": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D83", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_11->CMT_IN_FIFO_D93": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D93", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_2->CMT_IN_FIFO_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_3->CMT_IN_FIFO_D33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_4->CMT_IN_FIFO_D43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_5->CMT_IN_FIFO_D53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_6->CMT_IN_FIFO_D57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_6" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_7->CMT_IN_FIFO_D67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_7" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_8->CMT_IN_FIFO_D63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX42_9->CMT_IN_FIFO_D73": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_D73", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX42_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_0->CMT_OUT_FIFO_D05": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D05", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_1->CMT_OUT_FIFO_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_10->CMT_OUT_FIFO_D85": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D85", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_11->CMT_OUT_FIFO_D95": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D95", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_2->CMT_OUT_FIFO_D25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_3->CMT_OUT_FIFO_D35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_4->CMT_OUT_FIFO_D45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_5->CMT_OUT_FIFO_D55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_6->CMT_OUT_FIFO_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_6" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_7->CMT_IN_FIFO_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_7" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_8->CMT_OUT_FIFO_D65": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D65", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX5_9->CMT_OUT_FIFO_D75": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D75", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX5_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_0->CMT_OUT_FIFO_D07": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D07", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_1->CMT_OUT_FIFO_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_10->CMT_OUT_FIFO_D87": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D87", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_11->CMT_OUT_FIFO_D97": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D97", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_2->CMT_OUT_FIFO_D27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_3->CMT_OUT_FIFO_D37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_4->CMT_OUT_FIFO_D47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_5->CMT_OUT_FIFO_D57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_6->CMT_OUT_FIFO_WREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_WREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_6" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_7->CMT_OUT_FIFO_RDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_7" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_8->CMT_OUT_FIFO_D67": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D67", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX6_9->CMT_OUT_FIFO_D77": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D77", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX6_9" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_0->CMT_OUT_FIFO_D06": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D06", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_0" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_1->CMT_OUT_FIFO_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_1" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_10->CMT_OUT_FIFO_D86": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D86", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_10" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_11->CMT_OUT_FIFO_D96": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D96", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_11" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_2->CMT_OUT_FIFO_D26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_2" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_3->CMT_OUT_FIFO_D36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_3" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_4->CMT_OUT_FIFO_D46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_4" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_5->CMT_OUT_FIFO_D56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_5" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_6->CMT_IN_FIFO_WREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_6" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_7->CMT_IN_FIFO_RDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_RDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_7" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_8->CMT_OUT_FIFO_D66": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D66", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_8" }, "CMT_FIFO_R.CMT_FIFO_L_IMUX7_9->CMT_OUT_FIFO_D76": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_D76", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_IMUX7_9" }, "CMT_FIFO_R.CMT_FIFO_L_PHASER_RDCLK->CMT_OUT_FIFO_RDCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_RDCLK" }, "CMT_FIFO_R.CMT_FIFO_L_PHASER_RDENABLE->CMT_OUT_FIFO_RDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_OUT_FIFO_RDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_RDENABLE" }, "CMT_FIFO_R.CMT_FIFO_L_PHASER_WRCLK->CMT_IN_FIFO_WRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_WRCLK" }, "CMT_FIFO_R.CMT_FIFO_L_PHASER_WRENABLE->CMT_IN_FIFO_WREN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_IN_FIFO_WREN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_FIFO_L_PHASER_WRENABLE" }, "CMT_FIFO_R.CMT_IN_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_ALMOSTEMPTY" }, "CMT_FIFO_R.CMT_IN_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_ALMOSTFULL" }, "CMT_FIFO_R.CMT_IN_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_EMPTY" }, "CMT_FIFO_R.CMT_IN_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_FULL" }, "CMT_FIFO_R.CMT_IN_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q00" }, "CMT_FIFO_R.CMT_IN_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q01" }, "CMT_FIFO_R.CMT_IN_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q02" }, "CMT_FIFO_R.CMT_IN_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q03" }, "CMT_FIFO_R.CMT_IN_FIFO_Q04->CMT_FIFO_L_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q04" }, "CMT_FIFO_R.CMT_IN_FIFO_Q05->CMT_FIFO_L_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q05" }, "CMT_FIFO_R.CMT_IN_FIFO_Q06->CMT_FIFO_L_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q06" }, "CMT_FIFO_R.CMT_IN_FIFO_Q07->CMT_FIFO_L_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q07" }, "CMT_FIFO_R.CMT_IN_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q10" }, "CMT_FIFO_R.CMT_IN_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q11" }, "CMT_FIFO_R.CMT_IN_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q12" }, "CMT_FIFO_R.CMT_IN_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q13" }, "CMT_FIFO_R.CMT_IN_FIFO_Q14->CMT_FIFO_L_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q14" }, "CMT_FIFO_R.CMT_IN_FIFO_Q15->CMT_FIFO_L_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q15" }, "CMT_FIFO_R.CMT_IN_FIFO_Q16->CMT_FIFO_L_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q16" }, "CMT_FIFO_R.CMT_IN_FIFO_Q17->CMT_FIFO_L_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q17" }, "CMT_FIFO_R.CMT_IN_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q20" }, "CMT_FIFO_R.CMT_IN_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q21" }, "CMT_FIFO_R.CMT_IN_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q22" }, "CMT_FIFO_R.CMT_IN_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q23" }, "CMT_FIFO_R.CMT_IN_FIFO_Q24->CMT_FIFO_L_LOGIC_OUTS12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q24" }, "CMT_FIFO_R.CMT_IN_FIFO_Q25->CMT_FIFO_L_LOGIC_OUTS8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q25" }, "CMT_FIFO_R.CMT_IN_FIFO_Q26->CMT_FIFO_L_LOGIC_OUTS9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q26" }, "CMT_FIFO_R.CMT_IN_FIFO_Q27->CMT_FIFO_L_LOGIC_OUTS13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q27" }, "CMT_FIFO_R.CMT_IN_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q30" }, "CMT_FIFO_R.CMT_IN_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q31" }, "CMT_FIFO_R.CMT_IN_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q32" }, "CMT_FIFO_R.CMT_IN_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q33" }, "CMT_FIFO_R.CMT_IN_FIFO_Q34->CMT_FIFO_L_LOGIC_OUTS12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q34" }, "CMT_FIFO_R.CMT_IN_FIFO_Q35->CMT_FIFO_L_LOGIC_OUTS8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q35" }, "CMT_FIFO_R.CMT_IN_FIFO_Q36->CMT_FIFO_L_LOGIC_OUTS9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q36" }, "CMT_FIFO_R.CMT_IN_FIFO_Q37->CMT_FIFO_L_LOGIC_OUTS13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q37" }, "CMT_FIFO_R.CMT_IN_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q40" }, "CMT_FIFO_R.CMT_IN_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q41" }, "CMT_FIFO_R.CMT_IN_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q42" }, "CMT_FIFO_R.CMT_IN_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q43" }, "CMT_FIFO_R.CMT_IN_FIFO_Q44->CMT_FIFO_L_LOGIC_OUTS12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q44" }, "CMT_FIFO_R.CMT_IN_FIFO_Q45->CMT_FIFO_L_LOGIC_OUTS8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q45" }, "CMT_FIFO_R.CMT_IN_FIFO_Q46->CMT_FIFO_L_LOGIC_OUTS9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q46" }, "CMT_FIFO_R.CMT_IN_FIFO_Q47->CMT_FIFO_L_LOGIC_OUTS13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q47" }, "CMT_FIFO_R.CMT_IN_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q50" }, "CMT_FIFO_R.CMT_IN_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q51" }, "CMT_FIFO_R.CMT_IN_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q52" }, "CMT_FIFO_R.CMT_IN_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q53" }, "CMT_FIFO_R.CMT_IN_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q54" }, "CMT_FIFO_R.CMT_IN_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q55" }, "CMT_FIFO_R.CMT_IN_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q56" }, "CMT_FIFO_R.CMT_IN_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q57" }, "CMT_FIFO_R.CMT_IN_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q60" }, "CMT_FIFO_R.CMT_IN_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q61" }, "CMT_FIFO_R.CMT_IN_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q62" }, "CMT_FIFO_R.CMT_IN_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q63" }, "CMT_FIFO_R.CMT_IN_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q64" }, "CMT_FIFO_R.CMT_IN_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q65" }, "CMT_FIFO_R.CMT_IN_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q66" }, "CMT_FIFO_R.CMT_IN_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q67" }, "CMT_FIFO_R.CMT_IN_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q70" }, "CMT_FIFO_R.CMT_IN_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q71" }, "CMT_FIFO_R.CMT_IN_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q72" }, "CMT_FIFO_R.CMT_IN_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q73" }, "CMT_FIFO_R.CMT_IN_FIFO_Q74->CMT_FIFO_L_LOGIC_OUTS12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q74" }, "CMT_FIFO_R.CMT_IN_FIFO_Q75->CMT_FIFO_L_LOGIC_OUTS8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q75" }, "CMT_FIFO_R.CMT_IN_FIFO_Q76->CMT_FIFO_L_LOGIC_OUTS9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q76" }, "CMT_FIFO_R.CMT_IN_FIFO_Q77->CMT_FIFO_L_LOGIC_OUTS13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q77" }, "CMT_FIFO_R.CMT_IN_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q80" }, "CMT_FIFO_R.CMT_IN_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q81" }, "CMT_FIFO_R.CMT_IN_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q82" }, "CMT_FIFO_R.CMT_IN_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q83" }, "CMT_FIFO_R.CMT_IN_FIFO_Q84->CMT_FIFO_L_LOGIC_OUTS12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q84" }, "CMT_FIFO_R.CMT_IN_FIFO_Q85->CMT_FIFO_L_LOGIC_OUTS8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q85" }, "CMT_FIFO_R.CMT_IN_FIFO_Q86->CMT_FIFO_L_LOGIC_OUTS9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q86" }, "CMT_FIFO_R.CMT_IN_FIFO_Q87->CMT_FIFO_L_LOGIC_OUTS13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q87" }, "CMT_FIFO_R.CMT_IN_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS0_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS0_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q90" }, "CMT_FIFO_R.CMT_IN_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS4_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS4_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q91" }, "CMT_FIFO_R.CMT_IN_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS5_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS5_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q92" }, "CMT_FIFO_R.CMT_IN_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS1_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS1_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q93" }, "CMT_FIFO_R.CMT_IN_FIFO_Q94->CMT_FIFO_L_LOGIC_OUTS12_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS12_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q94" }, "CMT_FIFO_R.CMT_IN_FIFO_Q95->CMT_FIFO_L_LOGIC_OUTS8_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS8_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q95" }, "CMT_FIFO_R.CMT_IN_FIFO_Q96->CMT_FIFO_L_LOGIC_OUTS9_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS9_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q96" }, "CMT_FIFO_R.CMT_IN_FIFO_Q97->CMT_FIFO_L_LOGIC_OUTS13_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS13_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_IN_FIFO_Q97" }, "CMT_FIFO_R.CMT_OUT_FIFO_ALMOSTEMPTY->CMT_FIFO_L_LOGIC_OUTS3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_ALMOSTEMPTY" }, "CMT_FIFO_R.CMT_OUT_FIFO_ALMOSTFULL->CMT_FIFO_L_LOGIC_OUTS7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_ALMOSTFULL" }, "CMT_FIFO_R.CMT_OUT_FIFO_EMPTY->CMT_FIFO_L_LOGIC_OUTS10_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS10_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_EMPTY" }, "CMT_FIFO_R.CMT_OUT_FIFO_FULL->CMT_FIFO_L_LOGIC_OUTS2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_FULL" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q00->CMT_FIFO_L_LOGIC_OUTS22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q00" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q01->CMT_FIFO_L_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q01" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q02->CMT_FIFO_L_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q02" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q03->CMT_FIFO_L_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q03" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q10->CMT_FIFO_L_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q10" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q11->CMT_FIFO_L_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q11" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q12->CMT_FIFO_L_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q12" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q13->CMT_FIFO_L_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q13" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q20->CMT_FIFO_L_LOGIC_OUTS22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q20" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q21->CMT_FIFO_L_LOGIC_OUTS19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q21" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q22->CMT_FIFO_L_LOGIC_OUTS11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q22" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q23->CMT_FIFO_L_LOGIC_OUTS20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q23" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q30->CMT_FIFO_L_LOGIC_OUTS22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q30" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q31->CMT_FIFO_L_LOGIC_OUTS19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q31" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q32->CMT_FIFO_L_LOGIC_OUTS11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q32" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q33->CMT_FIFO_L_LOGIC_OUTS20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q33" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q40->CMT_FIFO_L_LOGIC_OUTS22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q40" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q41->CMT_FIFO_L_LOGIC_OUTS19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q41" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q42->CMT_FIFO_L_LOGIC_OUTS11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q42" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q43->CMT_FIFO_L_LOGIC_OUTS20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q43" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q50->CMT_FIFO_L_LOGIC_OUTS22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q50" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q51->CMT_FIFO_L_LOGIC_OUTS19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q51" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q52->CMT_FIFO_L_LOGIC_OUTS11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q52" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q53->CMT_FIFO_L_LOGIC_OUTS20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q53" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q54->CMT_FIFO_L_LOGIC_OUTS22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q54" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q55->CMT_FIFO_L_LOGIC_OUTS19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q55" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q56->CMT_FIFO_L_LOGIC_OUTS11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q56" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q57->CMT_FIFO_L_LOGIC_OUTS20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q57" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q60->CMT_FIFO_L_LOGIC_OUTS22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q60" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q61->CMT_FIFO_L_LOGIC_OUTS19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q61" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q62->CMT_FIFO_L_LOGIC_OUTS11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q62" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q63->CMT_FIFO_L_LOGIC_OUTS20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q63" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q64->CMT_FIFO_L_LOGIC_OUTS22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q64" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q65->CMT_FIFO_L_LOGIC_OUTS19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q65" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q66->CMT_FIFO_L_LOGIC_OUTS11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q66" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q67->CMT_FIFO_L_LOGIC_OUTS20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q67" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q70->CMT_FIFO_L_LOGIC_OUTS22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q70" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q71->CMT_FIFO_L_LOGIC_OUTS19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q71" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q72->CMT_FIFO_L_LOGIC_OUTS11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q72" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q73->CMT_FIFO_L_LOGIC_OUTS20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q73" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q80->CMT_FIFO_L_LOGIC_OUTS22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q80" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q81->CMT_FIFO_L_LOGIC_OUTS19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q81" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q82->CMT_FIFO_L_LOGIC_OUTS11_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q82" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q83->CMT_FIFO_L_LOGIC_OUTS20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q83" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q90->CMT_FIFO_L_LOGIC_OUTS22_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS22_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q90" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q91->CMT_FIFO_L_LOGIC_OUTS19_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS19_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q91" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q92->CMT_FIFO_L_LOGIC_OUTS11_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS11_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q92" }, "CMT_FIFO_R.CMT_OUT_FIFO_Q93->CMT_FIFO_L_LOGIC_OUTS20_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_FIFO_L_LOGIC_OUTS20_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_OUT_FIFO_Q93" } }, @@ -1952,155 +5010,1496 @@ "name": "X0Y0", "prefix": "OUT_FIFO", "site_pins": { - "ALMOSTEMPTY": "CMT_OUT_FIFO_ALMOSTEMPTY", - "ALMOSTFULL": "CMT_OUT_FIFO_ALMOSTFULL", - "D00": "CMT_OUT_FIFO_D00", - "D01": "CMT_OUT_FIFO_D01", - "D02": "CMT_OUT_FIFO_D02", - "D03": "CMT_OUT_FIFO_D03", - "D04": "CMT_OUT_FIFO_D04", - "D05": "CMT_OUT_FIFO_D05", - "D06": "CMT_OUT_FIFO_D06", - "D07": "CMT_OUT_FIFO_D07", - "D10": "CMT_OUT_FIFO_D10", - "D11": "CMT_OUT_FIFO_D11", - "D12": "CMT_OUT_FIFO_D12", - "D13": "CMT_OUT_FIFO_D13", - "D14": "CMT_OUT_FIFO_D14", - "D15": "CMT_OUT_FIFO_D15", - "D16": "CMT_OUT_FIFO_D16", - "D17": "CMT_OUT_FIFO_D17", - "D20": "CMT_OUT_FIFO_D20", - "D21": "CMT_OUT_FIFO_D21", - "D22": "CMT_OUT_FIFO_D22", - "D23": "CMT_OUT_FIFO_D23", - "D24": "CMT_OUT_FIFO_D24", - "D25": "CMT_OUT_FIFO_D25", - "D26": "CMT_OUT_FIFO_D26", - "D27": "CMT_OUT_FIFO_D27", - "D30": "CMT_OUT_FIFO_D30", - "D31": "CMT_OUT_FIFO_D31", - "D32": "CMT_OUT_FIFO_D32", - "D33": "CMT_OUT_FIFO_D33", - "D34": "CMT_OUT_FIFO_D34", - "D35": "CMT_OUT_FIFO_D35", - "D36": "CMT_OUT_FIFO_D36", - "D37": "CMT_OUT_FIFO_D37", - "D40": "CMT_OUT_FIFO_D40", - "D41": "CMT_OUT_FIFO_D41", - "D42": "CMT_OUT_FIFO_D42", - "D43": "CMT_OUT_FIFO_D43", - "D44": "CMT_OUT_FIFO_D44", - "D45": "CMT_OUT_FIFO_D45", - "D46": "CMT_OUT_FIFO_D46", - "D47": "CMT_OUT_FIFO_D47", - "D50": "CMT_OUT_FIFO_D50", - "D51": "CMT_OUT_FIFO_D51", - "D52": "CMT_OUT_FIFO_D52", - "D53": "CMT_OUT_FIFO_D53", - "D54": "CMT_OUT_FIFO_D54", - "D55": "CMT_OUT_FIFO_D55", - "D56": "CMT_OUT_FIFO_D56", - "D57": "CMT_OUT_FIFO_D57", - "D60": "CMT_OUT_FIFO_D60", - "D61": "CMT_OUT_FIFO_D61", - "D62": "CMT_OUT_FIFO_D62", - "D63": "CMT_OUT_FIFO_D63", - "D64": "CMT_OUT_FIFO_D64", - "D65": "CMT_OUT_FIFO_D65", - "D66": "CMT_OUT_FIFO_D66", - "D67": "CMT_OUT_FIFO_D67", - "D70": "CMT_OUT_FIFO_D70", - "D71": "CMT_OUT_FIFO_D71", - "D72": "CMT_OUT_FIFO_D72", - "D73": "CMT_OUT_FIFO_D73", - "D74": "CMT_OUT_FIFO_D74", - "D75": "CMT_OUT_FIFO_D75", - "D76": "CMT_OUT_FIFO_D76", - "D77": "CMT_OUT_FIFO_D77", - "D80": "CMT_OUT_FIFO_D80", - "D81": "CMT_OUT_FIFO_D81", - "D82": "CMT_OUT_FIFO_D82", - "D83": "CMT_OUT_FIFO_D83", - "D84": "CMT_OUT_FIFO_D84", - "D85": "CMT_OUT_FIFO_D85", - "D86": "CMT_OUT_FIFO_D86", - "D87": "CMT_OUT_FIFO_D87", - "D90": "CMT_OUT_FIFO_D90", - "D91": "CMT_OUT_FIFO_D91", - "D92": "CMT_OUT_FIFO_D92", - "D93": "CMT_OUT_FIFO_D93", - "D94": "CMT_OUT_FIFO_D94", - "D95": "CMT_OUT_FIFO_D95", - "D96": "CMT_OUT_FIFO_D96", - "D97": "CMT_OUT_FIFO_D97", - "EMPTY": "CMT_OUT_FIFO_EMPTY", - "FULL": "CMT_OUT_FIFO_FULL", - "Q00": "CMT_OUT_FIFO_Q00", - "Q01": "CMT_OUT_FIFO_Q01", - "Q02": "CMT_OUT_FIFO_Q02", - "Q03": "CMT_OUT_FIFO_Q03", - "Q10": "CMT_OUT_FIFO_Q10", - "Q11": "CMT_OUT_FIFO_Q11", - "Q12": "CMT_OUT_FIFO_Q12", - "Q13": "CMT_OUT_FIFO_Q13", - "Q20": "CMT_OUT_FIFO_Q20", - "Q21": "CMT_OUT_FIFO_Q21", - "Q22": "CMT_OUT_FIFO_Q22", - "Q23": "CMT_OUT_FIFO_Q23", - "Q30": "CMT_OUT_FIFO_Q30", - "Q31": "CMT_OUT_FIFO_Q31", - "Q32": "CMT_OUT_FIFO_Q32", - "Q33": "CMT_OUT_FIFO_Q33", - "Q40": "CMT_OUT_FIFO_Q40", - "Q41": "CMT_OUT_FIFO_Q41", - "Q42": "CMT_OUT_FIFO_Q42", - "Q43": "CMT_OUT_FIFO_Q43", - "Q50": "CMT_OUT_FIFO_Q50", - "Q51": "CMT_OUT_FIFO_Q51", - "Q52": "CMT_OUT_FIFO_Q52", - "Q53": "CMT_OUT_FIFO_Q53", - "Q54": "CMT_OUT_FIFO_Q54", - "Q55": "CMT_OUT_FIFO_Q55", - "Q56": "CMT_OUT_FIFO_Q56", - "Q57": "CMT_OUT_FIFO_Q57", - "Q60": "CMT_OUT_FIFO_Q60", - "Q61": "CMT_OUT_FIFO_Q61", - "Q62": "CMT_OUT_FIFO_Q62", - "Q63": "CMT_OUT_FIFO_Q63", - "Q64": "CMT_OUT_FIFO_Q64", - "Q65": "CMT_OUT_FIFO_Q65", - "Q66": "CMT_OUT_FIFO_Q66", - "Q67": "CMT_OUT_FIFO_Q67", - "Q70": "CMT_OUT_FIFO_Q70", - "Q71": "CMT_OUT_FIFO_Q71", - "Q72": "CMT_OUT_FIFO_Q72", - "Q73": "CMT_OUT_FIFO_Q73", - "Q80": "CMT_OUT_FIFO_Q80", - "Q81": "CMT_OUT_FIFO_Q81", - "Q82": "CMT_OUT_FIFO_Q82", - "Q83": "CMT_OUT_FIFO_Q83", - "Q90": "CMT_OUT_FIFO_Q90", - "Q91": "CMT_OUT_FIFO_Q91", - "Q92": "CMT_OUT_FIFO_Q92", - "Q93": "CMT_OUT_FIFO_Q93", - "RDCLK": "CMT_OUT_FIFO_RDCLK", - "RDEN": "CMT_OUT_FIFO_RDEN", - "RESET": "CMT_OUT_FIFO_RESET", - "SCANENB": "CMT_OUT_FIFO_SCANENB", - "SCANIN0": "CMT_OUT_FIFO_SCANIN0", - "SCANIN1": "CMT_OUT_FIFO_SCANIN1", - "SCANIN2": "CMT_OUT_FIFO_SCANIN2", - "SCANIN3": "CMT_OUT_FIFO_SCANIN3", - "SCANOUT0": "CMT_OUT_FIFO_SCANOUT0", - "SCANOUT1": "CMT_OUT_FIFO_SCANOUT1", - "SCANOUT2": "CMT_OUT_FIFO_SCANOUT2", - "SCANOUT3": "CMT_OUT_FIFO_SCANOUT3", - "TESTMODEB": "CMT_OUT_FIFO_TESTMODEB", - "TESTREADDISB": "CMT_OUT_FIFO_TESTREADDISB", - "TESTWRITEDISB": "CMT_OUT_FIFO_TESTWRITEDISB", - "WRCLK": "CMT_OUT_FIFO_WRCLK", - "WREN": "CMT_OUT_FIFO_WREN" + "ALMOSTEMPTY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_OUT_FIFO_ALMOSTEMPTY" + }, + "ALMOSTFULL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_OUT_FIFO_ALMOSTFULL" + }, + "D00": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D00" + }, + "D01": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D01" + }, + "D02": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D02" + }, + "D03": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D03" + }, + "D04": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D04" + }, + "D05": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D05" + }, + "D06": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D06" + }, + "D07": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D07" + }, + "D10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D10" + }, + "D11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D11" + }, + "D12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D12" + }, + "D13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D13" + }, + "D14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D14" + }, + "D15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D15" + }, + "D16": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D16" + }, + "D17": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D17" + }, + "D20": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D20" + }, + "D21": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D21" + }, + "D22": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D22" + }, + "D23": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D23" + }, + "D24": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D24" + }, + "D25": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D25" + }, + "D26": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D26" + }, + "D27": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D27" + }, + "D30": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D30" + }, + "D31": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D31" + }, + "D32": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D32" + }, + "D33": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D33" + }, + "D34": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D34" + }, + "D35": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D35" + }, + "D36": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D36" + }, + "D37": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D37" + }, + "D40": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_OUT_FIFO_D40" + }, + "D41": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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"CMT_FIFO_EE2A3_1", - "CMT_FIFO_EE2A3_10", - "CMT_FIFO_EE2A3_11", - "CMT_FIFO_EE2A3_2", - "CMT_FIFO_EE2A3_3", - "CMT_FIFO_EE2A3_4", - "CMT_FIFO_EE2A3_5", - "CMT_FIFO_EE2A3_6", - "CMT_FIFO_EE2A3_7", - "CMT_FIFO_EE2A3_8", - "CMT_FIFO_EE2A3_9", - "CMT_FIFO_EE2BEG0_0", - "CMT_FIFO_EE2BEG0_1", - "CMT_FIFO_EE2BEG0_10", - "CMT_FIFO_EE2BEG0_11", - "CMT_FIFO_EE2BEG0_2", - "CMT_FIFO_EE2BEG0_3", - "CMT_FIFO_EE2BEG0_4", - "CMT_FIFO_EE2BEG0_5", - "CMT_FIFO_EE2BEG0_6", - "CMT_FIFO_EE2BEG0_7", - "CMT_FIFO_EE2BEG0_8", - "CMT_FIFO_EE2BEG0_9", - "CMT_FIFO_EE2BEG1_0", - "CMT_FIFO_EE2BEG1_1", - "CMT_FIFO_EE2BEG1_10", - "CMT_FIFO_EE2BEG1_11", - "CMT_FIFO_EE2BEG1_2", - "CMT_FIFO_EE2BEG1_3", - "CMT_FIFO_EE2BEG1_4", - "CMT_FIFO_EE2BEG1_5", - "CMT_FIFO_EE2BEG1_6", - "CMT_FIFO_EE2BEG1_7", - "CMT_FIFO_EE2BEG1_8", - "CMT_FIFO_EE2BEG1_9", - "CMT_FIFO_EE2BEG2_0", - "CMT_FIFO_EE2BEG2_1", - "CMT_FIFO_EE2BEG2_10", - "CMT_FIFO_EE2BEG2_11", - "CMT_FIFO_EE2BEG2_2", - "CMT_FIFO_EE2BEG2_3", - "CMT_FIFO_EE2BEG2_4", - "CMT_FIFO_EE2BEG2_5", - "CMT_FIFO_EE2BEG2_6", - "CMT_FIFO_EE2BEG2_7", - "CMT_FIFO_EE2BEG2_8", - "CMT_FIFO_EE2BEG2_9", - "CMT_FIFO_EE2BEG3_0", - "CMT_FIFO_EE2BEG3_1", - "CMT_FIFO_EE2BEG3_10", - "CMT_FIFO_EE2BEG3_11", - "CMT_FIFO_EE2BEG3_2", - "CMT_FIFO_EE2BEG3_3", - "CMT_FIFO_EE2BEG3_4", - "CMT_FIFO_EE2BEG3_5", - "CMT_FIFO_EE2BEG3_6", - "CMT_FIFO_EE2BEG3_7", - "CMT_FIFO_EE2BEG3_8", - "CMT_FIFO_EE2BEG3_9", - "CMT_FIFO_EE4A0_0", - "CMT_FIFO_EE4A0_1", - "CMT_FIFO_EE4A0_10", - "CMT_FIFO_EE4A0_11", - "CMT_FIFO_EE4A0_2", - "CMT_FIFO_EE4A0_3", - "CMT_FIFO_EE4A0_4", - "CMT_FIFO_EE4A0_5", - "CMT_FIFO_EE4A0_6", - "CMT_FIFO_EE4A0_7", - "CMT_FIFO_EE4A0_8", - "CMT_FIFO_EE4A0_9", - "CMT_FIFO_EE4A1_0", - "CMT_FIFO_EE4A1_1", - "CMT_FIFO_EE4A1_10", - "CMT_FIFO_EE4A1_11", - "CMT_FIFO_EE4A1_2", - "CMT_FIFO_EE4A1_3", - "CMT_FIFO_EE4A1_4", - "CMT_FIFO_EE4A1_5", - "CMT_FIFO_EE4A1_6", - "CMT_FIFO_EE4A1_7", - "CMT_FIFO_EE4A1_8", - "CMT_FIFO_EE4A1_9", - "CMT_FIFO_EE4A2_0", - "CMT_FIFO_EE4A2_1", - "CMT_FIFO_EE4A2_10", - "CMT_FIFO_EE4A2_11", - "CMT_FIFO_EE4A2_2", - "CMT_FIFO_EE4A2_3", - "CMT_FIFO_EE4A2_4", - "CMT_FIFO_EE4A2_5", - "CMT_FIFO_EE4A2_6", - "CMT_FIFO_EE4A2_7", - "CMT_FIFO_EE4A2_8", - "CMT_FIFO_EE4A2_9", - "CMT_FIFO_EE4A3_0", - "CMT_FIFO_EE4A3_1", - "CMT_FIFO_EE4A3_10", - "CMT_FIFO_EE4A3_11", - "CMT_FIFO_EE4A3_2", - "CMT_FIFO_EE4A3_3", - "CMT_FIFO_EE4A3_4", - "CMT_FIFO_EE4A3_5", - "CMT_FIFO_EE4A3_6", - "CMT_FIFO_EE4A3_7", - "CMT_FIFO_EE4A3_8", - "CMT_FIFO_EE4A3_9", - "CMT_FIFO_EE4B0_0", - "CMT_FIFO_EE4B0_1", - "CMT_FIFO_EE4B0_10", - "CMT_FIFO_EE4B0_11", - "CMT_FIFO_EE4B0_2", - "CMT_FIFO_EE4B0_3", - "CMT_FIFO_EE4B0_4", - "CMT_FIFO_EE4B0_5", - "CMT_FIFO_EE4B0_6", - "CMT_FIFO_EE4B0_7", - "CMT_FIFO_EE4B0_8", - "CMT_FIFO_EE4B0_9", - "CMT_FIFO_EE4B1_0", - "CMT_FIFO_EE4B1_1", - "CMT_FIFO_EE4B1_10", - "CMT_FIFO_EE4B1_11", - "CMT_FIFO_EE4B1_2", - "CMT_FIFO_EE4B1_3", - "CMT_FIFO_EE4B1_4", - "CMT_FIFO_EE4B1_5", - "CMT_FIFO_EE4B1_6", - "CMT_FIFO_EE4B1_7", - "CMT_FIFO_EE4B1_8", - "CMT_FIFO_EE4B1_9", - "CMT_FIFO_EE4B2_0", - "CMT_FIFO_EE4B2_1", - "CMT_FIFO_EE4B2_10", - "CMT_FIFO_EE4B2_11", - "CMT_FIFO_EE4B2_2", - "CMT_FIFO_EE4B2_3", - "CMT_FIFO_EE4B2_4", - "CMT_FIFO_EE4B2_5", - "CMT_FIFO_EE4B2_6", - "CMT_FIFO_EE4B2_7", - "CMT_FIFO_EE4B2_8", - "CMT_FIFO_EE4B2_9", - "CMT_FIFO_EE4B3_0", - "CMT_FIFO_EE4B3_1", - "CMT_FIFO_EE4B3_10", - "CMT_FIFO_EE4B3_11", - "CMT_FIFO_EE4B3_2", - "CMT_FIFO_EE4B3_3", - "CMT_FIFO_EE4B3_4", - "CMT_FIFO_EE4B3_5", - "CMT_FIFO_EE4B3_6", - "CMT_FIFO_EE4B3_7", - "CMT_FIFO_EE4B3_8", - "CMT_FIFO_EE4B3_9", - "CMT_FIFO_EE4BEG0_0", - "CMT_FIFO_EE4BEG0_1", - "CMT_FIFO_EE4BEG0_10", - "CMT_FIFO_EE4BEG0_11", - "CMT_FIFO_EE4BEG0_2", - "CMT_FIFO_EE4BEG0_3", - "CMT_FIFO_EE4BEG0_4", - "CMT_FIFO_EE4BEG0_5", - "CMT_FIFO_EE4BEG0_6", - "CMT_FIFO_EE4BEG0_7", - "CMT_FIFO_EE4BEG0_8", - "CMT_FIFO_EE4BEG0_9", - "CMT_FIFO_EE4BEG1_0", - "CMT_FIFO_EE4BEG1_1", - "CMT_FIFO_EE4BEG1_10", - "CMT_FIFO_EE4BEG1_11", - "CMT_FIFO_EE4BEG1_2", - "CMT_FIFO_EE4BEG1_3", - "CMT_FIFO_EE4BEG1_4", - "CMT_FIFO_EE4BEG1_5", - "CMT_FIFO_EE4BEG1_6", - "CMT_FIFO_EE4BEG1_7", - "CMT_FIFO_EE4BEG1_8", - "CMT_FIFO_EE4BEG1_9", - "CMT_FIFO_EE4BEG2_0", - "CMT_FIFO_EE4BEG2_1", - "CMT_FIFO_EE4BEG2_10", - "CMT_FIFO_EE4BEG2_11", - "CMT_FIFO_EE4BEG2_2", - "CMT_FIFO_EE4BEG2_3", - "CMT_FIFO_EE4BEG2_4", - "CMT_FIFO_EE4BEG2_5", - "CMT_FIFO_EE4BEG2_6", - "CMT_FIFO_EE4BEG2_7", - "CMT_FIFO_EE4BEG2_8", - "CMT_FIFO_EE4BEG2_9", - "CMT_FIFO_EE4BEG3_0", - "CMT_FIFO_EE4BEG3_1", - "CMT_FIFO_EE4BEG3_10", - "CMT_FIFO_EE4BEG3_11", - "CMT_FIFO_EE4BEG3_2", - "CMT_FIFO_EE4BEG3_3", - "CMT_FIFO_EE4BEG3_4", - "CMT_FIFO_EE4BEG3_5", - "CMT_FIFO_EE4BEG3_6", - "CMT_FIFO_EE4BEG3_7", - "CMT_FIFO_EE4BEG3_8", - "CMT_FIFO_EE4BEG3_9", - "CMT_FIFO_EE4C0_0", - "CMT_FIFO_EE4C0_1", - "CMT_FIFO_EE4C0_10", - "CMT_FIFO_EE4C0_11", - "CMT_FIFO_EE4C0_2", - "CMT_FIFO_EE4C0_3", - "CMT_FIFO_EE4C0_4", - "CMT_FIFO_EE4C0_5", - "CMT_FIFO_EE4C0_6", - "CMT_FIFO_EE4C0_7", - "CMT_FIFO_EE4C0_8", - "CMT_FIFO_EE4C0_9", - "CMT_FIFO_EE4C1_0", - "CMT_FIFO_EE4C1_1", - "CMT_FIFO_EE4C1_10", - "CMT_FIFO_EE4C1_11", - "CMT_FIFO_EE4C1_2", - "CMT_FIFO_EE4C1_3", - "CMT_FIFO_EE4C1_4", - "CMT_FIFO_EE4C1_5", - "CMT_FIFO_EE4C1_6", - "CMT_FIFO_EE4C1_7", - "CMT_FIFO_EE4C1_8", - "CMT_FIFO_EE4C1_9", - "CMT_FIFO_EE4C2_0", - "CMT_FIFO_EE4C2_1", - "CMT_FIFO_EE4C2_10", - "CMT_FIFO_EE4C2_11", - "CMT_FIFO_EE4C2_2", - "CMT_FIFO_EE4C2_3", - "CMT_FIFO_EE4C2_4", - "CMT_FIFO_EE4C2_5", - "CMT_FIFO_EE4C2_6", - "CMT_FIFO_EE4C2_7", - "CMT_FIFO_EE4C2_8", - "CMT_FIFO_EE4C2_9", - "CMT_FIFO_EE4C3_0", - "CMT_FIFO_EE4C3_1", - "CMT_FIFO_EE4C3_10", - "CMT_FIFO_EE4C3_11", - "CMT_FIFO_EE4C3_2", - "CMT_FIFO_EE4C3_3", - "CMT_FIFO_EE4C3_4", - "CMT_FIFO_EE4C3_5", - "CMT_FIFO_EE4C3_6", - "CMT_FIFO_EE4C3_7", - "CMT_FIFO_EE4C3_8", - "CMT_FIFO_EE4C3_9", - "CMT_FIFO_EL1BEG0_0", - "CMT_FIFO_EL1BEG0_1", - "CMT_FIFO_EL1BEG0_10", - "CMT_FIFO_EL1BEG0_11", - "CMT_FIFO_EL1BEG0_2", - "CMT_FIFO_EL1BEG0_3", - "CMT_FIFO_EL1BEG0_4", - "CMT_FIFO_EL1BEG0_5", - "CMT_FIFO_EL1BEG0_6", - "CMT_FIFO_EL1BEG0_7", - "CMT_FIFO_EL1BEG0_8", - "CMT_FIFO_EL1BEG0_9", - "CMT_FIFO_EL1BEG1_0", - "CMT_FIFO_EL1BEG1_1", - "CMT_FIFO_EL1BEG1_10", - "CMT_FIFO_EL1BEG1_11", - "CMT_FIFO_EL1BEG1_2", - "CMT_FIFO_EL1BEG1_3", - "CMT_FIFO_EL1BEG1_4", - "CMT_FIFO_EL1BEG1_5", - "CMT_FIFO_EL1BEG1_6", - "CMT_FIFO_EL1BEG1_7", - "CMT_FIFO_EL1BEG1_8", - "CMT_FIFO_EL1BEG1_9", - "CMT_FIFO_EL1BEG2_0", - "CMT_FIFO_EL1BEG2_1", - "CMT_FIFO_EL1BEG2_10", - "CMT_FIFO_EL1BEG2_11", - "CMT_FIFO_EL1BEG2_2", - "CMT_FIFO_EL1BEG2_3", - "CMT_FIFO_EL1BEG2_4", - "CMT_FIFO_EL1BEG2_5", - "CMT_FIFO_EL1BEG2_6", - "CMT_FIFO_EL1BEG2_7", - "CMT_FIFO_EL1BEG2_8", - "CMT_FIFO_EL1BEG2_9", - "CMT_FIFO_EL1BEG3_0", - "CMT_FIFO_EL1BEG3_1", - "CMT_FIFO_EL1BEG3_10", - "CMT_FIFO_EL1BEG3_11", - "CMT_FIFO_EL1BEG3_2", - "CMT_FIFO_EL1BEG3_3", - "CMT_FIFO_EL1BEG3_4", - "CMT_FIFO_EL1BEG3_5", - "CMT_FIFO_EL1BEG3_6", - "CMT_FIFO_EL1BEG3_7", - "CMT_FIFO_EL1BEG3_8", - "CMT_FIFO_EL1BEG3_9", - "CMT_FIFO_ER1BEG0_0", - "CMT_FIFO_ER1BEG0_1", - "CMT_FIFO_ER1BEG0_10", - "CMT_FIFO_ER1BEG0_11", - "CMT_FIFO_ER1BEG0_2", - "CMT_FIFO_ER1BEG0_3", - "CMT_FIFO_ER1BEG0_4", - "CMT_FIFO_ER1BEG0_5", - "CMT_FIFO_ER1BEG0_6", - "CMT_FIFO_ER1BEG0_7", - "CMT_FIFO_ER1BEG0_8", - "CMT_FIFO_ER1BEG0_9", - "CMT_FIFO_ER1BEG1_0", - "CMT_FIFO_ER1BEG1_1", - "CMT_FIFO_ER1BEG1_10", - "CMT_FIFO_ER1BEG1_11", - "CMT_FIFO_ER1BEG1_2", - "CMT_FIFO_ER1BEG1_3", - "CMT_FIFO_ER1BEG1_4", - "CMT_FIFO_ER1BEG1_5", - "CMT_FIFO_ER1BEG1_6", - "CMT_FIFO_ER1BEG1_7", - "CMT_FIFO_ER1BEG1_8", - "CMT_FIFO_ER1BEG1_9", - "CMT_FIFO_ER1BEG2_0", - "CMT_FIFO_ER1BEG2_1", - "CMT_FIFO_ER1BEG2_10", - "CMT_FIFO_ER1BEG2_11", - "CMT_FIFO_ER1BEG2_2", - "CMT_FIFO_ER1BEG2_3", - "CMT_FIFO_ER1BEG2_4", - "CMT_FIFO_ER1BEG2_5", - "CMT_FIFO_ER1BEG2_6", - "CMT_FIFO_ER1BEG2_7", - "CMT_FIFO_ER1BEG2_8", - "CMT_FIFO_ER1BEG2_9", - "CMT_FIFO_ER1BEG3_0", - "CMT_FIFO_ER1BEG3_1", - "CMT_FIFO_ER1BEG3_10", - "CMT_FIFO_ER1BEG3_11", - "CMT_FIFO_ER1BEG3_2", - "CMT_FIFO_ER1BEG3_3", - "CMT_FIFO_ER1BEG3_4", - "CMT_FIFO_ER1BEG3_5", - "CMT_FIFO_ER1BEG3_6", - "CMT_FIFO_ER1BEG3_7", - "CMT_FIFO_ER1BEG3_8", - "CMT_FIFO_ER1BEG3_9", - "CMT_FIFO_LH10_0", - "CMT_FIFO_LH10_1", - "CMT_FIFO_LH10_10", - "CMT_FIFO_LH10_11", - "CMT_FIFO_LH10_2", - "CMT_FIFO_LH10_3", - "CMT_FIFO_LH10_4", - "CMT_FIFO_LH10_5", - "CMT_FIFO_LH10_6", - "CMT_FIFO_LH10_7", - "CMT_FIFO_LH10_8", - "CMT_FIFO_LH10_9", - "CMT_FIFO_LH11_0", - "CMT_FIFO_LH11_1", - "CMT_FIFO_LH11_10", - "CMT_FIFO_LH11_11", - "CMT_FIFO_LH11_2", - "CMT_FIFO_LH11_3", - "CMT_FIFO_LH11_4", - "CMT_FIFO_LH11_5", - "CMT_FIFO_LH11_6", - "CMT_FIFO_LH11_7", - "CMT_FIFO_LH11_8", - "CMT_FIFO_LH11_9", - "CMT_FIFO_LH12_0", - "CMT_FIFO_LH12_1", - "CMT_FIFO_LH12_10", - "CMT_FIFO_LH12_11", - "CMT_FIFO_LH12_2", - "CMT_FIFO_LH12_3", - "CMT_FIFO_LH12_4", - "CMT_FIFO_LH12_5", - "CMT_FIFO_LH12_6", - "CMT_FIFO_LH12_7", - "CMT_FIFO_LH12_8", - "CMT_FIFO_LH12_9", - "CMT_FIFO_LH1_0", - "CMT_FIFO_LH1_1", - "CMT_FIFO_LH1_10", - "CMT_FIFO_LH1_11", - "CMT_FIFO_LH1_2", - "CMT_FIFO_LH1_3", - "CMT_FIFO_LH1_4", - "CMT_FIFO_LH1_5", - "CMT_FIFO_LH1_6", - "CMT_FIFO_LH1_7", - "CMT_FIFO_LH1_8", - "CMT_FIFO_LH1_9", - "CMT_FIFO_LH2_0", - "CMT_FIFO_LH2_1", - "CMT_FIFO_LH2_10", - "CMT_FIFO_LH2_11", - "CMT_FIFO_LH2_2", - "CMT_FIFO_LH2_3", - "CMT_FIFO_LH2_4", - "CMT_FIFO_LH2_5", - "CMT_FIFO_LH2_6", - "CMT_FIFO_LH2_7", - "CMT_FIFO_LH2_8", - "CMT_FIFO_LH2_9", - "CMT_FIFO_LH3_0", - "CMT_FIFO_LH3_1", - "CMT_FIFO_LH3_10", - "CMT_FIFO_LH3_11", - "CMT_FIFO_LH3_2", - "CMT_FIFO_LH3_3", - "CMT_FIFO_LH3_4", - "CMT_FIFO_LH3_5", - "CMT_FIFO_LH3_6", - "CMT_FIFO_LH3_7", - "CMT_FIFO_LH3_8", - "CMT_FIFO_LH3_9", - "CMT_FIFO_LH4_0", - "CMT_FIFO_LH4_1", - "CMT_FIFO_LH4_10", - "CMT_FIFO_LH4_11", - "CMT_FIFO_LH4_2", - "CMT_FIFO_LH4_3", - "CMT_FIFO_LH4_4", - "CMT_FIFO_LH4_5", - "CMT_FIFO_LH4_6", - "CMT_FIFO_LH4_7", - "CMT_FIFO_LH4_8", - "CMT_FIFO_LH4_9", - "CMT_FIFO_LH5_0", - "CMT_FIFO_LH5_1", - "CMT_FIFO_LH5_10", - "CMT_FIFO_LH5_11", - "CMT_FIFO_LH5_2", - "CMT_FIFO_LH5_3", - "CMT_FIFO_LH5_4", - "CMT_FIFO_LH5_5", - "CMT_FIFO_LH5_6", - "CMT_FIFO_LH5_7", - "CMT_FIFO_LH5_8", - "CMT_FIFO_LH5_9", - "CMT_FIFO_LH6_0", - "CMT_FIFO_LH6_1", - "CMT_FIFO_LH6_10", - "CMT_FIFO_LH6_11", - "CMT_FIFO_LH6_2", - "CMT_FIFO_LH6_3", - "CMT_FIFO_LH6_4", - "CMT_FIFO_LH6_5", - "CMT_FIFO_LH6_6", - "CMT_FIFO_LH6_7", - "CMT_FIFO_LH6_8", - "CMT_FIFO_LH6_9", - "CMT_FIFO_LH7_0", - "CMT_FIFO_LH7_1", - "CMT_FIFO_LH7_10", - "CMT_FIFO_LH7_11", - "CMT_FIFO_LH7_2", - "CMT_FIFO_LH7_3", - "CMT_FIFO_LH7_4", - "CMT_FIFO_LH7_5", - "CMT_FIFO_LH7_6", - "CMT_FIFO_LH7_7", - "CMT_FIFO_LH7_8", - "CMT_FIFO_LH7_9", - "CMT_FIFO_LH8_0", - "CMT_FIFO_LH8_1", - "CMT_FIFO_LH8_10", - "CMT_FIFO_LH8_11", - "CMT_FIFO_LH8_2", - "CMT_FIFO_LH8_3", - "CMT_FIFO_LH8_4", - "CMT_FIFO_LH8_5", - "CMT_FIFO_LH8_6", - "CMT_FIFO_LH8_7", - "CMT_FIFO_LH8_8", - "CMT_FIFO_LH8_9", - "CMT_FIFO_LH9_0", - "CMT_FIFO_LH9_1", - "CMT_FIFO_LH9_10", - "CMT_FIFO_LH9_11", - "CMT_FIFO_LH9_2", - "CMT_FIFO_LH9_3", - "CMT_FIFO_LH9_4", - "CMT_FIFO_LH9_5", - "CMT_FIFO_LH9_6", - "CMT_FIFO_LH9_7", - "CMT_FIFO_LH9_8", - "CMT_FIFO_LH9_9", - "CMT_FIFO_L_BYP0_0", - "CMT_FIFO_L_BYP0_1", - "CMT_FIFO_L_BYP0_10", - "CMT_FIFO_L_BYP0_11", - "CMT_FIFO_L_BYP0_2", - "CMT_FIFO_L_BYP0_3", - "CMT_FIFO_L_BYP0_4", - "CMT_FIFO_L_BYP0_5", - "CMT_FIFO_L_BYP0_6", - "CMT_FIFO_L_BYP0_7", - "CMT_FIFO_L_BYP0_8", - "CMT_FIFO_L_BYP0_9", - "CMT_FIFO_L_BYP1_0", - "CMT_FIFO_L_BYP1_1", - "CMT_FIFO_L_BYP1_10", - "CMT_FIFO_L_BYP1_11", - "CMT_FIFO_L_BYP1_2", - "CMT_FIFO_L_BYP1_3", - "CMT_FIFO_L_BYP1_4", - "CMT_FIFO_L_BYP1_5", - "CMT_FIFO_L_BYP1_6", - "CMT_FIFO_L_BYP1_7", - "CMT_FIFO_L_BYP1_8", - "CMT_FIFO_L_BYP1_9", - "CMT_FIFO_L_BYP2_0", - "CMT_FIFO_L_BYP2_1", - "CMT_FIFO_L_BYP2_10", - "CMT_FIFO_L_BYP2_11", - "CMT_FIFO_L_BYP2_2", - "CMT_FIFO_L_BYP2_3", - "CMT_FIFO_L_BYP2_4", - "CMT_FIFO_L_BYP2_5", - "CMT_FIFO_L_BYP2_6", - "CMT_FIFO_L_BYP2_7", - "CMT_FIFO_L_BYP2_8", - "CMT_FIFO_L_BYP2_9", - "CMT_FIFO_L_BYP3_0", - "CMT_FIFO_L_BYP3_1", - "CMT_FIFO_L_BYP3_10", - "CMT_FIFO_L_BYP3_11", - "CMT_FIFO_L_BYP3_2", - "CMT_FIFO_L_BYP3_3", - "CMT_FIFO_L_BYP3_4", - "CMT_FIFO_L_BYP3_5", - "CMT_FIFO_L_BYP3_6", - "CMT_FIFO_L_BYP3_7", - "CMT_FIFO_L_BYP3_8", - "CMT_FIFO_L_BYP3_9", - "CMT_FIFO_L_BYP4_0", - "CMT_FIFO_L_BYP4_1", - "CMT_FIFO_L_BYP4_10", - "CMT_FIFO_L_BYP4_11", - "CMT_FIFO_L_BYP4_2", - "CMT_FIFO_L_BYP4_3", - "CMT_FIFO_L_BYP4_4", - "CMT_FIFO_L_BYP4_5", - "CMT_FIFO_L_BYP4_6", - "CMT_FIFO_L_BYP4_7", - "CMT_FIFO_L_BYP4_8", - "CMT_FIFO_L_BYP4_9", - "CMT_FIFO_L_BYP5_0", - "CMT_FIFO_L_BYP5_1", - "CMT_FIFO_L_BYP5_10", - "CMT_FIFO_L_BYP5_11", - "CMT_FIFO_L_BYP5_2", - "CMT_FIFO_L_BYP5_3", - "CMT_FIFO_L_BYP5_4", - "CMT_FIFO_L_BYP5_5", - "CMT_FIFO_L_BYP5_6", - "CMT_FIFO_L_BYP5_7", - "CMT_FIFO_L_BYP5_8", - "CMT_FIFO_L_BYP5_9", - "CMT_FIFO_L_BYP6_0", - "CMT_FIFO_L_BYP6_1", - "CMT_FIFO_L_BYP6_10", - "CMT_FIFO_L_BYP6_11", - "CMT_FIFO_L_BYP6_2", - "CMT_FIFO_L_BYP6_3", - "CMT_FIFO_L_BYP6_4", - "CMT_FIFO_L_BYP6_5", - "CMT_FIFO_L_BYP6_6", - "CMT_FIFO_L_BYP6_7", - "CMT_FIFO_L_BYP6_8", - "CMT_FIFO_L_BYP6_9", - "CMT_FIFO_L_BYP7_0", - "CMT_FIFO_L_BYP7_1", - "CMT_FIFO_L_BYP7_10", - "CMT_FIFO_L_BYP7_11", - "CMT_FIFO_L_BYP7_2", - "CMT_FIFO_L_BYP7_3", - "CMT_FIFO_L_BYP7_4", - "CMT_FIFO_L_BYP7_5", - "CMT_FIFO_L_BYP7_6", - "CMT_FIFO_L_BYP7_7", - "CMT_FIFO_L_BYP7_8", - "CMT_FIFO_L_BYP7_9", - "CMT_FIFO_L_CLK0_0", - "CMT_FIFO_L_CLK0_1", - "CMT_FIFO_L_CLK0_10", - "CMT_FIFO_L_CLK0_11", - "CMT_FIFO_L_CLK0_2", - "CMT_FIFO_L_CLK0_3", - "CMT_FIFO_L_CLK0_4", - "CMT_FIFO_L_CLK0_5", - "CMT_FIFO_L_CLK0_6", - "CMT_FIFO_L_CLK0_7", - "CMT_FIFO_L_CLK0_8", - "CMT_FIFO_L_CLK0_9", - "CMT_FIFO_L_CLK1_0", - "CMT_FIFO_L_CLK1_1", - "CMT_FIFO_L_CLK1_10", - "CMT_FIFO_L_CLK1_11", - "CMT_FIFO_L_CLK1_2", - "CMT_FIFO_L_CLK1_3", - "CMT_FIFO_L_CLK1_4", - "CMT_FIFO_L_CLK1_5", - "CMT_FIFO_L_CLK1_6", - "CMT_FIFO_L_CLK1_7", - "CMT_FIFO_L_CLK1_8", - "CMT_FIFO_L_CLK1_9", - "CMT_FIFO_L_CTRL0_0", - "CMT_FIFO_L_CTRL0_1", - "CMT_FIFO_L_CTRL0_10", - "CMT_FIFO_L_CTRL0_11", - "CMT_FIFO_L_CTRL0_2", - "CMT_FIFO_L_CTRL0_3", - "CMT_FIFO_L_CTRL0_4", - "CMT_FIFO_L_CTRL0_5", - "CMT_FIFO_L_CTRL0_6", - "CMT_FIFO_L_CTRL0_7", - "CMT_FIFO_L_CTRL0_8", - "CMT_FIFO_L_CTRL0_9", - "CMT_FIFO_L_CTRL1_0", - "CMT_FIFO_L_CTRL1_1", - "CMT_FIFO_L_CTRL1_10", - "CMT_FIFO_L_CTRL1_11", - "CMT_FIFO_L_CTRL1_2", - "CMT_FIFO_L_CTRL1_3", - "CMT_FIFO_L_CTRL1_4", - "CMT_FIFO_L_CTRL1_5", - "CMT_FIFO_L_CTRL1_6", - "CMT_FIFO_L_CTRL1_7", - "CMT_FIFO_L_CTRL1_8", - "CMT_FIFO_L_CTRL1_9", - "CMT_FIFO_L_FAN0_0", - "CMT_FIFO_L_FAN0_1", - "CMT_FIFO_L_FAN0_10", - "CMT_FIFO_L_FAN0_11", - "CMT_FIFO_L_FAN0_2", - "CMT_FIFO_L_FAN0_3", - "CMT_FIFO_L_FAN0_4", - "CMT_FIFO_L_FAN0_5", - "CMT_FIFO_L_FAN0_6", - "CMT_FIFO_L_FAN0_7", - "CMT_FIFO_L_FAN0_8", - "CMT_FIFO_L_FAN0_9", - "CMT_FIFO_L_FAN1_0", - "CMT_FIFO_L_FAN1_1", - "CMT_FIFO_L_FAN1_10", - "CMT_FIFO_L_FAN1_11", - "CMT_FIFO_L_FAN1_2", - "CMT_FIFO_L_FAN1_3", - "CMT_FIFO_L_FAN1_4", - "CMT_FIFO_L_FAN1_5", - "CMT_FIFO_L_FAN1_6", - "CMT_FIFO_L_FAN1_7", - "CMT_FIFO_L_FAN1_8", - "CMT_FIFO_L_FAN1_9", - "CMT_FIFO_L_FAN2_0", - "CMT_FIFO_L_FAN2_1", - "CMT_FIFO_L_FAN2_10", - "CMT_FIFO_L_FAN2_11", - "CMT_FIFO_L_FAN2_2", - "CMT_FIFO_L_FAN2_3", - "CMT_FIFO_L_FAN2_4", - "CMT_FIFO_L_FAN2_5", - "CMT_FIFO_L_FAN2_6", - "CMT_FIFO_L_FAN2_7", - "CMT_FIFO_L_FAN2_8", - "CMT_FIFO_L_FAN2_9", - "CMT_FIFO_L_FAN3_0", - "CMT_FIFO_L_FAN3_1", - "CMT_FIFO_L_FAN3_10", - "CMT_FIFO_L_FAN3_11", - "CMT_FIFO_L_FAN3_2", - "CMT_FIFO_L_FAN3_3", - "CMT_FIFO_L_FAN3_4", - "CMT_FIFO_L_FAN3_5", - "CMT_FIFO_L_FAN3_6", - "CMT_FIFO_L_FAN3_7", - "CMT_FIFO_L_FAN3_8", - "CMT_FIFO_L_FAN3_9", - "CMT_FIFO_L_FAN4_0", - "CMT_FIFO_L_FAN4_1", - "CMT_FIFO_L_FAN4_10", - "CMT_FIFO_L_FAN4_11", - "CMT_FIFO_L_FAN4_2", - "CMT_FIFO_L_FAN4_3", - "CMT_FIFO_L_FAN4_4", - "CMT_FIFO_L_FAN4_5", - "CMT_FIFO_L_FAN4_6", - "CMT_FIFO_L_FAN4_7", - "CMT_FIFO_L_FAN4_8", - "CMT_FIFO_L_FAN4_9", - "CMT_FIFO_L_FAN5_0", - "CMT_FIFO_L_FAN5_1", - "CMT_FIFO_L_FAN5_10", - "CMT_FIFO_L_FAN5_11", - "CMT_FIFO_L_FAN5_2", - "CMT_FIFO_L_FAN5_3", - "CMT_FIFO_L_FAN5_4", - "CMT_FIFO_L_FAN5_5", - "CMT_FIFO_L_FAN5_6", - "CMT_FIFO_L_FAN5_7", - "CMT_FIFO_L_FAN5_8", - "CMT_FIFO_L_FAN5_9", - "CMT_FIFO_L_FAN6_0", - "CMT_FIFO_L_FAN6_1", - "CMT_FIFO_L_FAN6_10", - "CMT_FIFO_L_FAN6_11", - "CMT_FIFO_L_FAN6_2", - "CMT_FIFO_L_FAN6_3", - "CMT_FIFO_L_FAN6_4", - "CMT_FIFO_L_FAN6_5", - "CMT_FIFO_L_FAN6_6", - "CMT_FIFO_L_FAN6_7", - "CMT_FIFO_L_FAN6_8", - "CMT_FIFO_L_FAN6_9", - "CMT_FIFO_L_FAN7_0", - "CMT_FIFO_L_FAN7_1", - "CMT_FIFO_L_FAN7_10", - "CMT_FIFO_L_FAN7_11", - "CMT_FIFO_L_FAN7_2", - "CMT_FIFO_L_FAN7_3", - "CMT_FIFO_L_FAN7_4", - "CMT_FIFO_L_FAN7_5", - "CMT_FIFO_L_FAN7_6", - "CMT_FIFO_L_FAN7_7", - "CMT_FIFO_L_FAN7_8", - "CMT_FIFO_L_FAN7_9", - "CMT_FIFO_L_IMUX0_0", - "CMT_FIFO_L_IMUX0_1", - "CMT_FIFO_L_IMUX0_10", - "CMT_FIFO_L_IMUX0_11", - "CMT_FIFO_L_IMUX0_2", - "CMT_FIFO_L_IMUX0_3", - "CMT_FIFO_L_IMUX0_4", - "CMT_FIFO_L_IMUX0_5", - "CMT_FIFO_L_IMUX0_6", - "CMT_FIFO_L_IMUX0_7", - "CMT_FIFO_L_IMUX0_8", - "CMT_FIFO_L_IMUX0_9", - "CMT_FIFO_L_IMUX10_0", - "CMT_FIFO_L_IMUX10_1", - "CMT_FIFO_L_IMUX10_10", - "CMT_FIFO_L_IMUX10_11", - "CMT_FIFO_L_IMUX10_2", - "CMT_FIFO_L_IMUX10_3", - "CMT_FIFO_L_IMUX10_4", - "CMT_FIFO_L_IMUX10_5", - "CMT_FIFO_L_IMUX10_6", - "CMT_FIFO_L_IMUX10_7", - "CMT_FIFO_L_IMUX10_8", - "CMT_FIFO_L_IMUX10_9", - "CMT_FIFO_L_IMUX11_0", - "CMT_FIFO_L_IMUX11_1", - "CMT_FIFO_L_IMUX11_10", - "CMT_FIFO_L_IMUX11_11", - "CMT_FIFO_L_IMUX11_2", - "CMT_FIFO_L_IMUX11_3", - "CMT_FIFO_L_IMUX11_4", - "CMT_FIFO_L_IMUX11_5", - "CMT_FIFO_L_IMUX11_6", - "CMT_FIFO_L_IMUX11_7", - "CMT_FIFO_L_IMUX11_8", - "CMT_FIFO_L_IMUX11_9", - "CMT_FIFO_L_IMUX12_0", - "CMT_FIFO_L_IMUX12_1", - "CMT_FIFO_L_IMUX12_10", - "CMT_FIFO_L_IMUX12_11", - "CMT_FIFO_L_IMUX12_2", - "CMT_FIFO_L_IMUX12_3", - "CMT_FIFO_L_IMUX12_4", - "CMT_FIFO_L_IMUX12_5", - "CMT_FIFO_L_IMUX12_6", - "CMT_FIFO_L_IMUX12_7", - "CMT_FIFO_L_IMUX12_8", - "CMT_FIFO_L_IMUX12_9", - "CMT_FIFO_L_IMUX13_0", - "CMT_FIFO_L_IMUX13_1", - "CMT_FIFO_L_IMUX13_10", - "CMT_FIFO_L_IMUX13_11", - "CMT_FIFO_L_IMUX13_2", - "CMT_FIFO_L_IMUX13_3", - "CMT_FIFO_L_IMUX13_4", - "CMT_FIFO_L_IMUX13_5", - "CMT_FIFO_L_IMUX13_6", - "CMT_FIFO_L_IMUX13_7", - "CMT_FIFO_L_IMUX13_8", - "CMT_FIFO_L_IMUX13_9", - "CMT_FIFO_L_IMUX14_0", - "CMT_FIFO_L_IMUX14_1", - "CMT_FIFO_L_IMUX14_10", - "CMT_FIFO_L_IMUX14_11", - "CMT_FIFO_L_IMUX14_2", - "CMT_FIFO_L_IMUX14_3", - "CMT_FIFO_L_IMUX14_4", - "CMT_FIFO_L_IMUX14_5", - "CMT_FIFO_L_IMUX14_6", - "CMT_FIFO_L_IMUX14_7", - "CMT_FIFO_L_IMUX14_8", - "CMT_FIFO_L_IMUX14_9", - "CMT_FIFO_L_IMUX15_0", - "CMT_FIFO_L_IMUX15_1", - "CMT_FIFO_L_IMUX15_10", - "CMT_FIFO_L_IMUX15_11", - "CMT_FIFO_L_IMUX15_2", - "CMT_FIFO_L_IMUX15_3", - "CMT_FIFO_L_IMUX15_4", - "CMT_FIFO_L_IMUX15_5", - "CMT_FIFO_L_IMUX15_6", - "CMT_FIFO_L_IMUX15_7", - "CMT_FIFO_L_IMUX15_8", - "CMT_FIFO_L_IMUX15_9", - "CMT_FIFO_L_IMUX16_0", - "CMT_FIFO_L_IMUX16_1", - "CMT_FIFO_L_IMUX16_10", - "CMT_FIFO_L_IMUX16_11", - "CMT_FIFO_L_IMUX16_2", - "CMT_FIFO_L_IMUX16_3", - "CMT_FIFO_L_IMUX16_4", - "CMT_FIFO_L_IMUX16_5", - "CMT_FIFO_L_IMUX16_6", - "CMT_FIFO_L_IMUX16_7", - "CMT_FIFO_L_IMUX16_8", - "CMT_FIFO_L_IMUX16_9", - "CMT_FIFO_L_IMUX17_0", - "CMT_FIFO_L_IMUX17_1", - "CMT_FIFO_L_IMUX17_10", - "CMT_FIFO_L_IMUX17_11", - "CMT_FIFO_L_IMUX17_2", - "CMT_FIFO_L_IMUX17_3", - "CMT_FIFO_L_IMUX17_4", - "CMT_FIFO_L_IMUX17_5", - "CMT_FIFO_L_IMUX17_6", - "CMT_FIFO_L_IMUX17_7", - "CMT_FIFO_L_IMUX17_8", - "CMT_FIFO_L_IMUX17_9", - "CMT_FIFO_L_IMUX18_0", - "CMT_FIFO_L_IMUX18_1", - "CMT_FIFO_L_IMUX18_10", - "CMT_FIFO_L_IMUX18_11", - "CMT_FIFO_L_IMUX18_2", - "CMT_FIFO_L_IMUX18_3", - "CMT_FIFO_L_IMUX18_4", - "CMT_FIFO_L_IMUX18_5", - "CMT_FIFO_L_IMUX18_6", - "CMT_FIFO_L_IMUX18_7", - "CMT_FIFO_L_IMUX18_8", - "CMT_FIFO_L_IMUX18_9", - "CMT_FIFO_L_IMUX19_0", - "CMT_FIFO_L_IMUX19_1", - "CMT_FIFO_L_IMUX19_10", - "CMT_FIFO_L_IMUX19_11", - "CMT_FIFO_L_IMUX19_2", - "CMT_FIFO_L_IMUX19_3", - "CMT_FIFO_L_IMUX19_4", - "CMT_FIFO_L_IMUX19_5", - "CMT_FIFO_L_IMUX19_6", - "CMT_FIFO_L_IMUX19_7", - "CMT_FIFO_L_IMUX19_8", - "CMT_FIFO_L_IMUX19_9", - "CMT_FIFO_L_IMUX1_0", - "CMT_FIFO_L_IMUX1_1", - "CMT_FIFO_L_IMUX1_10", - "CMT_FIFO_L_IMUX1_11", - "CMT_FIFO_L_IMUX1_2", - "CMT_FIFO_L_IMUX1_3", - "CMT_FIFO_L_IMUX1_4", - "CMT_FIFO_L_IMUX1_5", - "CMT_FIFO_L_IMUX1_6", - "CMT_FIFO_L_IMUX1_7", - "CMT_FIFO_L_IMUX1_8", - "CMT_FIFO_L_IMUX1_9", - "CMT_FIFO_L_IMUX20_0", - "CMT_FIFO_L_IMUX20_1", - "CMT_FIFO_L_IMUX20_10", - "CMT_FIFO_L_IMUX20_11", - "CMT_FIFO_L_IMUX20_2", - "CMT_FIFO_L_IMUX20_3", - "CMT_FIFO_L_IMUX20_4", - "CMT_FIFO_L_IMUX20_5", - "CMT_FIFO_L_IMUX20_6", - "CMT_FIFO_L_IMUX20_7", - "CMT_FIFO_L_IMUX20_8", - "CMT_FIFO_L_IMUX20_9", - "CMT_FIFO_L_IMUX21_0", - "CMT_FIFO_L_IMUX21_1", - "CMT_FIFO_L_IMUX21_10", - "CMT_FIFO_L_IMUX21_11", - "CMT_FIFO_L_IMUX21_2", - "CMT_FIFO_L_IMUX21_3", - "CMT_FIFO_L_IMUX21_4", - "CMT_FIFO_L_IMUX21_5", - "CMT_FIFO_L_IMUX21_6", - "CMT_FIFO_L_IMUX21_7", - "CMT_FIFO_L_IMUX21_8", - "CMT_FIFO_L_IMUX21_9", - "CMT_FIFO_L_IMUX22_0", - "CMT_FIFO_L_IMUX22_1", - "CMT_FIFO_L_IMUX22_10", - "CMT_FIFO_L_IMUX22_11", - "CMT_FIFO_L_IMUX22_2", - "CMT_FIFO_L_IMUX22_3", - "CMT_FIFO_L_IMUX22_4", - "CMT_FIFO_L_IMUX22_5", - "CMT_FIFO_L_IMUX22_6", - "CMT_FIFO_L_IMUX22_7", - "CMT_FIFO_L_IMUX22_8", - "CMT_FIFO_L_IMUX22_9", - "CMT_FIFO_L_IMUX23_0", - "CMT_FIFO_L_IMUX23_1", - "CMT_FIFO_L_IMUX23_10", - "CMT_FIFO_L_IMUX23_11", - "CMT_FIFO_L_IMUX23_2", - "CMT_FIFO_L_IMUX23_3", - "CMT_FIFO_L_IMUX23_4", - "CMT_FIFO_L_IMUX23_5", - "CMT_FIFO_L_IMUX23_6", - "CMT_FIFO_L_IMUX23_7", - "CMT_FIFO_L_IMUX23_8", - "CMT_FIFO_L_IMUX23_9", - "CMT_FIFO_L_IMUX24_0", - "CMT_FIFO_L_IMUX24_1", - "CMT_FIFO_L_IMUX24_10", - "CMT_FIFO_L_IMUX24_11", - "CMT_FIFO_L_IMUX24_2", - "CMT_FIFO_L_IMUX24_3", - "CMT_FIFO_L_IMUX24_4", - "CMT_FIFO_L_IMUX24_5", - "CMT_FIFO_L_IMUX24_6", - "CMT_FIFO_L_IMUX24_7", - "CMT_FIFO_L_IMUX24_8", - "CMT_FIFO_L_IMUX24_9", - "CMT_FIFO_L_IMUX25_0", - "CMT_FIFO_L_IMUX25_1", - "CMT_FIFO_L_IMUX25_10", - "CMT_FIFO_L_IMUX25_11", - "CMT_FIFO_L_IMUX25_2", - "CMT_FIFO_L_IMUX25_3", - "CMT_FIFO_L_IMUX25_4", - "CMT_FIFO_L_IMUX25_5", - "CMT_FIFO_L_IMUX25_6", - "CMT_FIFO_L_IMUX25_7", - "CMT_FIFO_L_IMUX25_8", - "CMT_FIFO_L_IMUX25_9", - "CMT_FIFO_L_IMUX26_0", - "CMT_FIFO_L_IMUX26_1", - "CMT_FIFO_L_IMUX26_10", - "CMT_FIFO_L_IMUX26_11", - "CMT_FIFO_L_IMUX26_2", - "CMT_FIFO_L_IMUX26_3", - "CMT_FIFO_L_IMUX26_4", - "CMT_FIFO_L_IMUX26_5", - "CMT_FIFO_L_IMUX26_6", - "CMT_FIFO_L_IMUX26_7", - "CMT_FIFO_L_IMUX26_8", - "CMT_FIFO_L_IMUX26_9", - "CMT_FIFO_L_IMUX27_0", - "CMT_FIFO_L_IMUX27_1", - "CMT_FIFO_L_IMUX27_10", - "CMT_FIFO_L_IMUX27_11", - "CMT_FIFO_L_IMUX27_2", - "CMT_FIFO_L_IMUX27_3", - "CMT_FIFO_L_IMUX27_4", - "CMT_FIFO_L_IMUX27_5", - "CMT_FIFO_L_IMUX27_6", - "CMT_FIFO_L_IMUX27_7", - "CMT_FIFO_L_IMUX27_8", - "CMT_FIFO_L_IMUX27_9", - "CMT_FIFO_L_IMUX28_0", - "CMT_FIFO_L_IMUX28_1", - "CMT_FIFO_L_IMUX28_10", - "CMT_FIFO_L_IMUX28_11", - "CMT_FIFO_L_IMUX28_2", - "CMT_FIFO_L_IMUX28_3", - "CMT_FIFO_L_IMUX28_4", - "CMT_FIFO_L_IMUX28_5", - "CMT_FIFO_L_IMUX28_6", - "CMT_FIFO_L_IMUX28_7", - "CMT_FIFO_L_IMUX28_8", - "CMT_FIFO_L_IMUX28_9", - "CMT_FIFO_L_IMUX29_0", - "CMT_FIFO_L_IMUX29_1", - "CMT_FIFO_L_IMUX29_10", - "CMT_FIFO_L_IMUX29_11", - "CMT_FIFO_L_IMUX29_2", - "CMT_FIFO_L_IMUX29_3", - "CMT_FIFO_L_IMUX29_4", - "CMT_FIFO_L_IMUX29_5", - "CMT_FIFO_L_IMUX29_6", - "CMT_FIFO_L_IMUX29_7", - "CMT_FIFO_L_IMUX29_8", - "CMT_FIFO_L_IMUX29_9", - "CMT_FIFO_L_IMUX2_0", - "CMT_FIFO_L_IMUX2_1", - "CMT_FIFO_L_IMUX2_10", - "CMT_FIFO_L_IMUX2_11", - "CMT_FIFO_L_IMUX2_2", - "CMT_FIFO_L_IMUX2_3", - "CMT_FIFO_L_IMUX2_4", - "CMT_FIFO_L_IMUX2_5", - "CMT_FIFO_L_IMUX2_6", - "CMT_FIFO_L_IMUX2_7", - "CMT_FIFO_L_IMUX2_8", - "CMT_FIFO_L_IMUX2_9", - "CMT_FIFO_L_IMUX30_0", - "CMT_FIFO_L_IMUX30_1", - "CMT_FIFO_L_IMUX30_10", - "CMT_FIFO_L_IMUX30_11", - "CMT_FIFO_L_IMUX30_2", - "CMT_FIFO_L_IMUX30_3", - "CMT_FIFO_L_IMUX30_4", - "CMT_FIFO_L_IMUX30_5", - "CMT_FIFO_L_IMUX30_6", - "CMT_FIFO_L_IMUX30_7", - "CMT_FIFO_L_IMUX30_8", - "CMT_FIFO_L_IMUX30_9", - "CMT_FIFO_L_IMUX31_0", - "CMT_FIFO_L_IMUX31_1", - "CMT_FIFO_L_IMUX31_10", - "CMT_FIFO_L_IMUX31_11", - "CMT_FIFO_L_IMUX31_2", - "CMT_FIFO_L_IMUX31_3", - "CMT_FIFO_L_IMUX31_4", - "CMT_FIFO_L_IMUX31_5", - "CMT_FIFO_L_IMUX31_6", - "CMT_FIFO_L_IMUX31_7", - "CMT_FIFO_L_IMUX31_8", - "CMT_FIFO_L_IMUX31_9", - "CMT_FIFO_L_IMUX32_0", - "CMT_FIFO_L_IMUX32_1", - "CMT_FIFO_L_IMUX32_10", - "CMT_FIFO_L_IMUX32_11", - "CMT_FIFO_L_IMUX32_2", - "CMT_FIFO_L_IMUX32_3", - "CMT_FIFO_L_IMUX32_4", - "CMT_FIFO_L_IMUX32_5", - "CMT_FIFO_L_IMUX32_6", - "CMT_FIFO_L_IMUX32_7", - "CMT_FIFO_L_IMUX32_8", - "CMT_FIFO_L_IMUX32_9", - "CMT_FIFO_L_IMUX33_0", - "CMT_FIFO_L_IMUX33_1", - "CMT_FIFO_L_IMUX33_10", - "CMT_FIFO_L_IMUX33_11", - "CMT_FIFO_L_IMUX33_2", - "CMT_FIFO_L_IMUX33_3", - "CMT_FIFO_L_IMUX33_4", - "CMT_FIFO_L_IMUX33_5", - "CMT_FIFO_L_IMUX33_6", - "CMT_FIFO_L_IMUX33_7", - "CMT_FIFO_L_IMUX33_8", - "CMT_FIFO_L_IMUX33_9", - "CMT_FIFO_L_IMUX34_0", - "CMT_FIFO_L_IMUX34_1", - "CMT_FIFO_L_IMUX34_10", - "CMT_FIFO_L_IMUX34_11", - "CMT_FIFO_L_IMUX34_2", - "CMT_FIFO_L_IMUX34_3", - "CMT_FIFO_L_IMUX34_4", - "CMT_FIFO_L_IMUX34_5", - "CMT_FIFO_L_IMUX34_6", - "CMT_FIFO_L_IMUX34_7", - "CMT_FIFO_L_IMUX34_8", - "CMT_FIFO_L_IMUX34_9", - "CMT_FIFO_L_IMUX35_0", - "CMT_FIFO_L_IMUX35_1", - "CMT_FIFO_L_IMUX35_10", - "CMT_FIFO_L_IMUX35_11", - "CMT_FIFO_L_IMUX35_2", - "CMT_FIFO_L_IMUX35_3", - "CMT_FIFO_L_IMUX35_4", - "CMT_FIFO_L_IMUX35_5", - "CMT_FIFO_L_IMUX35_6", - "CMT_FIFO_L_IMUX35_7", - "CMT_FIFO_L_IMUX35_8", - "CMT_FIFO_L_IMUX35_9", - "CMT_FIFO_L_IMUX36_0", - "CMT_FIFO_L_IMUX36_1", - "CMT_FIFO_L_IMUX36_10", - "CMT_FIFO_L_IMUX36_11", - "CMT_FIFO_L_IMUX36_2", - "CMT_FIFO_L_IMUX36_3", - "CMT_FIFO_L_IMUX36_4", - "CMT_FIFO_L_IMUX36_5", - "CMT_FIFO_L_IMUX36_6", - "CMT_FIFO_L_IMUX36_7", - "CMT_FIFO_L_IMUX36_8", - "CMT_FIFO_L_IMUX36_9", - "CMT_FIFO_L_IMUX37_0", - "CMT_FIFO_L_IMUX37_1", - "CMT_FIFO_L_IMUX37_10", - "CMT_FIFO_L_IMUX37_11", - "CMT_FIFO_L_IMUX37_2", - "CMT_FIFO_L_IMUX37_3", - "CMT_FIFO_L_IMUX37_4", - "CMT_FIFO_L_IMUX37_5", - "CMT_FIFO_L_IMUX37_6", - "CMT_FIFO_L_IMUX37_7", - "CMT_FIFO_L_IMUX37_8", - "CMT_FIFO_L_IMUX37_9", - "CMT_FIFO_L_IMUX38_0", - "CMT_FIFO_L_IMUX38_1", - "CMT_FIFO_L_IMUX38_10", - "CMT_FIFO_L_IMUX38_11", - "CMT_FIFO_L_IMUX38_2", - "CMT_FIFO_L_IMUX38_3", - "CMT_FIFO_L_IMUX38_4", - "CMT_FIFO_L_IMUX38_5", - "CMT_FIFO_L_IMUX38_6", - "CMT_FIFO_L_IMUX38_7", - "CMT_FIFO_L_IMUX38_8", - "CMT_FIFO_L_IMUX38_9", - "CMT_FIFO_L_IMUX39_0", - "CMT_FIFO_L_IMUX39_1", - "CMT_FIFO_L_IMUX39_10", - "CMT_FIFO_L_IMUX39_11", - "CMT_FIFO_L_IMUX39_2", - "CMT_FIFO_L_IMUX39_3", - "CMT_FIFO_L_IMUX39_4", - "CMT_FIFO_L_IMUX39_5", - "CMT_FIFO_L_IMUX39_6", - "CMT_FIFO_L_IMUX39_7", - "CMT_FIFO_L_IMUX39_8", - "CMT_FIFO_L_IMUX39_9", - "CMT_FIFO_L_IMUX3_0", - "CMT_FIFO_L_IMUX3_1", - "CMT_FIFO_L_IMUX3_10", - "CMT_FIFO_L_IMUX3_11", - "CMT_FIFO_L_IMUX3_2", - "CMT_FIFO_L_IMUX3_3", - "CMT_FIFO_L_IMUX3_4", - "CMT_FIFO_L_IMUX3_5", - "CMT_FIFO_L_IMUX3_6", - "CMT_FIFO_L_IMUX3_7", - "CMT_FIFO_L_IMUX3_8", - "CMT_FIFO_L_IMUX3_9", - "CMT_FIFO_L_IMUX40_0", - "CMT_FIFO_L_IMUX40_1", - "CMT_FIFO_L_IMUX40_10", - "CMT_FIFO_L_IMUX40_11", - "CMT_FIFO_L_IMUX40_2", - "CMT_FIFO_L_IMUX40_3", - "CMT_FIFO_L_IMUX40_4", - "CMT_FIFO_L_IMUX40_5", - "CMT_FIFO_L_IMUX40_6", - "CMT_FIFO_L_IMUX40_7", - "CMT_FIFO_L_IMUX40_8", - "CMT_FIFO_L_IMUX40_9", - "CMT_FIFO_L_IMUX41_0", - "CMT_FIFO_L_IMUX41_1", - "CMT_FIFO_L_IMUX41_10", - "CMT_FIFO_L_IMUX41_11", - "CMT_FIFO_L_IMUX41_2", - "CMT_FIFO_L_IMUX41_3", - "CMT_FIFO_L_IMUX41_4", - "CMT_FIFO_L_IMUX41_5", - "CMT_FIFO_L_IMUX41_6", - "CMT_FIFO_L_IMUX41_7", - "CMT_FIFO_L_IMUX41_8", - "CMT_FIFO_L_IMUX41_9", - "CMT_FIFO_L_IMUX42_0", - "CMT_FIFO_L_IMUX42_1", - "CMT_FIFO_L_IMUX42_10", - "CMT_FIFO_L_IMUX42_11", - "CMT_FIFO_L_IMUX42_2", - "CMT_FIFO_L_IMUX42_3", - "CMT_FIFO_L_IMUX42_4", - "CMT_FIFO_L_IMUX42_5", - "CMT_FIFO_L_IMUX42_6", - "CMT_FIFO_L_IMUX42_7", - "CMT_FIFO_L_IMUX42_8", - "CMT_FIFO_L_IMUX42_9", - "CMT_FIFO_L_IMUX43_0", - "CMT_FIFO_L_IMUX43_1", - "CMT_FIFO_L_IMUX43_10", - "CMT_FIFO_L_IMUX43_11", - "CMT_FIFO_L_IMUX43_2", - "CMT_FIFO_L_IMUX43_3", - "CMT_FIFO_L_IMUX43_4", - "CMT_FIFO_L_IMUX43_5", - "CMT_FIFO_L_IMUX43_6", - "CMT_FIFO_L_IMUX43_7", - "CMT_FIFO_L_IMUX43_8", - "CMT_FIFO_L_IMUX43_9", - "CMT_FIFO_L_IMUX44_0", - "CMT_FIFO_L_IMUX44_1", - "CMT_FIFO_L_IMUX44_10", - "CMT_FIFO_L_IMUX44_11", - "CMT_FIFO_L_IMUX44_2", - "CMT_FIFO_L_IMUX44_3", - "CMT_FIFO_L_IMUX44_4", - "CMT_FIFO_L_IMUX44_5", - "CMT_FIFO_L_IMUX44_6", - "CMT_FIFO_L_IMUX44_7", - "CMT_FIFO_L_IMUX44_8", - "CMT_FIFO_L_IMUX44_9", - "CMT_FIFO_L_IMUX45_0", - "CMT_FIFO_L_IMUX45_1", - "CMT_FIFO_L_IMUX45_10", - "CMT_FIFO_L_IMUX45_11", - "CMT_FIFO_L_IMUX45_2", - "CMT_FIFO_L_IMUX45_3", - "CMT_FIFO_L_IMUX45_4", - "CMT_FIFO_L_IMUX45_5", - "CMT_FIFO_L_IMUX45_6", - "CMT_FIFO_L_IMUX45_7", - "CMT_FIFO_L_IMUX45_8", - "CMT_FIFO_L_IMUX45_9", - "CMT_FIFO_L_IMUX46_0", - "CMT_FIFO_L_IMUX46_1", - "CMT_FIFO_L_IMUX46_10", - "CMT_FIFO_L_IMUX46_11", - "CMT_FIFO_L_IMUX46_2", - "CMT_FIFO_L_IMUX46_3", - "CMT_FIFO_L_IMUX46_4", - "CMT_FIFO_L_IMUX46_5", - "CMT_FIFO_L_IMUX46_6", - "CMT_FIFO_L_IMUX46_7", - "CMT_FIFO_L_IMUX46_8", - "CMT_FIFO_L_IMUX46_9", - "CMT_FIFO_L_IMUX47_0", - "CMT_FIFO_L_IMUX47_1", - "CMT_FIFO_L_IMUX47_10", - "CMT_FIFO_L_IMUX47_11", - "CMT_FIFO_L_IMUX47_2", - "CMT_FIFO_L_IMUX47_3", - "CMT_FIFO_L_IMUX47_4", - "CMT_FIFO_L_IMUX47_5", - "CMT_FIFO_L_IMUX47_6", - "CMT_FIFO_L_IMUX47_7", - "CMT_FIFO_L_IMUX47_8", - "CMT_FIFO_L_IMUX47_9", - "CMT_FIFO_L_IMUX4_0", - "CMT_FIFO_L_IMUX4_1", - "CMT_FIFO_L_IMUX4_10", - "CMT_FIFO_L_IMUX4_11", - "CMT_FIFO_L_IMUX4_2", - "CMT_FIFO_L_IMUX4_3", - "CMT_FIFO_L_IMUX4_4", - "CMT_FIFO_L_IMUX4_5", - "CMT_FIFO_L_IMUX4_6", - "CMT_FIFO_L_IMUX4_7", - "CMT_FIFO_L_IMUX4_8", - "CMT_FIFO_L_IMUX4_9", - "CMT_FIFO_L_IMUX5_0", - "CMT_FIFO_L_IMUX5_1", - "CMT_FIFO_L_IMUX5_10", - "CMT_FIFO_L_IMUX5_11", - "CMT_FIFO_L_IMUX5_2", - "CMT_FIFO_L_IMUX5_3", - "CMT_FIFO_L_IMUX5_4", - "CMT_FIFO_L_IMUX5_5", - "CMT_FIFO_L_IMUX5_6", - "CMT_FIFO_L_IMUX5_7", - "CMT_FIFO_L_IMUX5_8", - "CMT_FIFO_L_IMUX5_9", - "CMT_FIFO_L_IMUX6_0", - "CMT_FIFO_L_IMUX6_1", - "CMT_FIFO_L_IMUX6_10", - "CMT_FIFO_L_IMUX6_11", - "CMT_FIFO_L_IMUX6_2", - "CMT_FIFO_L_IMUX6_3", - "CMT_FIFO_L_IMUX6_4", - "CMT_FIFO_L_IMUX6_5", - "CMT_FIFO_L_IMUX6_6", - "CMT_FIFO_L_IMUX6_7", - "CMT_FIFO_L_IMUX6_8", - "CMT_FIFO_L_IMUX6_9", - "CMT_FIFO_L_IMUX7_0", - "CMT_FIFO_L_IMUX7_1", - "CMT_FIFO_L_IMUX7_10", - "CMT_FIFO_L_IMUX7_11", - "CMT_FIFO_L_IMUX7_2", - "CMT_FIFO_L_IMUX7_3", - "CMT_FIFO_L_IMUX7_4", - "CMT_FIFO_L_IMUX7_5", - "CMT_FIFO_L_IMUX7_6", - "CMT_FIFO_L_IMUX7_7", - "CMT_FIFO_L_IMUX7_8", - "CMT_FIFO_L_IMUX7_9", - "CMT_FIFO_L_IMUX8_0", - "CMT_FIFO_L_IMUX8_1", - "CMT_FIFO_L_IMUX8_10", - "CMT_FIFO_L_IMUX8_11", - "CMT_FIFO_L_IMUX8_2", - "CMT_FIFO_L_IMUX8_3", - "CMT_FIFO_L_IMUX8_4", - "CMT_FIFO_L_IMUX8_5", - "CMT_FIFO_L_IMUX8_6", - "CMT_FIFO_L_IMUX8_7", - "CMT_FIFO_L_IMUX8_8", - "CMT_FIFO_L_IMUX8_9", - "CMT_FIFO_L_IMUX9_0", - "CMT_FIFO_L_IMUX9_1", - "CMT_FIFO_L_IMUX9_10", - "CMT_FIFO_L_IMUX9_11", - "CMT_FIFO_L_IMUX9_2", - "CMT_FIFO_L_IMUX9_3", - "CMT_FIFO_L_IMUX9_4", - "CMT_FIFO_L_IMUX9_5", - "CMT_FIFO_L_IMUX9_6", - "CMT_FIFO_L_IMUX9_7", - "CMT_FIFO_L_IMUX9_8", - "CMT_FIFO_L_IMUX9_9", - "CMT_FIFO_L_LOGIC_OUTS0_0", - "CMT_FIFO_L_LOGIC_OUTS0_1", - "CMT_FIFO_L_LOGIC_OUTS0_10", - "CMT_FIFO_L_LOGIC_OUTS0_11", - "CMT_FIFO_L_LOGIC_OUTS0_2", - "CMT_FIFO_L_LOGIC_OUTS0_3", - "CMT_FIFO_L_LOGIC_OUTS0_4", - "CMT_FIFO_L_LOGIC_OUTS0_5", - "CMT_FIFO_L_LOGIC_OUTS0_6", - "CMT_FIFO_L_LOGIC_OUTS0_7", - "CMT_FIFO_L_LOGIC_OUTS0_8", - "CMT_FIFO_L_LOGIC_OUTS0_9", - "CMT_FIFO_L_LOGIC_OUTS10_0", - "CMT_FIFO_L_LOGIC_OUTS10_1", - "CMT_FIFO_L_LOGIC_OUTS10_10", - "CMT_FIFO_L_LOGIC_OUTS10_11", - "CMT_FIFO_L_LOGIC_OUTS10_2", - "CMT_FIFO_L_LOGIC_OUTS10_3", - "CMT_FIFO_L_LOGIC_OUTS10_4", - "CMT_FIFO_L_LOGIC_OUTS10_5", - "CMT_FIFO_L_LOGIC_OUTS10_6", - "CMT_FIFO_L_LOGIC_OUTS10_7", - "CMT_FIFO_L_LOGIC_OUTS10_8", - "CMT_FIFO_L_LOGIC_OUTS10_9", - "CMT_FIFO_L_LOGIC_OUTS11_0", - "CMT_FIFO_L_LOGIC_OUTS11_1", - "CMT_FIFO_L_LOGIC_OUTS11_10", - "CMT_FIFO_L_LOGIC_OUTS11_11", - "CMT_FIFO_L_LOGIC_OUTS11_2", - "CMT_FIFO_L_LOGIC_OUTS11_3", - "CMT_FIFO_L_LOGIC_OUTS11_4", - "CMT_FIFO_L_LOGIC_OUTS11_5", - "CMT_FIFO_L_LOGIC_OUTS11_6", - "CMT_FIFO_L_LOGIC_OUTS11_7", - "CMT_FIFO_L_LOGIC_OUTS11_8", - "CMT_FIFO_L_LOGIC_OUTS11_9", - "CMT_FIFO_L_LOGIC_OUTS12_0", - "CMT_FIFO_L_LOGIC_OUTS12_1", - "CMT_FIFO_L_LOGIC_OUTS12_10", - "CMT_FIFO_L_LOGIC_OUTS12_11", - "CMT_FIFO_L_LOGIC_OUTS12_2", - "CMT_FIFO_L_LOGIC_OUTS12_3", - "CMT_FIFO_L_LOGIC_OUTS12_4", - "CMT_FIFO_L_LOGIC_OUTS12_5", - "CMT_FIFO_L_LOGIC_OUTS12_6", - "CMT_FIFO_L_LOGIC_OUTS12_7", - "CMT_FIFO_L_LOGIC_OUTS12_8", - "CMT_FIFO_L_LOGIC_OUTS12_9", - "CMT_FIFO_L_LOGIC_OUTS13_0", - "CMT_FIFO_L_LOGIC_OUTS13_1", - "CMT_FIFO_L_LOGIC_OUTS13_10", - "CMT_FIFO_L_LOGIC_OUTS13_11", - "CMT_FIFO_L_LOGIC_OUTS13_2", - "CMT_FIFO_L_LOGIC_OUTS13_3", - "CMT_FIFO_L_LOGIC_OUTS13_4", - "CMT_FIFO_L_LOGIC_OUTS13_5", - "CMT_FIFO_L_LOGIC_OUTS13_6", - "CMT_FIFO_L_LOGIC_OUTS13_7", - "CMT_FIFO_L_LOGIC_OUTS13_8", - "CMT_FIFO_L_LOGIC_OUTS13_9", - "CMT_FIFO_L_LOGIC_OUTS14_0", - "CMT_FIFO_L_LOGIC_OUTS14_1", - "CMT_FIFO_L_LOGIC_OUTS14_10", - "CMT_FIFO_L_LOGIC_OUTS14_11", - "CMT_FIFO_L_LOGIC_OUTS14_2", - "CMT_FIFO_L_LOGIC_OUTS14_3", - "CMT_FIFO_L_LOGIC_OUTS14_4", - "CMT_FIFO_L_LOGIC_OUTS14_5", - "CMT_FIFO_L_LOGIC_OUTS14_6", - "CMT_FIFO_L_LOGIC_OUTS14_7", - "CMT_FIFO_L_LOGIC_OUTS14_8", - "CMT_FIFO_L_LOGIC_OUTS14_9", - "CMT_FIFO_L_LOGIC_OUTS15_0", - "CMT_FIFO_L_LOGIC_OUTS15_1", - "CMT_FIFO_L_LOGIC_OUTS15_10", - "CMT_FIFO_L_LOGIC_OUTS15_11", - "CMT_FIFO_L_LOGIC_OUTS15_2", - "CMT_FIFO_L_LOGIC_OUTS15_3", - "CMT_FIFO_L_LOGIC_OUTS15_4", - "CMT_FIFO_L_LOGIC_OUTS15_5", - "CMT_FIFO_L_LOGIC_OUTS15_6", - "CMT_FIFO_L_LOGIC_OUTS15_7", - "CMT_FIFO_L_LOGIC_OUTS15_8", - "CMT_FIFO_L_LOGIC_OUTS15_9", - "CMT_FIFO_L_LOGIC_OUTS16_0", - "CMT_FIFO_L_LOGIC_OUTS16_1", - "CMT_FIFO_L_LOGIC_OUTS16_10", - "CMT_FIFO_L_LOGIC_OUTS16_11", - "CMT_FIFO_L_LOGIC_OUTS16_2", - "CMT_FIFO_L_LOGIC_OUTS16_3", - "CMT_FIFO_L_LOGIC_OUTS16_4", - "CMT_FIFO_L_LOGIC_OUTS16_5", - "CMT_FIFO_L_LOGIC_OUTS16_6", - "CMT_FIFO_L_LOGIC_OUTS16_7", - "CMT_FIFO_L_LOGIC_OUTS16_8", - "CMT_FIFO_L_LOGIC_OUTS16_9", - "CMT_FIFO_L_LOGIC_OUTS17_0", - "CMT_FIFO_L_LOGIC_OUTS17_1", - "CMT_FIFO_L_LOGIC_OUTS17_10", - "CMT_FIFO_L_LOGIC_OUTS17_11", - "CMT_FIFO_L_LOGIC_OUTS17_2", - "CMT_FIFO_L_LOGIC_OUTS17_3", - "CMT_FIFO_L_LOGIC_OUTS17_4", - "CMT_FIFO_L_LOGIC_OUTS17_5", - "CMT_FIFO_L_LOGIC_OUTS17_6", - "CMT_FIFO_L_LOGIC_OUTS17_7", - "CMT_FIFO_L_LOGIC_OUTS17_8", - "CMT_FIFO_L_LOGIC_OUTS17_9", - "CMT_FIFO_L_LOGIC_OUTS18_0", - "CMT_FIFO_L_LOGIC_OUTS18_1", - "CMT_FIFO_L_LOGIC_OUTS18_10", - "CMT_FIFO_L_LOGIC_OUTS18_11", - "CMT_FIFO_L_LOGIC_OUTS18_2", - "CMT_FIFO_L_LOGIC_OUTS18_3", - "CMT_FIFO_L_LOGIC_OUTS18_4", - "CMT_FIFO_L_LOGIC_OUTS18_5", - "CMT_FIFO_L_LOGIC_OUTS18_6", - "CMT_FIFO_L_LOGIC_OUTS18_7", - "CMT_FIFO_L_LOGIC_OUTS18_8", - "CMT_FIFO_L_LOGIC_OUTS18_9", - "CMT_FIFO_L_LOGIC_OUTS19_0", - "CMT_FIFO_L_LOGIC_OUTS19_1", - "CMT_FIFO_L_LOGIC_OUTS19_10", - "CMT_FIFO_L_LOGIC_OUTS19_11", - "CMT_FIFO_L_LOGIC_OUTS19_2", - "CMT_FIFO_L_LOGIC_OUTS19_3", - "CMT_FIFO_L_LOGIC_OUTS19_4", - "CMT_FIFO_L_LOGIC_OUTS19_5", - "CMT_FIFO_L_LOGIC_OUTS19_6", - "CMT_FIFO_L_LOGIC_OUTS19_7", - "CMT_FIFO_L_LOGIC_OUTS19_8", - "CMT_FIFO_L_LOGIC_OUTS19_9", - "CMT_FIFO_L_LOGIC_OUTS1_0", - "CMT_FIFO_L_LOGIC_OUTS1_1", - "CMT_FIFO_L_LOGIC_OUTS1_10", - "CMT_FIFO_L_LOGIC_OUTS1_11", - "CMT_FIFO_L_LOGIC_OUTS1_2", - "CMT_FIFO_L_LOGIC_OUTS1_3", - "CMT_FIFO_L_LOGIC_OUTS1_4", - "CMT_FIFO_L_LOGIC_OUTS1_5", - "CMT_FIFO_L_LOGIC_OUTS1_6", - "CMT_FIFO_L_LOGIC_OUTS1_7", - "CMT_FIFO_L_LOGIC_OUTS1_8", - "CMT_FIFO_L_LOGIC_OUTS1_9", - "CMT_FIFO_L_LOGIC_OUTS20_0", - "CMT_FIFO_L_LOGIC_OUTS20_1", - "CMT_FIFO_L_LOGIC_OUTS20_10", - "CMT_FIFO_L_LOGIC_OUTS20_11", - "CMT_FIFO_L_LOGIC_OUTS20_2", - "CMT_FIFO_L_LOGIC_OUTS20_3", - "CMT_FIFO_L_LOGIC_OUTS20_4", - "CMT_FIFO_L_LOGIC_OUTS20_5", - "CMT_FIFO_L_LOGIC_OUTS20_6", - "CMT_FIFO_L_LOGIC_OUTS20_7", - "CMT_FIFO_L_LOGIC_OUTS20_8", - "CMT_FIFO_L_LOGIC_OUTS20_9", - "CMT_FIFO_L_LOGIC_OUTS21_0", - "CMT_FIFO_L_LOGIC_OUTS21_1", - "CMT_FIFO_L_LOGIC_OUTS21_10", - "CMT_FIFO_L_LOGIC_OUTS21_11", - "CMT_FIFO_L_LOGIC_OUTS21_2", - "CMT_FIFO_L_LOGIC_OUTS21_3", - "CMT_FIFO_L_LOGIC_OUTS21_4", - "CMT_FIFO_L_LOGIC_OUTS21_5", - "CMT_FIFO_L_LOGIC_OUTS21_6", - "CMT_FIFO_L_LOGIC_OUTS21_7", - "CMT_FIFO_L_LOGIC_OUTS21_8", - "CMT_FIFO_L_LOGIC_OUTS21_9", - "CMT_FIFO_L_LOGIC_OUTS22_0", - "CMT_FIFO_L_LOGIC_OUTS22_1", - "CMT_FIFO_L_LOGIC_OUTS22_10", - "CMT_FIFO_L_LOGIC_OUTS22_11", - "CMT_FIFO_L_LOGIC_OUTS22_2", - "CMT_FIFO_L_LOGIC_OUTS22_3", - "CMT_FIFO_L_LOGIC_OUTS22_4", - "CMT_FIFO_L_LOGIC_OUTS22_5", - "CMT_FIFO_L_LOGIC_OUTS22_6", - "CMT_FIFO_L_LOGIC_OUTS22_7", - "CMT_FIFO_L_LOGIC_OUTS22_8", - "CMT_FIFO_L_LOGIC_OUTS22_9", - "CMT_FIFO_L_LOGIC_OUTS23_0", - "CMT_FIFO_L_LOGIC_OUTS23_1", - "CMT_FIFO_L_LOGIC_OUTS23_10", - "CMT_FIFO_L_LOGIC_OUTS23_11", - "CMT_FIFO_L_LOGIC_OUTS23_2", - "CMT_FIFO_L_LOGIC_OUTS23_3", - "CMT_FIFO_L_LOGIC_OUTS23_4", - "CMT_FIFO_L_LOGIC_OUTS23_5", - "CMT_FIFO_L_LOGIC_OUTS23_6", - "CMT_FIFO_L_LOGIC_OUTS23_7", - "CMT_FIFO_L_LOGIC_OUTS23_8", - "CMT_FIFO_L_LOGIC_OUTS23_9", - "CMT_FIFO_L_LOGIC_OUTS2_0", - "CMT_FIFO_L_LOGIC_OUTS2_1", - "CMT_FIFO_L_LOGIC_OUTS2_10", - "CMT_FIFO_L_LOGIC_OUTS2_11", - "CMT_FIFO_L_LOGIC_OUTS2_2", - "CMT_FIFO_L_LOGIC_OUTS2_3", - "CMT_FIFO_L_LOGIC_OUTS2_4", - "CMT_FIFO_L_LOGIC_OUTS2_5", - "CMT_FIFO_L_LOGIC_OUTS2_6", - "CMT_FIFO_L_LOGIC_OUTS2_7", - "CMT_FIFO_L_LOGIC_OUTS2_8", - "CMT_FIFO_L_LOGIC_OUTS2_9", - "CMT_FIFO_L_LOGIC_OUTS3_0", - "CMT_FIFO_L_LOGIC_OUTS3_1", - "CMT_FIFO_L_LOGIC_OUTS3_10", - "CMT_FIFO_L_LOGIC_OUTS3_11", - "CMT_FIFO_L_LOGIC_OUTS3_2", - "CMT_FIFO_L_LOGIC_OUTS3_3", - "CMT_FIFO_L_LOGIC_OUTS3_4", - "CMT_FIFO_L_LOGIC_OUTS3_5", - "CMT_FIFO_L_LOGIC_OUTS3_6", - "CMT_FIFO_L_LOGIC_OUTS3_7", - "CMT_FIFO_L_LOGIC_OUTS3_8", - "CMT_FIFO_L_LOGIC_OUTS3_9", - "CMT_FIFO_L_LOGIC_OUTS4_0", - "CMT_FIFO_L_LOGIC_OUTS4_1", - "CMT_FIFO_L_LOGIC_OUTS4_10", - "CMT_FIFO_L_LOGIC_OUTS4_11", - "CMT_FIFO_L_LOGIC_OUTS4_2", - "CMT_FIFO_L_LOGIC_OUTS4_3", - "CMT_FIFO_L_LOGIC_OUTS4_4", - "CMT_FIFO_L_LOGIC_OUTS4_5", - "CMT_FIFO_L_LOGIC_OUTS4_6", - "CMT_FIFO_L_LOGIC_OUTS4_7", - "CMT_FIFO_L_LOGIC_OUTS4_8", - "CMT_FIFO_L_LOGIC_OUTS4_9", - "CMT_FIFO_L_LOGIC_OUTS5_0", - "CMT_FIFO_L_LOGIC_OUTS5_1", - "CMT_FIFO_L_LOGIC_OUTS5_10", - "CMT_FIFO_L_LOGIC_OUTS5_11", - "CMT_FIFO_L_LOGIC_OUTS5_2", - "CMT_FIFO_L_LOGIC_OUTS5_3", - "CMT_FIFO_L_LOGIC_OUTS5_4", - "CMT_FIFO_L_LOGIC_OUTS5_5", - "CMT_FIFO_L_LOGIC_OUTS5_6", - "CMT_FIFO_L_LOGIC_OUTS5_7", - "CMT_FIFO_L_LOGIC_OUTS5_8", - "CMT_FIFO_L_LOGIC_OUTS5_9", - "CMT_FIFO_L_LOGIC_OUTS6_0", - "CMT_FIFO_L_LOGIC_OUTS6_1", - "CMT_FIFO_L_LOGIC_OUTS6_10", - "CMT_FIFO_L_LOGIC_OUTS6_11", - "CMT_FIFO_L_LOGIC_OUTS6_2", - "CMT_FIFO_L_LOGIC_OUTS6_3", - "CMT_FIFO_L_LOGIC_OUTS6_4", - "CMT_FIFO_L_LOGIC_OUTS6_5", - "CMT_FIFO_L_LOGIC_OUTS6_6", - "CMT_FIFO_L_LOGIC_OUTS6_7", - "CMT_FIFO_L_LOGIC_OUTS6_8", - "CMT_FIFO_L_LOGIC_OUTS6_9", - "CMT_FIFO_L_LOGIC_OUTS7_0", - "CMT_FIFO_L_LOGIC_OUTS7_1", - "CMT_FIFO_L_LOGIC_OUTS7_10", - "CMT_FIFO_L_LOGIC_OUTS7_11", - "CMT_FIFO_L_LOGIC_OUTS7_2", - "CMT_FIFO_L_LOGIC_OUTS7_3", - "CMT_FIFO_L_LOGIC_OUTS7_4", - "CMT_FIFO_L_LOGIC_OUTS7_5", - "CMT_FIFO_L_LOGIC_OUTS7_6", - "CMT_FIFO_L_LOGIC_OUTS7_7", - "CMT_FIFO_L_LOGIC_OUTS7_8", - "CMT_FIFO_L_LOGIC_OUTS7_9", - "CMT_FIFO_L_LOGIC_OUTS8_0", - "CMT_FIFO_L_LOGIC_OUTS8_1", - "CMT_FIFO_L_LOGIC_OUTS8_10", - "CMT_FIFO_L_LOGIC_OUTS8_11", - "CMT_FIFO_L_LOGIC_OUTS8_2", - "CMT_FIFO_L_LOGIC_OUTS8_3", - "CMT_FIFO_L_LOGIC_OUTS8_4", - "CMT_FIFO_L_LOGIC_OUTS8_5", - "CMT_FIFO_L_LOGIC_OUTS8_6", - "CMT_FIFO_L_LOGIC_OUTS8_7", - "CMT_FIFO_L_LOGIC_OUTS8_8", - "CMT_FIFO_L_LOGIC_OUTS8_9", - "CMT_FIFO_L_LOGIC_OUTS9_0", - "CMT_FIFO_L_LOGIC_OUTS9_1", - "CMT_FIFO_L_LOGIC_OUTS9_10", - "CMT_FIFO_L_LOGIC_OUTS9_11", - "CMT_FIFO_L_LOGIC_OUTS9_2", - "CMT_FIFO_L_LOGIC_OUTS9_3", - "CMT_FIFO_L_LOGIC_OUTS9_4", - "CMT_FIFO_L_LOGIC_OUTS9_5", - "CMT_FIFO_L_LOGIC_OUTS9_6", - "CMT_FIFO_L_LOGIC_OUTS9_7", - "CMT_FIFO_L_LOGIC_OUTS9_8", - "CMT_FIFO_L_LOGIC_OUTS9_9", - "CMT_FIFO_L_PHASER_RDCLK", - "CMT_FIFO_L_PHASER_RDENABLE", - "CMT_FIFO_L_PHASER_WRCLK", - "CMT_FIFO_L_PHASER_WRENABLE", - "CMT_FIFO_MONITOR_N_0", - "CMT_FIFO_MONITOR_N_1", - "CMT_FIFO_MONITOR_N_10", - "CMT_FIFO_MONITOR_N_11", - "CMT_FIFO_MONITOR_N_2", - "CMT_FIFO_MONITOR_N_3", - "CMT_FIFO_MONITOR_N_4", - "CMT_FIFO_MONITOR_N_5", - "CMT_FIFO_MONITOR_N_6", - "CMT_FIFO_MONITOR_N_7", - "CMT_FIFO_MONITOR_N_8", - "CMT_FIFO_MONITOR_N_9", - "CMT_FIFO_MONITOR_P_0", - "CMT_FIFO_MONITOR_P_1", - "CMT_FIFO_MONITOR_P_10", - "CMT_FIFO_MONITOR_P_11", - "CMT_FIFO_MONITOR_P_2", - "CMT_FIFO_MONITOR_P_3", - "CMT_FIFO_MONITOR_P_4", - "CMT_FIFO_MONITOR_P_5", - "CMT_FIFO_MONITOR_P_6", - "CMT_FIFO_MONITOR_P_7", - "CMT_FIFO_MONITOR_P_8", - "CMT_FIFO_MONITOR_P_9", - "CMT_FIFO_NE2A0_0", - "CMT_FIFO_NE2A0_1", - "CMT_FIFO_NE2A0_10", - "CMT_FIFO_NE2A0_11", - "CMT_FIFO_NE2A0_2", - "CMT_FIFO_NE2A0_3", - "CMT_FIFO_NE2A0_4", - "CMT_FIFO_NE2A0_5", - "CMT_FIFO_NE2A0_6", - "CMT_FIFO_NE2A0_7", - "CMT_FIFO_NE2A0_8", - "CMT_FIFO_NE2A0_9", - "CMT_FIFO_NE2A1_0", - "CMT_FIFO_NE2A1_1", - "CMT_FIFO_NE2A1_10", - "CMT_FIFO_NE2A1_11", - "CMT_FIFO_NE2A1_2", - "CMT_FIFO_NE2A1_3", - "CMT_FIFO_NE2A1_4", - "CMT_FIFO_NE2A1_5", - "CMT_FIFO_NE2A1_6", - "CMT_FIFO_NE2A1_7", - "CMT_FIFO_NE2A1_8", - "CMT_FIFO_NE2A1_9", - "CMT_FIFO_NE2A2_0", - "CMT_FIFO_NE2A2_1", - "CMT_FIFO_NE2A2_10", - "CMT_FIFO_NE2A2_11", - "CMT_FIFO_NE2A2_2", - "CMT_FIFO_NE2A2_3", - "CMT_FIFO_NE2A2_4", - "CMT_FIFO_NE2A2_5", - "CMT_FIFO_NE2A2_6", - "CMT_FIFO_NE2A2_7", - "CMT_FIFO_NE2A2_8", - "CMT_FIFO_NE2A2_9", - "CMT_FIFO_NE2A3_0", - "CMT_FIFO_NE2A3_1", - "CMT_FIFO_NE2A3_10", - "CMT_FIFO_NE2A3_11", - "CMT_FIFO_NE2A3_2", - "CMT_FIFO_NE2A3_3", - "CMT_FIFO_NE2A3_4", - "CMT_FIFO_NE2A3_5", - "CMT_FIFO_NE2A3_6", - "CMT_FIFO_NE2A3_7", - "CMT_FIFO_NE2A3_8", - "CMT_FIFO_NE2A3_9", - "CMT_FIFO_NE4BEG0_0", - "CMT_FIFO_NE4BEG0_1", - "CMT_FIFO_NE4BEG0_10", - "CMT_FIFO_NE4BEG0_11", - "CMT_FIFO_NE4BEG0_2", - "CMT_FIFO_NE4BEG0_3", - "CMT_FIFO_NE4BEG0_4", - "CMT_FIFO_NE4BEG0_5", - "CMT_FIFO_NE4BEG0_6", - "CMT_FIFO_NE4BEG0_7", - "CMT_FIFO_NE4BEG0_8", - "CMT_FIFO_NE4BEG0_9", - "CMT_FIFO_NE4BEG1_0", - "CMT_FIFO_NE4BEG1_1", - "CMT_FIFO_NE4BEG1_10", - "CMT_FIFO_NE4BEG1_11", - "CMT_FIFO_NE4BEG1_2", - "CMT_FIFO_NE4BEG1_3", - "CMT_FIFO_NE4BEG1_4", - "CMT_FIFO_NE4BEG1_5", - "CMT_FIFO_NE4BEG1_6", - "CMT_FIFO_NE4BEG1_7", - "CMT_FIFO_NE4BEG1_8", - "CMT_FIFO_NE4BEG1_9", - "CMT_FIFO_NE4BEG2_0", - "CMT_FIFO_NE4BEG2_1", - "CMT_FIFO_NE4BEG2_10", - "CMT_FIFO_NE4BEG2_11", - "CMT_FIFO_NE4BEG2_2", - "CMT_FIFO_NE4BEG2_3", - "CMT_FIFO_NE4BEG2_4", - "CMT_FIFO_NE4BEG2_5", - "CMT_FIFO_NE4BEG2_6", - "CMT_FIFO_NE4BEG2_7", - "CMT_FIFO_NE4BEG2_8", - "CMT_FIFO_NE4BEG2_9", - "CMT_FIFO_NE4BEG3_0", - "CMT_FIFO_NE4BEG3_1", - "CMT_FIFO_NE4BEG3_10", - "CMT_FIFO_NE4BEG3_11", - "CMT_FIFO_NE4BEG3_2", - "CMT_FIFO_NE4BEG3_3", - "CMT_FIFO_NE4BEG3_4", - "CMT_FIFO_NE4BEG3_5", - "CMT_FIFO_NE4BEG3_6", - "CMT_FIFO_NE4BEG3_7", - "CMT_FIFO_NE4BEG3_8", - "CMT_FIFO_NE4BEG3_9", - "CMT_FIFO_NE4C0_0", - "CMT_FIFO_NE4C0_1", - "CMT_FIFO_NE4C0_10", - "CMT_FIFO_NE4C0_11", - "CMT_FIFO_NE4C0_2", - "CMT_FIFO_NE4C0_3", - "CMT_FIFO_NE4C0_4", - "CMT_FIFO_NE4C0_5", - "CMT_FIFO_NE4C0_6", - "CMT_FIFO_NE4C0_7", - "CMT_FIFO_NE4C0_8", - "CMT_FIFO_NE4C0_9", - "CMT_FIFO_NE4C1_0", - "CMT_FIFO_NE4C1_1", - "CMT_FIFO_NE4C1_10", - "CMT_FIFO_NE4C1_11", - "CMT_FIFO_NE4C1_2", - "CMT_FIFO_NE4C1_3", - "CMT_FIFO_NE4C1_4", - "CMT_FIFO_NE4C1_5", - "CMT_FIFO_NE4C1_6", - "CMT_FIFO_NE4C1_7", - "CMT_FIFO_NE4C1_8", - "CMT_FIFO_NE4C1_9", - "CMT_FIFO_NE4C2_0", - "CMT_FIFO_NE4C2_1", - "CMT_FIFO_NE4C2_10", - "CMT_FIFO_NE4C2_11", - "CMT_FIFO_NE4C2_2", - "CMT_FIFO_NE4C2_3", - "CMT_FIFO_NE4C2_4", - "CMT_FIFO_NE4C2_5", - "CMT_FIFO_NE4C2_6", - "CMT_FIFO_NE4C2_7", - "CMT_FIFO_NE4C2_8", - "CMT_FIFO_NE4C2_9", - "CMT_FIFO_NE4C3_0", - "CMT_FIFO_NE4C3_1", - "CMT_FIFO_NE4C3_10", - "CMT_FIFO_NE4C3_11", - "CMT_FIFO_NE4C3_2", - "CMT_FIFO_NE4C3_3", - "CMT_FIFO_NE4C3_4", - "CMT_FIFO_NE4C3_5", - "CMT_FIFO_NE4C3_6", - "CMT_FIFO_NE4C3_7", - "CMT_FIFO_NE4C3_8", - "CMT_FIFO_NE4C3_9", - "CMT_FIFO_NW2A0_0", - "CMT_FIFO_NW2A0_1", - "CMT_FIFO_NW2A0_10", - "CMT_FIFO_NW2A0_11", - "CMT_FIFO_NW2A0_2", - "CMT_FIFO_NW2A0_3", - "CMT_FIFO_NW2A0_4", - "CMT_FIFO_NW2A0_5", - "CMT_FIFO_NW2A0_6", - "CMT_FIFO_NW2A0_7", - "CMT_FIFO_NW2A0_8", - "CMT_FIFO_NW2A0_9", - "CMT_FIFO_NW2A1_0", - "CMT_FIFO_NW2A1_1", - "CMT_FIFO_NW2A1_10", - "CMT_FIFO_NW2A1_11", - "CMT_FIFO_NW2A1_2", - "CMT_FIFO_NW2A1_3", - "CMT_FIFO_NW2A1_4", - "CMT_FIFO_NW2A1_5", - "CMT_FIFO_NW2A1_6", - "CMT_FIFO_NW2A1_7", - "CMT_FIFO_NW2A1_8", - "CMT_FIFO_NW2A1_9", - "CMT_FIFO_NW2A2_0", - "CMT_FIFO_NW2A2_1", - "CMT_FIFO_NW2A2_10", - "CMT_FIFO_NW2A2_11", - "CMT_FIFO_NW2A2_2", - "CMT_FIFO_NW2A2_3", - "CMT_FIFO_NW2A2_4", - "CMT_FIFO_NW2A2_5", - "CMT_FIFO_NW2A2_6", - "CMT_FIFO_NW2A2_7", - "CMT_FIFO_NW2A2_8", - "CMT_FIFO_NW2A2_9", - "CMT_FIFO_NW2A3_0", - "CMT_FIFO_NW2A3_1", - "CMT_FIFO_NW2A3_10", - "CMT_FIFO_NW2A3_11", - "CMT_FIFO_NW2A3_2", - "CMT_FIFO_NW2A3_3", - "CMT_FIFO_NW2A3_4", - "CMT_FIFO_NW2A3_5", - "CMT_FIFO_NW2A3_6", - "CMT_FIFO_NW2A3_7", - "CMT_FIFO_NW2A3_8", - "CMT_FIFO_NW2A3_9", - "CMT_FIFO_NW4A0_0", - "CMT_FIFO_NW4A0_1", - "CMT_FIFO_NW4A0_10", - "CMT_FIFO_NW4A0_11", - "CMT_FIFO_NW4A0_2", - "CMT_FIFO_NW4A0_3", - "CMT_FIFO_NW4A0_4", - "CMT_FIFO_NW4A0_5", - "CMT_FIFO_NW4A0_6", - "CMT_FIFO_NW4A0_7", - "CMT_FIFO_NW4A0_8", - "CMT_FIFO_NW4A0_9", - "CMT_FIFO_NW4A1_0", - "CMT_FIFO_NW4A1_1", - "CMT_FIFO_NW4A1_10", - "CMT_FIFO_NW4A1_11", - "CMT_FIFO_NW4A1_2", - "CMT_FIFO_NW4A1_3", - "CMT_FIFO_NW4A1_4", - "CMT_FIFO_NW4A1_5", - "CMT_FIFO_NW4A1_6", - "CMT_FIFO_NW4A1_7", - "CMT_FIFO_NW4A1_8", - "CMT_FIFO_NW4A1_9", - "CMT_FIFO_NW4A2_0", - "CMT_FIFO_NW4A2_1", - "CMT_FIFO_NW4A2_10", - "CMT_FIFO_NW4A2_11", - "CMT_FIFO_NW4A2_2", - "CMT_FIFO_NW4A2_3", - "CMT_FIFO_NW4A2_4", - "CMT_FIFO_NW4A2_5", - "CMT_FIFO_NW4A2_6", - "CMT_FIFO_NW4A2_7", - "CMT_FIFO_NW4A2_8", - "CMT_FIFO_NW4A2_9", - "CMT_FIFO_NW4A3_0", - "CMT_FIFO_NW4A3_1", - "CMT_FIFO_NW4A3_10", - "CMT_FIFO_NW4A3_11", - "CMT_FIFO_NW4A3_2", - "CMT_FIFO_NW4A3_3", - "CMT_FIFO_NW4A3_4", - "CMT_FIFO_NW4A3_5", - "CMT_FIFO_NW4A3_6", - "CMT_FIFO_NW4A3_7", - "CMT_FIFO_NW4A3_8", - "CMT_FIFO_NW4A3_9", - "CMT_FIFO_NW4END0_0", - "CMT_FIFO_NW4END0_1", - "CMT_FIFO_NW4END0_10", - "CMT_FIFO_NW4END0_11", - "CMT_FIFO_NW4END0_2", - "CMT_FIFO_NW4END0_3", - "CMT_FIFO_NW4END0_4", - "CMT_FIFO_NW4END0_5", - "CMT_FIFO_NW4END0_6", - "CMT_FIFO_NW4END0_7", - "CMT_FIFO_NW4END0_8", - "CMT_FIFO_NW4END0_9", - "CMT_FIFO_NW4END1_0", - "CMT_FIFO_NW4END1_1", - "CMT_FIFO_NW4END1_10", - "CMT_FIFO_NW4END1_11", - "CMT_FIFO_NW4END1_2", - "CMT_FIFO_NW4END1_3", - "CMT_FIFO_NW4END1_4", - "CMT_FIFO_NW4END1_5", - "CMT_FIFO_NW4END1_6", - "CMT_FIFO_NW4END1_7", - "CMT_FIFO_NW4END1_8", - "CMT_FIFO_NW4END1_9", - "CMT_FIFO_NW4END2_0", - "CMT_FIFO_NW4END2_1", - "CMT_FIFO_NW4END2_10", - "CMT_FIFO_NW4END2_11", - "CMT_FIFO_NW4END2_2", - "CMT_FIFO_NW4END2_3", - "CMT_FIFO_NW4END2_4", - "CMT_FIFO_NW4END2_5", - "CMT_FIFO_NW4END2_6", - "CMT_FIFO_NW4END2_7", - "CMT_FIFO_NW4END2_8", - "CMT_FIFO_NW4END2_9", - "CMT_FIFO_NW4END3_0", - "CMT_FIFO_NW4END3_1", - "CMT_FIFO_NW4END3_10", - "CMT_FIFO_NW4END3_11", - "CMT_FIFO_NW4END3_2", - "CMT_FIFO_NW4END3_3", - "CMT_FIFO_NW4END3_4", - "CMT_FIFO_NW4END3_5", - "CMT_FIFO_NW4END3_6", - "CMT_FIFO_NW4END3_7", - "CMT_FIFO_NW4END3_8", - "CMT_FIFO_NW4END3_9", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_0", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_1", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_10", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_11", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_2", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_3", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_4", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_5", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_6", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_7", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_8", - "CMT_FIFO_PHASER_TO_IO_ICLKDIV_9", - "CMT_FIFO_PHASER_TO_IO_ICLK_0", - "CMT_FIFO_PHASER_TO_IO_ICLK_1", - "CMT_FIFO_PHASER_TO_IO_ICLK_10", - "CMT_FIFO_PHASER_TO_IO_ICLK_11", - "CMT_FIFO_PHASER_TO_IO_ICLK_2", - "CMT_FIFO_PHASER_TO_IO_ICLK_3", - "CMT_FIFO_PHASER_TO_IO_ICLK_4", - "CMT_FIFO_PHASER_TO_IO_ICLK_5", - "CMT_FIFO_PHASER_TO_IO_ICLK_6", - "CMT_FIFO_PHASER_TO_IO_ICLK_7", - "CMT_FIFO_PHASER_TO_IO_ICLK_8", - "CMT_FIFO_PHASER_TO_IO_ICLK_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_1", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_10", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_2", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_3", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_7", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_8", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_9", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_0", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_1", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_10", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_11", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_2", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_3", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_4", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_5", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_6", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_7", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_8", - "CMT_FIFO_PHASER_TO_IO_OCLK1X_90_9", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_0", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_1", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_10", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_11", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_2", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_3", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_4", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_5", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_6", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_7", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_8", - "CMT_FIFO_PHASER_TO_IO_OCLKDIV_9", - "CMT_FIFO_SE2A0_0", - "CMT_FIFO_SE2A0_1", - "CMT_FIFO_SE2A0_10", - "CMT_FIFO_SE2A0_11", - "CMT_FIFO_SE2A0_2", - "CMT_FIFO_SE2A0_3", - "CMT_FIFO_SE2A0_4", - "CMT_FIFO_SE2A0_5", - "CMT_FIFO_SE2A0_6", - "CMT_FIFO_SE2A0_7", - "CMT_FIFO_SE2A0_8", - "CMT_FIFO_SE2A0_9", - "CMT_FIFO_SE2A1_0", - "CMT_FIFO_SE2A1_1", - "CMT_FIFO_SE2A1_10", - "CMT_FIFO_SE2A1_11", - "CMT_FIFO_SE2A1_2", - "CMT_FIFO_SE2A1_3", - "CMT_FIFO_SE2A1_4", - "CMT_FIFO_SE2A1_5", - "CMT_FIFO_SE2A1_6", - "CMT_FIFO_SE2A1_7", - "CMT_FIFO_SE2A1_8", - "CMT_FIFO_SE2A1_9", - "CMT_FIFO_SE2A2_0", - "CMT_FIFO_SE2A2_1", - "CMT_FIFO_SE2A2_10", - "CMT_FIFO_SE2A2_11", - "CMT_FIFO_SE2A2_2", - "CMT_FIFO_SE2A2_3", - "CMT_FIFO_SE2A2_4", - "CMT_FIFO_SE2A2_5", - "CMT_FIFO_SE2A2_6", - "CMT_FIFO_SE2A2_7", - "CMT_FIFO_SE2A2_8", - "CMT_FIFO_SE2A2_9", - "CMT_FIFO_SE2A3_0", - "CMT_FIFO_SE2A3_1", - "CMT_FIFO_SE2A3_10", - "CMT_FIFO_SE2A3_11", - "CMT_FIFO_SE2A3_2", - "CMT_FIFO_SE2A3_3", - "CMT_FIFO_SE2A3_4", - "CMT_FIFO_SE2A3_5", - "CMT_FIFO_SE2A3_6", - "CMT_FIFO_SE2A3_7", - "CMT_FIFO_SE2A3_8", - "CMT_FIFO_SE2A3_9", - "CMT_FIFO_SE4BEG0_0", - "CMT_FIFO_SE4BEG0_1", - "CMT_FIFO_SE4BEG0_10", - "CMT_FIFO_SE4BEG0_11", - "CMT_FIFO_SE4BEG0_2", - "CMT_FIFO_SE4BEG0_3", - "CMT_FIFO_SE4BEG0_4", - "CMT_FIFO_SE4BEG0_5", - "CMT_FIFO_SE4BEG0_6", - "CMT_FIFO_SE4BEG0_7", - "CMT_FIFO_SE4BEG0_8", - "CMT_FIFO_SE4BEG0_9", - "CMT_FIFO_SE4BEG1_0", - "CMT_FIFO_SE4BEG1_1", - "CMT_FIFO_SE4BEG1_10", - "CMT_FIFO_SE4BEG1_11", - "CMT_FIFO_SE4BEG1_2", - "CMT_FIFO_SE4BEG1_3", - "CMT_FIFO_SE4BEG1_4", - "CMT_FIFO_SE4BEG1_5", - "CMT_FIFO_SE4BEG1_6", - "CMT_FIFO_SE4BEG1_7", - "CMT_FIFO_SE4BEG1_8", - "CMT_FIFO_SE4BEG1_9", - "CMT_FIFO_SE4BEG2_0", - "CMT_FIFO_SE4BEG2_1", - "CMT_FIFO_SE4BEG2_10", - "CMT_FIFO_SE4BEG2_11", - "CMT_FIFO_SE4BEG2_2", - "CMT_FIFO_SE4BEG2_3", - "CMT_FIFO_SE4BEG2_4", - "CMT_FIFO_SE4BEG2_5", - "CMT_FIFO_SE4BEG2_6", - "CMT_FIFO_SE4BEG2_7", - "CMT_FIFO_SE4BEG2_8", - "CMT_FIFO_SE4BEG2_9", - "CMT_FIFO_SE4BEG3_0", - "CMT_FIFO_SE4BEG3_1", - "CMT_FIFO_SE4BEG3_10", - "CMT_FIFO_SE4BEG3_11", - "CMT_FIFO_SE4BEG3_2", - "CMT_FIFO_SE4BEG3_3", - "CMT_FIFO_SE4BEG3_4", - "CMT_FIFO_SE4BEG3_5", - "CMT_FIFO_SE4BEG3_6", - "CMT_FIFO_SE4BEG3_7", - "CMT_FIFO_SE4BEG3_8", - "CMT_FIFO_SE4BEG3_9", - "CMT_FIFO_SE4C0_0", - "CMT_FIFO_SE4C0_1", - "CMT_FIFO_SE4C0_10", - "CMT_FIFO_SE4C0_11", - "CMT_FIFO_SE4C0_2", - "CMT_FIFO_SE4C0_3", - "CMT_FIFO_SE4C0_4", - "CMT_FIFO_SE4C0_5", - "CMT_FIFO_SE4C0_6", - "CMT_FIFO_SE4C0_7", - "CMT_FIFO_SE4C0_8", - "CMT_FIFO_SE4C0_9", - "CMT_FIFO_SE4C1_0", - "CMT_FIFO_SE4C1_1", - "CMT_FIFO_SE4C1_10", - "CMT_FIFO_SE4C1_11", - "CMT_FIFO_SE4C1_2", - "CMT_FIFO_SE4C1_3", - "CMT_FIFO_SE4C1_4", - "CMT_FIFO_SE4C1_5", - "CMT_FIFO_SE4C1_6", - "CMT_FIFO_SE4C1_7", - "CMT_FIFO_SE4C1_8", - "CMT_FIFO_SE4C1_9", - "CMT_FIFO_SE4C2_0", - "CMT_FIFO_SE4C2_1", - "CMT_FIFO_SE4C2_10", - "CMT_FIFO_SE4C2_11", - "CMT_FIFO_SE4C2_2", - "CMT_FIFO_SE4C2_3", - "CMT_FIFO_SE4C2_4", - "CMT_FIFO_SE4C2_5", - "CMT_FIFO_SE4C2_6", - "CMT_FIFO_SE4C2_7", - "CMT_FIFO_SE4C2_8", - "CMT_FIFO_SE4C2_9", - "CMT_FIFO_SE4C3_0", - "CMT_FIFO_SE4C3_1", - "CMT_FIFO_SE4C3_10", - "CMT_FIFO_SE4C3_11", - "CMT_FIFO_SE4C3_2", - "CMT_FIFO_SE4C3_3", - "CMT_FIFO_SE4C3_4", - "CMT_FIFO_SE4C3_5", - "CMT_FIFO_SE4C3_6", - "CMT_FIFO_SE4C3_7", - "CMT_FIFO_SE4C3_8", - "CMT_FIFO_SE4C3_9", - "CMT_FIFO_SW2A0_0", - "CMT_FIFO_SW2A0_1", - "CMT_FIFO_SW2A0_10", - "CMT_FIFO_SW2A0_11", - "CMT_FIFO_SW2A0_2", - "CMT_FIFO_SW2A0_3", - "CMT_FIFO_SW2A0_4", - "CMT_FIFO_SW2A0_5", - "CMT_FIFO_SW2A0_6", - "CMT_FIFO_SW2A0_7", - "CMT_FIFO_SW2A0_8", - "CMT_FIFO_SW2A0_9", - "CMT_FIFO_SW2A1_0", - "CMT_FIFO_SW2A1_1", - "CMT_FIFO_SW2A1_10", - "CMT_FIFO_SW2A1_11", - "CMT_FIFO_SW2A1_2", - "CMT_FIFO_SW2A1_3", - "CMT_FIFO_SW2A1_4", - "CMT_FIFO_SW2A1_5", - "CMT_FIFO_SW2A1_6", - "CMT_FIFO_SW2A1_7", - "CMT_FIFO_SW2A1_8", - "CMT_FIFO_SW2A1_9", - "CMT_FIFO_SW2A2_0", - "CMT_FIFO_SW2A2_1", - "CMT_FIFO_SW2A2_10", - "CMT_FIFO_SW2A2_11", - "CMT_FIFO_SW2A2_2", - "CMT_FIFO_SW2A2_3", - "CMT_FIFO_SW2A2_4", - "CMT_FIFO_SW2A2_5", - "CMT_FIFO_SW2A2_6", - "CMT_FIFO_SW2A2_7", - "CMT_FIFO_SW2A2_8", - "CMT_FIFO_SW2A2_9", - "CMT_FIFO_SW2A3_0", - "CMT_FIFO_SW2A3_1", - "CMT_FIFO_SW2A3_10", - "CMT_FIFO_SW2A3_11", - "CMT_FIFO_SW2A3_2", - "CMT_FIFO_SW2A3_3", - "CMT_FIFO_SW2A3_4", - "CMT_FIFO_SW2A3_5", - "CMT_FIFO_SW2A3_6", - "CMT_FIFO_SW2A3_7", - "CMT_FIFO_SW2A3_8", - "CMT_FIFO_SW2A3_9", - "CMT_FIFO_SW4A0_0", - "CMT_FIFO_SW4A0_1", - "CMT_FIFO_SW4A0_10", - "CMT_FIFO_SW4A0_11", - "CMT_FIFO_SW4A0_2", - "CMT_FIFO_SW4A0_3", - "CMT_FIFO_SW4A0_4", - "CMT_FIFO_SW4A0_5", - "CMT_FIFO_SW4A0_6", - "CMT_FIFO_SW4A0_7", - "CMT_FIFO_SW4A0_8", - "CMT_FIFO_SW4A0_9", - "CMT_FIFO_SW4A1_0", - "CMT_FIFO_SW4A1_1", - "CMT_FIFO_SW4A1_10", - "CMT_FIFO_SW4A1_11", - "CMT_FIFO_SW4A1_2", - "CMT_FIFO_SW4A1_3", - "CMT_FIFO_SW4A1_4", - "CMT_FIFO_SW4A1_5", - "CMT_FIFO_SW4A1_6", - "CMT_FIFO_SW4A1_7", - "CMT_FIFO_SW4A1_8", - "CMT_FIFO_SW4A1_9", - "CMT_FIFO_SW4A2_0", - "CMT_FIFO_SW4A2_1", - "CMT_FIFO_SW4A2_10", - "CMT_FIFO_SW4A2_11", - "CMT_FIFO_SW4A2_2", - "CMT_FIFO_SW4A2_3", - "CMT_FIFO_SW4A2_4", - "CMT_FIFO_SW4A2_5", - "CMT_FIFO_SW4A2_6", - "CMT_FIFO_SW4A2_7", - "CMT_FIFO_SW4A2_8", - "CMT_FIFO_SW4A2_9", - "CMT_FIFO_SW4A3_0", - "CMT_FIFO_SW4A3_1", - "CMT_FIFO_SW4A3_10", - "CMT_FIFO_SW4A3_11", - "CMT_FIFO_SW4A3_2", - "CMT_FIFO_SW4A3_3", - "CMT_FIFO_SW4A3_4", - "CMT_FIFO_SW4A3_5", - "CMT_FIFO_SW4A3_6", - "CMT_FIFO_SW4A3_7", - "CMT_FIFO_SW4A3_8", - "CMT_FIFO_SW4A3_9", - "CMT_FIFO_SW4END0_0", - "CMT_FIFO_SW4END0_1", - "CMT_FIFO_SW4END0_10", - "CMT_FIFO_SW4END0_11", - "CMT_FIFO_SW4END0_2", - "CMT_FIFO_SW4END0_3", - "CMT_FIFO_SW4END0_4", - "CMT_FIFO_SW4END0_5", - "CMT_FIFO_SW4END0_6", - "CMT_FIFO_SW4END0_7", - "CMT_FIFO_SW4END0_8", - "CMT_FIFO_SW4END0_9", - "CMT_FIFO_SW4END1_0", - "CMT_FIFO_SW4END1_1", - "CMT_FIFO_SW4END1_10", - "CMT_FIFO_SW4END1_11", - "CMT_FIFO_SW4END1_2", - "CMT_FIFO_SW4END1_3", - "CMT_FIFO_SW4END1_4", - "CMT_FIFO_SW4END1_5", - "CMT_FIFO_SW4END1_6", - "CMT_FIFO_SW4END1_7", - "CMT_FIFO_SW4END1_8", - "CMT_FIFO_SW4END1_9", - "CMT_FIFO_SW4END2_0", - "CMT_FIFO_SW4END2_1", - "CMT_FIFO_SW4END2_10", - "CMT_FIFO_SW4END2_11", - "CMT_FIFO_SW4END2_2", - "CMT_FIFO_SW4END2_3", - "CMT_FIFO_SW4END2_4", - "CMT_FIFO_SW4END2_5", - "CMT_FIFO_SW4END2_6", - "CMT_FIFO_SW4END2_7", - "CMT_FIFO_SW4END2_8", - "CMT_FIFO_SW4END2_9", - "CMT_FIFO_SW4END3_0", - "CMT_FIFO_SW4END3_1", - "CMT_FIFO_SW4END3_10", - "CMT_FIFO_SW4END3_11", - "CMT_FIFO_SW4END3_2", - "CMT_FIFO_SW4END3_3", - "CMT_FIFO_SW4END3_4", - "CMT_FIFO_SW4END3_5", - "CMT_FIFO_SW4END3_6", - "CMT_FIFO_SW4END3_7", - "CMT_FIFO_SW4END3_8", - "CMT_FIFO_SW4END3_9", - "CMT_FIFO_WL1END0_0", - "CMT_FIFO_WL1END0_1", - "CMT_FIFO_WL1END0_10", - "CMT_FIFO_WL1END0_11", - "CMT_FIFO_WL1END0_2", - "CMT_FIFO_WL1END0_3", - "CMT_FIFO_WL1END0_4", - "CMT_FIFO_WL1END0_5", - "CMT_FIFO_WL1END0_6", - "CMT_FIFO_WL1END0_7", - "CMT_FIFO_WL1END0_8", - "CMT_FIFO_WL1END0_9", - "CMT_FIFO_WL1END1_0", - "CMT_FIFO_WL1END1_1", - "CMT_FIFO_WL1END1_10", - "CMT_FIFO_WL1END1_11", - "CMT_FIFO_WL1END1_2", - "CMT_FIFO_WL1END1_3", - "CMT_FIFO_WL1END1_4", - "CMT_FIFO_WL1END1_5", - "CMT_FIFO_WL1END1_6", - "CMT_FIFO_WL1END1_7", - "CMT_FIFO_WL1END1_8", - "CMT_FIFO_WL1END1_9", - "CMT_FIFO_WL1END2_0", - "CMT_FIFO_WL1END2_1", - "CMT_FIFO_WL1END2_10", - "CMT_FIFO_WL1END2_11", - "CMT_FIFO_WL1END2_2", - "CMT_FIFO_WL1END2_3", - "CMT_FIFO_WL1END2_4", - "CMT_FIFO_WL1END2_5", - "CMT_FIFO_WL1END2_6", - "CMT_FIFO_WL1END2_7", - "CMT_FIFO_WL1END2_8", - "CMT_FIFO_WL1END2_9", - "CMT_FIFO_WL1END3_0", - "CMT_FIFO_WL1END3_1", - "CMT_FIFO_WL1END3_10", - "CMT_FIFO_WL1END3_11", - "CMT_FIFO_WL1END3_2", - "CMT_FIFO_WL1END3_3", - "CMT_FIFO_WL1END3_4", - "CMT_FIFO_WL1END3_5", - "CMT_FIFO_WL1END3_6", - "CMT_FIFO_WL1END3_7", - "CMT_FIFO_WL1END3_8", - "CMT_FIFO_WL1END3_9", - "CMT_FIFO_WR1END0_0", - "CMT_FIFO_WR1END0_1", - "CMT_FIFO_WR1END0_10", - "CMT_FIFO_WR1END0_11", - "CMT_FIFO_WR1END0_2", - "CMT_FIFO_WR1END0_3", - "CMT_FIFO_WR1END0_4", - "CMT_FIFO_WR1END0_5", - "CMT_FIFO_WR1END0_6", - "CMT_FIFO_WR1END0_7", - "CMT_FIFO_WR1END0_8", - "CMT_FIFO_WR1END0_9", - "CMT_FIFO_WR1END1_0", - "CMT_FIFO_WR1END1_1", - "CMT_FIFO_WR1END1_10", - "CMT_FIFO_WR1END1_11", - "CMT_FIFO_WR1END1_2", - "CMT_FIFO_WR1END1_3", - "CMT_FIFO_WR1END1_4", - "CMT_FIFO_WR1END1_5", - "CMT_FIFO_WR1END1_6", - "CMT_FIFO_WR1END1_7", - "CMT_FIFO_WR1END1_8", - "CMT_FIFO_WR1END1_9", - "CMT_FIFO_WR1END2_0", - "CMT_FIFO_WR1END2_1", - "CMT_FIFO_WR1END2_10", - "CMT_FIFO_WR1END2_11", - "CMT_FIFO_WR1END2_2", - "CMT_FIFO_WR1END2_3", - "CMT_FIFO_WR1END2_4", - "CMT_FIFO_WR1END2_5", - "CMT_FIFO_WR1END2_6", - "CMT_FIFO_WR1END2_7", - "CMT_FIFO_WR1END2_8", - "CMT_FIFO_WR1END2_9", - "CMT_FIFO_WR1END3_0", - "CMT_FIFO_WR1END3_1", - "CMT_FIFO_WR1END3_10", - "CMT_FIFO_WR1END3_11", - "CMT_FIFO_WR1END3_2", - "CMT_FIFO_WR1END3_3", - "CMT_FIFO_WR1END3_4", - "CMT_FIFO_WR1END3_5", - "CMT_FIFO_WR1END3_6", - "CMT_FIFO_WR1END3_7", - "CMT_FIFO_WR1END3_8", - "CMT_FIFO_WR1END3_9", - "CMT_FIFO_WW2A0_0", - "CMT_FIFO_WW2A0_1", - "CMT_FIFO_WW2A0_10", - "CMT_FIFO_WW2A0_11", - "CMT_FIFO_WW2A0_2", - "CMT_FIFO_WW2A0_3", - "CMT_FIFO_WW2A0_4", - "CMT_FIFO_WW2A0_5", - "CMT_FIFO_WW2A0_6", - "CMT_FIFO_WW2A0_7", - "CMT_FIFO_WW2A0_8", - "CMT_FIFO_WW2A0_9", - "CMT_FIFO_WW2A1_0", - "CMT_FIFO_WW2A1_1", - "CMT_FIFO_WW2A1_10", - "CMT_FIFO_WW2A1_11", - "CMT_FIFO_WW2A1_2", - "CMT_FIFO_WW2A1_3", - "CMT_FIFO_WW2A1_4", - "CMT_FIFO_WW2A1_5", - "CMT_FIFO_WW2A1_6", - "CMT_FIFO_WW2A1_7", - "CMT_FIFO_WW2A1_8", - "CMT_FIFO_WW2A1_9", - "CMT_FIFO_WW2A2_0", - "CMT_FIFO_WW2A2_1", - "CMT_FIFO_WW2A2_10", - "CMT_FIFO_WW2A2_11", - "CMT_FIFO_WW2A2_2", - "CMT_FIFO_WW2A2_3", - "CMT_FIFO_WW2A2_4", - "CMT_FIFO_WW2A2_5", - "CMT_FIFO_WW2A2_6", - "CMT_FIFO_WW2A2_7", - "CMT_FIFO_WW2A2_8", - "CMT_FIFO_WW2A2_9", - "CMT_FIFO_WW2A3_0", - "CMT_FIFO_WW2A3_1", - "CMT_FIFO_WW2A3_10", - "CMT_FIFO_WW2A3_11", - "CMT_FIFO_WW2A3_2", - "CMT_FIFO_WW2A3_3", - "CMT_FIFO_WW2A3_4", - "CMT_FIFO_WW2A3_5", - "CMT_FIFO_WW2A3_6", - "CMT_FIFO_WW2A3_7", - "CMT_FIFO_WW2A3_8", - "CMT_FIFO_WW2A3_9", - "CMT_FIFO_WW2END0_0", - "CMT_FIFO_WW2END0_1", - "CMT_FIFO_WW2END0_10", - "CMT_FIFO_WW2END0_11", - "CMT_FIFO_WW2END0_2", - "CMT_FIFO_WW2END0_3", - "CMT_FIFO_WW2END0_4", - "CMT_FIFO_WW2END0_5", - "CMT_FIFO_WW2END0_6", - "CMT_FIFO_WW2END0_7", - "CMT_FIFO_WW2END0_8", - "CMT_FIFO_WW2END0_9", - "CMT_FIFO_WW2END1_0", - "CMT_FIFO_WW2END1_1", - "CMT_FIFO_WW2END1_10", - "CMT_FIFO_WW2END1_11", - "CMT_FIFO_WW2END1_2", - "CMT_FIFO_WW2END1_3", - "CMT_FIFO_WW2END1_4", - "CMT_FIFO_WW2END1_5", - "CMT_FIFO_WW2END1_6", - "CMT_FIFO_WW2END1_7", - "CMT_FIFO_WW2END1_8", - "CMT_FIFO_WW2END1_9", - "CMT_FIFO_WW2END2_0", - "CMT_FIFO_WW2END2_1", - "CMT_FIFO_WW2END2_10", - "CMT_FIFO_WW2END2_11", - "CMT_FIFO_WW2END2_2", - "CMT_FIFO_WW2END2_3", - "CMT_FIFO_WW2END2_4", - "CMT_FIFO_WW2END2_5", - "CMT_FIFO_WW2END2_6", - "CMT_FIFO_WW2END2_7", - "CMT_FIFO_WW2END2_8", - "CMT_FIFO_WW2END2_9", - "CMT_FIFO_WW2END3_0", - "CMT_FIFO_WW2END3_1", - "CMT_FIFO_WW2END3_10", - "CMT_FIFO_WW2END3_11", - "CMT_FIFO_WW2END3_2", - "CMT_FIFO_WW2END3_3", - "CMT_FIFO_WW2END3_4", - "CMT_FIFO_WW2END3_5", - "CMT_FIFO_WW2END3_6", - "CMT_FIFO_WW2END3_7", - "CMT_FIFO_WW2END3_8", - "CMT_FIFO_WW2END3_9", - "CMT_FIFO_WW4A0_0", - "CMT_FIFO_WW4A0_1", - "CMT_FIFO_WW4A0_10", - "CMT_FIFO_WW4A0_11", - "CMT_FIFO_WW4A0_2", - "CMT_FIFO_WW4A0_3", - "CMT_FIFO_WW4A0_4", - "CMT_FIFO_WW4A0_5", - "CMT_FIFO_WW4A0_6", - "CMT_FIFO_WW4A0_7", - "CMT_FIFO_WW4A0_8", - "CMT_FIFO_WW4A0_9", - "CMT_FIFO_WW4A1_0", - "CMT_FIFO_WW4A1_1", - "CMT_FIFO_WW4A1_10", - "CMT_FIFO_WW4A1_11", - "CMT_FIFO_WW4A1_2", - "CMT_FIFO_WW4A1_3", - "CMT_FIFO_WW4A1_4", - "CMT_FIFO_WW4A1_5", - "CMT_FIFO_WW4A1_6", - "CMT_FIFO_WW4A1_7", - "CMT_FIFO_WW4A1_8", - "CMT_FIFO_WW4A1_9", - "CMT_FIFO_WW4A2_0", - "CMT_FIFO_WW4A2_1", - "CMT_FIFO_WW4A2_10", - "CMT_FIFO_WW4A2_11", - "CMT_FIFO_WW4A2_2", - "CMT_FIFO_WW4A2_3", - "CMT_FIFO_WW4A2_4", - "CMT_FIFO_WW4A2_5", - "CMT_FIFO_WW4A2_6", - "CMT_FIFO_WW4A2_7", - "CMT_FIFO_WW4A2_8", - "CMT_FIFO_WW4A2_9", - "CMT_FIFO_WW4A3_0", - "CMT_FIFO_WW4A3_1", - "CMT_FIFO_WW4A3_10", - "CMT_FIFO_WW4A3_11", - "CMT_FIFO_WW4A3_2", - "CMT_FIFO_WW4A3_3", - "CMT_FIFO_WW4A3_4", - "CMT_FIFO_WW4A3_5", - "CMT_FIFO_WW4A3_6", - "CMT_FIFO_WW4A3_7", - "CMT_FIFO_WW4A3_8", - "CMT_FIFO_WW4A3_9", - "CMT_FIFO_WW4B0_0", - "CMT_FIFO_WW4B0_1", - "CMT_FIFO_WW4B0_10", - "CMT_FIFO_WW4B0_11", - "CMT_FIFO_WW4B0_2", - "CMT_FIFO_WW4B0_3", - "CMT_FIFO_WW4B0_4", - "CMT_FIFO_WW4B0_5", - "CMT_FIFO_WW4B0_6", - "CMT_FIFO_WW4B0_7", - "CMT_FIFO_WW4B0_8", - "CMT_FIFO_WW4B0_9", - "CMT_FIFO_WW4B1_0", - "CMT_FIFO_WW4B1_1", - "CMT_FIFO_WW4B1_10", - "CMT_FIFO_WW4B1_11", - "CMT_FIFO_WW4B1_2", - "CMT_FIFO_WW4B1_3", - "CMT_FIFO_WW4B1_4", - "CMT_FIFO_WW4B1_5", - "CMT_FIFO_WW4B1_6", - "CMT_FIFO_WW4B1_7", - "CMT_FIFO_WW4B1_8", - "CMT_FIFO_WW4B1_9", - "CMT_FIFO_WW4B2_0", - "CMT_FIFO_WW4B2_1", - "CMT_FIFO_WW4B2_10", - "CMT_FIFO_WW4B2_11", - "CMT_FIFO_WW4B2_2", - "CMT_FIFO_WW4B2_3", - "CMT_FIFO_WW4B2_4", - "CMT_FIFO_WW4B2_5", - "CMT_FIFO_WW4B2_6", - "CMT_FIFO_WW4B2_7", - "CMT_FIFO_WW4B2_8", - "CMT_FIFO_WW4B2_9", - "CMT_FIFO_WW4B3_0", - "CMT_FIFO_WW4B3_1", - "CMT_FIFO_WW4B3_10", - "CMT_FIFO_WW4B3_11", - "CMT_FIFO_WW4B3_2", - "CMT_FIFO_WW4B3_3", - "CMT_FIFO_WW4B3_4", - "CMT_FIFO_WW4B3_5", - "CMT_FIFO_WW4B3_6", - "CMT_FIFO_WW4B3_7", - "CMT_FIFO_WW4B3_8", - "CMT_FIFO_WW4B3_9", - "CMT_FIFO_WW4C0_0", - "CMT_FIFO_WW4C0_1", - "CMT_FIFO_WW4C0_10", - "CMT_FIFO_WW4C0_11", - "CMT_FIFO_WW4C0_2", - "CMT_FIFO_WW4C0_3", - "CMT_FIFO_WW4C0_4", - "CMT_FIFO_WW4C0_5", - "CMT_FIFO_WW4C0_6", - "CMT_FIFO_WW4C0_7", - "CMT_FIFO_WW4C0_8", - "CMT_FIFO_WW4C0_9", - "CMT_FIFO_WW4C1_0", - "CMT_FIFO_WW4C1_1", - "CMT_FIFO_WW4C1_10", - "CMT_FIFO_WW4C1_11", - "CMT_FIFO_WW4C1_2", - "CMT_FIFO_WW4C1_3", - "CMT_FIFO_WW4C1_4", - "CMT_FIFO_WW4C1_5", - "CMT_FIFO_WW4C1_6", - "CMT_FIFO_WW4C1_7", - "CMT_FIFO_WW4C1_8", - "CMT_FIFO_WW4C1_9", - "CMT_FIFO_WW4C2_0", - "CMT_FIFO_WW4C2_1", - "CMT_FIFO_WW4C2_10", - "CMT_FIFO_WW4C2_11", - "CMT_FIFO_WW4C2_2", - "CMT_FIFO_WW4C2_3", - "CMT_FIFO_WW4C2_4", - "CMT_FIFO_WW4C2_5", - "CMT_FIFO_WW4C2_6", - "CMT_FIFO_WW4C2_7", - "CMT_FIFO_WW4C2_8", - "CMT_FIFO_WW4C2_9", - "CMT_FIFO_WW4C3_0", - "CMT_FIFO_WW4C3_1", - "CMT_FIFO_WW4C3_10", - "CMT_FIFO_WW4C3_11", - "CMT_FIFO_WW4C3_2", - "CMT_FIFO_WW4C3_3", - "CMT_FIFO_WW4C3_4", - "CMT_FIFO_WW4C3_5", - "CMT_FIFO_WW4C3_6", - "CMT_FIFO_WW4C3_7", - "CMT_FIFO_WW4C3_8", - "CMT_FIFO_WW4C3_9", - "CMT_FIFO_WW4END0_0", - "CMT_FIFO_WW4END0_1", - "CMT_FIFO_WW4END0_10", - "CMT_FIFO_WW4END0_11", - "CMT_FIFO_WW4END0_2", - "CMT_FIFO_WW4END0_3", - "CMT_FIFO_WW4END0_4", - "CMT_FIFO_WW4END0_5", - "CMT_FIFO_WW4END0_6", - "CMT_FIFO_WW4END0_7", - "CMT_FIFO_WW4END0_8", - "CMT_FIFO_WW4END0_9", - "CMT_FIFO_WW4END1_0", - "CMT_FIFO_WW4END1_1", - "CMT_FIFO_WW4END1_10", - "CMT_FIFO_WW4END1_11", - "CMT_FIFO_WW4END1_2", - "CMT_FIFO_WW4END1_3", - "CMT_FIFO_WW4END1_4", - "CMT_FIFO_WW4END1_5", - "CMT_FIFO_WW4END1_6", - "CMT_FIFO_WW4END1_7", - "CMT_FIFO_WW4END1_8", - "CMT_FIFO_WW4END1_9", - "CMT_FIFO_WW4END2_0", - "CMT_FIFO_WW4END2_1", - "CMT_FIFO_WW4END2_10", - "CMT_FIFO_WW4END2_11", - "CMT_FIFO_WW4END2_2", - "CMT_FIFO_WW4END2_3", - "CMT_FIFO_WW4END2_4", - "CMT_FIFO_WW4END2_5", - "CMT_FIFO_WW4END2_6", - "CMT_FIFO_WW4END2_7", - "CMT_FIFO_WW4END2_8", - "CMT_FIFO_WW4END2_9", - "CMT_FIFO_WW4END3_0", - "CMT_FIFO_WW4END3_1", - "CMT_FIFO_WW4END3_10", - "CMT_FIFO_WW4END3_11", - "CMT_FIFO_WW4END3_2", - "CMT_FIFO_WW4END3_3", - "CMT_FIFO_WW4END3_4", - "CMT_FIFO_WW4END3_5", - "CMT_FIFO_WW4END3_6", - "CMT_FIFO_WW4END3_7", - "CMT_FIFO_WW4END3_8", - "CMT_FIFO_WW4END3_9", - "CMT_IN_FIFO_ALMOSTEMPTY", - "CMT_IN_FIFO_ALMOSTFULL", - "CMT_IN_FIFO_D00", - "CMT_IN_FIFO_D01", - "CMT_IN_FIFO_D02", - "CMT_IN_FIFO_D03", - "CMT_IN_FIFO_D10", - "CMT_IN_FIFO_D11", - "CMT_IN_FIFO_D12", - "CMT_IN_FIFO_D13", - "CMT_IN_FIFO_D20", - "CMT_IN_FIFO_D21", - "CMT_IN_FIFO_D22", - "CMT_IN_FIFO_D23", - "CMT_IN_FIFO_D30", - "CMT_IN_FIFO_D31", - "CMT_IN_FIFO_D32", - "CMT_IN_FIFO_D33", - "CMT_IN_FIFO_D40", - "CMT_IN_FIFO_D41", - "CMT_IN_FIFO_D42", - "CMT_IN_FIFO_D43", - "CMT_IN_FIFO_D50", - "CMT_IN_FIFO_D51", - "CMT_IN_FIFO_D52", - "CMT_IN_FIFO_D53", - "CMT_IN_FIFO_D54", - "CMT_IN_FIFO_D55", - "CMT_IN_FIFO_D56", - "CMT_IN_FIFO_D57", - "CMT_IN_FIFO_D60", - "CMT_IN_FIFO_D61", - "CMT_IN_FIFO_D62", - "CMT_IN_FIFO_D63", - "CMT_IN_FIFO_D64", - "CMT_IN_FIFO_D65", - "CMT_IN_FIFO_D66", - "CMT_IN_FIFO_D67", - "CMT_IN_FIFO_D70", - "CMT_IN_FIFO_D71", - "CMT_IN_FIFO_D72", - "CMT_IN_FIFO_D73", - "CMT_IN_FIFO_D80", - "CMT_IN_FIFO_D81", - "CMT_IN_FIFO_D82", - "CMT_IN_FIFO_D83", - "CMT_IN_FIFO_D90", - "CMT_IN_FIFO_D91", - "CMT_IN_FIFO_D92", - "CMT_IN_FIFO_D93", - "CMT_IN_FIFO_EMPTY", - "CMT_IN_FIFO_FULL", - "CMT_IN_FIFO_Q00", - "CMT_IN_FIFO_Q01", - "CMT_IN_FIFO_Q02", - "CMT_IN_FIFO_Q03", - "CMT_IN_FIFO_Q04", - "CMT_IN_FIFO_Q05", - "CMT_IN_FIFO_Q06", - "CMT_IN_FIFO_Q07", - "CMT_IN_FIFO_Q10", - "CMT_IN_FIFO_Q11", - "CMT_IN_FIFO_Q12", - "CMT_IN_FIFO_Q13", - "CMT_IN_FIFO_Q14", - "CMT_IN_FIFO_Q15", - "CMT_IN_FIFO_Q16", - "CMT_IN_FIFO_Q17", - "CMT_IN_FIFO_Q20", - "CMT_IN_FIFO_Q21", - "CMT_IN_FIFO_Q22", - "CMT_IN_FIFO_Q23", - "CMT_IN_FIFO_Q24", - "CMT_IN_FIFO_Q25", - "CMT_IN_FIFO_Q26", - "CMT_IN_FIFO_Q27", - "CMT_IN_FIFO_Q30", - "CMT_IN_FIFO_Q31", - "CMT_IN_FIFO_Q32", - "CMT_IN_FIFO_Q33", - "CMT_IN_FIFO_Q34", - "CMT_IN_FIFO_Q35", - "CMT_IN_FIFO_Q36", - "CMT_IN_FIFO_Q37", - "CMT_IN_FIFO_Q40", - "CMT_IN_FIFO_Q41", - "CMT_IN_FIFO_Q42", - "CMT_IN_FIFO_Q43", - "CMT_IN_FIFO_Q44", - "CMT_IN_FIFO_Q45", - "CMT_IN_FIFO_Q46", - "CMT_IN_FIFO_Q47", - "CMT_IN_FIFO_Q50", - "CMT_IN_FIFO_Q51", - "CMT_IN_FIFO_Q52", - "CMT_IN_FIFO_Q53", - "CMT_IN_FIFO_Q54", - "CMT_IN_FIFO_Q55", - "CMT_IN_FIFO_Q56", - "CMT_IN_FIFO_Q57", - "CMT_IN_FIFO_Q60", - "CMT_IN_FIFO_Q61", - "CMT_IN_FIFO_Q62", - "CMT_IN_FIFO_Q63", - "CMT_IN_FIFO_Q64", - "CMT_IN_FIFO_Q65", - "CMT_IN_FIFO_Q66", - "CMT_IN_FIFO_Q67", - "CMT_IN_FIFO_Q70", - "CMT_IN_FIFO_Q71", - "CMT_IN_FIFO_Q72", - "CMT_IN_FIFO_Q73", - "CMT_IN_FIFO_Q74", - "CMT_IN_FIFO_Q75", - "CMT_IN_FIFO_Q76", - "CMT_IN_FIFO_Q77", - "CMT_IN_FIFO_Q80", - "CMT_IN_FIFO_Q81", - "CMT_IN_FIFO_Q82", - "CMT_IN_FIFO_Q83", - "CMT_IN_FIFO_Q84", - "CMT_IN_FIFO_Q85", - "CMT_IN_FIFO_Q86", - "CMT_IN_FIFO_Q87", - "CMT_IN_FIFO_Q90", - "CMT_IN_FIFO_Q91", - "CMT_IN_FIFO_Q92", - "CMT_IN_FIFO_Q93", - "CMT_IN_FIFO_Q94", - "CMT_IN_FIFO_Q95", - "CMT_IN_FIFO_Q96", - "CMT_IN_FIFO_Q97", - "CMT_IN_FIFO_RDCLK", - "CMT_IN_FIFO_RDEN", - "CMT_IN_FIFO_RESET", - "CMT_IN_FIFO_SCANENB", - "CMT_IN_FIFO_SCANIN0", - "CMT_IN_FIFO_SCANIN1", - "CMT_IN_FIFO_SCANIN2", - "CMT_IN_FIFO_SCANIN3", - "CMT_IN_FIFO_SCANOUT0", - "CMT_IN_FIFO_SCANOUT1", - "CMT_IN_FIFO_SCANOUT2", - "CMT_IN_FIFO_SCANOUT3", - "CMT_IN_FIFO_TESTMODEB", - "CMT_IN_FIFO_TESTREADDISB", - "CMT_IN_FIFO_TESTWRITEDISB", - "CMT_IN_FIFO_WRCLK", - "CMT_IN_FIFO_WREN", - "CMT_OUT_FIFO_ALMOSTEMPTY", - "CMT_OUT_FIFO_ALMOSTFULL", - "CMT_OUT_FIFO_D00", - "CMT_OUT_FIFO_D01", - "CMT_OUT_FIFO_D02", - "CMT_OUT_FIFO_D03", - "CMT_OUT_FIFO_D04", - "CMT_OUT_FIFO_D05", - "CMT_OUT_FIFO_D06", - "CMT_OUT_FIFO_D07", - "CMT_OUT_FIFO_D10", - "CMT_OUT_FIFO_D11", - "CMT_OUT_FIFO_D12", - "CMT_OUT_FIFO_D13", - "CMT_OUT_FIFO_D14", - "CMT_OUT_FIFO_D15", - "CMT_OUT_FIFO_D16", - "CMT_OUT_FIFO_D17", - "CMT_OUT_FIFO_D20", - "CMT_OUT_FIFO_D21", - "CMT_OUT_FIFO_D22", - "CMT_OUT_FIFO_D23", - "CMT_OUT_FIFO_D24", - "CMT_OUT_FIFO_D25", - "CMT_OUT_FIFO_D26", - "CMT_OUT_FIFO_D27", - "CMT_OUT_FIFO_D30", - "CMT_OUT_FIFO_D31", - "CMT_OUT_FIFO_D32", - "CMT_OUT_FIFO_D33", - "CMT_OUT_FIFO_D34", - "CMT_OUT_FIFO_D35", - "CMT_OUT_FIFO_D36", - "CMT_OUT_FIFO_D37", - "CMT_OUT_FIFO_D40", - "CMT_OUT_FIFO_D41", - "CMT_OUT_FIFO_D42", - "CMT_OUT_FIFO_D43", - "CMT_OUT_FIFO_D44", - "CMT_OUT_FIFO_D45", - "CMT_OUT_FIFO_D46", - "CMT_OUT_FIFO_D47", - "CMT_OUT_FIFO_D50", - "CMT_OUT_FIFO_D51", - "CMT_OUT_FIFO_D52", - "CMT_OUT_FIFO_D53", - "CMT_OUT_FIFO_D54", - "CMT_OUT_FIFO_D55", - "CMT_OUT_FIFO_D56", - "CMT_OUT_FIFO_D57", - "CMT_OUT_FIFO_D60", - "CMT_OUT_FIFO_D61", - "CMT_OUT_FIFO_D62", - "CMT_OUT_FIFO_D63", - "CMT_OUT_FIFO_D64", - "CMT_OUT_FIFO_D65", - "CMT_OUT_FIFO_D66", - "CMT_OUT_FIFO_D67", - "CMT_OUT_FIFO_D70", - "CMT_OUT_FIFO_D71", - "CMT_OUT_FIFO_D72", - "CMT_OUT_FIFO_D73", - "CMT_OUT_FIFO_D74", - "CMT_OUT_FIFO_D75", - "CMT_OUT_FIFO_D76", - "CMT_OUT_FIFO_D77", - "CMT_OUT_FIFO_D80", - "CMT_OUT_FIFO_D81", - "CMT_OUT_FIFO_D82", - "CMT_OUT_FIFO_D83", - "CMT_OUT_FIFO_D84", - "CMT_OUT_FIFO_D85", - "CMT_OUT_FIFO_D86", - "CMT_OUT_FIFO_D87", - "CMT_OUT_FIFO_D90", - "CMT_OUT_FIFO_D91", - "CMT_OUT_FIFO_D92", - "CMT_OUT_FIFO_D93", - "CMT_OUT_FIFO_D94", - "CMT_OUT_FIFO_D95", - "CMT_OUT_FIFO_D96", - "CMT_OUT_FIFO_D97", - "CMT_OUT_FIFO_EMPTY", - "CMT_OUT_FIFO_FULL", - "CMT_OUT_FIFO_Q00", - "CMT_OUT_FIFO_Q01", - "CMT_OUT_FIFO_Q02", - "CMT_OUT_FIFO_Q03", - "CMT_OUT_FIFO_Q10", - "CMT_OUT_FIFO_Q11", - "CMT_OUT_FIFO_Q12", - "CMT_OUT_FIFO_Q13", - "CMT_OUT_FIFO_Q20", - "CMT_OUT_FIFO_Q21", - "CMT_OUT_FIFO_Q22", - "CMT_OUT_FIFO_Q23", - "CMT_OUT_FIFO_Q30", - "CMT_OUT_FIFO_Q31", - "CMT_OUT_FIFO_Q32", - "CMT_OUT_FIFO_Q33", - "CMT_OUT_FIFO_Q40", - "CMT_OUT_FIFO_Q41", - "CMT_OUT_FIFO_Q42", - "CMT_OUT_FIFO_Q43", - "CMT_OUT_FIFO_Q50", - "CMT_OUT_FIFO_Q51", - "CMT_OUT_FIFO_Q52", - "CMT_OUT_FIFO_Q53", - "CMT_OUT_FIFO_Q54", - "CMT_OUT_FIFO_Q55", - "CMT_OUT_FIFO_Q56", - "CMT_OUT_FIFO_Q57", - "CMT_OUT_FIFO_Q60", - "CMT_OUT_FIFO_Q61", - "CMT_OUT_FIFO_Q62", - "CMT_OUT_FIFO_Q63", - "CMT_OUT_FIFO_Q64", - "CMT_OUT_FIFO_Q65", - "CMT_OUT_FIFO_Q66", - "CMT_OUT_FIFO_Q67", - "CMT_OUT_FIFO_Q70", - "CMT_OUT_FIFO_Q71", - "CMT_OUT_FIFO_Q72", - "CMT_OUT_FIFO_Q73", - "CMT_OUT_FIFO_Q80", - "CMT_OUT_FIFO_Q81", - "CMT_OUT_FIFO_Q82", - "CMT_OUT_FIFO_Q83", - "CMT_OUT_FIFO_Q90", - "CMT_OUT_FIFO_Q91", - "CMT_OUT_FIFO_Q92", - "CMT_OUT_FIFO_Q93", - "CMT_OUT_FIFO_RDCLK", - "CMT_OUT_FIFO_RDEN", - "CMT_OUT_FIFO_RESET", - "CMT_OUT_FIFO_SCANENB", - "CMT_OUT_FIFO_SCANIN0", - "CMT_OUT_FIFO_SCANIN1", - "CMT_OUT_FIFO_SCANIN2", - "CMT_OUT_FIFO_SCANIN3", - "CMT_OUT_FIFO_SCANOUT0", - "CMT_OUT_FIFO_SCANOUT1", - "CMT_OUT_FIFO_SCANOUT2", - "CMT_OUT_FIFO_SCANOUT3", - "CMT_OUT_FIFO_TESTMODEB", - "CMT_OUT_FIFO_TESTREADDISB", - "CMT_OUT_FIFO_TESTWRITEDISB", - "CMT_OUT_FIFO_WRCLK", - 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"CMT_OUT_FIFO_D87": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D90": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D91": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D92": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D93": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D94": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D95": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D96": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_D97": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_EMPTY": { + "cap": "6.850", + "res": "0.000" + }, + "CMT_OUT_FIFO_FULL": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q00": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q01": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q02": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q03": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q10": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q11": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q12": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q13": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q20": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q21": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q22": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q23": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q30": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q31": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q32": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q33": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q40": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q41": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q42": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q43": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q50": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q51": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q52": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q53": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q54": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q55": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q56": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q57": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q60": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q61": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q62": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q63": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q64": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q65": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q66": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q67": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q70": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q71": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q72": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q73": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q80": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q81": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q82": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q83": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q90": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q91": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q92": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_Q93": { + "cap": "0.685", + "res": "0.000" + }, + "CMT_OUT_FIFO_RDCLK": { + "cap": "9.585", + "res": "0.000" + }, + "CMT_OUT_FIFO_RDEN": { + "cap": "4.293", + "res": "0.000" + }, + "CMT_OUT_FIFO_RESET": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANENB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN0": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN1": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN2": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANIN3": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT0": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT1": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT2": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_SCANOUT3": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_TESTMODEB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_TESTREADDISB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_TESTWRITEDISB": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_OUT_FIFO_WRCLK": { + "cap": "9.585", + "res": "0.000" + }, + "CMT_OUT_FIFO_WREN": { + "cap": "1.649", + "res": "0.000" + }, + "FIFO_DQS_IOTOPHASER_1": null, + "FIFO_DQS_IOTOPHASER_11": null, + "FIFO_DQS_IOTOPHASER_2": null, + "FIFO_DQS_IOTOPHASER_22": null, + "FIFO_DQS_IOTOPHASER_3": null, + "FIFO_DQS_IOTOPHASER_33": null, + "FIFO_DQS_IOTOPHASER_4": null, + "FIFO_DQS_IOTOPHASER_44": null, + "FIFO_DQS_IOTOPHASER_5": null, + "FIFO_DQS_IOTOPHASER_55": null, + "FIFO_DQS_IOTOPHASER_6": null, + "FIFO_DQS_IOTOPHASER_66": null + } } diff --git a/kintex7/tile_type_CMT_PMV.json b/kintex7/tile_type_CMT_PMV.json index 4b27f04..0759c87 100644 --- a/kintex7/tile_type_CMT_PMV.json +++ b/kintex7/tile_type_CMT_PMV.json @@ -2,229 +2,601 @@ "pips": {}, "sites": [], "tile_type": "CMT_PMV", - "wires": [ - "CMT_PMV_BYP0", - "CMT_PMV_BYP1", - "CMT_PMV_BYP2", - "CMT_PMV_BYP3", - "CMT_PMV_BYP4", - "CMT_PMV_BYP5", - "CMT_PMV_BYP6", - "CMT_PMV_BYP7", - "CMT_PMV_CLK0", - "CMT_PMV_CLK1", - "CMT_PMV_CTRL0", - "CMT_PMV_CTRL1", - "CMT_PMV_EE2A0", - "CMT_PMV_EE2A1", - "CMT_PMV_EE2A2", - "CMT_PMV_EE2A3", - "CMT_PMV_EE2BEG0", - "CMT_PMV_EE2BEG1", - "CMT_PMV_EE2BEG2", - "CMT_PMV_EE2BEG3", - "CMT_PMV_EE4A0", - "CMT_PMV_EE4A1", - "CMT_PMV_EE4A2", - "CMT_PMV_EE4A3", - "CMT_PMV_EE4B0", - "CMT_PMV_EE4B1", - "CMT_PMV_EE4B2", - "CMT_PMV_EE4B3", - "CMT_PMV_EE4BEG0", - "CMT_PMV_EE4BEG1", - "CMT_PMV_EE4BEG2", - "CMT_PMV_EE4BEG3", - "CMT_PMV_EE4C0", - "CMT_PMV_EE4C1", - "CMT_PMV_EE4C2", - "CMT_PMV_EE4C3", - "CMT_PMV_EL1BEG0", - "CMT_PMV_EL1BEG1", - "CMT_PMV_EL1BEG2", - "CMT_PMV_EL1BEG3", - "CMT_PMV_ER1BEG0", - "CMT_PMV_ER1BEG1", - "CMT_PMV_ER1BEG2", - "CMT_PMV_ER1BEG3", - "CMT_PMV_FAN0", - "CMT_PMV_FAN1", - "CMT_PMV_FAN2", - "CMT_PMV_FAN3", - "CMT_PMV_FAN4", - "CMT_PMV_FAN5", - "CMT_PMV_FAN6", - "CMT_PMV_FAN7", - "CMT_PMV_IMUX0", - "CMT_PMV_IMUX1", - "CMT_PMV_IMUX10", - "CMT_PMV_IMUX11", - "CMT_PMV_IMUX12", - "CMT_PMV_IMUX13", - "CMT_PMV_IMUX14", - "CMT_PMV_IMUX15", - "CMT_PMV_IMUX16", - "CMT_PMV_IMUX17", - "CMT_PMV_IMUX18", - "CMT_PMV_IMUX19", - "CMT_PMV_IMUX2", - "CMT_PMV_IMUX20", - "CMT_PMV_IMUX21", - "CMT_PMV_IMUX22", - "CMT_PMV_IMUX23", - "CMT_PMV_IMUX24", - "CMT_PMV_IMUX25", - "CMT_PMV_IMUX26", - "CMT_PMV_IMUX27", - "CMT_PMV_IMUX28", - "CMT_PMV_IMUX29", - "CMT_PMV_IMUX3", - "CMT_PMV_IMUX30", - "CMT_PMV_IMUX31", - "CMT_PMV_IMUX32", - "CMT_PMV_IMUX33", - "CMT_PMV_IMUX34", - "CMT_PMV_IMUX35", - "CMT_PMV_IMUX36", - "CMT_PMV_IMUX37", - "CMT_PMV_IMUX38", - "CMT_PMV_IMUX39", - "CMT_PMV_IMUX4", - "CMT_PMV_IMUX40", - "CMT_PMV_IMUX41", - "CMT_PMV_IMUX42", - "CMT_PMV_IMUX43", - "CMT_PMV_IMUX44", - "CMT_PMV_IMUX45", - "CMT_PMV_IMUX46", - "CMT_PMV_IMUX47", - "CMT_PMV_IMUX5", - "CMT_PMV_IMUX6", - "CMT_PMV_IMUX7", - "CMT_PMV_IMUX8", - "CMT_PMV_IMUX9", - "CMT_PMV_LH1", - "CMT_PMV_LH10", - "CMT_PMV_LH11", - "CMT_PMV_LH12", - "CMT_PMV_LH2", - "CMT_PMV_LH3", - "CMT_PMV_LH4", - "CMT_PMV_LH5", - "CMT_PMV_LH6", - "CMT_PMV_LH7", - "CMT_PMV_LH8", - "CMT_PMV_LH9", - "CMT_PMV_LOGIC_OUTS0", - "CMT_PMV_LOGIC_OUTS1", - "CMT_PMV_LOGIC_OUTS10", - "CMT_PMV_LOGIC_OUTS11", - "CMT_PMV_LOGIC_OUTS12", - "CMT_PMV_LOGIC_OUTS13", - "CMT_PMV_LOGIC_OUTS14", - "CMT_PMV_LOGIC_OUTS15", - "CMT_PMV_LOGIC_OUTS16", - "CMT_PMV_LOGIC_OUTS17", - "CMT_PMV_LOGIC_OUTS18", - "CMT_PMV_LOGIC_OUTS19", - "CMT_PMV_LOGIC_OUTS2", - "CMT_PMV_LOGIC_OUTS20", - "CMT_PMV_LOGIC_OUTS21", - "CMT_PMV_LOGIC_OUTS22", - "CMT_PMV_LOGIC_OUTS23", - "CMT_PMV_LOGIC_OUTS3", - "CMT_PMV_LOGIC_OUTS4", - "CMT_PMV_LOGIC_OUTS5", - "CMT_PMV_LOGIC_OUTS6", - "CMT_PMV_LOGIC_OUTS7", - "CMT_PMV_LOGIC_OUTS8", - "CMT_PMV_LOGIC_OUTS9", - "CMT_PMV_MONITOR_N", - "CMT_PMV_MONITOR_P", - "CMT_PMV_NE2A0", - "CMT_PMV_NE2A1", - "CMT_PMV_NE2A2", - "CMT_PMV_NE2A3", - "CMT_PMV_NE4BEG0", - "CMT_PMV_NE4BEG1", - "CMT_PMV_NE4BEG2", - "CMT_PMV_NE4BEG3", - "CMT_PMV_NE4C0", - "CMT_PMV_NE4C1", - "CMT_PMV_NE4C2", - "CMT_PMV_NE4C3", - "CMT_PMV_NW2A0", - "CMT_PMV_NW2A1", - "CMT_PMV_NW2A2", - "CMT_PMV_NW2A3", - "CMT_PMV_NW4A0", - "CMT_PMV_NW4A1", - "CMT_PMV_NW4A2", - "CMT_PMV_NW4A3", - "CMT_PMV_NW4END0", - "CMT_PMV_NW4END1", - "CMT_PMV_NW4END2", - "CMT_PMV_NW4END3", - "CMT_PMV_SE2A0", - "CMT_PMV_SE2A1", - "CMT_PMV_SE2A2", - "CMT_PMV_SE2A3", - "CMT_PMV_SE4BEG0", - "CMT_PMV_SE4BEG1", - "CMT_PMV_SE4BEG2", - "CMT_PMV_SE4BEG3", - "CMT_PMV_SE4C0", - "CMT_PMV_SE4C1", - "CMT_PMV_SE4C2", - "CMT_PMV_SE4C3", - "CMT_PMV_SW2A0", - "CMT_PMV_SW2A1", - "CMT_PMV_SW2A2", - "CMT_PMV_SW2A3", - "CMT_PMV_SW4A0", - "CMT_PMV_SW4A1", - "CMT_PMV_SW4A2", - "CMT_PMV_SW4A3", - "CMT_PMV_SW4END0", - "CMT_PMV_SW4END1", - "CMT_PMV_SW4END2", - "CMT_PMV_SW4END3", - "CMT_PMV_WL1END0", - "CMT_PMV_WL1END1", - "CMT_PMV_WL1END2", - "CMT_PMV_WL1END3", - "CMT_PMV_WR1END0", - "CMT_PMV_WR1END1", - "CMT_PMV_WR1END2", - "CMT_PMV_WR1END3", - "CMT_PMV_WW2A0", - "CMT_PMV_WW2A1", - "CMT_PMV_WW2A2", - "CMT_PMV_WW2A3", - "CMT_PMV_WW2END0", - "CMT_PMV_WW2END1", - "CMT_PMV_WW2END2", - "CMT_PMV_WW2END3", - "CMT_PMV_WW4A0", - "CMT_PMV_WW4A1", - "CMT_PMV_WW4A2", - "CMT_PMV_WW4A3", - "CMT_PMV_WW4B0", - "CMT_PMV_WW4B1", - "CMT_PMV_WW4B2", - "CMT_PMV_WW4B3", - "CMT_PMV_WW4C0", - "CMT_PMV_WW4C1", - "CMT_PMV_WW4C2", - "CMT_PMV_WW4C3", - "CMT_PMV_WW4END0", - "CMT_PMV_WW4END1", - "CMT_PMV_WW4END2", - "CMT_PMV_WW4END3", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ] + "wires": { + "CMT_PMV_BYP0": null, + "CMT_PMV_BYP1": null, + "CMT_PMV_BYP2": null, + "CMT_PMV_BYP3": null, + "CMT_PMV_BYP4": null, + "CMT_PMV_BYP5": null, + "CMT_PMV_BYP6": null, + "CMT_PMV_BYP7": null, + "CMT_PMV_CLK0": null, + "CMT_PMV_CLK1": null, + "CMT_PMV_CTRL0": null, + "CMT_PMV_CTRL1": null, + "CMT_PMV_EE2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2BEG0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2BEG1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2BEG2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2BEG3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE4A0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4A1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4A2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4A3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4B0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4B1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4B2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4B3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4C0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4C1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4C2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4C3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG0": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG1": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG2": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG3": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG0": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG1": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG2": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG3": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_FAN0": null, + "CMT_PMV_FAN1": null, + "CMT_PMV_FAN2": null, + "CMT_PMV_FAN3": null, + "CMT_PMV_FAN4": null, + "CMT_PMV_FAN5": null, + "CMT_PMV_FAN6": null, + "CMT_PMV_FAN7": null, + "CMT_PMV_IMUX0": null, + "CMT_PMV_IMUX1": null, + "CMT_PMV_IMUX10": null, + "CMT_PMV_IMUX11": null, + "CMT_PMV_IMUX12": null, + "CMT_PMV_IMUX13": null, + "CMT_PMV_IMUX14": null, + "CMT_PMV_IMUX15": null, + "CMT_PMV_IMUX16": null, + "CMT_PMV_IMUX17": null, + "CMT_PMV_IMUX18": null, + "CMT_PMV_IMUX19": null, + "CMT_PMV_IMUX2": null, + "CMT_PMV_IMUX20": null, + "CMT_PMV_IMUX21": null, + "CMT_PMV_IMUX22": null, + "CMT_PMV_IMUX23": null, + "CMT_PMV_IMUX24": null, + "CMT_PMV_IMUX25": null, + "CMT_PMV_IMUX26": null, + "CMT_PMV_IMUX27": null, + "CMT_PMV_IMUX28": null, + "CMT_PMV_IMUX29": null, + "CMT_PMV_IMUX3": null, + "CMT_PMV_IMUX30": null, + "CMT_PMV_IMUX31": null, + "CMT_PMV_IMUX32": null, + "CMT_PMV_IMUX33": null, + "CMT_PMV_IMUX34": null, + "CMT_PMV_IMUX35": null, + "CMT_PMV_IMUX36": null, + "CMT_PMV_IMUX37": null, + "CMT_PMV_IMUX38": null, + "CMT_PMV_IMUX39": null, + "CMT_PMV_IMUX4": null, + "CMT_PMV_IMUX40": null, + "CMT_PMV_IMUX41": null, + "CMT_PMV_IMUX42": null, + "CMT_PMV_IMUX43": null, + "CMT_PMV_IMUX44": null, + "CMT_PMV_IMUX45": null, + "CMT_PMV_IMUX46": null, + "CMT_PMV_IMUX47": null, + "CMT_PMV_IMUX5": null, + "CMT_PMV_IMUX6": null, + "CMT_PMV_IMUX7": null, + "CMT_PMV_IMUX8": null, + "CMT_PMV_IMUX9": null, + "CMT_PMV_LH1": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH10": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH11": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH12": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH2": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH3": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH4": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH5": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH6": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH7": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH8": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH9": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LOGIC_OUTS0": null, + "CMT_PMV_LOGIC_OUTS1": null, + "CMT_PMV_LOGIC_OUTS10": null, + "CMT_PMV_LOGIC_OUTS11": null, + "CMT_PMV_LOGIC_OUTS12": null, + "CMT_PMV_LOGIC_OUTS13": null, + "CMT_PMV_LOGIC_OUTS14": null, + "CMT_PMV_LOGIC_OUTS15": null, + "CMT_PMV_LOGIC_OUTS16": null, + "CMT_PMV_LOGIC_OUTS17": null, + "CMT_PMV_LOGIC_OUTS18": null, + "CMT_PMV_LOGIC_OUTS19": null, + "CMT_PMV_LOGIC_OUTS2": null, + "CMT_PMV_LOGIC_OUTS20": null, + "CMT_PMV_LOGIC_OUTS21": null, + "CMT_PMV_LOGIC_OUTS22": null, + "CMT_PMV_LOGIC_OUTS23": null, + "CMT_PMV_LOGIC_OUTS3": null, + "CMT_PMV_LOGIC_OUTS4": null, + "CMT_PMV_LOGIC_OUTS5": null, + "CMT_PMV_LOGIC_OUTS6": null, + "CMT_PMV_LOGIC_OUTS7": null, + "CMT_PMV_LOGIC_OUTS8": null, + "CMT_PMV_LOGIC_OUTS9": null, + "CMT_PMV_MONITOR_N": null, + "CMT_PMV_MONITOR_P": null, + "CMT_PMV_NE2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NE2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NE2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NE2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4C0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4C1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4C2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4C3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NW2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NW2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NW2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NW4A0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4A1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4A2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4A3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4END0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4END1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4END2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4END3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SE2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SE2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SE2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4C0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4C1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4C2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4C3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SW2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SW2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SW2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SW4A0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4A1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4A2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4A3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4END0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4END1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4END2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4END3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WL1END0": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WL1END1": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WL1END2": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WL1END3": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WR1END0": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WR1END1": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WR1END2": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WR1END3": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WW2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2END0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2END1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2END2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2END3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW4A0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4A1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4A2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4A3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4B0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4B1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4B2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4B3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4C0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4C1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4C2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4C3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4END0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4END1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4END2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4END3": { + "cap": "78.000", + "res": "317.510" + }, + "L_TERM_INT_PHASER_TO_IO_ICLK": null, + "L_TERM_INT_PHASER_TO_IO_ICLKDIV": null, + "L_TERM_INT_PHASER_TO_IO_OCLK": null, + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90": null, + "L_TERM_INT_PHASER_TO_IO_OCLKDIV": null + } } diff --git a/kintex7/tile_type_CMT_PMV_L.json b/kintex7/tile_type_CMT_PMV_L.json index 4fa0775..ab8847a 100644 --- a/kintex7/tile_type_CMT_PMV_L.json +++ b/kintex7/tile_type_CMT_PMV_L.json @@ -2,229 +2,601 @@ "pips": {}, "sites": [], "tile_type": "CMT_PMV_L", - "wires": [ - "CMT_PMV_BYP0", - "CMT_PMV_BYP1", - "CMT_PMV_BYP2", - "CMT_PMV_BYP3", - "CMT_PMV_BYP4", - "CMT_PMV_BYP5", - "CMT_PMV_BYP6", - "CMT_PMV_BYP7", - "CMT_PMV_CLK0", - "CMT_PMV_CLK1", - "CMT_PMV_CTRL0", - "CMT_PMV_CTRL1", - "CMT_PMV_EE2A0", - "CMT_PMV_EE2A1", - "CMT_PMV_EE2A2", - "CMT_PMV_EE2A3", - "CMT_PMV_EE2BEG0", - "CMT_PMV_EE2BEG1", - "CMT_PMV_EE2BEG2", - "CMT_PMV_EE2BEG3", - "CMT_PMV_EE4A0", - "CMT_PMV_EE4A1", - "CMT_PMV_EE4A2", - "CMT_PMV_EE4A3", - "CMT_PMV_EE4B0", - "CMT_PMV_EE4B1", - "CMT_PMV_EE4B2", - "CMT_PMV_EE4B3", - "CMT_PMV_EE4BEG0", - "CMT_PMV_EE4BEG1", - "CMT_PMV_EE4BEG2", - "CMT_PMV_EE4BEG3", - "CMT_PMV_EE4C0", - "CMT_PMV_EE4C1", - "CMT_PMV_EE4C2", - "CMT_PMV_EE4C3", - "CMT_PMV_EL1BEG0", - "CMT_PMV_EL1BEG1", - "CMT_PMV_EL1BEG2", - "CMT_PMV_EL1BEG3", - "CMT_PMV_ER1BEG0", - "CMT_PMV_ER1BEG1", - "CMT_PMV_ER1BEG2", - "CMT_PMV_ER1BEG3", - "CMT_PMV_FAN0", - "CMT_PMV_FAN1", - "CMT_PMV_FAN2", - "CMT_PMV_FAN3", - "CMT_PMV_FAN4", - "CMT_PMV_FAN5", - "CMT_PMV_FAN6", - "CMT_PMV_FAN7", - "CMT_PMV_IMUX0", - "CMT_PMV_IMUX1", - "CMT_PMV_IMUX10", - "CMT_PMV_IMUX11", - "CMT_PMV_IMUX12", - "CMT_PMV_IMUX13", - "CMT_PMV_IMUX14", - "CMT_PMV_IMUX15", - "CMT_PMV_IMUX16", - "CMT_PMV_IMUX17", - "CMT_PMV_IMUX18", - "CMT_PMV_IMUX19", - "CMT_PMV_IMUX2", - "CMT_PMV_IMUX20", - "CMT_PMV_IMUX21", - "CMT_PMV_IMUX22", - "CMT_PMV_IMUX23", - "CMT_PMV_IMUX24", - "CMT_PMV_IMUX25", - "CMT_PMV_IMUX26", - "CMT_PMV_IMUX27", - "CMT_PMV_IMUX28", - "CMT_PMV_IMUX29", - "CMT_PMV_IMUX3", - "CMT_PMV_IMUX30", - "CMT_PMV_IMUX31", - "CMT_PMV_IMUX32", - "CMT_PMV_IMUX33", - "CMT_PMV_IMUX34", - "CMT_PMV_IMUX35", - "CMT_PMV_IMUX36", - "CMT_PMV_IMUX37", - "CMT_PMV_IMUX38", - "CMT_PMV_IMUX39", - "CMT_PMV_IMUX4", - "CMT_PMV_IMUX40", - "CMT_PMV_IMUX41", - "CMT_PMV_IMUX42", - "CMT_PMV_IMUX43", - "CMT_PMV_IMUX44", - "CMT_PMV_IMUX45", - "CMT_PMV_IMUX46", - "CMT_PMV_IMUX47", - "CMT_PMV_IMUX5", - "CMT_PMV_IMUX6", - "CMT_PMV_IMUX7", - "CMT_PMV_IMUX8", - "CMT_PMV_IMUX9", - "CMT_PMV_LH1", - "CMT_PMV_LH10", - "CMT_PMV_LH11", - "CMT_PMV_LH12", - "CMT_PMV_LH2", - "CMT_PMV_LH3", - "CMT_PMV_LH4", - "CMT_PMV_LH5", - "CMT_PMV_LH6", - "CMT_PMV_LH7", - "CMT_PMV_LH8", - "CMT_PMV_LH9", - "CMT_PMV_LOGIC_OUTS0", - "CMT_PMV_LOGIC_OUTS1", - "CMT_PMV_LOGIC_OUTS10", - "CMT_PMV_LOGIC_OUTS11", - "CMT_PMV_LOGIC_OUTS12", - "CMT_PMV_LOGIC_OUTS13", - "CMT_PMV_LOGIC_OUTS14", - "CMT_PMV_LOGIC_OUTS15", - "CMT_PMV_LOGIC_OUTS16", - "CMT_PMV_LOGIC_OUTS17", - "CMT_PMV_LOGIC_OUTS18", - "CMT_PMV_LOGIC_OUTS19", - "CMT_PMV_LOGIC_OUTS2", - "CMT_PMV_LOGIC_OUTS20", - "CMT_PMV_LOGIC_OUTS21", - "CMT_PMV_LOGIC_OUTS22", - "CMT_PMV_LOGIC_OUTS23", - "CMT_PMV_LOGIC_OUTS3", - "CMT_PMV_LOGIC_OUTS4", - "CMT_PMV_LOGIC_OUTS5", - "CMT_PMV_LOGIC_OUTS6", - "CMT_PMV_LOGIC_OUTS7", - "CMT_PMV_LOGIC_OUTS8", - "CMT_PMV_LOGIC_OUTS9", - "CMT_PMV_MONITOR_N", - "CMT_PMV_MONITOR_P", - "CMT_PMV_NE2A0", - "CMT_PMV_NE2A1", - "CMT_PMV_NE2A2", - "CMT_PMV_NE2A3", - "CMT_PMV_NE4BEG0", - "CMT_PMV_NE4BEG1", - "CMT_PMV_NE4BEG2", - "CMT_PMV_NE4BEG3", - "CMT_PMV_NE4C0", - "CMT_PMV_NE4C1", - "CMT_PMV_NE4C2", - "CMT_PMV_NE4C3", - "CMT_PMV_NW2A0", - "CMT_PMV_NW2A1", - "CMT_PMV_NW2A2", - "CMT_PMV_NW2A3", - "CMT_PMV_NW4A0", - "CMT_PMV_NW4A1", - "CMT_PMV_NW4A2", - "CMT_PMV_NW4A3", - "CMT_PMV_NW4END0", - "CMT_PMV_NW4END1", - "CMT_PMV_NW4END2", - "CMT_PMV_NW4END3", - "CMT_PMV_SE2A0", - "CMT_PMV_SE2A1", - "CMT_PMV_SE2A2", - "CMT_PMV_SE2A3", - "CMT_PMV_SE4BEG0", - "CMT_PMV_SE4BEG1", - "CMT_PMV_SE4BEG2", - "CMT_PMV_SE4BEG3", - "CMT_PMV_SE4C0", - "CMT_PMV_SE4C1", - "CMT_PMV_SE4C2", - "CMT_PMV_SE4C3", - "CMT_PMV_SW2A0", - "CMT_PMV_SW2A1", - "CMT_PMV_SW2A2", - "CMT_PMV_SW2A3", - "CMT_PMV_SW4A0", - "CMT_PMV_SW4A1", - "CMT_PMV_SW4A2", - "CMT_PMV_SW4A3", - "CMT_PMV_SW4END0", - "CMT_PMV_SW4END1", - "CMT_PMV_SW4END2", - "CMT_PMV_SW4END3", - "CMT_PMV_WL1END0", - "CMT_PMV_WL1END1", - "CMT_PMV_WL1END2", - "CMT_PMV_WL1END3", - "CMT_PMV_WR1END0", - "CMT_PMV_WR1END1", - "CMT_PMV_WR1END2", - "CMT_PMV_WR1END3", - "CMT_PMV_WW2A0", - "CMT_PMV_WW2A1", - "CMT_PMV_WW2A2", - "CMT_PMV_WW2A3", - "CMT_PMV_WW2END0", - "CMT_PMV_WW2END1", - "CMT_PMV_WW2END2", - "CMT_PMV_WW2END3", - "CMT_PMV_WW4A0", - "CMT_PMV_WW4A1", - "CMT_PMV_WW4A2", - "CMT_PMV_WW4A3", - "CMT_PMV_WW4B0", - "CMT_PMV_WW4B1", - "CMT_PMV_WW4B2", - "CMT_PMV_WW4B3", - "CMT_PMV_WW4C0", - "CMT_PMV_WW4C1", - "CMT_PMV_WW4C2", - "CMT_PMV_WW4C3", - "CMT_PMV_WW4END0", - "CMT_PMV_WW4END1", - "CMT_PMV_WW4END2", - "CMT_PMV_WW4END3", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV" - ] + "wires": { + "CMT_PMV_BYP0": null, + "CMT_PMV_BYP1": null, + "CMT_PMV_BYP2": null, + "CMT_PMV_BYP3": null, + "CMT_PMV_BYP4": null, + "CMT_PMV_BYP5": null, + "CMT_PMV_BYP6": null, + "CMT_PMV_BYP7": null, + "CMT_PMV_CLK0": null, + "CMT_PMV_CLK1": null, + "CMT_PMV_CTRL0": null, + "CMT_PMV_CTRL1": null, + "CMT_PMV_EE2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2BEG0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2BEG1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2BEG2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE2BEG3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_EE4A0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4A1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4A2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4A3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4B0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4B1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4B2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4B3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4BEG3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4C0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4C1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4C2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EE4C3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG0": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG1": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG2": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_EL1BEG3": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG0": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG1": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG2": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_ER1BEG3": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_FAN0": null, + "CMT_PMV_FAN1": null, + "CMT_PMV_FAN2": null, + "CMT_PMV_FAN3": null, + "CMT_PMV_FAN4": null, + "CMT_PMV_FAN5": null, + "CMT_PMV_FAN6": null, + "CMT_PMV_FAN7": null, + "CMT_PMV_IMUX0": null, + "CMT_PMV_IMUX1": null, + "CMT_PMV_IMUX10": null, + "CMT_PMV_IMUX11": null, + "CMT_PMV_IMUX12": null, + "CMT_PMV_IMUX13": null, + "CMT_PMV_IMUX14": null, + "CMT_PMV_IMUX15": null, + "CMT_PMV_IMUX16": null, + "CMT_PMV_IMUX17": null, + "CMT_PMV_IMUX18": null, + "CMT_PMV_IMUX19": null, + "CMT_PMV_IMUX2": null, + "CMT_PMV_IMUX20": null, + "CMT_PMV_IMUX21": null, + "CMT_PMV_IMUX22": null, + "CMT_PMV_IMUX23": null, + "CMT_PMV_IMUX24": null, + "CMT_PMV_IMUX25": null, + "CMT_PMV_IMUX26": null, + "CMT_PMV_IMUX27": null, + "CMT_PMV_IMUX28": null, + "CMT_PMV_IMUX29": null, + "CMT_PMV_IMUX3": null, + "CMT_PMV_IMUX30": null, + "CMT_PMV_IMUX31": null, + "CMT_PMV_IMUX32": null, + "CMT_PMV_IMUX33": null, + "CMT_PMV_IMUX34": null, + "CMT_PMV_IMUX35": null, + "CMT_PMV_IMUX36": null, + "CMT_PMV_IMUX37": null, + "CMT_PMV_IMUX38": null, + "CMT_PMV_IMUX39": null, + "CMT_PMV_IMUX4": null, + "CMT_PMV_IMUX40": null, + "CMT_PMV_IMUX41": null, + "CMT_PMV_IMUX42": null, + "CMT_PMV_IMUX43": null, + "CMT_PMV_IMUX44": null, + "CMT_PMV_IMUX45": null, + "CMT_PMV_IMUX46": null, + "CMT_PMV_IMUX47": null, + "CMT_PMV_IMUX5": null, + "CMT_PMV_IMUX6": null, + "CMT_PMV_IMUX7": null, + "CMT_PMV_IMUX8": null, + "CMT_PMV_IMUX9": null, + "CMT_PMV_LH1": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH10": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH11": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH12": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH2": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH3": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH4": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH5": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH6": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH7": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH8": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LH9": { + "cap": "60.260", + "res": "15.190" + }, + "CMT_PMV_LOGIC_OUTS0": null, + "CMT_PMV_LOGIC_OUTS1": null, + "CMT_PMV_LOGIC_OUTS10": null, + "CMT_PMV_LOGIC_OUTS11": null, + "CMT_PMV_LOGIC_OUTS12": null, + "CMT_PMV_LOGIC_OUTS13": null, + "CMT_PMV_LOGIC_OUTS14": null, + "CMT_PMV_LOGIC_OUTS15": null, + "CMT_PMV_LOGIC_OUTS16": null, + "CMT_PMV_LOGIC_OUTS17": null, + "CMT_PMV_LOGIC_OUTS18": null, + "CMT_PMV_LOGIC_OUTS19": null, + "CMT_PMV_LOGIC_OUTS2": null, + "CMT_PMV_LOGIC_OUTS20": null, + "CMT_PMV_LOGIC_OUTS21": null, + "CMT_PMV_LOGIC_OUTS22": null, + "CMT_PMV_LOGIC_OUTS23": null, + "CMT_PMV_LOGIC_OUTS3": null, + "CMT_PMV_LOGIC_OUTS4": null, + "CMT_PMV_LOGIC_OUTS5": null, + "CMT_PMV_LOGIC_OUTS6": null, + "CMT_PMV_LOGIC_OUTS7": null, + "CMT_PMV_LOGIC_OUTS8": null, + "CMT_PMV_LOGIC_OUTS9": null, + "CMT_PMV_MONITOR_N": null, + "CMT_PMV_MONITOR_P": null, + "CMT_PMV_NE2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NE2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NE2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NE2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4BEG3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4C0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4C1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4C2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NE4C3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NW2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NW2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NW2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_NW4A0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4A1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4A2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4A3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4END0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4END1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4END2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_NW4END3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SE2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SE2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SE2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4BEG3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4C0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4C1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4C2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SE4C3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SW2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SW2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SW2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_SW4A0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4A1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4A2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4A3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4END0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4END1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4END2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_SW4END3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WL1END0": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WL1END1": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WL1END2": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WL1END3": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WR1END0": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WR1END1": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WR1END2": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WR1END3": { + "cap": "82.000", + "res": "317.510" + }, + "CMT_PMV_WW2A0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2A1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2A2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2A3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2END0": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2END1": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2END2": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW2END3": { + "cap": "74.000", + "res": "317.510" + }, + "CMT_PMV_WW4A0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4A1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4A2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4A3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4B0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4B1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4B2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4B3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4C0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4C1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4C2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4C3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4END0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4END1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4END2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_PMV_WW4END3": { + "cap": "78.000", + "res": "317.510" + }, + "L_TERM_INT_PHASER_TO_IO_ICLK": null, + "L_TERM_INT_PHASER_TO_IO_ICLKDIV": null, + "L_TERM_INT_PHASER_TO_IO_OCLK": null, + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90": null, + "L_TERM_INT_PHASER_TO_IO_OCLKDIV": null + } } diff --git a/kintex7/tile_type_CMT_TOP_L_LOWER_B.json b/kintex7/tile_type_CMT_TOP_L_LOWER_B.json index 55db716..6d69b26 100644 --- a/kintex7/tile_type_CMT_TOP_L_LOWER_B.json +++ b/kintex7/tile_type_CMT_TOP_L_LOWER_B.json @@ -2,1395 +2,5514 @@ "pips": { "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_LR_LOWER_B_CLKFBOUT2IN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_CLKFBOUT2IN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_MMCM11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_MMCM11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUT->>CMT_L_LOWER_B_CLK_PERF3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBOUTB->>CMT_L_LOWER_B_CLK_MMCM12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_MMCM12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKINSTOPPED->>CMT_TOP_LOGIC_OUTS_L_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_MMCM0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_MMCM0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>CMT_L_LOWER_B_CLK_PERF3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0->>MMCMOUT_CLK_FREQ_BB_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT0B->>CMT_L_LOWER_B_CLK_MMCM1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_MMCM1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0B" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_MMCM2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_MMCM2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1" }, "CMT_TOP_L_LOWER_B.CMT_LR_LOWER_B_MMCM_CLKOUT1->>CMT_L_LOWER_B_CLK_PERF1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_PERF1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": 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"can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_DI13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX38_0" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX39_0->>CMT_LR_LOWER_B_MMCM_DI15": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_DI15", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX39_0" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX3_0->>CMT_LR_LOWER_B_MMCM_DI6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_DI6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX3_0" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX3_1->>CMT_LR_LOWER_B_MMCM_DADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX3_1" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX44_1->>CMT_LR_LOWER_B_MMCM_DADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_DADDR6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX44_1" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX47_1->>CMT_LR_LOWER_B_MMCM_PWRDWN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_PWRDWN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX47_1" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX4_0->>CMT_LR_LOWER_B_MMCM_DI8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_DI8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX4_0" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX5_0->>CMT_LR_LOWER_B_MMCM_DI10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_DI10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX5_0" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX6_0->>CMT_LR_LOWER_B_MMCM_DI12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_DI12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX6_0" }, "CMT_TOP_L_LOWER_B.CMT_TOP_IMUX7_0->>CMT_LR_LOWER_B_MMCM_DI14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_DI14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_IMUX7_0" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS0->>CMT_L_LOWER_B_CLK_FREQ_BB3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS0" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS1->>CMT_L_LOWER_B_CLK_FREQ_BB2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS1" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS2->>CMT_L_LOWER_B_CLK_FREQ_BB1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS2" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_NS3->>CMT_L_LOWER_B_CLK_FREQ_BB0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_LOWER_B_CLK_FREQ_BB0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS3" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS0", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF0_NS" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF1_NS<<->>MMCM_CLK_FREQ_BB_NS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS1", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF1_NS" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF2_NS<<->>MMCM_CLK_FREQ_BB_NS2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS2", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF2_NS" }, "CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS<<->>MMCM_CLK_FREQ_BB_NS3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS3", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF3_NS" } }, @@ -1399,172 +5518,1666 @@ "name": "X0Y0", "prefix": "MMCME2_ADV", "site_pins": { - "CLKFBIN": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "CLKFBOUT": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "CLKFBOUTB": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", - "CLKFBSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", - "CLKIN1": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "CLKIN2": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "CLKINSEL": "CMT_LR_LOWER_B_MMCM_CLKINSEL", - "CLKINSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", - "CLKOUT0": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "CLKOUT0B": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", - "CLKOUT1": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "CLKOUT1B": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "CLKOUT2": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "CLKOUT2B": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "CLKOUT3": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "CLKOUT3B": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "CLKOUT4": "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "CLKOUT5": "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "CLKOUT6": "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "DADDR0": "CMT_LR_LOWER_B_MMCM_DADDR0", - "DADDR1": "CMT_LR_LOWER_B_MMCM_DADDR1", - "DADDR2": "CMT_LR_LOWER_B_MMCM_DADDR2", - "DADDR3": "CMT_LR_LOWER_B_MMCM_DADDR3", - "DADDR4": "CMT_LR_LOWER_B_MMCM_DADDR4", - "DADDR5": "CMT_LR_LOWER_B_MMCM_DADDR5", - "DADDR6": "CMT_LR_LOWER_B_MMCM_DADDR6", - "DCLK": "CMT_LR_LOWER_B_MMCM_DCLK", - "DEN": "CMT_LR_LOWER_B_MMCM_DEN", - "DI0": "CMT_LR_LOWER_B_MMCM_DI0", - "DI1": "CMT_LR_LOWER_B_MMCM_DI1", - "DI10": "CMT_LR_LOWER_B_MMCM_DI10", - "DI11": "CMT_LR_LOWER_B_MMCM_DI11", - "DI12": "CMT_LR_LOWER_B_MMCM_DI12", - "DI13": "CMT_LR_LOWER_B_MMCM_DI13", - "DI14": "CMT_LR_LOWER_B_MMCM_DI14", - "DI15": "CMT_LR_LOWER_B_MMCM_DI15", - "DI2": "CMT_LR_LOWER_B_MMCM_DI2", - "DI3": "CMT_LR_LOWER_B_MMCM_DI3", - "DI4": "CMT_LR_LOWER_B_MMCM_DI4", - "DI5": "CMT_LR_LOWER_B_MMCM_DI5", - "DI6": "CMT_LR_LOWER_B_MMCM_DI6", - "DI7": "CMT_LR_LOWER_B_MMCM_DI7", - "DI8": "CMT_LR_LOWER_B_MMCM_DI8", - "DI9": "CMT_LR_LOWER_B_MMCM_DI9", - "DO0": "CMT_LR_LOWER_B_MMCM_DO0", - "DO1": "CMT_LR_LOWER_B_MMCM_DO1", - "DO10": "CMT_LR_LOWER_B_MMCM_DO10", - "DO11": "CMT_LR_LOWER_B_MMCM_DO11", - "DO12": "CMT_LR_LOWER_B_MMCM_DO12", - "DO13": "CMT_LR_LOWER_B_MMCM_DO13", - "DO14": "CMT_LR_LOWER_B_MMCM_DO14", - "DO15": "CMT_LR_LOWER_B_MMCM_DO15", - "DO2": "CMT_LR_LOWER_B_MMCM_DO2", - "DO3": "CMT_LR_LOWER_B_MMCM_DO3", - "DO4": "CMT_LR_LOWER_B_MMCM_DO4", - "DO5": "CMT_LR_LOWER_B_MMCM_DO5", - "DO6": "CMT_LR_LOWER_B_MMCM_DO6", - "DO7": "CMT_LR_LOWER_B_MMCM_DO7", - "DO8": "CMT_LR_LOWER_B_MMCM_DO8", - "DO9": "CMT_LR_LOWER_B_MMCM_DO9", - "DRDY": "CMT_LR_LOWER_B_MMCM_DRDY", - "DWE": "CMT_LR_LOWER_B_MMCM_DWE", - "LOCKED": "CMT_LR_LOWER_B_MMCM_LOCKED", - "PSCLK": "CMT_LR_LOWER_B_MMCM_PSCLK", - "PSDONE": "CMT_LR_LOWER_B_MMCM_PSDONE", - "PSEN": "CMT_LR_LOWER_B_MMCM_PSEN", - "PSINCDEC": "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "PWRDWN": "CMT_LR_LOWER_B_MMCM_PWRDWN", - "RST": "CMT_LR_LOWER_B_MMCM_RST", - "TESTIN0": "CMT_LR_LOWER_B_MMCM_TESTIN0", - "TESTIN1": "CMT_LR_LOWER_B_MMCM_TESTIN1", - "TESTIN10": "CMT_LR_LOWER_B_MMCM_TESTIN10", - "TESTIN11": "CMT_LR_LOWER_B_MMCM_TESTIN11", - "TESTIN12": "CMT_LR_LOWER_B_MMCM_TESTIN12", - "TESTIN13": "CMT_LR_LOWER_B_MMCM_TESTIN13", - "TESTIN14": "CMT_LR_LOWER_B_MMCM_TESTIN14", - "TESTIN15": "CMT_LR_LOWER_B_MMCM_TESTIN15", - "TESTIN16": "CMT_LR_LOWER_B_MMCM_TESTIN16", - "TESTIN17": "CMT_LR_LOWER_B_MMCM_TESTIN17", - "TESTIN18": "CMT_LR_LOWER_B_MMCM_TESTIN18", - "TESTIN19": "CMT_LR_LOWER_B_MMCM_TESTIN19", - "TESTIN2": "CMT_LR_LOWER_B_MMCM_TESTIN2", - "TESTIN20": "CMT_LR_LOWER_B_MMCM_TESTIN20", - "TESTIN21": "CMT_LR_LOWER_B_MMCM_TESTIN21", - "TESTIN22": "CMT_LR_LOWER_B_MMCM_TESTIN22", - "TESTIN23": "CMT_LR_LOWER_B_MMCM_TESTIN23", - "TESTIN24": "CMT_LR_LOWER_B_MMCM_TESTIN24", - "TESTIN25": "CMT_LR_LOWER_B_MMCM_TESTIN25", - "TESTIN26": "CMT_LR_LOWER_B_MMCM_TESTIN26", - "TESTIN27": "CMT_LR_LOWER_B_MMCM_TESTIN27", - "TESTIN28": "CMT_LR_LOWER_B_MMCM_TESTIN28", - "TESTIN29": "CMT_LR_LOWER_B_MMCM_TESTIN29", - "TESTIN3": "CMT_LR_LOWER_B_MMCM_TESTIN3", - "TESTIN30": "CMT_LR_LOWER_B_MMCM_TESTIN30", - "TESTIN31": "CMT_LR_LOWER_B_MMCM_TESTIN31", - "TESTIN4": "CMT_LR_LOWER_B_MMCM_TESTIN4", - "TESTIN5": "CMT_LR_LOWER_B_MMCM_TESTIN5", - "TESTIN6": "CMT_LR_LOWER_B_MMCM_TESTIN6", - "TESTIN7": "CMT_LR_LOWER_B_MMCM_TESTIN7", - "TESTIN8": "CMT_LR_LOWER_B_MMCM_TESTIN8", - "TESTIN9": "CMT_LR_LOWER_B_MMCM_TESTIN9", - "TESTOUT0": "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "TESTOUT1": "CMT_LR_LOWER_B_MMCM_TESTOUT1", - "TESTOUT10": "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "TESTOUT11": "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "TESTOUT12": "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "TESTOUT13": "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "TESTOUT14": "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "TESTOUT15": "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "TESTOUT16": "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "TESTOUT17": "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "TESTOUT18": "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "TESTOUT19": "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "TESTOUT2": "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "TESTOUT20": "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "TESTOUT21": "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "TESTOUT22": "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "TESTOUT23": "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "TESTOUT24": "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "TESTOUT25": "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "TESTOUT26": "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "TESTOUT27": "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "TESTOUT28": "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "TESTOUT29": "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "TESTOUT3": "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "TESTOUT30": "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "TESTOUT31": "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "TESTOUT32": "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "TESTOUT33": "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "TESTOUT34": "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "TESTOUT35": "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "TESTOUT36": "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "TESTOUT37": "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "TESTOUT38": "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "TESTOUT39": "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "TESTOUT4": "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "TESTOUT40": "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "TESTOUT41": "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "TESTOUT42": "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "TESTOUT43": "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "TESTOUT44": "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "TESTOUT45": "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "TESTOUT46": "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "TESTOUT47": "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "TESTOUT48": "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "TESTOUT49": "CMT_LR_LOWER_B_MMCM_TESTOUT49", - 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"CMT_LR_LOWER_B_MMCM_CLKOUT3", - "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "CMT_LR_LOWER_B_MMCM_DADDR0", - "CMT_LR_LOWER_B_MMCM_DADDR1", - "CMT_LR_LOWER_B_MMCM_DADDR2", - "CMT_LR_LOWER_B_MMCM_DADDR3", - "CMT_LR_LOWER_B_MMCM_DADDR4", - "CMT_LR_LOWER_B_MMCM_DADDR5", - "CMT_LR_LOWER_B_MMCM_DADDR6", - "CMT_LR_LOWER_B_MMCM_DCLK", - "CMT_LR_LOWER_B_MMCM_DEN", - "CMT_LR_LOWER_B_MMCM_DI0", - "CMT_LR_LOWER_B_MMCM_DI1", - "CMT_LR_LOWER_B_MMCM_DI10", - "CMT_LR_LOWER_B_MMCM_DI11", - "CMT_LR_LOWER_B_MMCM_DI12", - "CMT_LR_LOWER_B_MMCM_DI13", - "CMT_LR_LOWER_B_MMCM_DI14", - "CMT_LR_LOWER_B_MMCM_DI15", - "CMT_LR_LOWER_B_MMCM_DI2", - "CMT_LR_LOWER_B_MMCM_DI3", - "CMT_LR_LOWER_B_MMCM_DI4", - "CMT_LR_LOWER_B_MMCM_DI5", - "CMT_LR_LOWER_B_MMCM_DI6", - "CMT_LR_LOWER_B_MMCM_DI7", - "CMT_LR_LOWER_B_MMCM_DI8", - "CMT_LR_LOWER_B_MMCM_DI9", - "CMT_LR_LOWER_B_MMCM_DO0", - "CMT_LR_LOWER_B_MMCM_DO1", - "CMT_LR_LOWER_B_MMCM_DO10", - "CMT_LR_LOWER_B_MMCM_DO11", - "CMT_LR_LOWER_B_MMCM_DO12", - "CMT_LR_LOWER_B_MMCM_DO13", - "CMT_LR_LOWER_B_MMCM_DO14", - "CMT_LR_LOWER_B_MMCM_DO15", - "CMT_LR_LOWER_B_MMCM_DO2", - "CMT_LR_LOWER_B_MMCM_DO3", - "CMT_LR_LOWER_B_MMCM_DO4", - "CMT_LR_LOWER_B_MMCM_DO5", - "CMT_LR_LOWER_B_MMCM_DO6", - "CMT_LR_LOWER_B_MMCM_DO7", - "CMT_LR_LOWER_B_MMCM_DO8", - "CMT_LR_LOWER_B_MMCM_DO9", - "CMT_LR_LOWER_B_MMCM_DRDY", - "CMT_LR_LOWER_B_MMCM_DWE", - "CMT_LR_LOWER_B_MMCM_LOCKED", - "CMT_LR_LOWER_B_MMCM_PSCLK", - "CMT_LR_LOWER_B_MMCM_PSDONE", - "CMT_LR_LOWER_B_MMCM_PSEN", - "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "CMT_LR_LOWER_B_MMCM_PWRDWN", - "CMT_LR_LOWER_B_MMCM_RST", - "CMT_LR_LOWER_B_MMCM_TESTIN0", - "CMT_LR_LOWER_B_MMCM_TESTIN1", - "CMT_LR_LOWER_B_MMCM_TESTIN10", - "CMT_LR_LOWER_B_MMCM_TESTIN11", - "CMT_LR_LOWER_B_MMCM_TESTIN12", - "CMT_LR_LOWER_B_MMCM_TESTIN13", - "CMT_LR_LOWER_B_MMCM_TESTIN14", - "CMT_LR_LOWER_B_MMCM_TESTIN15", - "CMT_LR_LOWER_B_MMCM_TESTIN16", - "CMT_LR_LOWER_B_MMCM_TESTIN17", - "CMT_LR_LOWER_B_MMCM_TESTIN18", - "CMT_LR_LOWER_B_MMCM_TESTIN19", - "CMT_LR_LOWER_B_MMCM_TESTIN2", - "CMT_LR_LOWER_B_MMCM_TESTIN20", - "CMT_LR_LOWER_B_MMCM_TESTIN21", - "CMT_LR_LOWER_B_MMCM_TESTIN22", - "CMT_LR_LOWER_B_MMCM_TESTIN23", - "CMT_LR_LOWER_B_MMCM_TESTIN24", - "CMT_LR_LOWER_B_MMCM_TESTIN25", - "CMT_LR_LOWER_B_MMCM_TESTIN26", - "CMT_LR_LOWER_B_MMCM_TESTIN27", - "CMT_LR_LOWER_B_MMCM_TESTIN28", - "CMT_LR_LOWER_B_MMCM_TESTIN29", - "CMT_LR_LOWER_B_MMCM_TESTIN3", - "CMT_LR_LOWER_B_MMCM_TESTIN30", - "CMT_LR_LOWER_B_MMCM_TESTIN31", - "CMT_LR_LOWER_B_MMCM_TESTIN4", - "CMT_LR_LOWER_B_MMCM_TESTIN5", - "CMT_LR_LOWER_B_MMCM_TESTIN6", - "CMT_LR_LOWER_B_MMCM_TESTIN7", - "CMT_LR_LOWER_B_MMCM_TESTIN8", - "CMT_LR_LOWER_B_MMCM_TESTIN9", - "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "CMT_LR_LOWER_B_MMCM_TESTOUT1", - "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "CMT_LR_LOWER_B_MMCM_TESTOUT49", - "CMT_LR_LOWER_B_MMCM_TESTOUT5", - "CMT_LR_LOWER_B_MMCM_TESTOUT50", - "CMT_LR_LOWER_B_MMCM_TESTOUT51", - "CMT_LR_LOWER_B_MMCM_TESTOUT52", - "CMT_LR_LOWER_B_MMCM_TESTOUT53", - "CMT_LR_LOWER_B_MMCM_TESTOUT54", - "CMT_LR_LOWER_B_MMCM_TESTOUT55", - "CMT_LR_LOWER_B_MMCM_TESTOUT56", - "CMT_LR_LOWER_B_MMCM_TESTOUT57", - "CMT_LR_LOWER_B_MMCM_TESTOUT58", - "CMT_LR_LOWER_B_MMCM_TESTOUT59", - "CMT_LR_LOWER_B_MMCM_TESTOUT6", - "CMT_LR_LOWER_B_MMCM_TESTOUT60", - "CMT_LR_LOWER_B_MMCM_TESTOUT61", - "CMT_LR_LOWER_B_MMCM_TESTOUT62", - "CMT_LR_LOWER_B_MMCM_TESTOUT63", - "CMT_LR_LOWER_B_MMCM_TESTOUT7", - "CMT_LR_LOWER_B_MMCM_TESTOUT8", - "CMT_LR_LOWER_B_MMCM_TESTOUT9", - "CMT_LR_LOWER_B_MMCM_TMUXOUT", - "CMT_L_LOWER_B_CLK_FREQ_BB0", - "CMT_L_LOWER_B_CLK_FREQ_BB1", - "CMT_L_LOWER_B_CLK_FREQ_BB2", - "CMT_L_LOWER_B_CLK_FREQ_BB3", - "CMT_L_LOWER_B_CLK_IN1_HCLK", - "CMT_L_LOWER_B_CLK_IN1_INT", - "CMT_L_LOWER_B_CLK_IN2_HCLK", - "CMT_L_LOWER_B_CLK_IN2_INT", - "CMT_L_LOWER_B_CLK_IN3_HCLK", - "CMT_L_LOWER_B_CLK_IN3_INT", - "CMT_L_LOWER_B_CLK_MMCM0", - "CMT_L_LOWER_B_CLK_MMCM1", - "CMT_L_LOWER_B_CLK_MMCM10", - "CMT_L_LOWER_B_CLK_MMCM11", - "CMT_L_LOWER_B_CLK_MMCM12", - "CMT_L_LOWER_B_CLK_MMCM13", - "CMT_L_LOWER_B_CLK_MMCM2", - "CMT_L_LOWER_B_CLK_MMCM3", - "CMT_L_LOWER_B_CLK_MMCM4", - "CMT_L_LOWER_B_CLK_MMCM5", - "CMT_L_LOWER_B_CLK_MMCM6", - "CMT_L_LOWER_B_CLK_MMCM7", - "CMT_L_LOWER_B_CLK_MMCM8", - "CMT_L_LOWER_B_CLK_MMCM9", - "CMT_L_LOWER_B_CLK_PERF0", - "CMT_L_LOWER_B_CLK_PERF1", - "CMT_L_LOWER_B_CLK_PERF2", - "CMT_L_LOWER_B_CLK_PERF3", - "CMT_MMCM_A_RDCLK_TOFIFO", - "CMT_MMCM_A_RDEN_TOFIFO", - "CMT_MMCM_A_WRCLK_TOFIFO", - "CMT_MMCM_A_WREN_TOFIFO", - "CMT_MMCM_DQS_TO_PHASERA", - "CMT_MMCM_PHASERA_CTSBUS0", - "CMT_MMCM_PHASERA_CTSBUS1", - "CMT_MMCM_PHASERA_DQSBUS0", - "CMT_MMCM_PHASERA_DQSBUS1", - "CMT_MMCM_PHASERA_DTSBUS0", - "CMT_MMCM_PHASERA_DTSBUS1", - "CMT_MMCM_PHASERREF0", - "CMT_MMCM_PHASERREF1", - "CMT_MMCM_PHASERREF_ABOVE0", - "CMT_MMCM_PHASERREF_ABOVE1", - "CMT_MMCM_PHASERREF_BELOW0", - "CMT_MMCM_PHASERREF_BELOW1", - "CMT_MMCM_PHASER_IN_A_ICLK", - "CMT_MMCM_PHASER_IN_A_ICLKDIV", - "CMT_MMCM_PHASER_IN_B_ICLK", - "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "CMT_MMCM_PHASER_OUT_A_OCLK", - "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", - "CMT_MMCM_PHASER_OUT_A_OCLKDIV", - "CMT_MMCM_PHASER_OUT_B_OCLK", - "CMT_MMCM_PHASER_OUT_B_OCLK1X_90", - "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "CMT_MMCM_PHYCTRL_SYNC_BB_DN", - "CMT_MMCM_PHYCTRL_SYNC_BB_UP", - "CMT_PHASER_A_ICLKDIV_TOIOI", - "CMT_PHASER_A_ICLK_TOIOI", - "CMT_PHASER_A_OCLK90_TOIOI", - "CMT_PHASER_A_OCLKDIV_TOIOI", - "CMT_PHASER_A_OCLK_TOIOI", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_BLOCK_OUTS_L_B0_12", - "CMT_TOP_BLOCK_OUTS_L_B0_13", - "CMT_TOP_BLOCK_OUTS_L_B0_14", - "CMT_TOP_BLOCK_OUTS_L_B0_15", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_12", - "CMT_TOP_BLOCK_OUTS_L_B1_13", - "CMT_TOP_BLOCK_OUTS_L_B1_14", - "CMT_TOP_BLOCK_OUTS_L_B1_15", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_BLOCK_OUTS_L_B2_12", - "CMT_TOP_BLOCK_OUTS_L_B2_13", - "CMT_TOP_BLOCK_OUTS_L_B2_14", - "CMT_TOP_BLOCK_OUTS_L_B2_15", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_12", - "CMT_TOP_BLOCK_OUTS_L_B3_13", - "CMT_TOP_BLOCK_OUTS_L_B3_14", - "CMT_TOP_BLOCK_OUTS_L_B3_15", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_BYP0_11", - "CMT_TOP_BYP0_12", - "CMT_TOP_BYP0_13", - "CMT_TOP_BYP0_14", - "CMT_TOP_BYP0_15", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_10", - "CMT_TOP_BYP1_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_BYP1_13", - "CMT_TOP_BYP1_14", - "CMT_TOP_BYP1_15", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP1_9", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_10", - "CMT_TOP_BYP2_11", - "CMT_TOP_BYP2_12", - "CMT_TOP_BYP2_13", - "CMT_TOP_BYP2_14", - "CMT_TOP_BYP2_15", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_10", - "CMT_TOP_BYP3_11", - "CMT_TOP_BYP3_12", - "CMT_TOP_BYP3_13", - "CMT_TOP_BYP3_14", - "CMT_TOP_BYP3_15", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP3_9", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_10", - "CMT_TOP_BYP4_11", - "CMT_TOP_BYP4_12", - "CMT_TOP_BYP4_13", - "CMT_TOP_BYP4_14", - "CMT_TOP_BYP4_15", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP4_9", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_10", - "CMT_TOP_BYP5_11", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP5_13", - "CMT_TOP_BYP5_14", - "CMT_TOP_BYP5_15", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP5_9", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_10", - "CMT_TOP_BYP6_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_BYP6_13", - "CMT_TOP_BYP6_14", - "CMT_TOP_BYP6_15", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP6_9", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_10", - "CMT_TOP_BYP7_11", - "CMT_TOP_BYP7_12", - "CMT_TOP_BYP7_13", - "CMT_TOP_BYP7_14", - "CMT_TOP_BYP7_15", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_BYP7_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_CLK0_12", - "CMT_TOP_CLK0_13", - "CMT_TOP_CLK0_14", - "CMT_TOP_CLK0_15", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK0_9", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_10", - "CMT_TOP_CLK1_11", - "CMT_TOP_CLK1_12", - "CMT_TOP_CLK1_13", - "CMT_TOP_CLK1_14", - "CMT_TOP_CLK1_15", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CLK1_9", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CTRL0_12", - "CMT_TOP_CTRL0_13", - "CMT_TOP_CTRL0_14", - "CMT_TOP_CTRL0_15", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL0_9", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_CTRL1_11", - "CMT_TOP_CTRL1_12", - "CMT_TOP_CTRL1_13", - "CMT_TOP_CTRL1_14", - "CMT_TOP_CTRL1_15", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_CTRL1_9", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_EE2A0_12", - "CMT_TOP_EE2A0_13", - "CMT_TOP_EE2A0_14", - "CMT_TOP_EE2A0_15", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A0_9", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_10", - "CMT_TOP_EE2A1_11", - "CMT_TOP_EE2A1_12", - "CMT_TOP_EE2A1_13", - "CMT_TOP_EE2A1_14", - "CMT_TOP_EE2A1_15", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A1_9", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_10", - "CMT_TOP_EE2A2_11", - "CMT_TOP_EE2A2_12", - "CMT_TOP_EE2A2_13", - "CMT_TOP_EE2A2_14", - "CMT_TOP_EE2A2_15", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A2_9", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_10", - "CMT_TOP_EE2A3_11", - "CMT_TOP_EE2A3_12", - "CMT_TOP_EE2A3_13", - "CMT_TOP_EE2A3_14", - "CMT_TOP_EE2A3_15", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_EE2BEG0_13", - "CMT_TOP_EE2BEG0_14", - "CMT_TOP_EE2BEG0_15", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_EE2BEG1_13", - "CMT_TOP_EE2BEG1_14", - "CMT_TOP_EE2BEG1_15", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_EE2BEG2_13", - "CMT_TOP_EE2BEG2_14", - "CMT_TOP_EE2BEG2_15", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_EE2BEG3_13", - "CMT_TOP_EE2BEG3_14", - "CMT_TOP_EE2BEG3_15", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_10", - "CMT_TOP_EE4A0_11", - "CMT_TOP_EE4A0_12", - "CMT_TOP_EE4A0_13", - "CMT_TOP_EE4A0_14", - "CMT_TOP_EE4A0_15", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A0_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_EE4A1_11", - "CMT_TOP_EE4A1_12", - "CMT_TOP_EE4A1_13", - "CMT_TOP_EE4A1_14", - "CMT_TOP_EE4A1_15", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A1_9", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_10", - "CMT_TOP_EE4A2_11", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EE4A2_13", - "CMT_TOP_EE4A2_14", - "CMT_TOP_EE4A2_15", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A2_9", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_EE4A3_11", - "CMT_TOP_EE4A3_12", - "CMT_TOP_EE4A3_13", - "CMT_TOP_EE4A3_14", - "CMT_TOP_EE4A3_15", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_10", - "CMT_TOP_EE4B0_11", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4B0_13", - "CMT_TOP_EE4B0_14", - "CMT_TOP_EE4B0_15", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B0_9", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_10", - "CMT_TOP_EE4B1_11", - "CMT_TOP_EE4B1_12", - "CMT_TOP_EE4B1_13", - "CMT_TOP_EE4B1_14", - "CMT_TOP_EE4B1_15", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B1_9", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_10", - "CMT_TOP_EE4B2_11", - "CMT_TOP_EE4B2_12", - "CMT_TOP_EE4B2_13", - "CMT_TOP_EE4B2_14", - "CMT_TOP_EE4B2_15", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B2_9", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_10", - "CMT_TOP_EE4B3_11", - "CMT_TOP_EE4B3_12", - "CMT_TOP_EE4B3_13", - "CMT_TOP_EE4B3_14", - "CMT_TOP_EE4B3_15", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4B3_9", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_EE4BEG0_13", - "CMT_TOP_EE4BEG0_14", - "CMT_TOP_EE4BEG0_15", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_EE4BEG1_13", - "CMT_TOP_EE4BEG1_14", - "CMT_TOP_EE4BEG1_15", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_EE4BEG2_12", - "CMT_TOP_EE4BEG2_13", - "CMT_TOP_EE4BEG2_14", - "CMT_TOP_EE4BEG2_15", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_EE4BEG3_13", - "CMT_TOP_EE4BEG3_14", - "CMT_TOP_EE4BEG3_15", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_10", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EE4C0_12", - "CMT_TOP_EE4C0_13", - "CMT_TOP_EE4C0_14", - "CMT_TOP_EE4C0_15", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C0_9", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_10", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EE4C1_12", - "CMT_TOP_EE4C1_13", - "CMT_TOP_EE4C1_14", - "CMT_TOP_EE4C1_15", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_EE4C2_12", - "CMT_TOP_EE4C2_13", - "CMT_TOP_EE4C2_14", - "CMT_TOP_EE4C2_15", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C2_9", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_EE4C3_11", - "CMT_TOP_EE4C3_12", - "CMT_TOP_EE4C3_13", - "CMT_TOP_EE4C3_14", - "CMT_TOP_EE4C3_15", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EE4C3_9", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_EL1BEG0_13", - "CMT_TOP_EL1BEG0_14", - "CMT_TOP_EL1BEG0_15", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_EL1BEG1_12", - "CMT_TOP_EL1BEG1_13", - "CMT_TOP_EL1BEG1_14", - "CMT_TOP_EL1BEG1_15", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_EL1BEG2_13", - "CMT_TOP_EL1BEG2_14", - "CMT_TOP_EL1BEG2_15", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_EL1BEG3_13", - "CMT_TOP_EL1BEG3_14", - "CMT_TOP_EL1BEG3_15", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_ER1BEG0_13", - "CMT_TOP_ER1BEG0_14", - "CMT_TOP_ER1BEG0_15", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_ER1BEG1_13", - "CMT_TOP_ER1BEG1_14", - "CMT_TOP_ER1BEG1_15", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_ER1BEG2_13", - "CMT_TOP_ER1BEG2_14", - "CMT_TOP_ER1BEG2_15", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_ER1BEG3_13", - "CMT_TOP_ER1BEG3_14", - "CMT_TOP_ER1BEG3_15", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_10", - "CMT_TOP_FAN0_11", - "CMT_TOP_FAN0_12", - "CMT_TOP_FAN0_13", - "CMT_TOP_FAN0_14", - "CMT_TOP_FAN0_15", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN0_9", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_10", - "CMT_TOP_FAN1_11", - "CMT_TOP_FAN1_12", - "CMT_TOP_FAN1_13", - "CMT_TOP_FAN1_14", - "CMT_TOP_FAN1_15", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN1_9", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_10", - "CMT_TOP_FAN2_11", - "CMT_TOP_FAN2_12", - "CMT_TOP_FAN2_13", - "CMT_TOP_FAN2_14", - "CMT_TOP_FAN2_15", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN2_9", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_FAN3_12", - "CMT_TOP_FAN3_13", - "CMT_TOP_FAN3_14", - "CMT_TOP_FAN3_15", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN3_9", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_10", - "CMT_TOP_FAN4_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_FAN4_13", - "CMT_TOP_FAN4_14", - "CMT_TOP_FAN4_15", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN4_9", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_10", - "CMT_TOP_FAN5_11", - "CMT_TOP_FAN5_12", - "CMT_TOP_FAN5_13", - "CMT_TOP_FAN5_14", - "CMT_TOP_FAN5_15", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN5_9", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_10", - "CMT_TOP_FAN6_11", - "CMT_TOP_FAN6_12", - "CMT_TOP_FAN6_13", - "CMT_TOP_FAN6_14", - "CMT_TOP_FAN6_15", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN6_9", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_FAN7_11", - "CMT_TOP_FAN7_12", - "CMT_TOP_FAN7_13", - "CMT_TOP_FAN7_14", - "CMT_TOP_FAN7_15", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_FAN7_9", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_ICLKDIV_13", - "CMT_TOP_ICLKDIV_14", - "CMT_TOP_ICLKDIV_15", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_ICLK_11", - "CMT_TOP_ICLK_12", - "CMT_TOP_ICLK_13", - "CMT_TOP_ICLK_14", - "CMT_TOP_ICLK_15", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_10", - "CMT_TOP_IMUX0_11", - "CMT_TOP_IMUX0_12", - "CMT_TOP_IMUX0_13", - "CMT_TOP_IMUX0_14", - "CMT_TOP_IMUX0_15", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_10", - "CMT_TOP_IMUX10_11", - "CMT_TOP_IMUX10_12", - "CMT_TOP_IMUX10_13", - "CMT_TOP_IMUX10_14", - "CMT_TOP_IMUX10_15", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX10_4", - "CMT_TOP_IMUX10_5", - "CMT_TOP_IMUX10_6", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_IMUX10_9", - "CMT_TOP_IMUX11_0", - "CMT_TOP_IMUX11_1", - "CMT_TOP_IMUX11_10", - "CMT_TOP_IMUX11_11", - "CMT_TOP_IMUX11_12", - "CMT_TOP_IMUX11_13", - "CMT_TOP_IMUX11_14", - "CMT_TOP_IMUX11_15", - "CMT_TOP_IMUX11_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX11_4", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_IMUX11_9", - "CMT_TOP_IMUX12_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX12_10", - "CMT_TOP_IMUX12_11", - "CMT_TOP_IMUX12_12", - "CMT_TOP_IMUX12_13", - "CMT_TOP_IMUX12_14", - "CMT_TOP_IMUX12_15", - "CMT_TOP_IMUX12_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX12_6", - "CMT_TOP_IMUX12_7", - "CMT_TOP_IMUX12_8", - "CMT_TOP_IMUX12_9", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX13_10", - "CMT_TOP_IMUX13_11", - "CMT_TOP_IMUX13_12", - "CMT_TOP_IMUX13_13", - "CMT_TOP_IMUX13_14", - "CMT_TOP_IMUX13_15", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX13_3", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX13_8", - "CMT_TOP_IMUX13_9", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX14_10", - "CMT_TOP_IMUX14_11", - "CMT_TOP_IMUX14_12", - "CMT_TOP_IMUX14_13", - "CMT_TOP_IMUX14_14", - "CMT_TOP_IMUX14_15", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX14_3", - "CMT_TOP_IMUX14_4", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX15_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_IMUX15_10", - "CMT_TOP_IMUX15_11", - "CMT_TOP_IMUX15_12", - "CMT_TOP_IMUX15_13", - "CMT_TOP_IMUX15_14", - "CMT_TOP_IMUX15_15", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX15_4", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_IMUX15_9", - "CMT_TOP_IMUX16_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX16_10", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX16_12", - "CMT_TOP_IMUX16_13", - "CMT_TOP_IMUX16_14", - "CMT_TOP_IMUX16_15", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX16_5", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX16_7", - "CMT_TOP_IMUX16_8", - "CMT_TOP_IMUX16_9", - "CMT_TOP_IMUX17_0", - "CMT_TOP_IMUX17_1", - "CMT_TOP_IMUX17_10", - "CMT_TOP_IMUX17_11", - "CMT_TOP_IMUX17_12", - "CMT_TOP_IMUX17_13", - "CMT_TOP_IMUX17_14", - "CMT_TOP_IMUX17_15", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX17_3", - "CMT_TOP_IMUX17_4", - "CMT_TOP_IMUX17_5", - "CMT_TOP_IMUX17_6", - "CMT_TOP_IMUX17_7", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX17_9", - "CMT_TOP_IMUX18_0", - "CMT_TOP_IMUX18_1", - "CMT_TOP_IMUX18_10", - "CMT_TOP_IMUX18_11", - "CMT_TOP_IMUX18_12", - "CMT_TOP_IMUX18_13", - "CMT_TOP_IMUX18_14", - "CMT_TOP_IMUX18_15", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX18_3", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX18_5", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX18_7", - "CMT_TOP_IMUX18_8", - "CMT_TOP_IMUX18_9", - "CMT_TOP_IMUX19_0", - "CMT_TOP_IMUX19_1", - "CMT_TOP_IMUX19_10", - "CMT_TOP_IMUX19_11", - "CMT_TOP_IMUX19_12", - "CMT_TOP_IMUX19_13", - "CMT_TOP_IMUX19_14", - "CMT_TOP_IMUX19_15", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX19_3", - "CMT_TOP_IMUX19_4", - "CMT_TOP_IMUX19_5", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX19_7", - "CMT_TOP_IMUX19_8", - "CMT_TOP_IMUX19_9", - "CMT_TOP_IMUX1_0", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX1_10", - "CMT_TOP_IMUX1_11", - "CMT_TOP_IMUX1_12", - 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"CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX22_11", - "CMT_TOP_IMUX22_12", - "CMT_TOP_IMUX22_13", - "CMT_TOP_IMUX22_14", - "CMT_TOP_IMUX22_15", - "CMT_TOP_IMUX22_2", - "CMT_TOP_IMUX22_3", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX22_7", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX22_9", - "CMT_TOP_IMUX23_0", - "CMT_TOP_IMUX23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_IMUX23_11", - "CMT_TOP_IMUX23_12", - "CMT_TOP_IMUX23_13", - "CMT_TOP_IMUX23_14", - "CMT_TOP_IMUX23_15", - "CMT_TOP_IMUX23_2", - "CMT_TOP_IMUX23_3", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX23_7", - "CMT_TOP_IMUX23_8", - "CMT_TOP_IMUX23_9", - "CMT_TOP_IMUX24_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_IMUX24_10", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX24_12", - "CMT_TOP_IMUX24_13", - "CMT_TOP_IMUX24_14", - "CMT_TOP_IMUX24_15", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_IMUX24_4", - "CMT_TOP_IMUX24_5", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX24_7", - 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"CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX6_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_10", - "CMT_TOP_IMUX7_11", - "CMT_TOP_IMUX7_12", - "CMT_TOP_IMUX7_13", - "CMT_TOP_IMUX7_14", - "CMT_TOP_IMUX7_15", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX7_9", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_IMUX8_12", - "CMT_TOP_IMUX8_13", - "CMT_TOP_IMUX8_14", - "CMT_TOP_IMUX8_15", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_10", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX9_13", - "CMT_TOP_IMUX9_14", - "CMT_TOP_IMUX9_15", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX9_9", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_10", - "CMT_TOP_LH10_11", - "CMT_TOP_LH10_12", - "CMT_TOP_LH10_13", - "CMT_TOP_LH10_14", - "CMT_TOP_LH10_15", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH10_9", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_10", - "CMT_TOP_LH11_11", - "CMT_TOP_LH11_12", - "CMT_TOP_LH11_13", - "CMT_TOP_LH11_14", - "CMT_TOP_LH11_15", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH11_9", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_10", - "CMT_TOP_LH12_11", - "CMT_TOP_LH12_12", - "CMT_TOP_LH12_13", - "CMT_TOP_LH12_14", - "CMT_TOP_LH12_15", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH12_9", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_10", - "CMT_TOP_LH1_11", - "CMT_TOP_LH1_12", - "CMT_TOP_LH1_13", - "CMT_TOP_LH1_14", - "CMT_TOP_LH1_15", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH1_9", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_10", - "CMT_TOP_LH2_11", - "CMT_TOP_LH2_12", - "CMT_TOP_LH2_13", - "CMT_TOP_LH2_14", - "CMT_TOP_LH2_15", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH2_9", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_10", - "CMT_TOP_LH3_11", - "CMT_TOP_LH3_12", - "CMT_TOP_LH3_13", - "CMT_TOP_LH3_14", - "CMT_TOP_LH3_15", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH3_9", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_10", - "CMT_TOP_LH4_11", - "CMT_TOP_LH4_12", - "CMT_TOP_LH4_13", - "CMT_TOP_LH4_14", - "CMT_TOP_LH4_15", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH4_9", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_10", - "CMT_TOP_LH5_11", - "CMT_TOP_LH5_12", - "CMT_TOP_LH5_13", - "CMT_TOP_LH5_14", - "CMT_TOP_LH5_15", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH5_9", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_10", - "CMT_TOP_LH6_11", - "CMT_TOP_LH6_12", - "CMT_TOP_LH6_13", - "CMT_TOP_LH6_14", - "CMT_TOP_LH6_15", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH6_9", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_10", - "CMT_TOP_LH7_11", - "CMT_TOP_LH7_12", - "CMT_TOP_LH7_13", - "CMT_TOP_LH7_14", - "CMT_TOP_LH7_15", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH7_9", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_10", - "CMT_TOP_LH8_11", - "CMT_TOP_LH8_12", - "CMT_TOP_LH8_13", - "CMT_TOP_LH8_14", - "CMT_TOP_LH8_15", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH8_9", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_10", - "CMT_TOP_LH9_11", - "CMT_TOP_LH9_12", - "CMT_TOP_LH9_13", - "CMT_TOP_LH9_14", - "CMT_TOP_LH9_15", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LH9_9", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_LOGIC_OUTS_L_B0_13", - "CMT_TOP_LOGIC_OUTS_L_B0_14", - "CMT_TOP_LOGIC_OUTS_L_B0_15", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_LOGIC_OUTS_L_B10_13", - "CMT_TOP_LOGIC_OUTS_L_B10_14", - "CMT_TOP_LOGIC_OUTS_L_B10_15", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_LOGIC_OUTS_L_B11_13", - "CMT_TOP_LOGIC_OUTS_L_B11_14", - "CMT_TOP_LOGIC_OUTS_L_B11_15", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_LOGIC_OUTS_L_B12_13", - "CMT_TOP_LOGIC_OUTS_L_B12_14", - "CMT_TOP_LOGIC_OUTS_L_B12_15", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_10", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_LOGIC_OUTS_L_B13_13", - "CMT_TOP_LOGIC_OUTS_L_B13_14", - "CMT_TOP_LOGIC_OUTS_L_B13_15", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_TOP_LOGIC_OUTS_L_B14_13", - "CMT_TOP_LOGIC_OUTS_L_B14_14", - "CMT_TOP_LOGIC_OUTS_L_B14_15", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_LOGIC_OUTS_L_B15_13", - "CMT_TOP_LOGIC_OUTS_L_B15_14", - "CMT_TOP_LOGIC_OUTS_L_B15_15", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_LOGIC_OUTS_L_B16_13", - "CMT_TOP_LOGIC_OUTS_L_B16_14", - "CMT_TOP_LOGIC_OUTS_L_B16_15", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B17_13", - "CMT_TOP_LOGIC_OUTS_L_B17_14", - "CMT_TOP_LOGIC_OUTS_L_B17_15", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_LOGIC_OUTS_L_B18_13", - "CMT_TOP_LOGIC_OUTS_L_B18_14", - "CMT_TOP_LOGIC_OUTS_L_B18_15", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_LOGIC_OUTS_L_B19_13", - "CMT_TOP_LOGIC_OUTS_L_B19_14", - "CMT_TOP_LOGIC_OUTS_L_B19_15", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_LOGIC_OUTS_L_B1_13", - "CMT_TOP_LOGIC_OUTS_L_B1_14", - "CMT_TOP_LOGIC_OUTS_L_B1_15", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_LOGIC_OUTS_L_B20_13", - "CMT_TOP_LOGIC_OUTS_L_B20_14", - "CMT_TOP_LOGIC_OUTS_L_B20_15", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_LOGIC_OUTS_L_B21_13", - "CMT_TOP_LOGIC_OUTS_L_B21_14", - "CMT_TOP_LOGIC_OUTS_L_B21_15", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_LOGIC_OUTS_L_B22_13", - "CMT_TOP_LOGIC_OUTS_L_B22_14", - "CMT_TOP_LOGIC_OUTS_L_B22_15", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B23_13", - "CMT_TOP_LOGIC_OUTS_L_B23_14", - "CMT_TOP_LOGIC_OUTS_L_B23_15", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_LOGIC_OUTS_L_B2_13", - "CMT_TOP_LOGIC_OUTS_L_B2_14", - "CMT_TOP_LOGIC_OUTS_L_B2_15", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B3_13", - "CMT_TOP_LOGIC_OUTS_L_B3_14", - "CMT_TOP_LOGIC_OUTS_L_B3_15", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_LOGIC_OUTS_L_B4_13", - "CMT_TOP_LOGIC_OUTS_L_B4_14", - "CMT_TOP_LOGIC_OUTS_L_B4_15", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_LOGIC_OUTS_L_B5_13", - "CMT_TOP_LOGIC_OUTS_L_B5_14", - "CMT_TOP_LOGIC_OUTS_L_B5_15", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_LOGIC_OUTS_L_B6_13", - "CMT_TOP_LOGIC_OUTS_L_B6_14", - "CMT_TOP_LOGIC_OUTS_L_B6_15", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_LOGIC_OUTS_L_B7_13", - "CMT_TOP_LOGIC_OUTS_L_B7_14", - "CMT_TOP_LOGIC_OUTS_L_B7_15", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_LOGIC_OUTS_L_B8_13", - "CMT_TOP_LOGIC_OUTS_L_B8_14", - "CMT_TOP_LOGIC_OUTS_L_B8_15", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_LOGIC_OUTS_L_B9_13", - "CMT_TOP_LOGIC_OUTS_L_B9_14", - "CMT_TOP_LOGIC_OUTS_L_B9_15", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_MONITOR_N_12", - "CMT_TOP_MONITOR_N_13", - "CMT_TOP_MONITOR_N_14", - "CMT_TOP_MONITOR_N_15", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_MONITOR_P_13", - "CMT_TOP_MONITOR_P_14", - "CMT_TOP_MONITOR_P_15", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_10", - "CMT_TOP_NE2A0_11", - "CMT_TOP_NE2A0_12", - "CMT_TOP_NE2A0_13", - "CMT_TOP_NE2A0_14", - "CMT_TOP_NE2A0_15", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A0_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_10", - "CMT_TOP_NE2A1_11", - "CMT_TOP_NE2A1_12", - "CMT_TOP_NE2A1_13", - "CMT_TOP_NE2A1_14", - "CMT_TOP_NE2A1_15", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_10", - "CMT_TOP_NE2A2_11", - "CMT_TOP_NE2A2_12", - "CMT_TOP_NE2A2_13", - "CMT_TOP_NE2A2_14", - "CMT_TOP_NE2A2_15", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A2_9", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_10", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NE2A3_12", - "CMT_TOP_NE2A3_13", - "CMT_TOP_NE2A3_14", - "CMT_TOP_NE2A3_15", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_NE4BEG0_13", - "CMT_TOP_NE4BEG0_14", - "CMT_TOP_NE4BEG0_15", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_NE4BEG1_13", - "CMT_TOP_NE4BEG1_14", - "CMT_TOP_NE4BEG1_15", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_NE4BEG2_13", - "CMT_TOP_NE4BEG2_14", - "CMT_TOP_NE4BEG2_15", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_NE4BEG3_13", - "CMT_TOP_NE4BEG3_14", - "CMT_TOP_NE4BEG3_15", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_10", - "CMT_TOP_NE4C0_11", - "CMT_TOP_NE4C0_12", - "CMT_TOP_NE4C0_13", - "CMT_TOP_NE4C0_14", - "CMT_TOP_NE4C0_15", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_9", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_NE4C1_11", - "CMT_TOP_NE4C1_12", - "CMT_TOP_NE4C1_13", - "CMT_TOP_NE4C1_14", - "CMT_TOP_NE4C1_15", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C1_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_10", - "CMT_TOP_NE4C2_11", - "CMT_TOP_NE4C2_12", - "CMT_TOP_NE4C2_13", - "CMT_TOP_NE4C2_14", - "CMT_TOP_NE4C2_15", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C2_9", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_10", - "CMT_TOP_NE4C3_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_NE4C3_13", - "CMT_TOP_NE4C3_14", - "CMT_TOP_NE4C3_15", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NE4C3_9", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_10", - "CMT_TOP_NW2A0_11", - "CMT_TOP_NW2A0_12", - "CMT_TOP_NW2A0_13", - "CMT_TOP_NW2A0_14", - "CMT_TOP_NW2A0_15", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A0_9", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_10", - "CMT_TOP_NW2A1_11", - "CMT_TOP_NW2A1_12", - "CMT_TOP_NW2A1_13", - "CMT_TOP_NW2A1_14", - "CMT_TOP_NW2A1_15", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_10", - "CMT_TOP_NW2A2_11", - "CMT_TOP_NW2A2_12", - "CMT_TOP_NW2A2_13", - "CMT_TOP_NW2A2_14", - "CMT_TOP_NW2A2_15", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A2_9", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW2A3_11", - "CMT_TOP_NW2A3_12", - "CMT_TOP_NW2A3_13", - "CMT_TOP_NW2A3_14", - "CMT_TOP_NW2A3_15", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW2A3_9", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_10", - "CMT_TOP_NW4A0_11", - "CMT_TOP_NW4A0_12", - "CMT_TOP_NW4A0_13", - "CMT_TOP_NW4A0_14", - "CMT_TOP_NW4A0_15", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_10", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A1_12", - "CMT_TOP_NW4A1_13", - "CMT_TOP_NW4A1_14", - "CMT_TOP_NW4A1_15", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A1_9", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW4A2_11", - "CMT_TOP_NW4A2_12", - "CMT_TOP_NW4A2_13", - "CMT_TOP_NW4A2_14", - "CMT_TOP_NW4A2_15", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A2_9", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_10", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4A3_12", - "CMT_TOP_NW4A3_13", - "CMT_TOP_NW4A3_14", - "CMT_TOP_NW4A3_15", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_10", - "CMT_TOP_NW4END0_11", - "CMT_TOP_NW4END0_12", - "CMT_TOP_NW4END0_13", - "CMT_TOP_NW4END0_14", - "CMT_TOP_NW4END0_15", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END0_9", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_10", - "CMT_TOP_NW4END1_11", - "CMT_TOP_NW4END1_12", - "CMT_TOP_NW4END1_13", - "CMT_TOP_NW4END1_14", - "CMT_TOP_NW4END1_15", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END1_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_10", - "CMT_TOP_NW4END2_11", - "CMT_TOP_NW4END2_12", - "CMT_TOP_NW4END2_13", - "CMT_TOP_NW4END2_14", - "CMT_TOP_NW4END2_15", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END2_9", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4END3_11", - "CMT_TOP_NW4END3_12", - "CMT_TOP_NW4END3_13", - "CMT_TOP_NW4END3_14", - "CMT_TOP_NW4END3_15", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_NW4END3_9", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_OCLK1X_90_13", - "CMT_TOP_OCLK1X_90_14", - "CMT_TOP_OCLK1X_90_15", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_OCLKDIV_13", - "CMT_TOP_OCLKDIV_14", - "CMT_TOP_OCLKDIV_15", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_10", - "CMT_TOP_OCLK_11", - "CMT_TOP_OCLK_12", - "CMT_TOP_OCLK_13", - "CMT_TOP_OCLK_14", - "CMT_TOP_OCLK_15", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_OCLK_9", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_10", - "CMT_TOP_SE2A0_11", - "CMT_TOP_SE2A0_12", - "CMT_TOP_SE2A0_13", - "CMT_TOP_SE2A0_14", - "CMT_TOP_SE2A0_15", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A0_9", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_10", - "CMT_TOP_SE2A1_11", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE2A1_13", - "CMT_TOP_SE2A1_14", - "CMT_TOP_SE2A1_15", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A1_9", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_10", - "CMT_TOP_SE2A2_11", - "CMT_TOP_SE2A2_12", - "CMT_TOP_SE2A2_13", - "CMT_TOP_SE2A2_14", - "CMT_TOP_SE2A2_15", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_10", - "CMT_TOP_SE2A3_11", - "CMT_TOP_SE2A3_12", - "CMT_TOP_SE2A3_13", - "CMT_TOP_SE2A3_14", - "CMT_TOP_SE2A3_15", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE2A3_9", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_SE4BEG0_12", - "CMT_TOP_SE4BEG0_13", - "CMT_TOP_SE4BEG0_14", - "CMT_TOP_SE4BEG0_15", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_SE4BEG1_13", - "CMT_TOP_SE4BEG1_14", - "CMT_TOP_SE4BEG1_15", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SE4BEG2_12", - "CMT_TOP_SE4BEG2_13", - "CMT_TOP_SE4BEG2_14", - "CMT_TOP_SE4BEG2_15", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG3_12", - "CMT_TOP_SE4BEG3_13", - "CMT_TOP_SE4BEG3_14", - "CMT_TOP_SE4BEG3_15", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_10", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE4C0_12", - "CMT_TOP_SE4C0_13", - "CMT_TOP_SE4C0_14", - "CMT_TOP_SE4C0_15", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C0_9", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_10", - "CMT_TOP_SE4C1_11", - "CMT_TOP_SE4C1_12", - "CMT_TOP_SE4C1_13", - "CMT_TOP_SE4C1_14", - "CMT_TOP_SE4C1_15", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C1_9", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_10", - "CMT_TOP_SE4C2_11", - "CMT_TOP_SE4C2_12", - "CMT_TOP_SE4C2_13", - "CMT_TOP_SE4C2_14", - "CMT_TOP_SE4C2_15", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C2_9", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_10", - "CMT_TOP_SE4C3_11", - "CMT_TOP_SE4C3_12", - "CMT_TOP_SE4C3_13", - "CMT_TOP_SE4C3_14", - "CMT_TOP_SE4C3_15", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SE4C3_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SW2A0_11", - "CMT_TOP_SW2A0_12", - "CMT_TOP_SW2A0_13", - "CMT_TOP_SW2A0_14", - "CMT_TOP_SW2A0_15", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A0_9", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_10", - "CMT_TOP_SW2A1_11", - "CMT_TOP_SW2A1_12", - "CMT_TOP_SW2A1_13", - "CMT_TOP_SW2A1_14", - "CMT_TOP_SW2A1_15", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A1_9", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_10", - "CMT_TOP_SW2A2_11", - "CMT_TOP_SW2A2_12", - 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"CMT_TOP_WL1END3_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END0_11", - "CMT_TOP_WR1END0_12", - "CMT_TOP_WR1END0_13", - "CMT_TOP_WR1END0_14", - "CMT_TOP_WR1END0_15", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_WR1END1_12", - "CMT_TOP_WR1END1_13", - "CMT_TOP_WR1END1_14", - "CMT_TOP_WR1END1_15", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END1_9", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_10", - "CMT_TOP_WR1END2_11", - "CMT_TOP_WR1END2_12", - "CMT_TOP_WR1END2_13", - "CMT_TOP_WR1END2_14", - "CMT_TOP_WR1END2_15", - "CMT_TOP_WR1END2_2", - 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"CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_10", - "CMT_TOP_WW2END3_11", - "CMT_TOP_WW2END3_12", - "CMT_TOP_WW2END3_13", - "CMT_TOP_WW2END3_14", - "CMT_TOP_WW2END3_15", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW2END3_9", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_10", - "CMT_TOP_WW4A0_11", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4A0_13", - "CMT_TOP_WW4A0_14", - "CMT_TOP_WW4A0_15", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_10", - "CMT_TOP_WW4A1_11", - "CMT_TOP_WW4A1_12", - "CMT_TOP_WW4A1_13", - "CMT_TOP_WW4A1_14", - "CMT_TOP_WW4A1_15", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_10", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WW4A2_12", - "CMT_TOP_WW4A2_13", - "CMT_TOP_WW4A2_14", - "CMT_TOP_WW4A2_15", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A2_9", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_10", - "CMT_TOP_WW4A3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_WW4A3_13", - "CMT_TOP_WW4A3_14", - "CMT_TOP_WW4A3_15", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4A3_9", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_10", - "CMT_TOP_WW4B0_11", - "CMT_TOP_WW4B0_12", - "CMT_TOP_WW4B0_13", - "CMT_TOP_WW4B0_14", - "CMT_TOP_WW4B0_15", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_9", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_10", - "CMT_TOP_WW4B1_11", - "CMT_TOP_WW4B1_12", - "CMT_TOP_WW4B1_13", - "CMT_TOP_WW4B1_14", - "CMT_TOP_WW4B1_15", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_10", - "CMT_TOP_WW4B2_11", - "CMT_TOP_WW4B2_12", - "CMT_TOP_WW4B2_13", - "CMT_TOP_WW4B2_14", - "CMT_TOP_WW4B2_15", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_10", - "CMT_TOP_WW4B3_11", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4B3_13", - "CMT_TOP_WW4B3_14", - "CMT_TOP_WW4B3_15", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4B3_9", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_10", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4C0_12", - "CMT_TOP_WW4C0_13", - "CMT_TOP_WW4C0_14", - "CMT_TOP_WW4C0_15", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C0_9", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_WW4C1_12", - "CMT_TOP_WW4C1_13", - "CMT_TOP_WW4C1_14", - "CMT_TOP_WW4C1_15", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C1_9", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_10", - "CMT_TOP_WW4C2_11", - "CMT_TOP_WW4C2_12", - "CMT_TOP_WW4C2_13", - "CMT_TOP_WW4C2_14", - "CMT_TOP_WW4C2_15", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C2_9", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_WW4C3_12", - "CMT_TOP_WW4C3_13", - "CMT_TOP_WW4C3_14", - "CMT_TOP_WW4C3_15", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4C3_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_WW4END0_12", - "CMT_TOP_WW4END0_13", - "CMT_TOP_WW4END0_14", - "CMT_TOP_WW4END0_15", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END0_9", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_10", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WW4END1_12", - "CMT_TOP_WW4END1_13", - "CMT_TOP_WW4END1_14", - "CMT_TOP_WW4END1_15", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END1_9", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_WW4END2_12", - "CMT_TOP_WW4END2_13", - "CMT_TOP_WW4END2_14", - "CMT_TOP_WW4END2_15", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END2_9", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_10", - "CMT_TOP_WW4END3_11", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WW4END3_13", - "CMT_TOP_WW4END3_14", - "CMT_TOP_WW4END3_15", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4END3_9", - "MMCMOUT_CLK_FREQ_BB_0", - "MMCMOUT_CLK_FREQ_BB_1", - "MMCMOUT_CLK_FREQ_BB_2", - "MMCMOUT_CLK_FREQ_BB_3", - "MMCM_CLK_FREQ_BB_NS0", - "MMCM_CLK_FREQ_BB_NS1", - "MMCM_CLK_FREQ_BB_NS2", - "MMCM_CLK_FREQ_BB_NS3", - "MMCM_CLK_FREQ_BB_REBUF0_NS", - "MMCM_CLK_FREQ_BB_REBUF1_NS", - "MMCM_CLK_FREQ_BB_REBUF2_NS", - "MMCM_CLK_FREQ_BB_REBUF3_NS" - ] + "wires": { + "CMT_LR_LOWER_B_CLKFBOUT2IN": null, + "CMT_LR_LOWER_B_MMCM_CLKFBIN": null, + "CMT_LR_LOWER_B_MMCM_CLKFBOUT": null, + "CMT_LR_LOWER_B_MMCM_CLKFBOUTB": null, + "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED": null, + "CMT_LR_LOWER_B_MMCM_CLKIN1": null, + "CMT_LR_LOWER_B_MMCM_CLKIN2": null, + "CMT_LR_LOWER_B_MMCM_CLKINSEL": null, + "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT0": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT0B": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT1": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT1B": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT2": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT2B": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT3": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT3B": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT4": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT5": null, + "CMT_LR_LOWER_B_MMCM_CLKOUT6": null, + "CMT_LR_LOWER_B_MMCM_DADDR0": null, + "CMT_LR_LOWER_B_MMCM_DADDR1": null, + "CMT_LR_LOWER_B_MMCM_DADDR2": null, + "CMT_LR_LOWER_B_MMCM_DADDR3": null, + "CMT_LR_LOWER_B_MMCM_DADDR4": null, + "CMT_LR_LOWER_B_MMCM_DADDR5": null, + "CMT_LR_LOWER_B_MMCM_DADDR6": null, + "CMT_LR_LOWER_B_MMCM_DCLK": null, + "CMT_LR_LOWER_B_MMCM_DEN": null, + "CMT_LR_LOWER_B_MMCM_DI0": null, + "CMT_LR_LOWER_B_MMCM_DI1": null, + "CMT_LR_LOWER_B_MMCM_DI10": null, + "CMT_LR_LOWER_B_MMCM_DI11": null, + "CMT_LR_LOWER_B_MMCM_DI12": null, + "CMT_LR_LOWER_B_MMCM_DI13": null, + "CMT_LR_LOWER_B_MMCM_DI14": null, + "CMT_LR_LOWER_B_MMCM_DI15": null, + "CMT_LR_LOWER_B_MMCM_DI2": null, + "CMT_LR_LOWER_B_MMCM_DI3": null, + "CMT_LR_LOWER_B_MMCM_DI4": null, + "CMT_LR_LOWER_B_MMCM_DI5": null, + "CMT_LR_LOWER_B_MMCM_DI6": null, + "CMT_LR_LOWER_B_MMCM_DI7": null, + "CMT_LR_LOWER_B_MMCM_DI8": null, + "CMT_LR_LOWER_B_MMCM_DI9": null, + "CMT_LR_LOWER_B_MMCM_DO0": null, + "CMT_LR_LOWER_B_MMCM_DO1": null, + "CMT_LR_LOWER_B_MMCM_DO10": null, + "CMT_LR_LOWER_B_MMCM_DO11": null, + "CMT_LR_LOWER_B_MMCM_DO12": null, + "CMT_LR_LOWER_B_MMCM_DO13": null, + "CMT_LR_LOWER_B_MMCM_DO14": null, + "CMT_LR_LOWER_B_MMCM_DO15": null, + "CMT_LR_LOWER_B_MMCM_DO2": null, + "CMT_LR_LOWER_B_MMCM_DO3": null, + "CMT_LR_LOWER_B_MMCM_DO4": null, + "CMT_LR_LOWER_B_MMCM_DO5": null, + "CMT_LR_LOWER_B_MMCM_DO6": null, + "CMT_LR_LOWER_B_MMCM_DO7": null, + "CMT_LR_LOWER_B_MMCM_DO8": null, + "CMT_LR_LOWER_B_MMCM_DO9": null, + "CMT_LR_LOWER_B_MMCM_DRDY": null, + "CMT_LR_LOWER_B_MMCM_DWE": null, + "CMT_LR_LOWER_B_MMCM_LOCKED": null, + "CMT_LR_LOWER_B_MMCM_PSCLK": null, + "CMT_LR_LOWER_B_MMCM_PSDONE": null, + "CMT_LR_LOWER_B_MMCM_PSEN": null, + "CMT_LR_LOWER_B_MMCM_PSINCDEC": null, + "CMT_LR_LOWER_B_MMCM_PWRDWN": null, + "CMT_LR_LOWER_B_MMCM_RST": null, + "CMT_LR_LOWER_B_MMCM_TESTIN0": null, + "CMT_LR_LOWER_B_MMCM_TESTIN1": null, + "CMT_LR_LOWER_B_MMCM_TESTIN10": null, + "CMT_LR_LOWER_B_MMCM_TESTIN11": null, + "CMT_LR_LOWER_B_MMCM_TESTIN12": null, + "CMT_LR_LOWER_B_MMCM_TESTIN13": null, + "CMT_LR_LOWER_B_MMCM_TESTIN14": null, + "CMT_LR_LOWER_B_MMCM_TESTIN15": null, + "CMT_LR_LOWER_B_MMCM_TESTIN16": null, + "CMT_LR_LOWER_B_MMCM_TESTIN17": null, + "CMT_LR_LOWER_B_MMCM_TESTIN18": null, + "CMT_LR_LOWER_B_MMCM_TESTIN19": null, + "CMT_LR_LOWER_B_MMCM_TESTIN2": null, + "CMT_LR_LOWER_B_MMCM_TESTIN20": null, + "CMT_LR_LOWER_B_MMCM_TESTIN21": null, + "CMT_LR_LOWER_B_MMCM_TESTIN22": null, + "CMT_LR_LOWER_B_MMCM_TESTIN23": null, + "CMT_LR_LOWER_B_MMCM_TESTIN24": null, + "CMT_LR_LOWER_B_MMCM_TESTIN25": null, + "CMT_LR_LOWER_B_MMCM_TESTIN26": null, + "CMT_LR_LOWER_B_MMCM_TESTIN27": null, + "CMT_LR_LOWER_B_MMCM_TESTIN28": null, + "CMT_LR_LOWER_B_MMCM_TESTIN29": null, + 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null, + "CMT_LR_LOWER_B_MMCM_TESTOUT23": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT24": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT25": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT26": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT27": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT28": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT29": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT3": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT30": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT31": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT32": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT33": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT34": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT35": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT36": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT37": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT38": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT39": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT4": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT40": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT41": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT42": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT43": null, + "CMT_LR_LOWER_B_MMCM_TESTOUT44": null, + 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"res": "317.510" + }, + "CMT_TOP_WW4END1_15": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END1_2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END1_3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END1_4": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END1_5": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END1_6": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END1_7": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END1_8": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END1_9": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_10": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_11": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_12": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_13": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_14": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_15": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_4": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_5": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_6": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_7": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_8": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_9": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_10": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_11": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_12": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_13": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_14": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_15": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_4": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_5": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_6": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_7": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_8": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_9": { + "cap": "78.000", + "res": "317.510" + }, + "MMCMOUT_CLK_FREQ_BB_0": null, + "MMCMOUT_CLK_FREQ_BB_1": null, + "MMCMOUT_CLK_FREQ_BB_2": null, + "MMCMOUT_CLK_FREQ_BB_3": null, + "MMCM_CLK_FREQ_BB_NS0": null, + "MMCM_CLK_FREQ_BB_NS1": null, + "MMCM_CLK_FREQ_BB_NS2": null, + "MMCM_CLK_FREQ_BB_NS3": null, + "MMCM_CLK_FREQ_BB_REBUF0_NS": null, + "MMCM_CLK_FREQ_BB_REBUF1_NS": null, + "MMCM_CLK_FREQ_BB_REBUF2_NS": null, + "MMCM_CLK_FREQ_BB_REBUF3_NS": null + } } diff --git a/kintex7/tile_type_CMT_TOP_L_LOWER_T.json b/kintex7/tile_type_CMT_TOP_L_LOWER_T.json index 1484003..5312791 100644 --- a/kintex7/tile_type_CMT_TOP_L_LOWER_T.json +++ b/kintex7/tile_type_CMT_TOP_L_LOWER_T.json @@ -2,1962 +2,6082 @@ "pips": { "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_A->CMT_PHASER_IN_CA_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" }, "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_B->CMT_PHASER_IN_DB_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" }, "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_A->CMT_PHASER_OUT_CA_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" }, "CMT_TOP_L_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_B->CMT_PHASER_OUT_DB_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, 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}, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_DQSFOUND" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_DQSOUTOFRANGE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_A_ICLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_A_ICLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ICLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_A_WRCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_A_WRCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ICLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ISERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_CA_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_A_RCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_A_RCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_RCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_A_WREN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_A_WREN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_WRENABLE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSFOUND" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_ICLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ISERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_DB_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_RCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_RCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_WRENABLE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK->>CMT_PHASER_B_OCLK_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.043", + "0.071", + "0.080" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_B_OCLK_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.043", + "0.071", + "0.080" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_B_OCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.036", + "0.041", + "0.065", + "0.073" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.036", + "0.041", + "0.065", + "0.073" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV->>CMT_PHASER_B_OCLKDIV_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.045", + "0.072", + "0.081" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.045", + "0.072", + "0.081" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_B_OCLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_CTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_CTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DQSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DQSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_RDENABLE" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLK" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_B_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST" }, "CMT_TOP_L_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_RDENABLE" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK0_8" }, "CMT_TOP_L_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK1_8" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX12_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX12_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX1_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX21_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX25_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX25_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX28_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX2_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_1" }, 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"is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX32_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX39_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_2" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_6->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_5->CMT_PHASER_OUT_DB_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX46_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_4" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_1" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_5->CMT_PHASER_OUT_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_5" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_6->CMT_PHASER_IN_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_6" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX47_7->CMT_PHASER_IN_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_7" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX8_3" }, "CMT_TOP_L_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { 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"in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT0->>MMCM_CLK_FREQBB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT1->>MMCM_CLK_FREQBB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT2->>MMCM_CLK_FREQBB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" }, "CMT_TOP_L_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT3->>MMCM_CLK_FREQBB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" } }, @@ -1966,83 +6086,776 @@ "name": "X0Y0", "prefix": "PHASER_OUT_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "RST": "CMT_PHASER_OUT_CA_RST", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" + }, + "COARSEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEENABLE" + }, + "COARSEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "COARSEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "COUNTERLOADVAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "COUNTERLOADVAL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1" + }, + "COUNTERLOADVAL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2" + }, + "COUNTERLOADVAL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3" + }, + "COUNTERLOADVAL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4" + }, + "COUNTERLOADVAL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5" + }, + "COUNTERLOADVAL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6" + }, + "COUNTERLOADVAL7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7" + }, + "COUNTERLOADVAL8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8" + }, + "COUNTERREADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERREADEN" + }, + "COUNTERREADVAL0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" + }, + "COUNTERREADVAL1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" + }, + "COUNTERREADVAL2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" + }, + "COUNTERREADVAL3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" + }, + "COUNTERREADVAL4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" + }, + "COUNTERREADVAL5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" + }, + "COUNTERREADVAL6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6" + }, + "COUNTERREADVAL7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7" + }, + "COUNTERREADVAL8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8" + }, + "CTSBUS0": { + "delay": [ + "0.000", + "0.000", + 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"wire": "CMT_PHASER_OUT_CA_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT3" + } }, "type": "PHASER_OUT_PHY", "x_coord": 0, @@ -2052,98 +6865,926 @@ "name": "X0Y0", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_CA_ICLK", - "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_CA_RCLK", - "RST": "CMT_PHASER_IN_CA_RST", - "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", - "SCANENB": "CMT_PHASER_IN_CA_SCANENB", - "SCANIN": "CMT_PHASER_IN_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_CA_STG1READ", - "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", - "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", - "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", - "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", - "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", - "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", - "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", - "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", - "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", - "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", - "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", - "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", - "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", - "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", - "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", - "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", - "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", - "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", - "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", - "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", - "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", - "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", - "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", - "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", - "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", - "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", - "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", - "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", - "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", - "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", - "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", - "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", - "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", - "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", - "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_CA_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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"CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", - "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", - "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", - "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", - "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", - "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", - "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", - "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", - "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_DB_OCLK", - "OCLKDELAYED": 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"TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", - "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", - "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", - "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", - "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", - "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", - "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", - "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", - "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", - "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY" + }, + "COARSEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COARSEENABLE" + }, + "COARSEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COARSEINC" + }, + "COARSEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN" + }, + "COUNTERLOADVAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0" + }, + "COUNTERLOADVAL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1" + }, + "COUNTERLOADVAL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2" + }, + "COUNTERLOADVAL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3" + }, + "COUNTERLOADVAL4": { + "cap": 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"0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_DTSBUS0" + }, + "DTSBUS1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_DTSBUS1" + }, + "EDGEADV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_EDGEADV" + }, + "ENCALIB0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIB0" + }, + "ENCALIB1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIB1" + }, + "ENCALIBPHY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0" + }, + "ENCALIBPHY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1" + }, + "FINEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_FINEENABLE" + }, + "FINEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_FINEINC" + }, + "FINEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW" + }, + "FREQREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_FREQREFCLK" + }, + "MEMREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_MEMREFCLK" + }, + "OCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OCLK" + }, + "OCLKDELAYED": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OCLKDELAYED" + }, + "OCLKDIV": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OCLKDIV" + }, + "OSERDESRST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OSERDESRST" + }, + "PHASEREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_PHASEREFCLK" + }, + "RDENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_RDENABLE" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_RST" + }, + "SCANCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANCLK" + }, + "SCANENB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANENB" + }, + "SCANIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANIN" + }, + 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"0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT3" + } }, "type": "PHASER_OUT_PHY", "x_coord": 0, @@ -2239,98 +8573,926 @@ "name": "X0Y1", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_DB_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_DB_ICLK", - "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_DB_RCLK", - "RST": "CMT_PHASER_IN_DB_RST", - "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", - "SCANENB": "CMT_PHASER_IN_DB_SCANENB", - "SCANIN": "CMT_PHASER_IN_DB_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_DB_STG1READ", - "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", - "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", - "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", - "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", - "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", - "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", - "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", - "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", - "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", - "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", - "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", - "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", - "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", - "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", - "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", - "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", - "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", - "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", - "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", - "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", - "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", - "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", - "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", - "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", - "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", - "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", - "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", - "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", - "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", - "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", - "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", - "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", - "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", - "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", - "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", - "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", - "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", - "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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+ "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN13" + }, + "TESTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN2" + }, + "TESTIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN3" + }, + "TESTIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN4" + }, + "TESTIN5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN5" + }, + "TESTIN6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN6" + }, + "TESTIN7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN7" + }, + "TESTIN8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN8" + }, + "TESTIN9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN9" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT3" + }, + "WRENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_WRENABLE" + } }, "type": "PHASER_IN_PHY", "x_coord": 0, @@ -2338,2486 +9500,7130 @@ } ], "tile_type": "CMT_TOP_L_LOWER_T", - "wires": [ - "CMT_BOT_HCLKMUX_CLKINT_0", - "CMT_BOT_HCLKMUX_CLKINT_1", - "CMT_LR_LOWER_T_CLK_IN1_HCLK", - "CMT_LR_LOWER_T_CLK_IN2_HCLK", - "CMT_LR_LOWER_T_CLK_IN3_HCLK", - "CMT_LR_LOWER_T_CLK_MMCM0", - "CMT_LR_LOWER_T_CLK_MMCM1", - "CMT_LR_LOWER_T_CLK_MMCM10", - "CMT_LR_LOWER_T_CLK_MMCM11", - "CMT_LR_LOWER_T_CLK_MMCM12", - "CMT_LR_LOWER_T_CLK_MMCM13", - "CMT_LR_LOWER_T_CLK_MMCM2", - "CMT_LR_LOWER_T_CLK_MMCM3", - "CMT_LR_LOWER_T_CLK_MMCM4", - "CMT_LR_LOWER_T_CLK_MMCM5", - "CMT_LR_LOWER_T_CLK_MMCM6", - "CMT_LR_LOWER_T_CLK_MMCM7", - "CMT_LR_LOWER_T_CLK_MMCM8", - "CMT_LR_LOWER_T_CLK_MMCM9", - "CMT_LR_LOWER_T_CLK_PERF0", - "CMT_LR_LOWER_T_CLK_PERF1", - "CMT_LR_LOWER_T_CLK_PERF2", - "CMT_LR_LOWER_T_CLK_PERF3", - "CMT_PHASERA_CTSBUS0", - "CMT_PHASERA_CTSBUS1", - "CMT_PHASERA_DQSBUS0", - "CMT_PHASERA_DQSBUS1", - "CMT_PHASERA_DTSBUS0", - "CMT_PHASERA_DTSBUS1", - "CMT_PHASERREF_DOWN_PHASERIN_A", - "CMT_PHASERREF_DOWN_PHASERIN_B", - "CMT_PHASERREF_DOWN_PHASEROUT_A", - "CMT_PHASERREF_DOWN_PHASEROUT_B", - "CMT_PHASER_BOT_ENCALIB0", - "CMT_PHASER_BOT_ENCALIB1", - "CMT_PHASER_BOT_IBURSTPENDING0", - "CMT_PHASER_BOT_IBURSTPENDING1", - "CMT_PHASER_BOT_IRANKA0", - "CMT_PHASER_BOT_IRANKA1", - "CMT_PHASER_BOT_IRANKB0", - "CMT_PHASER_BOT_IRANKB1", - "CMT_PHASER_BOT_OBURSTPENDING0", - "CMT_PHASER_BOT_OBURSTPENDING1", - "CMT_PHASER_BOT_REFMUX_0", - "CMT_PHASER_BOT_REFMUX_1", - "CMT_PHASER_BOT_REFMUX_2", - "CMT_PHASER_BOT_SYNC_BB", - "CMT_PHASER_B_ICLKDIV_TOIOI", - "CMT_PHASER_B_ICLK_TOIOI", - "CMT_PHASER_B_OCLK90_TOIOI", - "CMT_PHASER_B_OCLKDIV_TOIOI", - "CMT_PHASER_B_OCLK_TOIOI", - "CMT_PHASER_B_TOMMCM_ICLK", - "CMT_PHASER_B_TOMMCM_ICLKDIV", - "CMT_PHASER_B_TOMMCM_OCLK", - "CMT_PHASER_B_TOMMCM_OCLK1X_90", - "CMT_PHASER_B_TOMMCM_OCLKDIV", - "CMT_PHASER_DOWN_DQS_TO_PHASER_A", - "CMT_PHASER_DOWN_DQS_TO_PHASER_B", - "CMT_PHASER_DOWN_PHASERREF0", - "CMT_PHASER_DOWN_PHASERREF1", - "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "CMT_PHASER_IN_A_ICLK", - "CMT_PHASER_IN_A_ICLKDIV", - "CMT_PHASER_IN_A_RCLK0", - "CMT_PHASER_IN_A_WRCLK_TOFIFO", - "CMT_PHASER_IN_A_WREN_TOFIFO", - "CMT_PHASER_IN_B_ICLK", - "CMT_PHASER_IN_B_ICLKDIV", - "CMT_PHASER_IN_B_RCLK1", - "CMT_PHASER_IN_B_WRCLK_TOFIFO", - "CMT_PHASER_IN_B_WREN_TOFIFO", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_CA_ICLK", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_PHASER_IN_CA_RCLK", - "CMT_PHASER_IN_CA_RST", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_PHASER_IN_DB_ICLK", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_PHASER_IN_DB_RCLK", - "CMT_PHASER_IN_DB_RST", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_PHASER_IN_DB_STG1REGR1", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_PHASER_IN_DB_TESTIN7", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_PHASER_IN_DB_TESTOUT1", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_PHASER_OUT_A_OCLK", - "CMT_PHASER_OUT_A_OCLK1X_90", - "CMT_PHASER_OUT_A_OCLKDIV", - "CMT_PHASER_OUT_A_RDCLK_TOFIFO", - "CMT_PHASER_OUT_A_RDEN_TOFIFO", - "CMT_PHASER_OUT_B_OCLK", - "CMT_PHASER_OUT_B_OCLK1X_90", - "CMT_PHASER_OUT_B_OCLKDIV", - "CMT_PHASER_OUT_B_RDCLK_TOFIFO", - "CMT_PHASER_OUT_B_RDEN_TOFIFO", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_PHASER_OUT_CA_RST", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_PHASER_OUT_CA_TESTIN4", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_DIVIDERST", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_PHASER_OUT_DB_RST", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_R_TOP_LOWER_B_CLKINT_0", - "CMT_R_TOP_LOWER_B_CLKINT_1", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX10_4", - "CMT_TOP_IMUX10_5", - "CMT_TOP_IMUX10_6", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_IMUX11_0", - "CMT_TOP_IMUX11_1", - "CMT_TOP_IMUX11_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX11_4", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_IMUX12_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX12_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX12_6", - "CMT_TOP_IMUX12_7", - "CMT_TOP_IMUX12_8", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX13_3", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX13_8", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX14_3", - "CMT_TOP_IMUX14_4", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_IMUX15_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX15_4", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_IMUX16_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX16_5", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX16_7", - "CMT_TOP_IMUX16_8", - "CMT_TOP_IMUX17_0", - "CMT_TOP_IMUX17_1", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX17_3", - "CMT_TOP_IMUX17_4", - "CMT_TOP_IMUX17_5", - "CMT_TOP_IMUX17_6", - "CMT_TOP_IMUX17_7", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_IMUX18_1", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX18_3", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX18_5", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX18_7", - "CMT_TOP_IMUX18_8", - "CMT_TOP_IMUX19_0", - "CMT_TOP_IMUX19_1", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX19_3", - "CMT_TOP_IMUX19_4", - "CMT_TOP_IMUX19_5", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX19_7", - "CMT_TOP_IMUX19_8", - "CMT_TOP_IMUX1_0", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX1_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_IMUX1_8", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX20_2", - "CMT_TOP_IMUX20_3", - "CMT_TOP_IMUX20_4", - "CMT_TOP_IMUX20_5", - "CMT_TOP_IMUX20_6", - "CMT_TOP_IMUX20_7", - "CMT_TOP_IMUX20_8", - "CMT_TOP_IMUX21_0", - "CMT_TOP_IMUX21_1", - "CMT_TOP_IMUX21_2", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_IMUX21_7", - "CMT_TOP_IMUX21_8", - "CMT_TOP_IMUX22_0", - "CMT_TOP_IMUX22_1", - "CMT_TOP_IMUX22_2", - "CMT_TOP_IMUX22_3", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX22_7", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX23_0", - "CMT_TOP_IMUX23_1", - "CMT_TOP_IMUX23_2", - "CMT_TOP_IMUX23_3", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX23_7", - "CMT_TOP_IMUX23_8", - "CMT_TOP_IMUX24_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_IMUX24_4", - "CMT_TOP_IMUX24_5", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX24_8", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX25_1", - "CMT_TOP_IMUX25_2", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX25_6", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX25_8", - "CMT_TOP_IMUX26_0", - "CMT_TOP_IMUX26_1", - "CMT_TOP_IMUX26_2", - "CMT_TOP_IMUX26_3", - "CMT_TOP_IMUX26_4", - "CMT_TOP_IMUX26_5", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX26_7", - "CMT_TOP_IMUX26_8", - "CMT_TOP_IMUX27_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX27_2", - "CMT_TOP_IMUX27_3", - "CMT_TOP_IMUX27_4", - "CMT_TOP_IMUX27_5", - "CMT_TOP_IMUX27_6", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX27_8", - "CMT_TOP_IMUX28_0", - "CMT_TOP_IMUX28_1", - "CMT_TOP_IMUX28_2", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX28_5", - "CMT_TOP_IMUX28_6", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX28_8", - "CMT_TOP_IMUX29_0", - "CMT_TOP_IMUX29_1", - "CMT_TOP_IMUX29_2", - "CMT_TOP_IMUX29_3", - "CMT_TOP_IMUX29_4", - "CMT_TOP_IMUX29_5", - "CMT_TOP_IMUX29_6", - "CMT_TOP_IMUX29_7", - "CMT_TOP_IMUX29_8", - "CMT_TOP_IMUX2_0", - "CMT_TOP_IMUX2_1", - "CMT_TOP_IMUX2_2", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX2_4", - "CMT_TOP_IMUX2_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_IMUX2_7", - "CMT_TOP_IMUX2_8", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX30_1", - "CMT_TOP_IMUX30_2", - "CMT_TOP_IMUX30_3", - "CMT_TOP_IMUX30_4", - "CMT_TOP_IMUX30_5", - "CMT_TOP_IMUX30_6", - "CMT_TOP_IMUX30_7", - "CMT_TOP_IMUX30_8", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX31_2", - "CMT_TOP_IMUX31_3", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX31_5", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX31_8", - "CMT_TOP_IMUX32_0", - "CMT_TOP_IMUX32_1", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX32_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_IMUX32_5", - "CMT_TOP_IMUX32_6", - "CMT_TOP_IMUX32_7", - "CMT_TOP_IMUX32_8", - "CMT_TOP_IMUX33_0", - "CMT_TOP_IMUX33_1", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX33_4", - "CMT_TOP_IMUX33_5", - "CMT_TOP_IMUX33_6", - "CMT_TOP_IMUX33_7", - "CMT_TOP_IMUX33_8", - "CMT_TOP_IMUX34_0", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX34_4", - "CMT_TOP_IMUX34_5", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX34_7", - "CMT_TOP_IMUX34_8", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX35_1", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX35_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_IMUX35_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_IMUX35_7", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX36_0", - "CMT_TOP_IMUX36_1", - "CMT_TOP_IMUX36_2", - "CMT_TOP_IMUX36_3", - "CMT_TOP_IMUX36_4", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX36_6", - "CMT_TOP_IMUX36_7", - "CMT_TOP_IMUX36_8", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX37_2", - "CMT_TOP_IMUX37_3", - "CMT_TOP_IMUX37_4", - "CMT_TOP_IMUX37_5", - "CMT_TOP_IMUX37_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_IMUX38_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_IMUX38_2", - "CMT_TOP_IMUX38_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX38_6", - "CMT_TOP_IMUX38_7", - "CMT_TOP_IMUX38_8", - "CMT_TOP_IMUX39_0", - "CMT_TOP_IMUX39_1", - "CMT_TOP_IMUX39_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_IMUX39_5", - "CMT_TOP_IMUX39_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX39_8", - "CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "MMCM_CLK_FREQBB_REBUFOUT0", - "MMCM_CLK_FREQBB_REBUFOUT1", - "MMCM_CLK_FREQBB_REBUFOUT2", - "MMCM_CLK_FREQBB_REBUFOUT3" - ] + "wires": { + "CMT_BOT_HCLKMUX_CLKINT_0": null, + "CMT_BOT_HCLKMUX_CLKINT_1": null, + "CMT_LR_LOWER_T_CLK_IN1_HCLK": null, + "CMT_LR_LOWER_T_CLK_IN2_HCLK": null, + "CMT_LR_LOWER_T_CLK_IN3_HCLK": null, + "CMT_LR_LOWER_T_CLK_MMCM0": null, + "CMT_LR_LOWER_T_CLK_MMCM1": null, + "CMT_LR_LOWER_T_CLK_MMCM10": null, + "CMT_LR_LOWER_T_CLK_MMCM11": null, + "CMT_LR_LOWER_T_CLK_MMCM12": null, + "CMT_LR_LOWER_T_CLK_MMCM13": null, + "CMT_LR_LOWER_T_CLK_MMCM2": null, + "CMT_LR_LOWER_T_CLK_MMCM3": null, + "CMT_LR_LOWER_T_CLK_MMCM4": null, + "CMT_LR_LOWER_T_CLK_MMCM5": null, + "CMT_LR_LOWER_T_CLK_MMCM6": null, + "CMT_LR_LOWER_T_CLK_MMCM7": null, + "CMT_LR_LOWER_T_CLK_MMCM8": null, + "CMT_LR_LOWER_T_CLK_MMCM9": null, + "CMT_LR_LOWER_T_CLK_PERF0": null, + "CMT_LR_LOWER_T_CLK_PERF1": null, + "CMT_LR_LOWER_T_CLK_PERF2": null, + "CMT_LR_LOWER_T_CLK_PERF3": null, + "CMT_PHASERA_CTSBUS0": null, + "CMT_PHASERA_CTSBUS1": null, + "CMT_PHASERA_DQSBUS0": null, + "CMT_PHASERA_DQSBUS1": null, + "CMT_PHASERA_DTSBUS0": null, + "CMT_PHASERA_DTSBUS1": null, + "CMT_PHASERREF_DOWN_PHASERIN_A": null, + "CMT_PHASERREF_DOWN_PHASERIN_B": null, + "CMT_PHASERREF_DOWN_PHASEROUT_A": null, + "CMT_PHASERREF_DOWN_PHASEROUT_B": null, + "CMT_PHASER_BOT_ENCALIB0": null, + "CMT_PHASER_BOT_ENCALIB1": null, + "CMT_PHASER_BOT_IBURSTPENDING0": null, + "CMT_PHASER_BOT_IBURSTPENDING1": null, + "CMT_PHASER_BOT_IRANKA0": null, + "CMT_PHASER_BOT_IRANKA1": null, + "CMT_PHASER_BOT_IRANKB0": null, + "CMT_PHASER_BOT_IRANKB1": null, + "CMT_PHASER_BOT_OBURSTPENDING0": null, + "CMT_PHASER_BOT_OBURSTPENDING1": null, + "CMT_PHASER_BOT_REFMUX_0": null, + "CMT_PHASER_BOT_REFMUX_1": null, + "CMT_PHASER_BOT_REFMUX_2": null, + "CMT_PHASER_BOT_SYNC_BB": null, + "CMT_PHASER_B_ICLKDIV_TOIOI": null, + "CMT_PHASER_B_ICLK_TOIOI": null, + "CMT_PHASER_B_OCLK90_TOIOI": null, + "CMT_PHASER_B_OCLKDIV_TOIOI": null, + "CMT_PHASER_B_OCLK_TOIOI": null, + "CMT_PHASER_B_TOMMCM_ICLK": null, + "CMT_PHASER_B_TOMMCM_ICLKDIV": null, + "CMT_PHASER_B_TOMMCM_OCLK": null, + "CMT_PHASER_B_TOMMCM_OCLK1X_90": null, + "CMT_PHASER_B_TOMMCM_OCLKDIV": null, + "CMT_PHASER_DOWN_DQS_TO_PHASER_A": null, + "CMT_PHASER_DOWN_DQS_TO_PHASER_B": null, + "CMT_PHASER_DOWN_PHASERREF0": null, + "CMT_PHASER_DOWN_PHASERREF1": null, + "CMT_PHASER_DOWN_PHASERREF_ABOVE0": null, + "CMT_PHASER_DOWN_PHASERREF_ABOVE1": null, + "CMT_PHASER_DOWN_PHASERREF_BELOW0": null, + "CMT_PHASER_DOWN_PHASERREF_BELOW1": null, + "CMT_PHASER_IN_A_ICLK": null, + "CMT_PHASER_IN_A_ICLKDIV": null, + "CMT_PHASER_IN_A_RCLK0": null, + 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"MMCMOUT_CLK_FREQ_BB_REBUFIN0": null, + "MMCMOUT_CLK_FREQ_BB_REBUFIN1": null, + "MMCMOUT_CLK_FREQ_BB_REBUFIN2": null, + "MMCMOUT_CLK_FREQ_BB_REBUFIN3": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT0": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT1": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT2": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT3": null, + "MMCM_CLK_FREQBB_REBUFOUT0": null, + "MMCM_CLK_FREQBB_REBUFOUT1": null, + "MMCM_CLK_FREQBB_REBUFOUT2": null, + "MMCM_CLK_FREQBB_REBUFOUT3": null + } } diff --git a/kintex7/tile_type_CMT_TOP_L_UPPER_B.json b/kintex7/tile_type_CMT_TOP_L_UPPER_B.json index 2013056..3068653 100644 --- a/kintex7/tile_type_CMT_TOP_L_UPPER_B.json +++ b/kintex7/tile_type_CMT_TOP_L_UPPER_B.json @@ -2,2711 +2,8368 @@ "pips": { "CMT_TOP_L_UPPER_B.CMT_FREQ_BB_PREF_IN0->>CMT_FREQ_PHASER_REFMUX_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.077", + "0.088", + "0.187", + "0.209" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", "is_directional": "1", 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null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL4" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_COUNTERREADVAL5" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_DQSFOUND" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B15_3": { 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"src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ICLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_R_PHASER_IN_C_WRCLK_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ICLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ISERDESRST" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { 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"CMT_PHASER_IN_C_RCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_RCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_WRENABLE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.043", + "0.073", + "0.082" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_ICLK_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.043", + "0.073", + "0.082" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_C_ICLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.041", + "0.046", + "0.075", + "0.085" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.041", + "0.046", + "0.075", + "0.085" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_C_ICLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSFOUND" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_ICLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_R_PHASER_IN_D_WRCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ISERDESRST" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_DB_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_RCLK3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_RCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_WRENABLE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_R_PHASER_OUT_C_RDCLK_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_R_PHASER_OUT_C_RDENABLE_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_OUT_C_RDENABLE_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_RDENABLE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.043", + "0.069", + "0.078" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_OCLK_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.043", + "0.069", + "0.078" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_C_OCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.045", + "0.073", + "0.082" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.045", + "0.073", + "0.082" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.042", + "0.047", + "0.077", + "0.087" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.042", + "0.047", + "0.077", + "0.087" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_C_OCLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS0->CMT_PHASERD_CTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_CTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_CTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS0->CMT_PHASERD_DQSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_DQSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_DQSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS0->CMT_PHASERD_DTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_DTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_DTSBUS1->CMT_PHASERD_DTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_DTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_D_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_D_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLK" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_D_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_D_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OCLKDIV->CMT_R_PHASER_OUT_D_RDCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_OUT_DB_RDENABLE->CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_RDENABLE" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_CLKOUT->CMT_PHASER_REF_CLKOUT_TOHCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_REF_CLKOUT_TOHCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_REF_CLKOUT" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_LOCKED->CMT_TOP_LOGIC_OUTS_L_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_REF_LOCKED" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_REF_TMUXOUT->CMT_PHASER_REF_TMUXOUT_TOHCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_REF_TMUXOUT_TOHCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_REF_TMUXOUT" }, "CMT_TOP_L_UPPER_B.CMT_PHASER_TOP_SYNC_BB->>CMT_PHASERTOP_PHYCTLMSTREMPTY": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + 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"0.000" + }, "src_wire": "CMT_PHY_CONTROL_ECALIB0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_ECALIB0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_ECALIB1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_ECALIB1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_ECALIB1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_ECALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_ECALIB1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING2->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING2" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IBURSTPENDING3->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IBURSTPENDING3" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING0->CMT_PHY_CONTROL_IBURSTPENDING0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING1->CMT_PHY_CONTROL_IBURSTPENDING1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING2->CMT_PHY_CONTROL_IBURSTPENDING2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING2" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INBURSTPENDING3->CMT_PHY_CONTROL_IBURSTPENDING3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IBURSTPENDING3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INBURSTPENDING3" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA0->CMT_PHY_CONTROL_IRANKA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKA0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKA1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKB0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKB1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKC0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKC1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKD0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKD1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKC0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKC1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKD0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKD1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING2" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_ECALIB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_ECALIB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL" }, "CMT_TOP_L_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY" }, "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_C_WRCLK_FIFO->CMT_PHASER_IN_C_ICLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_ICLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_R_PHASER_IN_C_WRCLK_FIFO" }, "CMT_TOP_L_UPPER_B.CMT_R_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_ICLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_R_PHASER_IN_D_WRCLK_TOFIFO" }, "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_C_RDCLK_FIFO->CMT_PHASER_OUT_C_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_R_PHASER_OUT_C_RDCLK_FIFO" }, "CMT_TOP_L_UPPER_B.CMT_R_PHASER_OUT_D_RDCLK_TOFIFO->CMT_PHASER_OUT_D_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_D_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_0->>CMT_L_TOP_UPPER_B_CLKINT_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK0_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_8" }, "CMT_TOP_L_UPPER_B.CMT_TOP_CLK1_0->>CMT_L_TOP_UPPER_B_CLKINT_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_L_TOP_UPPER_B_CLKINT_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK1_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX12_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_REF_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_10->CMT_PHY_CONTROL_PHYCTLWD18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX16_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX16_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX17_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX17_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX17_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX18_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX18_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX1_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX1_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX22_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX28_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX2_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX2_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX32_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX32_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX37_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX39_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX3_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX3_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_4" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PLLLOCK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_0->CMT_PHASER_REF_PWRDWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_REF_PWRDWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_0" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_1" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_3" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX4_10" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX4_11" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX4_9" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX8_6" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX8_7" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_2" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_5" }, "CMT_TOP_L_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_6" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>CMT_FREQ_PHASER_REFMUX_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>CMT_FREQ_PHASER_REFMUX_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" }, "CMT_TOP_L_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" }, "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT0" }, "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT1" }, "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT2" }, "CMT_TOP_L_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT3" } }, @@ -2715,28 +8372,226 @@ "name": "X0Y0", "prefix": "PHASER_REF", "site_pins": { - "CLKIN": "CMT_PHASER_REF_CLKIN", - "CLKOUT": "CMT_PHASER_REF_CLKOUT", - "LOCKED": "CMT_PHASER_REF_LOCKED", - "PWRDWN": "CMT_PHASER_REF_PWRDWN", - "RST": "CMT_PHASER_REF_RST", - "TESTIN0": "CMT_PHASER_REF_TESTIN0", - "TESTIN1": "CMT_PHASER_REF_TESTIN1", - "TESTIN2": "CMT_PHASER_REF_TESTIN2", - "TESTIN3": "CMT_PHASER_REF_TESTIN3", - "TESTIN4": "CMT_PHASER_REF_TESTIN4", - "TESTIN5": "CMT_PHASER_REF_TESTIN5", - "TESTIN6": "CMT_PHASER_REF_TESTIN6", - "TESTIN7": "CMT_PHASER_REF_TESTIN7", - "TESTOUT0": "CMT_PHASER_REF_TESTOUT0", - "TESTOUT1": "CMT_PHASER_REF_TESTOUT1", - "TESTOUT2": "CMT_PHASER_REF_TESTOUT2", - "TESTOUT3": "CMT_PHASER_REF_TESTOUT3", - "TESTOUT4": "CMT_PHASER_REF_TESTOUT4", - "TESTOUT5": "CMT_PHASER_REF_TESTOUT5", - "TESTOUT6": "CMT_PHASER_REF_TESTOUT6", - "TESTOUT7": "CMT_PHASER_REF_TESTOUT7", - "TMUXOUT": "CMT_PHASER_REF_TMUXOUT" + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_CLKIN" + }, + "CLKOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_CLKOUT" + }, + "LOCKED": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_LOCKED" + }, + "PWRDWN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_PWRDWN" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_RST" + }, + "TESTIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN0" + }, + "TESTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN1" + }, + "TESTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN2" + }, + "TESTIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN3" + }, + "TESTIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN4" + }, + "TESTIN5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN5" + }, + "TESTIN6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN6" + }, + "TESTIN7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN7" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT3" + }, + "TESTOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT4" + }, + "TESTOUT5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT5" + }, + "TESTOUT6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT6" + }, + "TESTOUT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT7" + }, + "TMUXOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TMUXOUT" + } }, "type": "PHASER_REF", "x_coord": 0, @@ -2746,110 +8601,1046 @@ "name": "X0Y0", "prefix": "PHY_CONTROL", "site_pins": { - "AUXOUTPUT0": "CMT_PHY_CONTROL_AUXOUTPUT0", - "AUXOUTPUT1": "CMT_PHY_CONTROL_AUXOUTPUT1", - "AUXOUTPUT2": "CMT_PHY_CONTROL_AUXOUTPUT2", - "AUXOUTPUT3": "CMT_PHY_CONTROL_AUXOUTPUT3", - "INBURSTPENDING0": "CMT_PHY_CONTROL_INBURSTPENDING0", - "INBURSTPENDING1": "CMT_PHY_CONTROL_INBURSTPENDING1", - "INBURSTPENDING2": "CMT_PHY_CONTROL_INBURSTPENDING2", - "INBURSTPENDING3": "CMT_PHY_CONTROL_INBURSTPENDING3", - "INRANKA0": "CMT_PHY_CONTROL_INRANKA0", - "INRANKA1": "CMT_PHY_CONTROL_INRANKA1", - "INRANKB0": "CMT_PHY_CONTROL_INRANKB0", - "INRANKB1": "CMT_PHY_CONTROL_INRANKB1", - "INRANKC0": "CMT_PHY_CONTROL_INRANKC0", - "INRANKC1": "CMT_PHY_CONTROL_INRANKC1", - "INRANKD0": "CMT_PHY_CONTROL_INRANKD0", - "INRANKD1": "CMT_PHY_CONTROL_INRANKD1", - "MEMREFCLK": "CMT_PHY_CONTROL_MEMREFCLK", - "OUTBURSTPENDING0": "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "OUTBURSTPENDING1": "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "OUTBURSTPENDING2": "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "OUTBURSTPENDING3": "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "PCENABLECALIB0": "CMT_PHY_CONTROL_PCENABLECALIB0", - "PCENABLECALIB1": "CMT_PHY_CONTROL_PCENABLECALIB1", - "PHYCLK": "CMT_PHY_CONTROL_PHYCLK", - "PHYCTLALMOSTFULL": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "PHYCTLEMPTY": "CMT_PHY_CONTROL_PHYCTLEMPTY", - "PHYCTLFULL": "CMT_PHY_CONTROL_PHYCTLFULL", - "PHYCTLMSTREMPTY": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "PHYCTLREADY": "CMT_PHY_CONTROL_PHYCTLREADY", - "PHYCTLWD0": "CMT_PHY_CONTROL_PHYCTLWD0", - "PHYCTLWD1": "CMT_PHY_CONTROL_PHYCTLWD1", - "PHYCTLWD10": "CMT_PHY_CONTROL_PHYCTLWD10", - "PHYCTLWD11": "CMT_PHY_CONTROL_PHYCTLWD11", - "PHYCTLWD12": "CMT_PHY_CONTROL_PHYCTLWD12", - "PHYCTLWD13": "CMT_PHY_CONTROL_PHYCTLWD13", - "PHYCTLWD14": "CMT_PHY_CONTROL_PHYCTLWD14", - "PHYCTLWD15": "CMT_PHY_CONTROL_PHYCTLWD15", - "PHYCTLWD16": "CMT_PHY_CONTROL_PHYCTLWD16", - "PHYCTLWD17": "CMT_PHY_CONTROL_PHYCTLWD17", - "PHYCTLWD18": "CMT_PHY_CONTROL_PHYCTLWD18", - "PHYCTLWD19": "CMT_PHY_CONTROL_PHYCTLWD19", - "PHYCTLWD2": "CMT_PHY_CONTROL_PHYCTLWD2", - "PHYCTLWD20": "CMT_PHY_CONTROL_PHYCTLWD20", - "PHYCTLWD21": "CMT_PHY_CONTROL_PHYCTLWD21", - "PHYCTLWD22": "CMT_PHY_CONTROL_PHYCTLWD22", - "PHYCTLWD23": "CMT_PHY_CONTROL_PHYCTLWD23", - "PHYCTLWD24": "CMT_PHY_CONTROL_PHYCTLWD24", - "PHYCTLWD25": "CMT_PHY_CONTROL_PHYCTLWD25", - "PHYCTLWD26": "CMT_PHY_CONTROL_PHYCTLWD26", - "PHYCTLWD27": "CMT_PHY_CONTROL_PHYCTLWD27", - "PHYCTLWD28": "CMT_PHY_CONTROL_PHYCTLWD28", - "PHYCTLWD29": "CMT_PHY_CONTROL_PHYCTLWD29", - "PHYCTLWD3": "CMT_PHY_CONTROL_PHYCTLWD3", - "PHYCTLWD30": "CMT_PHY_CONTROL_PHYCTLWD30", - "PHYCTLWD31": "CMT_PHY_CONTROL_PHYCTLWD31", - "PHYCTLWD4": "CMT_PHY_CONTROL_PHYCTLWD4", - "PHYCTLWD5": "CMT_PHY_CONTROL_PHYCTLWD5", - "PHYCTLWD6": "CMT_PHY_CONTROL_PHYCTLWD6", - "PHYCTLWD7": "CMT_PHY_CONTROL_PHYCTLWD7", - "PHYCTLWD8": "CMT_PHY_CONTROL_PHYCTLWD8", - "PHYCTLWD9": "CMT_PHY_CONTROL_PHYCTLWD9", - "PHYCTLWRENABLE": "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "PLLLOCK": "CMT_PHY_CONTROL_PLLLOCK", - "READCALIBENABLE": "CMT_PHY_CONTROL_READCALIBENABLE", - "REFDLLLOCK": "CMT_PHY_CONTROL_REFDLLLOCK", - "RESET": "CMT_PHY_CONTROL_RESET", - "SCANENABLEN": "CMT_PHY_CONTROL_SCANENABLEN", - "SYNCIN": "CMT_PHY_CONTROL_SYNCIN", - "TESTINPUT0": "CMT_PHY_CONTROL_TESTINPUT0", - "TESTINPUT1": "CMT_PHY_CONTROL_TESTINPUT1", - "TESTINPUT10": "CMT_PHY_CONTROL_TESTINPUT10", - "TESTINPUT11": "CMT_PHY_CONTROL_TESTINPUT11", - "TESTINPUT12": "CMT_PHY_CONTROL_TESTINPUT12", - "TESTINPUT13": "CMT_PHY_CONTROL_TESTINPUT13", - "TESTINPUT14": "CMT_PHY_CONTROL_TESTINPUT14", - "TESTINPUT15": "CMT_PHY_CONTROL_TESTINPUT15", - "TESTINPUT2": "CMT_PHY_CONTROL_TESTINPUT2", - "TESTINPUT3": "CMT_PHY_CONTROL_TESTINPUT3", - "TESTINPUT4": "CMT_PHY_CONTROL_TESTINPUT4", - "TESTINPUT5": "CMT_PHY_CONTROL_TESTINPUT5", - "TESTINPUT6": "CMT_PHY_CONTROL_TESTINPUT6", - "TESTINPUT7": "CMT_PHY_CONTROL_TESTINPUT7", - "TESTINPUT8": "CMT_PHY_CONTROL_TESTINPUT8", - "TESTINPUT9": "CMT_PHY_CONTROL_TESTINPUT9", - "TESTOUTPUT0": "CMT_PHY_CONTROL_TESTOUTPUT0", - "TESTOUTPUT1": "CMT_PHY_CONTROL_TESTOUTPUT1", - "TESTOUTPUT10": "CMT_PHY_CONTROL_TESTOUTPUT10", - "TESTOUTPUT11": "CMT_PHY_CONTROL_TESTOUTPUT11", - "TESTOUTPUT12": "CMT_PHY_CONTROL_TESTOUTPUT12", - "TESTOUTPUT13": "CMT_PHY_CONTROL_TESTOUTPUT13", - "TESTOUTPUT14": "CMT_PHY_CONTROL_TESTOUTPUT14", - "TESTOUTPUT15": "CMT_PHY_CONTROL_TESTOUTPUT15", - "TESTOUTPUT2": "CMT_PHY_CONTROL_TESTOUTPUT2", - "TESTOUTPUT3": "CMT_PHY_CONTROL_TESTOUTPUT3", - "TESTOUTPUT4": "CMT_PHY_CONTROL_TESTOUTPUT4", - "TESTOUTPUT5": "CMT_PHY_CONTROL_TESTOUTPUT5", - "TESTOUTPUT6": "CMT_PHY_CONTROL_TESTOUTPUT6", - "TESTOUTPUT7": "CMT_PHY_CONTROL_TESTOUTPUT7", - "TESTOUTPUT8": "CMT_PHY_CONTROL_TESTOUTPUT8", - "TESTOUTPUT9": "CMT_PHY_CONTROL_TESTOUTPUT9", - "TESTSELECT0": "CMT_PHY_CONTROL_TESTSELECT0", - "TESTSELECT1": "CMT_PHY_CONTROL_TESTSELECT1", - "TESTSELECT2": "CMT_PHY_CONTROL_TESTSELECT2", - "WRITECALIBENABLE": "CMT_PHY_CONTROL_WRITECALIBENABLE" + "AUXOUTPUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT0" + }, + "AUXOUTPUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT1" + }, + "AUXOUTPUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT2" + }, + "AUXOUTPUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT3" + }, + "INBURSTPENDING0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING0" + }, + "INBURSTPENDING1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING1" + }, + "INBURSTPENDING2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING2" + }, + "INBURSTPENDING3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING3" + }, + "INRANKA0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKA0" + }, + "INRANKA1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKA1" + }, + "INRANKB0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKB0" + }, + "INRANKB1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKB1" + }, + "INRANKC0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKC0" + }, + "INRANKC1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKC1" + }, + "INRANKD0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKD0" + }, + "INRANKD1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKD1" + }, + "MEMREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_MEMREFCLK" + }, + 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"CMT_PHY_CONTROL_TESTSELECT0" + }, + "TESTSELECT1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTSELECT1" + }, + "TESTSELECT2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTSELECT2" + }, + "WRITECALIBENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_WRITECALIBENABLE" + } }, "type": "PHY_CONTROL", "x_coord": 0, @@ -2859,83 +9650,776 @@ "name": "X0Y0", "prefix": "PHASER_OUT_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "RST": "CMT_PHASER_OUT_CA_RST", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" + }, + "COARSEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEENABLE" + }, + "COARSEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "COARSEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "COUNTERLOADVAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "COUNTERLOADVAL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1" + }, + "COUNTERLOADVAL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2" + }, + "COUNTERLOADVAL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3" + }, + "COUNTERLOADVAL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4" + }, + "COUNTERLOADVAL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5" + }, + "COUNTERLOADVAL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6" + }, + "COUNTERLOADVAL7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7" + }, + "COUNTERLOADVAL8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8" + }, + "COUNTERREADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERREADEN" + }, + "COUNTERREADVAL0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" + }, + "COUNTERREADVAL1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": 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"res": "0.0", + "wire": "CMT_PHASER_OUT_CA_DTSBUS1" + }, + "EDGEADV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_EDGEADV" + }, + "ENCALIB0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIB0" + }, + "ENCALIB1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIB1" + }, + "ENCALIBPHY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0" + }, + "ENCALIBPHY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1" + }, + "FINEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_FINEENABLE" + }, + "FINEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_FINEINC" + }, + "FINEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" + }, + "FREQREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_FREQREFCLK" + }, + "MEMREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_MEMREFCLK" + }, + "OCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OCLK" + }, + "OCLKDELAYED": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" + }, + "OCLKDIV": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OCLKDIV" + }, + "OSERDESRST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OSERDESRST" + }, + "PHASEREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_PHASEREFCLK" + }, + "RDENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_RDENABLE" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_RST" + }, + "SCANCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANCLK" + }, + "SCANENB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANENB" + }, + "SCANIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANIN" + }, + "SCANMODEB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANMODEB" + }, + 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"wire": "CMT_PHASER_OUT_CA_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT3" + } }, "type": "PHASER_OUT_PHY", "x_coord": 0, @@ -2945,98 +10429,926 @@ "name": "X0Y0", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_CA_ICLK", - "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_CA_RCLK", - "RST": "CMT_PHASER_IN_CA_RST", - "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", - "SCANENB": "CMT_PHASER_IN_CA_SCANENB", - "SCANIN": "CMT_PHASER_IN_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_CA_STG1READ", - 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+ ], + "wire": "CMT_PHASER_OUT_DB_TESTIN9" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT3" + } }, "type": "PHASER_OUT_PHY", "x_coord": 0, @@ -3132,98 +12137,926 @@ "name": "X0Y1", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_DB_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_DB_ICLK", - "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_DB_RCLK", - "RST": "CMT_PHASER_IN_DB_RST", - "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", - "SCANENB": "CMT_PHASER_IN_DB_SCANENB", - "SCANIN": "CMT_PHASER_IN_DB_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_DB_STG1READ", - "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", - "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", - "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", - "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", - "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", - "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", - "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", - "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", - "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", - "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", - "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", - "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", - "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", - "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", - "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", - "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", - "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", - "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", - "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", - "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", - "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", - "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", - "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", - "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", - "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", - "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", - "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", - "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", - "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", - "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", - "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", - "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", - "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", - "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", - "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", - "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", - "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", - "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE" + "BURSTPENDING": { + "cap": "0.000", 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+13064,9792 @@ } ], "tile_type": "CMT_TOP_L_UPPER_B", - "wires": [ - "CMT_FREQ_BB_PREF_IN0", - "CMT_FREQ_BB_PREF_IN1", - "CMT_FREQ_BB_PREF_IN2", - "CMT_FREQ_BB_PREF_IN3", - "CMT_FREQ_PHASER_REFMUX_0", - "CMT_FREQ_PHASER_REFMUX_1", - "CMT_FREQ_PHASER_REFMUX_2", - "CMT_L_TOP_UPPER_B_CLKINT_2", - "CMT_L_TOP_UPPER_B_CLKINT_3", - "CMT_PHASERD_CTSBUS0", - "CMT_PHASERD_CTSBUS1", - "CMT_PHASERD_DQSBUS0", - "CMT_PHASERD_DQSBUS1", - "CMT_PHASERD_DTSBUS0", - "CMT_PHASERD_DTSBUS1", - "CMT_PHASERREF_PHASERIN_C", - "CMT_PHASERREF_PHASERIN_D", - "CMT_PHASERREF_PHASEROUT_C", - "CMT_PHASERREF_PHASEROUT_D", - "CMT_PHASERTOP_PHYCTLEMPTY", - "CMT_PHASERTOP_PHYCTLMSTREMPTY", - "CMT_PHASER_C_ICLKDIV_TOIOI", - "CMT_PHASER_C_ICLK_TOIOI", - "CMT_PHASER_C_OCLK90_TOIOI", - "CMT_PHASER_C_OCLKDIV_TOIOI", - "CMT_PHASER_C_OCLK_TOIOI", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_CA_ICLK", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_PHASER_IN_CA_RCLK", - "CMT_PHASER_IN_CA_RST", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_PHASER_IN_C_ICLK", - "CMT_PHASER_IN_C_ICLKDIV", - "CMT_PHASER_IN_C_RCLK2", - "CMT_PHASER_IN_C_WRENABLE_FIFO", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_PHASER_IN_DB_ICLK", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_PHASER_IN_DB_RCLK", - "CMT_PHASER_IN_DB_RST", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_PHASER_IN_DB_STG1REGR1", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_PHASER_IN_DB_TESTIN7", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_PHASER_IN_DB_TESTOUT1", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_PHASER_IN_D_ICLK", - "CMT_PHASER_IN_D_ICLKDIV", - "CMT_PHASER_IN_D_RCLK3", - "CMT_PHASER_IN_D_WRENABLE_FIFO", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_PHASER_OUT_CA_RST", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_PHASER_OUT_CA_TESTIN4", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_PHASER_OUT_C_OCLK", - "CMT_PHASER_OUT_C_OCLK1X_90", - "CMT_PHASER_OUT_C_OCLKDIV", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_DIVIDERST", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_PHASER_OUT_DB_RST", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_PHASER_OUT_D_OCLK", - "CMT_PHASER_OUT_D_OCLK1X_90", - "CMT_PHASER_OUT_D_OCLKDIV", - "CMT_PHASER_REF_CLKIN", - "CMT_PHASER_REF_CLKOUT", - "CMT_PHASER_REF_CLKOUT_TOHCLK", - "CMT_PHASER_REF_LOCKED", - "CMT_PHASER_REF_PWRDWN", - "CMT_PHASER_REF_RST", - "CMT_PHASER_REF_TESTIN0", - "CMT_PHASER_REF_TESTIN1", - "CMT_PHASER_REF_TESTIN2", - "CMT_PHASER_REF_TESTIN3", - "CMT_PHASER_REF_TESTIN4", - "CMT_PHASER_REF_TESTIN5", - "CMT_PHASER_REF_TESTIN6", - "CMT_PHASER_REF_TESTIN7", - "CMT_PHASER_REF_TESTOUT0", - "CMT_PHASER_REF_TESTOUT1", - "CMT_PHASER_REF_TESTOUT2", - "CMT_PHASER_REF_TESTOUT3", - "CMT_PHASER_REF_TESTOUT4", - "CMT_PHASER_REF_TESTOUT5", - "CMT_PHASER_REF_TESTOUT6", - "CMT_PHASER_REF_TESTOUT7", - "CMT_PHASER_REF_TMUXOUT", - "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "CMT_PHASER_TOP_SYNC_BB", - "CMT_PHASER_UP_BUFMRCE_CE0", - "CMT_PHASER_UP_BUFMRCE_CE1", - "CMT_PHASER_UP_DQS_TO_PHASER_C", - "CMT_PHASER_UP_DQS_TO_PHASER_D", - "CMT_PHASER_UP_PHASERREF0", - "CMT_PHASER_UP_PHASERREF1", - "CMT_PHASER_UP_PHASERREF_ABOVE0", - "CMT_PHASER_UP_PHASERREF_ABOVE1", - "CMT_PHASER_UP_PHASERREF_BELOW0", - "CMT_PHASER_UP_PHASERREF_BELOW1", - "CMT_PHY_CONTROL_AUXOUTPUT0", - "CMT_PHY_CONTROL_AUXOUTPUT1", - "CMT_PHY_CONTROL_AUXOUTPUT2", - "CMT_PHY_CONTROL_AUXOUTPUT3", - "CMT_PHY_CONTROL_ECALIB0", - "CMT_PHY_CONTROL_ECALIB1", - "CMT_PHY_CONTROL_IBURSTPENDING0", - "CMT_PHY_CONTROL_IBURSTPENDING1", - "CMT_PHY_CONTROL_IBURSTPENDING2", - "CMT_PHY_CONTROL_IBURSTPENDING3", - "CMT_PHY_CONTROL_INBURSTPENDING0", - "CMT_PHY_CONTROL_INBURSTPENDING1", - "CMT_PHY_CONTROL_INBURSTPENDING2", - "CMT_PHY_CONTROL_INBURSTPENDING3", - "CMT_PHY_CONTROL_INRANKA0", - "CMT_PHY_CONTROL_INRANKA1", - "CMT_PHY_CONTROL_INRANKB0", - "CMT_PHY_CONTROL_INRANKB1", - "CMT_PHY_CONTROL_INRANKC0", - "CMT_PHY_CONTROL_INRANKC1", - "CMT_PHY_CONTROL_INRANKD0", - "CMT_PHY_CONTROL_INRANKD1", - "CMT_PHY_CONTROL_IRANKA0", - "CMT_PHY_CONTROL_IRANKA1", - "CMT_PHY_CONTROL_IRANKB0", - "CMT_PHY_CONTROL_IRANKB1", - "CMT_PHY_CONTROL_IRANKC0", - "CMT_PHY_CONTROL_IRANKC1", - "CMT_PHY_CONTROL_IRANKD0", - "CMT_PHY_CONTROL_IRANKD1", - "CMT_PHY_CONTROL_MEMREFCLK", - "CMT_PHY_CONTROL_OBURSTPENDING0", - "CMT_PHY_CONTROL_OBURSTPENDING1", - "CMT_PHY_CONTROL_OBURSTPENDING2", - "CMT_PHY_CONTROL_OBURSTPENDING3", - "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "CMT_PHY_CONTROL_PCENABLECALIB0", - "CMT_PHY_CONTROL_PCENABLECALIB1", - "CMT_PHY_CONTROL_PHYCLK", - "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "CMT_PHY_CONTROL_PHYCTLEMPTY", - "CMT_PHY_CONTROL_PHYCTLFULL", - "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "CMT_PHY_CONTROL_PHYCTLREADY", - "CMT_PHY_CONTROL_PHYCTLWD0", - "CMT_PHY_CONTROL_PHYCTLWD1", - "CMT_PHY_CONTROL_PHYCTLWD10", - "CMT_PHY_CONTROL_PHYCTLWD11", - "CMT_PHY_CONTROL_PHYCTLWD12", - "CMT_PHY_CONTROL_PHYCTLWD13", - "CMT_PHY_CONTROL_PHYCTLWD14", - "CMT_PHY_CONTROL_PHYCTLWD15", - "CMT_PHY_CONTROL_PHYCTLWD16", - "CMT_PHY_CONTROL_PHYCTLWD17", - "CMT_PHY_CONTROL_PHYCTLWD18", - "CMT_PHY_CONTROL_PHYCTLWD19", - "CMT_PHY_CONTROL_PHYCTLWD2", - "CMT_PHY_CONTROL_PHYCTLWD20", - "CMT_PHY_CONTROL_PHYCTLWD21", - "CMT_PHY_CONTROL_PHYCTLWD22", - "CMT_PHY_CONTROL_PHYCTLWD23", - "CMT_PHY_CONTROL_PHYCTLWD24", - "CMT_PHY_CONTROL_PHYCTLWD25", - "CMT_PHY_CONTROL_PHYCTLWD26", - "CMT_PHY_CONTROL_PHYCTLWD27", - "CMT_PHY_CONTROL_PHYCTLWD28", - "CMT_PHY_CONTROL_PHYCTLWD29", - "CMT_PHY_CONTROL_PHYCTLWD3", - "CMT_PHY_CONTROL_PHYCTLWD30", - "CMT_PHY_CONTROL_PHYCTLWD31", - "CMT_PHY_CONTROL_PHYCTLWD4", - "CMT_PHY_CONTROL_PHYCTLWD5", - "CMT_PHY_CONTROL_PHYCTLWD6", - "CMT_PHY_CONTROL_PHYCTLWD7", - "CMT_PHY_CONTROL_PHYCTLWD8", - "CMT_PHY_CONTROL_PHYCTLWD9", - "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "CMT_PHY_CONTROL_PLLLOCK", - "CMT_PHY_CONTROL_READCALIBENABLE", - "CMT_PHY_CONTROL_REFDLLLOCK", - "CMT_PHY_CONTROL_RESET", - "CMT_PHY_CONTROL_SCANENABLEN", - "CMT_PHY_CONTROL_SYNCIN", - "CMT_PHY_CONTROL_TESTINPUT0", - "CMT_PHY_CONTROL_TESTINPUT1", - "CMT_PHY_CONTROL_TESTINPUT10", - "CMT_PHY_CONTROL_TESTINPUT11", - "CMT_PHY_CONTROL_TESTINPUT12", - "CMT_PHY_CONTROL_TESTINPUT13", - "CMT_PHY_CONTROL_TESTINPUT14", - "CMT_PHY_CONTROL_TESTINPUT15", - "CMT_PHY_CONTROL_TESTINPUT2", - "CMT_PHY_CONTROL_TESTINPUT3", - "CMT_PHY_CONTROL_TESTINPUT4", - "CMT_PHY_CONTROL_TESTINPUT5", - "CMT_PHY_CONTROL_TESTINPUT6", - "CMT_PHY_CONTROL_TESTINPUT7", - "CMT_PHY_CONTROL_TESTINPUT8", - "CMT_PHY_CONTROL_TESTINPUT9", - "CMT_PHY_CONTROL_TESTOUTPUT0", - "CMT_PHY_CONTROL_TESTOUTPUT1", - "CMT_PHY_CONTROL_TESTOUTPUT10", - "CMT_PHY_CONTROL_TESTOUTPUT11", - "CMT_PHY_CONTROL_TESTOUTPUT12", - "CMT_PHY_CONTROL_TESTOUTPUT13", - "CMT_PHY_CONTROL_TESTOUTPUT14", - "CMT_PHY_CONTROL_TESTOUTPUT15", - "CMT_PHY_CONTROL_TESTOUTPUT2", - "CMT_PHY_CONTROL_TESTOUTPUT3", - "CMT_PHY_CONTROL_TESTOUTPUT4", - "CMT_PHY_CONTROL_TESTOUTPUT5", - "CMT_PHY_CONTROL_TESTOUTPUT6", - "CMT_PHY_CONTROL_TESTOUTPUT7", - "CMT_PHY_CONTROL_TESTOUTPUT8", - "CMT_PHY_CONTROL_TESTOUTPUT9", - "CMT_PHY_CONTROL_TESTSELECT0", - "CMT_PHY_CONTROL_TESTSELECT1", - "CMT_PHY_CONTROL_TESTSELECT2", - "CMT_PHY_CONTROL_WRITECALIBENABLE", - "CMT_R_PHASER_IN_C_WRCLK_FIFO", - "CMT_R_PHASER_IN_D_WRCLK_TOFIFO", - "CMT_R_PHASER_OUT_C_RDCLK_FIFO", - "CMT_R_PHASER_OUT_C_RDENABLE_FIFO", - "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO", - "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO", - "CMT_R_TOP_UPPER_B_CLKFBIN", - "CMT_R_TOP_UPPER_B_CLKIN1", - "CMT_R_TOP_UPPER_B_CLKIN2", - "CMT_R_TOP_UPPER_B_CLKPLL0", - "CMT_R_TOP_UPPER_B_CLKPLL1", - "CMT_R_TOP_UPPER_B_CLKPLL2", - "CMT_R_TOP_UPPER_B_CLKPLL3", - "CMT_R_TOP_UPPER_B_CLKPLL4", - "CMT_R_TOP_UPPER_B_CLKPLL5", - "CMT_R_TOP_UPPER_B_CLKPLL6", - "CMT_R_TOP_UPPER_B_CLKPLL7", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_BYP0_11", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_10", - "CMT_TOP_BYP1_11", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP1_9", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_10", - "CMT_TOP_BYP2_11", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_10", - "CMT_TOP_BYP3_11", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP3_9", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_10", - "CMT_TOP_BYP4_11", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP4_9", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_10", - "CMT_TOP_BYP5_11", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP5_9", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_10", - "CMT_TOP_BYP6_11", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP6_9", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_10", - "CMT_TOP_BYP7_11", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_BYP7_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK0_9", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_10", - "CMT_TOP_CLK1_11", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CLK1_9", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL0_9", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_CTRL1_11", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_CTRL1_9", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A0_9", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_10", - "CMT_TOP_EE2A1_11", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A1_9", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_10", - "CMT_TOP_EE2A2_11", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A2_9", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_10", - "CMT_TOP_EE2A3_11", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_10", - "CMT_TOP_EE4A0_11", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A0_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_EE4A1_11", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A1_9", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_10", - "CMT_TOP_EE4A2_11", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A2_9", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_EE4A3_11", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_10", - "CMT_TOP_EE4B0_11", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B0_9", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_10", - "CMT_TOP_EE4B1_11", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B1_9", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_10", - "CMT_TOP_EE4B2_11", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B2_9", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_10", - "CMT_TOP_EE4B3_11", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4B3_9", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_10", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C0_9", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_10", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C2_9", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_EE4C3_11", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EE4C3_9", - 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"CMT_TOP_IMUX24_10", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_IMUX24_4", - "CMT_TOP_IMUX24_5", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX24_8", - "CMT_TOP_IMUX24_9", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX25_1", - "CMT_TOP_IMUX25_10", - "CMT_TOP_IMUX25_11", - "CMT_TOP_IMUX25_2", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX25_6", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX25_8", - "CMT_TOP_IMUX25_9", - "CMT_TOP_IMUX26_0", - "CMT_TOP_IMUX26_1", - "CMT_TOP_IMUX26_10", - "CMT_TOP_IMUX26_11", - "CMT_TOP_IMUX26_2", - "CMT_TOP_IMUX26_3", - "CMT_TOP_IMUX26_4", - "CMT_TOP_IMUX26_5", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX26_7", - "CMT_TOP_IMUX26_8", - "CMT_TOP_IMUX26_9", - "CMT_TOP_IMUX27_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX27_11", - "CMT_TOP_IMUX27_2", - "CMT_TOP_IMUX27_3", - "CMT_TOP_IMUX27_4", - "CMT_TOP_IMUX27_5", - "CMT_TOP_IMUX27_6", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX27_8", - "CMT_TOP_IMUX27_9", - "CMT_TOP_IMUX28_0", - "CMT_TOP_IMUX28_1", - "CMT_TOP_IMUX28_10", - "CMT_TOP_IMUX28_11", - "CMT_TOP_IMUX28_2", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX28_5", - "CMT_TOP_IMUX28_6", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX28_8", - "CMT_TOP_IMUX28_9", - "CMT_TOP_IMUX29_0", - "CMT_TOP_IMUX29_1", - "CMT_TOP_IMUX29_10", - "CMT_TOP_IMUX29_11", - "CMT_TOP_IMUX29_2", - "CMT_TOP_IMUX29_3", - "CMT_TOP_IMUX29_4", - "CMT_TOP_IMUX29_5", - "CMT_TOP_IMUX29_6", - "CMT_TOP_IMUX29_7", - "CMT_TOP_IMUX29_8", - "CMT_TOP_IMUX29_9", - "CMT_TOP_IMUX2_0", - "CMT_TOP_IMUX2_1", - "CMT_TOP_IMUX2_10", - "CMT_TOP_IMUX2_11", - "CMT_TOP_IMUX2_2", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX2_4", - "CMT_TOP_IMUX2_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_IMUX2_7", - "CMT_TOP_IMUX2_8", - "CMT_TOP_IMUX2_9", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX30_1", - "CMT_TOP_IMUX30_10", - "CMT_TOP_IMUX30_11", - "CMT_TOP_IMUX30_2", - "CMT_TOP_IMUX30_3", - "CMT_TOP_IMUX30_4", - "CMT_TOP_IMUX30_5", - "CMT_TOP_IMUX30_6", - "CMT_TOP_IMUX30_7", - "CMT_TOP_IMUX30_8", - "CMT_TOP_IMUX30_9", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX31_10", - "CMT_TOP_IMUX31_11", - "CMT_TOP_IMUX31_2", - "CMT_TOP_IMUX31_3", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX31_5", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX31_8", - "CMT_TOP_IMUX31_9", - "CMT_TOP_IMUX32_0", - "CMT_TOP_IMUX32_1", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX32_11", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX32_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_IMUX32_5", - "CMT_TOP_IMUX32_6", - "CMT_TOP_IMUX32_7", - "CMT_TOP_IMUX32_8", - "CMT_TOP_IMUX32_9", - "CMT_TOP_IMUX33_0", - "CMT_TOP_IMUX33_1", - "CMT_TOP_IMUX33_10", - "CMT_TOP_IMUX33_11", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX33_4", - "CMT_TOP_IMUX33_5", - "CMT_TOP_IMUX33_6", - "CMT_TOP_IMUX33_7", - "CMT_TOP_IMUX33_8", - "CMT_TOP_IMUX33_9", - "CMT_TOP_IMUX34_0", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX34_10", - "CMT_TOP_IMUX34_11", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX34_4", - "CMT_TOP_IMUX34_5", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX34_7", - "CMT_TOP_IMUX34_8", - "CMT_TOP_IMUX34_9", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX35_1", - "CMT_TOP_IMUX35_10", - "CMT_TOP_IMUX35_11", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX35_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_IMUX35_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_IMUX35_7", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX35_9", - "CMT_TOP_IMUX36_0", - "CMT_TOP_IMUX36_1", - "CMT_TOP_IMUX36_10", - "CMT_TOP_IMUX36_11", - "CMT_TOP_IMUX36_2", - "CMT_TOP_IMUX36_3", - "CMT_TOP_IMUX36_4", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX36_6", - "CMT_TOP_IMUX36_7", - "CMT_TOP_IMUX36_8", - "CMT_TOP_IMUX36_9", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX37_11", - "CMT_TOP_IMUX37_2", - "CMT_TOP_IMUX37_3", - "CMT_TOP_IMUX37_4", - "CMT_TOP_IMUX37_5", - "CMT_TOP_IMUX37_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_IMUX37_9", - "CMT_TOP_IMUX38_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX38_11", - "CMT_TOP_IMUX38_2", - "CMT_TOP_IMUX38_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX38_6", - "CMT_TOP_IMUX38_7", - "CMT_TOP_IMUX38_8", - "CMT_TOP_IMUX38_9", - "CMT_TOP_IMUX39_0", - "CMT_TOP_IMUX39_1", - "CMT_TOP_IMUX39_10", - "CMT_TOP_IMUX39_11", - "CMT_TOP_IMUX39_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_IMUX39_5", - "CMT_TOP_IMUX39_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX39_8", - "CMT_TOP_IMUX39_9", - "CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_10", - "CMT_TOP_IMUX3_11", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX3_9", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX40_9", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_10", - "CMT_TOP_IMUX41_11", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX41_9", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX42_11", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX42_9", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX43_9", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_10", - "CMT_TOP_IMUX44_11", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX45_11", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX45_9", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_10", - "CMT_TOP_IMUX46_11", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX46_9", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX47_11", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX47_9", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_10", - "CMT_TOP_IMUX4_11", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX4_9", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX5_11", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_10", - "CMT_TOP_IMUX6_11", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX6_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_10", - "CMT_TOP_IMUX7_11", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX7_9", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_10", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX9_9", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_10", - "CMT_TOP_LH10_11", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH10_9", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_10", - "CMT_TOP_LH11_11", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH11_9", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_10", - "CMT_TOP_LH12_11", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH12_9", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_10", - "CMT_TOP_LH1_11", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH1_9", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_10", - "CMT_TOP_LH2_11", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH2_9", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_10", - "CMT_TOP_LH3_11", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH3_9", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_10", - "CMT_TOP_LH4_11", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH4_9", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_10", - "CMT_TOP_LH5_11", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH5_9", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_10", - "CMT_TOP_LH6_11", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH6_9", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_10", - "CMT_TOP_LH7_11", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH7_9", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_10", - "CMT_TOP_LH8_11", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH8_9", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_10", - "CMT_TOP_LH9_11", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LH9_9", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_10", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_10", - "CMT_TOP_NE2A0_11", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A0_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_10", - "CMT_TOP_NE2A1_11", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_10", - "CMT_TOP_NE2A2_11", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A2_9", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_10", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_10", - "CMT_TOP_NE4C0_11", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_9", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_NE4C1_11", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C1_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_10", - "CMT_TOP_NE4C2_11", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C2_9", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_10", - "CMT_TOP_NE4C3_11", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NE4C3_9", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_10", - "CMT_TOP_NW2A0_11", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A0_9", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_10", - "CMT_TOP_NW2A1_11", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_10", - "CMT_TOP_NW2A2_11", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A2_9", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW2A3_11", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW2A3_9", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_10", - "CMT_TOP_NW4A0_11", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_10", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A1_9", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW4A2_11", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A2_9", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_10", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_10", - "CMT_TOP_NW4END0_11", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END0_9", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_10", - "CMT_TOP_NW4END1_11", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END1_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_10", - "CMT_TOP_NW4END2_11", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END2_9", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4END3_11", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_NW4END3_9", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_10", - "CMT_TOP_OCLK_11", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_OCLK_9", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_10", - "CMT_TOP_SE2A0_11", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A0_9", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_10", - "CMT_TOP_SE2A1_11", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A1_9", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_10", - "CMT_TOP_SE2A2_11", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_10", - "CMT_TOP_SE2A3_11", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE2A3_9", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_10", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C0_9", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_10", - "CMT_TOP_SE4C1_11", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C1_9", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_10", - "CMT_TOP_SE4C2_11", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C2_9", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_10", - "CMT_TOP_SE4C3_11", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SE4C3_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SW2A0_11", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A0_9", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_10", - "CMT_TOP_SW2A1_11", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A1_9", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_10", - "CMT_TOP_SW2A2_11", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A2_9", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_10", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW2A3_9", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_SW4A0_11", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_10", - "CMT_TOP_SW4A1_11", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_10", - "CMT_TOP_SW4A2_11", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A2_9", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_10", - "CMT_TOP_SW4A3_11", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4A3_9", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_10", - "CMT_TOP_SW4END0_11", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END0_9", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_10", - "CMT_TOP_SW4END1_11", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END1_9", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_SW4END2_11", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END2_9", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_10", - "CMT_TOP_SW4END3_11", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_SW4END3_9", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_10", - "CMT_TOP_WL1END0_11", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END0_9", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_10", - "CMT_TOP_WL1END1_11", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END1_9", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_10", - "CMT_TOP_WL1END2_11", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END2_9", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_10", - "CMT_TOP_WL1END3_11", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WL1END3_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END0_11", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END1_9", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_10", - "CMT_TOP_WR1END2_11", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END2_9", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_10", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WR1END3_9", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_10", - "CMT_TOP_WW2A0_11", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A0_9", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_10", - "CMT_TOP_WW2A1_11", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A1_9", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_10", - "CMT_TOP_WW2A2_11", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A2_9", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_10", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2A3_9", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_10", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_10", - "CMT_TOP_WW2END1_11", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END1_9", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_10", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_10", - "CMT_TOP_WW2END3_11", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW2END3_9", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_10", - "CMT_TOP_WW4A0_11", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_10", - "CMT_TOP_WW4A1_11", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_10", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A2_9", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_10", - "CMT_TOP_WW4A3_11", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4A3_9", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_10", - "CMT_TOP_WW4B0_11", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_9", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_10", - "CMT_TOP_WW4B1_11", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_10", - "CMT_TOP_WW4B2_11", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_10", - "CMT_TOP_WW4B3_11", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4B3_9", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_10", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C0_9", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C1_9", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_10", - "CMT_TOP_WW4C2_11", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C2_9", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4C3_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END0_9", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_10", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END1_9", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END2_9", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_10", - "CMT_TOP_WW4END3_11", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4END3_9", - "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "PLL_CLK_FREQBB_REBUFOUT0", - "PLL_CLK_FREQBB_REBUFOUT1", - "PLL_CLK_FREQBB_REBUFOUT2", - "PLL_CLK_FREQBB_REBUFOUT3" - ] + "wires": { + "CMT_FREQ_BB_PREF_IN0": null, + "CMT_FREQ_BB_PREF_IN1": null, + "CMT_FREQ_BB_PREF_IN2": null, + "CMT_FREQ_BB_PREF_IN3": null, + "CMT_FREQ_PHASER_REFMUX_0": null, + "CMT_FREQ_PHASER_REFMUX_1": null, + "CMT_FREQ_PHASER_REFMUX_2": null, + "CMT_L_TOP_UPPER_B_CLKINT_2": null, + "CMT_L_TOP_UPPER_B_CLKINT_3": null, + "CMT_PHASERD_CTSBUS0": null, + "CMT_PHASERD_CTSBUS1": null, + "CMT_PHASERD_DQSBUS0": null, + "CMT_PHASERD_DQSBUS1": null, + "CMT_PHASERD_DTSBUS0": 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"CMT_PHASER_IN_CA_COUNTERREADVAL2": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL3": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL4": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL5": null, + "CMT_PHASER_IN_CA_DIVIDERST": null, + "CMT_PHASER_IN_CA_DQSFOUND": null, + "CMT_PHASER_IN_CA_DQSOUTOFRANGE": null, + "CMT_PHASER_IN_CA_EDGEADV": null, + "CMT_PHASER_IN_CA_ENCALIB0": null, + "CMT_PHASER_IN_CA_ENCALIB1": null, + "CMT_PHASER_IN_CA_ENCALIBPHY0": null, + "CMT_PHASER_IN_CA_ENCALIBPHY1": null, + "CMT_PHASER_IN_CA_ENSTG1": null, + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB": null, + "CMT_PHASER_IN_CA_FINEENABLE": null, + "CMT_PHASER_IN_CA_FINEINC": null, + "CMT_PHASER_IN_CA_FINEOVERFLOW": null, + "CMT_PHASER_IN_CA_FREQREFCLK": null, + "CMT_PHASER_IN_CA_ICLK": null, + "CMT_PHASER_IN_CA_ICLKDIV": null, + "CMT_PHASER_IN_CA_ISERDESRST": null, + "CMT_PHASER_IN_CA_MEMREFCLK": null, + "CMT_PHASER_IN_CA_PHASELOCKED": null, + "CMT_PHASER_IN_CA_PHASEREFCLK": null, + "CMT_PHASER_IN_CA_RANKSEL0": null, + "CMT_PHASER_IN_CA_RANKSEL1": null, + "CMT_PHASER_IN_CA_RANKSELPHY0": null, + "CMT_PHASER_IN_CA_RANKSELPHY1": null, + "CMT_PHASER_IN_CA_RCLK": null, + "CMT_PHASER_IN_CA_RST": null, + "CMT_PHASER_IN_CA_RSTDQSFIND": null, + "CMT_PHASER_IN_CA_SCANCLK": null, + "CMT_PHASER_IN_CA_SCANENB": null, + "CMT_PHASER_IN_CA_SCANIN": null, + "CMT_PHASER_IN_CA_SCANMODEB": null, + "CMT_PHASER_IN_CA_SCANOUT": null, + "CMT_PHASER_IN_CA_SELCALORSTG1": null, + "CMT_PHASER_IN_CA_STG1INCDEC": null, + "CMT_PHASER_IN_CA_STG1LOAD": null, + "CMT_PHASER_IN_CA_STG1OVERFLOW": null, + "CMT_PHASER_IN_CA_STG1READ": null, + "CMT_PHASER_IN_CA_STG1REGL0": null, + "CMT_PHASER_IN_CA_STG1REGL1": null, + "CMT_PHASER_IN_CA_STG1REGL2": null, + "CMT_PHASER_IN_CA_STG1REGL3": null, + "CMT_PHASER_IN_CA_STG1REGL4": null, + "CMT_PHASER_IN_CA_STG1REGL5": null, + "CMT_PHASER_IN_CA_STG1REGL6": null, + "CMT_PHASER_IN_CA_STG1REGL7": null, + "CMT_PHASER_IN_CA_STG1REGL8": null, + "CMT_PHASER_IN_CA_STG1REGR0": null, + "CMT_PHASER_IN_CA_STG1REGR1": null, + "CMT_PHASER_IN_CA_STG1REGR2": null, + "CMT_PHASER_IN_CA_STG1REGR3": null, + "CMT_PHASER_IN_CA_STG1REGR4": null, + "CMT_PHASER_IN_CA_STG1REGR5": null, + "CMT_PHASER_IN_CA_STG1REGR6": null, + "CMT_PHASER_IN_CA_STG1REGR7": null, + "CMT_PHASER_IN_CA_STG1REGR8": null, + "CMT_PHASER_IN_CA_SYNCIN": null, + "CMT_PHASER_IN_CA_SYSCLK": null, + "CMT_PHASER_IN_CA_TESTIN0": null, + "CMT_PHASER_IN_CA_TESTIN1": null, + "CMT_PHASER_IN_CA_TESTIN10": null, + "CMT_PHASER_IN_CA_TESTIN11": null, + "CMT_PHASER_IN_CA_TESTIN12": null, + "CMT_PHASER_IN_CA_TESTIN13": null, + "CMT_PHASER_IN_CA_TESTIN2": null, + "CMT_PHASER_IN_CA_TESTIN3": null, + "CMT_PHASER_IN_CA_TESTIN4": null, + "CMT_PHASER_IN_CA_TESTIN5": null, + "CMT_PHASER_IN_CA_TESTIN6": null, + "CMT_PHASER_IN_CA_TESTIN7": null, + "CMT_PHASER_IN_CA_TESTIN8": null, + "CMT_PHASER_IN_CA_TESTIN9": null, + "CMT_PHASER_IN_CA_TESTOUT0": null, + "CMT_PHASER_IN_CA_TESTOUT1": null, + "CMT_PHASER_IN_CA_TESTOUT2": null, + "CMT_PHASER_IN_CA_TESTOUT3": null, + "CMT_PHASER_IN_CA_WRENABLE": null, + "CMT_PHASER_IN_C_ICLK": null, + "CMT_PHASER_IN_C_ICLKDIV": null, + "CMT_PHASER_IN_C_RCLK2": null, + "CMT_PHASER_IN_C_WRENABLE_FIFO": null, + "CMT_PHASER_IN_DB_BURSTPENDING": null, + "CMT_PHASER_IN_DB_BURSTPENDINGPHY": null, + "CMT_PHASER_IN_DB_COUNTERLOADEN": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL0": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL1": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL2": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL3": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL4": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL5": null, + "CMT_PHASER_IN_DB_COUNTERREADEN": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL0": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL1": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL2": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL3": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL4": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL5": null, + "CMT_PHASER_IN_DB_DIVIDERST": null, + "CMT_PHASER_IN_DB_DQSFOUND": null, + "CMT_PHASER_IN_DB_DQSOUTOFRANGE": null, + "CMT_PHASER_IN_DB_EDGEADV": null, + "CMT_PHASER_IN_DB_ENCALIB0": null, + "CMT_PHASER_IN_DB_ENCALIB1": null, + "CMT_PHASER_IN_DB_ENCALIBPHY0": null, + "CMT_PHASER_IN_DB_ENCALIBPHY1": null, + "CMT_PHASER_IN_DB_ENSTG1": null, + "CMT_PHASER_IN_DB_ENSTG1ADJUSTB": null, + "CMT_PHASER_IN_DB_FINEENABLE": null, + "CMT_PHASER_IN_DB_FINEINC": null, + "CMT_PHASER_IN_DB_FINEOVERFLOW": null, + "CMT_PHASER_IN_DB_FREQREFCLK": null, + "CMT_PHASER_IN_DB_ICLK": null, + "CMT_PHASER_IN_DB_ICLKDIV": null, + "CMT_PHASER_IN_DB_ISERDESRST": null, + "CMT_PHASER_IN_DB_MEMREFCLK": null, + "CMT_PHASER_IN_DB_PHASELOCKED": null, + "CMT_PHASER_IN_DB_PHASEREFCLK": null, + "CMT_PHASER_IN_DB_RANKSEL0": null, + "CMT_PHASER_IN_DB_RANKSEL1": null, + "CMT_PHASER_IN_DB_RANKSELPHY0": null, + "CMT_PHASER_IN_DB_RANKSELPHY1": null, + "CMT_PHASER_IN_DB_RCLK": null, + "CMT_PHASER_IN_DB_RST": null, + "CMT_PHASER_IN_DB_RSTDQSFIND": null, + "CMT_PHASER_IN_DB_SCANCLK": null, + "CMT_PHASER_IN_DB_SCANENB": null, + "CMT_PHASER_IN_DB_SCANIN": null, + "CMT_PHASER_IN_DB_SCANMODEB": null, + "CMT_PHASER_IN_DB_SCANOUT": null, + "CMT_PHASER_IN_DB_SELCALORSTG1": null, + "CMT_PHASER_IN_DB_STG1INCDEC": null, + "CMT_PHASER_IN_DB_STG1LOAD": null, + "CMT_PHASER_IN_DB_STG1OVERFLOW": null, + "CMT_PHASER_IN_DB_STG1READ": null, + "CMT_PHASER_IN_DB_STG1REGL0": null, + "CMT_PHASER_IN_DB_STG1REGL1": null, + "CMT_PHASER_IN_DB_STG1REGL2": null, + "CMT_PHASER_IN_DB_STG1REGL3": null, + "CMT_PHASER_IN_DB_STG1REGL4": null, + "CMT_PHASER_IN_DB_STG1REGL5": null, + "CMT_PHASER_IN_DB_STG1REGL6": null, + "CMT_PHASER_IN_DB_STG1REGL7": null, + "CMT_PHASER_IN_DB_STG1REGL8": null, + "CMT_PHASER_IN_DB_STG1REGR0": null, + "CMT_PHASER_IN_DB_STG1REGR1": null, + "CMT_PHASER_IN_DB_STG1REGR2": null, + "CMT_PHASER_IN_DB_STG1REGR3": null, + "CMT_PHASER_IN_DB_STG1REGR4": null, + "CMT_PHASER_IN_DB_STG1REGR5": null, + "CMT_PHASER_IN_DB_STG1REGR6": null, + "CMT_PHASER_IN_DB_STG1REGR7": null, + "CMT_PHASER_IN_DB_STG1REGR8": null, + "CMT_PHASER_IN_DB_SYNCIN": null, + "CMT_PHASER_IN_DB_SYSCLK": null, + "CMT_PHASER_IN_DB_TESTIN0": null, + "CMT_PHASER_IN_DB_TESTIN1": null, + "CMT_PHASER_IN_DB_TESTIN10": null, + "CMT_PHASER_IN_DB_TESTIN11": null, + "CMT_PHASER_IN_DB_TESTIN12": null, + "CMT_PHASER_IN_DB_TESTIN13": null, + "CMT_PHASER_IN_DB_TESTIN2": null, + "CMT_PHASER_IN_DB_TESTIN3": null, + "CMT_PHASER_IN_DB_TESTIN4": null, + "CMT_PHASER_IN_DB_TESTIN5": null, + "CMT_PHASER_IN_DB_TESTIN6": null, + "CMT_PHASER_IN_DB_TESTIN7": null, + "CMT_PHASER_IN_DB_TESTIN8": null, + "CMT_PHASER_IN_DB_TESTIN9": null, + "CMT_PHASER_IN_DB_TESTOUT0": null, + "CMT_PHASER_IN_DB_TESTOUT1": null, + "CMT_PHASER_IN_DB_TESTOUT2": null, + "CMT_PHASER_IN_DB_TESTOUT3": null, + "CMT_PHASER_IN_DB_WRENABLE": null, + "CMT_PHASER_IN_D_ICLK": null, + "CMT_PHASER_IN_D_ICLKDIV": null, + "CMT_PHASER_IN_D_RCLK3": null, + "CMT_PHASER_IN_D_WRENABLE_FIFO": null, + "CMT_PHASER_OUT_CA_BURSTPENDING": null, + "CMT_PHASER_OUT_CA_BURSTPENDINGPHY": null, + "CMT_PHASER_OUT_CA_COARSEENABLE": null, + "CMT_PHASER_OUT_CA_COARSEINC": null, + "CMT_PHASER_OUT_CA_COARSEOVERFLOW": null, + "CMT_PHASER_OUT_CA_COUNTERLOADEN": null, + "CMT_PHASER_OUT_CA_COUNTERLOADVAL0": null, + "CMT_PHASER_OUT_CA_COUNTERLOADVAL1": null, + "CMT_PHASER_OUT_CA_COUNTERLOADVAL2": null, + "CMT_PHASER_OUT_CA_COUNTERLOADVAL3": null, + "CMT_PHASER_OUT_CA_COUNTERLOADVAL4": null, + "CMT_PHASER_OUT_CA_COUNTERLOADVAL5": null, + "CMT_PHASER_OUT_CA_COUNTERLOADVAL6": null, + "CMT_PHASER_OUT_CA_COUNTERLOADVAL7": null, + "CMT_PHASER_OUT_CA_COUNTERLOADVAL8": null, + "CMT_PHASER_OUT_CA_COUNTERREADEN": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL0": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL1": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL2": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL3": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL4": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL5": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL6": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL7": null, + "CMT_PHASER_OUT_CA_COUNTERREADVAL8": null, + "CMT_PHASER_OUT_CA_CTSBUS0": null, + "CMT_PHASER_OUT_CA_CTSBUS1": null, + "CMT_PHASER_OUT_CA_DIVIDERST": null, + "CMT_PHASER_OUT_CA_DQSBUS0": null, + "CMT_PHASER_OUT_CA_DQSBUS1": null, + "CMT_PHASER_OUT_CA_DTSBUS0": null, + "CMT_PHASER_OUT_CA_DTSBUS1": null, + "CMT_PHASER_OUT_CA_EDGEADV": null, + "CMT_PHASER_OUT_CA_ENCALIB0": null, + "CMT_PHASER_OUT_CA_ENCALIB1": null, + "CMT_PHASER_OUT_CA_ENCALIBPHY0": null, + "CMT_PHASER_OUT_CA_ENCALIBPHY1": null, + "CMT_PHASER_OUT_CA_FINEENABLE": null, + "CMT_PHASER_OUT_CA_FINEINC": null, + "CMT_PHASER_OUT_CA_FINEOVERFLOW": null, + "CMT_PHASER_OUT_CA_FREQREFCLK": null, + "CMT_PHASER_OUT_CA_MEMREFCLK": null, + "CMT_PHASER_OUT_CA_OCLK": null, + "CMT_PHASER_OUT_CA_OCLKDELAYED": null, + "CMT_PHASER_OUT_CA_OCLKDIV": null, + "CMT_PHASER_OUT_CA_OSERDESRST": null, + "CMT_PHASER_OUT_CA_PHASEREFCLK": null, + "CMT_PHASER_OUT_CA_RDENABLE": null, + "CMT_PHASER_OUT_CA_RST": null, + "CMT_PHASER_OUT_CA_SCANCLK": null, + "CMT_PHASER_OUT_CA_SCANENB": null, + "CMT_PHASER_OUT_CA_SCANIN": null, + "CMT_PHASER_OUT_CA_SCANMODEB": null, + "CMT_PHASER_OUT_CA_SCANOUT": null, + "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": null, + "CMT_PHASER_OUT_CA_SYNCIN": null, + "CMT_PHASER_OUT_CA_SYSCLK": null, + "CMT_PHASER_OUT_CA_TESTIN0": null, + "CMT_PHASER_OUT_CA_TESTIN1": null, + "CMT_PHASER_OUT_CA_TESTIN10": null, + "CMT_PHASER_OUT_CA_TESTIN11": null, + "CMT_PHASER_OUT_CA_TESTIN12": null, + "CMT_PHASER_OUT_CA_TESTIN13": null, + "CMT_PHASER_OUT_CA_TESTIN14": null, + "CMT_PHASER_OUT_CA_TESTIN15": null, + "CMT_PHASER_OUT_CA_TESTIN2": null, + "CMT_PHASER_OUT_CA_TESTIN3": null, + "CMT_PHASER_OUT_CA_TESTIN4": null, + "CMT_PHASER_OUT_CA_TESTIN5": null, + "CMT_PHASER_OUT_CA_TESTIN6": null, + "CMT_PHASER_OUT_CA_TESTIN7": null, + "CMT_PHASER_OUT_CA_TESTIN8": null, + "CMT_PHASER_OUT_CA_TESTIN9": null, + "CMT_PHASER_OUT_CA_TESTOUT0": null, + "CMT_PHASER_OUT_CA_TESTOUT1": null, + "CMT_PHASER_OUT_CA_TESTOUT2": null, + "CMT_PHASER_OUT_CA_TESTOUT3": null, + "CMT_PHASER_OUT_C_OCLK": null, + "CMT_PHASER_OUT_C_OCLK1X_90": null, + "CMT_PHASER_OUT_C_OCLKDIV": null, + "CMT_PHASER_OUT_DB_BURSTPENDING": null, + "CMT_PHASER_OUT_DB_BURSTPENDINGPHY": null, + "CMT_PHASER_OUT_DB_COARSEENABLE": null, + "CMT_PHASER_OUT_DB_COARSEINC": null, + "CMT_PHASER_OUT_DB_COARSEOVERFLOW": null, + "CMT_PHASER_OUT_DB_COUNTERLOADEN": null, + "CMT_PHASER_OUT_DB_COUNTERLOADVAL0": null, + "CMT_PHASER_OUT_DB_COUNTERLOADVAL1": null, + "CMT_PHASER_OUT_DB_COUNTERLOADVAL2": null, + "CMT_PHASER_OUT_DB_COUNTERLOADVAL3": null, + "CMT_PHASER_OUT_DB_COUNTERLOADVAL4": null, + "CMT_PHASER_OUT_DB_COUNTERLOADVAL5": null, + "CMT_PHASER_OUT_DB_COUNTERLOADVAL6": null, + "CMT_PHASER_OUT_DB_COUNTERLOADVAL7": null, + "CMT_PHASER_OUT_DB_COUNTERLOADVAL8": null, + "CMT_PHASER_OUT_DB_COUNTERREADEN": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL0": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL1": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL2": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL3": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL4": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL5": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL6": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL7": null, + "CMT_PHASER_OUT_DB_COUNTERREADVAL8": null, + "CMT_PHASER_OUT_DB_CTSBUS0": null, + "CMT_PHASER_OUT_DB_CTSBUS1": null, + "CMT_PHASER_OUT_DB_DIVIDERST": null, + "CMT_PHASER_OUT_DB_DQSBUS0": null, + "CMT_PHASER_OUT_DB_DQSBUS1": null, + "CMT_PHASER_OUT_DB_DTSBUS0": null, + "CMT_PHASER_OUT_DB_DTSBUS1": null, + "CMT_PHASER_OUT_DB_EDGEADV": null, + "CMT_PHASER_OUT_DB_ENCALIB0": null, + "CMT_PHASER_OUT_DB_ENCALIB1": null, + "CMT_PHASER_OUT_DB_ENCALIBPHY0": null, + "CMT_PHASER_OUT_DB_ENCALIBPHY1": null, + "CMT_PHASER_OUT_DB_FINEENABLE": null, + "CMT_PHASER_OUT_DB_FINEINC": null, + "CMT_PHASER_OUT_DB_FINEOVERFLOW": null, + "CMT_PHASER_OUT_DB_FREQREFCLK": null, + "CMT_PHASER_OUT_DB_MEMREFCLK": null, + "CMT_PHASER_OUT_DB_OCLK": null, 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"CMT_PHASER_OUT_DB_TESTIN6": null, + "CMT_PHASER_OUT_DB_TESTIN7": null, + "CMT_PHASER_OUT_DB_TESTIN8": null, + "CMT_PHASER_OUT_DB_TESTIN9": null, + "CMT_PHASER_OUT_DB_TESTOUT0": null, + "CMT_PHASER_OUT_DB_TESTOUT1": null, + "CMT_PHASER_OUT_DB_TESTOUT2": null, + "CMT_PHASER_OUT_DB_TESTOUT3": null, + "CMT_PHASER_OUT_D_OCLK": null, + "CMT_PHASER_OUT_D_OCLK1X_90": null, + "CMT_PHASER_OUT_D_OCLKDIV": null, + "CMT_PHASER_REF_CLKIN": null, + "CMT_PHASER_REF_CLKOUT": null, + "CMT_PHASER_REF_CLKOUT_TOHCLK": null, + "CMT_PHASER_REF_LOCKED": null, + "CMT_PHASER_REF_PWRDWN": null, + "CMT_PHASER_REF_RST": null, + "CMT_PHASER_REF_TESTIN0": null, + "CMT_PHASER_REF_TESTIN1": null, + "CMT_PHASER_REF_TESTIN2": null, + "CMT_PHASER_REF_TESTIN3": null, + "CMT_PHASER_REF_TESTIN4": null, + "CMT_PHASER_REF_TESTIN5": null, + "CMT_PHASER_REF_TESTIN6": null, + "CMT_PHASER_REF_TESTIN7": null, + "CMT_PHASER_REF_TESTOUT0": null, + "CMT_PHASER_REF_TESTOUT1": null, + "CMT_PHASER_REF_TESTOUT2": null, + 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"CMT_PHY_CONTROL_INRANKD0": { + "cap": "1.000", + "res": "0.035" + }, + "CMT_PHY_CONTROL_INRANKD1": { + "cap": "1.000", + "res": "0.035" + }, + "CMT_PHY_CONTROL_IRANKA0": null, + "CMT_PHY_CONTROL_IRANKA1": null, + "CMT_PHY_CONTROL_IRANKB0": null, + "CMT_PHY_CONTROL_IRANKB1": null, + "CMT_PHY_CONTROL_IRANKC0": null, + "CMT_PHY_CONTROL_IRANKC1": null, + "CMT_PHY_CONTROL_IRANKD0": null, + "CMT_PHY_CONTROL_IRANKD1": null, + "CMT_PHY_CONTROL_MEMREFCLK": { + "cap": "5.300", + "res": "0.000" + }, + "CMT_PHY_CONTROL_OBURSTPENDING0": null, + "CMT_PHY_CONTROL_OBURSTPENDING1": null, + "CMT_PHY_CONTROL_OBURSTPENDING2": null, + "CMT_PHY_CONTROL_OBURSTPENDING3": null, + "CMT_PHY_CONTROL_OUTBURSTPENDING0": { + "cap": "1.000", + "res": "0.038" + }, + "CMT_PHY_CONTROL_OUTBURSTPENDING1": { + "cap": "1.000", + "res": "0.038" + }, + "CMT_PHY_CONTROL_OUTBURSTPENDING2": { + "cap": "1.000", + "res": "0.038" + }, + "CMT_PHY_CONTROL_OUTBURSTPENDING3": { + "cap": "1.000", + "res": "0.038" + }, + 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"CMT_PHY_CONTROL_PHYCTLWD13": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD14": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD15": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD16": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD17": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD18": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD19": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD2": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD20": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD21": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD22": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD23": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD24": { + "cap": "3.100", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PHYCTLWD25": { + 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"CMT_PHY_CONTROL_PHYCTLWRENABLE": { + "cap": "1.700", + "res": "0.000" + }, + "CMT_PHY_CONTROL_PLLLOCK": { + "cap": "3.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_READCALIBENABLE": null, + "CMT_PHY_CONTROL_REFDLLLOCK": { + "cap": "1.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_RESET": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_SCANENABLEN": { + "cap": "3.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_SYNCIN": { + "cap": "15.700", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTINPUT0": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTINPUT1": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTINPUT10": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTINPUT11": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTINPUT12": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTINPUT13": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTINPUT14": { + "cap": "5.000", + "res": "0.000" + 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"CMT_PHY_CONTROL_TESTOUTPUT12": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT13": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT14": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT15": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT2": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT3": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT4": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT5": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT6": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT7": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT8": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTOUTPUT9": { + "cap": "0.032", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTSELECT0": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTSELECT1": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_TESTSELECT2": { + "cap": "5.000", + "res": "0.000" + }, + "CMT_PHY_CONTROL_WRITECALIBENABLE": null, + "CMT_R_PHASER_IN_C_WRCLK_FIFO": null, + "CMT_R_PHASER_IN_D_WRCLK_TOFIFO": null, + "CMT_R_PHASER_OUT_C_RDCLK_FIFO": null, + "CMT_R_PHASER_OUT_C_RDENABLE_FIFO": null, + "CMT_R_PHASER_OUT_D_RDCLK_TOFIFO": null, + "CMT_R_PHASER_OUT_D_RDENABLE_TOFIFO": null, + "CMT_R_TOP_UPPER_B_CLKFBIN": null, + "CMT_R_TOP_UPPER_B_CLKIN1": null, + "CMT_R_TOP_UPPER_B_CLKIN2": null, + "CMT_R_TOP_UPPER_B_CLKPLL0": null, + "CMT_R_TOP_UPPER_B_CLKPLL1": null, + "CMT_R_TOP_UPPER_B_CLKPLL2": null, + "CMT_R_TOP_UPPER_B_CLKPLL3": null, + "CMT_R_TOP_UPPER_B_CLKPLL4": null, + "CMT_R_TOP_UPPER_B_CLKPLL5": null, + "CMT_R_TOP_UPPER_B_CLKPLL6": null, + "CMT_R_TOP_UPPER_B_CLKPLL7": null, + "CMT_TOP_BLOCK_OUTS_L_B0_0": null, + "CMT_TOP_BLOCK_OUTS_L_B0_1": null, + "CMT_TOP_BLOCK_OUTS_L_B0_10": null, + "CMT_TOP_BLOCK_OUTS_L_B0_11": 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"PLL_CLK_FREQBB_REBUFOUT2": null, + "PLL_CLK_FREQBB_REBUFOUT3": null + } } diff --git a/kintex7/tile_type_CMT_TOP_L_UPPER_T.json b/kintex7/tile_type_CMT_TOP_L_UPPER_T.json index 3a35ee0..3ef38a0 100644 --- a/kintex7/tile_type_CMT_TOP_L_UPPER_T.json +++ b/kintex7/tile_type_CMT_TOP_L_UPPER_T.json @@ -2,1087 +2,4262 @@ "pips": { "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.101", + "0.116", + "0.164", + "0.188" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_ICLKDIV_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.101", + "0.116", + "0.164", + "0.188" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_D_ICLKDIV_TOIOI" }, "CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.101", + "0.116", + "0.164", + "0.188" + ], + "in_cap": "0.000", + "res": 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}, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO14->>CMT_TOP_LOGIC_OUTS_L_B18_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO14" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO15->>CMT_TOP_LOGIC_OUTS_L_B8_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B8_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO15" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO2->>CMT_TOP_LOGIC_OUTS_L_B21_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO2" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO3->>CMT_TOP_LOGIC_OUTS_L_B15_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO3" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO4->>CMT_TOP_LOGIC_OUTS_L_B20_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B20_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO4" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO5->>CMT_TOP_LOGIC_OUTS_L_B2_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO5" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO6->>CMT_TOP_LOGIC_OUTS_L_B16_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO6" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO7->>CMT_TOP_LOGIC_OUTS_L_B10_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO7" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO8->>CMT_TOP_LOGIC_OUTS_L_B19_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO8" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO9->>CMT_TOP_LOGIC_OUTS_L_B5_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO9" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DRDY" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B21_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED" }, "CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT->>CMT_TOP_L_UPPER_T_CLKPLL7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_CLKPLL7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS->>CMT_TOP_L_UPPER_T_FREQ_BB0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB0_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB0_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS0", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB0_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS->>CMT_TOP_L_UPPER_T_FREQ_BB1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB1_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB1_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS1", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB1_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS->>CMT_TOP_L_UPPER_T_FREQ_BB2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB2_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB2_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS2", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB2_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS->>CMT_TOP_L_UPPER_T_FREQ_BB3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_L_UPPER_T_FREQ_BB3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB3_NS" }, "CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS3", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB3_NS" } }, @@ -1091,160 +4266,1546 @@ "name": "X0Y0", "prefix": "PLLE2_ADV", "site_pins": { - "CLKFBIN": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CLKFBOUT": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "CLKIN1": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "CLKIN2": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "CLKINSEL": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "CLKOUT0": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "CLKOUT1": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "CLKOUT2": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CLKOUT3": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "CLKOUT4": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "CLKOUT5": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "DADDR0": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "DADDR1": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "DADDR2": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "DADDR3": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "DADDR4": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "DADDR5": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "DADDR6": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "DCLK": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "DEN": "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "DI0": "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "DI1": "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "DI10": "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "DI11": "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "DI12": "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "DI13": "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "DI14": "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "DI15": "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "DI2": "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "DI3": "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "DI4": "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "DI5": "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "DI6": "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "DI7": "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "DI8": "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "DI9": "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "DO0": "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "DO1": "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "DO10": "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "DO11": "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "DO12": "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "DO13": "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "DO14": "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "DO15": "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "DO2": "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "DO3": "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "DO4": "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "DO5": "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "DO6": "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "DO7": "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "DO8": "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "DO9": "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "DRDY": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "DWE": "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "LOCKED": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "PWRDWN": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "RST": "CMT_TOP_R_UPPER_T_PLLE2_RST", - "TESTIN0": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "TESTIN1": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "TESTIN10": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "TESTIN11": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "TESTIN12": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "TESTIN13": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "TESTIN14": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "TESTIN15": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "TESTIN16": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "TESTIN17": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "TESTIN18": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "TESTIN19": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "TESTIN2": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "TESTIN20": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "TESTIN21": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "TESTIN22": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "TESTIN23": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "TESTIN24": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "TESTIN25": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "TESTIN26": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", - "TESTIN27": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", - "TESTIN28": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", - "TESTIN29": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", - "TESTIN3": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", - "TESTIN30": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", - "TESTIN31": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", - "TESTIN4": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", - "TESTIN5": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", - "TESTIN6": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", - "TESTIN7": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", - "TESTIN8": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", - "TESTIN9": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", - "TESTOUT0": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", - "TESTOUT1": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", - "TESTOUT10": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", - "TESTOUT11": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", - "TESTOUT12": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", - "TESTOUT13": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", - "TESTOUT14": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", - "TESTOUT15": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", - "TESTOUT16": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", - "TESTOUT17": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", - "TESTOUT18": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", - "TESTOUT19": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", - "TESTOUT2": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", - "TESTOUT20": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", - "TESTOUT21": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", - "TESTOUT22": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", - "TESTOUT23": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", - "TESTOUT24": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", - "TESTOUT25": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", - "TESTOUT26": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", - "TESTOUT27": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", - "TESTOUT28": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", - "TESTOUT29": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", - "TESTOUT3": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", - "TESTOUT30": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", - "TESTOUT31": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", - "TESTOUT32": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", - "TESTOUT33": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", - "TESTOUT34": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", - "TESTOUT35": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", - "TESTOUT36": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", - "TESTOUT37": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", - "TESTOUT38": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", - "TESTOUT39": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", - "TESTOUT4": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", - "TESTOUT40": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", - "TESTOUT41": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", - "TESTOUT42": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", - "TESTOUT43": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", - "TESTOUT44": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", - "TESTOUT45": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", - "TESTOUT46": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", - "TESTOUT47": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", - "TESTOUT48": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", - "TESTOUT49": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", - "TESTOUT5": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", - "TESTOUT50": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", - "TESTOUT51": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", - "TESTOUT52": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", - "TESTOUT53": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", - "TESTOUT54": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", - "TESTOUT55": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", - "TESTOUT56": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", - "TESTOUT57": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", - "TESTOUT58": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", - "TESTOUT59": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", - "TESTOUT6": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", - "TESTOUT60": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", - "TESTOUT61": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", - "TESTOUT62": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", - "TESTOUT63": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", - "TESTOUT7": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", - "TESTOUT8": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", - "TESTOUT9": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", - "TMUXOUT": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT" + "CLKFBIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN" + }, + "CLKFBOUT": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT" + }, + "CLKIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1" + }, + "CLKIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2" + }, + "CLKINSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL" + }, + "CLKOUT0": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0" + }, + "CLKOUT1": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1" + }, + "CLKOUT2": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2" + }, + "CLKOUT3": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3" + }, + "CLKOUT4": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4" + }, + "CLKOUT5": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5" + }, + "DADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0" + }, + "DADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1" + }, + "DADDR2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2" + }, + "DADDR3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3" + }, + "DADDR4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4" + }, + "DADDR5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5" + }, + "DADDR6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6" + }, + "DCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DCLK" + }, + "DEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DEN" + }, + "DI0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DI0" + }, + "DI1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DI1" + }, + "DI10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DI10" + }, + "DI11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DI11" + }, + "DI12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DI12" + }, + "DI13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DI13" + }, + "DI14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DI14" + }, + "DI15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_TOP_R_UPPER_T_PLLE2_DI15" + }, + "DI2": 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"CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_BLOCK_OUTS_L_B2_12", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_12", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_BYP0_11", - "CMT_TOP_BYP0_12", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_10", - "CMT_TOP_BYP1_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP1_9", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_10", - "CMT_TOP_BYP2_11", - "CMT_TOP_BYP2_12", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_10", - "CMT_TOP_BYP3_11", - "CMT_TOP_BYP3_12", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP3_9", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_10", - "CMT_TOP_BYP4_11", - "CMT_TOP_BYP4_12", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP4_9", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_10", - "CMT_TOP_BYP5_11", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP5_9", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_10", - "CMT_TOP_BYP6_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP6_9", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_10", - "CMT_TOP_BYP7_11", - "CMT_TOP_BYP7_12", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_BYP7_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_CLK0_12", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK0_9", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_10", - "CMT_TOP_CLK1_11", - "CMT_TOP_CLK1_12", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CLK1_9", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CTRL0_12", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL0_9", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_CTRL1_11", - "CMT_TOP_CTRL1_12", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_CTRL1_9", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_EE2A0_12", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A0_9", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_10", - "CMT_TOP_EE2A1_11", - "CMT_TOP_EE2A1_12", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A1_9", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_10", - "CMT_TOP_EE2A2_11", - "CMT_TOP_EE2A2_12", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A2_9", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_10", - "CMT_TOP_EE2A3_11", - "CMT_TOP_EE2A3_12", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_10", - "CMT_TOP_EE4A0_11", - "CMT_TOP_EE4A0_12", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A0_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_EE4A1_11", - "CMT_TOP_EE4A1_12", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A1_9", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_10", - "CMT_TOP_EE4A2_11", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A2_9", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_EE4A3_11", - "CMT_TOP_EE4A3_12", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_10", - "CMT_TOP_EE4B0_11", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B0_9", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_10", - "CMT_TOP_EE4B1_11", - "CMT_TOP_EE4B1_12", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B1_9", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_10", - "CMT_TOP_EE4B2_11", - "CMT_TOP_EE4B2_12", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B2_9", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_10", - "CMT_TOP_EE4B3_11", - "CMT_TOP_EE4B3_12", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4B3_9", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_EE4BEG2_12", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_10", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EE4C0_12", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C0_9", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_10", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EE4C1_12", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_EE4C2_12", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C2_9", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_EE4C3_11", - "CMT_TOP_EE4C3_12", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EE4C3_9", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_EL1BEG1_12", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_10", - "CMT_TOP_FAN0_11", - "CMT_TOP_FAN0_12", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN0_9", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_10", - "CMT_TOP_FAN1_11", - "CMT_TOP_FAN1_12", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN1_9", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_10", - "CMT_TOP_FAN2_11", - "CMT_TOP_FAN2_12", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN2_9", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_FAN3_12", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN3_9", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_10", - "CMT_TOP_FAN4_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN4_9", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_10", - "CMT_TOP_FAN5_11", - "CMT_TOP_FAN5_12", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN5_9", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_10", - "CMT_TOP_FAN6_11", - "CMT_TOP_FAN6_12", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN6_9", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_FAN7_11", - "CMT_TOP_FAN7_12", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_FAN7_9", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_ICLK_11", - "CMT_TOP_ICLK_12", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_10", - "CMT_TOP_IMUX0_11", - "CMT_TOP_IMUX0_12", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_10", - "CMT_TOP_IMUX10_11", - "CMT_TOP_IMUX10_12", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX10_4", - "CMT_TOP_IMUX10_5", - "CMT_TOP_IMUX10_6", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_IMUX10_9", - "CMT_TOP_IMUX11_0", - "CMT_TOP_IMUX11_1", - "CMT_TOP_IMUX11_10", - "CMT_TOP_IMUX11_11", - "CMT_TOP_IMUX11_12", - "CMT_TOP_IMUX11_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX11_4", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_IMUX11_9", - "CMT_TOP_IMUX12_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX12_10", - "CMT_TOP_IMUX12_11", - "CMT_TOP_IMUX12_12", - "CMT_TOP_IMUX12_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX12_6", - "CMT_TOP_IMUX12_7", - "CMT_TOP_IMUX12_8", - "CMT_TOP_IMUX12_9", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX13_10", - "CMT_TOP_IMUX13_11", - "CMT_TOP_IMUX13_12", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX13_3", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX13_8", - "CMT_TOP_IMUX13_9", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX14_10", - "CMT_TOP_IMUX14_11", - "CMT_TOP_IMUX14_12", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX14_3", - "CMT_TOP_IMUX14_4", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX15_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_IMUX15_10", - "CMT_TOP_IMUX15_11", - "CMT_TOP_IMUX15_12", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX15_4", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_IMUX15_9", - "CMT_TOP_IMUX16_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX16_10", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX16_12", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX16_5", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX16_7", - "CMT_TOP_IMUX16_8", - "CMT_TOP_IMUX16_9", - "CMT_TOP_IMUX17_0", - "CMT_TOP_IMUX17_1", - "CMT_TOP_IMUX17_10", - "CMT_TOP_IMUX17_11", - "CMT_TOP_IMUX17_12", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX17_3", - "CMT_TOP_IMUX17_4", - "CMT_TOP_IMUX17_5", - "CMT_TOP_IMUX17_6", - "CMT_TOP_IMUX17_7", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX17_9", - "CMT_TOP_IMUX18_0", - "CMT_TOP_IMUX18_1", - "CMT_TOP_IMUX18_10", - "CMT_TOP_IMUX18_11", - "CMT_TOP_IMUX18_12", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX18_3", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX18_5", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX18_7", - "CMT_TOP_IMUX18_8", - "CMT_TOP_IMUX18_9", - "CMT_TOP_IMUX19_0", - "CMT_TOP_IMUX19_1", - "CMT_TOP_IMUX19_10", - "CMT_TOP_IMUX19_11", - "CMT_TOP_IMUX19_12", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX19_3", - "CMT_TOP_IMUX19_4", - "CMT_TOP_IMUX19_5", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX19_7", - "CMT_TOP_IMUX19_8", - "CMT_TOP_IMUX19_9", - "CMT_TOP_IMUX1_0", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX1_10", - "CMT_TOP_IMUX1_11", - "CMT_TOP_IMUX1_12", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX1_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_IMUX1_8", - "CMT_TOP_IMUX1_9", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX20_11", - "CMT_TOP_IMUX20_12", - "CMT_TOP_IMUX20_2", - "CMT_TOP_IMUX20_3", - "CMT_TOP_IMUX20_4", - "CMT_TOP_IMUX20_5", - "CMT_TOP_IMUX20_6", - "CMT_TOP_IMUX20_7", - "CMT_TOP_IMUX20_8", - "CMT_TOP_IMUX20_9", - "CMT_TOP_IMUX21_0", - "CMT_TOP_IMUX21_1", - "CMT_TOP_IMUX21_10", - "CMT_TOP_IMUX21_11", - "CMT_TOP_IMUX21_12", - "CMT_TOP_IMUX21_2", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_IMUX21_7", - "CMT_TOP_IMUX21_8", - "CMT_TOP_IMUX21_9", - "CMT_TOP_IMUX22_0", - "CMT_TOP_IMUX22_1", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX22_11", - "CMT_TOP_IMUX22_12", - "CMT_TOP_IMUX22_2", - "CMT_TOP_IMUX22_3", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX22_7", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX22_9", - "CMT_TOP_IMUX23_0", - "CMT_TOP_IMUX23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_IMUX23_11", - "CMT_TOP_IMUX23_12", - "CMT_TOP_IMUX23_2", - "CMT_TOP_IMUX23_3", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX23_7", - "CMT_TOP_IMUX23_8", - "CMT_TOP_IMUX23_9", - "CMT_TOP_IMUX24_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_IMUX24_10", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX24_12", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_IMUX24_4", - "CMT_TOP_IMUX24_5", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX24_8", - "CMT_TOP_IMUX24_9", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX25_1", - "CMT_TOP_IMUX25_10", - "CMT_TOP_IMUX25_11", - "CMT_TOP_IMUX25_12", - "CMT_TOP_IMUX25_2", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX25_6", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX25_8", - "CMT_TOP_IMUX25_9", - "CMT_TOP_IMUX26_0", - "CMT_TOP_IMUX26_1", - "CMT_TOP_IMUX26_10", - "CMT_TOP_IMUX26_11", - "CMT_TOP_IMUX26_12", - "CMT_TOP_IMUX26_2", - "CMT_TOP_IMUX26_3", - "CMT_TOP_IMUX26_4", - "CMT_TOP_IMUX26_5", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX26_7", - "CMT_TOP_IMUX26_8", - "CMT_TOP_IMUX26_9", - "CMT_TOP_IMUX27_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX27_11", - "CMT_TOP_IMUX27_12", - "CMT_TOP_IMUX27_2", - "CMT_TOP_IMUX27_3", - "CMT_TOP_IMUX27_4", - "CMT_TOP_IMUX27_5", - "CMT_TOP_IMUX27_6", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX27_8", - "CMT_TOP_IMUX27_9", - "CMT_TOP_IMUX28_0", - "CMT_TOP_IMUX28_1", - "CMT_TOP_IMUX28_10", - "CMT_TOP_IMUX28_11", - "CMT_TOP_IMUX28_12", - "CMT_TOP_IMUX28_2", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX28_5", - "CMT_TOP_IMUX28_6", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX28_8", - "CMT_TOP_IMUX28_9", - "CMT_TOP_IMUX29_0", - "CMT_TOP_IMUX29_1", - "CMT_TOP_IMUX29_10", - "CMT_TOP_IMUX29_11", - "CMT_TOP_IMUX29_12", - "CMT_TOP_IMUX29_2", - "CMT_TOP_IMUX29_3", - "CMT_TOP_IMUX29_4", - "CMT_TOP_IMUX29_5", - "CMT_TOP_IMUX29_6", - "CMT_TOP_IMUX29_7", - "CMT_TOP_IMUX29_8", - "CMT_TOP_IMUX29_9", - "CMT_TOP_IMUX2_0", - "CMT_TOP_IMUX2_1", - "CMT_TOP_IMUX2_10", - "CMT_TOP_IMUX2_11", - "CMT_TOP_IMUX2_12", - "CMT_TOP_IMUX2_2", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX2_4", - "CMT_TOP_IMUX2_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_IMUX2_7", - "CMT_TOP_IMUX2_8", - "CMT_TOP_IMUX2_9", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX30_1", - "CMT_TOP_IMUX30_10", - "CMT_TOP_IMUX30_11", - "CMT_TOP_IMUX30_12", - "CMT_TOP_IMUX30_2", - "CMT_TOP_IMUX30_3", - "CMT_TOP_IMUX30_4", - "CMT_TOP_IMUX30_5", - "CMT_TOP_IMUX30_6", - "CMT_TOP_IMUX30_7", - "CMT_TOP_IMUX30_8", - "CMT_TOP_IMUX30_9", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX31_10", - "CMT_TOP_IMUX31_11", - "CMT_TOP_IMUX31_12", - "CMT_TOP_IMUX31_2", - "CMT_TOP_IMUX31_3", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX31_5", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX31_8", - "CMT_TOP_IMUX31_9", - "CMT_TOP_IMUX32_0", - "CMT_TOP_IMUX32_1", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX32_11", - "CMT_TOP_IMUX32_12", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX32_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_IMUX32_5", - "CMT_TOP_IMUX32_6", - "CMT_TOP_IMUX32_7", - "CMT_TOP_IMUX32_8", - "CMT_TOP_IMUX32_9", - "CMT_TOP_IMUX33_0", - "CMT_TOP_IMUX33_1", - "CMT_TOP_IMUX33_10", - "CMT_TOP_IMUX33_11", - "CMT_TOP_IMUX33_12", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX33_4", - "CMT_TOP_IMUX33_5", - "CMT_TOP_IMUX33_6", - "CMT_TOP_IMUX33_7", - "CMT_TOP_IMUX33_8", - "CMT_TOP_IMUX33_9", - "CMT_TOP_IMUX34_0", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX34_10", - "CMT_TOP_IMUX34_11", - "CMT_TOP_IMUX34_12", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX34_4", - "CMT_TOP_IMUX34_5", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX34_7", - "CMT_TOP_IMUX34_8", - "CMT_TOP_IMUX34_9", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX35_1", - "CMT_TOP_IMUX35_10", - "CMT_TOP_IMUX35_11", - "CMT_TOP_IMUX35_12", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX35_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_IMUX35_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_IMUX35_7", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX35_9", - "CMT_TOP_IMUX36_0", - "CMT_TOP_IMUX36_1", - "CMT_TOP_IMUX36_10", - "CMT_TOP_IMUX36_11", - "CMT_TOP_IMUX36_12", - "CMT_TOP_IMUX36_2", - "CMT_TOP_IMUX36_3", - "CMT_TOP_IMUX36_4", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX36_6", - "CMT_TOP_IMUX36_7", - "CMT_TOP_IMUX36_8", - "CMT_TOP_IMUX36_9", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX37_10", - "CMT_TOP_IMUX37_11", - "CMT_TOP_IMUX37_12", - "CMT_TOP_IMUX37_2", - "CMT_TOP_IMUX37_3", - "CMT_TOP_IMUX37_4", - "CMT_TOP_IMUX37_5", - "CMT_TOP_IMUX37_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_IMUX37_9", - "CMT_TOP_IMUX38_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_IMUX38_10", - "CMT_TOP_IMUX38_11", - "CMT_TOP_IMUX38_12", - "CMT_TOP_IMUX38_2", - "CMT_TOP_IMUX38_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX38_6", - "CMT_TOP_IMUX38_7", - "CMT_TOP_IMUX38_8", - "CMT_TOP_IMUX38_9", - "CMT_TOP_IMUX39_0", - "CMT_TOP_IMUX39_1", - "CMT_TOP_IMUX39_10", - "CMT_TOP_IMUX39_11", - "CMT_TOP_IMUX39_12", - "CMT_TOP_IMUX39_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_IMUX39_5", - "CMT_TOP_IMUX39_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX39_8", - "CMT_TOP_IMUX39_9", - "CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_10", - "CMT_TOP_IMUX3_11", - "CMT_TOP_IMUX3_12", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX3_9", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_IMUX40_12", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX40_9", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_10", - "CMT_TOP_IMUX41_11", - "CMT_TOP_IMUX41_12", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX41_9", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX42_11", - "CMT_TOP_IMUX42_12", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX42_9", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_IMUX43_12", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX43_9", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_10", - "CMT_TOP_IMUX44_11", - "CMT_TOP_IMUX44_12", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX45_11", - "CMT_TOP_IMUX45_12", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX45_9", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_10", - "CMT_TOP_IMUX46_11", - "CMT_TOP_IMUX46_12", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX46_9", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX47_11", - "CMT_TOP_IMUX47_12", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX47_9", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_10", - "CMT_TOP_IMUX4_11", - "CMT_TOP_IMUX4_12", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX4_9", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX5_11", - "CMT_TOP_IMUX5_12", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_10", - "CMT_TOP_IMUX6_11", - "CMT_TOP_IMUX6_12", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX6_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_10", - "CMT_TOP_IMUX7_11", - "CMT_TOP_IMUX7_12", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX7_9", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_IMUX8_12", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_10", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX9_9", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_10", - "CMT_TOP_LH10_11", - "CMT_TOP_LH10_12", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH10_9", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_10", - "CMT_TOP_LH11_11", - "CMT_TOP_LH11_12", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH11_9", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_10", - "CMT_TOP_LH12_11", - "CMT_TOP_LH12_12", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH12_9", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_10", - "CMT_TOP_LH1_11", - "CMT_TOP_LH1_12", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH1_9", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_10", - "CMT_TOP_LH2_11", - "CMT_TOP_LH2_12", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH2_9", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_10", - "CMT_TOP_LH3_11", - "CMT_TOP_LH3_12", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH3_9", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_10", - "CMT_TOP_LH4_11", - "CMT_TOP_LH4_12", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH4_9", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_10", - "CMT_TOP_LH5_11", - "CMT_TOP_LH5_12", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH5_9", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_10", - "CMT_TOP_LH6_11", - "CMT_TOP_LH6_12", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH6_9", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_10", - "CMT_TOP_LH7_11", - "CMT_TOP_LH7_12", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH7_9", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_10", - "CMT_TOP_LH8_11", - "CMT_TOP_LH8_12", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH8_9", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_10", - "CMT_TOP_LH9_11", - "CMT_TOP_LH9_12", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LH9_9", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_10", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_L_CLKFBOUT2IN", - "CMT_TOP_L_UPPER_T_CLKFBIN", - "CMT_TOP_L_UPPER_T_CLKIN1", - "CMT_TOP_L_UPPER_T_CLKIN2", - "CMT_TOP_L_UPPER_T_CLKPLL0", - "CMT_TOP_L_UPPER_T_CLKPLL1", - "CMT_TOP_L_UPPER_T_CLKPLL2", - "CMT_TOP_L_UPPER_T_CLKPLL3", - "CMT_TOP_L_UPPER_T_CLKPLL4", - "CMT_TOP_L_UPPER_T_CLKPLL5", - "CMT_TOP_L_UPPER_T_CLKPLL6", - "CMT_TOP_L_UPPER_T_CLKPLL7", - "CMT_TOP_L_UPPER_T_FREQ_BB0", - "CMT_TOP_L_UPPER_T_FREQ_BB1", - "CMT_TOP_L_UPPER_T_FREQ_BB2", - "CMT_TOP_L_UPPER_T_FREQ_BB3", - "CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT", - "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT", - "CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_MONITOR_N_12", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_10", - "CMT_TOP_NE2A0_11", - "CMT_TOP_NE2A0_12", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A0_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_10", - "CMT_TOP_NE2A1_11", - "CMT_TOP_NE2A1_12", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_10", - "CMT_TOP_NE2A2_11", - "CMT_TOP_NE2A2_12", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A2_9", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_10", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NE2A3_12", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_10", - "CMT_TOP_NE4C0_11", - "CMT_TOP_NE4C0_12", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_9", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_NE4C1_11", - "CMT_TOP_NE4C1_12", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C1_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_10", - "CMT_TOP_NE4C2_11", - "CMT_TOP_NE4C2_12", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C2_9", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_10", - "CMT_TOP_NE4C3_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NE4C3_9", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_10", - "CMT_TOP_NW2A0_11", - "CMT_TOP_NW2A0_12", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A0_9", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_10", - "CMT_TOP_NW2A1_11", - "CMT_TOP_NW2A1_12", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_10", - "CMT_TOP_NW2A2_11", - "CMT_TOP_NW2A2_12", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A2_9", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW2A3_11", - "CMT_TOP_NW2A3_12", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW2A3_9", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_10", - "CMT_TOP_NW4A0_11", - "CMT_TOP_NW4A0_12", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_10", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A1_12", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A1_9", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW4A2_11", - "CMT_TOP_NW4A2_12", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A2_9", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_10", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4A3_12", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_10", - "CMT_TOP_NW4END0_11", - "CMT_TOP_NW4END0_12", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END0_9", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_10", - "CMT_TOP_NW4END1_11", - "CMT_TOP_NW4END1_12", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END1_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_10", - "CMT_TOP_NW4END2_11", - "CMT_TOP_NW4END2_12", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END2_9", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4END3_11", - "CMT_TOP_NW4END3_12", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_NW4END3_9", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_10", - "CMT_TOP_OCLK_11", - "CMT_TOP_OCLK_12", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_OCLK_9", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "CMT_TOP_R_UPPER_T_PLLE2_RST", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", - "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_10", - "CMT_TOP_SE2A0_11", - "CMT_TOP_SE2A0_12", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A0_9", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_10", - "CMT_TOP_SE2A1_11", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A1_9", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_10", - "CMT_TOP_SE2A2_11", - "CMT_TOP_SE2A2_12", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_10", - "CMT_TOP_SE2A3_11", - "CMT_TOP_SE2A3_12", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE2A3_9", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_SE4BEG0_12", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SE4BEG2_12", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG3_12", - "CMT_TOP_SE4BEG3_2", - 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"CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_10", - "CMT_TOP_SE4C3_11", - "CMT_TOP_SE4C3_12", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SE4C3_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SW2A0_11", - "CMT_TOP_SW2A0_12", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A0_9", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_10", - "CMT_TOP_SW2A1_11", - "CMT_TOP_SW2A1_12", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A1_9", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_10", - "CMT_TOP_SW2A2_11", - "CMT_TOP_SW2A2_12", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A2_9", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_10", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SW2A3_12", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW2A3_9", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_SW4A0_11", - "CMT_TOP_SW4A0_12", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_10", - "CMT_TOP_SW4A1_11", - "CMT_TOP_SW4A1_12", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_10", - 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"CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END1_9", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_SW4END2_11", - "CMT_TOP_SW4END2_12", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END2_9", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_10", - "CMT_TOP_SW4END3_11", - "CMT_TOP_SW4END3_12", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_SW4END3_9", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_10", - "CMT_TOP_WL1END0_11", - "CMT_TOP_WL1END0_12", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END0_9", - 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"CMT_TOP_WW2A3_10", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WW2A3_12", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2A3_9", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_10", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW2END0_12", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_10", - "CMT_TOP_WW2END1_11", - "CMT_TOP_WW2END1_12", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END1_9", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_10", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WW2END2_12", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_10", - "CMT_TOP_WW2END3_11", - "CMT_TOP_WW2END3_12", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW2END3_9", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_10", - "CMT_TOP_WW4A0_11", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_10", - "CMT_TOP_WW4A1_11", - "CMT_TOP_WW4A1_12", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_10", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WW4A2_12", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A2_9", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_10", - "CMT_TOP_WW4A3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4A3_9", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_10", - "CMT_TOP_WW4B0_11", - "CMT_TOP_WW4B0_12", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_9", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_10", - "CMT_TOP_WW4B1_11", - "CMT_TOP_WW4B1_12", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_10", - "CMT_TOP_WW4B2_11", - "CMT_TOP_WW4B2_12", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_10", - "CMT_TOP_WW4B3_11", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4B3_9", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_10", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4C0_12", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C0_9", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_WW4C1_12", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C1_9", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_10", - "CMT_TOP_WW4C2_11", - "CMT_TOP_WW4C2_12", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C2_9", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_WW4C3_12", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4C3_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_WW4END0_12", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END0_9", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_10", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WW4END1_12", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END1_9", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_WW4END2_12", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END2_9", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_10", - "CMT_TOP_WW4END3_11", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4END3_9", - "PLLOUT_CLK_FREQ_BB_0", - "PLLOUT_CLK_FREQ_BB_1", - "PLLOUT_CLK_FREQ_BB_2", - "PLLOUT_CLK_FREQ_BB_3", - "PLL_CLK_FREQ_BB0_NS", - "PLL_CLK_FREQ_BB1_NS", - "PLL_CLK_FREQ_BB2_NS", - "PLL_CLK_FREQ_BB3_NS", - "PLL_CLK_FREQ_BB_BUFOUT_NS0", - "PLL_CLK_FREQ_BB_BUFOUT_NS1", - "PLL_CLK_FREQ_BB_BUFOUT_NS2", - "PLL_CLK_FREQ_BB_BUFOUT_NS3" - ] + "wires": { + "CMT_PHASER_D_ICLKDIV_TOIOI": null, + "CMT_PHASER_D_ICLK_TOIOI": null, + "CMT_PHASER_D_OCLK90_TOIOI": null, + "CMT_PHASER_D_OCLKDIV_TOIOI": null, + "CMT_PHASER_D_OCLK_TOIOI": null, + "CMT_PLL_DQS_TO_PHASER_D": null, + "CMT_PLL_PHASERD_CTSBUS0": null, + "CMT_PLL_PHASERD_CTSBUS1": null, + "CMT_PLL_PHASERD_DQSBUS0": null, + "CMT_PLL_PHASERD_DQSBUS1": null, + "CMT_PLL_PHASERD_DTSBUS0": null, + "CMT_PLL_PHASERD_DTSBUS1": null, + "CMT_PLL_PHASERREF0": null, + "CMT_PLL_PHASERREF1": null, + "CMT_PLL_PHASERREF_ABOVE0": null, + "CMT_PLL_PHASERREF_ABOVE1": null, + "CMT_PLL_PHASERREF_BELOW0": null, + "CMT_PLL_PHASERREF_BELOW1": null, + "CMT_PLL_PHASER_IN_D_ICLK": null, + "CMT_PLL_PHASER_IN_D_ICLKDIV": null, + "CMT_PLL_PHASER_OUT_D_OCLK": null, + "CMT_PLL_PHASER_OUT_D_OCLK1X_90": null, + "CMT_PLL_PHASER_OUT_D_OCLKDIV": null, + "CMT_PLL_PHASER_RDCLK_TOFIFO": null, + "CMT_PLL_PHASER_RDENABLE_TOFIFO": null, + "CMT_PLL_PHASER_WRCLK_TOFIFO": null, + "CMT_PLL_PHASER_WRENABLE_TOFIFO": null, + "CMT_PLL_PHYCTRL_SYNC_BB_DN": null, + "CMT_PLL_PHYCTRL_SYNC_BB_UP": null, + "CMT_TOP_BLOCK_OUTS_L_B0_0": null, + "CMT_TOP_BLOCK_OUTS_L_B0_1": null, + "CMT_TOP_BLOCK_OUTS_L_B0_10": null, + "CMT_TOP_BLOCK_OUTS_L_B0_11": null, + "CMT_TOP_BLOCK_OUTS_L_B0_12": null, + "CMT_TOP_BLOCK_OUTS_L_B0_2": null, + "CMT_TOP_BLOCK_OUTS_L_B0_3": null, + "CMT_TOP_BLOCK_OUTS_L_B0_4": null, + "CMT_TOP_BLOCK_OUTS_L_B0_5": null, + "CMT_TOP_BLOCK_OUTS_L_B0_6": null, + "CMT_TOP_BLOCK_OUTS_L_B0_7": null, + "CMT_TOP_BLOCK_OUTS_L_B0_8": null, + "CMT_TOP_BLOCK_OUTS_L_B0_9": null, + "CMT_TOP_BLOCK_OUTS_L_B1_0": null, + "CMT_TOP_BLOCK_OUTS_L_B1_1": null, + "CMT_TOP_BLOCK_OUTS_L_B1_10": null, + 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null, + "PLLOUT_CLK_FREQ_BB_3": null, + "PLL_CLK_FREQ_BB0_NS": null, + "PLL_CLK_FREQ_BB1_NS": null, + "PLL_CLK_FREQ_BB2_NS": null, + "PLL_CLK_FREQ_BB3_NS": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS0": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS1": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS2": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS3": null + } } diff --git a/kintex7/tile_type_CMT_TOP_R_LOWER_B.json b/kintex7/tile_type_CMT_TOP_R_LOWER_B.json index 57d2328..248bd46 100644 --- a/kintex7/tile_type_CMT_TOP_R_LOWER_B.json +++ b/kintex7/tile_type_CMT_TOP_R_LOWER_B.json @@ -2,1395 +2,5514 @@ "pips": { "CMT_TOP_R_LOWER_B.CMT_LR_LOWER_B_CLKFBOUT2IN->>CMT_LR_LOWER_B_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": 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"0.0" + }, "src_wire": "CMT_TOP_IMUX7_0" }, "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS0->>CMT_R_LOWER_B_CLK_FREQ_BB3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS0" }, "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS1->>CMT_R_LOWER_B_CLK_FREQ_BB2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS1" }, "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS2->>CMT_R_LOWER_B_CLK_FREQ_BB1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS2" }, "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_NS3->>CMT_R_LOWER_B_CLK_FREQ_BB0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_R_LOWER_B_CLK_FREQ_BB0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCM_CLK_FREQ_BB_NS3" }, "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF0_NS<<->>MMCM_CLK_FREQ_BB_NS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS0", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF0_NS" }, "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF1_NS<<->>MMCM_CLK_FREQ_BB_NS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS1", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF1_NS" }, "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF2_NS<<->>MMCM_CLK_FREQ_BB_NS2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS2", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF2_NS" }, "CMT_TOP_R_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS<<->>MMCM_CLK_FREQ_BB_NS3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQ_BB_NS3", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCM_CLK_FREQ_BB_REBUF3_NS" } }, @@ -1399,172 +5518,1666 @@ "name": "X0Y0", "prefix": "MMCME2_ADV", "site_pins": { - "CLKFBIN": "CMT_LR_LOWER_B_MMCM_CLKFBIN", - "CLKFBOUT": "CMT_LR_LOWER_B_MMCM_CLKFBOUT", - "CLKFBOUTB": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB", - "CLKFBSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED", - "CLKIN1": "CMT_LR_LOWER_B_MMCM_CLKIN1", - "CLKIN2": "CMT_LR_LOWER_B_MMCM_CLKIN2", - "CLKINSEL": "CMT_LR_LOWER_B_MMCM_CLKINSEL", - "CLKINSTOPPED": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED", - "CLKOUT0": "CMT_LR_LOWER_B_MMCM_CLKOUT0", - "CLKOUT0B": "CMT_LR_LOWER_B_MMCM_CLKOUT0B", - "CLKOUT1": "CMT_LR_LOWER_B_MMCM_CLKOUT1", - "CLKOUT1B": "CMT_LR_LOWER_B_MMCM_CLKOUT1B", - "CLKOUT2": "CMT_LR_LOWER_B_MMCM_CLKOUT2", - "CLKOUT2B": "CMT_LR_LOWER_B_MMCM_CLKOUT2B", - "CLKOUT3": "CMT_LR_LOWER_B_MMCM_CLKOUT3", - "CLKOUT3B": "CMT_LR_LOWER_B_MMCM_CLKOUT3B", - "CLKOUT4": "CMT_LR_LOWER_B_MMCM_CLKOUT4", - "CLKOUT5": "CMT_LR_LOWER_B_MMCM_CLKOUT5", - "CLKOUT6": "CMT_LR_LOWER_B_MMCM_CLKOUT6", - "DADDR0": "CMT_LR_LOWER_B_MMCM_DADDR0", - "DADDR1": "CMT_LR_LOWER_B_MMCM_DADDR1", - "DADDR2": "CMT_LR_LOWER_B_MMCM_DADDR2", - "DADDR3": "CMT_LR_LOWER_B_MMCM_DADDR3", - "DADDR4": "CMT_LR_LOWER_B_MMCM_DADDR4", - "DADDR5": "CMT_LR_LOWER_B_MMCM_DADDR5", - "DADDR6": "CMT_LR_LOWER_B_MMCM_DADDR6", - "DCLK": "CMT_LR_LOWER_B_MMCM_DCLK", - "DEN": "CMT_LR_LOWER_B_MMCM_DEN", - "DI0": "CMT_LR_LOWER_B_MMCM_DI0", - "DI1": "CMT_LR_LOWER_B_MMCM_DI1", - "DI10": "CMT_LR_LOWER_B_MMCM_DI10", - "DI11": "CMT_LR_LOWER_B_MMCM_DI11", - "DI12": "CMT_LR_LOWER_B_MMCM_DI12", - "DI13": "CMT_LR_LOWER_B_MMCM_DI13", - "DI14": "CMT_LR_LOWER_B_MMCM_DI14", - "DI15": "CMT_LR_LOWER_B_MMCM_DI15", - "DI2": "CMT_LR_LOWER_B_MMCM_DI2", - "DI3": "CMT_LR_LOWER_B_MMCM_DI3", - "DI4": "CMT_LR_LOWER_B_MMCM_DI4", - "DI5": "CMT_LR_LOWER_B_MMCM_DI5", - "DI6": "CMT_LR_LOWER_B_MMCM_DI6", - "DI7": "CMT_LR_LOWER_B_MMCM_DI7", - "DI8": "CMT_LR_LOWER_B_MMCM_DI8", - "DI9": "CMT_LR_LOWER_B_MMCM_DI9", - "DO0": "CMT_LR_LOWER_B_MMCM_DO0", - "DO1": "CMT_LR_LOWER_B_MMCM_DO1", - "DO10": "CMT_LR_LOWER_B_MMCM_DO10", - "DO11": "CMT_LR_LOWER_B_MMCM_DO11", - "DO12": "CMT_LR_LOWER_B_MMCM_DO12", - "DO13": "CMT_LR_LOWER_B_MMCM_DO13", - "DO14": "CMT_LR_LOWER_B_MMCM_DO14", - "DO15": "CMT_LR_LOWER_B_MMCM_DO15", - "DO2": "CMT_LR_LOWER_B_MMCM_DO2", - "DO3": "CMT_LR_LOWER_B_MMCM_DO3", - "DO4": "CMT_LR_LOWER_B_MMCM_DO4", - "DO5": "CMT_LR_LOWER_B_MMCM_DO5", - "DO6": "CMT_LR_LOWER_B_MMCM_DO6", - "DO7": "CMT_LR_LOWER_B_MMCM_DO7", - "DO8": "CMT_LR_LOWER_B_MMCM_DO8", - "DO9": "CMT_LR_LOWER_B_MMCM_DO9", - "DRDY": "CMT_LR_LOWER_B_MMCM_DRDY", - "DWE": "CMT_LR_LOWER_B_MMCM_DWE", - "LOCKED": "CMT_LR_LOWER_B_MMCM_LOCKED", - "PSCLK": "CMT_LR_LOWER_B_MMCM_PSCLK", - "PSDONE": "CMT_LR_LOWER_B_MMCM_PSDONE", - "PSEN": "CMT_LR_LOWER_B_MMCM_PSEN", - "PSINCDEC": "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "PWRDWN": "CMT_LR_LOWER_B_MMCM_PWRDWN", - "RST": "CMT_LR_LOWER_B_MMCM_RST", - "TESTIN0": "CMT_LR_LOWER_B_MMCM_TESTIN0", - "TESTIN1": "CMT_LR_LOWER_B_MMCM_TESTIN1", - "TESTIN10": "CMT_LR_LOWER_B_MMCM_TESTIN10", - "TESTIN11": "CMT_LR_LOWER_B_MMCM_TESTIN11", - "TESTIN12": "CMT_LR_LOWER_B_MMCM_TESTIN12", - "TESTIN13": "CMT_LR_LOWER_B_MMCM_TESTIN13", - "TESTIN14": "CMT_LR_LOWER_B_MMCM_TESTIN14", - "TESTIN15": "CMT_LR_LOWER_B_MMCM_TESTIN15", - "TESTIN16": "CMT_LR_LOWER_B_MMCM_TESTIN16", - "TESTIN17": "CMT_LR_LOWER_B_MMCM_TESTIN17", - "TESTIN18": "CMT_LR_LOWER_B_MMCM_TESTIN18", - "TESTIN19": "CMT_LR_LOWER_B_MMCM_TESTIN19", - "TESTIN2": "CMT_LR_LOWER_B_MMCM_TESTIN2", - "TESTIN20": "CMT_LR_LOWER_B_MMCM_TESTIN20", - "TESTIN21": "CMT_LR_LOWER_B_MMCM_TESTIN21", - "TESTIN22": "CMT_LR_LOWER_B_MMCM_TESTIN22", - "TESTIN23": "CMT_LR_LOWER_B_MMCM_TESTIN23", - "TESTIN24": "CMT_LR_LOWER_B_MMCM_TESTIN24", - "TESTIN25": "CMT_LR_LOWER_B_MMCM_TESTIN25", - "TESTIN26": "CMT_LR_LOWER_B_MMCM_TESTIN26", - "TESTIN27": "CMT_LR_LOWER_B_MMCM_TESTIN27", - "TESTIN28": "CMT_LR_LOWER_B_MMCM_TESTIN28", - "TESTIN29": "CMT_LR_LOWER_B_MMCM_TESTIN29", - "TESTIN3": "CMT_LR_LOWER_B_MMCM_TESTIN3", - "TESTIN30": "CMT_LR_LOWER_B_MMCM_TESTIN30", - "TESTIN31": "CMT_LR_LOWER_B_MMCM_TESTIN31", - "TESTIN4": "CMT_LR_LOWER_B_MMCM_TESTIN4", - "TESTIN5": "CMT_LR_LOWER_B_MMCM_TESTIN5", - "TESTIN6": "CMT_LR_LOWER_B_MMCM_TESTIN6", - "TESTIN7": "CMT_LR_LOWER_B_MMCM_TESTIN7", - "TESTIN8": "CMT_LR_LOWER_B_MMCM_TESTIN8", - "TESTIN9": "CMT_LR_LOWER_B_MMCM_TESTIN9", - "TESTOUT0": "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "TESTOUT1": "CMT_LR_LOWER_B_MMCM_TESTOUT1", - "TESTOUT10": "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "TESTOUT11": "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "TESTOUT12": "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "TESTOUT13": "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "TESTOUT14": "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "TESTOUT15": "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "TESTOUT16": "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "TESTOUT17": "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "TESTOUT18": "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "TESTOUT19": "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "TESTOUT2": "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "TESTOUT20": "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "TESTOUT21": "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "TESTOUT22": "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "TESTOUT23": "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "TESTOUT24": "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "TESTOUT25": "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "TESTOUT26": "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "TESTOUT27": "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "TESTOUT28": "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "TESTOUT29": "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "TESTOUT3": "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "TESTOUT30": "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "TESTOUT31": "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "TESTOUT32": "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "TESTOUT33": "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "TESTOUT34": "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "TESTOUT35": "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "TESTOUT36": "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "TESTOUT37": "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "TESTOUT38": "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "TESTOUT39": "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "TESTOUT4": "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "TESTOUT40": "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "TESTOUT41": "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "TESTOUT42": "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "TESTOUT43": "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "TESTOUT44": "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "TESTOUT45": "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "TESTOUT46": "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "TESTOUT47": "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "TESTOUT48": "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "TESTOUT49": "CMT_LR_LOWER_B_MMCM_TESTOUT49", - "TESTOUT5": "CMT_LR_LOWER_B_MMCM_TESTOUT5", - "TESTOUT50": "CMT_LR_LOWER_B_MMCM_TESTOUT50", - "TESTOUT51": "CMT_LR_LOWER_B_MMCM_TESTOUT51", - "TESTOUT52": "CMT_LR_LOWER_B_MMCM_TESTOUT52", - "TESTOUT53": "CMT_LR_LOWER_B_MMCM_TESTOUT53", - "TESTOUT54": "CMT_LR_LOWER_B_MMCM_TESTOUT54", - "TESTOUT55": "CMT_LR_LOWER_B_MMCM_TESTOUT55", - "TESTOUT56": "CMT_LR_LOWER_B_MMCM_TESTOUT56", - "TESTOUT57": "CMT_LR_LOWER_B_MMCM_TESTOUT57", - "TESTOUT58": "CMT_LR_LOWER_B_MMCM_TESTOUT58", - "TESTOUT59": "CMT_LR_LOWER_B_MMCM_TESTOUT59", - "TESTOUT6": "CMT_LR_LOWER_B_MMCM_TESTOUT6", - "TESTOUT60": "CMT_LR_LOWER_B_MMCM_TESTOUT60", - "TESTOUT61": "CMT_LR_LOWER_B_MMCM_TESTOUT61", - "TESTOUT62": "CMT_LR_LOWER_B_MMCM_TESTOUT62", - "TESTOUT63": "CMT_LR_LOWER_B_MMCM_TESTOUT63", - "TESTOUT7": "CMT_LR_LOWER_B_MMCM_TESTOUT7", - "TESTOUT8": "CMT_LR_LOWER_B_MMCM_TESTOUT8", - "TESTOUT9": "CMT_LR_LOWER_B_MMCM_TESTOUT9", - "TMUXOUT": "CMT_LR_LOWER_B_MMCM_TMUXOUT" + "CLKFBIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_CLKFBIN" + }, + "CLKFBOUT": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUT" + }, + "CLKFBOUTB": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKFBOUTB" + }, + "CLKFBSTOPPED": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKFBSTOPPED" + }, + "CLKIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_CLKIN1" + }, + "CLKIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_CLKIN2" + }, + "CLKINSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_CLKINSEL" + }, + "CLKINSTOPPED": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKINSTOPPED" + }, + "CLKOUT0": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0" + }, + "CLKOUT0B": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT0B" + }, + "CLKOUT1": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1" + }, + "CLKOUT1B": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT1B" + }, + "CLKOUT2": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2" + }, + "CLKOUT2B": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT2B" + }, + "CLKOUT3": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3" + }, + "CLKOUT3B": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT3B" + }, + "CLKOUT4": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT4" + }, + "CLKOUT5": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT5" + }, + "CLKOUT6": { + "delay": [ + "0.005", + "0.005", + "0.011", + "0.012" + ], + "res": "0.85525", + "wire": "CMT_LR_LOWER_B_MMCM_CLKOUT6" + }, + "DADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_DADDR0" + }, + "DADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_DADDR1" + }, + "DADDR2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_DADDR2" + }, + "DADDR3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_DADDR3" + }, + "DADDR4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_DADDR4" + }, + "DADDR5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_LR_LOWER_B_MMCM_DADDR5" + }, + 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"CMT_LR_LOWER_B_MMCM_DI0", - "CMT_LR_LOWER_B_MMCM_DI1", - "CMT_LR_LOWER_B_MMCM_DI10", - "CMT_LR_LOWER_B_MMCM_DI11", - "CMT_LR_LOWER_B_MMCM_DI12", - "CMT_LR_LOWER_B_MMCM_DI13", - "CMT_LR_LOWER_B_MMCM_DI14", - "CMT_LR_LOWER_B_MMCM_DI15", - "CMT_LR_LOWER_B_MMCM_DI2", - "CMT_LR_LOWER_B_MMCM_DI3", - "CMT_LR_LOWER_B_MMCM_DI4", - "CMT_LR_LOWER_B_MMCM_DI5", - "CMT_LR_LOWER_B_MMCM_DI6", - "CMT_LR_LOWER_B_MMCM_DI7", - "CMT_LR_LOWER_B_MMCM_DI8", - "CMT_LR_LOWER_B_MMCM_DI9", - "CMT_LR_LOWER_B_MMCM_DO0", - "CMT_LR_LOWER_B_MMCM_DO1", - "CMT_LR_LOWER_B_MMCM_DO10", - "CMT_LR_LOWER_B_MMCM_DO11", - "CMT_LR_LOWER_B_MMCM_DO12", - "CMT_LR_LOWER_B_MMCM_DO13", - "CMT_LR_LOWER_B_MMCM_DO14", - "CMT_LR_LOWER_B_MMCM_DO15", - "CMT_LR_LOWER_B_MMCM_DO2", - "CMT_LR_LOWER_B_MMCM_DO3", - "CMT_LR_LOWER_B_MMCM_DO4", - "CMT_LR_LOWER_B_MMCM_DO5", - "CMT_LR_LOWER_B_MMCM_DO6", - "CMT_LR_LOWER_B_MMCM_DO7", - "CMT_LR_LOWER_B_MMCM_DO8", - "CMT_LR_LOWER_B_MMCM_DO9", - "CMT_LR_LOWER_B_MMCM_DRDY", - "CMT_LR_LOWER_B_MMCM_DWE", - "CMT_LR_LOWER_B_MMCM_LOCKED", - "CMT_LR_LOWER_B_MMCM_PSCLK", - "CMT_LR_LOWER_B_MMCM_PSDONE", - "CMT_LR_LOWER_B_MMCM_PSEN", - "CMT_LR_LOWER_B_MMCM_PSINCDEC", - "CMT_LR_LOWER_B_MMCM_PWRDWN", - "CMT_LR_LOWER_B_MMCM_RST", - "CMT_LR_LOWER_B_MMCM_TESTIN0", - "CMT_LR_LOWER_B_MMCM_TESTIN1", - "CMT_LR_LOWER_B_MMCM_TESTIN10", - "CMT_LR_LOWER_B_MMCM_TESTIN11", - "CMT_LR_LOWER_B_MMCM_TESTIN12", - "CMT_LR_LOWER_B_MMCM_TESTIN13", - "CMT_LR_LOWER_B_MMCM_TESTIN14", - "CMT_LR_LOWER_B_MMCM_TESTIN15", - "CMT_LR_LOWER_B_MMCM_TESTIN16", - "CMT_LR_LOWER_B_MMCM_TESTIN17", - "CMT_LR_LOWER_B_MMCM_TESTIN18", - "CMT_LR_LOWER_B_MMCM_TESTIN19", - "CMT_LR_LOWER_B_MMCM_TESTIN2", - "CMT_LR_LOWER_B_MMCM_TESTIN20", - "CMT_LR_LOWER_B_MMCM_TESTIN21", - "CMT_LR_LOWER_B_MMCM_TESTIN22", - "CMT_LR_LOWER_B_MMCM_TESTIN23", - "CMT_LR_LOWER_B_MMCM_TESTIN24", - "CMT_LR_LOWER_B_MMCM_TESTIN25", - "CMT_LR_LOWER_B_MMCM_TESTIN26", - "CMT_LR_LOWER_B_MMCM_TESTIN27", - "CMT_LR_LOWER_B_MMCM_TESTIN28", - "CMT_LR_LOWER_B_MMCM_TESTIN29", - "CMT_LR_LOWER_B_MMCM_TESTIN3", - "CMT_LR_LOWER_B_MMCM_TESTIN30", - "CMT_LR_LOWER_B_MMCM_TESTIN31", - "CMT_LR_LOWER_B_MMCM_TESTIN4", - "CMT_LR_LOWER_B_MMCM_TESTIN5", - "CMT_LR_LOWER_B_MMCM_TESTIN6", - "CMT_LR_LOWER_B_MMCM_TESTIN7", - "CMT_LR_LOWER_B_MMCM_TESTIN8", - "CMT_LR_LOWER_B_MMCM_TESTIN9", - "CMT_LR_LOWER_B_MMCM_TESTOUT0", - "CMT_LR_LOWER_B_MMCM_TESTOUT1", - "CMT_LR_LOWER_B_MMCM_TESTOUT10", - "CMT_LR_LOWER_B_MMCM_TESTOUT11", - "CMT_LR_LOWER_B_MMCM_TESTOUT12", - "CMT_LR_LOWER_B_MMCM_TESTOUT13", - "CMT_LR_LOWER_B_MMCM_TESTOUT14", - "CMT_LR_LOWER_B_MMCM_TESTOUT15", - "CMT_LR_LOWER_B_MMCM_TESTOUT16", - "CMT_LR_LOWER_B_MMCM_TESTOUT17", - "CMT_LR_LOWER_B_MMCM_TESTOUT18", - "CMT_LR_LOWER_B_MMCM_TESTOUT19", - "CMT_LR_LOWER_B_MMCM_TESTOUT2", - "CMT_LR_LOWER_B_MMCM_TESTOUT20", - "CMT_LR_LOWER_B_MMCM_TESTOUT21", - "CMT_LR_LOWER_B_MMCM_TESTOUT22", - "CMT_LR_LOWER_B_MMCM_TESTOUT23", - "CMT_LR_LOWER_B_MMCM_TESTOUT24", - "CMT_LR_LOWER_B_MMCM_TESTOUT25", - "CMT_LR_LOWER_B_MMCM_TESTOUT26", - "CMT_LR_LOWER_B_MMCM_TESTOUT27", - "CMT_LR_LOWER_B_MMCM_TESTOUT28", - "CMT_LR_LOWER_B_MMCM_TESTOUT29", - "CMT_LR_LOWER_B_MMCM_TESTOUT3", - "CMT_LR_LOWER_B_MMCM_TESTOUT30", - "CMT_LR_LOWER_B_MMCM_TESTOUT31", - "CMT_LR_LOWER_B_MMCM_TESTOUT32", - "CMT_LR_LOWER_B_MMCM_TESTOUT33", - "CMT_LR_LOWER_B_MMCM_TESTOUT34", - "CMT_LR_LOWER_B_MMCM_TESTOUT35", - "CMT_LR_LOWER_B_MMCM_TESTOUT36", - "CMT_LR_LOWER_B_MMCM_TESTOUT37", - "CMT_LR_LOWER_B_MMCM_TESTOUT38", - "CMT_LR_LOWER_B_MMCM_TESTOUT39", - "CMT_LR_LOWER_B_MMCM_TESTOUT4", - "CMT_LR_LOWER_B_MMCM_TESTOUT40", - "CMT_LR_LOWER_B_MMCM_TESTOUT41", - "CMT_LR_LOWER_B_MMCM_TESTOUT42", - "CMT_LR_LOWER_B_MMCM_TESTOUT43", - "CMT_LR_LOWER_B_MMCM_TESTOUT44", - "CMT_LR_LOWER_B_MMCM_TESTOUT45", - "CMT_LR_LOWER_B_MMCM_TESTOUT46", - "CMT_LR_LOWER_B_MMCM_TESTOUT47", - "CMT_LR_LOWER_B_MMCM_TESTOUT48", - "CMT_LR_LOWER_B_MMCM_TESTOUT49", - "CMT_LR_LOWER_B_MMCM_TESTOUT5", - "CMT_LR_LOWER_B_MMCM_TESTOUT50", - "CMT_LR_LOWER_B_MMCM_TESTOUT51", - "CMT_LR_LOWER_B_MMCM_TESTOUT52", - "CMT_LR_LOWER_B_MMCM_TESTOUT53", - "CMT_LR_LOWER_B_MMCM_TESTOUT54", - "CMT_LR_LOWER_B_MMCM_TESTOUT55", - "CMT_LR_LOWER_B_MMCM_TESTOUT56", - "CMT_LR_LOWER_B_MMCM_TESTOUT57", - "CMT_LR_LOWER_B_MMCM_TESTOUT58", - "CMT_LR_LOWER_B_MMCM_TESTOUT59", - "CMT_LR_LOWER_B_MMCM_TESTOUT6", - "CMT_LR_LOWER_B_MMCM_TESTOUT60", - "CMT_LR_LOWER_B_MMCM_TESTOUT61", - "CMT_LR_LOWER_B_MMCM_TESTOUT62", - "CMT_LR_LOWER_B_MMCM_TESTOUT63", - "CMT_LR_LOWER_B_MMCM_TESTOUT7", - "CMT_LR_LOWER_B_MMCM_TESTOUT8", - "CMT_LR_LOWER_B_MMCM_TESTOUT9", - "CMT_LR_LOWER_B_MMCM_TMUXOUT", - "CMT_MMCM_A_RDCLK_TOFIFO", - "CMT_MMCM_A_RDEN_TOFIFO", - "CMT_MMCM_A_WRCLK_TOFIFO", - "CMT_MMCM_A_WREN_TOFIFO", - "CMT_MMCM_DQS_TO_PHASERA", - "CMT_MMCM_PHASERA_CTSBUS0", - "CMT_MMCM_PHASERA_CTSBUS1", - "CMT_MMCM_PHASERA_DQSBUS0", - "CMT_MMCM_PHASERA_DQSBUS1", - "CMT_MMCM_PHASERA_DTSBUS0", - "CMT_MMCM_PHASERA_DTSBUS1", - "CMT_MMCM_PHASERREF0", - "CMT_MMCM_PHASERREF1", - "CMT_MMCM_PHASERREF_ABOVE0", - "CMT_MMCM_PHASERREF_ABOVE1", - "CMT_MMCM_PHASERREF_BELOW0", - "CMT_MMCM_PHASERREF_BELOW1", - "CMT_MMCM_PHASER_IN_A_ICLK", - "CMT_MMCM_PHASER_IN_A_ICLKDIV", - "CMT_MMCM_PHASER_IN_B_ICLK", - "CMT_MMCM_PHASER_IN_B_ICLKDIV", - "CMT_MMCM_PHASER_OUT_A_OCLK", - "CMT_MMCM_PHASER_OUT_A_OCLK1X_90", - "CMT_MMCM_PHASER_OUT_A_OCLKDIV", - "CMT_MMCM_PHASER_OUT_B_OCLK", - "CMT_MMCM_PHASER_OUT_B_OCLK1X_90", - "CMT_MMCM_PHASER_OUT_B_OCLKDIV", - "CMT_MMCM_PHYCTRL_SYNC_BB_DN", - "CMT_MMCM_PHYCTRL_SYNC_BB_UP", - "CMT_PHASER_A_ICLKDIV_TOIOI", - "CMT_PHASER_A_ICLK_TOIOI", - "CMT_PHASER_A_OCLK90_TOIOI", - "CMT_PHASER_A_OCLKDIV_TOIOI", - "CMT_PHASER_A_OCLK_TOIOI", - "CMT_R_LOWER_B_CLK_FREQ_BB0", - "CMT_R_LOWER_B_CLK_FREQ_BB1", - "CMT_R_LOWER_B_CLK_FREQ_BB2", - "CMT_R_LOWER_B_CLK_FREQ_BB3", - "CMT_R_LOWER_B_CLK_IN1_HCLK", - "CMT_R_LOWER_B_CLK_IN1_INT", - "CMT_R_LOWER_B_CLK_IN2_HCLK", - "CMT_R_LOWER_B_CLK_IN2_INT", - "CMT_R_LOWER_B_CLK_IN3_HCLK", - "CMT_R_LOWER_B_CLK_IN3_INT", - "CMT_R_LOWER_B_CLK_MMCM0", - "CMT_R_LOWER_B_CLK_MMCM1", - "CMT_R_LOWER_B_CLK_MMCM10", - "CMT_R_LOWER_B_CLK_MMCM11", - "CMT_R_LOWER_B_CLK_MMCM12", - "CMT_R_LOWER_B_CLK_MMCM13", - "CMT_R_LOWER_B_CLK_MMCM2", - "CMT_R_LOWER_B_CLK_MMCM3", - "CMT_R_LOWER_B_CLK_MMCM4", - "CMT_R_LOWER_B_CLK_MMCM5", - "CMT_R_LOWER_B_CLK_MMCM6", - "CMT_R_LOWER_B_CLK_MMCM7", - "CMT_R_LOWER_B_CLK_MMCM8", - "CMT_R_LOWER_B_CLK_MMCM9", - "CMT_R_LOWER_B_CLK_PERF0", - "CMT_R_LOWER_B_CLK_PERF1", - "CMT_R_LOWER_B_CLK_PERF2", - "CMT_R_LOWER_B_CLK_PERF3", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_BLOCK_OUTS_L_B0_12", - "CMT_TOP_BLOCK_OUTS_L_B0_13", - "CMT_TOP_BLOCK_OUTS_L_B0_14", - "CMT_TOP_BLOCK_OUTS_L_B0_15", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_12", - "CMT_TOP_BLOCK_OUTS_L_B1_13", - "CMT_TOP_BLOCK_OUTS_L_B1_14", - "CMT_TOP_BLOCK_OUTS_L_B1_15", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_BLOCK_OUTS_L_B2_12", - "CMT_TOP_BLOCK_OUTS_L_B2_13", - "CMT_TOP_BLOCK_OUTS_L_B2_14", - "CMT_TOP_BLOCK_OUTS_L_B2_15", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_12", - "CMT_TOP_BLOCK_OUTS_L_B3_13", - "CMT_TOP_BLOCK_OUTS_L_B3_14", - "CMT_TOP_BLOCK_OUTS_L_B3_15", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_BYP0_11", - "CMT_TOP_BYP0_12", - "CMT_TOP_BYP0_13", - "CMT_TOP_BYP0_14", - "CMT_TOP_BYP0_15", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_10", - "CMT_TOP_BYP1_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_BYP1_13", - "CMT_TOP_BYP1_14", - "CMT_TOP_BYP1_15", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP1_9", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_10", - "CMT_TOP_BYP2_11", - "CMT_TOP_BYP2_12", - "CMT_TOP_BYP2_13", - "CMT_TOP_BYP2_14", - "CMT_TOP_BYP2_15", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_10", - "CMT_TOP_BYP3_11", - "CMT_TOP_BYP3_12", - "CMT_TOP_BYP3_13", - "CMT_TOP_BYP3_14", - "CMT_TOP_BYP3_15", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP3_9", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_10", - "CMT_TOP_BYP4_11", - "CMT_TOP_BYP4_12", - "CMT_TOP_BYP4_13", - "CMT_TOP_BYP4_14", - "CMT_TOP_BYP4_15", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP4_9", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_10", - "CMT_TOP_BYP5_11", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP5_13", - "CMT_TOP_BYP5_14", - "CMT_TOP_BYP5_15", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP5_9", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_10", - "CMT_TOP_BYP6_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_BYP6_13", - "CMT_TOP_BYP6_14", - "CMT_TOP_BYP6_15", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP6_9", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_10", - "CMT_TOP_BYP7_11", - "CMT_TOP_BYP7_12", - "CMT_TOP_BYP7_13", - "CMT_TOP_BYP7_14", - "CMT_TOP_BYP7_15", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_BYP7_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_CLK0_12", - "CMT_TOP_CLK0_13", - "CMT_TOP_CLK0_14", - "CMT_TOP_CLK0_15", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK0_9", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_10", - "CMT_TOP_CLK1_11", - "CMT_TOP_CLK1_12", - "CMT_TOP_CLK1_13", - "CMT_TOP_CLK1_14", - "CMT_TOP_CLK1_15", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CLK1_9", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CTRL0_12", - "CMT_TOP_CTRL0_13", - "CMT_TOP_CTRL0_14", - "CMT_TOP_CTRL0_15", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL0_9", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_CTRL1_11", - "CMT_TOP_CTRL1_12", - "CMT_TOP_CTRL1_13", - "CMT_TOP_CTRL1_14", - "CMT_TOP_CTRL1_15", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_CTRL1_9", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_EE2A0_12", - "CMT_TOP_EE2A0_13", - "CMT_TOP_EE2A0_14", - "CMT_TOP_EE2A0_15", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A0_9", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_10", - "CMT_TOP_EE2A1_11", - "CMT_TOP_EE2A1_12", - "CMT_TOP_EE2A1_13", - "CMT_TOP_EE2A1_14", - "CMT_TOP_EE2A1_15", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A1_9", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_10", - "CMT_TOP_EE2A2_11", - "CMT_TOP_EE2A2_12", - "CMT_TOP_EE2A2_13", - "CMT_TOP_EE2A2_14", - "CMT_TOP_EE2A2_15", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A2_9", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_10", - "CMT_TOP_EE2A3_11", - "CMT_TOP_EE2A3_12", - "CMT_TOP_EE2A3_13", - "CMT_TOP_EE2A3_14", - "CMT_TOP_EE2A3_15", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_EE2BEG0_13", - "CMT_TOP_EE2BEG0_14", - "CMT_TOP_EE2BEG0_15", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_EE2BEG1_13", - "CMT_TOP_EE2BEG1_14", - "CMT_TOP_EE2BEG1_15", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_EE2BEG2_13", - "CMT_TOP_EE2BEG2_14", - "CMT_TOP_EE2BEG2_15", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_EE2BEG3_13", - "CMT_TOP_EE2BEG3_14", - "CMT_TOP_EE2BEG3_15", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_10", - "CMT_TOP_EE4A0_11", - "CMT_TOP_EE4A0_12", - "CMT_TOP_EE4A0_13", - "CMT_TOP_EE4A0_14", - "CMT_TOP_EE4A0_15", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A0_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_EE4A1_11", - "CMT_TOP_EE4A1_12", - "CMT_TOP_EE4A1_13", - "CMT_TOP_EE4A1_14", - "CMT_TOP_EE4A1_15", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A1_9", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_10", - "CMT_TOP_EE4A2_11", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EE4A2_13", - "CMT_TOP_EE4A2_14", - "CMT_TOP_EE4A2_15", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A2_9", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_EE4A3_11", - "CMT_TOP_EE4A3_12", - "CMT_TOP_EE4A3_13", - "CMT_TOP_EE4A3_14", - "CMT_TOP_EE4A3_15", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_10", - "CMT_TOP_EE4B0_11", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4B0_13", - "CMT_TOP_EE4B0_14", - "CMT_TOP_EE4B0_15", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B0_9", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_10", - "CMT_TOP_EE4B1_11", - "CMT_TOP_EE4B1_12", - "CMT_TOP_EE4B1_13", - "CMT_TOP_EE4B1_14", - "CMT_TOP_EE4B1_15", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B1_9", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_10", - "CMT_TOP_EE4B2_11", - "CMT_TOP_EE4B2_12", - "CMT_TOP_EE4B2_13", - "CMT_TOP_EE4B2_14", - "CMT_TOP_EE4B2_15", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B2_9", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_10", - "CMT_TOP_EE4B3_11", - "CMT_TOP_EE4B3_12", - "CMT_TOP_EE4B3_13", - "CMT_TOP_EE4B3_14", - "CMT_TOP_EE4B3_15", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4B3_9", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_EE4BEG0_13", - "CMT_TOP_EE4BEG0_14", - "CMT_TOP_EE4BEG0_15", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_EE4BEG1_13", - "CMT_TOP_EE4BEG1_14", - "CMT_TOP_EE4BEG1_15", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_EE4BEG2_12", - "CMT_TOP_EE4BEG2_13", - "CMT_TOP_EE4BEG2_14", - "CMT_TOP_EE4BEG2_15", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_EE4BEG3_13", - "CMT_TOP_EE4BEG3_14", - "CMT_TOP_EE4BEG3_15", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_10", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EE4C0_12", - "CMT_TOP_EE4C0_13", - "CMT_TOP_EE4C0_14", - "CMT_TOP_EE4C0_15", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C0_9", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_10", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EE4C1_12", - "CMT_TOP_EE4C1_13", - "CMT_TOP_EE4C1_14", - "CMT_TOP_EE4C1_15", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_EE4C2_12", - "CMT_TOP_EE4C2_13", - "CMT_TOP_EE4C2_14", - "CMT_TOP_EE4C2_15", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C2_9", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_EE4C3_11", - "CMT_TOP_EE4C3_12", - "CMT_TOP_EE4C3_13", - "CMT_TOP_EE4C3_14", - "CMT_TOP_EE4C3_15", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EE4C3_9", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_EL1BEG0_13", - "CMT_TOP_EL1BEG0_14", - "CMT_TOP_EL1BEG0_15", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_EL1BEG1_12", - "CMT_TOP_EL1BEG1_13", - "CMT_TOP_EL1BEG1_14", - "CMT_TOP_EL1BEG1_15", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_EL1BEG2_13", - "CMT_TOP_EL1BEG2_14", - "CMT_TOP_EL1BEG2_15", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_EL1BEG3_13", - "CMT_TOP_EL1BEG3_14", - "CMT_TOP_EL1BEG3_15", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_ER1BEG0_13", - "CMT_TOP_ER1BEG0_14", - "CMT_TOP_ER1BEG0_15", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_ER1BEG1_13", - "CMT_TOP_ER1BEG1_14", - "CMT_TOP_ER1BEG1_15", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_ER1BEG2_13", - "CMT_TOP_ER1BEG2_14", - "CMT_TOP_ER1BEG2_15", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_ER1BEG3_13", - "CMT_TOP_ER1BEG3_14", - "CMT_TOP_ER1BEG3_15", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_10", - "CMT_TOP_FAN0_11", - "CMT_TOP_FAN0_12", - "CMT_TOP_FAN0_13", - "CMT_TOP_FAN0_14", - "CMT_TOP_FAN0_15", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN0_9", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_10", - "CMT_TOP_FAN1_11", - "CMT_TOP_FAN1_12", - "CMT_TOP_FAN1_13", - "CMT_TOP_FAN1_14", - "CMT_TOP_FAN1_15", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN1_9", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_10", - "CMT_TOP_FAN2_11", - "CMT_TOP_FAN2_12", - "CMT_TOP_FAN2_13", - "CMT_TOP_FAN2_14", - "CMT_TOP_FAN2_15", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN2_9", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_FAN3_12", - "CMT_TOP_FAN3_13", - "CMT_TOP_FAN3_14", - "CMT_TOP_FAN3_15", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN3_9", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_10", - "CMT_TOP_FAN4_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_FAN4_13", - "CMT_TOP_FAN4_14", - "CMT_TOP_FAN4_15", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN4_9", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_10", - "CMT_TOP_FAN5_11", - "CMT_TOP_FAN5_12", - "CMT_TOP_FAN5_13", - "CMT_TOP_FAN5_14", - "CMT_TOP_FAN5_15", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN5_9", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_10", - "CMT_TOP_FAN6_11", - "CMT_TOP_FAN6_12", - "CMT_TOP_FAN6_13", - "CMT_TOP_FAN6_14", - "CMT_TOP_FAN6_15", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN6_9", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_FAN7_11", - "CMT_TOP_FAN7_12", - "CMT_TOP_FAN7_13", - "CMT_TOP_FAN7_14", - "CMT_TOP_FAN7_15", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_FAN7_9", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_ICLKDIV_13", - "CMT_TOP_ICLKDIV_14", - "CMT_TOP_ICLKDIV_15", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_ICLK_11", - "CMT_TOP_ICLK_12", - "CMT_TOP_ICLK_13", - "CMT_TOP_ICLK_14", - "CMT_TOP_ICLK_15", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_10", - "CMT_TOP_IMUX0_11", - "CMT_TOP_IMUX0_12", - "CMT_TOP_IMUX0_13", - "CMT_TOP_IMUX0_14", - "CMT_TOP_IMUX0_15", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_10", - "CMT_TOP_IMUX10_11", - "CMT_TOP_IMUX10_12", - "CMT_TOP_IMUX10_13", - "CMT_TOP_IMUX10_14", - "CMT_TOP_IMUX10_15", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - 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"CMT_TOP_IMUX39_0", - "CMT_TOP_IMUX39_1", - "CMT_TOP_IMUX39_10", - "CMT_TOP_IMUX39_11", - "CMT_TOP_IMUX39_12", - "CMT_TOP_IMUX39_13", - "CMT_TOP_IMUX39_14", - "CMT_TOP_IMUX39_15", - "CMT_TOP_IMUX39_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_IMUX39_5", - "CMT_TOP_IMUX39_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX39_8", - "CMT_TOP_IMUX39_9", - "CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_10", - "CMT_TOP_IMUX3_11", - "CMT_TOP_IMUX3_12", - "CMT_TOP_IMUX3_13", - "CMT_TOP_IMUX3_14", - "CMT_TOP_IMUX3_15", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX3_9", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_IMUX40_12", - "CMT_TOP_IMUX40_13", - "CMT_TOP_IMUX40_14", - "CMT_TOP_IMUX40_15", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX40_9", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_10", - "CMT_TOP_IMUX41_11", - "CMT_TOP_IMUX41_12", - "CMT_TOP_IMUX41_13", - "CMT_TOP_IMUX41_14", - "CMT_TOP_IMUX41_15", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX41_9", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX42_11", - "CMT_TOP_IMUX42_12", - "CMT_TOP_IMUX42_13", - "CMT_TOP_IMUX42_14", - "CMT_TOP_IMUX42_15", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX42_9", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_IMUX43_12", - "CMT_TOP_IMUX43_13", - "CMT_TOP_IMUX43_14", - "CMT_TOP_IMUX43_15", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX43_9", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_10", - "CMT_TOP_IMUX44_11", - "CMT_TOP_IMUX44_12", - "CMT_TOP_IMUX44_13", - "CMT_TOP_IMUX44_14", - "CMT_TOP_IMUX44_15", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX45_11", - "CMT_TOP_IMUX45_12", - "CMT_TOP_IMUX45_13", - "CMT_TOP_IMUX45_14", - "CMT_TOP_IMUX45_15", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX45_9", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_10", - "CMT_TOP_IMUX46_11", - "CMT_TOP_IMUX46_12", - "CMT_TOP_IMUX46_13", - "CMT_TOP_IMUX46_14", - "CMT_TOP_IMUX46_15", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX46_9", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX47_11", - "CMT_TOP_IMUX47_12", - "CMT_TOP_IMUX47_13", - "CMT_TOP_IMUX47_14", - "CMT_TOP_IMUX47_15", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX47_9", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_10", - "CMT_TOP_IMUX4_11", - "CMT_TOP_IMUX4_12", - "CMT_TOP_IMUX4_13", - "CMT_TOP_IMUX4_14", - "CMT_TOP_IMUX4_15", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX4_9", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX5_11", - "CMT_TOP_IMUX5_12", - "CMT_TOP_IMUX5_13", - "CMT_TOP_IMUX5_14", - "CMT_TOP_IMUX5_15", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_10", - "CMT_TOP_IMUX6_11", - "CMT_TOP_IMUX6_12", - "CMT_TOP_IMUX6_13", - "CMT_TOP_IMUX6_14", - "CMT_TOP_IMUX6_15", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX6_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_10", - "CMT_TOP_IMUX7_11", - "CMT_TOP_IMUX7_12", - "CMT_TOP_IMUX7_13", - "CMT_TOP_IMUX7_14", - "CMT_TOP_IMUX7_15", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX7_9", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_IMUX8_12", - "CMT_TOP_IMUX8_13", - "CMT_TOP_IMUX8_14", - "CMT_TOP_IMUX8_15", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_10", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX9_13", - "CMT_TOP_IMUX9_14", - "CMT_TOP_IMUX9_15", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX9_9", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_10", - "CMT_TOP_LH10_11", - "CMT_TOP_LH10_12", - "CMT_TOP_LH10_13", - "CMT_TOP_LH10_14", - "CMT_TOP_LH10_15", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH10_9", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_10", - "CMT_TOP_LH11_11", - "CMT_TOP_LH11_12", - "CMT_TOP_LH11_13", - "CMT_TOP_LH11_14", - "CMT_TOP_LH11_15", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH11_9", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_10", - "CMT_TOP_LH12_11", - "CMT_TOP_LH12_12", - "CMT_TOP_LH12_13", - "CMT_TOP_LH12_14", - "CMT_TOP_LH12_15", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH12_9", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_10", - "CMT_TOP_LH1_11", - "CMT_TOP_LH1_12", - "CMT_TOP_LH1_13", - "CMT_TOP_LH1_14", - "CMT_TOP_LH1_15", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH1_9", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_10", - "CMT_TOP_LH2_11", - "CMT_TOP_LH2_12", - "CMT_TOP_LH2_13", - "CMT_TOP_LH2_14", - "CMT_TOP_LH2_15", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH2_9", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_10", - "CMT_TOP_LH3_11", - "CMT_TOP_LH3_12", - "CMT_TOP_LH3_13", - "CMT_TOP_LH3_14", - "CMT_TOP_LH3_15", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH3_9", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_10", - "CMT_TOP_LH4_11", - "CMT_TOP_LH4_12", - "CMT_TOP_LH4_13", - "CMT_TOP_LH4_14", - "CMT_TOP_LH4_15", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH4_9", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_10", - "CMT_TOP_LH5_11", - "CMT_TOP_LH5_12", - "CMT_TOP_LH5_13", - "CMT_TOP_LH5_14", - "CMT_TOP_LH5_15", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH5_9", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_10", - "CMT_TOP_LH6_11", - "CMT_TOP_LH6_12", - "CMT_TOP_LH6_13", - "CMT_TOP_LH6_14", - "CMT_TOP_LH6_15", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH6_9", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_10", - "CMT_TOP_LH7_11", - "CMT_TOP_LH7_12", - "CMT_TOP_LH7_13", - "CMT_TOP_LH7_14", - "CMT_TOP_LH7_15", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH7_9", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_10", - "CMT_TOP_LH8_11", - "CMT_TOP_LH8_12", - "CMT_TOP_LH8_13", - "CMT_TOP_LH8_14", - "CMT_TOP_LH8_15", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH8_9", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_10", - "CMT_TOP_LH9_11", - "CMT_TOP_LH9_12", - "CMT_TOP_LH9_13", - "CMT_TOP_LH9_14", - "CMT_TOP_LH9_15", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LH9_9", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_LOGIC_OUTS_L_B0_13", - "CMT_TOP_LOGIC_OUTS_L_B0_14", - "CMT_TOP_LOGIC_OUTS_L_B0_15", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_LOGIC_OUTS_L_B10_13", - "CMT_TOP_LOGIC_OUTS_L_B10_14", - "CMT_TOP_LOGIC_OUTS_L_B10_15", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_LOGIC_OUTS_L_B11_13", - "CMT_TOP_LOGIC_OUTS_L_B11_14", - "CMT_TOP_LOGIC_OUTS_L_B11_15", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_LOGIC_OUTS_L_B12_13", - "CMT_TOP_LOGIC_OUTS_L_B12_14", - "CMT_TOP_LOGIC_OUTS_L_B12_15", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_10", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_LOGIC_OUTS_L_B13_13", - "CMT_TOP_LOGIC_OUTS_L_B13_14", - "CMT_TOP_LOGIC_OUTS_L_B13_15", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_TOP_LOGIC_OUTS_L_B14_13", - "CMT_TOP_LOGIC_OUTS_L_B14_14", - "CMT_TOP_LOGIC_OUTS_L_B14_15", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_LOGIC_OUTS_L_B15_13", - "CMT_TOP_LOGIC_OUTS_L_B15_14", - "CMT_TOP_LOGIC_OUTS_L_B15_15", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_LOGIC_OUTS_L_B16_13", - "CMT_TOP_LOGIC_OUTS_L_B16_14", - "CMT_TOP_LOGIC_OUTS_L_B16_15", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B17_13", - "CMT_TOP_LOGIC_OUTS_L_B17_14", - "CMT_TOP_LOGIC_OUTS_L_B17_15", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_LOGIC_OUTS_L_B18_13", - "CMT_TOP_LOGIC_OUTS_L_B18_14", - "CMT_TOP_LOGIC_OUTS_L_B18_15", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_LOGIC_OUTS_L_B19_13", - "CMT_TOP_LOGIC_OUTS_L_B19_14", - "CMT_TOP_LOGIC_OUTS_L_B19_15", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_LOGIC_OUTS_L_B1_13", - "CMT_TOP_LOGIC_OUTS_L_B1_14", - "CMT_TOP_LOGIC_OUTS_L_B1_15", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_LOGIC_OUTS_L_B20_13", - "CMT_TOP_LOGIC_OUTS_L_B20_14", - "CMT_TOP_LOGIC_OUTS_L_B20_15", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_LOGIC_OUTS_L_B21_13", - "CMT_TOP_LOGIC_OUTS_L_B21_14", - "CMT_TOP_LOGIC_OUTS_L_B21_15", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_LOGIC_OUTS_L_B22_13", - "CMT_TOP_LOGIC_OUTS_L_B22_14", - "CMT_TOP_LOGIC_OUTS_L_B22_15", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B23_13", - "CMT_TOP_LOGIC_OUTS_L_B23_14", - "CMT_TOP_LOGIC_OUTS_L_B23_15", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_LOGIC_OUTS_L_B2_13", - "CMT_TOP_LOGIC_OUTS_L_B2_14", - "CMT_TOP_LOGIC_OUTS_L_B2_15", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B3_13", - "CMT_TOP_LOGIC_OUTS_L_B3_14", - "CMT_TOP_LOGIC_OUTS_L_B3_15", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_LOGIC_OUTS_L_B4_13", - "CMT_TOP_LOGIC_OUTS_L_B4_14", - "CMT_TOP_LOGIC_OUTS_L_B4_15", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_LOGIC_OUTS_L_B5_13", - "CMT_TOP_LOGIC_OUTS_L_B5_14", - "CMT_TOP_LOGIC_OUTS_L_B5_15", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_LOGIC_OUTS_L_B6_13", - "CMT_TOP_LOGIC_OUTS_L_B6_14", - "CMT_TOP_LOGIC_OUTS_L_B6_15", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_LOGIC_OUTS_L_B7_13", - "CMT_TOP_LOGIC_OUTS_L_B7_14", - "CMT_TOP_LOGIC_OUTS_L_B7_15", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_LOGIC_OUTS_L_B8_13", - "CMT_TOP_LOGIC_OUTS_L_B8_14", - "CMT_TOP_LOGIC_OUTS_L_B8_15", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_LOGIC_OUTS_L_B9_13", - "CMT_TOP_LOGIC_OUTS_L_B9_14", - "CMT_TOP_LOGIC_OUTS_L_B9_15", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_MONITOR_N_12", - "CMT_TOP_MONITOR_N_13", - "CMT_TOP_MONITOR_N_14", - "CMT_TOP_MONITOR_N_15", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_MONITOR_P_13", - "CMT_TOP_MONITOR_P_14", - "CMT_TOP_MONITOR_P_15", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_10", - "CMT_TOP_NE2A0_11", - "CMT_TOP_NE2A0_12", - "CMT_TOP_NE2A0_13", - "CMT_TOP_NE2A0_14", - "CMT_TOP_NE2A0_15", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A0_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_10", - "CMT_TOP_NE2A1_11", - "CMT_TOP_NE2A1_12", - "CMT_TOP_NE2A1_13", - "CMT_TOP_NE2A1_14", - "CMT_TOP_NE2A1_15", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_10", - "CMT_TOP_NE2A2_11", - "CMT_TOP_NE2A2_12", - "CMT_TOP_NE2A2_13", - "CMT_TOP_NE2A2_14", - "CMT_TOP_NE2A2_15", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A2_9", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_10", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NE2A3_12", - "CMT_TOP_NE2A3_13", - "CMT_TOP_NE2A3_14", - "CMT_TOP_NE2A3_15", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_NE4BEG0_13", - "CMT_TOP_NE4BEG0_14", - "CMT_TOP_NE4BEG0_15", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_NE4BEG1_13", - "CMT_TOP_NE4BEG1_14", - "CMT_TOP_NE4BEG1_15", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_NE4BEG2_13", - "CMT_TOP_NE4BEG2_14", - "CMT_TOP_NE4BEG2_15", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_NE4BEG3_13", - "CMT_TOP_NE4BEG3_14", - "CMT_TOP_NE4BEG3_15", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_10", - "CMT_TOP_NE4C0_11", - "CMT_TOP_NE4C0_12", - "CMT_TOP_NE4C0_13", - "CMT_TOP_NE4C0_14", - "CMT_TOP_NE4C0_15", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_9", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_NE4C1_11", - "CMT_TOP_NE4C1_12", - "CMT_TOP_NE4C1_13", - "CMT_TOP_NE4C1_14", - "CMT_TOP_NE4C1_15", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C1_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_10", - "CMT_TOP_NE4C2_11", - "CMT_TOP_NE4C2_12", - "CMT_TOP_NE4C2_13", - "CMT_TOP_NE4C2_14", - "CMT_TOP_NE4C2_15", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C2_9", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_10", - "CMT_TOP_NE4C3_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_NE4C3_13", - "CMT_TOP_NE4C3_14", - "CMT_TOP_NE4C3_15", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NE4C3_9", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_10", - "CMT_TOP_NW2A0_11", - "CMT_TOP_NW2A0_12", - "CMT_TOP_NW2A0_13", - "CMT_TOP_NW2A0_14", - "CMT_TOP_NW2A0_15", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A0_9", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_10", - "CMT_TOP_NW2A1_11", - "CMT_TOP_NW2A1_12", - "CMT_TOP_NW2A1_13", - "CMT_TOP_NW2A1_14", - "CMT_TOP_NW2A1_15", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_10", - "CMT_TOP_NW2A2_11", - "CMT_TOP_NW2A2_12", - "CMT_TOP_NW2A2_13", - "CMT_TOP_NW2A2_14", - "CMT_TOP_NW2A2_15", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A2_9", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW2A3_11", - "CMT_TOP_NW2A3_12", - "CMT_TOP_NW2A3_13", - "CMT_TOP_NW2A3_14", - "CMT_TOP_NW2A3_15", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW2A3_9", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_10", - "CMT_TOP_NW4A0_11", - "CMT_TOP_NW4A0_12", - "CMT_TOP_NW4A0_13", - "CMT_TOP_NW4A0_14", - "CMT_TOP_NW4A0_15", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_10", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A1_12", - "CMT_TOP_NW4A1_13", - "CMT_TOP_NW4A1_14", - "CMT_TOP_NW4A1_15", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A1_9", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW4A2_11", - "CMT_TOP_NW4A2_12", - "CMT_TOP_NW4A2_13", - "CMT_TOP_NW4A2_14", - "CMT_TOP_NW4A2_15", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A2_9", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_10", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4A3_12", - "CMT_TOP_NW4A3_13", - "CMT_TOP_NW4A3_14", - "CMT_TOP_NW4A3_15", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_10", - "CMT_TOP_NW4END0_11", - "CMT_TOP_NW4END0_12", - "CMT_TOP_NW4END0_13", - "CMT_TOP_NW4END0_14", - "CMT_TOP_NW4END0_15", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END0_9", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_10", - "CMT_TOP_NW4END1_11", - "CMT_TOP_NW4END1_12", - "CMT_TOP_NW4END1_13", - "CMT_TOP_NW4END1_14", - "CMT_TOP_NW4END1_15", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END1_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_10", - "CMT_TOP_NW4END2_11", - "CMT_TOP_NW4END2_12", - "CMT_TOP_NW4END2_13", - "CMT_TOP_NW4END2_14", - "CMT_TOP_NW4END2_15", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END2_9", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4END3_11", - "CMT_TOP_NW4END3_12", - "CMT_TOP_NW4END3_13", - "CMT_TOP_NW4END3_14", - "CMT_TOP_NW4END3_15", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_NW4END3_9", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_OCLK1X_90_13", - "CMT_TOP_OCLK1X_90_14", - "CMT_TOP_OCLK1X_90_15", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_OCLKDIV_13", - "CMT_TOP_OCLKDIV_14", - "CMT_TOP_OCLKDIV_15", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_10", - "CMT_TOP_OCLK_11", - "CMT_TOP_OCLK_12", - "CMT_TOP_OCLK_13", - "CMT_TOP_OCLK_14", - "CMT_TOP_OCLK_15", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_OCLK_9", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_10", - "CMT_TOP_SE2A0_11", - "CMT_TOP_SE2A0_12", - "CMT_TOP_SE2A0_13", - "CMT_TOP_SE2A0_14", - "CMT_TOP_SE2A0_15", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A0_9", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_10", - "CMT_TOP_SE2A1_11", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE2A1_13", - "CMT_TOP_SE2A1_14", - "CMT_TOP_SE2A1_15", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A1_9", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_10", - "CMT_TOP_SE2A2_11", - "CMT_TOP_SE2A2_12", - "CMT_TOP_SE2A2_13", - "CMT_TOP_SE2A2_14", - "CMT_TOP_SE2A2_15", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_10", - "CMT_TOP_SE2A3_11", - "CMT_TOP_SE2A3_12", - "CMT_TOP_SE2A3_13", - "CMT_TOP_SE2A3_14", - "CMT_TOP_SE2A3_15", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE2A3_9", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_SE4BEG0_12", - "CMT_TOP_SE4BEG0_13", - "CMT_TOP_SE4BEG0_14", - "CMT_TOP_SE4BEG0_15", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_SE4BEG1_13", - "CMT_TOP_SE4BEG1_14", - "CMT_TOP_SE4BEG1_15", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SE4BEG2_12", - "CMT_TOP_SE4BEG2_13", - "CMT_TOP_SE4BEG2_14", - "CMT_TOP_SE4BEG2_15", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG3_12", - "CMT_TOP_SE4BEG3_13", - "CMT_TOP_SE4BEG3_14", - "CMT_TOP_SE4BEG3_15", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_10", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE4C0_12", - "CMT_TOP_SE4C0_13", - "CMT_TOP_SE4C0_14", - "CMT_TOP_SE4C0_15", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C0_9", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_10", - "CMT_TOP_SE4C1_11", - "CMT_TOP_SE4C1_12", - "CMT_TOP_SE4C1_13", - "CMT_TOP_SE4C1_14", - "CMT_TOP_SE4C1_15", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C1_9", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_10", - "CMT_TOP_SE4C2_11", - "CMT_TOP_SE4C2_12", - "CMT_TOP_SE4C2_13", - "CMT_TOP_SE4C2_14", - "CMT_TOP_SE4C2_15", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C2_9", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_10", - "CMT_TOP_SE4C3_11", - "CMT_TOP_SE4C3_12", - "CMT_TOP_SE4C3_13", - "CMT_TOP_SE4C3_14", - "CMT_TOP_SE4C3_15", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SE4C3_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SW2A0_11", - "CMT_TOP_SW2A0_12", - "CMT_TOP_SW2A0_13", - "CMT_TOP_SW2A0_14", - "CMT_TOP_SW2A0_15", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A0_9", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_10", - "CMT_TOP_SW2A1_11", - "CMT_TOP_SW2A1_12", - "CMT_TOP_SW2A1_13", - "CMT_TOP_SW2A1_14", - "CMT_TOP_SW2A1_15", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A1_9", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_10", - "CMT_TOP_SW2A2_11", - "CMT_TOP_SW2A2_12", - "CMT_TOP_SW2A2_13", - "CMT_TOP_SW2A2_14", - "CMT_TOP_SW2A2_15", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A2_9", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_10", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SW2A3_12", - "CMT_TOP_SW2A3_13", - "CMT_TOP_SW2A3_14", - "CMT_TOP_SW2A3_15", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW2A3_9", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_SW4A0_11", - "CMT_TOP_SW4A0_12", - "CMT_TOP_SW4A0_13", - "CMT_TOP_SW4A0_14", - "CMT_TOP_SW4A0_15", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_10", - "CMT_TOP_SW4A1_11", - "CMT_TOP_SW4A1_12", - "CMT_TOP_SW4A1_13", - "CMT_TOP_SW4A1_14", - "CMT_TOP_SW4A1_15", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_10", - "CMT_TOP_SW4A2_11", - "CMT_TOP_SW4A2_12", - "CMT_TOP_SW4A2_13", - "CMT_TOP_SW4A2_14", - "CMT_TOP_SW4A2_15", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A2_9", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_10", - "CMT_TOP_SW4A3_11", - "CMT_TOP_SW4A3_12", - "CMT_TOP_SW4A3_13", - "CMT_TOP_SW4A3_14", - "CMT_TOP_SW4A3_15", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4A3_9", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_10", - "CMT_TOP_SW4END0_11", - "CMT_TOP_SW4END0_12", - "CMT_TOP_SW4END0_13", - "CMT_TOP_SW4END0_14", - "CMT_TOP_SW4END0_15", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END0_9", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_10", - "CMT_TOP_SW4END1_11", - "CMT_TOP_SW4END1_12", - "CMT_TOP_SW4END1_13", - "CMT_TOP_SW4END1_14", - "CMT_TOP_SW4END1_15", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END1_9", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_SW4END2_11", - "CMT_TOP_SW4END2_12", - "CMT_TOP_SW4END2_13", - "CMT_TOP_SW4END2_14", - "CMT_TOP_SW4END2_15", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END2_9", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_10", - "CMT_TOP_SW4END3_11", - "CMT_TOP_SW4END3_12", - "CMT_TOP_SW4END3_13", - "CMT_TOP_SW4END3_14", - "CMT_TOP_SW4END3_15", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_SW4END3_9", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_10", - "CMT_TOP_WL1END0_11", - "CMT_TOP_WL1END0_12", - "CMT_TOP_WL1END0_13", - "CMT_TOP_WL1END0_14", - "CMT_TOP_WL1END0_15", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END0_9", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_10", - "CMT_TOP_WL1END1_11", - "CMT_TOP_WL1END1_12", - "CMT_TOP_WL1END1_13", - "CMT_TOP_WL1END1_14", - "CMT_TOP_WL1END1_15", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END1_9", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_10", - "CMT_TOP_WL1END2_11", - "CMT_TOP_WL1END2_12", - "CMT_TOP_WL1END2_13", - "CMT_TOP_WL1END2_14", - "CMT_TOP_WL1END2_15", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END2_9", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_10", - "CMT_TOP_WL1END3_11", - "CMT_TOP_WL1END3_12", - "CMT_TOP_WL1END3_13", - "CMT_TOP_WL1END3_14", - "CMT_TOP_WL1END3_15", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WL1END3_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END0_11", - "CMT_TOP_WR1END0_12", - "CMT_TOP_WR1END0_13", - "CMT_TOP_WR1END0_14", - "CMT_TOP_WR1END0_15", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_WR1END1_12", - "CMT_TOP_WR1END1_13", - "CMT_TOP_WR1END1_14", - "CMT_TOP_WR1END1_15", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END1_9", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_10", - "CMT_TOP_WR1END2_11", - "CMT_TOP_WR1END2_12", - "CMT_TOP_WR1END2_13", - "CMT_TOP_WR1END2_14", - "CMT_TOP_WR1END2_15", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END2_9", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_10", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WR1END3_12", - "CMT_TOP_WR1END3_13", - "CMT_TOP_WR1END3_14", - "CMT_TOP_WR1END3_15", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WR1END3_9", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_10", - "CMT_TOP_WW2A0_11", - "CMT_TOP_WW2A0_12", - "CMT_TOP_WW2A0_13", - "CMT_TOP_WW2A0_14", - "CMT_TOP_WW2A0_15", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A0_9", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_10", - "CMT_TOP_WW2A1_11", - "CMT_TOP_WW2A1_12", - "CMT_TOP_WW2A1_13", - "CMT_TOP_WW2A1_14", - "CMT_TOP_WW2A1_15", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A1_9", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_10", - "CMT_TOP_WW2A2_11", - "CMT_TOP_WW2A2_12", - "CMT_TOP_WW2A2_13", - "CMT_TOP_WW2A2_14", - "CMT_TOP_WW2A2_15", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A2_9", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_10", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WW2A3_12", - "CMT_TOP_WW2A3_13", - "CMT_TOP_WW2A3_14", - "CMT_TOP_WW2A3_15", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2A3_9", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_10", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW2END0_12", - "CMT_TOP_WW2END0_13", - "CMT_TOP_WW2END0_14", - "CMT_TOP_WW2END0_15", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_10", - "CMT_TOP_WW2END1_11", - "CMT_TOP_WW2END1_12", - "CMT_TOP_WW2END1_13", - "CMT_TOP_WW2END1_14", - "CMT_TOP_WW2END1_15", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END1_9", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_10", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WW2END2_12", - "CMT_TOP_WW2END2_13", - "CMT_TOP_WW2END2_14", - "CMT_TOP_WW2END2_15", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_10", - "CMT_TOP_WW2END3_11", - "CMT_TOP_WW2END3_12", - "CMT_TOP_WW2END3_13", - "CMT_TOP_WW2END3_14", - "CMT_TOP_WW2END3_15", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW2END3_9", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_10", - "CMT_TOP_WW4A0_11", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4A0_13", - "CMT_TOP_WW4A0_14", - "CMT_TOP_WW4A0_15", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_10", - "CMT_TOP_WW4A1_11", - "CMT_TOP_WW4A1_12", - "CMT_TOP_WW4A1_13", - "CMT_TOP_WW4A1_14", - "CMT_TOP_WW4A1_15", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_10", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WW4A2_12", - "CMT_TOP_WW4A2_13", - "CMT_TOP_WW4A2_14", - "CMT_TOP_WW4A2_15", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A2_9", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_10", - "CMT_TOP_WW4A3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_WW4A3_13", - "CMT_TOP_WW4A3_14", - "CMT_TOP_WW4A3_15", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4A3_9", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_10", - "CMT_TOP_WW4B0_11", - "CMT_TOP_WW4B0_12", - "CMT_TOP_WW4B0_13", - "CMT_TOP_WW4B0_14", - "CMT_TOP_WW4B0_15", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_9", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_10", - "CMT_TOP_WW4B1_11", - "CMT_TOP_WW4B1_12", - "CMT_TOP_WW4B1_13", - "CMT_TOP_WW4B1_14", - "CMT_TOP_WW4B1_15", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_10", - "CMT_TOP_WW4B2_11", - "CMT_TOP_WW4B2_12", - "CMT_TOP_WW4B2_13", - "CMT_TOP_WW4B2_14", - "CMT_TOP_WW4B2_15", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_10", - "CMT_TOP_WW4B3_11", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4B3_13", - "CMT_TOP_WW4B3_14", - "CMT_TOP_WW4B3_15", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4B3_9", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_10", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4C0_12", - "CMT_TOP_WW4C0_13", - "CMT_TOP_WW4C0_14", - "CMT_TOP_WW4C0_15", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C0_9", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_WW4C1_12", - "CMT_TOP_WW4C1_13", - "CMT_TOP_WW4C1_14", - "CMT_TOP_WW4C1_15", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C1_9", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_10", - "CMT_TOP_WW4C2_11", - "CMT_TOP_WW4C2_12", - "CMT_TOP_WW4C2_13", - "CMT_TOP_WW4C2_14", - "CMT_TOP_WW4C2_15", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C2_9", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_WW4C3_12", - "CMT_TOP_WW4C3_13", - "CMT_TOP_WW4C3_14", - "CMT_TOP_WW4C3_15", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4C3_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_WW4END0_12", - "CMT_TOP_WW4END0_13", - "CMT_TOP_WW4END0_14", - "CMT_TOP_WW4END0_15", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END0_9", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_10", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WW4END1_12", - "CMT_TOP_WW4END1_13", - "CMT_TOP_WW4END1_14", - "CMT_TOP_WW4END1_15", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END1_9", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_WW4END2_12", - "CMT_TOP_WW4END2_13", - "CMT_TOP_WW4END2_14", - "CMT_TOP_WW4END2_15", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END2_9", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_10", - "CMT_TOP_WW4END3_11", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WW4END3_13", - "CMT_TOP_WW4END3_14", - "CMT_TOP_WW4END3_15", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4END3_9", - "MMCMOUT_CLK_FREQ_BB_0", - "MMCMOUT_CLK_FREQ_BB_1", - "MMCMOUT_CLK_FREQ_BB_2", - "MMCMOUT_CLK_FREQ_BB_3", - "MMCM_CLK_FREQ_BB_NS0", - "MMCM_CLK_FREQ_BB_NS1", - "MMCM_CLK_FREQ_BB_NS2", - "MMCM_CLK_FREQ_BB_NS3", - "MMCM_CLK_FREQ_BB_REBUF0_NS", - "MMCM_CLK_FREQ_BB_REBUF1_NS", - "MMCM_CLK_FREQ_BB_REBUF2_NS", - "MMCM_CLK_FREQ_BB_REBUF3_NS" - ] + "wires": { + "CMT_LR_LOWER_B_CLKFBOUT2IN": null, + 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"CMT_TOP_WW4END2_6": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_7": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_8": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END2_9": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_0": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_1": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_10": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_11": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_12": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_13": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_14": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_15": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_2": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_3": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_4": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_5": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_6": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_7": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_8": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_9": { + "cap": "78.000", + "res": "317.510" + }, + "MMCMOUT_CLK_FREQ_BB_0": null, + "MMCMOUT_CLK_FREQ_BB_1": null, + "MMCMOUT_CLK_FREQ_BB_2": null, + "MMCMOUT_CLK_FREQ_BB_3": null, + "MMCM_CLK_FREQ_BB_NS0": null, + "MMCM_CLK_FREQ_BB_NS1": null, + "MMCM_CLK_FREQ_BB_NS2": null, + "MMCM_CLK_FREQ_BB_NS3": null, + "MMCM_CLK_FREQ_BB_REBUF0_NS": null, + "MMCM_CLK_FREQ_BB_REBUF1_NS": null, + "MMCM_CLK_FREQ_BB_REBUF2_NS": null, + "MMCM_CLK_FREQ_BB_REBUF3_NS": null + } } diff --git a/kintex7/tile_type_CMT_TOP_R_LOWER_T.json b/kintex7/tile_type_CMT_TOP_R_LOWER_T.json index 27886d4..11f9e81 100644 --- a/kintex7/tile_type_CMT_TOP_R_LOWER_T.json +++ b/kintex7/tile_type_CMT_TOP_R_LOWER_T.json @@ -2,1962 +2,6082 @@ "pips": { "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_A->CMT_PHASER_IN_CA_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_A" }, "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASERIN_B->CMT_PHASER_IN_DB_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASERIN_B" }, "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_A->CMT_PHASER_OUT_CA_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_A" }, "CMT_TOP_R_LOWER_T.CMT_PHASERREF_DOWN_PHASEROUT_B->CMT_PHASER_OUT_DB_PHASEREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_PHASEREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASERREF_DOWN_PHASEROUT_B" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_CA_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_IN_DB_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_CA_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB0->CMT_PHASER_OUT_DB_ENCALIBPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_CA_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_IN_DB_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_CA_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_ENCALIB1->CMT_PHASER_OUT_DB_ENCALIBPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_ENCALIB1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING0->CMT_PHASER_IN_CA_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IBURSTPENDING0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IBURSTPENDING1->CMT_PHASER_IN_DB_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IBURSTPENDING1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKA0->CMT_PHASER_IN_CA_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IRANKA0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKA1->CMT_PHASER_IN_CA_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IRANKA1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKB0->CMT_PHASER_IN_DB_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IRANKB0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_IRANKB1->CMT_PHASER_IN_DB_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_IRANKB1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING0->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_OBURSTPENDING0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_OBURSTPENDING1->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_BOT_OBURSTPENDING1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_CA_FREQREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.118", + "0.181", + "0.204" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_CA_FREQREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.118", + "0.181", + "0.204" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_IN_DB_FREQREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.180", + "0.203" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_DB_FREQREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.180", + "0.203" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_CA_FREQREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.108", + "0.123", + "0.188", + "0.211" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_OUT_CA_FREQREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.108", + "0.123", + "0.188", + "0.211" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_0->>CMT_PHASER_OUT_DB_FREQREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.108", + "0.123", + "0.188", + "0.211" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_OUT_DB_FREQREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.108", + "0.123", + "0.188", + "0.211" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_CA_MEMREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.105", + "0.118", + "0.181", + "0.204" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_CA_MEMREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.105", + "0.118", + "0.181", + "0.204" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_IN_DB_MEMREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.180", + "0.203" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_DB_MEMREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.180", + "0.203" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_CA_MEMREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.096", + "0.108", + "0.175", + "0.197" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_OUT_CA_MEMREFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.096", + "0.108", + "0.175", + "0.197" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_BOT_REFMUX_1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_BOT_REFMUX_1->>CMT_PHASER_OUT_DB_MEMREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.087", + "0.098", + "0.166", + "0.187" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_WRENABLE" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B21_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSFOUND" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_B_ICLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_ICLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLK" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_B_WRCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_WRCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLKDIV" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ISERDESRST" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_DB_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_B_RCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_RCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_RCLK" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_B_WREN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_B_WREN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_WRENABLE" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_A_RDCLK_TOFIFO->CMT_PHASER_OUT_A_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK->>CMT_PHASER_B_OCLK_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.043", + "0.071", + "0.080" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_B_OCLK_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.043", + "0.071", + "0.080" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_B_OCLK" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLK1X_90->>CMT_PHASER_B_OCLK90_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.036", + "0.041", + "0.065", + "0.073" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_B_OCLK90_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.036", + "0.041", + "0.065", + "0.073" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_B_OCLK1X_90" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_OCLKDIV->>CMT_PHASER_B_OCLKDIV_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.045", + "0.072", + "0.081" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_B_OCLKDIV_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.045", + "0.072", + "0.081" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_B_OCLKDIV" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_B_RDCLK_TOFIFO->CMT_PHASER_OUT_B_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS0->CMT_PHASERA_CTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_CTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_CTSBUS1->CMT_PHASERA_CTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_CTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS0->CMT_PHASERA_DQSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DQSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DQSBUS1->CMT_PHASERA_DQSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DQSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS0->CMT_PHASERA_DTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_DTSBUS1->CMT_PHASERA_DTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERA_DTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_A_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLK" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_A_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_A_RDCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_RDCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_A_RDEN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_A_RDEN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_RDENABLE" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B10_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS0" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DTSBUS1" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B18_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLK->CMT_PHASER_OUT_B_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLK" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLKDELAYED->CMT_PHASER_OUT_B_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDELAYED" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OCLKDIV->CMT_PHASER_OUT_B_RDCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_RDCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OCLKDIV" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_OSERDESRST" }, "CMT_TOP_R_LOWER_T.CMT_PHASER_OUT_DB_RDENABLE->CMT_PHASER_OUT_B_RDEN_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_B_RDEN_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_RDENABLE" }, "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_1->CMT_PHASER_OUT_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_2->CMT_PHASER_IN_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_2" }, "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_5" }, "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_6->CMT_PHASER_IN_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_CLK0_8->>CMT_BOT_HCLKMUX_CLKINT_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK0_8" }, "CMT_TOP_R_LOWER_T.CMT_TOP_CLK1_8->>CMT_BOT_HCLKMUX_CLKINT_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_BOT_HCLKMUX_CLKINT_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK1_8" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_2" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_5" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX0_7->CMT_PHASER_IN_DB_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_7" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX11_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX12_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX12_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX12_4->CMT_PHASER_IN_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX12_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_5->CMT_PHASER_OUT_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_5" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX13_6->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_5->CMT_PHASER_OUT_DB_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_5" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_7" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_7" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_2" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_7" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX1_2" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX20_4->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX21_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX21_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_4->CMT_PHASER_OUT_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX23_6->CMT_PHASER_IN_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX25_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX25_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX25_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX25_5" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_2" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX27_4->CMT_PHASER_IN_CA_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX28_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX28_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_5->CMT_PHASER_OUT_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_5" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX29_6->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX2_2" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_5->CMT_PHASER_OUT_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_5" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX31_7->CMT_PHASER_IN_DB_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_7" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX32_2->CMT_PHASER_OUT_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX32_2" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX39_4->CMT_PHASER_OUT_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX39_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_2" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX43_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX43_4->CMT_PHASER_IN_CA_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_6->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_7" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_5->CMT_PHASER_OUT_DB_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_5" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX46_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_4" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_1" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_5->CMT_PHASER_OUT_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_5" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_6->CMT_PHASER_IN_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_6" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX47_7->CMT_PHASER_IN_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_7" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX8_3->CMT_PHASER_IN_CA_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX8_3" }, "CMT_TOP_R_LOWER_T.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_2" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN0->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN1->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN2->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFIN3->>MMCMOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.160", + "0.180", + "0.351", + "0.392" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT0->>MMCM_CLK_FREQBB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT0" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT1->>MMCM_CLK_FREQBB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT1" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT2->>MMCM_CLK_FREQBB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT2" }, "CMT_TOP_R_LOWER_T.MMCMOUT_CLK_FREQ_BB_REBUFOUT3->>MMCM_CLK_FREQBB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "MMCM_CLK_FREQBB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "MMCMOUT_CLK_FREQ_BB_REBUFOUT3" } }, @@ -1966,83 +6086,776 @@ "name": "X0Y0", "prefix": "PHASER_OUT_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "RST": "CMT_PHASER_OUT_CA_RST", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" + }, + "COARSEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEENABLE" + }, + "COARSEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "COARSEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "COUNTERLOADVAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "COUNTERLOADVAL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1" + }, + "COUNTERLOADVAL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2" + }, + "COUNTERLOADVAL3": { + "cap": "0.000", + "delay": [ + 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"CMT_PHASER_OUT_CA_COUNTERREADEN" + }, + "COUNTERREADVAL0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" + }, + "COUNTERREADVAL1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" + }, + "COUNTERREADVAL2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" + }, + "COUNTERREADVAL3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" + }, + "COUNTERREADVAL4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" + }, + "COUNTERREADVAL5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" + }, + "COUNTERREADVAL6": { + "delay": [ + "0.000", + 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+ "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_DQSBUS1" + }, + "DTSBUS0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_DTSBUS0" + }, + "DTSBUS1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_DTSBUS1" + }, + "EDGEADV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_EDGEADV" + }, + "ENCALIB0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIB0" + }, + "ENCALIB1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIB1" + }, + "ENCALIBPHY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIBPHY0" + }, + "ENCALIBPHY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_ENCALIBPHY1" + }, + "FINEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_FINEENABLE" + }, + "FINEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_FINEINC" + }, + "FINEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" + }, + "FREQREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_FREQREFCLK" + }, + "MEMREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_MEMREFCLK" + }, + "OCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OCLK" + }, + "OCLKDELAYED": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" + }, + "OCLKDIV": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OCLKDIV" + }, + "OSERDESRST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_OSERDESRST" + }, + "PHASEREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_PHASEREFCLK" + }, + "RDENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_RDENABLE" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_RST" + }, + "SCANCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANCLK" + }, + "SCANENB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANENB" + }, + "SCANIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANIN" + }, + "SCANMODEB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SCANMODEB" + }, + "SCANOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_SCANOUT" + }, + "SELFINEOCLKDELAY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY" + }, + "SYNCIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SYNCIN" + }, + "SYSCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_SYSCLK" + }, + "TESTIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN0" + }, + "TESTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN1" + }, + "TESTIN10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN10" + }, + "TESTIN11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN11" + }, + "TESTIN12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN12" + }, + "TESTIN13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN13" + }, + "TESTIN14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN14" + }, + "TESTIN15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN15" + }, + "TESTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN2" + }, + "TESTIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN3" + }, + "TESTIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN4" + }, + "TESTIN5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN5" + }, + "TESTIN6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN6" + }, + "TESTIN7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN7" + }, + "TESTIN8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN8" + }, + "TESTIN9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_TESTIN9" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_TESTOUT3" + } }, "type": "PHASER_OUT_PHY", "x_coord": 0, @@ -2052,98 +6865,926 @@ "name": "X0Y0", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_CA_ICLK", - "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_CA_RCLK", - "RST": "CMT_PHASER_IN_CA_RST", - "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", - "SCANENB": "CMT_PHASER_IN_CA_SCANENB", - "SCANIN": "CMT_PHASER_IN_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_CA_STG1READ", - "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", - "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", - "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", - "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", - "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", - "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", - "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", - "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", - "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", - "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", - "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", - "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", - "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", - "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", - "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", - "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", - "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", - "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", - "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", - "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", - "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", - "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", - "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", - "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", - "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", - "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", - "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", - "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", - "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", - "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", - "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", - "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", - "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", - "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", - "WRENABLE": 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"type": "PHASER_IN_PHY", "x_coord": 0, @@ -2153,83 +7794,776 @@ "name": "X0Y1", "prefix": "PHASER_OUT_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_OUT_DB_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "COARSEENABLE": "CMT_PHASER_OUT_DB_COARSEENABLE", - "COARSEINC": "CMT_PHASER_OUT_DB_COARSEINC", - "COARSEOVERFLOW": "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "COUNTERLOADEN": "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "COUNTERREADEN": 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"ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_DB_OCLK", - "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", - "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", - "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", - "RST": "CMT_PHASER_OUT_DB_RST", - "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", - "SCANENB": "CMT_PHASER_OUT_DB_SCANENB", - "SCANIN": "CMT_PHASER_OUT_DB_SCANIN", - "SCANMODEB": "CMT_PHASER_OUT_DB_SCANMODEB", - "SCANOUT": "CMT_PHASER_OUT_DB_SCANOUT", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "SYNCIN": "CMT_PHASER_OUT_DB_SYNCIN", - "SYSCLK": "CMT_PHASER_OUT_DB_SYSCLK", - "TESTIN0": "CMT_PHASER_OUT_DB_TESTIN0", - "TESTIN1": "CMT_PHASER_OUT_DB_TESTIN1", - "TESTIN10": "CMT_PHASER_OUT_DB_TESTIN10", - "TESTIN11": "CMT_PHASER_OUT_DB_TESTIN11", - "TESTIN12": "CMT_PHASER_OUT_DB_TESTIN12", - "TESTIN13": "CMT_PHASER_OUT_DB_TESTIN13", - "TESTIN14": "CMT_PHASER_OUT_DB_TESTIN14", - "TESTIN15": "CMT_PHASER_OUT_DB_TESTIN15", - "TESTIN2": "CMT_PHASER_OUT_DB_TESTIN2", - "TESTIN3": "CMT_PHASER_OUT_DB_TESTIN3", - "TESTIN4": "CMT_PHASER_OUT_DB_TESTIN4", - "TESTIN5": "CMT_PHASER_OUT_DB_TESTIN5", - "TESTIN6": "CMT_PHASER_OUT_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_DB_TESTIN7", - "TESTIN8": "CMT_PHASER_OUT_DB_TESTIN8", - "TESTIN9": "CMT_PHASER_OUT_DB_TESTIN9", - "TESTOUT0": "CMT_PHASER_OUT_DB_TESTOUT0", - "TESTOUT1": "CMT_PHASER_OUT_DB_TESTOUT1", - "TESTOUT2": "CMT_PHASER_OUT_DB_TESTOUT2", - "TESTOUT3": "CMT_PHASER_OUT_DB_TESTOUT3" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_BURSTPENDING" + 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"BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_DB_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_DB_ICLK", - "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_DB_RCLK", - "RST": "CMT_PHASER_IN_DB_RST", - "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", - "SCANENB": "CMT_PHASER_IN_DB_SCANENB", - "SCANIN": "CMT_PHASER_IN_DB_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_DB_STG1READ", - "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", - "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", - "STG1REGL2": "CMT_PHASER_IN_DB_STG1REGL2", - "STG1REGL3": "CMT_PHASER_IN_DB_STG1REGL3", - "STG1REGL4": "CMT_PHASER_IN_DB_STG1REGL4", - "STG1REGL5": "CMT_PHASER_IN_DB_STG1REGL5", - "STG1REGL6": "CMT_PHASER_IN_DB_STG1REGL6", - "STG1REGL7": "CMT_PHASER_IN_DB_STG1REGL7", - "STG1REGL8": "CMT_PHASER_IN_DB_STG1REGL8", - "STG1REGR0": "CMT_PHASER_IN_DB_STG1REGR0", - "STG1REGR1": "CMT_PHASER_IN_DB_STG1REGR1", - "STG1REGR2": "CMT_PHASER_IN_DB_STG1REGR2", - "STG1REGR3": "CMT_PHASER_IN_DB_STG1REGR3", - "STG1REGR4": "CMT_PHASER_IN_DB_STG1REGR4", - "STG1REGR5": "CMT_PHASER_IN_DB_STG1REGR5", - "STG1REGR6": "CMT_PHASER_IN_DB_STG1REGR6", - "STG1REGR7": "CMT_PHASER_IN_DB_STG1REGR7", - "STG1REGR8": "CMT_PHASER_IN_DB_STG1REGR8", - "SYNCIN": "CMT_PHASER_IN_DB_SYNCIN", - "SYSCLK": "CMT_PHASER_IN_DB_SYSCLK", - "TESTIN0": "CMT_PHASER_IN_DB_TESTIN0", - "TESTIN1": "CMT_PHASER_IN_DB_TESTIN1", - "TESTIN10": "CMT_PHASER_IN_DB_TESTIN10", - "TESTIN11": "CMT_PHASER_IN_DB_TESTIN11", - "TESTIN12": "CMT_PHASER_IN_DB_TESTIN12", - "TESTIN13": "CMT_PHASER_IN_DB_TESTIN13", - "TESTIN2": "CMT_PHASER_IN_DB_TESTIN2", - "TESTIN3": "CMT_PHASER_IN_DB_TESTIN3", - "TESTIN4": "CMT_PHASER_IN_DB_TESTIN4", - "TESTIN5": "CMT_PHASER_IN_DB_TESTIN5", - "TESTIN6": "CMT_PHASER_IN_DB_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_DB_TESTIN7", - "TESTIN8": "CMT_PHASER_IN_DB_TESTIN8", - "TESTIN9": "CMT_PHASER_IN_DB_TESTIN9", - "TESTOUT0": "CMT_PHASER_IN_DB_TESTOUT0", - "TESTOUT1": "CMT_PHASER_IN_DB_TESTOUT1", - "TESTOUT2": "CMT_PHASER_IN_DB_TESTOUT2", - "TESTOUT3": "CMT_PHASER_IN_DB_TESTOUT3", - "WRENABLE": "CMT_PHASER_IN_DB_WRENABLE" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_BURSTPENDINGPHY" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_COUNTERLOADEN" + }, + "COUNTERLOADVAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0" + }, + "COUNTERLOADVAL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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"0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_RANKSELPHY1" + }, + "RCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_RCLK" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_RST" + }, + "RSTDQSFIND": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_RSTDQSFIND" + }, + "SCANCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_SCANCLK" + }, + "SCANENB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_SCANENB" + }, + "SCANIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_SCANIN" + }, + "SCANMODEB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_SCANMODEB" + }, + "SCANOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_SCANOUT" + }, + "SELCALORSTG1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_SELCALORSTG1" + }, + "STG1INCDEC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1INCDEC" + }, + "STG1LOAD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1LOAD" + }, + "STG1OVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1OVERFLOW" + }, + "STG1READ": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1READ" + }, + "STG1REGL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1REGL0" + }, + "STG1REGL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1REGL1" + }, + "STG1REGL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1REGL2" + }, + "STG1REGL3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1REGL3" + }, + "STG1REGL4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1REGL4" + }, + "STG1REGL5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1REGL5" + }, + "STG1REGL6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_STG1REGL6" + }, + "STG1REGL7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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}, + "STG1REGR6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR6" + }, + "STG1REGR7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR7" + }, + "STG1REGR8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_STG1REGR8" + }, + "SYNCIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_SYNCIN" + }, + "SYSCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_SYSCLK" + }, + "TESTIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN0" + }, + "TESTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN1" + }, + "TESTIN10": { + "cap": "0.000", + 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"0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN5" + }, + "TESTIN6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN6" + }, + "TESTIN7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN7" + }, + "TESTIN8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN8" + }, + "TESTIN9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN9" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT3" + }, + "WRENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_WRENABLE" + } }, "type": "PHASER_IN_PHY", "x_coord": 0, @@ -2338,2486 +9500,7130 @@ } ], "tile_type": "CMT_TOP_R_LOWER_T", - "wires": [ - "CMT_BOT_HCLKMUX_CLKINT_0", - "CMT_BOT_HCLKMUX_CLKINT_1", - "CMT_LR_LOWER_T_CLK_IN1_HCLK", - "CMT_LR_LOWER_T_CLK_IN2_HCLK", - "CMT_LR_LOWER_T_CLK_IN3_HCLK", - "CMT_LR_LOWER_T_CLK_MMCM0", - "CMT_LR_LOWER_T_CLK_MMCM1", - "CMT_LR_LOWER_T_CLK_MMCM10", - "CMT_LR_LOWER_T_CLK_MMCM11", - "CMT_LR_LOWER_T_CLK_MMCM12", - "CMT_LR_LOWER_T_CLK_MMCM13", - "CMT_LR_LOWER_T_CLK_MMCM2", - "CMT_LR_LOWER_T_CLK_MMCM3", - "CMT_LR_LOWER_T_CLK_MMCM4", - "CMT_LR_LOWER_T_CLK_MMCM5", - "CMT_LR_LOWER_T_CLK_MMCM6", - "CMT_LR_LOWER_T_CLK_MMCM7", - "CMT_LR_LOWER_T_CLK_MMCM8", - "CMT_LR_LOWER_T_CLK_MMCM9", - "CMT_LR_LOWER_T_CLK_PERF0", - "CMT_LR_LOWER_T_CLK_PERF1", - "CMT_LR_LOWER_T_CLK_PERF2", - "CMT_LR_LOWER_T_CLK_PERF3", - "CMT_PHASERA_CTSBUS0", - "CMT_PHASERA_CTSBUS1", - "CMT_PHASERA_DQSBUS0", - "CMT_PHASERA_DQSBUS1", - "CMT_PHASERA_DTSBUS0", - "CMT_PHASERA_DTSBUS1", - "CMT_PHASERREF_DOWN_PHASERIN_A", - "CMT_PHASERREF_DOWN_PHASERIN_B", - "CMT_PHASERREF_DOWN_PHASEROUT_A", - "CMT_PHASERREF_DOWN_PHASEROUT_B", - "CMT_PHASER_BOT_ENCALIB0", - "CMT_PHASER_BOT_ENCALIB1", - "CMT_PHASER_BOT_IBURSTPENDING0", - "CMT_PHASER_BOT_IBURSTPENDING1", - "CMT_PHASER_BOT_IRANKA0", - "CMT_PHASER_BOT_IRANKA1", - "CMT_PHASER_BOT_IRANKB0", - "CMT_PHASER_BOT_IRANKB1", - "CMT_PHASER_BOT_OBURSTPENDING0", - "CMT_PHASER_BOT_OBURSTPENDING1", - "CMT_PHASER_BOT_REFMUX_0", - "CMT_PHASER_BOT_REFMUX_1", - "CMT_PHASER_BOT_REFMUX_2", - "CMT_PHASER_BOT_SYNC_BB", - "CMT_PHASER_B_ICLKDIV_TOIOI", - "CMT_PHASER_B_ICLK_TOIOI", - "CMT_PHASER_B_OCLK90_TOIOI", - "CMT_PHASER_B_OCLKDIV_TOIOI", - "CMT_PHASER_B_OCLK_TOIOI", - "CMT_PHASER_B_TOMMCM_ICLK", - "CMT_PHASER_B_TOMMCM_ICLKDIV", - "CMT_PHASER_B_TOMMCM_OCLK", - "CMT_PHASER_B_TOMMCM_OCLK1X_90", - "CMT_PHASER_B_TOMMCM_OCLKDIV", - "CMT_PHASER_DOWN_DQS_TO_PHASER_A", - "CMT_PHASER_DOWN_DQS_TO_PHASER_B", - "CMT_PHASER_DOWN_PHASERREF0", - "CMT_PHASER_DOWN_PHASERREF1", - "CMT_PHASER_DOWN_PHASERREF_ABOVE0", - "CMT_PHASER_DOWN_PHASERREF_ABOVE1", - "CMT_PHASER_DOWN_PHASERREF_BELOW0", - "CMT_PHASER_DOWN_PHASERREF_BELOW1", - "CMT_PHASER_IN_A_ICLK", - "CMT_PHASER_IN_A_ICLKDIV", - "CMT_PHASER_IN_A_RCLK0", - "CMT_PHASER_IN_A_WRCLK_TOFIFO", - "CMT_PHASER_IN_A_WREN_TOFIFO", - "CMT_PHASER_IN_B_ICLK", - "CMT_PHASER_IN_B_ICLKDIV", - "CMT_PHASER_IN_B_RCLK1", - "CMT_PHASER_IN_B_WRCLK_TOFIFO", - "CMT_PHASER_IN_B_WREN_TOFIFO", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_CA_ICLK", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_PHASER_IN_CA_RCLK", - "CMT_PHASER_IN_CA_RST", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_PHASER_IN_DB_ICLK", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_PHASER_IN_DB_RCLK", - "CMT_PHASER_IN_DB_RST", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_PHASER_IN_DB_STG1REGR1", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_PHASER_IN_DB_TESTIN7", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_PHASER_IN_DB_TESTOUT1", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_PHASER_OUT_A_OCLK", - "CMT_PHASER_OUT_A_OCLK1X_90", - "CMT_PHASER_OUT_A_OCLKDIV", - "CMT_PHASER_OUT_A_RDCLK_TOFIFO", - "CMT_PHASER_OUT_A_RDEN_TOFIFO", - "CMT_PHASER_OUT_B_OCLK", - "CMT_PHASER_OUT_B_OCLK1X_90", - "CMT_PHASER_OUT_B_OCLKDIV", - "CMT_PHASER_OUT_B_RDCLK_TOFIFO", - "CMT_PHASER_OUT_B_RDEN_TOFIFO", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_PHASER_OUT_CA_RST", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_PHASER_OUT_CA_TESTIN4", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_DIVIDERST", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_PHASER_OUT_DB_RST", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_R_TOP_LOWER_B_CLKINT_0", - "CMT_R_TOP_LOWER_B_CLKINT_1", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX10_4", - "CMT_TOP_IMUX10_5", - "CMT_TOP_IMUX10_6", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_IMUX11_0", - "CMT_TOP_IMUX11_1", - "CMT_TOP_IMUX11_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX11_4", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_IMUX12_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX12_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX12_6", - "CMT_TOP_IMUX12_7", - "CMT_TOP_IMUX12_8", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX13_3", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX13_8", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX14_3", - "CMT_TOP_IMUX14_4", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_IMUX15_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX15_4", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_IMUX16_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX16_5", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX16_7", - "CMT_TOP_IMUX16_8", - "CMT_TOP_IMUX17_0", - "CMT_TOP_IMUX17_1", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX17_3", - "CMT_TOP_IMUX17_4", - "CMT_TOP_IMUX17_5", - "CMT_TOP_IMUX17_6", - "CMT_TOP_IMUX17_7", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX18_0", - "CMT_TOP_IMUX18_1", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX18_3", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX18_5", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX18_7", - "CMT_TOP_IMUX18_8", - "CMT_TOP_IMUX19_0", - "CMT_TOP_IMUX19_1", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX19_3", - "CMT_TOP_IMUX19_4", - "CMT_TOP_IMUX19_5", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX19_7", - "CMT_TOP_IMUX19_8", - "CMT_TOP_IMUX1_0", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX1_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_IMUX1_8", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX20_2", - "CMT_TOP_IMUX20_3", - "CMT_TOP_IMUX20_4", - "CMT_TOP_IMUX20_5", - "CMT_TOP_IMUX20_6", - "CMT_TOP_IMUX20_7", - "CMT_TOP_IMUX20_8", - "CMT_TOP_IMUX21_0", - "CMT_TOP_IMUX21_1", - "CMT_TOP_IMUX21_2", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_IMUX21_7", - "CMT_TOP_IMUX21_8", - "CMT_TOP_IMUX22_0", - "CMT_TOP_IMUX22_1", - "CMT_TOP_IMUX22_2", - "CMT_TOP_IMUX22_3", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX22_7", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX23_0", - "CMT_TOP_IMUX23_1", - "CMT_TOP_IMUX23_2", - "CMT_TOP_IMUX23_3", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX23_7", - "CMT_TOP_IMUX23_8", - "CMT_TOP_IMUX24_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_IMUX24_4", - "CMT_TOP_IMUX24_5", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX24_8", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX25_1", - "CMT_TOP_IMUX25_2", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX25_6", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX25_8", - "CMT_TOP_IMUX26_0", - "CMT_TOP_IMUX26_1", - "CMT_TOP_IMUX26_2", - "CMT_TOP_IMUX26_3", - "CMT_TOP_IMUX26_4", - "CMT_TOP_IMUX26_5", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX26_7", - "CMT_TOP_IMUX26_8", - "CMT_TOP_IMUX27_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX27_2", - "CMT_TOP_IMUX27_3", - "CMT_TOP_IMUX27_4", - "CMT_TOP_IMUX27_5", - "CMT_TOP_IMUX27_6", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX27_8", - "CMT_TOP_IMUX28_0", - "CMT_TOP_IMUX28_1", - "CMT_TOP_IMUX28_2", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX28_5", - "CMT_TOP_IMUX28_6", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX28_8", - "CMT_TOP_IMUX29_0", - "CMT_TOP_IMUX29_1", - "CMT_TOP_IMUX29_2", - "CMT_TOP_IMUX29_3", - "CMT_TOP_IMUX29_4", - "CMT_TOP_IMUX29_5", - "CMT_TOP_IMUX29_6", - "CMT_TOP_IMUX29_7", - "CMT_TOP_IMUX29_8", - "CMT_TOP_IMUX2_0", - "CMT_TOP_IMUX2_1", - "CMT_TOP_IMUX2_2", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX2_4", - "CMT_TOP_IMUX2_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_IMUX2_7", - "CMT_TOP_IMUX2_8", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX30_1", - "CMT_TOP_IMUX30_2", - "CMT_TOP_IMUX30_3", - "CMT_TOP_IMUX30_4", - "CMT_TOP_IMUX30_5", - "CMT_TOP_IMUX30_6", - "CMT_TOP_IMUX30_7", - "CMT_TOP_IMUX30_8", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX31_2", - "CMT_TOP_IMUX31_3", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX31_5", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX31_8", - "CMT_TOP_IMUX32_0", - "CMT_TOP_IMUX32_1", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX32_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_IMUX32_5", - "CMT_TOP_IMUX32_6", - "CMT_TOP_IMUX32_7", - "CMT_TOP_IMUX32_8", - "CMT_TOP_IMUX33_0", - "CMT_TOP_IMUX33_1", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX33_4", - "CMT_TOP_IMUX33_5", - "CMT_TOP_IMUX33_6", - "CMT_TOP_IMUX33_7", - "CMT_TOP_IMUX33_8", - "CMT_TOP_IMUX34_0", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX34_4", - "CMT_TOP_IMUX34_5", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX34_7", - "CMT_TOP_IMUX34_8", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX35_1", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX35_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_IMUX35_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_IMUX35_7", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX36_0", - "CMT_TOP_IMUX36_1", - "CMT_TOP_IMUX36_2", - "CMT_TOP_IMUX36_3", - "CMT_TOP_IMUX36_4", - "CMT_TOP_IMUX36_5", - "CMT_TOP_IMUX36_6", - "CMT_TOP_IMUX36_7", - "CMT_TOP_IMUX36_8", - "CMT_TOP_IMUX37_0", - "CMT_TOP_IMUX37_1", - "CMT_TOP_IMUX37_2", - "CMT_TOP_IMUX37_3", - "CMT_TOP_IMUX37_4", - "CMT_TOP_IMUX37_5", - "CMT_TOP_IMUX37_6", - "CMT_TOP_IMUX37_7", - "CMT_TOP_IMUX37_8", - "CMT_TOP_IMUX38_0", - "CMT_TOP_IMUX38_1", - "CMT_TOP_IMUX38_2", - "CMT_TOP_IMUX38_3", - "CMT_TOP_IMUX38_4", - "CMT_TOP_IMUX38_5", - "CMT_TOP_IMUX38_6", - "CMT_TOP_IMUX38_7", - "CMT_TOP_IMUX38_8", - "CMT_TOP_IMUX39_0", - "CMT_TOP_IMUX39_1", - "CMT_TOP_IMUX39_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_IMUX39_5", - "CMT_TOP_IMUX39_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX39_8", - "CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "MMCMOUT_CLK_FREQ_BB_REBUFIN0", - "MMCMOUT_CLK_FREQ_BB_REBUFIN1", - "MMCMOUT_CLK_FREQ_BB_REBUFIN2", - "MMCMOUT_CLK_FREQ_BB_REBUFIN3", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT0", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT1", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT2", - "MMCMOUT_CLK_FREQ_BB_REBUFOUT3", - "MMCM_CLK_FREQBB_REBUFOUT0", - "MMCM_CLK_FREQBB_REBUFOUT1", - "MMCM_CLK_FREQBB_REBUFOUT2", - "MMCM_CLK_FREQBB_REBUFOUT3" - ] + "wires": { + "CMT_BOT_HCLKMUX_CLKINT_0": null, + "CMT_BOT_HCLKMUX_CLKINT_1": null, + "CMT_LR_LOWER_T_CLK_IN1_HCLK": null, + "CMT_LR_LOWER_T_CLK_IN2_HCLK": null, + "CMT_LR_LOWER_T_CLK_IN3_HCLK": null, + "CMT_LR_LOWER_T_CLK_MMCM0": null, + "CMT_LR_LOWER_T_CLK_MMCM1": null, + "CMT_LR_LOWER_T_CLK_MMCM10": null, + "CMT_LR_LOWER_T_CLK_MMCM11": null, + "CMT_LR_LOWER_T_CLK_MMCM12": null, + "CMT_LR_LOWER_T_CLK_MMCM13": null, + "CMT_LR_LOWER_T_CLK_MMCM2": null, + "CMT_LR_LOWER_T_CLK_MMCM3": null, + "CMT_LR_LOWER_T_CLK_MMCM4": null, + "CMT_LR_LOWER_T_CLK_MMCM5": null, + "CMT_LR_LOWER_T_CLK_MMCM6": null, + "CMT_LR_LOWER_T_CLK_MMCM7": null, + "CMT_LR_LOWER_T_CLK_MMCM8": null, + "CMT_LR_LOWER_T_CLK_MMCM9": null, + "CMT_LR_LOWER_T_CLK_PERF0": null, + "CMT_LR_LOWER_T_CLK_PERF1": null, + "CMT_LR_LOWER_T_CLK_PERF2": null, + "CMT_LR_LOWER_T_CLK_PERF3": null, + "CMT_PHASERA_CTSBUS0": null, + "CMT_PHASERA_CTSBUS1": null, + "CMT_PHASERA_DQSBUS0": null, + "CMT_PHASERA_DQSBUS1": null, + "CMT_PHASERA_DTSBUS0": null, + "CMT_PHASERA_DTSBUS1": null, + "CMT_PHASERREF_DOWN_PHASERIN_A": null, + "CMT_PHASERREF_DOWN_PHASERIN_B": null, + "CMT_PHASERREF_DOWN_PHASEROUT_A": null, + "CMT_PHASERREF_DOWN_PHASEROUT_B": null, + "CMT_PHASER_BOT_ENCALIB0": null, + "CMT_PHASER_BOT_ENCALIB1": null, + "CMT_PHASER_BOT_IBURSTPENDING0": null, + "CMT_PHASER_BOT_IBURSTPENDING1": null, + "CMT_PHASER_BOT_IRANKA0": null, + "CMT_PHASER_BOT_IRANKA1": null, + "CMT_PHASER_BOT_IRANKB0": null, + "CMT_PHASER_BOT_IRANKB1": null, + "CMT_PHASER_BOT_OBURSTPENDING0": null, + "CMT_PHASER_BOT_OBURSTPENDING1": null, + "CMT_PHASER_BOT_REFMUX_0": null, + "CMT_PHASER_BOT_REFMUX_1": null, + "CMT_PHASER_BOT_REFMUX_2": null, + "CMT_PHASER_BOT_SYNC_BB": null, + "CMT_PHASER_B_ICLKDIV_TOIOI": null, + "CMT_PHASER_B_ICLK_TOIOI": null, + "CMT_PHASER_B_OCLK90_TOIOI": null, + "CMT_PHASER_B_OCLKDIV_TOIOI": null, + "CMT_PHASER_B_OCLK_TOIOI": null, + "CMT_PHASER_B_TOMMCM_ICLK": null, + "CMT_PHASER_B_TOMMCM_ICLKDIV": null, + "CMT_PHASER_B_TOMMCM_OCLK": null, + "CMT_PHASER_B_TOMMCM_OCLK1X_90": null, + "CMT_PHASER_B_TOMMCM_OCLKDIV": null, + "CMT_PHASER_DOWN_DQS_TO_PHASER_A": null, + "CMT_PHASER_DOWN_DQS_TO_PHASER_B": null, + "CMT_PHASER_DOWN_PHASERREF0": null, + "CMT_PHASER_DOWN_PHASERREF1": null, + "CMT_PHASER_DOWN_PHASERREF_ABOVE0": null, + "CMT_PHASER_DOWN_PHASERREF_ABOVE1": null, + "CMT_PHASER_DOWN_PHASERREF_BELOW0": null, + "CMT_PHASER_DOWN_PHASERREF_BELOW1": null, + "CMT_PHASER_IN_A_ICLK": null, + "CMT_PHASER_IN_A_ICLKDIV": null, + "CMT_PHASER_IN_A_RCLK0": null, + "CMT_PHASER_IN_A_WRCLK_TOFIFO": null, + "CMT_PHASER_IN_A_WREN_TOFIFO": null, + "CMT_PHASER_IN_B_ICLK": null, + "CMT_PHASER_IN_B_ICLKDIV": null, + "CMT_PHASER_IN_B_RCLK1": null, + "CMT_PHASER_IN_B_WRCLK_TOFIFO": null, + "CMT_PHASER_IN_B_WREN_TOFIFO": null, + "CMT_PHASER_IN_CA_BURSTPENDING": null, + "CMT_PHASER_IN_CA_BURSTPENDINGPHY": null, + "CMT_PHASER_IN_CA_COUNTERLOADEN": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL0": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL1": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL2": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL3": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL4": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL5": null, + "CMT_PHASER_IN_CA_COUNTERREADEN": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL0": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL1": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL2": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL3": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL4": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL5": null, + "CMT_PHASER_IN_CA_DIVIDERST": null, + "CMT_PHASER_IN_CA_DQSFOUND": null, + "CMT_PHASER_IN_CA_DQSOUTOFRANGE": null, + "CMT_PHASER_IN_CA_EDGEADV": null, + "CMT_PHASER_IN_CA_ENCALIB0": null, + "CMT_PHASER_IN_CA_ENCALIB1": null, + "CMT_PHASER_IN_CA_ENCALIBPHY0": null, + "CMT_PHASER_IN_CA_ENCALIBPHY1": null, + "CMT_PHASER_IN_CA_ENSTG1": null, + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB": null, + "CMT_PHASER_IN_CA_FINEENABLE": null, + "CMT_PHASER_IN_CA_FINEINC": null, + "CMT_PHASER_IN_CA_FINEOVERFLOW": null, + "CMT_PHASER_IN_CA_FREQREFCLK": null, + "CMT_PHASER_IN_CA_ICLK": null, + "CMT_PHASER_IN_CA_ICLKDIV": null, + "CMT_PHASER_IN_CA_ISERDESRST": null, + "CMT_PHASER_IN_CA_MEMREFCLK": null, + "CMT_PHASER_IN_CA_PHASELOCKED": null, + "CMT_PHASER_IN_CA_PHASEREFCLK": null, + "CMT_PHASER_IN_CA_RANKSEL0": null, + "CMT_PHASER_IN_CA_RANKSEL1": null, + "CMT_PHASER_IN_CA_RANKSELPHY0": null, + "CMT_PHASER_IN_CA_RANKSELPHY1": null, + "CMT_PHASER_IN_CA_RCLK": null, + "CMT_PHASER_IN_CA_RST": null, + "CMT_PHASER_IN_CA_RSTDQSFIND": null, + "CMT_PHASER_IN_CA_SCANCLK": null, + "CMT_PHASER_IN_CA_SCANENB": null, + "CMT_PHASER_IN_CA_SCANIN": null, + "CMT_PHASER_IN_CA_SCANMODEB": null, + "CMT_PHASER_IN_CA_SCANOUT": null, + "CMT_PHASER_IN_CA_SELCALORSTG1": null, + "CMT_PHASER_IN_CA_STG1INCDEC": null, + "CMT_PHASER_IN_CA_STG1LOAD": null, + "CMT_PHASER_IN_CA_STG1OVERFLOW": null, + "CMT_PHASER_IN_CA_STG1READ": null, + "CMT_PHASER_IN_CA_STG1REGL0": null, + "CMT_PHASER_IN_CA_STG1REGL1": null, + "CMT_PHASER_IN_CA_STG1REGL2": null, + "CMT_PHASER_IN_CA_STG1REGL3": null, + "CMT_PHASER_IN_CA_STG1REGL4": null, + "CMT_PHASER_IN_CA_STG1REGL5": null, + "CMT_PHASER_IN_CA_STG1REGL6": null, + "CMT_PHASER_IN_CA_STG1REGL7": null, + "CMT_PHASER_IN_CA_STG1REGL8": null, + "CMT_PHASER_IN_CA_STG1REGR0": null, + "CMT_PHASER_IN_CA_STG1REGR1": null, + "CMT_PHASER_IN_CA_STG1REGR2": null, + "CMT_PHASER_IN_CA_STG1REGR3": null, + "CMT_PHASER_IN_CA_STG1REGR4": null, + "CMT_PHASER_IN_CA_STG1REGR5": null, + "CMT_PHASER_IN_CA_STG1REGR6": null, + "CMT_PHASER_IN_CA_STG1REGR7": null, + "CMT_PHASER_IN_CA_STG1REGR8": null, + "CMT_PHASER_IN_CA_SYNCIN": null, + "CMT_PHASER_IN_CA_SYSCLK": null, + "CMT_PHASER_IN_CA_TESTIN0": null, + "CMT_PHASER_IN_CA_TESTIN1": null, + "CMT_PHASER_IN_CA_TESTIN10": null, + "CMT_PHASER_IN_CA_TESTIN11": null, + "CMT_PHASER_IN_CA_TESTIN12": null, + "CMT_PHASER_IN_CA_TESTIN13": null, + "CMT_PHASER_IN_CA_TESTIN2": null, + "CMT_PHASER_IN_CA_TESTIN3": null, + "CMT_PHASER_IN_CA_TESTIN4": null, + "CMT_PHASER_IN_CA_TESTIN5": null, + "CMT_PHASER_IN_CA_TESTIN6": null, + "CMT_PHASER_IN_CA_TESTIN7": null, + "CMT_PHASER_IN_CA_TESTIN8": null, + "CMT_PHASER_IN_CA_TESTIN9": null, + "CMT_PHASER_IN_CA_TESTOUT0": null, + "CMT_PHASER_IN_CA_TESTOUT1": null, + "CMT_PHASER_IN_CA_TESTOUT2": null, + "CMT_PHASER_IN_CA_TESTOUT3": null, + "CMT_PHASER_IN_CA_WRENABLE": null, + "CMT_PHASER_IN_DB_BURSTPENDING": null, + "CMT_PHASER_IN_DB_BURSTPENDINGPHY": null, + "CMT_PHASER_IN_DB_COUNTERLOADEN": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL0": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL1": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL2": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL3": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL4": null, + "CMT_PHASER_IN_DB_COUNTERLOADVAL5": null, + "CMT_PHASER_IN_DB_COUNTERREADEN": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL0": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL1": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL2": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL3": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL4": null, + "CMT_PHASER_IN_DB_COUNTERREADVAL5": null, + "CMT_PHASER_IN_DB_DIVIDERST": null, + "CMT_PHASER_IN_DB_DQSFOUND": null, + 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"CMT_PHASER_IN_DB_SCANENB": null, + "CMT_PHASER_IN_DB_SCANIN": null, + "CMT_PHASER_IN_DB_SCANMODEB": null, + "CMT_PHASER_IN_DB_SCANOUT": null, + "CMT_PHASER_IN_DB_SELCALORSTG1": null, + "CMT_PHASER_IN_DB_STG1INCDEC": null, + "CMT_PHASER_IN_DB_STG1LOAD": null, + "CMT_PHASER_IN_DB_STG1OVERFLOW": null, + "CMT_PHASER_IN_DB_STG1READ": null, + "CMT_PHASER_IN_DB_STG1REGL0": null, + "CMT_PHASER_IN_DB_STG1REGL1": null, + "CMT_PHASER_IN_DB_STG1REGL2": null, + "CMT_PHASER_IN_DB_STG1REGL3": null, + "CMT_PHASER_IN_DB_STG1REGL4": null, + "CMT_PHASER_IN_DB_STG1REGL5": null, + "CMT_PHASER_IN_DB_STG1REGL6": null, + "CMT_PHASER_IN_DB_STG1REGL7": null, + "CMT_PHASER_IN_DB_STG1REGL8": null, + "CMT_PHASER_IN_DB_STG1REGR0": null, + "CMT_PHASER_IN_DB_STG1REGR1": null, + "CMT_PHASER_IN_DB_STG1REGR2": null, + "CMT_PHASER_IN_DB_STG1REGR3": null, + "CMT_PHASER_IN_DB_STG1REGR4": null, + "CMT_PHASER_IN_DB_STG1REGR5": null, + "CMT_PHASER_IN_DB_STG1REGR6": null, + "CMT_PHASER_IN_DB_STG1REGR7": null, + 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"cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_6": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_7": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_8": { + "cap": "78.000", + "res": "317.510" + }, + "MMCMOUT_CLK_FREQ_BB_REBUFIN0": null, + "MMCMOUT_CLK_FREQ_BB_REBUFIN1": null, + "MMCMOUT_CLK_FREQ_BB_REBUFIN2": null, + "MMCMOUT_CLK_FREQ_BB_REBUFIN3": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT0": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT1": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT2": null, + "MMCMOUT_CLK_FREQ_BB_REBUFOUT3": null, + "MMCM_CLK_FREQBB_REBUFOUT0": null, + "MMCM_CLK_FREQBB_REBUFOUT1": null, + "MMCM_CLK_FREQBB_REBUFOUT2": null, + "MMCM_CLK_FREQBB_REBUFOUT3": null + } } diff --git a/kintex7/tile_type_CMT_TOP_R_UPPER_B.json b/kintex7/tile_type_CMT_TOP_R_UPPER_B.json index 664df55..6e9a84f 100644 --- a/kintex7/tile_type_CMT_TOP_R_UPPER_B.json +++ b/kintex7/tile_type_CMT_TOP_R_UPPER_B.json @@ -2,2711 +2,8368 @@ "pips": { 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null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_FINEOVERFLOW" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ICLK->CMT_PHASER_IN_C_ICLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_ICLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ICLK" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ICLKDIV->CMT_PHASER_IN_C_WRCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_WRCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ICLKDIV" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_ISERDESRST" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_PHASELOCKED" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_PHASEREFCLK->>CMT_PHASER_IN_CA_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_CA_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_CA_PHASEREFCLK" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_RCLK->CMT_PHASER_IN_C_RCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_RCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_RCLK" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_CA_WRENABLE->CMT_PHASER_IN_C_WRENABLE_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_WRENABLE_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_CA_WRENABLE" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLK->>CMT_PHASER_C_ICLK_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.043", + "0.073", + "0.082" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_ICLK_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.043", + "0.073", + "0.082" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_C_ICLK" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_ICLKDIV->>CMT_PHASER_C_ICLKDIV_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.041", + "0.046", + "0.075", + "0.085" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_ICLKDIV_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.041", + "0.046", + "0.075", + "0.085" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_C_ICLKDIV" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_C_WRCLK_TOFIFO->CMT_PHASER_IN_C_ICLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_C_ICLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_C_WRCLK_TOFIFO" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL1" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL2" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL3" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL4" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_COUNTERREADVAL5" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DQSFOUND->CMT_TOP_LOGIC_OUTS_L_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSFOUND" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_DQSOUTOFRANGE->CMT_TOP_LOGIC_OUTS_L_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_DQSOUTOFRANGE" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_FINEOVERFLOW" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ICLK->CMT_PHASER_IN_D_ICLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_ICLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLK" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ICLKDIV->CMT_PHASER_IN_D_WRCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_WRCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ICLKDIV" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_ISERDESRST->CMT_TOP_LOGIC_OUTS_L_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_ISERDESRST" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASELOCKED->CMT_TOP_LOGIC_OUTS_L_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_PHASELOCKED" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_PHASEREFCLK->>CMT_PHASER_IN_DB_RCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "CMT_PHASER_IN_DB_RCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.100", + "0.115", + "0.188", + "0.216" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "CMT_PHASER_IN_DB_PHASEREFCLK" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_RCLK->CMT_PHASER_IN_D_RCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_RCLK3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_RCLK" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_DB_WRENABLE->CMT_PHASER_IN_D_WRENABLE_FIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_WRENABLE_FIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_DB_WRENABLE" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_IN_D_WRCLK_TOFIFO->CMT_PHASER_IN_D_ICLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_D_ICLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_IN_D_WRCLK_TOFIFO" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL4" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL5" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL6" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL7" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL8" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_CTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_CTSBUS1" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS0->CMT_TOP_LOGIC_OUTS_L_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DQSBUS1->CMT_TOP_LOGIC_OUTS_L_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DQSBUS1" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS0->CMT_TOP_LOGIC_OUTS_L_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_DTSBUS1->CMT_TOP_LOGIC_OUTS_L_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_DTSBUS1" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_FINEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_FINEOVERFLOW" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLK->CMT_PHASER_OUT_C_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLK" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLKDELAYED->CMT_PHASER_OUT_C_OCLK1X_90": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_OCLK1X_90", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDELAYED" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OCLKDIV->CMT_PHASER_OUT_C_RDCLK_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_RDCLK_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OCLKDIV" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_OSERDESRST->CMT_TOP_LOGIC_OUTS_L_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_OSERDESRST" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_CA_RDENABLE->CMT_PHASER_OUT_C_RDENABLE_TOFIFO": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_RDENABLE_TOFIFO", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_CA_RDENABLE" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK->>CMT_PHASER_C_OCLK_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.043", + "0.069", + "0.078" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_OCLK_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.043", + "0.069", + "0.078" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_C_OCLK" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLK1X_90->>CMT_PHASER_C_OCLK90_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.040", + "0.045", + "0.073", + "0.082" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_OCLK90_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.040", + "0.045", + "0.073", + "0.082" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_C_OCLK1X_90" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_OCLKDIV->>CMT_PHASER_C_OCLKDIV_TOIOI": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.042", + "0.047", + "0.077", + "0.087" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_PHASER_C_OCLKDIV_TOIOI", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.042", + "0.047", + "0.077", + "0.087" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_PHASER_OUT_C_OCLKDIV" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_C_RDCLK_TOFIFO->CMT_PHASER_OUT_C_OCLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_C_OCLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_C_RDCLK_TOFIFO" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COARSEOVERFLOW->CMT_TOP_LOGIC_OUTS_L_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COARSEOVERFLOW" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL0->CMT_TOP_LOGIC_OUTS_L_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL1->CMT_TOP_LOGIC_OUTS_L_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL1" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL2->CMT_TOP_LOGIC_OUTS_L_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL2" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL3->CMT_TOP_LOGIC_OUTS_L_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL3" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL4->CMT_TOP_LOGIC_OUTS_L_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL4" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL5->CMT_TOP_LOGIC_OUTS_L_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL5" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL6->CMT_TOP_LOGIC_OUTS_L_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL6" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL7->CMT_TOP_LOGIC_OUTS_L_B21_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL7" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_COUNTERREADVAL8->CMT_TOP_LOGIC_OUTS_L_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_COUNTERREADVAL8" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS0->CMT_PHASERD_CTSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_CTSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_CTSBUS1->CMT_PHASERD_CTSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_CTSBUS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_CTSBUS1" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS0->CMT_PHASERD_DQSBUS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_DQSBUS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHASER_OUT_DB_DQSBUS0" }, "CMT_TOP_R_UPPER_B.CMT_PHASER_OUT_DB_DQSBUS1->CMT_PHASERD_DQSBUS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERD_DQSBUS1", "is_directional": "1", + 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"can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKA0" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKA1->CMT_PHY_CONTROL_IRANKA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKA1" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKB0->CMT_PHY_CONTROL_IRANKB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKB0" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKB1->CMT_PHY_CONTROL_IRANKB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKB1" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKC0->CMT_PHY_CONTROL_IRANKC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKC0" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKC1->CMT_PHY_CONTROL_IRANKC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKC1" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKD0->CMT_PHY_CONTROL_IRANKD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKD0" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_INRANKD1->CMT_PHY_CONTROL_IRANKD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_IRANKD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_INRANKD1" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC0->CMT_PHASER_IN_CA_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKC0" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKC1->CMT_PHASER_IN_CA_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKC1" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD0->CMT_PHASER_IN_DB_RANKSELPHY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKD0" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_IRANKD1->CMT_PHASER_IN_DB_RANKSELPHY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSELPHY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_IRANKD1" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING2->CMT_PHASER_OUT_CA_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING2" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OBURSTPENDING3->CMT_PHASER_OUT_DB_BURSTPENDINGPHY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OBURSTPENDING3" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING0->CMT_PHY_CONTROL_OBURSTPENDING0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING1->CMT_PHY_CONTROL_OBURSTPENDING1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING2->CMT_PHY_CONTROL_OBURSTPENDING2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_OUTBURSTPENDING3->CMT_PHY_CONTROL_OBURSTPENDING3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_OBURSTPENDING3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB0->CMT_PHY_CONTROL_ECALIB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_ECALIB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB0" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PCENABLECALIB1->CMT_PHY_CONTROL_ECALIB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_ECALIB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PCENABLECALIB1" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLALMOSTFULL->CMT_TOP_LOGIC_OUTS_L_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLEMPTY->CMT_PHASERTOP_PHYCTLEMPTY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASERTOP_PHYCTLEMPTY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLEMPTY" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLFULL->CMT_TOP_LOGIC_OUTS_L_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLFULL" }, "CMT_TOP_R_UPPER_B.CMT_PHY_CONTROL_PHYCTLREADY->CMT_TOP_LOGIC_OUTS_L_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_PHY_CONTROL_PHYCTLREADY" }, "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_0->>CMT_R_TOP_UPPER_B_CLKINT_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_R_TOP_UPPER_B_CLKINT_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK0_0" }, "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_10->CMT_PHY_CONTROL_PHYCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_2->CMT_PHASER_OUT_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_4->CMT_PHASER_IN_CA_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_4" }, "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_5->CMT_PHASER_OUT_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_CLK0_8->CMT_PHASER_IN_DB_SYSCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_SYSCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_CLK0_8" }, "CMT_TOP_R_UPPER_B.CMT_TOP_CLK1_0->>CMT_R_TOP_UPPER_B_CLKINT_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_R_TOP_UPPER_B_CLKINT_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_CLK1_0" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_0->CMT_PHASER_UP_BUFMRCE_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_0" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_1->CMT_PHASER_OUT_CA_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_2->CMT_PHASER_OUT_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_3->CMT_PHASER_IN_CA_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX0_5->CMT_PHASER_OUT_DB_SELFINEOCLKDELAY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX0_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_11->CMT_PHY_CONTROL_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_4->CMT_PHASER_IN_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_4" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX11_5->CMT_PHASER_OUT_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX11_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX12_7->CMT_PHASER_IN_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX12_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_10->CMT_PHY_CONTROL_PHYCTLWD13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_11->CMT_PHY_CONTROL_PHYCTLWD25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_3->CMT_PHASER_IN_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX13_9->CMT_PHY_CONTROL_PHYCTLWD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX13_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_10->CMT_PHY_CONTROL_PHYCTLWD15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_11->CMT_PHY_CONTROL_PHYCTLWD27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_3->CMT_PHASER_IN_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_6->CMT_PHASER_IN_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_7->CMT_PHASER_IN_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX14_9->CMT_PHY_CONTROL_PHYCTLWD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX14_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_0->CMT_PHASER_REF_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_REF_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_0" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_1->CMT_PHASER_OUT_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_10->CMT_PHY_CONTROL_PHYCTLWD18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_11->CMT_PHY_CONTROL_PHYCTLWD30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_7->CMT_PHASER_IN_DB_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX15_9->CMT_PHY_CONTROL_PHYCTLWD8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX15_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX16_0->CMT_PHASER_UP_BUFMRCE_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_UP_BUFMRCE_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX16_0" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX16_6->CMT_PHASER_OUT_DB_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX16_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_2->CMT_PHASER_OUT_CA_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX17_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX17_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX17_6->CMT_PHASER_OUT_DB_ENCALIB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_ENCALIB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX17_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX18_2->CMT_PHASER_OUT_CA_ENCALIB0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_ENCALIB0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX18_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX18_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX18_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_2->CMT_PHASER_IN_CA_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_4->CMT_PHASER_OUT_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_4" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_6->CMT_PHASER_IN_DB_DIVIDERST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_DIVIDERST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX19_7->CMT_PHASER_IN_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX19_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX1_2->CMT_PHASER_OUT_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX1_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX1_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX1_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_10->CMT_PHY_CONTROL_PHYCTLWD11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_11->CMT_PHY_CONTROL_PHYCTLWD23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX20_9->CMT_PHY_CONTROL_PHYCTLWD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX20_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX22_10->CMT_PHY_CONTROL_WRITECALIBENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_WRITECALIBENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX22_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX23_3->CMT_PHASER_IN_CA_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX23_7->CMT_PHASER_IN_DB_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX23_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_2->CMT_PHASER_OUT_CA_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_5->CMT_PHASER_OUT_DB_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX27_7->CMT_PHASER_IN_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX27_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX28_7->CMT_PHASER_IN_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX28_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_10->CMT_PHY_CONTROL_READCALIBENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_READCALIBENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX29_3->CMT_PHASER_IN_CA_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX29_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX2_2->CMT_PHASER_OUT_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX2_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX2_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX2_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_10->CMT_PHY_CONTROL_PHYCTLWD16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_11->CMT_PHY_CONTROL_PHYCTLWD28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_3->CMT_PHASER_IN_CA_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_6->CMT_PHASER_IN_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX30_9->CMT_PHY_CONTROL_PHYCTLWD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX30_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_1->CMT_PHASER_OUT_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_10->CMT_PHY_CONTROL_PHYCTLWD19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_11->CMT_PHY_CONTROL_PHYCTLWD31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_3->CMT_PHASER_IN_CA_COUNTERLOADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX31_9->CMT_PHY_CONTROL_PHYCTLWD9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX31_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX32_4->CMT_PHASER_IN_CA_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX32_4" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX32_6->CMT_PHASER_OUT_DB_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX32_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_4->CMT_PHASER_IN_CA_RANKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_4" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX34_6->CMT_PHASER_OUT_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX34_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX37_4->CMT_PHASER_OUT_DB_COUNTERLOADVAL8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX37_4" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX39_7->CMT_PHASER_IN_DB_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX39_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX3_4->CMT_PHASER_IN_CA_RANKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_RANKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX3_4" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX3_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX3_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_2->CMT_PHASER_OUT_CA_COARSEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_4->CMT_PHASER_IN_CA_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_4" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX41_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX41_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_11->CMT_PHY_CONTROL_PHYCTLWD21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_5->CMT_PHASER_OUT_DB_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_7->CMT_PHASER_IN_DB_COUNTERLOADVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX43_9->CMT_PHY_CONTROL_PLLLOCK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PLLLOCK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX43_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_10->CMT_PHY_CONTROL_PHYCTLWD12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_11->CMT_PHY_CONTROL_PHYCTLWD24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_3->CMT_PHASER_IN_CA_COUNTERLOADVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_7->CMT_PHASER_IN_DB_COUNTERLOADVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX44_9->CMT_PHY_CONTROL_PHYCTLWD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX44_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_0->CMT_PHASER_REF_PWRDWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_REF_PWRDWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_0" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_10->CMT_PHY_CONTROL_PHYCTLWD14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_11->CMT_PHY_CONTROL_PHYCTLWD26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_3->CMT_PHASER_IN_CA_COUNTERLOADVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_6->CMT_PHASER_IN_DB_COUNTERREADEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_COUNTERREADEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX45_9->CMT_PHY_CONTROL_PHYCTLWD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX45_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_1->CMT_PHASER_OUT_CA_COUNTERLOADVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_10->CMT_PHY_CONTROL_PHYCTLWD17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_11->CMT_PHY_CONTROL_PHYCTLWD29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_6->CMT_PHASER_IN_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX46_9->CMT_PHY_CONTROL_PHYCTLWD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX46_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_1->CMT_PHASER_OUT_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_1" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_10->CMT_PHY_CONTROL_PHYCTLWD20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_11->CMT_PHY_CONTROL_PHYCTLWRENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_3->CMT_PHASER_IN_CA_FINEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_CA_FINEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_3" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX47_9->CMT_PHY_CONTROL_PHYCTLWD10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX47_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_10->CMT_PHY_CONTROL_REFDLLLOCK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_REFDLLLOCK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX4_10" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_11->CMT_PHY_CONTROL_PHYCTLWD22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX4_11" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX4_9->CMT_PHY_CONTROL_PHYCTLWD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHY_CONTROL_PHYCTLWD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX4_9" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX8_6->CMT_PHASER_OUT_DB_FINEENABLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_FINEENABLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX8_6" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX8_7->CMT_PHASER_IN_DB_RSTDQSFIND": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_IN_DB_RSTDQSFIND", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX8_7" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_2->CMT_PHASER_OUT_CA_COARSEINC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_CA_COARSEINC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_2" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_5->CMT_PHASER_OUT_DB_COUNTERLOADVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_5" }, "CMT_TOP_R_UPPER_B.CMT_TOP_IMUX9_6->CMT_PHASER_OUT_DB_EDGEADV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "CMT_PHASER_OUT_DB_EDGEADV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "CMT_TOP_IMUX9_6" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>CMT_FREQ_PHASER_REFMUX_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN0->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN0" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>CMT_FREQ_PHASER_REFMUX_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN1->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN1" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>CMT_FREQ_PHASER_REFMUX_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_PHASER_REFMUX_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.139", + "0.158", + "0.310", + "0.345" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN2->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN2" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFIN3->>PLLOUT_CLK_FREQ_BB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.191", + "0.216", + "0.420", + "0.468" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFIN3" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT0->>PLL_CLK_FREQBB_REBUFOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT0" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT1->>PLL_CLK_FREQBB_REBUFOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT1" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT2->>PLL_CLK_FREQBB_REBUFOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT2" }, "CMT_TOP_R_UPPER_B.PLLOUT_CLK_FREQ_BB_REBUFOUT3->>PLL_CLK_FREQBB_REBUFOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQBB_REBUFOUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLLOUT_CLK_FREQ_BB_REBUFOUT3" }, "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT0->>CMT_FREQ_BB_PREF_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT0" }, "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT1->>CMT_FREQ_BB_PREF_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT1" }, "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT2->>CMT_FREQ_BB_PREF_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT2" }, "CMT_TOP_R_UPPER_B.PLL_CLK_FREQBB_REBUFOUT3->>CMT_FREQ_BB_PREF_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_FREQ_BB_PREF_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQBB_REBUFOUT3" } }, @@ -2715,28 +8372,226 @@ "name": "X0Y0", "prefix": "PHASER_REF", "site_pins": { - "CLKIN": "CMT_PHASER_REF_CLKIN", - "CLKOUT": "CMT_PHASER_REF_CLKOUT", - "LOCKED": "CMT_PHASER_REF_LOCKED", - "PWRDWN": "CMT_PHASER_REF_PWRDWN", - "RST": "CMT_PHASER_REF_RST", - "TESTIN0": "CMT_PHASER_REF_TESTIN0", - "TESTIN1": "CMT_PHASER_REF_TESTIN1", - "TESTIN2": "CMT_PHASER_REF_TESTIN2", - "TESTIN3": "CMT_PHASER_REF_TESTIN3", - "TESTIN4": "CMT_PHASER_REF_TESTIN4", - "TESTIN5": "CMT_PHASER_REF_TESTIN5", - "TESTIN6": "CMT_PHASER_REF_TESTIN6", - "TESTIN7": "CMT_PHASER_REF_TESTIN7", - "TESTOUT0": "CMT_PHASER_REF_TESTOUT0", - "TESTOUT1": "CMT_PHASER_REF_TESTOUT1", - "TESTOUT2": "CMT_PHASER_REF_TESTOUT2", - "TESTOUT3": "CMT_PHASER_REF_TESTOUT3", - "TESTOUT4": "CMT_PHASER_REF_TESTOUT4", - "TESTOUT5": "CMT_PHASER_REF_TESTOUT5", - "TESTOUT6": "CMT_PHASER_REF_TESTOUT6", - "TESTOUT7": "CMT_PHASER_REF_TESTOUT7", - "TMUXOUT": "CMT_PHASER_REF_TMUXOUT" + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_CLKIN" + }, + "CLKOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_CLKOUT" + }, + "LOCKED": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_LOCKED" + }, + "PWRDWN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_PWRDWN" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_RST" + }, + "TESTIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN0" + }, + "TESTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN1" + }, + "TESTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN2" + }, + "TESTIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN3" + }, + "TESTIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN4" + }, + "TESTIN5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN5" + }, + "TESTIN6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN6" + }, + "TESTIN7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_REF_TESTIN7" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT3" + }, + "TESTOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT4" + }, + "TESTOUT5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT5" + }, + "TESTOUT6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT6" + }, + "TESTOUT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TESTOUT7" + }, + "TMUXOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_REF_TMUXOUT" + } }, "type": "PHASER_REF", "x_coord": 0, @@ -2746,110 +8601,1046 @@ "name": "X0Y0", "prefix": "PHY_CONTROL", "site_pins": { - "AUXOUTPUT0": "CMT_PHY_CONTROL_AUXOUTPUT0", - "AUXOUTPUT1": "CMT_PHY_CONTROL_AUXOUTPUT1", - "AUXOUTPUT2": "CMT_PHY_CONTROL_AUXOUTPUT2", - "AUXOUTPUT3": "CMT_PHY_CONTROL_AUXOUTPUT3", - "INBURSTPENDING0": "CMT_PHY_CONTROL_INBURSTPENDING0", - "INBURSTPENDING1": "CMT_PHY_CONTROL_INBURSTPENDING1", - "INBURSTPENDING2": "CMT_PHY_CONTROL_INBURSTPENDING2", - "INBURSTPENDING3": "CMT_PHY_CONTROL_INBURSTPENDING3", - "INRANKA0": "CMT_PHY_CONTROL_INRANKA0", - "INRANKA1": "CMT_PHY_CONTROL_INRANKA1", - "INRANKB0": "CMT_PHY_CONTROL_INRANKB0", - "INRANKB1": "CMT_PHY_CONTROL_INRANKB1", - "INRANKC0": "CMT_PHY_CONTROL_INRANKC0", - "INRANKC1": "CMT_PHY_CONTROL_INRANKC1", - "INRANKD0": "CMT_PHY_CONTROL_INRANKD0", - "INRANKD1": "CMT_PHY_CONTROL_INRANKD1", - "MEMREFCLK": "CMT_PHY_CONTROL_MEMREFCLK", - "OUTBURSTPENDING0": "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "OUTBURSTPENDING1": "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "OUTBURSTPENDING2": "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "OUTBURSTPENDING3": "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "PCENABLECALIB0": "CMT_PHY_CONTROL_PCENABLECALIB0", - "PCENABLECALIB1": "CMT_PHY_CONTROL_PCENABLECALIB1", - "PHYCLK": "CMT_PHY_CONTROL_PHYCLK", - "PHYCTLALMOSTFULL": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "PHYCTLEMPTY": "CMT_PHY_CONTROL_PHYCTLEMPTY", - "PHYCTLFULL": "CMT_PHY_CONTROL_PHYCTLFULL", - "PHYCTLMSTREMPTY": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "PHYCTLREADY": "CMT_PHY_CONTROL_PHYCTLREADY", - "PHYCTLWD0": "CMT_PHY_CONTROL_PHYCTLWD0", - "PHYCTLWD1": "CMT_PHY_CONTROL_PHYCTLWD1", - "PHYCTLWD10": "CMT_PHY_CONTROL_PHYCTLWD10", - "PHYCTLWD11": "CMT_PHY_CONTROL_PHYCTLWD11", - "PHYCTLWD12": "CMT_PHY_CONTROL_PHYCTLWD12", - "PHYCTLWD13": "CMT_PHY_CONTROL_PHYCTLWD13", - "PHYCTLWD14": "CMT_PHY_CONTROL_PHYCTLWD14", - "PHYCTLWD15": "CMT_PHY_CONTROL_PHYCTLWD15", - "PHYCTLWD16": "CMT_PHY_CONTROL_PHYCTLWD16", - "PHYCTLWD17": "CMT_PHY_CONTROL_PHYCTLWD17", - "PHYCTLWD18": "CMT_PHY_CONTROL_PHYCTLWD18", - "PHYCTLWD19": "CMT_PHY_CONTROL_PHYCTLWD19", - "PHYCTLWD2": "CMT_PHY_CONTROL_PHYCTLWD2", - "PHYCTLWD20": "CMT_PHY_CONTROL_PHYCTLWD20", - "PHYCTLWD21": "CMT_PHY_CONTROL_PHYCTLWD21", - "PHYCTLWD22": "CMT_PHY_CONTROL_PHYCTLWD22", - "PHYCTLWD23": "CMT_PHY_CONTROL_PHYCTLWD23", - "PHYCTLWD24": "CMT_PHY_CONTROL_PHYCTLWD24", - "PHYCTLWD25": "CMT_PHY_CONTROL_PHYCTLWD25", - "PHYCTLWD26": "CMT_PHY_CONTROL_PHYCTLWD26", - "PHYCTLWD27": "CMT_PHY_CONTROL_PHYCTLWD27", - "PHYCTLWD28": "CMT_PHY_CONTROL_PHYCTLWD28", - "PHYCTLWD29": "CMT_PHY_CONTROL_PHYCTLWD29", - "PHYCTLWD3": "CMT_PHY_CONTROL_PHYCTLWD3", - "PHYCTLWD30": "CMT_PHY_CONTROL_PHYCTLWD30", - "PHYCTLWD31": "CMT_PHY_CONTROL_PHYCTLWD31", - "PHYCTLWD4": "CMT_PHY_CONTROL_PHYCTLWD4", - "PHYCTLWD5": "CMT_PHY_CONTROL_PHYCTLWD5", - "PHYCTLWD6": "CMT_PHY_CONTROL_PHYCTLWD6", - "PHYCTLWD7": "CMT_PHY_CONTROL_PHYCTLWD7", - "PHYCTLWD8": "CMT_PHY_CONTROL_PHYCTLWD8", - "PHYCTLWD9": "CMT_PHY_CONTROL_PHYCTLWD9", - "PHYCTLWRENABLE": "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "PLLLOCK": "CMT_PHY_CONTROL_PLLLOCK", - "READCALIBENABLE": "CMT_PHY_CONTROL_READCALIBENABLE", - "REFDLLLOCK": "CMT_PHY_CONTROL_REFDLLLOCK", - "RESET": "CMT_PHY_CONTROL_RESET", - "SCANENABLEN": "CMT_PHY_CONTROL_SCANENABLEN", - "SYNCIN": "CMT_PHY_CONTROL_SYNCIN", - "TESTINPUT0": "CMT_PHY_CONTROL_TESTINPUT0", - "TESTINPUT1": "CMT_PHY_CONTROL_TESTINPUT1", - "TESTINPUT10": "CMT_PHY_CONTROL_TESTINPUT10", - "TESTINPUT11": "CMT_PHY_CONTROL_TESTINPUT11", - "TESTINPUT12": "CMT_PHY_CONTROL_TESTINPUT12", - "TESTINPUT13": "CMT_PHY_CONTROL_TESTINPUT13", - "TESTINPUT14": "CMT_PHY_CONTROL_TESTINPUT14", - "TESTINPUT15": "CMT_PHY_CONTROL_TESTINPUT15", - "TESTINPUT2": "CMT_PHY_CONTROL_TESTINPUT2", - "TESTINPUT3": "CMT_PHY_CONTROL_TESTINPUT3", - "TESTINPUT4": "CMT_PHY_CONTROL_TESTINPUT4", - "TESTINPUT5": "CMT_PHY_CONTROL_TESTINPUT5", - "TESTINPUT6": "CMT_PHY_CONTROL_TESTINPUT6", - "TESTINPUT7": "CMT_PHY_CONTROL_TESTINPUT7", - "TESTINPUT8": "CMT_PHY_CONTROL_TESTINPUT8", - "TESTINPUT9": "CMT_PHY_CONTROL_TESTINPUT9", - "TESTOUTPUT0": "CMT_PHY_CONTROL_TESTOUTPUT0", - "TESTOUTPUT1": "CMT_PHY_CONTROL_TESTOUTPUT1", - "TESTOUTPUT10": "CMT_PHY_CONTROL_TESTOUTPUT10", - "TESTOUTPUT11": "CMT_PHY_CONTROL_TESTOUTPUT11", - "TESTOUTPUT12": "CMT_PHY_CONTROL_TESTOUTPUT12", - "TESTOUTPUT13": "CMT_PHY_CONTROL_TESTOUTPUT13", - "TESTOUTPUT14": "CMT_PHY_CONTROL_TESTOUTPUT14", - "TESTOUTPUT15": "CMT_PHY_CONTROL_TESTOUTPUT15", - "TESTOUTPUT2": "CMT_PHY_CONTROL_TESTOUTPUT2", - "TESTOUTPUT3": "CMT_PHY_CONTROL_TESTOUTPUT3", - "TESTOUTPUT4": "CMT_PHY_CONTROL_TESTOUTPUT4", - "TESTOUTPUT5": "CMT_PHY_CONTROL_TESTOUTPUT5", - "TESTOUTPUT6": "CMT_PHY_CONTROL_TESTOUTPUT6", - "TESTOUTPUT7": "CMT_PHY_CONTROL_TESTOUTPUT7", - "TESTOUTPUT8": "CMT_PHY_CONTROL_TESTOUTPUT8", - "TESTOUTPUT9": "CMT_PHY_CONTROL_TESTOUTPUT9", - "TESTSELECT0": "CMT_PHY_CONTROL_TESTSELECT0", - "TESTSELECT1": "CMT_PHY_CONTROL_TESTSELECT1", - "TESTSELECT2": "CMT_PHY_CONTROL_TESTSELECT2", - "WRITECALIBENABLE": "CMT_PHY_CONTROL_WRITECALIBENABLE" + "AUXOUTPUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT0" + }, + "AUXOUTPUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT1" + }, + "AUXOUTPUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT2" + }, + "AUXOUTPUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_AUXOUTPUT3" + }, + "INBURSTPENDING0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING0" + }, + "INBURSTPENDING1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING1" + }, + "INBURSTPENDING2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING2" + }, + "INBURSTPENDING3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INBURSTPENDING3" + }, + "INRANKA0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKA0" + }, + "INRANKA1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKA1" + }, + "INRANKB0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKB0" + }, + "INRANKB1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKB1" + }, + "INRANKC0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKC0" + }, + "INRANKC1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKC1" + }, + "INRANKD0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKD0" + }, + "INRANKD1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_INRANKD1" + }, + "MEMREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_MEMREFCLK" + }, + "OUTBURSTPENDING0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING0" + }, + "OUTBURSTPENDING1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING1" + }, + "OUTBURSTPENDING2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING2" + }, + "OUTBURSTPENDING3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_OUTBURSTPENDING3" + }, + "PCENABLECALIB0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PCENABLECALIB0" + }, + "PCENABLECALIB1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PCENABLECALIB1" + }, + "PHYCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCLK" + }, + "PHYCTLALMOSTFULL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PHYCTLALMOSTFULL" + }, + "PHYCTLEMPTY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PHYCTLEMPTY" + }, + "PHYCTLFULL": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PHYCTLFULL" + }, + "PHYCTLMSTREMPTY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLMSTREMPTY" + }, + "PHYCTLREADY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_PHYCTLREADY" + }, + "PHYCTLWD0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD0" + }, + "PHYCTLWD1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD1" + }, + "PHYCTLWD10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD10" + }, + "PHYCTLWD11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD11" + }, + "PHYCTLWD12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD12" + }, + "PHYCTLWD13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD13" + }, + "PHYCTLWD14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD14" + }, + "PHYCTLWD15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD15" + }, + "PHYCTLWD16": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD16" + }, + "PHYCTLWD17": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD17" + }, + "PHYCTLWD18": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD18" + }, + "PHYCTLWD19": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD19" + }, + "PHYCTLWD2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD2" + }, + "PHYCTLWD20": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD20" + }, + "PHYCTLWD21": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD21" + }, + "PHYCTLWD22": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD22" + }, + "PHYCTLWD23": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD23" + }, + "PHYCTLWD24": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD24" + }, + "PHYCTLWD25": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD25" + }, + "PHYCTLWD26": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD26" + }, + "PHYCTLWD27": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD27" + }, + "PHYCTLWD28": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD28" + }, + "PHYCTLWD29": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD29" + }, + "PHYCTLWD3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD3" + }, + "PHYCTLWD30": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD30" + }, + "PHYCTLWD31": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD31" + }, + "PHYCTLWD4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD4" + }, + "PHYCTLWD5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD5" + }, + "PHYCTLWD6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD6" + }, + "PHYCTLWD7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD7" + }, + "PHYCTLWD8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD8" + }, + "PHYCTLWD9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWD9" + }, + "PHYCTLWRENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PHYCTLWRENABLE" + }, + "PLLLOCK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_PLLLOCK" + }, + "READCALIBENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_READCALIBENABLE" + }, + "REFDLLLOCK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_REFDLLLOCK" + }, + "RESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_RESET" + }, + "SCANENABLEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_SCANENABLEN" + }, + "SYNCIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_SYNCIN" + }, + "TESTINPUT0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT0" + }, + "TESTINPUT1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT1" + }, + "TESTINPUT10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT10" + }, + "TESTINPUT11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT11" + }, + "TESTINPUT12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT12" + }, + "TESTINPUT13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT13" + }, + "TESTINPUT14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT14" + }, + "TESTINPUT15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT15" + }, + "TESTINPUT2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT2" + }, + "TESTINPUT3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT3" + }, + "TESTINPUT4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT4" + }, + "TESTINPUT5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT5" + }, + "TESTINPUT6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT6" + }, + "TESTINPUT7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHY_CONTROL_TESTINPUT7" + }, + "TESTINPUT8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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"CMT_PHY_CONTROL_TESTOUTPUT13" + }, + "TESTOUTPUT14": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT14" + }, + "TESTOUTPUT15": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT15" + }, + "TESTOUTPUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT2" + }, + "TESTOUTPUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT3" + }, + "TESTOUTPUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT4" + }, + "TESTOUTPUT5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHY_CONTROL_TESTOUTPUT5" + }, + "TESTOUTPUT6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": 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"CMT_PHY_CONTROL_WRITECALIBENABLE" + } }, "type": "PHY_CONTROL", "x_coord": 0, @@ -2859,83 +9650,776 @@ "name": "X0Y0", "prefix": "PHASER_OUT_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_OUT_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "COARSEENABLE": "CMT_PHASER_OUT_CA_COARSEENABLE", - "COARSEINC": "CMT_PHASER_OUT_CA_COARSEINC", - "COARSEOVERFLOW": "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "COUNTERLOADEN": "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "COUNTERREADEN": "CMT_PHASER_OUT_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "COUNTERREADVAL6": "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "COUNTERREADVAL7": "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "COUNTERREADVAL8": "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CTSBUS0": "CMT_PHASER_OUT_CA_CTSBUS0", - "CTSBUS1": "CMT_PHASER_OUT_CA_CTSBUS1", - "DIVIDERST": "CMT_PHASER_OUT_CA_DIVIDERST", - "DQSBUS0": "CMT_PHASER_OUT_CA_DQSBUS0", - "DQSBUS1": "CMT_PHASER_OUT_CA_DQSBUS1", - "DTSBUS0": "CMT_PHASER_OUT_CA_DTSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_CA_DTSBUS1", - "EDGEADV": "CMT_PHASER_OUT_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_OUT_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_OUT_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_CA_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_CA_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_CA_OCLK", - "OCLKDELAYED": "CMT_PHASER_OUT_CA_OCLKDELAYED", - "OCLKDIV": "CMT_PHASER_OUT_CA_OCLKDIV", - "OSERDESRST": "CMT_PHASER_OUT_CA_OSERDESRST", - "PHASEREFCLK": "CMT_PHASER_OUT_CA_PHASEREFCLK", - "RDENABLE": "CMT_PHASER_OUT_CA_RDENABLE", - "RST": "CMT_PHASER_OUT_CA_RST", - "SCANCLK": "CMT_PHASER_OUT_CA_SCANCLK", - "SCANENB": "CMT_PHASER_OUT_CA_SCANENB", - "SCANIN": "CMT_PHASER_OUT_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_OUT_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_OUT_CA_SCANOUT", - "SELFINEOCLKDELAY": "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "SYNCIN": "CMT_PHASER_OUT_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_OUT_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_OUT_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_OUT_CA_TESTIN1", - "TESTIN10": "CMT_PHASER_OUT_CA_TESTIN10", - "TESTIN11": "CMT_PHASER_OUT_CA_TESTIN11", - "TESTIN12": "CMT_PHASER_OUT_CA_TESTIN12", - "TESTIN13": "CMT_PHASER_OUT_CA_TESTIN13", - "TESTIN14": "CMT_PHASER_OUT_CA_TESTIN14", - "TESTIN15": "CMT_PHASER_OUT_CA_TESTIN15", - "TESTIN2": "CMT_PHASER_OUT_CA_TESTIN2", - "TESTIN3": "CMT_PHASER_OUT_CA_TESTIN3", - "TESTIN4": "CMT_PHASER_OUT_CA_TESTIN4", - "TESTIN5": "CMT_PHASER_OUT_CA_TESTIN5", - "TESTIN6": "CMT_PHASER_OUT_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_OUT_CA_TESTIN7", - "TESTIN8": "CMT_PHASER_OUT_CA_TESTIN8", - "TESTIN9": "CMT_PHASER_OUT_CA_TESTIN9", - "TESTOUT0": "CMT_PHASER_OUT_CA_TESTOUT0", - "TESTOUT1": "CMT_PHASER_OUT_CA_TESTOUT1", - "TESTOUT2": "CMT_PHASER_OUT_CA_TESTOUT2", - "TESTOUT3": "CMT_PHASER_OUT_CA_TESTOUT3" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_BURSTPENDINGPHY" + }, + "COARSEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEENABLE" + }, + "COARSEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COARSEINC" + }, + "COARSEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COARSEOVERFLOW" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADEN" + }, + "COUNTERLOADVAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL0" + }, + "COUNTERLOADVAL1": { + "cap": "0.000", + "delay": [ + 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"CMT_PHASER_OUT_CA_COUNTERLOADVAL7" + }, + "COUNTERLOADVAL8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERLOADVAL8" + }, + "COUNTERREADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_CA_COUNTERREADEN" + }, + "COUNTERREADVAL0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL0" + }, + "COUNTERREADVAL1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL1" + }, + "COUNTERREADVAL2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL2" + }, + "COUNTERREADVAL3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_CA_COUNTERREADVAL3" + }, + "COUNTERREADVAL4": { + "delay": [ + "0.000", + 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"X0Y0", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_CA_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_CA_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_CA_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_CA_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_CA_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_CA_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_CA_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_CA_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_CA_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_CA_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_CA_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_CA_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_CA_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_CA_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_CA_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_CA_ICLK", - "ICLKDIV": "CMT_PHASER_IN_CA_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_CA_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_CA_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_CA_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_CA_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_CA_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_CA_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_CA_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_CA_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_CA_RCLK", - "RST": "CMT_PHASER_IN_CA_RST", - "RSTDQSFIND": "CMT_PHASER_IN_CA_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_CA_SCANCLK", - "SCANENB": "CMT_PHASER_IN_CA_SCANENB", - "SCANIN": "CMT_PHASER_IN_CA_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_CA_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_CA_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_CA_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_CA_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_CA_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_CA_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_CA_STG1READ", - "STG1REGL0": "CMT_PHASER_IN_CA_STG1REGL0", - "STG1REGL1": "CMT_PHASER_IN_CA_STG1REGL1", - "STG1REGL2": "CMT_PHASER_IN_CA_STG1REGL2", - "STG1REGL3": "CMT_PHASER_IN_CA_STG1REGL3", - "STG1REGL4": "CMT_PHASER_IN_CA_STG1REGL4", - "STG1REGL5": "CMT_PHASER_IN_CA_STG1REGL5", - "STG1REGL6": "CMT_PHASER_IN_CA_STG1REGL6", - "STG1REGL7": "CMT_PHASER_IN_CA_STG1REGL7", - "STG1REGL8": "CMT_PHASER_IN_CA_STG1REGL8", - "STG1REGR0": "CMT_PHASER_IN_CA_STG1REGR0", - "STG1REGR1": "CMT_PHASER_IN_CA_STG1REGR1", - "STG1REGR2": "CMT_PHASER_IN_CA_STG1REGR2", - "STG1REGR3": "CMT_PHASER_IN_CA_STG1REGR3", - "STG1REGR4": "CMT_PHASER_IN_CA_STG1REGR4", - "STG1REGR5": "CMT_PHASER_IN_CA_STG1REGR5", - "STG1REGR6": "CMT_PHASER_IN_CA_STG1REGR6", - "STG1REGR7": "CMT_PHASER_IN_CA_STG1REGR7", - "STG1REGR8": "CMT_PHASER_IN_CA_STG1REGR8", - "SYNCIN": "CMT_PHASER_IN_CA_SYNCIN", - "SYSCLK": "CMT_PHASER_IN_CA_SYSCLK", - "TESTIN0": "CMT_PHASER_IN_CA_TESTIN0", - "TESTIN1": "CMT_PHASER_IN_CA_TESTIN1", - "TESTIN10": "CMT_PHASER_IN_CA_TESTIN10", - "TESTIN11": "CMT_PHASER_IN_CA_TESTIN11", - "TESTIN12": "CMT_PHASER_IN_CA_TESTIN12", - "TESTIN13": "CMT_PHASER_IN_CA_TESTIN13", - "TESTIN2": "CMT_PHASER_IN_CA_TESTIN2", - "TESTIN3": "CMT_PHASER_IN_CA_TESTIN3", - "TESTIN4": "CMT_PHASER_IN_CA_TESTIN4", - "TESTIN5": "CMT_PHASER_IN_CA_TESTIN5", - "TESTIN6": "CMT_PHASER_IN_CA_TESTIN6", - "TESTIN7": "CMT_PHASER_IN_CA_TESTIN7", - "TESTIN8": "CMT_PHASER_IN_CA_TESTIN8", - "TESTIN9": "CMT_PHASER_IN_CA_TESTIN9", - "TESTOUT0": "CMT_PHASER_IN_CA_TESTOUT0", - "TESTOUT1": "CMT_PHASER_IN_CA_TESTOUT1", - "TESTOUT2": "CMT_PHASER_IN_CA_TESTOUT2", - "TESTOUT3": "CMT_PHASER_IN_CA_TESTOUT3", - "WRENABLE": "CMT_PHASER_IN_CA_WRENABLE" + "BURSTPENDING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_CA_BURSTPENDING" + }, + "BURSTPENDINGPHY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_CA_BURSTPENDINGPHY" + }, + "COUNTERLOADEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_CA_COUNTERLOADEN" + }, + "COUNTERLOADVAL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_CA_COUNTERLOADVAL0" + }, + "COUNTERLOADVAL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + 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"COUNTERLOADVAL4": "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "COUNTERLOADVAL6": "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "COUNTERLOADVAL7": "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "COUNTERLOADVAL8": "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "COUNTERREADEN": "CMT_PHASER_OUT_DB_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "COUNTERREADVAL6": "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "COUNTERREADVAL7": "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "COUNTERREADVAL8": "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CTSBUS0": "CMT_PHASER_OUT_DB_CTSBUS0", - "CTSBUS1": "CMT_PHASER_OUT_DB_CTSBUS1", - "DIVIDERST": "CMT_PHASER_OUT_DB_DIVIDERST", - "DQSBUS0": "CMT_PHASER_OUT_DB_DQSBUS0", - "DQSBUS1": "CMT_PHASER_OUT_DB_DQSBUS1", - "DTSBUS0": "CMT_PHASER_OUT_DB_DTSBUS0", - "DTSBUS1": "CMT_PHASER_OUT_DB_DTSBUS1", - "EDGEADV": "CMT_PHASER_OUT_DB_EDGEADV", - "ENCALIB0": "CMT_PHASER_OUT_DB_ENCALIB0", - "ENCALIB1": "CMT_PHASER_OUT_DB_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "FINEENABLE": "CMT_PHASER_OUT_DB_FINEENABLE", - "FINEINC": "CMT_PHASER_OUT_DB_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_OUT_DB_FREQREFCLK", - "MEMREFCLK": "CMT_PHASER_OUT_DB_MEMREFCLK", - "OCLK": "CMT_PHASER_OUT_DB_OCLK", - "OCLKDELAYED": "CMT_PHASER_OUT_DB_OCLKDELAYED", - "OCLKDIV": "CMT_PHASER_OUT_DB_OCLKDIV", - "OSERDESRST": "CMT_PHASER_OUT_DB_OSERDESRST", - "PHASEREFCLK": "CMT_PHASER_OUT_DB_PHASEREFCLK", - "RDENABLE": "CMT_PHASER_OUT_DB_RDENABLE", - "RST": "CMT_PHASER_OUT_DB_RST", - "SCANCLK": "CMT_PHASER_OUT_DB_SCANCLK", - "SCANENB": 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"wire": "CMT_PHASER_OUT_DB_EDGEADV" + }, + "ENCALIB0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIB0" + }, + "ENCALIB1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIB1" + }, + "ENCALIBPHY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIBPHY0" + }, + "ENCALIBPHY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_ENCALIBPHY1" + }, + "FINEENABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_FINEENABLE" + }, + "FINEINC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_FINEINC" + }, + "FINEOVERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_FINEOVERFLOW" + }, + "FREQREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_FREQREFCLK" + }, + "MEMREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_MEMREFCLK" + }, + "OCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OCLK" + }, + "OCLKDELAYED": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OCLKDELAYED" + }, + "OCLKDIV": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OCLKDIV" + }, + "OSERDESRST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_OSERDESRST" + }, + "PHASEREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_PHASEREFCLK" + }, + "RDENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_RDENABLE" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_RST" + }, + "SCANCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANCLK" + }, + "SCANENB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANENB" + }, + "SCANIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANIN" + }, + "SCANMODEB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_OUT_DB_SCANMODEB" + }, + "SCANOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_SCANOUT" + }, + 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"wire": "CMT_PHASER_OUT_DB_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_OUT_DB_TESTOUT3" + } }, "type": "PHASER_OUT_PHY", "x_coord": 0, @@ -3132,98 +12137,926 @@ "name": "X0Y1", "prefix": "PHASER_IN_PHY", "site_pins": { - "BURSTPENDING": "CMT_PHASER_IN_DB_BURSTPENDING", - "BURSTPENDINGPHY": "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "COUNTERLOADEN": "CMT_PHASER_IN_DB_COUNTERLOADEN", - "COUNTERLOADVAL0": "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "COUNTERLOADVAL1": "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "COUNTERLOADVAL2": "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "COUNTERLOADVAL3": "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "COUNTERLOADVAL4": "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "COUNTERLOADVAL5": "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "COUNTERREADEN": "CMT_PHASER_IN_DB_COUNTERREADEN", - "COUNTERREADVAL0": "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "COUNTERREADVAL1": "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "COUNTERREADVAL2": "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "COUNTERREADVAL3": "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "COUNTERREADVAL4": "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "COUNTERREADVAL5": "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "DIVIDERST": "CMT_PHASER_IN_DB_DIVIDERST", - "DQSFOUND": "CMT_PHASER_IN_DB_DQSFOUND", - "DQSOUTOFRANGE": "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "EDGEADV": "CMT_PHASER_IN_DB_EDGEADV", - "ENCALIB0": "CMT_PHASER_IN_DB_ENCALIB0", - "ENCALIB1": "CMT_PHASER_IN_DB_ENCALIB1", - "ENCALIBPHY0": "CMT_PHASER_IN_DB_ENCALIBPHY0", - "ENCALIBPHY1": "CMT_PHASER_IN_DB_ENCALIBPHY1", - "ENSTG1": "CMT_PHASER_IN_DB_ENSTG1", - "ENSTG1ADJUSTB": "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "FINEENABLE": "CMT_PHASER_IN_DB_FINEENABLE", - "FINEINC": "CMT_PHASER_IN_DB_FINEINC", - "FINEOVERFLOW": "CMT_PHASER_IN_DB_FINEOVERFLOW", - "FREQREFCLK": "CMT_PHASER_IN_DB_FREQREFCLK", - "ICLK": "CMT_PHASER_IN_DB_ICLK", - "ICLKDIV": "CMT_PHASER_IN_DB_ICLKDIV", - "ISERDESRST": "CMT_PHASER_IN_DB_ISERDESRST", - "MEMREFCLK": "CMT_PHASER_IN_DB_MEMREFCLK", - "PHASELOCKED": "CMT_PHASER_IN_DB_PHASELOCKED", - "PHASEREFCLK": "CMT_PHASER_IN_DB_PHASEREFCLK", - "RANKSEL0": "CMT_PHASER_IN_DB_RANKSEL0", - "RANKSEL1": "CMT_PHASER_IN_DB_RANKSEL1", - "RANKSELPHY0": "CMT_PHASER_IN_DB_RANKSELPHY0", - "RANKSELPHY1": "CMT_PHASER_IN_DB_RANKSELPHY1", - "RCLK": "CMT_PHASER_IN_DB_RCLK", - "RST": "CMT_PHASER_IN_DB_RST", - "RSTDQSFIND": "CMT_PHASER_IN_DB_RSTDQSFIND", - "SCANCLK": "CMT_PHASER_IN_DB_SCANCLK", - "SCANENB": "CMT_PHASER_IN_DB_SCANENB", - "SCANIN": "CMT_PHASER_IN_DB_SCANIN", - "SCANMODEB": "CMT_PHASER_IN_DB_SCANMODEB", - "SCANOUT": "CMT_PHASER_IN_DB_SCANOUT", - "SELCALORSTG1": "CMT_PHASER_IN_DB_SELCALORSTG1", - "STG1INCDEC": "CMT_PHASER_IN_DB_STG1INCDEC", - "STG1LOAD": "CMT_PHASER_IN_DB_STG1LOAD", - "STG1OVERFLOW": "CMT_PHASER_IN_DB_STG1OVERFLOW", - "STG1READ": "CMT_PHASER_IN_DB_STG1READ", - "STG1REGL0": "CMT_PHASER_IN_DB_STG1REGL0", - "STG1REGL1": "CMT_PHASER_IN_DB_STG1REGL1", - "STG1REGL2": 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"0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN3" + }, + "TESTIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN4" + }, + "TESTIN5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN5" + }, + "TESTIN6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN6" + }, + "TESTIN7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN7" + }, + "TESTIN8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN8" + }, + "TESTIN9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "CMT_PHASER_IN_DB_TESTIN9" + }, + "TESTOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT0" + }, + "TESTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT1" + }, + "TESTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT2" + }, + "TESTOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_TESTOUT3" + }, + "WRENABLE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "CMT_PHASER_IN_DB_WRENABLE" + } }, "type": "PHASER_IN_PHY", "x_coord": 0, @@ -3231,3294 +13064,9792 @@ } ], "tile_type": "CMT_TOP_R_UPPER_B", - "wires": [ - "CMT_FREQ_BB_PREF_IN0", - "CMT_FREQ_BB_PREF_IN1", - "CMT_FREQ_BB_PREF_IN2", - "CMT_FREQ_BB_PREF_IN3", - "CMT_FREQ_PHASER_REFMUX_0", - "CMT_FREQ_PHASER_REFMUX_1", - "CMT_FREQ_PHASER_REFMUX_2", - "CMT_PHASERD_CTSBUS0", - "CMT_PHASERD_CTSBUS1", - "CMT_PHASERD_DQSBUS0", - "CMT_PHASERD_DQSBUS1", - "CMT_PHASERD_DTSBUS0", - "CMT_PHASERD_DTSBUS1", - "CMT_PHASERREF_PHASERIN_C", - "CMT_PHASERREF_PHASERIN_D", - "CMT_PHASERREF_PHASEROUT_C", - "CMT_PHASERREF_PHASEROUT_D", - "CMT_PHASERTOP_PHYCTLEMPTY", - "CMT_PHASERTOP_PHYCTLMSTREMPTY", - "CMT_PHASER_C_ICLKDIV_TOIOI", - "CMT_PHASER_C_ICLK_TOIOI", - "CMT_PHASER_C_OCLK90_TOIOI", - "CMT_PHASER_C_OCLKDIV_TOIOI", - "CMT_PHASER_C_OCLK_TOIOI", - "CMT_PHASER_IN_CA_BURSTPENDING", - "CMT_PHASER_IN_CA_BURSTPENDINGPHY", - "CMT_PHASER_IN_CA_COUNTERLOADEN", - "CMT_PHASER_IN_CA_COUNTERLOADVAL0", - "CMT_PHASER_IN_CA_COUNTERLOADVAL1", - "CMT_PHASER_IN_CA_COUNTERLOADVAL2", - "CMT_PHASER_IN_CA_COUNTERLOADVAL3", - "CMT_PHASER_IN_CA_COUNTERLOADVAL4", - "CMT_PHASER_IN_CA_COUNTERLOADVAL5", - "CMT_PHASER_IN_CA_COUNTERREADEN", - "CMT_PHASER_IN_CA_COUNTERREADVAL0", - "CMT_PHASER_IN_CA_COUNTERREADVAL1", - "CMT_PHASER_IN_CA_COUNTERREADVAL2", - "CMT_PHASER_IN_CA_COUNTERREADVAL3", - "CMT_PHASER_IN_CA_COUNTERREADVAL4", - "CMT_PHASER_IN_CA_COUNTERREADVAL5", - "CMT_PHASER_IN_CA_DIVIDERST", - "CMT_PHASER_IN_CA_DQSFOUND", - "CMT_PHASER_IN_CA_DQSOUTOFRANGE", - "CMT_PHASER_IN_CA_EDGEADV", - "CMT_PHASER_IN_CA_ENCALIB0", - "CMT_PHASER_IN_CA_ENCALIB1", - "CMT_PHASER_IN_CA_ENCALIBPHY0", - "CMT_PHASER_IN_CA_ENCALIBPHY1", - "CMT_PHASER_IN_CA_ENSTG1", - "CMT_PHASER_IN_CA_ENSTG1ADJUSTB", - "CMT_PHASER_IN_CA_FINEENABLE", - "CMT_PHASER_IN_CA_FINEINC", - "CMT_PHASER_IN_CA_FINEOVERFLOW", - "CMT_PHASER_IN_CA_FREQREFCLK", - "CMT_PHASER_IN_CA_ICLK", - "CMT_PHASER_IN_CA_ICLKDIV", - "CMT_PHASER_IN_CA_ISERDESRST", - "CMT_PHASER_IN_CA_MEMREFCLK", - "CMT_PHASER_IN_CA_PHASELOCKED", - "CMT_PHASER_IN_CA_PHASEREFCLK", - "CMT_PHASER_IN_CA_RANKSEL0", - "CMT_PHASER_IN_CA_RANKSEL1", - "CMT_PHASER_IN_CA_RANKSELPHY0", - "CMT_PHASER_IN_CA_RANKSELPHY1", - "CMT_PHASER_IN_CA_RCLK", - "CMT_PHASER_IN_CA_RST", - "CMT_PHASER_IN_CA_RSTDQSFIND", - "CMT_PHASER_IN_CA_SCANCLK", - "CMT_PHASER_IN_CA_SCANENB", - "CMT_PHASER_IN_CA_SCANIN", - "CMT_PHASER_IN_CA_SCANMODEB", - "CMT_PHASER_IN_CA_SCANOUT", - "CMT_PHASER_IN_CA_SELCALORSTG1", - "CMT_PHASER_IN_CA_STG1INCDEC", - "CMT_PHASER_IN_CA_STG1LOAD", - "CMT_PHASER_IN_CA_STG1OVERFLOW", - "CMT_PHASER_IN_CA_STG1READ", - "CMT_PHASER_IN_CA_STG1REGL0", - "CMT_PHASER_IN_CA_STG1REGL1", - "CMT_PHASER_IN_CA_STG1REGL2", - "CMT_PHASER_IN_CA_STG1REGL3", - "CMT_PHASER_IN_CA_STG1REGL4", - "CMT_PHASER_IN_CA_STG1REGL5", - "CMT_PHASER_IN_CA_STG1REGL6", - "CMT_PHASER_IN_CA_STG1REGL7", - "CMT_PHASER_IN_CA_STG1REGL8", - "CMT_PHASER_IN_CA_STG1REGR0", - "CMT_PHASER_IN_CA_STG1REGR1", - "CMT_PHASER_IN_CA_STG1REGR2", - "CMT_PHASER_IN_CA_STG1REGR3", - "CMT_PHASER_IN_CA_STG1REGR4", - "CMT_PHASER_IN_CA_STG1REGR5", - "CMT_PHASER_IN_CA_STG1REGR6", - "CMT_PHASER_IN_CA_STG1REGR7", - "CMT_PHASER_IN_CA_STG1REGR8", - "CMT_PHASER_IN_CA_SYNCIN", - "CMT_PHASER_IN_CA_SYSCLK", - "CMT_PHASER_IN_CA_TESTIN0", - "CMT_PHASER_IN_CA_TESTIN1", - "CMT_PHASER_IN_CA_TESTIN10", - "CMT_PHASER_IN_CA_TESTIN11", - "CMT_PHASER_IN_CA_TESTIN12", - "CMT_PHASER_IN_CA_TESTIN13", - "CMT_PHASER_IN_CA_TESTIN2", - "CMT_PHASER_IN_CA_TESTIN3", - "CMT_PHASER_IN_CA_TESTIN4", - "CMT_PHASER_IN_CA_TESTIN5", - "CMT_PHASER_IN_CA_TESTIN6", - "CMT_PHASER_IN_CA_TESTIN7", - "CMT_PHASER_IN_CA_TESTIN8", - "CMT_PHASER_IN_CA_TESTIN9", - "CMT_PHASER_IN_CA_TESTOUT0", - "CMT_PHASER_IN_CA_TESTOUT1", - "CMT_PHASER_IN_CA_TESTOUT2", - "CMT_PHASER_IN_CA_TESTOUT3", - "CMT_PHASER_IN_CA_WRENABLE", - "CMT_PHASER_IN_C_ICLK", - "CMT_PHASER_IN_C_ICLKDIV", - "CMT_PHASER_IN_C_RCLK2", - "CMT_PHASER_IN_C_WRCLK_TOFIFO", - "CMT_PHASER_IN_C_WRENABLE_FIFO", - "CMT_PHASER_IN_DB_BURSTPENDING", - "CMT_PHASER_IN_DB_BURSTPENDINGPHY", - "CMT_PHASER_IN_DB_COUNTERLOADEN", - "CMT_PHASER_IN_DB_COUNTERLOADVAL0", - "CMT_PHASER_IN_DB_COUNTERLOADVAL1", - "CMT_PHASER_IN_DB_COUNTERLOADVAL2", - "CMT_PHASER_IN_DB_COUNTERLOADVAL3", - "CMT_PHASER_IN_DB_COUNTERLOADVAL4", - "CMT_PHASER_IN_DB_COUNTERLOADVAL5", - "CMT_PHASER_IN_DB_COUNTERREADEN", - "CMT_PHASER_IN_DB_COUNTERREADVAL0", - "CMT_PHASER_IN_DB_COUNTERREADVAL1", - "CMT_PHASER_IN_DB_COUNTERREADVAL2", - "CMT_PHASER_IN_DB_COUNTERREADVAL3", - "CMT_PHASER_IN_DB_COUNTERREADVAL4", - "CMT_PHASER_IN_DB_COUNTERREADVAL5", - "CMT_PHASER_IN_DB_DIVIDERST", - "CMT_PHASER_IN_DB_DQSFOUND", - "CMT_PHASER_IN_DB_DQSOUTOFRANGE", - "CMT_PHASER_IN_DB_EDGEADV", - "CMT_PHASER_IN_DB_ENCALIB0", - "CMT_PHASER_IN_DB_ENCALIB1", - "CMT_PHASER_IN_DB_ENCALIBPHY0", - "CMT_PHASER_IN_DB_ENCALIBPHY1", - "CMT_PHASER_IN_DB_ENSTG1", - "CMT_PHASER_IN_DB_ENSTG1ADJUSTB", - "CMT_PHASER_IN_DB_FINEENABLE", - "CMT_PHASER_IN_DB_FINEINC", - "CMT_PHASER_IN_DB_FINEOVERFLOW", - "CMT_PHASER_IN_DB_FREQREFCLK", - "CMT_PHASER_IN_DB_ICLK", - "CMT_PHASER_IN_DB_ICLKDIV", - "CMT_PHASER_IN_DB_ISERDESRST", - "CMT_PHASER_IN_DB_MEMREFCLK", - "CMT_PHASER_IN_DB_PHASELOCKED", - "CMT_PHASER_IN_DB_PHASEREFCLK", - "CMT_PHASER_IN_DB_RANKSEL0", - "CMT_PHASER_IN_DB_RANKSEL1", - "CMT_PHASER_IN_DB_RANKSELPHY0", - "CMT_PHASER_IN_DB_RANKSELPHY1", - "CMT_PHASER_IN_DB_RCLK", - "CMT_PHASER_IN_DB_RST", - "CMT_PHASER_IN_DB_RSTDQSFIND", - "CMT_PHASER_IN_DB_SCANCLK", - "CMT_PHASER_IN_DB_SCANENB", - "CMT_PHASER_IN_DB_SCANIN", - "CMT_PHASER_IN_DB_SCANMODEB", - "CMT_PHASER_IN_DB_SCANOUT", - "CMT_PHASER_IN_DB_SELCALORSTG1", - "CMT_PHASER_IN_DB_STG1INCDEC", - "CMT_PHASER_IN_DB_STG1LOAD", - "CMT_PHASER_IN_DB_STG1OVERFLOW", - "CMT_PHASER_IN_DB_STG1READ", - "CMT_PHASER_IN_DB_STG1REGL0", - "CMT_PHASER_IN_DB_STG1REGL1", - "CMT_PHASER_IN_DB_STG1REGL2", - "CMT_PHASER_IN_DB_STG1REGL3", - "CMT_PHASER_IN_DB_STG1REGL4", - "CMT_PHASER_IN_DB_STG1REGL5", - "CMT_PHASER_IN_DB_STG1REGL6", - "CMT_PHASER_IN_DB_STG1REGL7", - "CMT_PHASER_IN_DB_STG1REGL8", - "CMT_PHASER_IN_DB_STG1REGR0", - "CMT_PHASER_IN_DB_STG1REGR1", - "CMT_PHASER_IN_DB_STG1REGR2", - "CMT_PHASER_IN_DB_STG1REGR3", - "CMT_PHASER_IN_DB_STG1REGR4", - "CMT_PHASER_IN_DB_STG1REGR5", - "CMT_PHASER_IN_DB_STG1REGR6", - "CMT_PHASER_IN_DB_STG1REGR7", - "CMT_PHASER_IN_DB_STG1REGR8", - "CMT_PHASER_IN_DB_SYNCIN", - "CMT_PHASER_IN_DB_SYSCLK", - "CMT_PHASER_IN_DB_TESTIN0", - "CMT_PHASER_IN_DB_TESTIN1", - "CMT_PHASER_IN_DB_TESTIN10", - "CMT_PHASER_IN_DB_TESTIN11", - "CMT_PHASER_IN_DB_TESTIN12", - "CMT_PHASER_IN_DB_TESTIN13", - "CMT_PHASER_IN_DB_TESTIN2", - "CMT_PHASER_IN_DB_TESTIN3", - "CMT_PHASER_IN_DB_TESTIN4", - "CMT_PHASER_IN_DB_TESTIN5", - "CMT_PHASER_IN_DB_TESTIN6", - "CMT_PHASER_IN_DB_TESTIN7", - "CMT_PHASER_IN_DB_TESTIN8", - "CMT_PHASER_IN_DB_TESTIN9", - "CMT_PHASER_IN_DB_TESTOUT0", - "CMT_PHASER_IN_DB_TESTOUT1", - "CMT_PHASER_IN_DB_TESTOUT2", - "CMT_PHASER_IN_DB_TESTOUT3", - "CMT_PHASER_IN_DB_WRENABLE", - "CMT_PHASER_IN_D_ICLK", - "CMT_PHASER_IN_D_ICLKDIV", - "CMT_PHASER_IN_D_RCLK3", - "CMT_PHASER_IN_D_WRCLK_TOFIFO", - "CMT_PHASER_IN_D_WRENABLE_FIFO", - "CMT_PHASER_OUT_CA_BURSTPENDING", - "CMT_PHASER_OUT_CA_BURSTPENDINGPHY", - "CMT_PHASER_OUT_CA_COARSEENABLE", - "CMT_PHASER_OUT_CA_COARSEINC", - "CMT_PHASER_OUT_CA_COARSEOVERFLOW", - "CMT_PHASER_OUT_CA_COUNTERLOADEN", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL0", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL1", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL2", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL3", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL4", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL5", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL6", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL7", - "CMT_PHASER_OUT_CA_COUNTERLOADVAL8", - "CMT_PHASER_OUT_CA_COUNTERREADEN", - "CMT_PHASER_OUT_CA_COUNTERREADVAL0", - "CMT_PHASER_OUT_CA_COUNTERREADVAL1", - "CMT_PHASER_OUT_CA_COUNTERREADVAL2", - "CMT_PHASER_OUT_CA_COUNTERREADVAL3", - "CMT_PHASER_OUT_CA_COUNTERREADVAL4", - "CMT_PHASER_OUT_CA_COUNTERREADVAL5", - "CMT_PHASER_OUT_CA_COUNTERREADVAL6", - "CMT_PHASER_OUT_CA_COUNTERREADVAL7", - "CMT_PHASER_OUT_CA_COUNTERREADVAL8", - "CMT_PHASER_OUT_CA_CTSBUS0", - "CMT_PHASER_OUT_CA_CTSBUS1", - "CMT_PHASER_OUT_CA_DIVIDERST", - "CMT_PHASER_OUT_CA_DQSBUS0", - "CMT_PHASER_OUT_CA_DQSBUS1", - "CMT_PHASER_OUT_CA_DTSBUS0", - "CMT_PHASER_OUT_CA_DTSBUS1", - "CMT_PHASER_OUT_CA_EDGEADV", - "CMT_PHASER_OUT_CA_ENCALIB0", - "CMT_PHASER_OUT_CA_ENCALIB1", - "CMT_PHASER_OUT_CA_ENCALIBPHY0", - "CMT_PHASER_OUT_CA_ENCALIBPHY1", - "CMT_PHASER_OUT_CA_FINEENABLE", - "CMT_PHASER_OUT_CA_FINEINC", - "CMT_PHASER_OUT_CA_FINEOVERFLOW", - "CMT_PHASER_OUT_CA_FREQREFCLK", - "CMT_PHASER_OUT_CA_MEMREFCLK", - "CMT_PHASER_OUT_CA_OCLK", - "CMT_PHASER_OUT_CA_OCLKDELAYED", - "CMT_PHASER_OUT_CA_OCLKDIV", - "CMT_PHASER_OUT_CA_OSERDESRST", - "CMT_PHASER_OUT_CA_PHASEREFCLK", - "CMT_PHASER_OUT_CA_RDENABLE", - "CMT_PHASER_OUT_CA_RST", - "CMT_PHASER_OUT_CA_SCANCLK", - "CMT_PHASER_OUT_CA_SCANENB", - "CMT_PHASER_OUT_CA_SCANIN", - "CMT_PHASER_OUT_CA_SCANMODEB", - "CMT_PHASER_OUT_CA_SCANOUT", - "CMT_PHASER_OUT_CA_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_CA_SYNCIN", - "CMT_PHASER_OUT_CA_SYSCLK", - "CMT_PHASER_OUT_CA_TESTIN0", - "CMT_PHASER_OUT_CA_TESTIN1", - "CMT_PHASER_OUT_CA_TESTIN10", - "CMT_PHASER_OUT_CA_TESTIN11", - "CMT_PHASER_OUT_CA_TESTIN12", - "CMT_PHASER_OUT_CA_TESTIN13", - "CMT_PHASER_OUT_CA_TESTIN14", - "CMT_PHASER_OUT_CA_TESTIN15", - "CMT_PHASER_OUT_CA_TESTIN2", - "CMT_PHASER_OUT_CA_TESTIN3", - "CMT_PHASER_OUT_CA_TESTIN4", - "CMT_PHASER_OUT_CA_TESTIN5", - "CMT_PHASER_OUT_CA_TESTIN6", - "CMT_PHASER_OUT_CA_TESTIN7", - "CMT_PHASER_OUT_CA_TESTIN8", - "CMT_PHASER_OUT_CA_TESTIN9", - "CMT_PHASER_OUT_CA_TESTOUT0", - "CMT_PHASER_OUT_CA_TESTOUT1", - "CMT_PHASER_OUT_CA_TESTOUT2", - "CMT_PHASER_OUT_CA_TESTOUT3", - "CMT_PHASER_OUT_C_OCLK", - "CMT_PHASER_OUT_C_OCLK1X_90", - "CMT_PHASER_OUT_C_OCLKDIV", - "CMT_PHASER_OUT_C_RDCLK_TOFIFO", - "CMT_PHASER_OUT_C_RDENABLE_TOFIFO", - "CMT_PHASER_OUT_DB_BURSTPENDING", - "CMT_PHASER_OUT_DB_BURSTPENDINGPHY", - "CMT_PHASER_OUT_DB_COARSEENABLE", - "CMT_PHASER_OUT_DB_COARSEINC", - "CMT_PHASER_OUT_DB_COARSEOVERFLOW", - "CMT_PHASER_OUT_DB_COUNTERLOADEN", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL0", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL1", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL2", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL3", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL4", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL5", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL6", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL7", - "CMT_PHASER_OUT_DB_COUNTERLOADVAL8", - "CMT_PHASER_OUT_DB_COUNTERREADEN", - "CMT_PHASER_OUT_DB_COUNTERREADVAL0", - "CMT_PHASER_OUT_DB_COUNTERREADVAL1", - "CMT_PHASER_OUT_DB_COUNTERREADVAL2", - "CMT_PHASER_OUT_DB_COUNTERREADVAL3", - "CMT_PHASER_OUT_DB_COUNTERREADVAL4", - "CMT_PHASER_OUT_DB_COUNTERREADVAL5", - "CMT_PHASER_OUT_DB_COUNTERREADVAL6", - "CMT_PHASER_OUT_DB_COUNTERREADVAL7", - "CMT_PHASER_OUT_DB_COUNTERREADVAL8", - "CMT_PHASER_OUT_DB_CTSBUS0", - "CMT_PHASER_OUT_DB_CTSBUS1", - "CMT_PHASER_OUT_DB_DIVIDERST", - "CMT_PHASER_OUT_DB_DQSBUS0", - "CMT_PHASER_OUT_DB_DQSBUS1", - "CMT_PHASER_OUT_DB_DTSBUS0", - "CMT_PHASER_OUT_DB_DTSBUS1", - "CMT_PHASER_OUT_DB_EDGEADV", - "CMT_PHASER_OUT_DB_ENCALIB0", - "CMT_PHASER_OUT_DB_ENCALIB1", - "CMT_PHASER_OUT_DB_ENCALIBPHY0", - "CMT_PHASER_OUT_DB_ENCALIBPHY1", - "CMT_PHASER_OUT_DB_FINEENABLE", - "CMT_PHASER_OUT_DB_FINEINC", - "CMT_PHASER_OUT_DB_FINEOVERFLOW", - "CMT_PHASER_OUT_DB_FREQREFCLK", - "CMT_PHASER_OUT_DB_MEMREFCLK", - "CMT_PHASER_OUT_DB_OCLK", - "CMT_PHASER_OUT_DB_OCLKDELAYED", - "CMT_PHASER_OUT_DB_OCLKDIV", - "CMT_PHASER_OUT_DB_OSERDESRST", - "CMT_PHASER_OUT_DB_PHASEREFCLK", - "CMT_PHASER_OUT_DB_RDENABLE", - "CMT_PHASER_OUT_DB_RST", - "CMT_PHASER_OUT_DB_SCANCLK", - "CMT_PHASER_OUT_DB_SCANENB", - "CMT_PHASER_OUT_DB_SCANIN", - "CMT_PHASER_OUT_DB_SCANMODEB", - "CMT_PHASER_OUT_DB_SCANOUT", - "CMT_PHASER_OUT_DB_SELFINEOCLKDELAY", - "CMT_PHASER_OUT_DB_SYNCIN", - "CMT_PHASER_OUT_DB_SYSCLK", - "CMT_PHASER_OUT_DB_TESTIN0", - "CMT_PHASER_OUT_DB_TESTIN1", - "CMT_PHASER_OUT_DB_TESTIN10", - "CMT_PHASER_OUT_DB_TESTIN11", - "CMT_PHASER_OUT_DB_TESTIN12", - "CMT_PHASER_OUT_DB_TESTIN13", - "CMT_PHASER_OUT_DB_TESTIN14", - "CMT_PHASER_OUT_DB_TESTIN15", - "CMT_PHASER_OUT_DB_TESTIN2", - "CMT_PHASER_OUT_DB_TESTIN3", - "CMT_PHASER_OUT_DB_TESTIN4", - "CMT_PHASER_OUT_DB_TESTIN5", - "CMT_PHASER_OUT_DB_TESTIN6", - "CMT_PHASER_OUT_DB_TESTIN7", - "CMT_PHASER_OUT_DB_TESTIN8", - "CMT_PHASER_OUT_DB_TESTIN9", - "CMT_PHASER_OUT_DB_TESTOUT0", - "CMT_PHASER_OUT_DB_TESTOUT1", - "CMT_PHASER_OUT_DB_TESTOUT2", - "CMT_PHASER_OUT_DB_TESTOUT3", - "CMT_PHASER_OUT_D_OCLK", - "CMT_PHASER_OUT_D_OCLK1X_90", - "CMT_PHASER_OUT_D_OCLKDIV", - "CMT_PHASER_OUT_D_RDCLK_TOFIFO", - "CMT_PHASER_OUT_D_RDENABLE_TOFIFO", - "CMT_PHASER_REF_CLKIN", - "CMT_PHASER_REF_CLKOUT", - "CMT_PHASER_REF_CLKOUT_TOHCLK", - "CMT_PHASER_REF_LOCKED", - "CMT_PHASER_REF_PWRDWN", - "CMT_PHASER_REF_RST", - "CMT_PHASER_REF_TESTIN0", - "CMT_PHASER_REF_TESTIN1", - "CMT_PHASER_REF_TESTIN2", - "CMT_PHASER_REF_TESTIN3", - "CMT_PHASER_REF_TESTIN4", - "CMT_PHASER_REF_TESTIN5", - "CMT_PHASER_REF_TESTIN6", - "CMT_PHASER_REF_TESTIN7", - "CMT_PHASER_REF_TESTOUT0", - "CMT_PHASER_REF_TESTOUT1", - "CMT_PHASER_REF_TESTOUT2", - "CMT_PHASER_REF_TESTOUT3", - "CMT_PHASER_REF_TESTOUT4", - "CMT_PHASER_REF_TESTOUT5", - "CMT_PHASER_REF_TESTOUT6", - "CMT_PHASER_REF_TESTOUT7", - "CMT_PHASER_REF_TMUXOUT", - "CMT_PHASER_REF_TMUXOUT_TOHCLK", - "CMT_PHASER_TOP_SYNC_BB", - "CMT_PHASER_UP_BUFMRCE_CE0", - "CMT_PHASER_UP_BUFMRCE_CE1", - "CMT_PHASER_UP_DQS_TO_PHASER_C", - "CMT_PHASER_UP_DQS_TO_PHASER_D", - "CMT_PHASER_UP_PHASERREF0", - "CMT_PHASER_UP_PHASERREF1", - "CMT_PHASER_UP_PHASERREF_ABOVE0", - "CMT_PHASER_UP_PHASERREF_ABOVE1", - "CMT_PHASER_UP_PHASERREF_BELOW0", - "CMT_PHASER_UP_PHASERREF_BELOW1", - "CMT_PHY_CONTROL_AUXOUTPUT0", - "CMT_PHY_CONTROL_AUXOUTPUT1", - "CMT_PHY_CONTROL_AUXOUTPUT2", - "CMT_PHY_CONTROL_AUXOUTPUT3", - "CMT_PHY_CONTROL_ECALIB0", - "CMT_PHY_CONTROL_ECALIB1", - "CMT_PHY_CONTROL_IBURSTPENDING0", - "CMT_PHY_CONTROL_IBURSTPENDING1", - "CMT_PHY_CONTROL_IBURSTPENDING2", - "CMT_PHY_CONTROL_IBURSTPENDING3", - "CMT_PHY_CONTROL_INBURSTPENDING0", - "CMT_PHY_CONTROL_INBURSTPENDING1", - "CMT_PHY_CONTROL_INBURSTPENDING2", - "CMT_PHY_CONTROL_INBURSTPENDING3", - "CMT_PHY_CONTROL_INRANKA0", - "CMT_PHY_CONTROL_INRANKA1", - "CMT_PHY_CONTROL_INRANKB0", - "CMT_PHY_CONTROL_INRANKB1", - "CMT_PHY_CONTROL_INRANKC0", - "CMT_PHY_CONTROL_INRANKC1", - "CMT_PHY_CONTROL_INRANKD0", - "CMT_PHY_CONTROL_INRANKD1", - "CMT_PHY_CONTROL_IRANKA0", - "CMT_PHY_CONTROL_IRANKA1", - "CMT_PHY_CONTROL_IRANKB0", - "CMT_PHY_CONTROL_IRANKB1", - "CMT_PHY_CONTROL_IRANKC0", - "CMT_PHY_CONTROL_IRANKC1", - "CMT_PHY_CONTROL_IRANKD0", - "CMT_PHY_CONTROL_IRANKD1", - "CMT_PHY_CONTROL_MEMREFCLK", - "CMT_PHY_CONTROL_OBURSTPENDING0", - "CMT_PHY_CONTROL_OBURSTPENDING1", - "CMT_PHY_CONTROL_OBURSTPENDING2", - "CMT_PHY_CONTROL_OBURSTPENDING3", - "CMT_PHY_CONTROL_OUTBURSTPENDING0", - "CMT_PHY_CONTROL_OUTBURSTPENDING1", - "CMT_PHY_CONTROL_OUTBURSTPENDING2", - "CMT_PHY_CONTROL_OUTBURSTPENDING3", - "CMT_PHY_CONTROL_PCENABLECALIB0", - "CMT_PHY_CONTROL_PCENABLECALIB1", - "CMT_PHY_CONTROL_PHYCLK", - "CMT_PHY_CONTROL_PHYCTLALMOSTFULL", - "CMT_PHY_CONTROL_PHYCTLEMPTY", - "CMT_PHY_CONTROL_PHYCTLFULL", - "CMT_PHY_CONTROL_PHYCTLMSTREMPTY", - "CMT_PHY_CONTROL_PHYCTLREADY", - "CMT_PHY_CONTROL_PHYCTLWD0", - "CMT_PHY_CONTROL_PHYCTLWD1", - "CMT_PHY_CONTROL_PHYCTLWD10", - "CMT_PHY_CONTROL_PHYCTLWD11", - "CMT_PHY_CONTROL_PHYCTLWD12", - "CMT_PHY_CONTROL_PHYCTLWD13", - "CMT_PHY_CONTROL_PHYCTLWD14", - "CMT_PHY_CONTROL_PHYCTLWD15", - "CMT_PHY_CONTROL_PHYCTLWD16", - "CMT_PHY_CONTROL_PHYCTLWD17", - "CMT_PHY_CONTROL_PHYCTLWD18", - "CMT_PHY_CONTROL_PHYCTLWD19", - "CMT_PHY_CONTROL_PHYCTLWD2", - "CMT_PHY_CONTROL_PHYCTLWD20", - "CMT_PHY_CONTROL_PHYCTLWD21", - "CMT_PHY_CONTROL_PHYCTLWD22", - "CMT_PHY_CONTROL_PHYCTLWD23", - "CMT_PHY_CONTROL_PHYCTLWD24", - "CMT_PHY_CONTROL_PHYCTLWD25", - "CMT_PHY_CONTROL_PHYCTLWD26", - "CMT_PHY_CONTROL_PHYCTLWD27", - "CMT_PHY_CONTROL_PHYCTLWD28", - "CMT_PHY_CONTROL_PHYCTLWD29", - "CMT_PHY_CONTROL_PHYCTLWD3", - "CMT_PHY_CONTROL_PHYCTLWD30", - "CMT_PHY_CONTROL_PHYCTLWD31", - "CMT_PHY_CONTROL_PHYCTLWD4", - "CMT_PHY_CONTROL_PHYCTLWD5", - "CMT_PHY_CONTROL_PHYCTLWD6", - "CMT_PHY_CONTROL_PHYCTLWD7", - "CMT_PHY_CONTROL_PHYCTLWD8", - "CMT_PHY_CONTROL_PHYCTLWD9", - "CMT_PHY_CONTROL_PHYCTLWRENABLE", - "CMT_PHY_CONTROL_PLLLOCK", - "CMT_PHY_CONTROL_READCALIBENABLE", - "CMT_PHY_CONTROL_REFDLLLOCK", - "CMT_PHY_CONTROL_RESET", - "CMT_PHY_CONTROL_SCANENABLEN", - "CMT_PHY_CONTROL_SYNCIN", - "CMT_PHY_CONTROL_TESTINPUT0", - "CMT_PHY_CONTROL_TESTINPUT1", - "CMT_PHY_CONTROL_TESTINPUT10", - "CMT_PHY_CONTROL_TESTINPUT11", - "CMT_PHY_CONTROL_TESTINPUT12", - "CMT_PHY_CONTROL_TESTINPUT13", - "CMT_PHY_CONTROL_TESTINPUT14", - "CMT_PHY_CONTROL_TESTINPUT15", - "CMT_PHY_CONTROL_TESTINPUT2", - "CMT_PHY_CONTROL_TESTINPUT3", - "CMT_PHY_CONTROL_TESTINPUT4", - "CMT_PHY_CONTROL_TESTINPUT5", - "CMT_PHY_CONTROL_TESTINPUT6", - "CMT_PHY_CONTROL_TESTINPUT7", - "CMT_PHY_CONTROL_TESTINPUT8", - "CMT_PHY_CONTROL_TESTINPUT9", - "CMT_PHY_CONTROL_TESTOUTPUT0", - "CMT_PHY_CONTROL_TESTOUTPUT1", - "CMT_PHY_CONTROL_TESTOUTPUT10", - "CMT_PHY_CONTROL_TESTOUTPUT11", - "CMT_PHY_CONTROL_TESTOUTPUT12", - "CMT_PHY_CONTROL_TESTOUTPUT13", - "CMT_PHY_CONTROL_TESTOUTPUT14", - "CMT_PHY_CONTROL_TESTOUTPUT15", - "CMT_PHY_CONTROL_TESTOUTPUT2", - "CMT_PHY_CONTROL_TESTOUTPUT3", - "CMT_PHY_CONTROL_TESTOUTPUT4", - "CMT_PHY_CONTROL_TESTOUTPUT5", - "CMT_PHY_CONTROL_TESTOUTPUT6", - "CMT_PHY_CONTROL_TESTOUTPUT7", - "CMT_PHY_CONTROL_TESTOUTPUT8", - "CMT_PHY_CONTROL_TESTOUTPUT9", - "CMT_PHY_CONTROL_TESTSELECT0", - "CMT_PHY_CONTROL_TESTSELECT1", - "CMT_PHY_CONTROL_TESTSELECT2", - "CMT_PHY_CONTROL_WRITECALIBENABLE", - "CMT_R_TOP_UPPER_B_CLKFBIN", - "CMT_R_TOP_UPPER_B_CLKIN1", - "CMT_R_TOP_UPPER_B_CLKIN2", - "CMT_R_TOP_UPPER_B_CLKINT_2", - "CMT_R_TOP_UPPER_B_CLKINT_3", - "CMT_R_TOP_UPPER_B_CLKPLL0", - "CMT_R_TOP_UPPER_B_CLKPLL1", - "CMT_R_TOP_UPPER_B_CLKPLL2", - "CMT_R_TOP_UPPER_B_CLKPLL3", - "CMT_R_TOP_UPPER_B_CLKPLL4", - "CMT_R_TOP_UPPER_B_CLKPLL5", - "CMT_R_TOP_UPPER_B_CLKPLL6", - "CMT_R_TOP_UPPER_B_CLKPLL7", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_BYP0_11", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_10", - "CMT_TOP_BYP1_11", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP1_9", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_10", - "CMT_TOP_BYP2_11", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_10", - "CMT_TOP_BYP3_11", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP3_9", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_10", - "CMT_TOP_BYP4_11", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP4_9", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_10", - "CMT_TOP_BYP5_11", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP5_9", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_10", - "CMT_TOP_BYP6_11", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP6_9", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_10", - "CMT_TOP_BYP7_11", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_BYP7_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK0_9", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_10", - "CMT_TOP_CLK1_11", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CLK1_9", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL0_9", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_CTRL1_11", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_CTRL1_9", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A0_9", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_10", - "CMT_TOP_EE2A1_11", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A1_9", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_10", - "CMT_TOP_EE2A2_11", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A2_9", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_10", - "CMT_TOP_EE2A3_11", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_10", - "CMT_TOP_EE4A0_11", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A0_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_EE4A1_11", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A1_9", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_10", - "CMT_TOP_EE4A2_11", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A2_9", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_EE4A3_11", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_10", - "CMT_TOP_EE4B0_11", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B0_9", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_10", - "CMT_TOP_EE4B1_11", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B1_9", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_10", - "CMT_TOP_EE4B2_11", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B2_9", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_10", - "CMT_TOP_EE4B3_11", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4B3_9", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_10", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C0_9", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_10", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C2_9", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_EE4C3_11", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EE4C3_9", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_10", - "CMT_TOP_FAN0_11", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN0_9", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_10", - "CMT_TOP_FAN1_11", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN1_9", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_10", - "CMT_TOP_FAN2_11", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN2_9", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN3_9", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_10", - "CMT_TOP_FAN4_11", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN4_9", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_10", - "CMT_TOP_FAN5_11", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN5_9", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_10", - "CMT_TOP_FAN6_11", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN6_9", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_FAN7_11", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_FAN7_9", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_ICLKDIV_2", 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"CMT_TOP_IMUX39_11", - "CMT_TOP_IMUX39_2", - "CMT_TOP_IMUX39_3", - "CMT_TOP_IMUX39_4", - "CMT_TOP_IMUX39_5", - "CMT_TOP_IMUX39_6", - "CMT_TOP_IMUX39_7", - "CMT_TOP_IMUX39_8", - "CMT_TOP_IMUX39_9", - "CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_10", - "CMT_TOP_IMUX3_11", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX3_9", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX40_9", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_10", - "CMT_TOP_IMUX41_11", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX41_9", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX42_11", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX42_9", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX43_9", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_10", - "CMT_TOP_IMUX44_11", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX45_11", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX45_9", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_10", - "CMT_TOP_IMUX46_11", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX46_9", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX47_11", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX47_9", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_10", - "CMT_TOP_IMUX4_11", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX4_9", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX5_11", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_10", - "CMT_TOP_IMUX6_11", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX6_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_10", - "CMT_TOP_IMUX7_11", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX7_9", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_10", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX9_9", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_10", - "CMT_TOP_LH10_11", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH10_9", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_10", - "CMT_TOP_LH11_11", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH11_9", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_10", - "CMT_TOP_LH12_11", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH12_9", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_10", - "CMT_TOP_LH1_11", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH1_9", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_10", - "CMT_TOP_LH2_11", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH2_9", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_10", - "CMT_TOP_LH3_11", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH3_9", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_10", - "CMT_TOP_LH4_11", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH4_9", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_10", - "CMT_TOP_LH5_11", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH5_9", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_10", - "CMT_TOP_LH6_11", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH6_9", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_10", - "CMT_TOP_LH7_11", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH7_9", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_10", - "CMT_TOP_LH8_11", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH8_9", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_10", - "CMT_TOP_LH9_11", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LH9_9", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_10", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_10", - "CMT_TOP_NE2A0_11", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A0_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_10", - "CMT_TOP_NE2A1_11", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_10", - "CMT_TOP_NE2A2_11", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A2_9", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_10", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_10", - "CMT_TOP_NE4C0_11", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_9", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_NE4C1_11", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C1_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_10", - "CMT_TOP_NE4C2_11", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C2_9", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_10", - "CMT_TOP_NE4C3_11", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NE4C3_9", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_10", - "CMT_TOP_NW2A0_11", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A0_9", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_10", - "CMT_TOP_NW2A1_11", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_10", - "CMT_TOP_NW2A2_11", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A2_9", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW2A3_11", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW2A3_9", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_10", - "CMT_TOP_NW4A0_11", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_10", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A1_9", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW4A2_11", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A2_9", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_10", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_10", - "CMT_TOP_NW4END0_11", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END0_9", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_10", - "CMT_TOP_NW4END1_11", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END1_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_10", - "CMT_TOP_NW4END2_11", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END2_9", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4END3_11", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_NW4END3_9", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_10", - "CMT_TOP_OCLK_11", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_OCLK_9", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_10", - "CMT_TOP_SE2A0_11", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A0_9", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_10", - "CMT_TOP_SE2A1_11", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A1_9", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_10", - "CMT_TOP_SE2A2_11", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_10", - "CMT_TOP_SE2A3_11", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE2A3_9", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_10", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C0_9", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_10", - "CMT_TOP_SE4C1_11", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C1_9", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_10", - "CMT_TOP_SE4C2_11", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C2_9", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_10", - "CMT_TOP_SE4C3_11", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SE4C3_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SW2A0_11", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A0_9", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_10", - "CMT_TOP_SW2A1_11", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A1_9", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_10", - "CMT_TOP_SW2A2_11", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A2_9", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_10", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW2A3_9", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_SW4A0_11", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_10", - "CMT_TOP_SW4A1_11", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_10", - "CMT_TOP_SW4A2_11", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A2_9", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_10", - "CMT_TOP_SW4A3_11", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4A3_9", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_10", - "CMT_TOP_SW4END0_11", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END0_9", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_10", - "CMT_TOP_SW4END1_11", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END1_9", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_SW4END2_11", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END2_9", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_10", - "CMT_TOP_SW4END3_11", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_SW4END3_9", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_10", - "CMT_TOP_WL1END0_11", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END0_9", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_10", - "CMT_TOP_WL1END1_11", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END1_9", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_10", - "CMT_TOP_WL1END2_11", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END2_9", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_10", - "CMT_TOP_WL1END3_11", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WL1END3_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END0_11", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END1_9", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_10", - "CMT_TOP_WR1END2_11", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END2_9", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_10", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WR1END3_9", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_10", - "CMT_TOP_WW2A0_11", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A0_9", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_10", - "CMT_TOP_WW2A1_11", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A1_9", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_10", - "CMT_TOP_WW2A2_11", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A2_9", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_10", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2A3_9", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_10", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_10", - "CMT_TOP_WW2END1_11", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END1_9", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_10", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_10", - "CMT_TOP_WW2END3_11", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW2END3_9", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_10", - "CMT_TOP_WW4A0_11", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_10", - "CMT_TOP_WW4A1_11", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_10", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A2_9", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_10", - "CMT_TOP_WW4A3_11", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4A3_9", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_10", - "CMT_TOP_WW4B0_11", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_9", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_10", - "CMT_TOP_WW4B1_11", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_10", - "CMT_TOP_WW4B2_11", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_10", - "CMT_TOP_WW4B3_11", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4B3_9", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_10", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C0_9", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C1_9", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_10", - "CMT_TOP_WW4C2_11", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C2_9", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4C3_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END0_9", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_10", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END1_9", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END2_9", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_10", - "CMT_TOP_WW4END3_11", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4END3_9", - "PLLOUT_CLK_FREQ_BB_REBUFIN0", - "PLLOUT_CLK_FREQ_BB_REBUFIN1", - "PLLOUT_CLK_FREQ_BB_REBUFIN2", - "PLLOUT_CLK_FREQ_BB_REBUFIN3", - "PLLOUT_CLK_FREQ_BB_REBUFOUT0", - "PLLOUT_CLK_FREQ_BB_REBUFOUT1", - "PLLOUT_CLK_FREQ_BB_REBUFOUT2", - "PLLOUT_CLK_FREQ_BB_REBUFOUT3", - "PLL_CLK_FREQBB_REBUFOUT0", - "PLL_CLK_FREQBB_REBUFOUT1", - "PLL_CLK_FREQBB_REBUFOUT2", - "PLL_CLK_FREQBB_REBUFOUT3" - ] + "wires": { + "CMT_FREQ_BB_PREF_IN0": null, + "CMT_FREQ_BB_PREF_IN1": null, + "CMT_FREQ_BB_PREF_IN2": null, + "CMT_FREQ_BB_PREF_IN3": null, + "CMT_FREQ_PHASER_REFMUX_0": null, + "CMT_FREQ_PHASER_REFMUX_1": null, + "CMT_FREQ_PHASER_REFMUX_2": null, + "CMT_PHASERD_CTSBUS0": null, + "CMT_PHASERD_CTSBUS1": null, + "CMT_PHASERD_DQSBUS0": null, + "CMT_PHASERD_DQSBUS1": null, + "CMT_PHASERD_DTSBUS0": null, + "CMT_PHASERD_DTSBUS1": null, + "CMT_PHASERREF_PHASERIN_C": null, + "CMT_PHASERREF_PHASERIN_D": null, + "CMT_PHASERREF_PHASEROUT_C": null, + "CMT_PHASERREF_PHASEROUT_D": null, + "CMT_PHASERTOP_PHYCTLEMPTY": null, + "CMT_PHASERTOP_PHYCTLMSTREMPTY": null, + "CMT_PHASER_C_ICLKDIV_TOIOI": null, + "CMT_PHASER_C_ICLK_TOIOI": null, + "CMT_PHASER_C_OCLK90_TOIOI": null, + "CMT_PHASER_C_OCLKDIV_TOIOI": null, + "CMT_PHASER_C_OCLK_TOIOI": null, + "CMT_PHASER_IN_CA_BURSTPENDING": null, + "CMT_PHASER_IN_CA_BURSTPENDINGPHY": null, + "CMT_PHASER_IN_CA_COUNTERLOADEN": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL0": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL1": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL2": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL3": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL4": null, + "CMT_PHASER_IN_CA_COUNTERLOADVAL5": null, + "CMT_PHASER_IN_CA_COUNTERREADEN": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL0": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL1": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL2": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL3": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL4": null, + "CMT_PHASER_IN_CA_COUNTERREADVAL5": null, + "CMT_PHASER_IN_CA_DIVIDERST": null, + "CMT_PHASER_IN_CA_DQSFOUND": null, + "CMT_PHASER_IN_CA_DQSOUTOFRANGE": null, + "CMT_PHASER_IN_CA_EDGEADV": null, + "CMT_PHASER_IN_CA_ENCALIB0": null, + "CMT_PHASER_IN_CA_ENCALIB1": null, + "CMT_PHASER_IN_CA_ENCALIBPHY0": null, + "CMT_PHASER_IN_CA_ENCALIBPHY1": null, + "CMT_PHASER_IN_CA_ENSTG1": null, + "CMT_PHASER_IN_CA_ENSTG1ADJUSTB": null, + "CMT_PHASER_IN_CA_FINEENABLE": null, + "CMT_PHASER_IN_CA_FINEINC": null, + "CMT_PHASER_IN_CA_FINEOVERFLOW": null, + "CMT_PHASER_IN_CA_FREQREFCLK": null, + "CMT_PHASER_IN_CA_ICLK": null, + "CMT_PHASER_IN_CA_ICLKDIV": null, + "CMT_PHASER_IN_CA_ISERDESRST": null, + "CMT_PHASER_IN_CA_MEMREFCLK": null, + "CMT_PHASER_IN_CA_PHASELOCKED": null, + "CMT_PHASER_IN_CA_PHASEREFCLK": null, + "CMT_PHASER_IN_CA_RANKSEL0": null, + "CMT_PHASER_IN_CA_RANKSEL1": null, + "CMT_PHASER_IN_CA_RANKSELPHY0": null, + "CMT_PHASER_IN_CA_RANKSELPHY1": null, + "CMT_PHASER_IN_CA_RCLK": null, + "CMT_PHASER_IN_CA_RST": null, + "CMT_PHASER_IN_CA_RSTDQSFIND": null, + "CMT_PHASER_IN_CA_SCANCLK": null, + "CMT_PHASER_IN_CA_SCANENB": null, + "CMT_PHASER_IN_CA_SCANIN": null, + "CMT_PHASER_IN_CA_SCANMODEB": null, + "CMT_PHASER_IN_CA_SCANOUT": null, + "CMT_PHASER_IN_CA_SELCALORSTG1": null, + "CMT_PHASER_IN_CA_STG1INCDEC": null, + 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"CMT_PHASER_OUT_D_OCLK1X_90": null, + "CMT_PHASER_OUT_D_OCLKDIV": null, + "CMT_PHASER_OUT_D_RDCLK_TOFIFO": null, + "CMT_PHASER_OUT_D_RDENABLE_TOFIFO": null, + "CMT_PHASER_REF_CLKIN": null, + "CMT_PHASER_REF_CLKOUT": null, + "CMT_PHASER_REF_CLKOUT_TOHCLK": null, + "CMT_PHASER_REF_LOCKED": null, + "CMT_PHASER_REF_PWRDWN": null, + "CMT_PHASER_REF_RST": null, + "CMT_PHASER_REF_TESTIN0": null, + "CMT_PHASER_REF_TESTIN1": null, + "CMT_PHASER_REF_TESTIN2": null, + "CMT_PHASER_REF_TESTIN3": null, + "CMT_PHASER_REF_TESTIN4": null, + "CMT_PHASER_REF_TESTIN5": null, + "CMT_PHASER_REF_TESTIN6": null, + "CMT_PHASER_REF_TESTIN7": null, + "CMT_PHASER_REF_TESTOUT0": null, + "CMT_PHASER_REF_TESTOUT1": null, + "CMT_PHASER_REF_TESTOUT2": null, + "CMT_PHASER_REF_TESTOUT3": null, + "CMT_PHASER_REF_TESTOUT4": null, + "CMT_PHASER_REF_TESTOUT5": null, + "CMT_PHASER_REF_TESTOUT6": null, + "CMT_PHASER_REF_TESTOUT7": null, + "CMT_PHASER_REF_TMUXOUT": null, + "CMT_PHASER_REF_TMUXOUT_TOHCLK": null, + "CMT_PHASER_TOP_SYNC_BB": null, + "CMT_PHASER_UP_BUFMRCE_CE0": null, + "CMT_PHASER_UP_BUFMRCE_CE1": null, + "CMT_PHASER_UP_DQS_TO_PHASER_C": null, + "CMT_PHASER_UP_DQS_TO_PHASER_D": null, + "CMT_PHASER_UP_PHASERREF0": null, + "CMT_PHASER_UP_PHASERREF1": null, + "CMT_PHASER_UP_PHASERREF_ABOVE0": null, + "CMT_PHASER_UP_PHASERREF_ABOVE1": null, + "CMT_PHASER_UP_PHASERREF_BELOW0": null, + "CMT_PHASER_UP_PHASERREF_BELOW1": null, + "CMT_PHY_CONTROL_AUXOUTPUT0": { + "cap": "0.200", + "res": "0.000" + }, + "CMT_PHY_CONTROL_AUXOUTPUT1": { + "cap": "0.200", + "res": "0.000" + }, + "CMT_PHY_CONTROL_AUXOUTPUT2": { + "cap": "0.200", + "res": "0.000" + }, + "CMT_PHY_CONTROL_AUXOUTPUT3": { + "cap": "0.200", + "res": "0.000" + }, + "CMT_PHY_CONTROL_ECALIB0": null, + "CMT_PHY_CONTROL_ECALIB1": null, + "CMT_PHY_CONTROL_IBURSTPENDING0": null, + "CMT_PHY_CONTROL_IBURSTPENDING1": null, + "CMT_PHY_CONTROL_IBURSTPENDING2": null, + "CMT_PHY_CONTROL_IBURSTPENDING3": null, + "CMT_PHY_CONTROL_INBURSTPENDING0": { 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+ "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_9": { + "cap": "78.000", + "res": "317.510" + }, + "PLLOUT_CLK_FREQ_BB_REBUFIN0": null, + "PLLOUT_CLK_FREQ_BB_REBUFIN1": null, + "PLLOUT_CLK_FREQ_BB_REBUFIN2": null, + "PLLOUT_CLK_FREQ_BB_REBUFIN3": null, + "PLLOUT_CLK_FREQ_BB_REBUFOUT0": null, + "PLLOUT_CLK_FREQ_BB_REBUFOUT1": null, + "PLLOUT_CLK_FREQ_BB_REBUFOUT2": null, + "PLLOUT_CLK_FREQ_BB_REBUFOUT3": null, + "PLL_CLK_FREQBB_REBUFOUT0": null, + "PLL_CLK_FREQBB_REBUFOUT1": null, + "PLL_CLK_FREQBB_REBUFOUT2": null, + "PLL_CLK_FREQBB_REBUFOUT3": null + } } diff --git a/kintex7/tile_type_CMT_TOP_R_UPPER_T.json b/kintex7/tile_type_CMT_TOP_R_UPPER_T.json index 5219792..3c84d33 100644 --- a/kintex7/tile_type_CMT_TOP_R_UPPER_T.json +++ b/kintex7/tile_type_CMT_TOP_R_UPPER_T.json @@ -2,1087 +2,4262 @@ "pips": { "CMT_TOP_R_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI->>CMT_TOP_ICLKDIV_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.101", + "0.116", + "0.164", + "0.188" + ], + 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"0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B2_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO5" }, "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO6->>CMT_TOP_LOGIC_OUTS_L_B16_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO6" }, "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO7->>CMT_TOP_LOGIC_OUTS_L_B10_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B10_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO7" }, "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO8->>CMT_TOP_LOGIC_OUTS_L_B19_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B19_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO8" }, "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DO9->>CMT_TOP_LOGIC_OUTS_L_B5_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B5_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DO9" }, "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DRDY->>CMT_TOP_LOGIC_OUTS_L_B16_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B16_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_DRDY" }, "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_LOCKED->>CMT_TOP_LOGIC_OUTS_L_B21_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "dst_wire": "CMT_TOP_LOGIC_OUTS_L_B21_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "412.5" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED" }, "CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT->>CMT_TOP_R_UPPER_T_CLKPLL7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_R_UPPER_T_CLKPLL7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT" }, "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS->>CMT_TOP_R_UPPER_T_FREQ_BB0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB0_NS" }, "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB0_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS0", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB0_NS" }, "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS->>CMT_TOP_R_UPPER_T_FREQ_BB1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB1_NS" }, "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB1_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS1", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB1_NS" }, "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS->>CMT_TOP_R_UPPER_T_FREQ_BB2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB2_NS" }, "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB2_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS2", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB2_NS" }, "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS->>CMT_TOP_R_UPPER_T_FREQ_BB3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "CMT_TOP_R_UPPER_T_FREQ_BB3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "PLL_CLK_FREQ_BB3_NS" }, "CMT_TOP_R_UPPER_T.PLL_CLK_FREQ_BB3_NS<<->>PLL_CLK_FREQ_BB_BUFOUT_NS3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "PLL_CLK_FREQ_BB_BUFOUT_NS3", "is_directional": "0", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "PLL_CLK_FREQ_BB3_NS" } }, @@ -1091,160 +4266,1546 @@ "name": "X0Y0", "prefix": "PLLE2_ADV", "site_pins": { - "CLKFBIN": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CLKFBOUT": "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "CLKIN1": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "CLKIN2": "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "CLKINSEL": "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "CLKOUT0": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "CLKOUT1": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "CLKOUT2": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CLKOUT3": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "CLKOUT4": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "CLKOUT5": "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "DADDR0": "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "DADDR1": "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "DADDR2": "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "DADDR3": "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "DADDR4": "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "DADDR5": "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "DADDR6": "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "DCLK": "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "DEN": "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "DI0": "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "DI1": "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "DI10": "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "DI11": "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "DI12": "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "DI13": "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "DI14": "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "DI15": "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "DI2": "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "DI3": "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "DI4": "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "DI5": "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "DI6": "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "DI7": "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "DI8": "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "DI9": "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "DO0": "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "DO1": "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "DO10": "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "DO11": "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "DO12": "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "DO13": "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "DO14": "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "DO15": "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "DO2": "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "DO3": "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "DO4": "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "DO5": "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "DO6": "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "DO7": "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "DO8": "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "DO9": "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "DRDY": "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "DWE": "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "LOCKED": "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "PWRDWN": "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "RST": "CMT_TOP_R_UPPER_T_PLLE2_RST", - "TESTIN0": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "TESTIN1": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "TESTIN10": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "TESTIN11": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "TESTIN12": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "TESTIN13": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "TESTIN14": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "TESTIN15": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "TESTIN16": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "TESTIN17": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "TESTIN18": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "TESTIN19": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "TESTIN2": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "TESTIN20": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "TESTIN21": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "TESTIN22": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "TESTIN23": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "TESTIN24": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "TESTIN25": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "TESTIN26": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", - "TESTIN27": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", - "TESTIN28": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", - "TESTIN29": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", - "TESTIN3": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", - "TESTIN30": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", - "TESTIN31": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", - "TESTIN4": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", - "TESTIN5": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", - "TESTIN6": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", - "TESTIN7": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", - "TESTIN8": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", - "TESTIN9": "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", - "TESTOUT0": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", - "TESTOUT1": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", - "TESTOUT10": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", - "TESTOUT11": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", - "TESTOUT12": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", - "TESTOUT13": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", - "TESTOUT14": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", - "TESTOUT15": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", - "TESTOUT16": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", - "TESTOUT17": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", - "TESTOUT18": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", - "TESTOUT19": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", - "TESTOUT2": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", - "TESTOUT20": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", - "TESTOUT21": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", - "TESTOUT22": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", - "TESTOUT23": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", - "TESTOUT24": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", - "TESTOUT25": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", - "TESTOUT26": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", - "TESTOUT27": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", - "TESTOUT28": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", - "TESTOUT29": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", - "TESTOUT3": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", - "TESTOUT30": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", - "TESTOUT31": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", - "TESTOUT32": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", - "TESTOUT33": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", - "TESTOUT34": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", - "TESTOUT35": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", - "TESTOUT36": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", - "TESTOUT37": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", - "TESTOUT38": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", - "TESTOUT39": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", - "TESTOUT4": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", - "TESTOUT40": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", - "TESTOUT41": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", - "TESTOUT42": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", - "TESTOUT43": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", - "TESTOUT44": "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", - "TESTOUT45": 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"CMT_PLL_PHASERD_DQSBUS0", - "CMT_PLL_PHASERD_DQSBUS1", - "CMT_PLL_PHASERD_DTSBUS0", - "CMT_PLL_PHASERD_DTSBUS1", - "CMT_PLL_PHASERREF0", - "CMT_PLL_PHASERREF1", - "CMT_PLL_PHASERREF_ABOVE0", - "CMT_PLL_PHASERREF_ABOVE1", - "CMT_PLL_PHASERREF_BELOW0", - "CMT_PLL_PHASERREF_BELOW1", - "CMT_PLL_PHASER_IN_D_ICLK", - "CMT_PLL_PHASER_IN_D_ICLKDIV", - "CMT_PLL_PHASER_OUT_D_OCLK", - "CMT_PLL_PHASER_OUT_D_OCLK1X_90", - "CMT_PLL_PHASER_OUT_D_OCLKDIV", - "CMT_PLL_PHASER_RDCLK_TOFIFO", - "CMT_PLL_PHASER_RDENABLE_TOFIFO", - "CMT_PLL_PHASER_WRCLK_TOFIFO", - "CMT_PLL_PHASER_WRENABLE_TOFIFO", - "CMT_PLL_PHYCTRL_SYNC_BB_DN", - "CMT_PLL_PHYCTRL_SYNC_BB_UP", - "CMT_TOP_BLOCK_OUTS_L_B0_0", - "CMT_TOP_BLOCK_OUTS_L_B0_1", - "CMT_TOP_BLOCK_OUTS_L_B0_10", - "CMT_TOP_BLOCK_OUTS_L_B0_11", - "CMT_TOP_BLOCK_OUTS_L_B0_12", - "CMT_TOP_BLOCK_OUTS_L_B0_2", - "CMT_TOP_BLOCK_OUTS_L_B0_3", - "CMT_TOP_BLOCK_OUTS_L_B0_4", - "CMT_TOP_BLOCK_OUTS_L_B0_5", - "CMT_TOP_BLOCK_OUTS_L_B0_6", - "CMT_TOP_BLOCK_OUTS_L_B0_7", - "CMT_TOP_BLOCK_OUTS_L_B0_8", - "CMT_TOP_BLOCK_OUTS_L_B0_9", - "CMT_TOP_BLOCK_OUTS_L_B1_0", - "CMT_TOP_BLOCK_OUTS_L_B1_1", - "CMT_TOP_BLOCK_OUTS_L_B1_10", - "CMT_TOP_BLOCK_OUTS_L_B1_11", - "CMT_TOP_BLOCK_OUTS_L_B1_12", - "CMT_TOP_BLOCK_OUTS_L_B1_2", - "CMT_TOP_BLOCK_OUTS_L_B1_3", - "CMT_TOP_BLOCK_OUTS_L_B1_4", - "CMT_TOP_BLOCK_OUTS_L_B1_5", - "CMT_TOP_BLOCK_OUTS_L_B1_6", - "CMT_TOP_BLOCK_OUTS_L_B1_7", - "CMT_TOP_BLOCK_OUTS_L_B1_8", - "CMT_TOP_BLOCK_OUTS_L_B1_9", - "CMT_TOP_BLOCK_OUTS_L_B2_0", - "CMT_TOP_BLOCK_OUTS_L_B2_1", - "CMT_TOP_BLOCK_OUTS_L_B2_10", - "CMT_TOP_BLOCK_OUTS_L_B2_11", - "CMT_TOP_BLOCK_OUTS_L_B2_12", - "CMT_TOP_BLOCK_OUTS_L_B2_2", - "CMT_TOP_BLOCK_OUTS_L_B2_3", - "CMT_TOP_BLOCK_OUTS_L_B2_4", - "CMT_TOP_BLOCK_OUTS_L_B2_5", - "CMT_TOP_BLOCK_OUTS_L_B2_6", - "CMT_TOP_BLOCK_OUTS_L_B2_7", - "CMT_TOP_BLOCK_OUTS_L_B2_8", - "CMT_TOP_BLOCK_OUTS_L_B2_9", - "CMT_TOP_BLOCK_OUTS_L_B3_0", - "CMT_TOP_BLOCK_OUTS_L_B3_1", - "CMT_TOP_BLOCK_OUTS_L_B3_10", - "CMT_TOP_BLOCK_OUTS_L_B3_11", - "CMT_TOP_BLOCK_OUTS_L_B3_12", - "CMT_TOP_BLOCK_OUTS_L_B3_2", - "CMT_TOP_BLOCK_OUTS_L_B3_3", - "CMT_TOP_BLOCK_OUTS_L_B3_4", - "CMT_TOP_BLOCK_OUTS_L_B3_5", - "CMT_TOP_BLOCK_OUTS_L_B3_6", - "CMT_TOP_BLOCK_OUTS_L_B3_7", - "CMT_TOP_BLOCK_OUTS_L_B3_8", - "CMT_TOP_BLOCK_OUTS_L_B3_9", - "CMT_TOP_BYP0_0", - "CMT_TOP_BYP0_1", - "CMT_TOP_BYP0_10", - "CMT_TOP_BYP0_11", - "CMT_TOP_BYP0_12", - "CMT_TOP_BYP0_2", - "CMT_TOP_BYP0_3", - "CMT_TOP_BYP0_4", - "CMT_TOP_BYP0_5", - "CMT_TOP_BYP0_6", - "CMT_TOP_BYP0_7", - "CMT_TOP_BYP0_8", - "CMT_TOP_BYP0_9", - "CMT_TOP_BYP1_0", - "CMT_TOP_BYP1_1", - "CMT_TOP_BYP1_10", - "CMT_TOP_BYP1_11", - "CMT_TOP_BYP1_12", - "CMT_TOP_BYP1_2", - "CMT_TOP_BYP1_3", - "CMT_TOP_BYP1_4", - "CMT_TOP_BYP1_5", - "CMT_TOP_BYP1_6", - "CMT_TOP_BYP1_7", - "CMT_TOP_BYP1_8", - "CMT_TOP_BYP1_9", - "CMT_TOP_BYP2_0", - "CMT_TOP_BYP2_1", - "CMT_TOP_BYP2_10", - "CMT_TOP_BYP2_11", - "CMT_TOP_BYP2_12", - "CMT_TOP_BYP2_2", - "CMT_TOP_BYP2_3", - "CMT_TOP_BYP2_4", - "CMT_TOP_BYP2_5", - "CMT_TOP_BYP2_6", - "CMT_TOP_BYP2_7", - "CMT_TOP_BYP2_8", - "CMT_TOP_BYP2_9", - "CMT_TOP_BYP3_0", - "CMT_TOP_BYP3_1", - "CMT_TOP_BYP3_10", - "CMT_TOP_BYP3_11", - "CMT_TOP_BYP3_12", - "CMT_TOP_BYP3_2", - "CMT_TOP_BYP3_3", - "CMT_TOP_BYP3_4", - "CMT_TOP_BYP3_5", - "CMT_TOP_BYP3_6", - "CMT_TOP_BYP3_7", - "CMT_TOP_BYP3_8", - "CMT_TOP_BYP3_9", - "CMT_TOP_BYP4_0", - "CMT_TOP_BYP4_1", - "CMT_TOP_BYP4_10", - "CMT_TOP_BYP4_11", - "CMT_TOP_BYP4_12", - "CMT_TOP_BYP4_2", - "CMT_TOP_BYP4_3", - "CMT_TOP_BYP4_4", - "CMT_TOP_BYP4_5", - "CMT_TOP_BYP4_6", - "CMT_TOP_BYP4_7", - "CMT_TOP_BYP4_8", - "CMT_TOP_BYP4_9", - "CMT_TOP_BYP5_0", - "CMT_TOP_BYP5_1", - "CMT_TOP_BYP5_10", - "CMT_TOP_BYP5_11", - "CMT_TOP_BYP5_12", - "CMT_TOP_BYP5_2", - "CMT_TOP_BYP5_3", - "CMT_TOP_BYP5_4", - "CMT_TOP_BYP5_5", - "CMT_TOP_BYP5_6", - "CMT_TOP_BYP5_7", - "CMT_TOP_BYP5_8", - "CMT_TOP_BYP5_9", - "CMT_TOP_BYP6_0", - "CMT_TOP_BYP6_1", - "CMT_TOP_BYP6_10", - "CMT_TOP_BYP6_11", - "CMT_TOP_BYP6_12", - "CMT_TOP_BYP6_2", - "CMT_TOP_BYP6_3", - "CMT_TOP_BYP6_4", - "CMT_TOP_BYP6_5", - "CMT_TOP_BYP6_6", - "CMT_TOP_BYP6_7", - "CMT_TOP_BYP6_8", - "CMT_TOP_BYP6_9", - "CMT_TOP_BYP7_0", - "CMT_TOP_BYP7_1", - "CMT_TOP_BYP7_10", - "CMT_TOP_BYP7_11", - "CMT_TOP_BYP7_12", - "CMT_TOP_BYP7_2", - "CMT_TOP_BYP7_3", - "CMT_TOP_BYP7_4", - "CMT_TOP_BYP7_5", - "CMT_TOP_BYP7_6", - "CMT_TOP_BYP7_7", - "CMT_TOP_BYP7_8", - "CMT_TOP_BYP7_9", - "CMT_TOP_CLK0_0", - "CMT_TOP_CLK0_1", - "CMT_TOP_CLK0_10", - "CMT_TOP_CLK0_11", - "CMT_TOP_CLK0_12", - "CMT_TOP_CLK0_2", - "CMT_TOP_CLK0_3", - "CMT_TOP_CLK0_4", - "CMT_TOP_CLK0_5", - "CMT_TOP_CLK0_6", - "CMT_TOP_CLK0_7", - "CMT_TOP_CLK0_8", - "CMT_TOP_CLK0_9", - "CMT_TOP_CLK1_0", - "CMT_TOP_CLK1_1", - "CMT_TOP_CLK1_10", - "CMT_TOP_CLK1_11", - "CMT_TOP_CLK1_12", - "CMT_TOP_CLK1_2", - "CMT_TOP_CLK1_3", - "CMT_TOP_CLK1_4", - "CMT_TOP_CLK1_5", - "CMT_TOP_CLK1_6", - "CMT_TOP_CLK1_7", - "CMT_TOP_CLK1_8", - "CMT_TOP_CLK1_9", - "CMT_TOP_CTRL0_0", - "CMT_TOP_CTRL0_1", - "CMT_TOP_CTRL0_10", - "CMT_TOP_CTRL0_11", - "CMT_TOP_CTRL0_12", - "CMT_TOP_CTRL0_2", - "CMT_TOP_CTRL0_3", - "CMT_TOP_CTRL0_4", - "CMT_TOP_CTRL0_5", - "CMT_TOP_CTRL0_6", - "CMT_TOP_CTRL0_7", - "CMT_TOP_CTRL0_8", - "CMT_TOP_CTRL0_9", - "CMT_TOP_CTRL1_0", - "CMT_TOP_CTRL1_1", - "CMT_TOP_CTRL1_10", - "CMT_TOP_CTRL1_11", - "CMT_TOP_CTRL1_12", - "CMT_TOP_CTRL1_2", - "CMT_TOP_CTRL1_3", - "CMT_TOP_CTRL1_4", - "CMT_TOP_CTRL1_5", - "CMT_TOP_CTRL1_6", - "CMT_TOP_CTRL1_7", - "CMT_TOP_CTRL1_8", - "CMT_TOP_CTRL1_9", - "CMT_TOP_EE2A0_0", - "CMT_TOP_EE2A0_1", - "CMT_TOP_EE2A0_10", - "CMT_TOP_EE2A0_11", - "CMT_TOP_EE2A0_12", - "CMT_TOP_EE2A0_2", - "CMT_TOP_EE2A0_3", - "CMT_TOP_EE2A0_4", - "CMT_TOP_EE2A0_5", - "CMT_TOP_EE2A0_6", - "CMT_TOP_EE2A0_7", - "CMT_TOP_EE2A0_8", - "CMT_TOP_EE2A0_9", - "CMT_TOP_EE2A1_0", - "CMT_TOP_EE2A1_1", - "CMT_TOP_EE2A1_10", - "CMT_TOP_EE2A1_11", - "CMT_TOP_EE2A1_12", - "CMT_TOP_EE2A1_2", - "CMT_TOP_EE2A1_3", - "CMT_TOP_EE2A1_4", - "CMT_TOP_EE2A1_5", - "CMT_TOP_EE2A1_6", - "CMT_TOP_EE2A1_7", - "CMT_TOP_EE2A1_8", - "CMT_TOP_EE2A1_9", - "CMT_TOP_EE2A2_0", - "CMT_TOP_EE2A2_1", - "CMT_TOP_EE2A2_10", - "CMT_TOP_EE2A2_11", - "CMT_TOP_EE2A2_12", - "CMT_TOP_EE2A2_2", - "CMT_TOP_EE2A2_3", - "CMT_TOP_EE2A2_4", - "CMT_TOP_EE2A2_5", - "CMT_TOP_EE2A2_6", - "CMT_TOP_EE2A2_7", - "CMT_TOP_EE2A2_8", - "CMT_TOP_EE2A2_9", - "CMT_TOP_EE2A3_0", - "CMT_TOP_EE2A3_1", - "CMT_TOP_EE2A3_10", - "CMT_TOP_EE2A3_11", - "CMT_TOP_EE2A3_12", - "CMT_TOP_EE2A3_2", - "CMT_TOP_EE2A3_3", - "CMT_TOP_EE2A3_4", - "CMT_TOP_EE2A3_5", - "CMT_TOP_EE2A3_6", - "CMT_TOP_EE2A3_7", - "CMT_TOP_EE2A3_8", - "CMT_TOP_EE2A3_9", - "CMT_TOP_EE2BEG0_0", - "CMT_TOP_EE2BEG0_1", - "CMT_TOP_EE2BEG0_10", - "CMT_TOP_EE2BEG0_11", - "CMT_TOP_EE2BEG0_12", - "CMT_TOP_EE2BEG0_2", - "CMT_TOP_EE2BEG0_3", - "CMT_TOP_EE2BEG0_4", - "CMT_TOP_EE2BEG0_5", - "CMT_TOP_EE2BEG0_6", - "CMT_TOP_EE2BEG0_7", - "CMT_TOP_EE2BEG0_8", - "CMT_TOP_EE2BEG0_9", - "CMT_TOP_EE2BEG1_0", - "CMT_TOP_EE2BEG1_1", - "CMT_TOP_EE2BEG1_10", - "CMT_TOP_EE2BEG1_11", - "CMT_TOP_EE2BEG1_12", - "CMT_TOP_EE2BEG1_2", - "CMT_TOP_EE2BEG1_3", - "CMT_TOP_EE2BEG1_4", - "CMT_TOP_EE2BEG1_5", - "CMT_TOP_EE2BEG1_6", - "CMT_TOP_EE2BEG1_7", - "CMT_TOP_EE2BEG1_8", - "CMT_TOP_EE2BEG1_9", - "CMT_TOP_EE2BEG2_0", - "CMT_TOP_EE2BEG2_1", - "CMT_TOP_EE2BEG2_10", - "CMT_TOP_EE2BEG2_11", - "CMT_TOP_EE2BEG2_12", - "CMT_TOP_EE2BEG2_2", - "CMT_TOP_EE2BEG2_3", - "CMT_TOP_EE2BEG2_4", - "CMT_TOP_EE2BEG2_5", - "CMT_TOP_EE2BEG2_6", - "CMT_TOP_EE2BEG2_7", - "CMT_TOP_EE2BEG2_8", - "CMT_TOP_EE2BEG2_9", - "CMT_TOP_EE2BEG3_0", - "CMT_TOP_EE2BEG3_1", - "CMT_TOP_EE2BEG3_10", - "CMT_TOP_EE2BEG3_11", - "CMT_TOP_EE2BEG3_12", - "CMT_TOP_EE2BEG3_2", - "CMT_TOP_EE2BEG3_3", - "CMT_TOP_EE2BEG3_4", - "CMT_TOP_EE2BEG3_5", - "CMT_TOP_EE2BEG3_6", - "CMT_TOP_EE2BEG3_7", - "CMT_TOP_EE2BEG3_8", - "CMT_TOP_EE2BEG3_9", - "CMT_TOP_EE4A0_0", - "CMT_TOP_EE4A0_1", - "CMT_TOP_EE4A0_10", - "CMT_TOP_EE4A0_11", - "CMT_TOP_EE4A0_12", - "CMT_TOP_EE4A0_2", - "CMT_TOP_EE4A0_3", - "CMT_TOP_EE4A0_4", - "CMT_TOP_EE4A0_5", - "CMT_TOP_EE4A0_6", - "CMT_TOP_EE4A0_7", - "CMT_TOP_EE4A0_8", - "CMT_TOP_EE4A0_9", - "CMT_TOP_EE4A1_0", - "CMT_TOP_EE4A1_1", - "CMT_TOP_EE4A1_10", - "CMT_TOP_EE4A1_11", - "CMT_TOP_EE4A1_12", - "CMT_TOP_EE4A1_2", - "CMT_TOP_EE4A1_3", - "CMT_TOP_EE4A1_4", - "CMT_TOP_EE4A1_5", - "CMT_TOP_EE4A1_6", - "CMT_TOP_EE4A1_7", - "CMT_TOP_EE4A1_8", - "CMT_TOP_EE4A1_9", - "CMT_TOP_EE4A2_0", - "CMT_TOP_EE4A2_1", - "CMT_TOP_EE4A2_10", - "CMT_TOP_EE4A2_11", - "CMT_TOP_EE4A2_12", - "CMT_TOP_EE4A2_2", - "CMT_TOP_EE4A2_3", - "CMT_TOP_EE4A2_4", - "CMT_TOP_EE4A2_5", - "CMT_TOP_EE4A2_6", - "CMT_TOP_EE4A2_7", - "CMT_TOP_EE4A2_8", - "CMT_TOP_EE4A2_9", - "CMT_TOP_EE4A3_0", - "CMT_TOP_EE4A3_1", - "CMT_TOP_EE4A3_10", - "CMT_TOP_EE4A3_11", - "CMT_TOP_EE4A3_12", - "CMT_TOP_EE4A3_2", - "CMT_TOP_EE4A3_3", - "CMT_TOP_EE4A3_4", - "CMT_TOP_EE4A3_5", - "CMT_TOP_EE4A3_6", - "CMT_TOP_EE4A3_7", - "CMT_TOP_EE4A3_8", - "CMT_TOP_EE4A3_9", - "CMT_TOP_EE4B0_0", - "CMT_TOP_EE4B0_1", - "CMT_TOP_EE4B0_10", - "CMT_TOP_EE4B0_11", - "CMT_TOP_EE4B0_12", - "CMT_TOP_EE4B0_2", - "CMT_TOP_EE4B0_3", - "CMT_TOP_EE4B0_4", - "CMT_TOP_EE4B0_5", - "CMT_TOP_EE4B0_6", - "CMT_TOP_EE4B0_7", - "CMT_TOP_EE4B0_8", - "CMT_TOP_EE4B0_9", - "CMT_TOP_EE4B1_0", - "CMT_TOP_EE4B1_1", - "CMT_TOP_EE4B1_10", - "CMT_TOP_EE4B1_11", - "CMT_TOP_EE4B1_12", - "CMT_TOP_EE4B1_2", - "CMT_TOP_EE4B1_3", - "CMT_TOP_EE4B1_4", - "CMT_TOP_EE4B1_5", - "CMT_TOP_EE4B1_6", - "CMT_TOP_EE4B1_7", - "CMT_TOP_EE4B1_8", - "CMT_TOP_EE4B1_9", - "CMT_TOP_EE4B2_0", - "CMT_TOP_EE4B2_1", - "CMT_TOP_EE4B2_10", - "CMT_TOP_EE4B2_11", - "CMT_TOP_EE4B2_12", - "CMT_TOP_EE4B2_2", - "CMT_TOP_EE4B2_3", - "CMT_TOP_EE4B2_4", - "CMT_TOP_EE4B2_5", - "CMT_TOP_EE4B2_6", - "CMT_TOP_EE4B2_7", - "CMT_TOP_EE4B2_8", - "CMT_TOP_EE4B2_9", - "CMT_TOP_EE4B3_0", - "CMT_TOP_EE4B3_1", - "CMT_TOP_EE4B3_10", - "CMT_TOP_EE4B3_11", - "CMT_TOP_EE4B3_12", - "CMT_TOP_EE4B3_2", - "CMT_TOP_EE4B3_3", - "CMT_TOP_EE4B3_4", - "CMT_TOP_EE4B3_5", - "CMT_TOP_EE4B3_6", - "CMT_TOP_EE4B3_7", - "CMT_TOP_EE4B3_8", - "CMT_TOP_EE4B3_9", - "CMT_TOP_EE4BEG0_0", - "CMT_TOP_EE4BEG0_1", - "CMT_TOP_EE4BEG0_10", - "CMT_TOP_EE4BEG0_11", - "CMT_TOP_EE4BEG0_12", - "CMT_TOP_EE4BEG0_2", - "CMT_TOP_EE4BEG0_3", - "CMT_TOP_EE4BEG0_4", - "CMT_TOP_EE4BEG0_5", - "CMT_TOP_EE4BEG0_6", - "CMT_TOP_EE4BEG0_7", - "CMT_TOP_EE4BEG0_8", - "CMT_TOP_EE4BEG0_9", - "CMT_TOP_EE4BEG1_0", - "CMT_TOP_EE4BEG1_1", - "CMT_TOP_EE4BEG1_10", - "CMT_TOP_EE4BEG1_11", - "CMT_TOP_EE4BEG1_12", - "CMT_TOP_EE4BEG1_2", - "CMT_TOP_EE4BEG1_3", - "CMT_TOP_EE4BEG1_4", - "CMT_TOP_EE4BEG1_5", - "CMT_TOP_EE4BEG1_6", - "CMT_TOP_EE4BEG1_7", - "CMT_TOP_EE4BEG1_8", - "CMT_TOP_EE4BEG1_9", - "CMT_TOP_EE4BEG2_0", - "CMT_TOP_EE4BEG2_1", - "CMT_TOP_EE4BEG2_10", - "CMT_TOP_EE4BEG2_11", - "CMT_TOP_EE4BEG2_12", - "CMT_TOP_EE4BEG2_2", - "CMT_TOP_EE4BEG2_3", - "CMT_TOP_EE4BEG2_4", - "CMT_TOP_EE4BEG2_5", - "CMT_TOP_EE4BEG2_6", - "CMT_TOP_EE4BEG2_7", - "CMT_TOP_EE4BEG2_8", - "CMT_TOP_EE4BEG2_9", - "CMT_TOP_EE4BEG3_0", - "CMT_TOP_EE4BEG3_1", - "CMT_TOP_EE4BEG3_10", - "CMT_TOP_EE4BEG3_11", - "CMT_TOP_EE4BEG3_12", - "CMT_TOP_EE4BEG3_2", - "CMT_TOP_EE4BEG3_3", - "CMT_TOP_EE4BEG3_4", - "CMT_TOP_EE4BEG3_5", - "CMT_TOP_EE4BEG3_6", - "CMT_TOP_EE4BEG3_7", - "CMT_TOP_EE4BEG3_8", - "CMT_TOP_EE4BEG3_9", - "CMT_TOP_EE4C0_0", - "CMT_TOP_EE4C0_1", - "CMT_TOP_EE4C0_10", - "CMT_TOP_EE4C0_11", - "CMT_TOP_EE4C0_12", - "CMT_TOP_EE4C0_2", - "CMT_TOP_EE4C0_3", - "CMT_TOP_EE4C0_4", - "CMT_TOP_EE4C0_5", - "CMT_TOP_EE4C0_6", - "CMT_TOP_EE4C0_7", - "CMT_TOP_EE4C0_8", - "CMT_TOP_EE4C0_9", - "CMT_TOP_EE4C1_0", - "CMT_TOP_EE4C1_1", - "CMT_TOP_EE4C1_10", - "CMT_TOP_EE4C1_11", - "CMT_TOP_EE4C1_12", - "CMT_TOP_EE4C1_2", - "CMT_TOP_EE4C1_3", - "CMT_TOP_EE4C1_4", - "CMT_TOP_EE4C1_5", - "CMT_TOP_EE4C1_6", - "CMT_TOP_EE4C1_7", - "CMT_TOP_EE4C1_8", - "CMT_TOP_EE4C1_9", - "CMT_TOP_EE4C2_0", - "CMT_TOP_EE4C2_1", - "CMT_TOP_EE4C2_10", - "CMT_TOP_EE4C2_11", - "CMT_TOP_EE4C2_12", - "CMT_TOP_EE4C2_2", - "CMT_TOP_EE4C2_3", - "CMT_TOP_EE4C2_4", - "CMT_TOP_EE4C2_5", - "CMT_TOP_EE4C2_6", - "CMT_TOP_EE4C2_7", - "CMT_TOP_EE4C2_8", - "CMT_TOP_EE4C2_9", - "CMT_TOP_EE4C3_0", - "CMT_TOP_EE4C3_1", - "CMT_TOP_EE4C3_10", - "CMT_TOP_EE4C3_11", - "CMT_TOP_EE4C3_12", - "CMT_TOP_EE4C3_2", - "CMT_TOP_EE4C3_3", - "CMT_TOP_EE4C3_4", - "CMT_TOP_EE4C3_5", - "CMT_TOP_EE4C3_6", - "CMT_TOP_EE4C3_7", - "CMT_TOP_EE4C3_8", - "CMT_TOP_EE4C3_9", - "CMT_TOP_EL1BEG0_0", - "CMT_TOP_EL1BEG0_1", - "CMT_TOP_EL1BEG0_10", - "CMT_TOP_EL1BEG0_11", - "CMT_TOP_EL1BEG0_12", - "CMT_TOP_EL1BEG0_2", - "CMT_TOP_EL1BEG0_3", - "CMT_TOP_EL1BEG0_4", - "CMT_TOP_EL1BEG0_5", - "CMT_TOP_EL1BEG0_6", - "CMT_TOP_EL1BEG0_7", - "CMT_TOP_EL1BEG0_8", - "CMT_TOP_EL1BEG0_9", - "CMT_TOP_EL1BEG1_0", - "CMT_TOP_EL1BEG1_1", - "CMT_TOP_EL1BEG1_10", - "CMT_TOP_EL1BEG1_11", - "CMT_TOP_EL1BEG1_12", - "CMT_TOP_EL1BEG1_2", - "CMT_TOP_EL1BEG1_3", - "CMT_TOP_EL1BEG1_4", - "CMT_TOP_EL1BEG1_5", - "CMT_TOP_EL1BEG1_6", - "CMT_TOP_EL1BEG1_7", - "CMT_TOP_EL1BEG1_8", - "CMT_TOP_EL1BEG1_9", - "CMT_TOP_EL1BEG2_0", - "CMT_TOP_EL1BEG2_1", - "CMT_TOP_EL1BEG2_10", - "CMT_TOP_EL1BEG2_11", - "CMT_TOP_EL1BEG2_12", - "CMT_TOP_EL1BEG2_2", - "CMT_TOP_EL1BEG2_3", - "CMT_TOP_EL1BEG2_4", - "CMT_TOP_EL1BEG2_5", - "CMT_TOP_EL1BEG2_6", - "CMT_TOP_EL1BEG2_7", - "CMT_TOP_EL1BEG2_8", - "CMT_TOP_EL1BEG2_9", - "CMT_TOP_EL1BEG3_0", - "CMT_TOP_EL1BEG3_1", - "CMT_TOP_EL1BEG3_10", - "CMT_TOP_EL1BEG3_11", - "CMT_TOP_EL1BEG3_12", - "CMT_TOP_EL1BEG3_2", - "CMT_TOP_EL1BEG3_3", - "CMT_TOP_EL1BEG3_4", - "CMT_TOP_EL1BEG3_5", - "CMT_TOP_EL1BEG3_6", - "CMT_TOP_EL1BEG3_7", - "CMT_TOP_EL1BEG3_8", - "CMT_TOP_EL1BEG3_9", - "CMT_TOP_ER1BEG0_0", - "CMT_TOP_ER1BEG0_1", - "CMT_TOP_ER1BEG0_10", - "CMT_TOP_ER1BEG0_11", - "CMT_TOP_ER1BEG0_12", - "CMT_TOP_ER1BEG0_2", - "CMT_TOP_ER1BEG0_3", - "CMT_TOP_ER1BEG0_4", - "CMT_TOP_ER1BEG0_5", - "CMT_TOP_ER1BEG0_6", - "CMT_TOP_ER1BEG0_7", - "CMT_TOP_ER1BEG0_8", - "CMT_TOP_ER1BEG0_9", - "CMT_TOP_ER1BEG1_0", - "CMT_TOP_ER1BEG1_1", - "CMT_TOP_ER1BEG1_10", - "CMT_TOP_ER1BEG1_11", - "CMT_TOP_ER1BEG1_12", - "CMT_TOP_ER1BEG1_2", - "CMT_TOP_ER1BEG1_3", - "CMT_TOP_ER1BEG1_4", - "CMT_TOP_ER1BEG1_5", - "CMT_TOP_ER1BEG1_6", - "CMT_TOP_ER1BEG1_7", - "CMT_TOP_ER1BEG1_8", - "CMT_TOP_ER1BEG1_9", - "CMT_TOP_ER1BEG2_0", - "CMT_TOP_ER1BEG2_1", - "CMT_TOP_ER1BEG2_10", - "CMT_TOP_ER1BEG2_11", - "CMT_TOP_ER1BEG2_12", - "CMT_TOP_ER1BEG2_2", - "CMT_TOP_ER1BEG2_3", - "CMT_TOP_ER1BEG2_4", - "CMT_TOP_ER1BEG2_5", - "CMT_TOP_ER1BEG2_6", - "CMT_TOP_ER1BEG2_7", - "CMT_TOP_ER1BEG2_8", - "CMT_TOP_ER1BEG2_9", - "CMT_TOP_ER1BEG3_0", - "CMT_TOP_ER1BEG3_1", - "CMT_TOP_ER1BEG3_10", - "CMT_TOP_ER1BEG3_11", - "CMT_TOP_ER1BEG3_12", - "CMT_TOP_ER1BEG3_2", - "CMT_TOP_ER1BEG3_3", - "CMT_TOP_ER1BEG3_4", - "CMT_TOP_ER1BEG3_5", - "CMT_TOP_ER1BEG3_6", - "CMT_TOP_ER1BEG3_7", - "CMT_TOP_ER1BEG3_8", - "CMT_TOP_ER1BEG3_9", - "CMT_TOP_FAN0_0", - "CMT_TOP_FAN0_1", - "CMT_TOP_FAN0_10", - "CMT_TOP_FAN0_11", - "CMT_TOP_FAN0_12", - "CMT_TOP_FAN0_2", - "CMT_TOP_FAN0_3", - "CMT_TOP_FAN0_4", - "CMT_TOP_FAN0_5", - "CMT_TOP_FAN0_6", - "CMT_TOP_FAN0_7", - "CMT_TOP_FAN0_8", - "CMT_TOP_FAN0_9", - "CMT_TOP_FAN1_0", - "CMT_TOP_FAN1_1", - "CMT_TOP_FAN1_10", - "CMT_TOP_FAN1_11", - "CMT_TOP_FAN1_12", - "CMT_TOP_FAN1_2", - "CMT_TOP_FAN1_3", - "CMT_TOP_FAN1_4", - "CMT_TOP_FAN1_5", - "CMT_TOP_FAN1_6", - "CMT_TOP_FAN1_7", - "CMT_TOP_FAN1_8", - "CMT_TOP_FAN1_9", - "CMT_TOP_FAN2_0", - "CMT_TOP_FAN2_1", - "CMT_TOP_FAN2_10", - "CMT_TOP_FAN2_11", - "CMT_TOP_FAN2_12", - "CMT_TOP_FAN2_2", - "CMT_TOP_FAN2_3", - "CMT_TOP_FAN2_4", - "CMT_TOP_FAN2_5", - "CMT_TOP_FAN2_6", - "CMT_TOP_FAN2_7", - "CMT_TOP_FAN2_8", - "CMT_TOP_FAN2_9", - "CMT_TOP_FAN3_0", - "CMT_TOP_FAN3_1", - "CMT_TOP_FAN3_10", - "CMT_TOP_FAN3_11", - "CMT_TOP_FAN3_12", - "CMT_TOP_FAN3_2", - "CMT_TOP_FAN3_3", - "CMT_TOP_FAN3_4", - "CMT_TOP_FAN3_5", - "CMT_TOP_FAN3_6", - "CMT_TOP_FAN3_7", - "CMT_TOP_FAN3_8", - "CMT_TOP_FAN3_9", - "CMT_TOP_FAN4_0", - "CMT_TOP_FAN4_1", - "CMT_TOP_FAN4_10", - "CMT_TOP_FAN4_11", - "CMT_TOP_FAN4_12", - "CMT_TOP_FAN4_2", - "CMT_TOP_FAN4_3", - "CMT_TOP_FAN4_4", - "CMT_TOP_FAN4_5", - "CMT_TOP_FAN4_6", - "CMT_TOP_FAN4_7", - "CMT_TOP_FAN4_8", - "CMT_TOP_FAN4_9", - "CMT_TOP_FAN5_0", - "CMT_TOP_FAN5_1", - "CMT_TOP_FAN5_10", - "CMT_TOP_FAN5_11", - "CMT_TOP_FAN5_12", - "CMT_TOP_FAN5_2", - "CMT_TOP_FAN5_3", - "CMT_TOP_FAN5_4", - "CMT_TOP_FAN5_5", - "CMT_TOP_FAN5_6", - "CMT_TOP_FAN5_7", - "CMT_TOP_FAN5_8", - "CMT_TOP_FAN5_9", - "CMT_TOP_FAN6_0", - "CMT_TOP_FAN6_1", - "CMT_TOP_FAN6_10", - "CMT_TOP_FAN6_11", - "CMT_TOP_FAN6_12", - "CMT_TOP_FAN6_2", - "CMT_TOP_FAN6_3", - "CMT_TOP_FAN6_4", - "CMT_TOP_FAN6_5", - "CMT_TOP_FAN6_6", - "CMT_TOP_FAN6_7", - "CMT_TOP_FAN6_8", - "CMT_TOP_FAN6_9", - "CMT_TOP_FAN7_0", - "CMT_TOP_FAN7_1", - "CMT_TOP_FAN7_10", - "CMT_TOP_FAN7_11", - "CMT_TOP_FAN7_12", - "CMT_TOP_FAN7_2", - "CMT_TOP_FAN7_3", - "CMT_TOP_FAN7_4", - "CMT_TOP_FAN7_5", - "CMT_TOP_FAN7_6", - "CMT_TOP_FAN7_7", - "CMT_TOP_FAN7_8", - "CMT_TOP_FAN7_9", - "CMT_TOP_ICLKDIV_0", - "CMT_TOP_ICLKDIV_1", - "CMT_TOP_ICLKDIV_10", - "CMT_TOP_ICLKDIV_11", - "CMT_TOP_ICLKDIV_12", - "CMT_TOP_ICLKDIV_2", - "CMT_TOP_ICLKDIV_3", - "CMT_TOP_ICLKDIV_4", - "CMT_TOP_ICLKDIV_5", - "CMT_TOP_ICLKDIV_6", - "CMT_TOP_ICLKDIV_7", - "CMT_TOP_ICLKDIV_8", - "CMT_TOP_ICLKDIV_9", - "CMT_TOP_ICLK_0", - "CMT_TOP_ICLK_1", - "CMT_TOP_ICLK_10", - "CMT_TOP_ICLK_11", - "CMT_TOP_ICLK_12", - "CMT_TOP_ICLK_2", - "CMT_TOP_ICLK_3", - "CMT_TOP_ICLK_4", - "CMT_TOP_ICLK_5", - "CMT_TOP_ICLK_6", - "CMT_TOP_ICLK_7", - "CMT_TOP_ICLK_8", - "CMT_TOP_ICLK_9", - "CMT_TOP_IMUX0_0", - "CMT_TOP_IMUX0_1", - "CMT_TOP_IMUX0_10", - "CMT_TOP_IMUX0_11", - "CMT_TOP_IMUX0_12", - "CMT_TOP_IMUX0_2", - "CMT_TOP_IMUX0_3", - "CMT_TOP_IMUX0_4", - "CMT_TOP_IMUX0_5", - "CMT_TOP_IMUX0_6", - "CMT_TOP_IMUX0_7", - "CMT_TOP_IMUX0_8", - "CMT_TOP_IMUX0_9", - "CMT_TOP_IMUX10_0", - "CMT_TOP_IMUX10_1", - "CMT_TOP_IMUX10_10", - "CMT_TOP_IMUX10_11", - "CMT_TOP_IMUX10_12", - "CMT_TOP_IMUX10_2", - "CMT_TOP_IMUX10_3", - "CMT_TOP_IMUX10_4", - "CMT_TOP_IMUX10_5", - "CMT_TOP_IMUX10_6", - "CMT_TOP_IMUX10_7", - "CMT_TOP_IMUX10_8", - "CMT_TOP_IMUX10_9", - "CMT_TOP_IMUX11_0", - "CMT_TOP_IMUX11_1", - "CMT_TOP_IMUX11_10", - "CMT_TOP_IMUX11_11", - "CMT_TOP_IMUX11_12", - "CMT_TOP_IMUX11_2", - "CMT_TOP_IMUX11_3", - "CMT_TOP_IMUX11_4", - "CMT_TOP_IMUX11_5", - "CMT_TOP_IMUX11_6", - "CMT_TOP_IMUX11_7", - "CMT_TOP_IMUX11_8", - "CMT_TOP_IMUX11_9", - "CMT_TOP_IMUX12_0", - "CMT_TOP_IMUX12_1", - "CMT_TOP_IMUX12_10", - "CMT_TOP_IMUX12_11", - "CMT_TOP_IMUX12_12", - "CMT_TOP_IMUX12_2", - "CMT_TOP_IMUX12_3", - "CMT_TOP_IMUX12_4", - "CMT_TOP_IMUX12_5", - "CMT_TOP_IMUX12_6", - "CMT_TOP_IMUX12_7", - "CMT_TOP_IMUX12_8", - "CMT_TOP_IMUX12_9", - "CMT_TOP_IMUX13_0", - "CMT_TOP_IMUX13_1", - "CMT_TOP_IMUX13_10", - "CMT_TOP_IMUX13_11", - "CMT_TOP_IMUX13_12", - "CMT_TOP_IMUX13_2", - "CMT_TOP_IMUX13_3", - "CMT_TOP_IMUX13_4", - "CMT_TOP_IMUX13_5", - "CMT_TOP_IMUX13_6", - "CMT_TOP_IMUX13_7", - "CMT_TOP_IMUX13_8", - "CMT_TOP_IMUX13_9", - "CMT_TOP_IMUX14_0", - "CMT_TOP_IMUX14_1", - "CMT_TOP_IMUX14_10", - "CMT_TOP_IMUX14_11", - "CMT_TOP_IMUX14_12", - "CMT_TOP_IMUX14_2", - "CMT_TOP_IMUX14_3", - "CMT_TOP_IMUX14_4", - "CMT_TOP_IMUX14_5", - "CMT_TOP_IMUX14_6", - "CMT_TOP_IMUX14_7", - "CMT_TOP_IMUX14_8", - "CMT_TOP_IMUX14_9", - "CMT_TOP_IMUX15_0", - "CMT_TOP_IMUX15_1", - "CMT_TOP_IMUX15_10", - "CMT_TOP_IMUX15_11", - "CMT_TOP_IMUX15_12", - "CMT_TOP_IMUX15_2", - "CMT_TOP_IMUX15_3", - "CMT_TOP_IMUX15_4", - "CMT_TOP_IMUX15_5", - "CMT_TOP_IMUX15_6", - "CMT_TOP_IMUX15_7", - "CMT_TOP_IMUX15_8", - "CMT_TOP_IMUX15_9", - "CMT_TOP_IMUX16_0", - "CMT_TOP_IMUX16_1", - "CMT_TOP_IMUX16_10", - "CMT_TOP_IMUX16_11", - "CMT_TOP_IMUX16_12", - "CMT_TOP_IMUX16_2", - "CMT_TOP_IMUX16_3", - "CMT_TOP_IMUX16_4", - "CMT_TOP_IMUX16_5", - "CMT_TOP_IMUX16_6", - "CMT_TOP_IMUX16_7", - "CMT_TOP_IMUX16_8", - "CMT_TOP_IMUX16_9", - "CMT_TOP_IMUX17_0", - "CMT_TOP_IMUX17_1", - "CMT_TOP_IMUX17_10", - "CMT_TOP_IMUX17_11", - "CMT_TOP_IMUX17_12", - "CMT_TOP_IMUX17_2", - "CMT_TOP_IMUX17_3", - "CMT_TOP_IMUX17_4", - "CMT_TOP_IMUX17_5", - "CMT_TOP_IMUX17_6", - "CMT_TOP_IMUX17_7", - "CMT_TOP_IMUX17_8", - "CMT_TOP_IMUX17_9", - "CMT_TOP_IMUX18_0", - "CMT_TOP_IMUX18_1", - "CMT_TOP_IMUX18_10", - "CMT_TOP_IMUX18_11", - "CMT_TOP_IMUX18_12", - "CMT_TOP_IMUX18_2", - "CMT_TOP_IMUX18_3", - "CMT_TOP_IMUX18_4", - "CMT_TOP_IMUX18_5", - "CMT_TOP_IMUX18_6", - "CMT_TOP_IMUX18_7", - "CMT_TOP_IMUX18_8", - "CMT_TOP_IMUX18_9", - "CMT_TOP_IMUX19_0", - "CMT_TOP_IMUX19_1", - "CMT_TOP_IMUX19_10", - "CMT_TOP_IMUX19_11", - "CMT_TOP_IMUX19_12", - "CMT_TOP_IMUX19_2", - "CMT_TOP_IMUX19_3", - "CMT_TOP_IMUX19_4", - "CMT_TOP_IMUX19_5", - "CMT_TOP_IMUX19_6", - "CMT_TOP_IMUX19_7", - "CMT_TOP_IMUX19_8", - "CMT_TOP_IMUX19_9", - "CMT_TOP_IMUX1_0", - "CMT_TOP_IMUX1_1", - "CMT_TOP_IMUX1_10", - "CMT_TOP_IMUX1_11", - "CMT_TOP_IMUX1_12", - "CMT_TOP_IMUX1_2", - "CMT_TOP_IMUX1_3", - "CMT_TOP_IMUX1_4", - "CMT_TOP_IMUX1_5", - "CMT_TOP_IMUX1_6", - "CMT_TOP_IMUX1_7", - "CMT_TOP_IMUX1_8", - "CMT_TOP_IMUX1_9", - "CMT_TOP_IMUX20_0", - "CMT_TOP_IMUX20_1", - "CMT_TOP_IMUX20_10", - "CMT_TOP_IMUX20_11", - "CMT_TOP_IMUX20_12", - "CMT_TOP_IMUX20_2", - "CMT_TOP_IMUX20_3", - "CMT_TOP_IMUX20_4", - "CMT_TOP_IMUX20_5", - "CMT_TOP_IMUX20_6", - "CMT_TOP_IMUX20_7", - "CMT_TOP_IMUX20_8", - "CMT_TOP_IMUX20_9", - "CMT_TOP_IMUX21_0", - "CMT_TOP_IMUX21_1", - "CMT_TOP_IMUX21_10", - "CMT_TOP_IMUX21_11", - "CMT_TOP_IMUX21_12", - "CMT_TOP_IMUX21_2", - "CMT_TOP_IMUX21_3", - "CMT_TOP_IMUX21_4", - "CMT_TOP_IMUX21_5", - "CMT_TOP_IMUX21_6", - "CMT_TOP_IMUX21_7", - "CMT_TOP_IMUX21_8", - "CMT_TOP_IMUX21_9", - "CMT_TOP_IMUX22_0", - "CMT_TOP_IMUX22_1", - "CMT_TOP_IMUX22_10", - "CMT_TOP_IMUX22_11", - "CMT_TOP_IMUX22_12", - "CMT_TOP_IMUX22_2", - "CMT_TOP_IMUX22_3", - "CMT_TOP_IMUX22_4", - "CMT_TOP_IMUX22_5", - "CMT_TOP_IMUX22_6", - "CMT_TOP_IMUX22_7", - "CMT_TOP_IMUX22_8", - "CMT_TOP_IMUX22_9", - "CMT_TOP_IMUX23_0", - "CMT_TOP_IMUX23_1", - "CMT_TOP_IMUX23_10", - "CMT_TOP_IMUX23_11", - "CMT_TOP_IMUX23_12", - "CMT_TOP_IMUX23_2", - "CMT_TOP_IMUX23_3", - "CMT_TOP_IMUX23_4", - "CMT_TOP_IMUX23_5", - "CMT_TOP_IMUX23_6", - "CMT_TOP_IMUX23_7", - "CMT_TOP_IMUX23_8", - "CMT_TOP_IMUX23_9", - "CMT_TOP_IMUX24_0", - "CMT_TOP_IMUX24_1", - "CMT_TOP_IMUX24_10", - "CMT_TOP_IMUX24_11", - "CMT_TOP_IMUX24_12", - "CMT_TOP_IMUX24_2", - "CMT_TOP_IMUX24_3", - "CMT_TOP_IMUX24_4", - "CMT_TOP_IMUX24_5", - "CMT_TOP_IMUX24_6", - "CMT_TOP_IMUX24_7", - "CMT_TOP_IMUX24_8", - "CMT_TOP_IMUX24_9", - "CMT_TOP_IMUX25_0", - "CMT_TOP_IMUX25_1", - "CMT_TOP_IMUX25_10", - "CMT_TOP_IMUX25_11", - "CMT_TOP_IMUX25_12", - "CMT_TOP_IMUX25_2", - "CMT_TOP_IMUX25_3", - "CMT_TOP_IMUX25_4", - "CMT_TOP_IMUX25_5", - "CMT_TOP_IMUX25_6", - "CMT_TOP_IMUX25_7", - "CMT_TOP_IMUX25_8", - "CMT_TOP_IMUX25_9", - "CMT_TOP_IMUX26_0", - "CMT_TOP_IMUX26_1", - "CMT_TOP_IMUX26_10", - "CMT_TOP_IMUX26_11", - "CMT_TOP_IMUX26_12", - "CMT_TOP_IMUX26_2", - "CMT_TOP_IMUX26_3", - "CMT_TOP_IMUX26_4", - "CMT_TOP_IMUX26_5", - "CMT_TOP_IMUX26_6", - "CMT_TOP_IMUX26_7", - "CMT_TOP_IMUX26_8", - "CMT_TOP_IMUX26_9", - "CMT_TOP_IMUX27_0", - "CMT_TOP_IMUX27_1", - "CMT_TOP_IMUX27_10", - "CMT_TOP_IMUX27_11", - "CMT_TOP_IMUX27_12", - "CMT_TOP_IMUX27_2", - "CMT_TOP_IMUX27_3", - "CMT_TOP_IMUX27_4", - "CMT_TOP_IMUX27_5", - "CMT_TOP_IMUX27_6", - "CMT_TOP_IMUX27_7", - "CMT_TOP_IMUX27_8", - "CMT_TOP_IMUX27_9", - "CMT_TOP_IMUX28_0", - "CMT_TOP_IMUX28_1", - "CMT_TOP_IMUX28_10", - "CMT_TOP_IMUX28_11", - "CMT_TOP_IMUX28_12", - "CMT_TOP_IMUX28_2", - "CMT_TOP_IMUX28_3", - "CMT_TOP_IMUX28_4", - "CMT_TOP_IMUX28_5", - "CMT_TOP_IMUX28_6", - "CMT_TOP_IMUX28_7", - "CMT_TOP_IMUX28_8", - "CMT_TOP_IMUX28_9", - "CMT_TOP_IMUX29_0", - "CMT_TOP_IMUX29_1", - "CMT_TOP_IMUX29_10", - "CMT_TOP_IMUX29_11", - "CMT_TOP_IMUX29_12", - "CMT_TOP_IMUX29_2", - "CMT_TOP_IMUX29_3", - "CMT_TOP_IMUX29_4", - "CMT_TOP_IMUX29_5", - "CMT_TOP_IMUX29_6", - "CMT_TOP_IMUX29_7", - "CMT_TOP_IMUX29_8", - "CMT_TOP_IMUX29_9", - "CMT_TOP_IMUX2_0", - "CMT_TOP_IMUX2_1", - "CMT_TOP_IMUX2_10", - "CMT_TOP_IMUX2_11", - "CMT_TOP_IMUX2_12", - "CMT_TOP_IMUX2_2", - "CMT_TOP_IMUX2_3", - "CMT_TOP_IMUX2_4", - "CMT_TOP_IMUX2_5", - "CMT_TOP_IMUX2_6", - "CMT_TOP_IMUX2_7", - "CMT_TOP_IMUX2_8", - "CMT_TOP_IMUX2_9", - "CMT_TOP_IMUX30_0", - "CMT_TOP_IMUX30_1", - "CMT_TOP_IMUX30_10", - "CMT_TOP_IMUX30_11", - "CMT_TOP_IMUX30_12", - "CMT_TOP_IMUX30_2", - "CMT_TOP_IMUX30_3", - "CMT_TOP_IMUX30_4", - "CMT_TOP_IMUX30_5", - "CMT_TOP_IMUX30_6", - "CMT_TOP_IMUX30_7", - "CMT_TOP_IMUX30_8", - "CMT_TOP_IMUX30_9", - "CMT_TOP_IMUX31_0", - "CMT_TOP_IMUX31_1", - "CMT_TOP_IMUX31_10", - "CMT_TOP_IMUX31_11", - "CMT_TOP_IMUX31_12", - "CMT_TOP_IMUX31_2", - "CMT_TOP_IMUX31_3", - "CMT_TOP_IMUX31_4", - "CMT_TOP_IMUX31_5", - "CMT_TOP_IMUX31_6", - "CMT_TOP_IMUX31_7", - "CMT_TOP_IMUX31_8", - "CMT_TOP_IMUX31_9", - "CMT_TOP_IMUX32_0", - "CMT_TOP_IMUX32_1", - "CMT_TOP_IMUX32_10", - "CMT_TOP_IMUX32_11", - "CMT_TOP_IMUX32_12", - "CMT_TOP_IMUX32_2", - "CMT_TOP_IMUX32_3", - "CMT_TOP_IMUX32_4", - "CMT_TOP_IMUX32_5", - "CMT_TOP_IMUX32_6", - "CMT_TOP_IMUX32_7", - "CMT_TOP_IMUX32_8", - "CMT_TOP_IMUX32_9", - "CMT_TOP_IMUX33_0", - "CMT_TOP_IMUX33_1", - "CMT_TOP_IMUX33_10", - "CMT_TOP_IMUX33_11", - "CMT_TOP_IMUX33_12", - "CMT_TOP_IMUX33_2", - "CMT_TOP_IMUX33_3", - "CMT_TOP_IMUX33_4", - "CMT_TOP_IMUX33_5", - "CMT_TOP_IMUX33_6", - "CMT_TOP_IMUX33_7", - "CMT_TOP_IMUX33_8", - "CMT_TOP_IMUX33_9", - "CMT_TOP_IMUX34_0", - "CMT_TOP_IMUX34_1", - "CMT_TOP_IMUX34_10", - "CMT_TOP_IMUX34_11", - "CMT_TOP_IMUX34_12", - "CMT_TOP_IMUX34_2", - "CMT_TOP_IMUX34_3", - "CMT_TOP_IMUX34_4", - "CMT_TOP_IMUX34_5", - "CMT_TOP_IMUX34_6", - "CMT_TOP_IMUX34_7", - "CMT_TOP_IMUX34_8", - "CMT_TOP_IMUX34_9", - "CMT_TOP_IMUX35_0", - "CMT_TOP_IMUX35_1", - "CMT_TOP_IMUX35_10", - "CMT_TOP_IMUX35_11", - "CMT_TOP_IMUX35_12", - "CMT_TOP_IMUX35_2", - "CMT_TOP_IMUX35_3", - "CMT_TOP_IMUX35_4", - "CMT_TOP_IMUX35_5", - "CMT_TOP_IMUX35_6", - "CMT_TOP_IMUX35_7", - "CMT_TOP_IMUX35_8", - "CMT_TOP_IMUX35_9", - "CMT_TOP_IMUX36_0", - "CMT_TOP_IMUX36_1", - "CMT_TOP_IMUX36_10", - "CMT_TOP_IMUX36_11", - "CMT_TOP_IMUX36_12", - "CMT_TOP_IMUX36_2", - "CMT_TOP_IMUX36_3", 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"CMT_TOP_IMUX3_0", - "CMT_TOP_IMUX3_1", - "CMT_TOP_IMUX3_10", - "CMT_TOP_IMUX3_11", - "CMT_TOP_IMUX3_12", - "CMT_TOP_IMUX3_2", - "CMT_TOP_IMUX3_3", - "CMT_TOP_IMUX3_4", - "CMT_TOP_IMUX3_5", - "CMT_TOP_IMUX3_6", - "CMT_TOP_IMUX3_7", - "CMT_TOP_IMUX3_8", - "CMT_TOP_IMUX3_9", - "CMT_TOP_IMUX40_0", - "CMT_TOP_IMUX40_1", - "CMT_TOP_IMUX40_10", - "CMT_TOP_IMUX40_11", - "CMT_TOP_IMUX40_12", - "CMT_TOP_IMUX40_2", - "CMT_TOP_IMUX40_3", - "CMT_TOP_IMUX40_4", - "CMT_TOP_IMUX40_5", - "CMT_TOP_IMUX40_6", - "CMT_TOP_IMUX40_7", - "CMT_TOP_IMUX40_8", - "CMT_TOP_IMUX40_9", - "CMT_TOP_IMUX41_0", - "CMT_TOP_IMUX41_1", - "CMT_TOP_IMUX41_10", - "CMT_TOP_IMUX41_11", - "CMT_TOP_IMUX41_12", - "CMT_TOP_IMUX41_2", - "CMT_TOP_IMUX41_3", - "CMT_TOP_IMUX41_4", - "CMT_TOP_IMUX41_5", - "CMT_TOP_IMUX41_6", - "CMT_TOP_IMUX41_7", - "CMT_TOP_IMUX41_8", - "CMT_TOP_IMUX41_9", - "CMT_TOP_IMUX42_0", - "CMT_TOP_IMUX42_1", - "CMT_TOP_IMUX42_10", - "CMT_TOP_IMUX42_11", - "CMT_TOP_IMUX42_12", - "CMT_TOP_IMUX42_2", - "CMT_TOP_IMUX42_3", - "CMT_TOP_IMUX42_4", - "CMT_TOP_IMUX42_5", - "CMT_TOP_IMUX42_6", - "CMT_TOP_IMUX42_7", - "CMT_TOP_IMUX42_8", - "CMT_TOP_IMUX42_9", - "CMT_TOP_IMUX43_0", - "CMT_TOP_IMUX43_1", - "CMT_TOP_IMUX43_10", - "CMT_TOP_IMUX43_11", - "CMT_TOP_IMUX43_12", - "CMT_TOP_IMUX43_2", - "CMT_TOP_IMUX43_3", - "CMT_TOP_IMUX43_4", - "CMT_TOP_IMUX43_5", - "CMT_TOP_IMUX43_6", - "CMT_TOP_IMUX43_7", - "CMT_TOP_IMUX43_8", - "CMT_TOP_IMUX43_9", - "CMT_TOP_IMUX44_0", - "CMT_TOP_IMUX44_1", - "CMT_TOP_IMUX44_10", - "CMT_TOP_IMUX44_11", - "CMT_TOP_IMUX44_12", - "CMT_TOP_IMUX44_2", - "CMT_TOP_IMUX44_3", - "CMT_TOP_IMUX44_4", - "CMT_TOP_IMUX44_5", - "CMT_TOP_IMUX44_6", - "CMT_TOP_IMUX44_7", - "CMT_TOP_IMUX44_8", - "CMT_TOP_IMUX44_9", - "CMT_TOP_IMUX45_0", - "CMT_TOP_IMUX45_1", - "CMT_TOP_IMUX45_10", - "CMT_TOP_IMUX45_11", - "CMT_TOP_IMUX45_12", - "CMT_TOP_IMUX45_2", - "CMT_TOP_IMUX45_3", - "CMT_TOP_IMUX45_4", - "CMT_TOP_IMUX45_5", - "CMT_TOP_IMUX45_6", - "CMT_TOP_IMUX45_7", - "CMT_TOP_IMUX45_8", - "CMT_TOP_IMUX45_9", - "CMT_TOP_IMUX46_0", - "CMT_TOP_IMUX46_1", - "CMT_TOP_IMUX46_10", - "CMT_TOP_IMUX46_11", - "CMT_TOP_IMUX46_12", - "CMT_TOP_IMUX46_2", - "CMT_TOP_IMUX46_3", - "CMT_TOP_IMUX46_4", - "CMT_TOP_IMUX46_5", - "CMT_TOP_IMUX46_6", - "CMT_TOP_IMUX46_7", - "CMT_TOP_IMUX46_8", - "CMT_TOP_IMUX46_9", - "CMT_TOP_IMUX47_0", - "CMT_TOP_IMUX47_1", - "CMT_TOP_IMUX47_10", - "CMT_TOP_IMUX47_11", - "CMT_TOP_IMUX47_12", - "CMT_TOP_IMUX47_2", - "CMT_TOP_IMUX47_3", - "CMT_TOP_IMUX47_4", - "CMT_TOP_IMUX47_5", - "CMT_TOP_IMUX47_6", - "CMT_TOP_IMUX47_7", - "CMT_TOP_IMUX47_8", - "CMT_TOP_IMUX47_9", - "CMT_TOP_IMUX4_0", - "CMT_TOP_IMUX4_1", - "CMT_TOP_IMUX4_10", - "CMT_TOP_IMUX4_11", - "CMT_TOP_IMUX4_12", - "CMT_TOP_IMUX4_2", - "CMT_TOP_IMUX4_3", - "CMT_TOP_IMUX4_4", - "CMT_TOP_IMUX4_5", - "CMT_TOP_IMUX4_6", - "CMT_TOP_IMUX4_7", - "CMT_TOP_IMUX4_8", - "CMT_TOP_IMUX4_9", - "CMT_TOP_IMUX5_0", - "CMT_TOP_IMUX5_1", - "CMT_TOP_IMUX5_10", - "CMT_TOP_IMUX5_11", - "CMT_TOP_IMUX5_12", - "CMT_TOP_IMUX5_2", - "CMT_TOP_IMUX5_3", - "CMT_TOP_IMUX5_4", - "CMT_TOP_IMUX5_5", - "CMT_TOP_IMUX5_6", - "CMT_TOP_IMUX5_7", - "CMT_TOP_IMUX5_8", - "CMT_TOP_IMUX5_9", - "CMT_TOP_IMUX6_0", - "CMT_TOP_IMUX6_1", - "CMT_TOP_IMUX6_10", - "CMT_TOP_IMUX6_11", - "CMT_TOP_IMUX6_12", - "CMT_TOP_IMUX6_2", - "CMT_TOP_IMUX6_3", - "CMT_TOP_IMUX6_4", - "CMT_TOP_IMUX6_5", - "CMT_TOP_IMUX6_6", - "CMT_TOP_IMUX6_7", - "CMT_TOP_IMUX6_8", - "CMT_TOP_IMUX6_9", - "CMT_TOP_IMUX7_0", - "CMT_TOP_IMUX7_1", - "CMT_TOP_IMUX7_10", - "CMT_TOP_IMUX7_11", - "CMT_TOP_IMUX7_12", - "CMT_TOP_IMUX7_2", - "CMT_TOP_IMUX7_3", - "CMT_TOP_IMUX7_4", - "CMT_TOP_IMUX7_5", - "CMT_TOP_IMUX7_6", - "CMT_TOP_IMUX7_7", - "CMT_TOP_IMUX7_8", - "CMT_TOP_IMUX7_9", - "CMT_TOP_IMUX8_0", - "CMT_TOP_IMUX8_1", - "CMT_TOP_IMUX8_10", - "CMT_TOP_IMUX8_11", - "CMT_TOP_IMUX8_12", - "CMT_TOP_IMUX8_2", - "CMT_TOP_IMUX8_3", - "CMT_TOP_IMUX8_4", - "CMT_TOP_IMUX8_5", - "CMT_TOP_IMUX8_6", - "CMT_TOP_IMUX8_7", - "CMT_TOP_IMUX8_8", - "CMT_TOP_IMUX8_9", - "CMT_TOP_IMUX9_0", - "CMT_TOP_IMUX9_1", - "CMT_TOP_IMUX9_10", - "CMT_TOP_IMUX9_11", - "CMT_TOP_IMUX9_12", - "CMT_TOP_IMUX9_2", - "CMT_TOP_IMUX9_3", - "CMT_TOP_IMUX9_4", - "CMT_TOP_IMUX9_5", - "CMT_TOP_IMUX9_6", - "CMT_TOP_IMUX9_7", - "CMT_TOP_IMUX9_8", - "CMT_TOP_IMUX9_9", - "CMT_TOP_LH10_0", - "CMT_TOP_LH10_1", - "CMT_TOP_LH10_10", - "CMT_TOP_LH10_11", - "CMT_TOP_LH10_12", - "CMT_TOP_LH10_2", - "CMT_TOP_LH10_3", - "CMT_TOP_LH10_4", - "CMT_TOP_LH10_5", - "CMT_TOP_LH10_6", - "CMT_TOP_LH10_7", - "CMT_TOP_LH10_8", - "CMT_TOP_LH10_9", - "CMT_TOP_LH11_0", - "CMT_TOP_LH11_1", - "CMT_TOP_LH11_10", - "CMT_TOP_LH11_11", - "CMT_TOP_LH11_12", - "CMT_TOP_LH11_2", - "CMT_TOP_LH11_3", - "CMT_TOP_LH11_4", - "CMT_TOP_LH11_5", - "CMT_TOP_LH11_6", - "CMT_TOP_LH11_7", - "CMT_TOP_LH11_8", - "CMT_TOP_LH11_9", - "CMT_TOP_LH12_0", - "CMT_TOP_LH12_1", - "CMT_TOP_LH12_10", - "CMT_TOP_LH12_11", - "CMT_TOP_LH12_12", - "CMT_TOP_LH12_2", - "CMT_TOP_LH12_3", - "CMT_TOP_LH12_4", - "CMT_TOP_LH12_5", - "CMT_TOP_LH12_6", - "CMT_TOP_LH12_7", - "CMT_TOP_LH12_8", - "CMT_TOP_LH12_9", - "CMT_TOP_LH1_0", - "CMT_TOP_LH1_1", - "CMT_TOP_LH1_10", - "CMT_TOP_LH1_11", - "CMT_TOP_LH1_12", - "CMT_TOP_LH1_2", - "CMT_TOP_LH1_3", - "CMT_TOP_LH1_4", - "CMT_TOP_LH1_5", - "CMT_TOP_LH1_6", - "CMT_TOP_LH1_7", - "CMT_TOP_LH1_8", - "CMT_TOP_LH1_9", - "CMT_TOP_LH2_0", - "CMT_TOP_LH2_1", - "CMT_TOP_LH2_10", - "CMT_TOP_LH2_11", - "CMT_TOP_LH2_12", - "CMT_TOP_LH2_2", - "CMT_TOP_LH2_3", - "CMT_TOP_LH2_4", - "CMT_TOP_LH2_5", - "CMT_TOP_LH2_6", - "CMT_TOP_LH2_7", - "CMT_TOP_LH2_8", - "CMT_TOP_LH2_9", - "CMT_TOP_LH3_0", - "CMT_TOP_LH3_1", - "CMT_TOP_LH3_10", - "CMT_TOP_LH3_11", - "CMT_TOP_LH3_12", - "CMT_TOP_LH3_2", - "CMT_TOP_LH3_3", - "CMT_TOP_LH3_4", - "CMT_TOP_LH3_5", - "CMT_TOP_LH3_6", - "CMT_TOP_LH3_7", - "CMT_TOP_LH3_8", - "CMT_TOP_LH3_9", - "CMT_TOP_LH4_0", - "CMT_TOP_LH4_1", - "CMT_TOP_LH4_10", - "CMT_TOP_LH4_11", - "CMT_TOP_LH4_12", - "CMT_TOP_LH4_2", - "CMT_TOP_LH4_3", - "CMT_TOP_LH4_4", - "CMT_TOP_LH4_5", - "CMT_TOP_LH4_6", - "CMT_TOP_LH4_7", - "CMT_TOP_LH4_8", - "CMT_TOP_LH4_9", - "CMT_TOP_LH5_0", - "CMT_TOP_LH5_1", - "CMT_TOP_LH5_10", - "CMT_TOP_LH5_11", - "CMT_TOP_LH5_12", - "CMT_TOP_LH5_2", - "CMT_TOP_LH5_3", - "CMT_TOP_LH5_4", - "CMT_TOP_LH5_5", - "CMT_TOP_LH5_6", - "CMT_TOP_LH5_7", - "CMT_TOP_LH5_8", - "CMT_TOP_LH5_9", - "CMT_TOP_LH6_0", - "CMT_TOP_LH6_1", - "CMT_TOP_LH6_10", - "CMT_TOP_LH6_11", - "CMT_TOP_LH6_12", - "CMT_TOP_LH6_2", - "CMT_TOP_LH6_3", - "CMT_TOP_LH6_4", - "CMT_TOP_LH6_5", - "CMT_TOP_LH6_6", - "CMT_TOP_LH6_7", - "CMT_TOP_LH6_8", - "CMT_TOP_LH6_9", - "CMT_TOP_LH7_0", - "CMT_TOP_LH7_1", - "CMT_TOP_LH7_10", - "CMT_TOP_LH7_11", - "CMT_TOP_LH7_12", - "CMT_TOP_LH7_2", - "CMT_TOP_LH7_3", - "CMT_TOP_LH7_4", - "CMT_TOP_LH7_5", - "CMT_TOP_LH7_6", - "CMT_TOP_LH7_7", - "CMT_TOP_LH7_8", - "CMT_TOP_LH7_9", - "CMT_TOP_LH8_0", - "CMT_TOP_LH8_1", - "CMT_TOP_LH8_10", - "CMT_TOP_LH8_11", - "CMT_TOP_LH8_12", - "CMT_TOP_LH8_2", - "CMT_TOP_LH8_3", - "CMT_TOP_LH8_4", - "CMT_TOP_LH8_5", - "CMT_TOP_LH8_6", - "CMT_TOP_LH8_7", - "CMT_TOP_LH8_8", - "CMT_TOP_LH8_9", - "CMT_TOP_LH9_0", - "CMT_TOP_LH9_1", - "CMT_TOP_LH9_10", - "CMT_TOP_LH9_11", - "CMT_TOP_LH9_12", - "CMT_TOP_LH9_2", - "CMT_TOP_LH9_3", - "CMT_TOP_LH9_4", - "CMT_TOP_LH9_5", - "CMT_TOP_LH9_6", - "CMT_TOP_LH9_7", - "CMT_TOP_LH9_8", - "CMT_TOP_LH9_9", - "CMT_TOP_LOGIC_OUTS_L_B0_0", - "CMT_TOP_LOGIC_OUTS_L_B0_1", - "CMT_TOP_LOGIC_OUTS_L_B0_10", - "CMT_TOP_LOGIC_OUTS_L_B0_11", - "CMT_TOP_LOGIC_OUTS_L_B0_12", - "CMT_TOP_LOGIC_OUTS_L_B0_2", - "CMT_TOP_LOGIC_OUTS_L_B0_3", - "CMT_TOP_LOGIC_OUTS_L_B0_4", - "CMT_TOP_LOGIC_OUTS_L_B0_5", - "CMT_TOP_LOGIC_OUTS_L_B0_6", - "CMT_TOP_LOGIC_OUTS_L_B0_7", - "CMT_TOP_LOGIC_OUTS_L_B0_8", - "CMT_TOP_LOGIC_OUTS_L_B0_9", - "CMT_TOP_LOGIC_OUTS_L_B10_0", - "CMT_TOP_LOGIC_OUTS_L_B10_1", - "CMT_TOP_LOGIC_OUTS_L_B10_10", - "CMT_TOP_LOGIC_OUTS_L_B10_11", - "CMT_TOP_LOGIC_OUTS_L_B10_12", - "CMT_TOP_LOGIC_OUTS_L_B10_2", - "CMT_TOP_LOGIC_OUTS_L_B10_3", - "CMT_TOP_LOGIC_OUTS_L_B10_4", - "CMT_TOP_LOGIC_OUTS_L_B10_5", - "CMT_TOP_LOGIC_OUTS_L_B10_6", - "CMT_TOP_LOGIC_OUTS_L_B10_7", - "CMT_TOP_LOGIC_OUTS_L_B10_8", - "CMT_TOP_LOGIC_OUTS_L_B10_9", - "CMT_TOP_LOGIC_OUTS_L_B11_0", - "CMT_TOP_LOGIC_OUTS_L_B11_1", - "CMT_TOP_LOGIC_OUTS_L_B11_10", - "CMT_TOP_LOGIC_OUTS_L_B11_11", - "CMT_TOP_LOGIC_OUTS_L_B11_12", - "CMT_TOP_LOGIC_OUTS_L_B11_2", - "CMT_TOP_LOGIC_OUTS_L_B11_3", - "CMT_TOP_LOGIC_OUTS_L_B11_4", - "CMT_TOP_LOGIC_OUTS_L_B11_5", - "CMT_TOP_LOGIC_OUTS_L_B11_6", - "CMT_TOP_LOGIC_OUTS_L_B11_7", - "CMT_TOP_LOGIC_OUTS_L_B11_8", - "CMT_TOP_LOGIC_OUTS_L_B11_9", - "CMT_TOP_LOGIC_OUTS_L_B12_0", - "CMT_TOP_LOGIC_OUTS_L_B12_1", - "CMT_TOP_LOGIC_OUTS_L_B12_10", - "CMT_TOP_LOGIC_OUTS_L_B12_11", - "CMT_TOP_LOGIC_OUTS_L_B12_12", - "CMT_TOP_LOGIC_OUTS_L_B12_2", - "CMT_TOP_LOGIC_OUTS_L_B12_3", - "CMT_TOP_LOGIC_OUTS_L_B12_4", - "CMT_TOP_LOGIC_OUTS_L_B12_5", - "CMT_TOP_LOGIC_OUTS_L_B12_6", - "CMT_TOP_LOGIC_OUTS_L_B12_7", - "CMT_TOP_LOGIC_OUTS_L_B12_8", - "CMT_TOP_LOGIC_OUTS_L_B12_9", - "CMT_TOP_LOGIC_OUTS_L_B13_0", - "CMT_TOP_LOGIC_OUTS_L_B13_1", - "CMT_TOP_LOGIC_OUTS_L_B13_10", - "CMT_TOP_LOGIC_OUTS_L_B13_11", - "CMT_TOP_LOGIC_OUTS_L_B13_12", - "CMT_TOP_LOGIC_OUTS_L_B13_2", - "CMT_TOP_LOGIC_OUTS_L_B13_3", - "CMT_TOP_LOGIC_OUTS_L_B13_4", - "CMT_TOP_LOGIC_OUTS_L_B13_5", - "CMT_TOP_LOGIC_OUTS_L_B13_6", - "CMT_TOP_LOGIC_OUTS_L_B13_7", - "CMT_TOP_LOGIC_OUTS_L_B13_8", - "CMT_TOP_LOGIC_OUTS_L_B13_9", - "CMT_TOP_LOGIC_OUTS_L_B14_0", - "CMT_TOP_LOGIC_OUTS_L_B14_1", - "CMT_TOP_LOGIC_OUTS_L_B14_10", - "CMT_TOP_LOGIC_OUTS_L_B14_11", - "CMT_TOP_LOGIC_OUTS_L_B14_12", - "CMT_TOP_LOGIC_OUTS_L_B14_2", - "CMT_TOP_LOGIC_OUTS_L_B14_3", - "CMT_TOP_LOGIC_OUTS_L_B14_4", - "CMT_TOP_LOGIC_OUTS_L_B14_5", - "CMT_TOP_LOGIC_OUTS_L_B14_6", - "CMT_TOP_LOGIC_OUTS_L_B14_7", - "CMT_TOP_LOGIC_OUTS_L_B14_8", - "CMT_TOP_LOGIC_OUTS_L_B14_9", - "CMT_TOP_LOGIC_OUTS_L_B15_0", - "CMT_TOP_LOGIC_OUTS_L_B15_1", - "CMT_TOP_LOGIC_OUTS_L_B15_10", - "CMT_TOP_LOGIC_OUTS_L_B15_11", - "CMT_TOP_LOGIC_OUTS_L_B15_12", - "CMT_TOP_LOGIC_OUTS_L_B15_2", - "CMT_TOP_LOGIC_OUTS_L_B15_3", - "CMT_TOP_LOGIC_OUTS_L_B15_4", - "CMT_TOP_LOGIC_OUTS_L_B15_5", - "CMT_TOP_LOGIC_OUTS_L_B15_6", - "CMT_TOP_LOGIC_OUTS_L_B15_7", - "CMT_TOP_LOGIC_OUTS_L_B15_8", - "CMT_TOP_LOGIC_OUTS_L_B15_9", - "CMT_TOP_LOGIC_OUTS_L_B16_0", - "CMT_TOP_LOGIC_OUTS_L_B16_1", - "CMT_TOP_LOGIC_OUTS_L_B16_10", - "CMT_TOP_LOGIC_OUTS_L_B16_11", - "CMT_TOP_LOGIC_OUTS_L_B16_12", - "CMT_TOP_LOGIC_OUTS_L_B16_2", - "CMT_TOP_LOGIC_OUTS_L_B16_3", - "CMT_TOP_LOGIC_OUTS_L_B16_4", - "CMT_TOP_LOGIC_OUTS_L_B16_5", - "CMT_TOP_LOGIC_OUTS_L_B16_6", - "CMT_TOP_LOGIC_OUTS_L_B16_7", - "CMT_TOP_LOGIC_OUTS_L_B16_8", - "CMT_TOP_LOGIC_OUTS_L_B16_9", - "CMT_TOP_LOGIC_OUTS_L_B17_0", - "CMT_TOP_LOGIC_OUTS_L_B17_1", - "CMT_TOP_LOGIC_OUTS_L_B17_10", - "CMT_TOP_LOGIC_OUTS_L_B17_11", - "CMT_TOP_LOGIC_OUTS_L_B17_12", - "CMT_TOP_LOGIC_OUTS_L_B17_2", - "CMT_TOP_LOGIC_OUTS_L_B17_3", - "CMT_TOP_LOGIC_OUTS_L_B17_4", - "CMT_TOP_LOGIC_OUTS_L_B17_5", - "CMT_TOP_LOGIC_OUTS_L_B17_6", - "CMT_TOP_LOGIC_OUTS_L_B17_7", - "CMT_TOP_LOGIC_OUTS_L_B17_8", - "CMT_TOP_LOGIC_OUTS_L_B17_9", - "CMT_TOP_LOGIC_OUTS_L_B18_0", - "CMT_TOP_LOGIC_OUTS_L_B18_1", - "CMT_TOP_LOGIC_OUTS_L_B18_10", - "CMT_TOP_LOGIC_OUTS_L_B18_11", - "CMT_TOP_LOGIC_OUTS_L_B18_12", - "CMT_TOP_LOGIC_OUTS_L_B18_2", - "CMT_TOP_LOGIC_OUTS_L_B18_3", - "CMT_TOP_LOGIC_OUTS_L_B18_4", - "CMT_TOP_LOGIC_OUTS_L_B18_5", - "CMT_TOP_LOGIC_OUTS_L_B18_6", - "CMT_TOP_LOGIC_OUTS_L_B18_7", - "CMT_TOP_LOGIC_OUTS_L_B18_8", - "CMT_TOP_LOGIC_OUTS_L_B18_9", - "CMT_TOP_LOGIC_OUTS_L_B19_0", - "CMT_TOP_LOGIC_OUTS_L_B19_1", - "CMT_TOP_LOGIC_OUTS_L_B19_10", - "CMT_TOP_LOGIC_OUTS_L_B19_11", - "CMT_TOP_LOGIC_OUTS_L_B19_12", - "CMT_TOP_LOGIC_OUTS_L_B19_2", - "CMT_TOP_LOGIC_OUTS_L_B19_3", - "CMT_TOP_LOGIC_OUTS_L_B19_4", - "CMT_TOP_LOGIC_OUTS_L_B19_5", - "CMT_TOP_LOGIC_OUTS_L_B19_6", - "CMT_TOP_LOGIC_OUTS_L_B19_7", - "CMT_TOP_LOGIC_OUTS_L_B19_8", - "CMT_TOP_LOGIC_OUTS_L_B19_9", - "CMT_TOP_LOGIC_OUTS_L_B1_0", - "CMT_TOP_LOGIC_OUTS_L_B1_1", - "CMT_TOP_LOGIC_OUTS_L_B1_10", - "CMT_TOP_LOGIC_OUTS_L_B1_11", - "CMT_TOP_LOGIC_OUTS_L_B1_12", - "CMT_TOP_LOGIC_OUTS_L_B1_2", - "CMT_TOP_LOGIC_OUTS_L_B1_3", - "CMT_TOP_LOGIC_OUTS_L_B1_4", - "CMT_TOP_LOGIC_OUTS_L_B1_5", - "CMT_TOP_LOGIC_OUTS_L_B1_6", - "CMT_TOP_LOGIC_OUTS_L_B1_7", - "CMT_TOP_LOGIC_OUTS_L_B1_8", - "CMT_TOP_LOGIC_OUTS_L_B1_9", - "CMT_TOP_LOGIC_OUTS_L_B20_0", - "CMT_TOP_LOGIC_OUTS_L_B20_1", - "CMT_TOP_LOGIC_OUTS_L_B20_10", - "CMT_TOP_LOGIC_OUTS_L_B20_11", - "CMT_TOP_LOGIC_OUTS_L_B20_12", - "CMT_TOP_LOGIC_OUTS_L_B20_2", - "CMT_TOP_LOGIC_OUTS_L_B20_3", - "CMT_TOP_LOGIC_OUTS_L_B20_4", - "CMT_TOP_LOGIC_OUTS_L_B20_5", - "CMT_TOP_LOGIC_OUTS_L_B20_6", - "CMT_TOP_LOGIC_OUTS_L_B20_7", - "CMT_TOP_LOGIC_OUTS_L_B20_8", - "CMT_TOP_LOGIC_OUTS_L_B20_9", - "CMT_TOP_LOGIC_OUTS_L_B21_0", - "CMT_TOP_LOGIC_OUTS_L_B21_1", - "CMT_TOP_LOGIC_OUTS_L_B21_10", - "CMT_TOP_LOGIC_OUTS_L_B21_11", - "CMT_TOP_LOGIC_OUTS_L_B21_12", - "CMT_TOP_LOGIC_OUTS_L_B21_2", - "CMT_TOP_LOGIC_OUTS_L_B21_3", - "CMT_TOP_LOGIC_OUTS_L_B21_4", - "CMT_TOP_LOGIC_OUTS_L_B21_5", - "CMT_TOP_LOGIC_OUTS_L_B21_6", - "CMT_TOP_LOGIC_OUTS_L_B21_7", - "CMT_TOP_LOGIC_OUTS_L_B21_8", - "CMT_TOP_LOGIC_OUTS_L_B21_9", - "CMT_TOP_LOGIC_OUTS_L_B22_0", - "CMT_TOP_LOGIC_OUTS_L_B22_1", - "CMT_TOP_LOGIC_OUTS_L_B22_10", - "CMT_TOP_LOGIC_OUTS_L_B22_11", - "CMT_TOP_LOGIC_OUTS_L_B22_12", - "CMT_TOP_LOGIC_OUTS_L_B22_2", - "CMT_TOP_LOGIC_OUTS_L_B22_3", - "CMT_TOP_LOGIC_OUTS_L_B22_4", - "CMT_TOP_LOGIC_OUTS_L_B22_5", - "CMT_TOP_LOGIC_OUTS_L_B22_6", - "CMT_TOP_LOGIC_OUTS_L_B22_7", - "CMT_TOP_LOGIC_OUTS_L_B22_8", - "CMT_TOP_LOGIC_OUTS_L_B22_9", - "CMT_TOP_LOGIC_OUTS_L_B23_0", - "CMT_TOP_LOGIC_OUTS_L_B23_1", - "CMT_TOP_LOGIC_OUTS_L_B23_10", - "CMT_TOP_LOGIC_OUTS_L_B23_11", - "CMT_TOP_LOGIC_OUTS_L_B23_12", - "CMT_TOP_LOGIC_OUTS_L_B23_2", - "CMT_TOP_LOGIC_OUTS_L_B23_3", - "CMT_TOP_LOGIC_OUTS_L_B23_4", - "CMT_TOP_LOGIC_OUTS_L_B23_5", - "CMT_TOP_LOGIC_OUTS_L_B23_6", - "CMT_TOP_LOGIC_OUTS_L_B23_7", - "CMT_TOP_LOGIC_OUTS_L_B23_8", - "CMT_TOP_LOGIC_OUTS_L_B23_9", - "CMT_TOP_LOGIC_OUTS_L_B2_0", - "CMT_TOP_LOGIC_OUTS_L_B2_1", - "CMT_TOP_LOGIC_OUTS_L_B2_10", - "CMT_TOP_LOGIC_OUTS_L_B2_11", - "CMT_TOP_LOGIC_OUTS_L_B2_12", - "CMT_TOP_LOGIC_OUTS_L_B2_2", - "CMT_TOP_LOGIC_OUTS_L_B2_3", - "CMT_TOP_LOGIC_OUTS_L_B2_4", - "CMT_TOP_LOGIC_OUTS_L_B2_5", - "CMT_TOP_LOGIC_OUTS_L_B2_6", - "CMT_TOP_LOGIC_OUTS_L_B2_7", - "CMT_TOP_LOGIC_OUTS_L_B2_8", - "CMT_TOP_LOGIC_OUTS_L_B2_9", - "CMT_TOP_LOGIC_OUTS_L_B3_0", - "CMT_TOP_LOGIC_OUTS_L_B3_1", - "CMT_TOP_LOGIC_OUTS_L_B3_10", - "CMT_TOP_LOGIC_OUTS_L_B3_11", - "CMT_TOP_LOGIC_OUTS_L_B3_12", - "CMT_TOP_LOGIC_OUTS_L_B3_2", - "CMT_TOP_LOGIC_OUTS_L_B3_3", - "CMT_TOP_LOGIC_OUTS_L_B3_4", - "CMT_TOP_LOGIC_OUTS_L_B3_5", - "CMT_TOP_LOGIC_OUTS_L_B3_6", - "CMT_TOP_LOGIC_OUTS_L_B3_7", - "CMT_TOP_LOGIC_OUTS_L_B3_8", - "CMT_TOP_LOGIC_OUTS_L_B3_9", - "CMT_TOP_LOGIC_OUTS_L_B4_0", - "CMT_TOP_LOGIC_OUTS_L_B4_1", - "CMT_TOP_LOGIC_OUTS_L_B4_10", - "CMT_TOP_LOGIC_OUTS_L_B4_11", - "CMT_TOP_LOGIC_OUTS_L_B4_12", - "CMT_TOP_LOGIC_OUTS_L_B4_2", - "CMT_TOP_LOGIC_OUTS_L_B4_3", - "CMT_TOP_LOGIC_OUTS_L_B4_4", - "CMT_TOP_LOGIC_OUTS_L_B4_5", - "CMT_TOP_LOGIC_OUTS_L_B4_6", - "CMT_TOP_LOGIC_OUTS_L_B4_7", - "CMT_TOP_LOGIC_OUTS_L_B4_8", - "CMT_TOP_LOGIC_OUTS_L_B4_9", - "CMT_TOP_LOGIC_OUTS_L_B5_0", - "CMT_TOP_LOGIC_OUTS_L_B5_1", - "CMT_TOP_LOGIC_OUTS_L_B5_10", - "CMT_TOP_LOGIC_OUTS_L_B5_11", - "CMT_TOP_LOGIC_OUTS_L_B5_12", - "CMT_TOP_LOGIC_OUTS_L_B5_2", - "CMT_TOP_LOGIC_OUTS_L_B5_3", - "CMT_TOP_LOGIC_OUTS_L_B5_4", - "CMT_TOP_LOGIC_OUTS_L_B5_5", - "CMT_TOP_LOGIC_OUTS_L_B5_6", - "CMT_TOP_LOGIC_OUTS_L_B5_7", - "CMT_TOP_LOGIC_OUTS_L_B5_8", - "CMT_TOP_LOGIC_OUTS_L_B5_9", - "CMT_TOP_LOGIC_OUTS_L_B6_0", - "CMT_TOP_LOGIC_OUTS_L_B6_1", - "CMT_TOP_LOGIC_OUTS_L_B6_10", - "CMT_TOP_LOGIC_OUTS_L_B6_11", - "CMT_TOP_LOGIC_OUTS_L_B6_12", - "CMT_TOP_LOGIC_OUTS_L_B6_2", - "CMT_TOP_LOGIC_OUTS_L_B6_3", - "CMT_TOP_LOGIC_OUTS_L_B6_4", - "CMT_TOP_LOGIC_OUTS_L_B6_5", - "CMT_TOP_LOGIC_OUTS_L_B6_6", - "CMT_TOP_LOGIC_OUTS_L_B6_7", - "CMT_TOP_LOGIC_OUTS_L_B6_8", - "CMT_TOP_LOGIC_OUTS_L_B6_9", - "CMT_TOP_LOGIC_OUTS_L_B7_0", - "CMT_TOP_LOGIC_OUTS_L_B7_1", - "CMT_TOP_LOGIC_OUTS_L_B7_10", - "CMT_TOP_LOGIC_OUTS_L_B7_11", - "CMT_TOP_LOGIC_OUTS_L_B7_12", - "CMT_TOP_LOGIC_OUTS_L_B7_2", - "CMT_TOP_LOGIC_OUTS_L_B7_3", - "CMT_TOP_LOGIC_OUTS_L_B7_4", - "CMT_TOP_LOGIC_OUTS_L_B7_5", - "CMT_TOP_LOGIC_OUTS_L_B7_6", - "CMT_TOP_LOGIC_OUTS_L_B7_7", - "CMT_TOP_LOGIC_OUTS_L_B7_8", - "CMT_TOP_LOGIC_OUTS_L_B7_9", - "CMT_TOP_LOGIC_OUTS_L_B8_0", - "CMT_TOP_LOGIC_OUTS_L_B8_1", - "CMT_TOP_LOGIC_OUTS_L_B8_10", - "CMT_TOP_LOGIC_OUTS_L_B8_11", - "CMT_TOP_LOGIC_OUTS_L_B8_12", - "CMT_TOP_LOGIC_OUTS_L_B8_2", - "CMT_TOP_LOGIC_OUTS_L_B8_3", - "CMT_TOP_LOGIC_OUTS_L_B8_4", - "CMT_TOP_LOGIC_OUTS_L_B8_5", - "CMT_TOP_LOGIC_OUTS_L_B8_6", - "CMT_TOP_LOGIC_OUTS_L_B8_7", - "CMT_TOP_LOGIC_OUTS_L_B8_8", - "CMT_TOP_LOGIC_OUTS_L_B8_9", - "CMT_TOP_LOGIC_OUTS_L_B9_0", - "CMT_TOP_LOGIC_OUTS_L_B9_1", - "CMT_TOP_LOGIC_OUTS_L_B9_10", - "CMT_TOP_LOGIC_OUTS_L_B9_11", - "CMT_TOP_LOGIC_OUTS_L_B9_12", - "CMT_TOP_LOGIC_OUTS_L_B9_2", - "CMT_TOP_LOGIC_OUTS_L_B9_3", - "CMT_TOP_LOGIC_OUTS_L_B9_4", - "CMT_TOP_LOGIC_OUTS_L_B9_5", - "CMT_TOP_LOGIC_OUTS_L_B9_6", - "CMT_TOP_LOGIC_OUTS_L_B9_7", - "CMT_TOP_LOGIC_OUTS_L_B9_8", - "CMT_TOP_LOGIC_OUTS_L_B9_9", - "CMT_TOP_MONITOR_N_0", - "CMT_TOP_MONITOR_N_1", - "CMT_TOP_MONITOR_N_10", - "CMT_TOP_MONITOR_N_11", - "CMT_TOP_MONITOR_N_12", - "CMT_TOP_MONITOR_N_2", - "CMT_TOP_MONITOR_N_3", - "CMT_TOP_MONITOR_N_4", - "CMT_TOP_MONITOR_N_5", - "CMT_TOP_MONITOR_N_6", - "CMT_TOP_MONITOR_N_7", - "CMT_TOP_MONITOR_N_8", - "CMT_TOP_MONITOR_N_9", - "CMT_TOP_MONITOR_P_0", - "CMT_TOP_MONITOR_P_1", - "CMT_TOP_MONITOR_P_10", - "CMT_TOP_MONITOR_P_11", - "CMT_TOP_MONITOR_P_12", - "CMT_TOP_MONITOR_P_2", - "CMT_TOP_MONITOR_P_3", - "CMT_TOP_MONITOR_P_4", - "CMT_TOP_MONITOR_P_5", - "CMT_TOP_MONITOR_P_6", - "CMT_TOP_MONITOR_P_7", - "CMT_TOP_MONITOR_P_8", - "CMT_TOP_MONITOR_P_9", - "CMT_TOP_NE2A0_0", - "CMT_TOP_NE2A0_1", - "CMT_TOP_NE2A0_10", - "CMT_TOP_NE2A0_11", - "CMT_TOP_NE2A0_12", - "CMT_TOP_NE2A0_2", - "CMT_TOP_NE2A0_3", - "CMT_TOP_NE2A0_4", - "CMT_TOP_NE2A0_5", - "CMT_TOP_NE2A0_6", - "CMT_TOP_NE2A0_7", - "CMT_TOP_NE2A0_8", - "CMT_TOP_NE2A0_9", - "CMT_TOP_NE2A1_0", - "CMT_TOP_NE2A1_1", - "CMT_TOP_NE2A1_10", - "CMT_TOP_NE2A1_11", - "CMT_TOP_NE2A1_12", - "CMT_TOP_NE2A1_2", - "CMT_TOP_NE2A1_3", - "CMT_TOP_NE2A1_4", - "CMT_TOP_NE2A1_5", - "CMT_TOP_NE2A1_6", - "CMT_TOP_NE2A1_7", - "CMT_TOP_NE2A1_8", - "CMT_TOP_NE2A1_9", - "CMT_TOP_NE2A2_0", - "CMT_TOP_NE2A2_1", - "CMT_TOP_NE2A2_10", - "CMT_TOP_NE2A2_11", - "CMT_TOP_NE2A2_12", - "CMT_TOP_NE2A2_2", - "CMT_TOP_NE2A2_3", - "CMT_TOP_NE2A2_4", - "CMT_TOP_NE2A2_5", - "CMT_TOP_NE2A2_6", - "CMT_TOP_NE2A2_7", - "CMT_TOP_NE2A2_8", - "CMT_TOP_NE2A2_9", - "CMT_TOP_NE2A3_0", - "CMT_TOP_NE2A3_1", - "CMT_TOP_NE2A3_10", - "CMT_TOP_NE2A3_11", - "CMT_TOP_NE2A3_12", - "CMT_TOP_NE2A3_2", - "CMT_TOP_NE2A3_3", - "CMT_TOP_NE2A3_4", - "CMT_TOP_NE2A3_5", - "CMT_TOP_NE2A3_6", - "CMT_TOP_NE2A3_7", - "CMT_TOP_NE2A3_8", - "CMT_TOP_NE2A3_9", - "CMT_TOP_NE4BEG0_0", - "CMT_TOP_NE4BEG0_1", - "CMT_TOP_NE4BEG0_10", - "CMT_TOP_NE4BEG0_11", - "CMT_TOP_NE4BEG0_12", - "CMT_TOP_NE4BEG0_2", - "CMT_TOP_NE4BEG0_3", - "CMT_TOP_NE4BEG0_4", - "CMT_TOP_NE4BEG0_5", - "CMT_TOP_NE4BEG0_6", - "CMT_TOP_NE4BEG0_7", - "CMT_TOP_NE4BEG0_8", - "CMT_TOP_NE4BEG0_9", - "CMT_TOP_NE4BEG1_0", - "CMT_TOP_NE4BEG1_1", - "CMT_TOP_NE4BEG1_10", - "CMT_TOP_NE4BEG1_11", - "CMT_TOP_NE4BEG1_12", - "CMT_TOP_NE4BEG1_2", - "CMT_TOP_NE4BEG1_3", - "CMT_TOP_NE4BEG1_4", - "CMT_TOP_NE4BEG1_5", - "CMT_TOP_NE4BEG1_6", - "CMT_TOP_NE4BEG1_7", - "CMT_TOP_NE4BEG1_8", - "CMT_TOP_NE4BEG1_9", - "CMT_TOP_NE4BEG2_0", - "CMT_TOP_NE4BEG2_1", - "CMT_TOP_NE4BEG2_10", - "CMT_TOP_NE4BEG2_11", - "CMT_TOP_NE4BEG2_12", - "CMT_TOP_NE4BEG2_2", - "CMT_TOP_NE4BEG2_3", - "CMT_TOP_NE4BEG2_4", - "CMT_TOP_NE4BEG2_5", - "CMT_TOP_NE4BEG2_6", - "CMT_TOP_NE4BEG2_7", - "CMT_TOP_NE4BEG2_8", - "CMT_TOP_NE4BEG2_9", - "CMT_TOP_NE4BEG3_0", - "CMT_TOP_NE4BEG3_1", - "CMT_TOP_NE4BEG3_10", - "CMT_TOP_NE4BEG3_11", - "CMT_TOP_NE4BEG3_12", - "CMT_TOP_NE4BEG3_2", - "CMT_TOP_NE4BEG3_3", - "CMT_TOP_NE4BEG3_4", - "CMT_TOP_NE4BEG3_5", - "CMT_TOP_NE4BEG3_6", - "CMT_TOP_NE4BEG3_7", - "CMT_TOP_NE4BEG3_8", - "CMT_TOP_NE4BEG3_9", - "CMT_TOP_NE4C0_0", - "CMT_TOP_NE4C0_1", - "CMT_TOP_NE4C0_10", - "CMT_TOP_NE4C0_11", - "CMT_TOP_NE4C0_12", - "CMT_TOP_NE4C0_2", - "CMT_TOP_NE4C0_3", - "CMT_TOP_NE4C0_4", - "CMT_TOP_NE4C0_5", - "CMT_TOP_NE4C0_6", - "CMT_TOP_NE4C0_7", - "CMT_TOP_NE4C0_8", - "CMT_TOP_NE4C0_9", - "CMT_TOP_NE4C1_0", - "CMT_TOP_NE4C1_1", - "CMT_TOP_NE4C1_10", - "CMT_TOP_NE4C1_11", - "CMT_TOP_NE4C1_12", - "CMT_TOP_NE4C1_2", - "CMT_TOP_NE4C1_3", - "CMT_TOP_NE4C1_4", - "CMT_TOP_NE4C1_5", - "CMT_TOP_NE4C1_6", - "CMT_TOP_NE4C1_7", - "CMT_TOP_NE4C1_8", - "CMT_TOP_NE4C1_9", - "CMT_TOP_NE4C2_0", - "CMT_TOP_NE4C2_1", - "CMT_TOP_NE4C2_10", - "CMT_TOP_NE4C2_11", - "CMT_TOP_NE4C2_12", - "CMT_TOP_NE4C2_2", - "CMT_TOP_NE4C2_3", - "CMT_TOP_NE4C2_4", - "CMT_TOP_NE4C2_5", - "CMT_TOP_NE4C2_6", - "CMT_TOP_NE4C2_7", - "CMT_TOP_NE4C2_8", - "CMT_TOP_NE4C2_9", - "CMT_TOP_NE4C3_0", - "CMT_TOP_NE4C3_1", - "CMT_TOP_NE4C3_10", - "CMT_TOP_NE4C3_11", - "CMT_TOP_NE4C3_12", - "CMT_TOP_NE4C3_2", - "CMT_TOP_NE4C3_3", - "CMT_TOP_NE4C3_4", - "CMT_TOP_NE4C3_5", - "CMT_TOP_NE4C3_6", - "CMT_TOP_NE4C3_7", - "CMT_TOP_NE4C3_8", - "CMT_TOP_NE4C3_9", - "CMT_TOP_NW2A0_0", - "CMT_TOP_NW2A0_1", - "CMT_TOP_NW2A0_10", - "CMT_TOP_NW2A0_11", - "CMT_TOP_NW2A0_12", - "CMT_TOP_NW2A0_2", - "CMT_TOP_NW2A0_3", - "CMT_TOP_NW2A0_4", - "CMT_TOP_NW2A0_5", - "CMT_TOP_NW2A0_6", - "CMT_TOP_NW2A0_7", - "CMT_TOP_NW2A0_8", - "CMT_TOP_NW2A0_9", - "CMT_TOP_NW2A1_0", - "CMT_TOP_NW2A1_1", - "CMT_TOP_NW2A1_10", - "CMT_TOP_NW2A1_11", - "CMT_TOP_NW2A1_12", - "CMT_TOP_NW2A1_2", - "CMT_TOP_NW2A1_3", - "CMT_TOP_NW2A1_4", - "CMT_TOP_NW2A1_5", - "CMT_TOP_NW2A1_6", - "CMT_TOP_NW2A1_7", - "CMT_TOP_NW2A1_8", - "CMT_TOP_NW2A1_9", - "CMT_TOP_NW2A2_0", - "CMT_TOP_NW2A2_1", - "CMT_TOP_NW2A2_10", - "CMT_TOP_NW2A2_11", - "CMT_TOP_NW2A2_12", - "CMT_TOP_NW2A2_2", - "CMT_TOP_NW2A2_3", - "CMT_TOP_NW2A2_4", - "CMT_TOP_NW2A2_5", - "CMT_TOP_NW2A2_6", - "CMT_TOP_NW2A2_7", - "CMT_TOP_NW2A2_8", - "CMT_TOP_NW2A2_9", - "CMT_TOP_NW2A3_0", - "CMT_TOP_NW2A3_1", - "CMT_TOP_NW2A3_10", - "CMT_TOP_NW2A3_11", - "CMT_TOP_NW2A3_12", - "CMT_TOP_NW2A3_2", - "CMT_TOP_NW2A3_3", - "CMT_TOP_NW2A3_4", - "CMT_TOP_NW2A3_5", - "CMT_TOP_NW2A3_6", - "CMT_TOP_NW2A3_7", - "CMT_TOP_NW2A3_8", - "CMT_TOP_NW2A3_9", - "CMT_TOP_NW4A0_0", - "CMT_TOP_NW4A0_1", - "CMT_TOP_NW4A0_10", - "CMT_TOP_NW4A0_11", - "CMT_TOP_NW4A0_12", - "CMT_TOP_NW4A0_2", - "CMT_TOP_NW4A0_3", - "CMT_TOP_NW4A0_4", - "CMT_TOP_NW4A0_5", - "CMT_TOP_NW4A0_6", - "CMT_TOP_NW4A0_7", - "CMT_TOP_NW4A0_8", - "CMT_TOP_NW4A0_9", - "CMT_TOP_NW4A1_0", - "CMT_TOP_NW4A1_1", - "CMT_TOP_NW4A1_10", - "CMT_TOP_NW4A1_11", - "CMT_TOP_NW4A1_12", - "CMT_TOP_NW4A1_2", - "CMT_TOP_NW4A1_3", - "CMT_TOP_NW4A1_4", - "CMT_TOP_NW4A1_5", - "CMT_TOP_NW4A1_6", - "CMT_TOP_NW4A1_7", - "CMT_TOP_NW4A1_8", - "CMT_TOP_NW4A1_9", - "CMT_TOP_NW4A2_0", - "CMT_TOP_NW4A2_1", - "CMT_TOP_NW4A2_10", - "CMT_TOP_NW4A2_11", - "CMT_TOP_NW4A2_12", - "CMT_TOP_NW4A2_2", - "CMT_TOP_NW4A2_3", - "CMT_TOP_NW4A2_4", - "CMT_TOP_NW4A2_5", - "CMT_TOP_NW4A2_6", - "CMT_TOP_NW4A2_7", - "CMT_TOP_NW4A2_8", - "CMT_TOP_NW4A2_9", - "CMT_TOP_NW4A3_0", - "CMT_TOP_NW4A3_1", - "CMT_TOP_NW4A3_10", - "CMT_TOP_NW4A3_11", - "CMT_TOP_NW4A3_12", - "CMT_TOP_NW4A3_2", - "CMT_TOP_NW4A3_3", - "CMT_TOP_NW4A3_4", - "CMT_TOP_NW4A3_5", - "CMT_TOP_NW4A3_6", - "CMT_TOP_NW4A3_7", - "CMT_TOP_NW4A3_8", - "CMT_TOP_NW4A3_9", - "CMT_TOP_NW4END0_0", - "CMT_TOP_NW4END0_1", - "CMT_TOP_NW4END0_10", - "CMT_TOP_NW4END0_11", - "CMT_TOP_NW4END0_12", - "CMT_TOP_NW4END0_2", - "CMT_TOP_NW4END0_3", - "CMT_TOP_NW4END0_4", - "CMT_TOP_NW4END0_5", - "CMT_TOP_NW4END0_6", - "CMT_TOP_NW4END0_7", - "CMT_TOP_NW4END0_8", - "CMT_TOP_NW4END0_9", - "CMT_TOP_NW4END1_0", - "CMT_TOP_NW4END1_1", - "CMT_TOP_NW4END1_10", - "CMT_TOP_NW4END1_11", - "CMT_TOP_NW4END1_12", - "CMT_TOP_NW4END1_2", - "CMT_TOP_NW4END1_3", - "CMT_TOP_NW4END1_4", - "CMT_TOP_NW4END1_5", - "CMT_TOP_NW4END1_6", - "CMT_TOP_NW4END1_7", - "CMT_TOP_NW4END1_8", - "CMT_TOP_NW4END1_9", - "CMT_TOP_NW4END2_0", - "CMT_TOP_NW4END2_1", - "CMT_TOP_NW4END2_10", - "CMT_TOP_NW4END2_11", - "CMT_TOP_NW4END2_12", - "CMT_TOP_NW4END2_2", - "CMT_TOP_NW4END2_3", - "CMT_TOP_NW4END2_4", - "CMT_TOP_NW4END2_5", - "CMT_TOP_NW4END2_6", - "CMT_TOP_NW4END2_7", - "CMT_TOP_NW4END2_8", - "CMT_TOP_NW4END2_9", - "CMT_TOP_NW4END3_0", - "CMT_TOP_NW4END3_1", - "CMT_TOP_NW4END3_10", - "CMT_TOP_NW4END3_11", - "CMT_TOP_NW4END3_12", - "CMT_TOP_NW4END3_2", - "CMT_TOP_NW4END3_3", - "CMT_TOP_NW4END3_4", - "CMT_TOP_NW4END3_5", - "CMT_TOP_NW4END3_6", - "CMT_TOP_NW4END3_7", - "CMT_TOP_NW4END3_8", - "CMT_TOP_NW4END3_9", - "CMT_TOP_OCLK1X_90_0", - "CMT_TOP_OCLK1X_90_1", - "CMT_TOP_OCLK1X_90_10", - "CMT_TOP_OCLK1X_90_11", - "CMT_TOP_OCLK1X_90_12", - "CMT_TOP_OCLK1X_90_2", - "CMT_TOP_OCLK1X_90_3", - "CMT_TOP_OCLK1X_90_4", - "CMT_TOP_OCLK1X_90_5", - "CMT_TOP_OCLK1X_90_6", - "CMT_TOP_OCLK1X_90_7", - "CMT_TOP_OCLK1X_90_8", - "CMT_TOP_OCLK1X_90_9", - "CMT_TOP_OCLKDIV_0", - "CMT_TOP_OCLKDIV_1", - "CMT_TOP_OCLKDIV_10", - "CMT_TOP_OCLKDIV_11", - "CMT_TOP_OCLKDIV_12", - "CMT_TOP_OCLKDIV_2", - "CMT_TOP_OCLKDIV_3", - "CMT_TOP_OCLKDIV_4", - "CMT_TOP_OCLKDIV_5", - "CMT_TOP_OCLKDIV_6", - "CMT_TOP_OCLKDIV_7", - "CMT_TOP_OCLKDIV_8", - "CMT_TOP_OCLKDIV_9", - "CMT_TOP_OCLK_0", - "CMT_TOP_OCLK_1", - "CMT_TOP_OCLK_10", - "CMT_TOP_OCLK_11", - "CMT_TOP_OCLK_12", - "CMT_TOP_OCLK_2", - "CMT_TOP_OCLK_3", - "CMT_TOP_OCLK_4", - "CMT_TOP_OCLK_5", - "CMT_TOP_OCLK_6", - "CMT_TOP_OCLK_7", - "CMT_TOP_OCLK_8", - "CMT_TOP_OCLK_9", - "CMT_TOP_R_CLKFBOUT2IN", - "CMT_TOP_R_UPPER_T_CLKFBIN", - "CMT_TOP_R_UPPER_T_CLKIN1", - "CMT_TOP_R_UPPER_T_CLKIN2", - "CMT_TOP_R_UPPER_T_CLKPLL0", - "CMT_TOP_R_UPPER_T_CLKPLL1", - "CMT_TOP_R_UPPER_T_CLKPLL2", - "CMT_TOP_R_UPPER_T_CLKPLL3", - "CMT_TOP_R_UPPER_T_CLKPLL4", - "CMT_TOP_R_UPPER_T_CLKPLL5", - "CMT_TOP_R_UPPER_T_CLKPLL6", - "CMT_TOP_R_UPPER_T_CLKPLL7", - "CMT_TOP_R_UPPER_T_FREQ_BB0", - "CMT_TOP_R_UPPER_T_FREQ_BB1", - "CMT_TOP_R_UPPER_T_FREQ_BB2", - "CMT_TOP_R_UPPER_T_FREQ_BB3", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN", - "CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN1", - "CMT_TOP_R_UPPER_T_PLLE2_CLKIN2", - "CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4", - "CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5", - "CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT", - "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT", - "CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR0", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR1", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR2", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR3", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR4", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR5", - "CMT_TOP_R_UPPER_T_PLLE2_DADDR6", - "CMT_TOP_R_UPPER_T_PLLE2_DCLK", - "CMT_TOP_R_UPPER_T_PLLE2_DEN", - "CMT_TOP_R_UPPER_T_PLLE2_DI0", - "CMT_TOP_R_UPPER_T_PLLE2_DI1", - "CMT_TOP_R_UPPER_T_PLLE2_DI10", - "CMT_TOP_R_UPPER_T_PLLE2_DI11", - "CMT_TOP_R_UPPER_T_PLLE2_DI12", - "CMT_TOP_R_UPPER_T_PLLE2_DI13", - "CMT_TOP_R_UPPER_T_PLLE2_DI14", - "CMT_TOP_R_UPPER_T_PLLE2_DI15", - "CMT_TOP_R_UPPER_T_PLLE2_DI2", - "CMT_TOP_R_UPPER_T_PLLE2_DI3", - "CMT_TOP_R_UPPER_T_PLLE2_DI4", - "CMT_TOP_R_UPPER_T_PLLE2_DI5", - "CMT_TOP_R_UPPER_T_PLLE2_DI6", - "CMT_TOP_R_UPPER_T_PLLE2_DI7", - "CMT_TOP_R_UPPER_T_PLLE2_DI8", - "CMT_TOP_R_UPPER_T_PLLE2_DI9", - "CMT_TOP_R_UPPER_T_PLLE2_DO0", - "CMT_TOP_R_UPPER_T_PLLE2_DO1", - "CMT_TOP_R_UPPER_T_PLLE2_DO10", - "CMT_TOP_R_UPPER_T_PLLE2_DO11", - "CMT_TOP_R_UPPER_T_PLLE2_DO12", - "CMT_TOP_R_UPPER_T_PLLE2_DO13", - "CMT_TOP_R_UPPER_T_PLLE2_DO14", - "CMT_TOP_R_UPPER_T_PLLE2_DO15", - "CMT_TOP_R_UPPER_T_PLLE2_DO2", - "CMT_TOP_R_UPPER_T_PLLE2_DO3", - "CMT_TOP_R_UPPER_T_PLLE2_DO4", - "CMT_TOP_R_UPPER_T_PLLE2_DO5", - "CMT_TOP_R_UPPER_T_PLLE2_DO6", - "CMT_TOP_R_UPPER_T_PLLE2_DO7", - "CMT_TOP_R_UPPER_T_PLLE2_DO8", - "CMT_TOP_R_UPPER_T_PLLE2_DO9", - "CMT_TOP_R_UPPER_T_PLLE2_DRDY", - "CMT_TOP_R_UPPER_T_PLLE2_DWE", - "CMT_TOP_R_UPPER_T_PLLE2_LOCKED", - "CMT_TOP_R_UPPER_T_PLLE2_PWRDWN", - "CMT_TOP_R_UPPER_T_PLLE2_RST", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN13", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN14", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN15", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN16", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN17", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN18", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN19", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN20", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN21", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN22", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN23", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN24", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN25", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN26", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN27", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN28", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN29", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN30", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN31", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN4", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTIN9", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT0", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT1", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT10", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT11", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT12", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT13", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT14", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT15", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT16", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT17", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT18", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT19", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT2", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT20", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT21", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT22", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT23", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT24", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT25", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT26", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT27", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT28", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT29", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT3", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT30", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT31", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT32", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT33", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT34", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT35", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT36", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT37", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT38", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT39", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT4", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT40", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT41", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT42", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT43", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT44", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT45", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT46", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT47", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT48", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT49", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT5", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT50", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT51", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT52", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT53", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT54", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT55", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT56", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT57", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT58", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT59", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT6", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT60", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT61", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT62", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT63", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT7", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT8", - "CMT_TOP_R_UPPER_T_PLLE2_TESTOUT9", - "CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT", - "CMT_TOP_SE2A0_0", - "CMT_TOP_SE2A0_1", - "CMT_TOP_SE2A0_10", - "CMT_TOP_SE2A0_11", - "CMT_TOP_SE2A0_12", - "CMT_TOP_SE2A0_2", - "CMT_TOP_SE2A0_3", - "CMT_TOP_SE2A0_4", - "CMT_TOP_SE2A0_5", - "CMT_TOP_SE2A0_6", - "CMT_TOP_SE2A0_7", - "CMT_TOP_SE2A0_8", - "CMT_TOP_SE2A0_9", - "CMT_TOP_SE2A1_0", - "CMT_TOP_SE2A1_1", - "CMT_TOP_SE2A1_10", - "CMT_TOP_SE2A1_11", - "CMT_TOP_SE2A1_12", - "CMT_TOP_SE2A1_2", - "CMT_TOP_SE2A1_3", - "CMT_TOP_SE2A1_4", - "CMT_TOP_SE2A1_5", - "CMT_TOP_SE2A1_6", - "CMT_TOP_SE2A1_7", - "CMT_TOP_SE2A1_8", - "CMT_TOP_SE2A1_9", - "CMT_TOP_SE2A2_0", - "CMT_TOP_SE2A2_1", - "CMT_TOP_SE2A2_10", - "CMT_TOP_SE2A2_11", - "CMT_TOP_SE2A2_12", - "CMT_TOP_SE2A2_2", - "CMT_TOP_SE2A2_3", - "CMT_TOP_SE2A2_4", - "CMT_TOP_SE2A2_5", - "CMT_TOP_SE2A2_6", - "CMT_TOP_SE2A2_7", - "CMT_TOP_SE2A2_8", - "CMT_TOP_SE2A2_9", - "CMT_TOP_SE2A3_0", - "CMT_TOP_SE2A3_1", - "CMT_TOP_SE2A3_10", - "CMT_TOP_SE2A3_11", - "CMT_TOP_SE2A3_12", - "CMT_TOP_SE2A3_2", - "CMT_TOP_SE2A3_3", - "CMT_TOP_SE2A3_4", - "CMT_TOP_SE2A3_5", - "CMT_TOP_SE2A3_6", - "CMT_TOP_SE2A3_7", - "CMT_TOP_SE2A3_8", - "CMT_TOP_SE2A3_9", - "CMT_TOP_SE4BEG0_0", - "CMT_TOP_SE4BEG0_1", - "CMT_TOP_SE4BEG0_10", - "CMT_TOP_SE4BEG0_11", - "CMT_TOP_SE4BEG0_12", - "CMT_TOP_SE4BEG0_2", - "CMT_TOP_SE4BEG0_3", - "CMT_TOP_SE4BEG0_4", - "CMT_TOP_SE4BEG0_5", - "CMT_TOP_SE4BEG0_6", - "CMT_TOP_SE4BEG0_7", - "CMT_TOP_SE4BEG0_8", - "CMT_TOP_SE4BEG0_9", - "CMT_TOP_SE4BEG1_0", - "CMT_TOP_SE4BEG1_1", - "CMT_TOP_SE4BEG1_10", - "CMT_TOP_SE4BEG1_11", - "CMT_TOP_SE4BEG1_12", - "CMT_TOP_SE4BEG1_2", - "CMT_TOP_SE4BEG1_3", - "CMT_TOP_SE4BEG1_4", - "CMT_TOP_SE4BEG1_5", - "CMT_TOP_SE4BEG1_6", - "CMT_TOP_SE4BEG1_7", - "CMT_TOP_SE4BEG1_8", - "CMT_TOP_SE4BEG1_9", - "CMT_TOP_SE4BEG2_0", - "CMT_TOP_SE4BEG2_1", - "CMT_TOP_SE4BEG2_10", - "CMT_TOP_SE4BEG2_11", - "CMT_TOP_SE4BEG2_12", - "CMT_TOP_SE4BEG2_2", - "CMT_TOP_SE4BEG2_3", - "CMT_TOP_SE4BEG2_4", - "CMT_TOP_SE4BEG2_5", - "CMT_TOP_SE4BEG2_6", - "CMT_TOP_SE4BEG2_7", - "CMT_TOP_SE4BEG2_8", - "CMT_TOP_SE4BEG2_9", - "CMT_TOP_SE4BEG3_0", - "CMT_TOP_SE4BEG3_1", - "CMT_TOP_SE4BEG3_10", - "CMT_TOP_SE4BEG3_11", - "CMT_TOP_SE4BEG3_12", - "CMT_TOP_SE4BEG3_2", - "CMT_TOP_SE4BEG3_3", - "CMT_TOP_SE4BEG3_4", - "CMT_TOP_SE4BEG3_5", - "CMT_TOP_SE4BEG3_6", - "CMT_TOP_SE4BEG3_7", - "CMT_TOP_SE4BEG3_8", - "CMT_TOP_SE4BEG3_9", - "CMT_TOP_SE4C0_0", - "CMT_TOP_SE4C0_1", - "CMT_TOP_SE4C0_10", - "CMT_TOP_SE4C0_11", - "CMT_TOP_SE4C0_12", - "CMT_TOP_SE4C0_2", - "CMT_TOP_SE4C0_3", - "CMT_TOP_SE4C0_4", - "CMT_TOP_SE4C0_5", - "CMT_TOP_SE4C0_6", - "CMT_TOP_SE4C0_7", - "CMT_TOP_SE4C0_8", - "CMT_TOP_SE4C0_9", - "CMT_TOP_SE4C1_0", - "CMT_TOP_SE4C1_1", - "CMT_TOP_SE4C1_10", - "CMT_TOP_SE4C1_11", - "CMT_TOP_SE4C1_12", - "CMT_TOP_SE4C1_2", - "CMT_TOP_SE4C1_3", - "CMT_TOP_SE4C1_4", - "CMT_TOP_SE4C1_5", - "CMT_TOP_SE4C1_6", - "CMT_TOP_SE4C1_7", - "CMT_TOP_SE4C1_8", - "CMT_TOP_SE4C1_9", - "CMT_TOP_SE4C2_0", - "CMT_TOP_SE4C2_1", - "CMT_TOP_SE4C2_10", - "CMT_TOP_SE4C2_11", - "CMT_TOP_SE4C2_12", - "CMT_TOP_SE4C2_2", - "CMT_TOP_SE4C2_3", - "CMT_TOP_SE4C2_4", - "CMT_TOP_SE4C2_5", - "CMT_TOP_SE4C2_6", - "CMT_TOP_SE4C2_7", - "CMT_TOP_SE4C2_8", - "CMT_TOP_SE4C2_9", - "CMT_TOP_SE4C3_0", - "CMT_TOP_SE4C3_1", - "CMT_TOP_SE4C3_10", - "CMT_TOP_SE4C3_11", - "CMT_TOP_SE4C3_12", - "CMT_TOP_SE4C3_2", - "CMT_TOP_SE4C3_3", - "CMT_TOP_SE4C3_4", - "CMT_TOP_SE4C3_5", - "CMT_TOP_SE4C3_6", - "CMT_TOP_SE4C3_7", - "CMT_TOP_SE4C3_8", - "CMT_TOP_SE4C3_9", - "CMT_TOP_SW2A0_0", - "CMT_TOP_SW2A0_1", - "CMT_TOP_SW2A0_10", - "CMT_TOP_SW2A0_11", - "CMT_TOP_SW2A0_12", - "CMT_TOP_SW2A0_2", - "CMT_TOP_SW2A0_3", - "CMT_TOP_SW2A0_4", - "CMT_TOP_SW2A0_5", - "CMT_TOP_SW2A0_6", - "CMT_TOP_SW2A0_7", - "CMT_TOP_SW2A0_8", - "CMT_TOP_SW2A0_9", - "CMT_TOP_SW2A1_0", - "CMT_TOP_SW2A1_1", - "CMT_TOP_SW2A1_10", - "CMT_TOP_SW2A1_11", - "CMT_TOP_SW2A1_12", - "CMT_TOP_SW2A1_2", - "CMT_TOP_SW2A1_3", - "CMT_TOP_SW2A1_4", - "CMT_TOP_SW2A1_5", - "CMT_TOP_SW2A1_6", - "CMT_TOP_SW2A1_7", - "CMT_TOP_SW2A1_8", - "CMT_TOP_SW2A1_9", - "CMT_TOP_SW2A2_0", - "CMT_TOP_SW2A2_1", - "CMT_TOP_SW2A2_10", - "CMT_TOP_SW2A2_11", - "CMT_TOP_SW2A2_12", - "CMT_TOP_SW2A2_2", - "CMT_TOP_SW2A2_3", - "CMT_TOP_SW2A2_4", - "CMT_TOP_SW2A2_5", - "CMT_TOP_SW2A2_6", - "CMT_TOP_SW2A2_7", - "CMT_TOP_SW2A2_8", - "CMT_TOP_SW2A2_9", - "CMT_TOP_SW2A3_0", - "CMT_TOP_SW2A3_1", - "CMT_TOP_SW2A3_10", - "CMT_TOP_SW2A3_11", - "CMT_TOP_SW2A3_12", - "CMT_TOP_SW2A3_2", - "CMT_TOP_SW2A3_3", - "CMT_TOP_SW2A3_4", - "CMT_TOP_SW2A3_5", - "CMT_TOP_SW2A3_6", - "CMT_TOP_SW2A3_7", - "CMT_TOP_SW2A3_8", - "CMT_TOP_SW2A3_9", - "CMT_TOP_SW4A0_0", - "CMT_TOP_SW4A0_1", - "CMT_TOP_SW4A0_10", - "CMT_TOP_SW4A0_11", - "CMT_TOP_SW4A0_12", - "CMT_TOP_SW4A0_2", - "CMT_TOP_SW4A0_3", - "CMT_TOP_SW4A0_4", - "CMT_TOP_SW4A0_5", - "CMT_TOP_SW4A0_6", - "CMT_TOP_SW4A0_7", - "CMT_TOP_SW4A0_8", - "CMT_TOP_SW4A0_9", - "CMT_TOP_SW4A1_0", - "CMT_TOP_SW4A1_1", - "CMT_TOP_SW4A1_10", - "CMT_TOP_SW4A1_11", - "CMT_TOP_SW4A1_12", - "CMT_TOP_SW4A1_2", - "CMT_TOP_SW4A1_3", - "CMT_TOP_SW4A1_4", - "CMT_TOP_SW4A1_5", - "CMT_TOP_SW4A1_6", - "CMT_TOP_SW4A1_7", - "CMT_TOP_SW4A1_8", - "CMT_TOP_SW4A1_9", - "CMT_TOP_SW4A2_0", - "CMT_TOP_SW4A2_1", - "CMT_TOP_SW4A2_10", - "CMT_TOP_SW4A2_11", - "CMT_TOP_SW4A2_12", - "CMT_TOP_SW4A2_2", - "CMT_TOP_SW4A2_3", - "CMT_TOP_SW4A2_4", - "CMT_TOP_SW4A2_5", - "CMT_TOP_SW4A2_6", - "CMT_TOP_SW4A2_7", - "CMT_TOP_SW4A2_8", - "CMT_TOP_SW4A2_9", - "CMT_TOP_SW4A3_0", - "CMT_TOP_SW4A3_1", - "CMT_TOP_SW4A3_10", - "CMT_TOP_SW4A3_11", - "CMT_TOP_SW4A3_12", - "CMT_TOP_SW4A3_2", - "CMT_TOP_SW4A3_3", - "CMT_TOP_SW4A3_4", - "CMT_TOP_SW4A3_5", - "CMT_TOP_SW4A3_6", - "CMT_TOP_SW4A3_7", - "CMT_TOP_SW4A3_8", - "CMT_TOP_SW4A3_9", - "CMT_TOP_SW4END0_0", - "CMT_TOP_SW4END0_1", - "CMT_TOP_SW4END0_10", - "CMT_TOP_SW4END0_11", - "CMT_TOP_SW4END0_12", - "CMT_TOP_SW4END0_2", - "CMT_TOP_SW4END0_3", - "CMT_TOP_SW4END0_4", - "CMT_TOP_SW4END0_5", - "CMT_TOP_SW4END0_6", - "CMT_TOP_SW4END0_7", - "CMT_TOP_SW4END0_8", - "CMT_TOP_SW4END0_9", - "CMT_TOP_SW4END1_0", - "CMT_TOP_SW4END1_1", - "CMT_TOP_SW4END1_10", - "CMT_TOP_SW4END1_11", - "CMT_TOP_SW4END1_12", - "CMT_TOP_SW4END1_2", - "CMT_TOP_SW4END1_3", - "CMT_TOP_SW4END1_4", - "CMT_TOP_SW4END1_5", - "CMT_TOP_SW4END1_6", - "CMT_TOP_SW4END1_7", - "CMT_TOP_SW4END1_8", - "CMT_TOP_SW4END1_9", - "CMT_TOP_SW4END2_0", - "CMT_TOP_SW4END2_1", - "CMT_TOP_SW4END2_10", - "CMT_TOP_SW4END2_11", - "CMT_TOP_SW4END2_12", - "CMT_TOP_SW4END2_2", - "CMT_TOP_SW4END2_3", - "CMT_TOP_SW4END2_4", - "CMT_TOP_SW4END2_5", - "CMT_TOP_SW4END2_6", - "CMT_TOP_SW4END2_7", - "CMT_TOP_SW4END2_8", - "CMT_TOP_SW4END2_9", - "CMT_TOP_SW4END3_0", - "CMT_TOP_SW4END3_1", - "CMT_TOP_SW4END3_10", - "CMT_TOP_SW4END3_11", - "CMT_TOP_SW4END3_12", - "CMT_TOP_SW4END3_2", - "CMT_TOP_SW4END3_3", - "CMT_TOP_SW4END3_4", - "CMT_TOP_SW4END3_5", - "CMT_TOP_SW4END3_6", - "CMT_TOP_SW4END3_7", - "CMT_TOP_SW4END3_8", - "CMT_TOP_SW4END3_9", - "CMT_TOP_WL1END0_0", - "CMT_TOP_WL1END0_1", - "CMT_TOP_WL1END0_10", - "CMT_TOP_WL1END0_11", - "CMT_TOP_WL1END0_12", - "CMT_TOP_WL1END0_2", - "CMT_TOP_WL1END0_3", - "CMT_TOP_WL1END0_4", - "CMT_TOP_WL1END0_5", - "CMT_TOP_WL1END0_6", - "CMT_TOP_WL1END0_7", - "CMT_TOP_WL1END0_8", - "CMT_TOP_WL1END0_9", - "CMT_TOP_WL1END1_0", - "CMT_TOP_WL1END1_1", - "CMT_TOP_WL1END1_10", - "CMT_TOP_WL1END1_11", - "CMT_TOP_WL1END1_12", - "CMT_TOP_WL1END1_2", - "CMT_TOP_WL1END1_3", - "CMT_TOP_WL1END1_4", - "CMT_TOP_WL1END1_5", - "CMT_TOP_WL1END1_6", - "CMT_TOP_WL1END1_7", - "CMT_TOP_WL1END1_8", - "CMT_TOP_WL1END1_9", - "CMT_TOP_WL1END2_0", - "CMT_TOP_WL1END2_1", - "CMT_TOP_WL1END2_10", - "CMT_TOP_WL1END2_11", - "CMT_TOP_WL1END2_12", - "CMT_TOP_WL1END2_2", - "CMT_TOP_WL1END2_3", - "CMT_TOP_WL1END2_4", - "CMT_TOP_WL1END2_5", - "CMT_TOP_WL1END2_6", - "CMT_TOP_WL1END2_7", - "CMT_TOP_WL1END2_8", - "CMT_TOP_WL1END2_9", - "CMT_TOP_WL1END3_0", - "CMT_TOP_WL1END3_1", - "CMT_TOP_WL1END3_10", - "CMT_TOP_WL1END3_11", - "CMT_TOP_WL1END3_12", - "CMT_TOP_WL1END3_2", - "CMT_TOP_WL1END3_3", - "CMT_TOP_WL1END3_4", - "CMT_TOP_WL1END3_5", - "CMT_TOP_WL1END3_6", - "CMT_TOP_WL1END3_7", - "CMT_TOP_WL1END3_8", - "CMT_TOP_WL1END3_9", - "CMT_TOP_WR1END0_0", - "CMT_TOP_WR1END0_1", - "CMT_TOP_WR1END0_10", - "CMT_TOP_WR1END0_11", - "CMT_TOP_WR1END0_12", - "CMT_TOP_WR1END0_2", - "CMT_TOP_WR1END0_3", - "CMT_TOP_WR1END0_4", - "CMT_TOP_WR1END0_5", - "CMT_TOP_WR1END0_6", - "CMT_TOP_WR1END0_7", - "CMT_TOP_WR1END0_8", - "CMT_TOP_WR1END0_9", - "CMT_TOP_WR1END1_0", - "CMT_TOP_WR1END1_1", - "CMT_TOP_WR1END1_10", - "CMT_TOP_WR1END1_11", - "CMT_TOP_WR1END1_12", - "CMT_TOP_WR1END1_2", - "CMT_TOP_WR1END1_3", - "CMT_TOP_WR1END1_4", - "CMT_TOP_WR1END1_5", - "CMT_TOP_WR1END1_6", - "CMT_TOP_WR1END1_7", - "CMT_TOP_WR1END1_8", - "CMT_TOP_WR1END1_9", - "CMT_TOP_WR1END2_0", - "CMT_TOP_WR1END2_1", - "CMT_TOP_WR1END2_10", - "CMT_TOP_WR1END2_11", - "CMT_TOP_WR1END2_12", - "CMT_TOP_WR1END2_2", - "CMT_TOP_WR1END2_3", - "CMT_TOP_WR1END2_4", - "CMT_TOP_WR1END2_5", - "CMT_TOP_WR1END2_6", - "CMT_TOP_WR1END2_7", - "CMT_TOP_WR1END2_8", - "CMT_TOP_WR1END2_9", - "CMT_TOP_WR1END3_0", - "CMT_TOP_WR1END3_1", - "CMT_TOP_WR1END3_10", - "CMT_TOP_WR1END3_11", - "CMT_TOP_WR1END3_12", - "CMT_TOP_WR1END3_2", - "CMT_TOP_WR1END3_3", - "CMT_TOP_WR1END3_4", - "CMT_TOP_WR1END3_5", - "CMT_TOP_WR1END3_6", - "CMT_TOP_WR1END3_7", - "CMT_TOP_WR1END3_8", - "CMT_TOP_WR1END3_9", - "CMT_TOP_WW2A0_0", - "CMT_TOP_WW2A0_1", - "CMT_TOP_WW2A0_10", - "CMT_TOP_WW2A0_11", - "CMT_TOP_WW2A0_12", - "CMT_TOP_WW2A0_2", - "CMT_TOP_WW2A0_3", - "CMT_TOP_WW2A0_4", - "CMT_TOP_WW2A0_5", - "CMT_TOP_WW2A0_6", - "CMT_TOP_WW2A0_7", - "CMT_TOP_WW2A0_8", - "CMT_TOP_WW2A0_9", - "CMT_TOP_WW2A1_0", - "CMT_TOP_WW2A1_1", - "CMT_TOP_WW2A1_10", - "CMT_TOP_WW2A1_11", - "CMT_TOP_WW2A1_12", - "CMT_TOP_WW2A1_2", - "CMT_TOP_WW2A1_3", - "CMT_TOP_WW2A1_4", - "CMT_TOP_WW2A1_5", - "CMT_TOP_WW2A1_6", - "CMT_TOP_WW2A1_7", - "CMT_TOP_WW2A1_8", - "CMT_TOP_WW2A1_9", - "CMT_TOP_WW2A2_0", - "CMT_TOP_WW2A2_1", - "CMT_TOP_WW2A2_10", - "CMT_TOP_WW2A2_11", - "CMT_TOP_WW2A2_12", - "CMT_TOP_WW2A2_2", - "CMT_TOP_WW2A2_3", - "CMT_TOP_WW2A2_4", - "CMT_TOP_WW2A2_5", - "CMT_TOP_WW2A2_6", - "CMT_TOP_WW2A2_7", - "CMT_TOP_WW2A2_8", - "CMT_TOP_WW2A2_9", - "CMT_TOP_WW2A3_0", - "CMT_TOP_WW2A3_1", - "CMT_TOP_WW2A3_10", - "CMT_TOP_WW2A3_11", - "CMT_TOP_WW2A3_12", - "CMT_TOP_WW2A3_2", - "CMT_TOP_WW2A3_3", - "CMT_TOP_WW2A3_4", - "CMT_TOP_WW2A3_5", - "CMT_TOP_WW2A3_6", - "CMT_TOP_WW2A3_7", - "CMT_TOP_WW2A3_8", - "CMT_TOP_WW2A3_9", - "CMT_TOP_WW2END0_0", - "CMT_TOP_WW2END0_1", - "CMT_TOP_WW2END0_10", - "CMT_TOP_WW2END0_11", - "CMT_TOP_WW2END0_12", - "CMT_TOP_WW2END0_2", - "CMT_TOP_WW2END0_3", - "CMT_TOP_WW2END0_4", - "CMT_TOP_WW2END0_5", - "CMT_TOP_WW2END0_6", - "CMT_TOP_WW2END0_7", - "CMT_TOP_WW2END0_8", - "CMT_TOP_WW2END0_9", - "CMT_TOP_WW2END1_0", - "CMT_TOP_WW2END1_1", - "CMT_TOP_WW2END1_10", - "CMT_TOP_WW2END1_11", - "CMT_TOP_WW2END1_12", - "CMT_TOP_WW2END1_2", - "CMT_TOP_WW2END1_3", - "CMT_TOP_WW2END1_4", - "CMT_TOP_WW2END1_5", - "CMT_TOP_WW2END1_6", - "CMT_TOP_WW2END1_7", - "CMT_TOP_WW2END1_8", - "CMT_TOP_WW2END1_9", - "CMT_TOP_WW2END2_0", - "CMT_TOP_WW2END2_1", - "CMT_TOP_WW2END2_10", - "CMT_TOP_WW2END2_11", - "CMT_TOP_WW2END2_12", - "CMT_TOP_WW2END2_2", - "CMT_TOP_WW2END2_3", - "CMT_TOP_WW2END2_4", - "CMT_TOP_WW2END2_5", - "CMT_TOP_WW2END2_6", - "CMT_TOP_WW2END2_7", - "CMT_TOP_WW2END2_8", - "CMT_TOP_WW2END2_9", - "CMT_TOP_WW2END3_0", - "CMT_TOP_WW2END3_1", - "CMT_TOP_WW2END3_10", - "CMT_TOP_WW2END3_11", - "CMT_TOP_WW2END3_12", - "CMT_TOP_WW2END3_2", - "CMT_TOP_WW2END3_3", - "CMT_TOP_WW2END3_4", - "CMT_TOP_WW2END3_5", - "CMT_TOP_WW2END3_6", - "CMT_TOP_WW2END3_7", - "CMT_TOP_WW2END3_8", - "CMT_TOP_WW2END3_9", - "CMT_TOP_WW4A0_0", - "CMT_TOP_WW4A0_1", - "CMT_TOP_WW4A0_10", - "CMT_TOP_WW4A0_11", - "CMT_TOP_WW4A0_12", - "CMT_TOP_WW4A0_2", - "CMT_TOP_WW4A0_3", - "CMT_TOP_WW4A0_4", - "CMT_TOP_WW4A0_5", - "CMT_TOP_WW4A0_6", - "CMT_TOP_WW4A0_7", - "CMT_TOP_WW4A0_8", - "CMT_TOP_WW4A0_9", - "CMT_TOP_WW4A1_0", - "CMT_TOP_WW4A1_1", - "CMT_TOP_WW4A1_10", - "CMT_TOP_WW4A1_11", - "CMT_TOP_WW4A1_12", - "CMT_TOP_WW4A1_2", - "CMT_TOP_WW4A1_3", - "CMT_TOP_WW4A1_4", - "CMT_TOP_WW4A1_5", - "CMT_TOP_WW4A1_6", - "CMT_TOP_WW4A1_7", - "CMT_TOP_WW4A1_8", - "CMT_TOP_WW4A1_9", - "CMT_TOP_WW4A2_0", - "CMT_TOP_WW4A2_1", - "CMT_TOP_WW4A2_10", - "CMT_TOP_WW4A2_11", - "CMT_TOP_WW4A2_12", - "CMT_TOP_WW4A2_2", - "CMT_TOP_WW4A2_3", - "CMT_TOP_WW4A2_4", - "CMT_TOP_WW4A2_5", - "CMT_TOP_WW4A2_6", - "CMT_TOP_WW4A2_7", - "CMT_TOP_WW4A2_8", - "CMT_TOP_WW4A2_9", - "CMT_TOP_WW4A3_0", - "CMT_TOP_WW4A3_1", - "CMT_TOP_WW4A3_10", - "CMT_TOP_WW4A3_11", - "CMT_TOP_WW4A3_12", - "CMT_TOP_WW4A3_2", - "CMT_TOP_WW4A3_3", - "CMT_TOP_WW4A3_4", - "CMT_TOP_WW4A3_5", - "CMT_TOP_WW4A3_6", - "CMT_TOP_WW4A3_7", - "CMT_TOP_WW4A3_8", - "CMT_TOP_WW4A3_9", - "CMT_TOP_WW4B0_0", - "CMT_TOP_WW4B0_1", - "CMT_TOP_WW4B0_10", - "CMT_TOP_WW4B0_11", - "CMT_TOP_WW4B0_12", - "CMT_TOP_WW4B0_2", - "CMT_TOP_WW4B0_3", - "CMT_TOP_WW4B0_4", - "CMT_TOP_WW4B0_5", - "CMT_TOP_WW4B0_6", - "CMT_TOP_WW4B0_7", - "CMT_TOP_WW4B0_8", - "CMT_TOP_WW4B0_9", - "CMT_TOP_WW4B1_0", - "CMT_TOP_WW4B1_1", - "CMT_TOP_WW4B1_10", - "CMT_TOP_WW4B1_11", - "CMT_TOP_WW4B1_12", - "CMT_TOP_WW4B1_2", - "CMT_TOP_WW4B1_3", - "CMT_TOP_WW4B1_4", - "CMT_TOP_WW4B1_5", - "CMT_TOP_WW4B1_6", - "CMT_TOP_WW4B1_7", - "CMT_TOP_WW4B1_8", - "CMT_TOP_WW4B1_9", - "CMT_TOP_WW4B2_0", - "CMT_TOP_WW4B2_1", - "CMT_TOP_WW4B2_10", - "CMT_TOP_WW4B2_11", - "CMT_TOP_WW4B2_12", - "CMT_TOP_WW4B2_2", - "CMT_TOP_WW4B2_3", - "CMT_TOP_WW4B2_4", - "CMT_TOP_WW4B2_5", - "CMT_TOP_WW4B2_6", - "CMT_TOP_WW4B2_7", - "CMT_TOP_WW4B2_8", - "CMT_TOP_WW4B2_9", - "CMT_TOP_WW4B3_0", - "CMT_TOP_WW4B3_1", - "CMT_TOP_WW4B3_10", - "CMT_TOP_WW4B3_11", - "CMT_TOP_WW4B3_12", - "CMT_TOP_WW4B3_2", - "CMT_TOP_WW4B3_3", - "CMT_TOP_WW4B3_4", - "CMT_TOP_WW4B3_5", - "CMT_TOP_WW4B3_6", - "CMT_TOP_WW4B3_7", - "CMT_TOP_WW4B3_8", - "CMT_TOP_WW4B3_9", - "CMT_TOP_WW4C0_0", - "CMT_TOP_WW4C0_1", - "CMT_TOP_WW4C0_10", - "CMT_TOP_WW4C0_11", - "CMT_TOP_WW4C0_12", - "CMT_TOP_WW4C0_2", - "CMT_TOP_WW4C0_3", - "CMT_TOP_WW4C0_4", - "CMT_TOP_WW4C0_5", - "CMT_TOP_WW4C0_6", - "CMT_TOP_WW4C0_7", - "CMT_TOP_WW4C0_8", - "CMT_TOP_WW4C0_9", - "CMT_TOP_WW4C1_0", - "CMT_TOP_WW4C1_1", - "CMT_TOP_WW4C1_10", - "CMT_TOP_WW4C1_11", - "CMT_TOP_WW4C1_12", - "CMT_TOP_WW4C1_2", - "CMT_TOP_WW4C1_3", - "CMT_TOP_WW4C1_4", - "CMT_TOP_WW4C1_5", - "CMT_TOP_WW4C1_6", - "CMT_TOP_WW4C1_7", - "CMT_TOP_WW4C1_8", - "CMT_TOP_WW4C1_9", - "CMT_TOP_WW4C2_0", - "CMT_TOP_WW4C2_1", - "CMT_TOP_WW4C2_10", - "CMT_TOP_WW4C2_11", - "CMT_TOP_WW4C2_12", - "CMT_TOP_WW4C2_2", - "CMT_TOP_WW4C2_3", - "CMT_TOP_WW4C2_4", - "CMT_TOP_WW4C2_5", - "CMT_TOP_WW4C2_6", - "CMT_TOP_WW4C2_7", - "CMT_TOP_WW4C2_8", - "CMT_TOP_WW4C2_9", - "CMT_TOP_WW4C3_0", - "CMT_TOP_WW4C3_1", - "CMT_TOP_WW4C3_10", - "CMT_TOP_WW4C3_11", - "CMT_TOP_WW4C3_12", - "CMT_TOP_WW4C3_2", - "CMT_TOP_WW4C3_3", - "CMT_TOP_WW4C3_4", - "CMT_TOP_WW4C3_5", - "CMT_TOP_WW4C3_6", - "CMT_TOP_WW4C3_7", - "CMT_TOP_WW4C3_8", - "CMT_TOP_WW4C3_9", - "CMT_TOP_WW4END0_0", - "CMT_TOP_WW4END0_1", - "CMT_TOP_WW4END0_10", - "CMT_TOP_WW4END0_11", - "CMT_TOP_WW4END0_12", - "CMT_TOP_WW4END0_2", - "CMT_TOP_WW4END0_3", - "CMT_TOP_WW4END0_4", - "CMT_TOP_WW4END0_5", - "CMT_TOP_WW4END0_6", - "CMT_TOP_WW4END0_7", - "CMT_TOP_WW4END0_8", - "CMT_TOP_WW4END0_9", - "CMT_TOP_WW4END1_0", - "CMT_TOP_WW4END1_1", - "CMT_TOP_WW4END1_10", - "CMT_TOP_WW4END1_11", - "CMT_TOP_WW4END1_12", - "CMT_TOP_WW4END1_2", - "CMT_TOP_WW4END1_3", - "CMT_TOP_WW4END1_4", - "CMT_TOP_WW4END1_5", - "CMT_TOP_WW4END1_6", - "CMT_TOP_WW4END1_7", - "CMT_TOP_WW4END1_8", - "CMT_TOP_WW4END1_9", - "CMT_TOP_WW4END2_0", - "CMT_TOP_WW4END2_1", - "CMT_TOP_WW4END2_10", - "CMT_TOP_WW4END2_11", - "CMT_TOP_WW4END2_12", - "CMT_TOP_WW4END2_2", - "CMT_TOP_WW4END2_3", - "CMT_TOP_WW4END2_4", - "CMT_TOP_WW4END2_5", - "CMT_TOP_WW4END2_6", - "CMT_TOP_WW4END2_7", - "CMT_TOP_WW4END2_8", - "CMT_TOP_WW4END2_9", - "CMT_TOP_WW4END3_0", - "CMT_TOP_WW4END3_1", - "CMT_TOP_WW4END3_10", - "CMT_TOP_WW4END3_11", - "CMT_TOP_WW4END3_12", - "CMT_TOP_WW4END3_2", - "CMT_TOP_WW4END3_3", - "CMT_TOP_WW4END3_4", - "CMT_TOP_WW4END3_5", - "CMT_TOP_WW4END3_6", - "CMT_TOP_WW4END3_7", - "CMT_TOP_WW4END3_8", - "CMT_TOP_WW4END3_9", - "PLLOUT_CLK_FREQ_BB_0", - "PLLOUT_CLK_FREQ_BB_1", - "PLLOUT_CLK_FREQ_BB_2", - "PLLOUT_CLK_FREQ_BB_3", - "PLL_CLK_FREQ_BB0_NS", - "PLL_CLK_FREQ_BB1_NS", - "PLL_CLK_FREQ_BB2_NS", - "PLL_CLK_FREQ_BB3_NS", - "PLL_CLK_FREQ_BB_BUFOUT_NS0", - "PLL_CLK_FREQ_BB_BUFOUT_NS1", - "PLL_CLK_FREQ_BB_BUFOUT_NS2", - "PLL_CLK_FREQ_BB_BUFOUT_NS3" - ] + "wires": { + "CMT_PHASER_D_ICLKDIV_TOIOI": null, + "CMT_PHASER_D_ICLK_TOIOI": null, + "CMT_PHASER_D_OCLK90_TOIOI": null, + "CMT_PHASER_D_OCLKDIV_TOIOI": null, + "CMT_PHASER_D_OCLK_TOIOI": null, + "CMT_PLL_DQS_TO_PHASER_D": null, + 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"res": "317.510" + }, + "CMT_TOP_WW4END3_6": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_7": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_8": { + "cap": "78.000", + "res": "317.510" + }, + "CMT_TOP_WW4END3_9": { + "cap": "78.000", + "res": "317.510" + }, + "PLLOUT_CLK_FREQ_BB_0": null, + "PLLOUT_CLK_FREQ_BB_1": null, + "PLLOUT_CLK_FREQ_BB_2": null, + "PLLOUT_CLK_FREQ_BB_3": null, + "PLL_CLK_FREQ_BB0_NS": null, + "PLL_CLK_FREQ_BB1_NS": null, + "PLL_CLK_FREQ_BB2_NS": null, + "PLL_CLK_FREQ_BB3_NS": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS0": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS1": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS2": null, + "PLL_CLK_FREQ_BB_BUFOUT_NS3": null + } } diff --git a/kintex7/tile_type_DSP_L.json b/kintex7/tile_type_DSP_L.json index 20bcc83..5e3c705 100644 --- a/kintex7/tile_type_DSP_L.json +++ b/kintex7/tile_type_DSP_L.json @@ -2,5560 +2,14294 @@ "pips": { "DSP_L.DSP_0_ACOUT0->DSP_1_ACIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT0" }, "DSP_L.DSP_0_ACOUT1->DSP_1_ACIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT1" }, "DSP_L.DSP_0_ACOUT10->DSP_1_ACIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT10" }, "DSP_L.DSP_0_ACOUT11->DSP_1_ACIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT11" }, "DSP_L.DSP_0_ACOUT12->DSP_1_ACIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT12" }, "DSP_L.DSP_0_ACOUT13->DSP_1_ACIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT13" }, "DSP_L.DSP_0_ACOUT14->DSP_1_ACIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT14" }, "DSP_L.DSP_0_ACOUT15->DSP_1_ACIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT15" }, "DSP_L.DSP_0_ACOUT16->DSP_1_ACIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT16" }, "DSP_L.DSP_0_ACOUT17->DSP_1_ACIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT17" }, "DSP_L.DSP_0_ACOUT18->DSP_1_ACIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT18" }, "DSP_L.DSP_0_ACOUT19->DSP_1_ACIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT19" }, "DSP_L.DSP_0_ACOUT2->DSP_1_ACIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT2" }, "DSP_L.DSP_0_ACOUT20->DSP_1_ACIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT20" }, "DSP_L.DSP_0_ACOUT21->DSP_1_ACIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT21" }, "DSP_L.DSP_0_ACOUT22->DSP_1_ACIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT22" }, "DSP_L.DSP_0_ACOUT23->DSP_1_ACIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT23" }, "DSP_L.DSP_0_ACOUT24->DSP_1_ACIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT24" }, "DSP_L.DSP_0_ACOUT25->DSP_1_ACIN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT25" }, "DSP_L.DSP_0_ACOUT26->DSP_1_ACIN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT26" }, "DSP_L.DSP_0_ACOUT27->DSP_1_ACIN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT27" }, "DSP_L.DSP_0_ACOUT28->DSP_1_ACIN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT28" }, "DSP_L.DSP_0_ACOUT29->DSP_1_ACIN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT29" }, "DSP_L.DSP_0_ACOUT3->DSP_1_ACIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT3" }, "DSP_L.DSP_0_ACOUT4->DSP_1_ACIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT4" }, "DSP_L.DSP_0_ACOUT5->DSP_1_ACIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT5" }, "DSP_L.DSP_0_ACOUT6->DSP_1_ACIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT6" }, "DSP_L.DSP_0_ACOUT7->DSP_1_ACIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT7" }, "DSP_L.DSP_0_ACOUT8->DSP_1_ACIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT8" }, "DSP_L.DSP_0_ACOUT9->DSP_1_ACIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT9" }, "DSP_L.DSP_0_BCOUT0->DSP_1_BCIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT0" }, "DSP_L.DSP_0_BCOUT1->DSP_1_BCIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT1" }, "DSP_L.DSP_0_BCOUT10->DSP_1_BCIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT10" }, "DSP_L.DSP_0_BCOUT11->DSP_1_BCIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT11" }, "DSP_L.DSP_0_BCOUT12->DSP_1_BCIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT12" }, "DSP_L.DSP_0_BCOUT13->DSP_1_BCIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT13" }, "DSP_L.DSP_0_BCOUT14->DSP_1_BCIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT14" }, "DSP_L.DSP_0_BCOUT15->DSP_1_BCIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT15" }, "DSP_L.DSP_0_BCOUT16->DSP_1_BCIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT16" }, "DSP_L.DSP_0_BCOUT17->DSP_1_BCIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT17" }, "DSP_L.DSP_0_BCOUT2->DSP_1_BCIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT2" }, "DSP_L.DSP_0_BCOUT3->DSP_1_BCIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT3" }, "DSP_L.DSP_0_BCOUT4->DSP_1_BCIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT4" }, "DSP_L.DSP_0_BCOUT5->DSP_1_BCIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT5" }, "DSP_L.DSP_0_BCOUT6->DSP_1_BCIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT6" }, "DSP_L.DSP_0_BCOUT7->DSP_1_BCIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT7" }, "DSP_L.DSP_0_BCOUT8->DSP_1_BCIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT8" }, "DSP_L.DSP_0_BCOUT9->DSP_1_BCIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT9" }, "DSP_L.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYCASCIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYCASCOUT" }, "DSP_L.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT0" }, "DSP_L.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT1" }, "DSP_L.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT2" }, "DSP_L.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT3" }, "DSP_L.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_MULTSIGNIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_MULTSIGNOUT" }, "DSP_L.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_OVERFLOW" }, "DSP_L.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P0" }, "DSP_L.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P1" }, "DSP_L.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P10" }, "DSP_L.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P11" }, "DSP_L.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P12" }, "DSP_L.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P13" }, "DSP_L.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P14" }, "DSP_L.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P15" }, "DSP_L.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P16" }, "DSP_L.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P17" }, "DSP_L.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P18" }, "DSP_L.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P19" }, "DSP_L.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P2" }, "DSP_L.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P20" }, "DSP_L.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P21" }, "DSP_L.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P22" }, "DSP_L.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P23" }, "DSP_L.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P24" }, "DSP_L.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P25" }, "DSP_L.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P26" }, "DSP_L.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P27" }, "DSP_L.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P28" }, "DSP_L.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P29" }, "DSP_L.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P3" }, "DSP_L.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P30" }, "DSP_L.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P31" }, "DSP_L.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P32" }, "DSP_L.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P33" }, "DSP_L.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P34" }, "DSP_L.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P35" }, "DSP_L.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P36" }, "DSP_L.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P37" }, "DSP_L.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P38" }, "DSP_L.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P39" }, "DSP_L.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P4" }, "DSP_L.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P40" }, "DSP_L.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P41" }, "DSP_L.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P42" }, "DSP_L.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P43" }, "DSP_L.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P44" }, "DSP_L.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P45" }, "DSP_L.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P46" }, "DSP_L.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P47" }, "DSP_L.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P5" }, "DSP_L.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P6" }, "DSP_L.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P7" }, "DSP_L.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P8" }, "DSP_L.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P9" }, "DSP_L.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PATTERNBDETECT" }, "DSP_L.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PATTERNDETECT" }, "DSP_L.DSP_0_PCOUT0->DSP_1_PCIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT0" }, "DSP_L.DSP_0_PCOUT1->DSP_1_PCIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT1" }, "DSP_L.DSP_0_PCOUT10->DSP_1_PCIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT10" }, "DSP_L.DSP_0_PCOUT11->DSP_1_PCIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT11" }, "DSP_L.DSP_0_PCOUT12->DSP_1_PCIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT12" }, "DSP_L.DSP_0_PCOUT13->DSP_1_PCIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT13" }, "DSP_L.DSP_0_PCOUT14->DSP_1_PCIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT14" }, "DSP_L.DSP_0_PCOUT15->DSP_1_PCIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT15" }, "DSP_L.DSP_0_PCOUT16->DSP_1_PCIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT16" }, "DSP_L.DSP_0_PCOUT17->DSP_1_PCIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT17" }, "DSP_L.DSP_0_PCOUT18->DSP_1_PCIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT18" }, "DSP_L.DSP_0_PCOUT19->DSP_1_PCIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT19" }, "DSP_L.DSP_0_PCOUT2->DSP_1_PCIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT2" }, "DSP_L.DSP_0_PCOUT20->DSP_1_PCIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT20" }, "DSP_L.DSP_0_PCOUT21->DSP_1_PCIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT21" }, "DSP_L.DSP_0_PCOUT22->DSP_1_PCIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT22" }, "DSP_L.DSP_0_PCOUT23->DSP_1_PCIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT23" }, "DSP_L.DSP_0_PCOUT24->DSP_1_PCIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT24" }, "DSP_L.DSP_0_PCOUT25->DSP_1_PCIN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT25" }, "DSP_L.DSP_0_PCOUT26->DSP_1_PCIN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT26" }, "DSP_L.DSP_0_PCOUT27->DSP_1_PCIN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT27" }, "DSP_L.DSP_0_PCOUT28->DSP_1_PCIN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT28" }, "DSP_L.DSP_0_PCOUT29->DSP_1_PCIN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT29" }, "DSP_L.DSP_0_PCOUT3->DSP_1_PCIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT3" }, "DSP_L.DSP_0_PCOUT30->DSP_1_PCIN30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT30" }, "DSP_L.DSP_0_PCOUT31->DSP_1_PCIN31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT31" }, "DSP_L.DSP_0_PCOUT32->DSP_1_PCIN32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT32" }, "DSP_L.DSP_0_PCOUT33->DSP_1_PCIN33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT33" }, "DSP_L.DSP_0_PCOUT34->DSP_1_PCIN34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT34" }, "DSP_L.DSP_0_PCOUT35->DSP_1_PCIN35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT35" }, "DSP_L.DSP_0_PCOUT36->DSP_1_PCIN36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT36" }, "DSP_L.DSP_0_PCOUT37->DSP_1_PCIN37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT37" }, "DSP_L.DSP_0_PCOUT38->DSP_1_PCIN38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT38" }, "DSP_L.DSP_0_PCOUT39->DSP_1_PCIN39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT39" }, "DSP_L.DSP_0_PCOUT4->DSP_1_PCIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT4" }, "DSP_L.DSP_0_PCOUT40->DSP_1_PCIN40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT40" }, "DSP_L.DSP_0_PCOUT41->DSP_1_PCIN41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT41" }, "DSP_L.DSP_0_PCOUT42->DSP_1_PCIN42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT42" }, "DSP_L.DSP_0_PCOUT43->DSP_1_PCIN43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT43" }, "DSP_L.DSP_0_PCOUT44->DSP_1_PCIN44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT44" }, "DSP_L.DSP_0_PCOUT45->DSP_1_PCIN45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT45" }, "DSP_L.DSP_0_PCOUT46->DSP_1_PCIN46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT46" }, "DSP_L.DSP_0_PCOUT47->DSP_1_PCIN47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT47" }, "DSP_L.DSP_0_PCOUT5->DSP_1_PCIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT5" }, "DSP_L.DSP_0_PCOUT6->DSP_1_PCIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT6" }, "DSP_L.DSP_0_PCOUT7->DSP_1_PCIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT7" }, "DSP_L.DSP_0_PCOUT8->DSP_1_PCIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT8" }, "DSP_L.DSP_0_PCOUT9->DSP_1_PCIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT9" }, "DSP_L.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_UNDERFLOW" }, "DSP_L.DSP_1_ACOUT0->DSP_ACOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT0" }, "DSP_L.DSP_1_ACOUT1->DSP_ACOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT1" }, "DSP_L.DSP_1_ACOUT10->DSP_ACOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT10" }, "DSP_L.DSP_1_ACOUT11->DSP_ACOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT11" }, "DSP_L.DSP_1_ACOUT12->DSP_ACOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT12" }, "DSP_L.DSP_1_ACOUT13->DSP_ACOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT13" }, "DSP_L.DSP_1_ACOUT14->DSP_ACOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT14" }, "DSP_L.DSP_1_ACOUT15->DSP_ACOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT15" }, "DSP_L.DSP_1_ACOUT16->DSP_ACOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT16" }, "DSP_L.DSP_1_ACOUT17->DSP_ACOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT17" }, "DSP_L.DSP_1_ACOUT18->DSP_ACOUT18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT18" }, "DSP_L.DSP_1_ACOUT19->DSP_ACOUT19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT19" }, "DSP_L.DSP_1_ACOUT2->DSP_ACOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT2" }, "DSP_L.DSP_1_ACOUT20->DSP_ACOUT20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT20" }, "DSP_L.DSP_1_ACOUT21->DSP_ACOUT21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT21" }, "DSP_L.DSP_1_ACOUT22->DSP_ACOUT22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT22" }, "DSP_L.DSP_1_ACOUT23->DSP_ACOUT23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT23" }, "DSP_L.DSP_1_ACOUT24->DSP_ACOUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT24" }, "DSP_L.DSP_1_ACOUT25->DSP_ACOUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT25" }, "DSP_L.DSP_1_ACOUT26->DSP_ACOUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT26" }, "DSP_L.DSP_1_ACOUT27->DSP_ACOUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT27" }, "DSP_L.DSP_1_ACOUT28->DSP_ACOUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT28" }, "DSP_L.DSP_1_ACOUT29->DSP_ACOUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT29" }, "DSP_L.DSP_1_ACOUT3->DSP_ACOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT3" }, "DSP_L.DSP_1_ACOUT4->DSP_ACOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT4" }, "DSP_L.DSP_1_ACOUT5->DSP_ACOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT5" }, "DSP_L.DSP_1_ACOUT6->DSP_ACOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT6" }, "DSP_L.DSP_1_ACOUT7->DSP_ACOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT7" }, "DSP_L.DSP_1_ACOUT8->DSP_ACOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT8" }, "DSP_L.DSP_1_ACOUT9->DSP_ACOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT9" }, "DSP_L.DSP_1_BCOUT0->DSP_BCOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT0" }, "DSP_L.DSP_1_BCOUT1->DSP_BCOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT1" }, "DSP_L.DSP_1_BCOUT10->DSP_BCOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT10" }, "DSP_L.DSP_1_BCOUT11->DSP_BCOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT11" }, "DSP_L.DSP_1_BCOUT12->DSP_BCOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT12" }, "DSP_L.DSP_1_BCOUT13->DSP_BCOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT13" }, "DSP_L.DSP_1_BCOUT14->DSP_BCOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT14" }, "DSP_L.DSP_1_BCOUT15->DSP_BCOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT15" }, "DSP_L.DSP_1_BCOUT16->DSP_BCOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT16" }, "DSP_L.DSP_1_BCOUT17->DSP_BCOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT17" }, "DSP_L.DSP_1_BCOUT2->DSP_BCOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT2" }, "DSP_L.DSP_1_BCOUT3->DSP_BCOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT3" }, "DSP_L.DSP_1_BCOUT4->DSP_BCOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT4" }, "DSP_L.DSP_1_BCOUT5->DSP_BCOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT5" }, "DSP_L.DSP_1_BCOUT6->DSP_BCOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT6" }, "DSP_L.DSP_1_BCOUT7->DSP_BCOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT7" }, "DSP_L.DSP_1_BCOUT8->DSP_BCOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT8" }, "DSP_L.DSP_1_BCOUT9->DSP_BCOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT9" }, "DSP_L.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_CARRYCASCOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYCASCOUT" }, "DSP_L.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT0" }, "DSP_L.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT1" }, "DSP_L.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT2" }, "DSP_L.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT3" }, "DSP_L.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_MULTSIGNOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_MULTSIGNOUT" }, "DSP_L.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_OVERFLOW" }, "DSP_L.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P0" }, "DSP_L.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P1" }, "DSP_L.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P10" }, "DSP_L.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P11" }, "DSP_L.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P12" }, "DSP_L.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P13" }, "DSP_L.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P14" }, "DSP_L.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P15" }, "DSP_L.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P16" }, "DSP_L.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P17" }, "DSP_L.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P18" }, "DSP_L.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P19" }, "DSP_L.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P2" }, "DSP_L.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P20" }, "DSP_L.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P21" }, "DSP_L.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P22" }, "DSP_L.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P23" }, "DSP_L.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P24" }, "DSP_L.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P25" }, "DSP_L.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P26" }, "DSP_L.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P27" }, "DSP_L.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P28" }, "DSP_L.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P29" }, "DSP_L.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P3" }, "DSP_L.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P30" }, "DSP_L.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P31" }, "DSP_L.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P32" }, "DSP_L.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P33" }, "DSP_L.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P34" }, "DSP_L.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P35" }, "DSP_L.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P36" }, "DSP_L.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P37" }, "DSP_L.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P38" }, "DSP_L.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P39" }, "DSP_L.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P4" }, "DSP_L.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P40" }, "DSP_L.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P41" }, "DSP_L.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P42" }, "DSP_L.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P43" }, "DSP_L.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P44" }, "DSP_L.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P45" }, "DSP_L.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P46" }, "DSP_L.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P47" }, "DSP_L.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P5" }, "DSP_L.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P6" }, "DSP_L.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P7" }, "DSP_L.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P8" }, "DSP_L.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P9" }, "DSP_L.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PATTERNBDETECT" }, "DSP_L.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PATTERNDETECT" }, "DSP_L.DSP_1_PCOUT0->DSP_PCOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT0" }, "DSP_L.DSP_1_PCOUT1->DSP_PCOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT1" }, "DSP_L.DSP_1_PCOUT10->DSP_PCOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT10" }, "DSP_L.DSP_1_PCOUT11->DSP_PCOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT11" }, "DSP_L.DSP_1_PCOUT12->DSP_PCOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT12" }, "DSP_L.DSP_1_PCOUT13->DSP_PCOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT13" }, "DSP_L.DSP_1_PCOUT14->DSP_PCOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT14" }, "DSP_L.DSP_1_PCOUT15->DSP_PCOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT15" }, "DSP_L.DSP_1_PCOUT16->DSP_PCOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT16" }, "DSP_L.DSP_1_PCOUT17->DSP_PCOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT17" }, "DSP_L.DSP_1_PCOUT18->DSP_PCOUT18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT18" }, "DSP_L.DSP_1_PCOUT19->DSP_PCOUT19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT19" }, "DSP_L.DSP_1_PCOUT2->DSP_PCOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT2" }, "DSP_L.DSP_1_PCOUT20->DSP_PCOUT20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT20" }, "DSP_L.DSP_1_PCOUT21->DSP_PCOUT21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT21" }, "DSP_L.DSP_1_PCOUT22->DSP_PCOUT22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT22" }, "DSP_L.DSP_1_PCOUT23->DSP_PCOUT23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT23" }, "DSP_L.DSP_1_PCOUT24->DSP_PCOUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT24" }, "DSP_L.DSP_1_PCOUT25->DSP_PCOUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT25" }, "DSP_L.DSP_1_PCOUT26->DSP_PCOUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT26" }, "DSP_L.DSP_1_PCOUT27->DSP_PCOUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT27" }, "DSP_L.DSP_1_PCOUT28->DSP_PCOUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT28" }, "DSP_L.DSP_1_PCOUT29->DSP_PCOUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT29" }, "DSP_L.DSP_1_PCOUT3->DSP_PCOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT3" }, "DSP_L.DSP_1_PCOUT30->DSP_PCOUT30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT30" }, "DSP_L.DSP_1_PCOUT31->DSP_PCOUT31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT31" }, "DSP_L.DSP_1_PCOUT32->DSP_PCOUT32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT32" }, "DSP_L.DSP_1_PCOUT33->DSP_PCOUT33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT33" }, "DSP_L.DSP_1_PCOUT34->DSP_PCOUT34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT34" }, "DSP_L.DSP_1_PCOUT35->DSP_PCOUT35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT35" }, "DSP_L.DSP_1_PCOUT36->DSP_PCOUT36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT36" }, "DSP_L.DSP_1_PCOUT37->DSP_PCOUT37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT37" }, "DSP_L.DSP_1_PCOUT38->DSP_PCOUT38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT38" }, "DSP_L.DSP_1_PCOUT39->DSP_PCOUT39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT39" }, "DSP_L.DSP_1_PCOUT4->DSP_PCOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT4" }, "DSP_L.DSP_1_PCOUT40->DSP_PCOUT40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT40" }, "DSP_L.DSP_1_PCOUT41->DSP_PCOUT41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT41" }, "DSP_L.DSP_1_PCOUT42->DSP_PCOUT42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT42" }, "DSP_L.DSP_1_PCOUT43->DSP_PCOUT43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT43" }, "DSP_L.DSP_1_PCOUT44->DSP_PCOUT44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT44" }, "DSP_L.DSP_1_PCOUT45->DSP_PCOUT45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT45" }, "DSP_L.DSP_1_PCOUT46->DSP_PCOUT46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT46" }, "DSP_L.DSP_1_PCOUT47->DSP_PCOUT47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT47" }, "DSP_L.DSP_1_PCOUT5->DSP_PCOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT5" }, "DSP_L.DSP_1_PCOUT6->DSP_PCOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT6" }, "DSP_L.DSP_1_PCOUT7->DSP_PCOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT7" }, "DSP_L.DSP_1_PCOUT8->DSP_PCOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT8" }, "DSP_L.DSP_1_PCOUT9->DSP_PCOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT9" }, "DSP_L.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_UNDERFLOW" }, "DSP_L.DSP_BYP0_0->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_0" }, "DSP_L.DSP_BYP0_1->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_1" }, "DSP_L.DSP_BYP0_2->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_2" }, "DSP_L.DSP_BYP0_3->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_3" }, "DSP_L.DSP_BYP0_4->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_4" }, "DSP_L.DSP_BYP1_0->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_0" }, "DSP_L.DSP_BYP1_1->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_1" }, "DSP_L.DSP_BYP1_2->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_2" }, "DSP_L.DSP_BYP1_3->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_3" }, "DSP_L.DSP_BYP1_4->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_4" }, "DSP_L.DSP_BYP2_0->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_0" }, "DSP_L.DSP_BYP2_1->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_1" }, "DSP_L.DSP_BYP2_2->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_2" }, "DSP_L.DSP_BYP2_3->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_3" }, "DSP_L.DSP_BYP2_4->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_4" }, "DSP_L.DSP_BYP3_0->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_0" }, "DSP_L.DSP_BYP3_1->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_1" }, "DSP_L.DSP_BYP3_2->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_2" }, "DSP_L.DSP_BYP3_3->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_3" }, "DSP_L.DSP_BYP3_4->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_4" }, "DSP_L.DSP_BYP4_0->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_0" }, "DSP_L.DSP_BYP4_1->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_1" }, "DSP_L.DSP_BYP4_2->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_2" }, "DSP_L.DSP_BYP4_3->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_3" }, "DSP_L.DSP_BYP4_4->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_4" }, "DSP_L.DSP_BYP5_0->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_0" }, "DSP_L.DSP_BYP5_1->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_1" }, "DSP_L.DSP_BYP5_2->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_2" }, "DSP_L.DSP_BYP5_3->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_3" }, "DSP_L.DSP_BYP5_4->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_4" }, "DSP_L.DSP_BYP6_0->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_0" }, "DSP_L.DSP_BYP6_1->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_1" }, "DSP_L.DSP_BYP6_2->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_2" }, "DSP_L.DSP_BYP6_3->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_3" }, "DSP_L.DSP_BYP6_4->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_4" }, "DSP_L.DSP_BYP7_0->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_0" }, "DSP_L.DSP_BYP7_1->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_1" }, "DSP_L.DSP_BYP7_2->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_2" }, "DSP_L.DSP_BYP7_3->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_3" }, "DSP_L.DSP_BYP7_4->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_4" }, "DSP_L.DSP_CLK0_1->DSP_0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CLK0_1" }, "DSP_L.DSP_CLK0_3->DSP_1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CLK0_3" }, "DSP_L.DSP_CTRL0_0->DSP_0_RSTP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_0" }, "DSP_L.DSP_CTRL0_1->DSP_0_RSTC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_1" }, "DSP_L.DSP_CTRL0_2->DSP_0_RSTB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_2" }, "DSP_L.DSP_CTRL0_3->DSP_1_RSTC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_3" }, "DSP_L.DSP_CTRL0_4->DSP_1_RSTP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_4" }, "DSP_L.DSP_CTRL1_0->DSP_0_RSTA": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTA", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_0" }, "DSP_L.DSP_CTRL1_1->DSP_0_RSTM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_1" }, "DSP_L.DSP_CTRL1_2->DSP_1_RSTA": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTA", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_2" }, "DSP_L.DSP_CTRL1_3->DSP_1_RSTM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_3" }, "DSP_L.DSP_CTRL1_4->DSP_1_RSTB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_4" }, "DSP_L.DSP_FAN0_0->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_0" }, "DSP_L.DSP_FAN0_1->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_1" }, "DSP_L.DSP_FAN0_2->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_2" }, "DSP_L.DSP_FAN0_3->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_3" }, "DSP_L.DSP_FAN0_4->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_4" }, "DSP_L.DSP_FAN1_0->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_0" }, "DSP_L.DSP_FAN1_1->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_1" }, "DSP_L.DSP_FAN1_2->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_2" }, "DSP_L.DSP_FAN1_3->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_3" }, "DSP_L.DSP_FAN2_0->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_0" }, "DSP_L.DSP_FAN2_2->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_2" }, "DSP_L.DSP_FAN2_3->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_3" }, "DSP_L.DSP_FAN2_4->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_4" }, "DSP_L.DSP_FAN3_0->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_0" }, "DSP_L.DSP_FAN3_1->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_1" }, "DSP_L.DSP_FAN3_2->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_2" }, "DSP_L.DSP_FAN3_3->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_3" }, "DSP_L.DSP_FAN3_4->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_4" }, "DSP_L.DSP_FAN4_0->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_0" }, "DSP_L.DSP_FAN4_1->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_1" }, "DSP_L.DSP_FAN4_2->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_2" }, "DSP_L.DSP_FAN4_3->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_3" }, "DSP_L.DSP_FAN4_4->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_4" }, "DSP_L.DSP_FAN5_0->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_0" }, "DSP_L.DSP_FAN5_1->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_1" }, "DSP_L.DSP_FAN5_2->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_2" }, "DSP_L.DSP_FAN5_3->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_3" }, "DSP_L.DSP_FAN5_4->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_4" }, "DSP_L.DSP_FAN6_0->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_0" }, "DSP_L.DSP_FAN6_1->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_1" }, "DSP_L.DSP_FAN6_2->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_2" }, "DSP_L.DSP_FAN6_3->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_3" }, "DSP_L.DSP_FAN6_4->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_4" }, "DSP_L.DSP_FAN7_0->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_0" }, "DSP_L.DSP_FAN7_1->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_1" }, "DSP_L.DSP_FAN7_2->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_2" }, "DSP_L.DSP_FAN7_3->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_3" }, "DSP_L.DSP_FAN7_4->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_4" }, "DSP_L.DSP_GND_L->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_GND_L->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_L" }, "DSP_L.DSP_IMUX0_0->DSP_1_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_0" }, "DSP_L.DSP_IMUX0_1->DSP_0_CEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_1" }, "DSP_L.DSP_IMUX0_2->DSP_0_CECARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CECARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_2" }, "DSP_L.DSP_IMUX0_3->DSP_1_B15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_3" }, "DSP_L.DSP_IMUX0_4->DSP_1_ALUMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_4" }, "DSP_L.DSP_IMUX10_0->DSP_1_C21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_0" }, "DSP_L.DSP_IMUX10_1->DSP_1_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_1" }, "DSP_L.DSP_IMUX10_2->DSP_1_C29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_2" }, "DSP_L.DSP_IMUX10_3->DSP_1_C33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_3" }, "DSP_L.DSP_IMUX10_4->DSP_1_C39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_4" }, "DSP_L.DSP_IMUX11_0->DSP_1_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_0" }, "DSP_L.DSP_IMUX11_1->DSP_1_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_1" }, "DSP_L.DSP_IMUX11_2->DSP_1_A9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_2" }, "DSP_L.DSP_IMUX11_3->DSP_1_CECTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CECTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_3" }, "DSP_L.DSP_IMUX11_4->DSP_1_C46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_4" }, "DSP_L.DSP_IMUX12_0->DSP_1_C22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_0" }, "DSP_L.DSP_IMUX12_1->DSP_1_C26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_1" }, "DSP_L.DSP_IMUX12_2->DSP_0_OPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_2" }, "DSP_L.DSP_IMUX12_3->DSP_1_C34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_3" }, "DSP_L.DSP_IMUX12_4->DSP_1_C38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_4" }, "DSP_L.DSP_IMUX13_0->DSP_1_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_0" }, "DSP_L.DSP_IMUX13_1->DSP_1_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_1" }, "DSP_L.DSP_IMUX13_2->DSP_1_A10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_2" }, "DSP_L.DSP_IMUX13_3->DSP_0_ALUMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_3" }, "DSP_L.DSP_IMUX13_4->DSP_1_C18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_4" }, "DSP_L.DSP_IMUX14_0->DSP_1_B0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_0" }, "DSP_L.DSP_IMUX14_1->DSP_1_C24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_1" }, "DSP_L.DSP_IMUX14_2->DSP_1_B8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_2" }, "DSP_L.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_3" }, "DSP_L.DSP_IMUX14_4->DSP_1_RSTCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_4" }, "DSP_L.DSP_IMUX15_0->DSP_1_A0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_0" }, "DSP_L.DSP_IMUX15_1->DSP_1_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_1" }, "DSP_L.DSP_IMUX15_2->DSP_1_A8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_2" }, "DSP_L.DSP_IMUX15_3->DSP_1_CARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_3" }, "DSP_L.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTALLCARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_4" }, "DSP_L.DSP_IMUX16_0->DSP_0_C41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_0" }, "DSP_L.DSP_IMUX16_1->DSP_0_B7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_1" }, "DSP_L.DSP_IMUX16_2->DSP_0_B11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_2" }, "DSP_L.DSP_IMUX16_3->DSP_1_CEB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_3" }, "DSP_L.DSP_IMUX16_4->DSP_1_OPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_4" }, "DSP_L.DSP_IMUX17_0->DSP_0_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_0" }, "DSP_L.DSP_IMUX17_1->DSP_0_A7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_1" }, "DSP_L.DSP_IMUX17_2->DSP_0_A11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_2" }, "DSP_L.DSP_IMUX17_3->DSP_1_CEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_3" }, "DSP_L.DSP_IMUX17_4->DSP_1_OPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_4" }, "DSP_L.DSP_IMUX18_0->DSP_0_C21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_0" }, "DSP_L.DSP_IMUX18_1->DSP_0_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_1" }, "DSP_L.DSP_IMUX18_2->DSP_0_B9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_2" }, "DSP_L.DSP_IMUX18_3->DSP_0_C33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_3" }, "DSP_L.DSP_IMUX18_4->DSP_0_C39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_4" }, "DSP_L.DSP_IMUX19_0->DSP_0_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_0" }, "DSP_L.DSP_IMUX19_1->DSP_0_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_1" }, "DSP_L.DSP_IMUX19_2->DSP_0_A9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_2" }, "DSP_L.DSP_IMUX19_3->DSP_1_CEM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_3" }, "DSP_L.DSP_IMUX19_4->DSP_0_C46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_4" }, "DSP_L.DSP_IMUX1_0->DSP_0_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_0" }, "DSP_L.DSP_IMUX1_1->DSP_0_CEB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_1" }, "DSP_L.DSP_IMUX1_2->DSP_0_CEM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_2" }, "DSP_L.DSP_IMUX1_3->DSP_1_B13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_3" }, "DSP_L.DSP_IMUX1_4->DSP_0_C19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_4" }, "DSP_L.DSP_IMUX20_0->DSP_0_C22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_0" }, "DSP_L.DSP_IMUX20_1->DSP_0_C26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_1" }, "DSP_L.DSP_IMUX20_2->DSP_0_OPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_2" }, "DSP_L.DSP_IMUX20_3->DSP_0_C34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_3" }, "DSP_L.DSP_IMUX20_4->DSP_0_C38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_4" }, "DSP_L.DSP_IMUX21_0->DSP_0_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_0" }, "DSP_L.DSP_IMUX21_1->DSP_0_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_1" }, "DSP_L.DSP_IMUX21_2->DSP_0_A10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_2" }, "DSP_L.DSP_IMUX21_3->DSP_0_ALUMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_3" }, "DSP_L.DSP_IMUX21_4->DSP_0_C18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_4" }, "DSP_L.DSP_IMUX22_0->DSP_0_B0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_0" }, "DSP_L.DSP_IMUX22_1->DSP_0_C24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_1" }, "DSP_L.DSP_IMUX22_2->DSP_0_B8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_2" }, "DSP_L.DSP_IMUX22_3->DSP_1_C32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_3" }, "DSP_L.DSP_IMUX22_4->DSP_1_RSTALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_4" }, "DSP_L.DSP_IMUX23_0->DSP_0_A0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_0" }, "DSP_L.DSP_IMUX23_1->DSP_0_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_1" }, "DSP_L.DSP_IMUX23_2->DSP_0_A8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_2" }, "DSP_L.DSP_IMUX23_3->DSP_0_CARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_3" }, "DSP_L.DSP_IMUX23_4->DSP_1_RSTINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_4" }, "DSP_L.DSP_IMUX24_0->DSP_1_C23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_0" }, "DSP_L.DSP_IMUX24_1->DSP_1_C27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_1" }, "DSP_L.DSP_IMUX24_2->DSP_1_C31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_2" }, "DSP_L.DSP_IMUX24_3->DSP_1_C35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_3" }, "DSP_L.DSP_IMUX24_4->DSP_1_C37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_4" }, "DSP_L.DSP_IMUX25_0->DSP_1_C43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_0" }, "DSP_L.DSP_IMUX25_1->DSP_1_C7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_1" }, "DSP_L.DSP_IMUX25_2->DSP_1_C11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_2" }, "DSP_L.DSP_IMUX25_3->DSP_1_C15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_3" }, "DSP_L.DSP_IMUX25_4->DSP_1_C47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_4" }, "DSP_L.DSP_IMUX26_0->DSP_1_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_0" }, "DSP_L.DSP_IMUX26_1->DSP_1_C25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_1" }, "DSP_L.DSP_IMUX26_2->DSP_1_CEP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_2" }, "DSP_L.DSP_IMUX26_3->DSP_1_CECARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CECARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_3" }, "DSP_L.DSP_IMUX26_4->DSP_1_C44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_4" }, "DSP_L.DSP_IMUX27_0->DSP_1_C40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_0" }, "DSP_L.DSP_IMUX27_1->DSP_1_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_1" }, "DSP_L.DSP_IMUX27_2->DSP_0_OPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_2" }, "DSP_L.DSP_IMUX27_3->DSP_1_C13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_3" }, "DSP_L.DSP_IMUX27_4->DSP_1_C17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_4" }, "DSP_L.DSP_IMUX28_0->DSP_1_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_0" }, "DSP_L.DSP_IMUX28_1->DSP_1_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_1" }, "DSP_L.DSP_IMUX28_2->DSP_1_C30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_2" }, "DSP_L.DSP_IMUX28_3->DSP_1_OPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_3" }, "DSP_L.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_4" }, "DSP_L.DSP_IMUX29_0->DSP_1_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_0" }, "DSP_L.DSP_IMUX29_1->DSP_1_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_1" }, "DSP_L.DSP_IMUX29_2->DSP_1_C10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_2" }, "DSP_L.DSP_IMUX29_3->DSP_1_C14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_3" }, "DSP_L.DSP_IMUX29_4->DSP_1_C45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_4" }, "DSP_L.DSP_IMUX2_0->DSP_1_C42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_0" }, "DSP_L.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTALLCARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_1" }, "DSP_L.DSP_IMUX2_2->DSP_0_C29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_2" }, "DSP_L.DSP_IMUX2_3->DSP_0_B15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_3" }, "DSP_L.DSP_IMUX2_4->DSP_1_B17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_4" }, "DSP_L.DSP_IMUX30_0->DSP_1_C20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_0" }, "DSP_L.DSP_IMUX30_1->DSP_1_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_1" }, "DSP_L.DSP_IMUX30_2->DSP_0_OPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_2" }, "DSP_L.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_3" }, "DSP_L.DSP_IMUX30_4->DSP_1_C36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_4" }, "DSP_L.DSP_IMUX31_0->DSP_1_C0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_0" }, "DSP_L.DSP_IMUX31_1->DSP_1_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_1" }, "DSP_L.DSP_IMUX31_2->DSP_1_C8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_2" }, "DSP_L.DSP_IMUX31_3->DSP_1_C12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_3" }, "DSP_L.DSP_IMUX31_4->DSP_1_C16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_4" }, "DSP_L.DSP_IMUX32_0->DSP_0_C23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_0" }, "DSP_L.DSP_IMUX32_1->DSP_0_C27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_1" }, "DSP_L.DSP_IMUX32_2->DSP_0_C31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_2" }, "DSP_L.DSP_IMUX32_3->DSP_0_C35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_3" }, "DSP_L.DSP_IMUX32_4->DSP_0_C37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_4" }, "DSP_L.DSP_IMUX33_0->DSP_0_C43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_0" }, "DSP_L.DSP_IMUX33_1->DSP_0_C7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_1" }, "DSP_L.DSP_IMUX33_2->DSP_0_C11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_2" }, "DSP_L.DSP_IMUX33_3->DSP_0_C15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_3" }, "DSP_L.DSP_IMUX33_4->DSP_0_C47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_4" }, "DSP_L.DSP_IMUX34_0->DSP_0_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_0" }, "DSP_L.DSP_IMUX34_1->DSP_0_C25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_1" }, "DSP_L.DSP_IMUX34_2->DSP_0_CEP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_2" }, "DSP_L.DSP_IMUX34_3->DSP_1_CEC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_3" }, "DSP_L.DSP_IMUX34_4->DSP_0_C44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_4" }, "DSP_L.DSP_IMUX35_0->DSP_0_C40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_0" }, "DSP_L.DSP_IMUX35_1->DSP_0_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_1" }, "DSP_L.DSP_IMUX35_2->DSP_0_OPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_2" }, "DSP_L.DSP_IMUX35_3->DSP_0_C13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_3" }, "DSP_L.DSP_IMUX35_4->DSP_0_C17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_4" }, "DSP_L.DSP_IMUX36_0->DSP_0_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_0" }, "DSP_L.DSP_IMUX36_1->DSP_0_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_1" }, "DSP_L.DSP_IMUX36_2->DSP_0_B10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_2" }, "DSP_L.DSP_IMUX36_3->DSP_1_OPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_3" }, "DSP_L.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_4" }, "DSP_L.DSP_IMUX37_0->DSP_0_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_0" }, "DSP_L.DSP_IMUX37_1->DSP_0_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_1" }, "DSP_L.DSP_IMUX37_2->DSP_0_C10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_2" }, "DSP_L.DSP_IMUX37_3->DSP_0_C14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_3" }, "DSP_L.DSP_IMUX37_4->DSP_0_C45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_4" }, "DSP_L.DSP_IMUX38_0->DSP_0_C20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_0" }, "DSP_L.DSP_IMUX38_1->DSP_0_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_1" }, "DSP_L.DSP_IMUX38_2->DSP_0_OPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_2" }, "DSP_L.DSP_IMUX38_3->DSP_0_C32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_3" }, "DSP_L.DSP_IMUX38_4->DSP_0_C36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_4" }, "DSP_L.DSP_IMUX39_0->DSP_0_C0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_0" }, "DSP_L.DSP_IMUX39_1->DSP_0_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_1" }, "DSP_L.DSP_IMUX39_2->DSP_0_C8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_2" }, "DSP_L.DSP_IMUX39_3->DSP_0_C12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_3" }, "DSP_L.DSP_IMUX39_4->DSP_0_C16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_4" }, "DSP_L.DSP_IMUX3_0->DSP_0_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_0" }, "DSP_L.DSP_IMUX3_1->DSP_0_RSTALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_1" }, "DSP_L.DSP_IMUX3_2->DSP_0_C9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_2" }, "DSP_L.DSP_IMUX3_3->DSP_0_B13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_3" }, "DSP_L.DSP_IMUX3_4->DSP_0_B17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_4" }, "DSP_L.DSP_IMUX40_0->DSP_0_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_0" }, "DSP_L.DSP_IMUX40_1->DSP_0_CEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_1" }, "DSP_L.DSP_IMUX40_2->DSP_0_CEC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_2" }, "DSP_L.DSP_IMUX40_3->DSP_1_B14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_3" }, "DSP_L.DSP_IMUX40_4->DSP_1_ALUMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_4" }, "DSP_L.DSP_IMUX41_0->DSP_1_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_0" }, "DSP_L.DSP_IMUX41_1->DSP_0_CEB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_1" }, "DSP_L.DSP_IMUX41_2->DSP_0_CECTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CECTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_2" }, "DSP_L.DSP_IMUX41_3->DSP_1_B12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_3" }, "DSP_L.DSP_IMUX41_4->DSP_1_C19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_4" }, "DSP_L.DSP_IMUX42_0->DSP_0_C42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_0" }, "DSP_L.DSP_IMUX42_1->DSP_0_RSTINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_1" }, "DSP_L.DSP_IMUX42_2->DSP_1_B9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_2" }, "DSP_L.DSP_IMUX42_3->DSP_0_B14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_3" }, "DSP_L.DSP_IMUX42_4->DSP_1_B16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_4" }, "DSP_L.DSP_IMUX43_0->DSP_1_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_0" }, "DSP_L.DSP_IMUX43_1->DSP_0_RSTCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_1" }, "DSP_L.DSP_IMUX43_2->DSP_1_C9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_2" }, "DSP_L.DSP_IMUX43_3->DSP_0_B12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_3" }, "DSP_L.DSP_IMUX43_4->DSP_0_B16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_4" }, "DSP_L.DSP_IMUX44_0->DSP_1_A22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_0" }, "DSP_L.DSP_IMUX44_1->DSP_1_A26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_1" }, "DSP_L.DSP_IMUX44_2->DSP_1_B10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_2" }, "DSP_L.DSP_IMUX44_3->DSP_1_A14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_3" }, "DSP_L.DSP_IMUX44_4->DSP_1_A18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_4" }, "DSP_L.DSP_IMUX45_0->DSP_1_A20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_0" }, "DSP_L.DSP_IMUX45_1->DSP_1_A24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_1" }, "DSP_L.DSP_IMUX45_2->DSP_1_A28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_2" }, "DSP_L.DSP_IMUX45_3->DSP_1_A12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_3" }, "DSP_L.DSP_IMUX45_4->DSP_1_A16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_4" }, "DSP_L.DSP_IMUX46_0->DSP_0_A22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_0" }, "DSP_L.DSP_IMUX46_1->DSP_0_A26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_1" }, "DSP_L.DSP_IMUX46_2->DSP_1_C28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_2" }, "DSP_L.DSP_IMUX46_3->DSP_0_A14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_3" }, "DSP_L.DSP_IMUX46_4->DSP_0_A18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_4" }, "DSP_L.DSP_IMUX47_0->DSP_0_A20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_0" }, "DSP_L.DSP_IMUX47_1->DSP_0_A24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_1" }, "DSP_L.DSP_IMUX47_2->DSP_0_A28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_2" }, "DSP_L.DSP_IMUX47_3->DSP_0_A12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_3" }, "DSP_L.DSP_IMUX47_4->DSP_0_A16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_4" }, "DSP_L.DSP_IMUX4_0->DSP_1_A23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_0" }, "DSP_L.DSP_IMUX4_1->DSP_1_A27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_1" }, "DSP_L.DSP_IMUX4_2->DSP_0_C30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_2" }, "DSP_L.DSP_IMUX4_3->DSP_1_A15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_3" }, "DSP_L.DSP_IMUX4_4->DSP_1_A19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_4" }, "DSP_L.DSP_IMUX5_0->DSP_1_A21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_0" }, "DSP_L.DSP_IMUX5_1->DSP_1_A25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_1" }, "DSP_L.DSP_IMUX5_2->DSP_1_A29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_2" }, "DSP_L.DSP_IMUX5_3->DSP_1_A13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_3" }, "DSP_L.DSP_IMUX5_4->DSP_1_A17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_4" }, "DSP_L.DSP_IMUX6_0->DSP_0_A23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_0" }, "DSP_L.DSP_IMUX6_1->DSP_0_A27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_1" }, "DSP_L.DSP_IMUX6_2->DSP_0_C28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_2" }, "DSP_L.DSP_IMUX6_3->DSP_0_A15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_3" }, "DSP_L.DSP_IMUX6_4->DSP_0_A19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_4" }, "DSP_L.DSP_IMUX7_0->DSP_0_A21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_0" }, "DSP_L.DSP_IMUX7_1->DSP_0_A25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_1" }, "DSP_L.DSP_IMUX7_2->DSP_0_A29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_2" }, "DSP_L.DSP_IMUX7_3->DSP_0_A13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_3" }, "DSP_L.DSP_IMUX7_4->DSP_0_A17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_4" }, "DSP_L.DSP_IMUX8_0->DSP_1_C41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_0" }, "DSP_L.DSP_IMUX8_1->DSP_1_B7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_1" }, "DSP_L.DSP_IMUX8_2->DSP_1_B11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_2" }, "DSP_L.DSP_IMUX8_3->DSP_1_CEB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_3" }, "DSP_L.DSP_IMUX8_4->DSP_1_OPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_4" }, "DSP_L.DSP_IMUX9_0->DSP_1_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_0" }, "DSP_L.DSP_IMUX9_1->DSP_1_A7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_1" }, "DSP_L.DSP_IMUX9_2->DSP_1_A11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_2" }, "DSP_L.DSP_IMUX9_3->DSP_1_CEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_3" }, "DSP_L.DSP_IMUX9_4->DSP_1_OPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_4" }, "DSP_L.DSP_VCC_L->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" }, "DSP_L.DSP_VCC_L->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_L" } }, @@ -5564,423 +14298,4176 @@ "name": "X0Y0", "prefix": "DSP48", "site_pins": { - "A0": "DSP_0_A0", - "A1": "DSP_0_A1", - "A10": "DSP_0_A10", - "A11": "DSP_0_A11", - "A12": "DSP_0_A12", - "A13": "DSP_0_A13", - "A14": "DSP_0_A14", - "A15": "DSP_0_A15", - "A16": "DSP_0_A16", - "A17": "DSP_0_A17", - "A18": "DSP_0_A18", - "A19": "DSP_0_A19", - "A2": "DSP_0_A2", - "A20": "DSP_0_A20", - "A21": "DSP_0_A21", - "A22": "DSP_0_A22", - "A23": "DSP_0_A23", - "A24": "DSP_0_A24", - "A25": "DSP_0_A25", - "A26": "DSP_0_A26", - "A27": "DSP_0_A27", - "A28": "DSP_0_A28", - "A29": "DSP_0_A29", - "A3": "DSP_0_A3", - "A4": "DSP_0_A4", - "A5": "DSP_0_A5", - "A6": "DSP_0_A6", - "A7": "DSP_0_A7", - "A8": "DSP_0_A8", - "A9": "DSP_0_A9", - "ACIN0": "DSP_0_ACIN0", - "ACIN1": "DSP_0_ACIN1", - "ACIN10": "DSP_0_ACIN10", - "ACIN11": "DSP_0_ACIN11", - "ACIN12": "DSP_0_ACIN12", - "ACIN13": "DSP_0_ACIN13", - "ACIN14": "DSP_0_ACIN14", - "ACIN15": "DSP_0_ACIN15", - "ACIN16": "DSP_0_ACIN16", - "ACIN17": "DSP_0_ACIN17", - "ACIN18": "DSP_0_ACIN18", - "ACIN19": "DSP_0_ACIN19", - "ACIN2": "DSP_0_ACIN2", - "ACIN20": "DSP_0_ACIN20", - "ACIN21": "DSP_0_ACIN21", - "ACIN22": "DSP_0_ACIN22", - "ACIN23": "DSP_0_ACIN23", - "ACIN24": "DSP_0_ACIN24", - "ACIN25": "DSP_0_ACIN25", - "ACIN26": "DSP_0_ACIN26", - "ACIN27": "DSP_0_ACIN27", - "ACIN28": "DSP_0_ACIN28", - "ACIN29": "DSP_0_ACIN29", - "ACIN3": "DSP_0_ACIN3", - "ACIN4": "DSP_0_ACIN4", - "ACIN5": "DSP_0_ACIN5", - "ACIN6": "DSP_0_ACIN6", - "ACIN7": "DSP_0_ACIN7", - "ACIN8": "DSP_0_ACIN8", - "ACIN9": "DSP_0_ACIN9", - "ACOUT0": "DSP_0_ACOUT0", - "ACOUT1": "DSP_0_ACOUT1", - "ACOUT10": "DSP_0_ACOUT10", - "ACOUT11": "DSP_0_ACOUT11", - "ACOUT12": "DSP_0_ACOUT12", - "ACOUT13": "DSP_0_ACOUT13", - "ACOUT14": "DSP_0_ACOUT14", - "ACOUT15": "DSP_0_ACOUT15", - "ACOUT16": "DSP_0_ACOUT16", - "ACOUT17": "DSP_0_ACOUT17", - "ACOUT18": "DSP_0_ACOUT18", - "ACOUT19": "DSP_0_ACOUT19", - "ACOUT2": "DSP_0_ACOUT2", - "ACOUT20": "DSP_0_ACOUT20", - "ACOUT21": "DSP_0_ACOUT21", - "ACOUT22": "DSP_0_ACOUT22", - "ACOUT23": "DSP_0_ACOUT23", - "ACOUT24": "DSP_0_ACOUT24", - "ACOUT25": "DSP_0_ACOUT25", - "ACOUT26": "DSP_0_ACOUT26", - "ACOUT27": "DSP_0_ACOUT27", - "ACOUT28": "DSP_0_ACOUT28", - "ACOUT29": "DSP_0_ACOUT29", - "ACOUT3": "DSP_0_ACOUT3", - "ACOUT4": "DSP_0_ACOUT4", - "ACOUT5": "DSP_0_ACOUT5", - "ACOUT6": "DSP_0_ACOUT6", - "ACOUT7": "DSP_0_ACOUT7", - "ACOUT8": "DSP_0_ACOUT8", - "ACOUT9": "DSP_0_ACOUT9", - "ALUMODE0": "DSP_0_ALUMODE0", - "ALUMODE1": "DSP_0_ALUMODE1", - "ALUMODE2": "DSP_0_ALUMODE2", - "ALUMODE3": "DSP_0_ALUMODE3", - "B0": "DSP_0_B0", - "B1": "DSP_0_B1", - "B10": "DSP_0_B10", - "B11": "DSP_0_B11", - "B12": "DSP_0_B12", - "B13": "DSP_0_B13", - "B14": "DSP_0_B14", - "B15": "DSP_0_B15", - "B16": "DSP_0_B16", - "B17": "DSP_0_B17", - "B2": "DSP_0_B2", - "B3": "DSP_0_B3", - "B4": "DSP_0_B4", - "B5": "DSP_0_B5", - "B6": "DSP_0_B6", - "B7": "DSP_0_B7", - "B8": "DSP_0_B8", - "B9": "DSP_0_B9", - "BCIN0": "DSP_0_BCIN0", - "BCIN1": "DSP_0_BCIN1", - "BCIN10": "DSP_0_BCIN10", - "BCIN11": "DSP_0_BCIN11", - "BCIN12": "DSP_0_BCIN12", - "BCIN13": "DSP_0_BCIN13", - "BCIN14": "DSP_0_BCIN14", - "BCIN15": "DSP_0_BCIN15", - "BCIN16": "DSP_0_BCIN16", - "BCIN17": "DSP_0_BCIN17", - "BCIN2": "DSP_0_BCIN2", - "BCIN3": "DSP_0_BCIN3", - "BCIN4": "DSP_0_BCIN4", - "BCIN5": "DSP_0_BCIN5", - "BCIN6": "DSP_0_BCIN6", - "BCIN7": "DSP_0_BCIN7", - "BCIN8": "DSP_0_BCIN8", - "BCIN9": "DSP_0_BCIN9", - "BCOUT0": "DSP_0_BCOUT0", - "BCOUT1": "DSP_0_BCOUT1", - "BCOUT10": "DSP_0_BCOUT10", - "BCOUT11": "DSP_0_BCOUT11", - "BCOUT12": "DSP_0_BCOUT12", - "BCOUT13": "DSP_0_BCOUT13", - "BCOUT14": "DSP_0_BCOUT14", - "BCOUT15": "DSP_0_BCOUT15", - "BCOUT16": "DSP_0_BCOUT16", - "BCOUT17": "DSP_0_BCOUT17", - "BCOUT2": "DSP_0_BCOUT2", - "BCOUT3": "DSP_0_BCOUT3", - "BCOUT4": "DSP_0_BCOUT4", - "BCOUT5": "DSP_0_BCOUT5", - "BCOUT6": "DSP_0_BCOUT6", - "BCOUT7": "DSP_0_BCOUT7", - "BCOUT8": "DSP_0_BCOUT8", - "BCOUT9": "DSP_0_BCOUT9", - "C0": "DSP_0_C0", - "C1": "DSP_0_C1", - "C10": "DSP_0_C10", - "C11": "DSP_0_C11", - "C12": "DSP_0_C12", - "C13": "DSP_0_C13", - "C14": "DSP_0_C14", - "C15": "DSP_0_C15", - "C16": "DSP_0_C16", - "C17": "DSP_0_C17", - "C18": "DSP_0_C18", - "C19": "DSP_0_C19", - "C2": "DSP_0_C2", - "C20": "DSP_0_C20", - "C21": "DSP_0_C21", - "C22": "DSP_0_C22", - "C23": "DSP_0_C23", - "C24": "DSP_0_C24", - "C25": "DSP_0_C25", - "C26": "DSP_0_C26", - "C27": "DSP_0_C27", - "C28": "DSP_0_C28", - "C29": "DSP_0_C29", - "C3": "DSP_0_C3", - "C30": "DSP_0_C30", - "C31": "DSP_0_C31", - "C32": "DSP_0_C32", - "C33": "DSP_0_C33", - "C34": "DSP_0_C34", - "C35": "DSP_0_C35", - "C36": "DSP_0_C36", - "C37": "DSP_0_C37", - "C38": "DSP_0_C38", - "C39": "DSP_0_C39", - "C4": "DSP_0_C4", - "C40": "DSP_0_C40", - "C41": "DSP_0_C41", - "C42": "DSP_0_C42", - "C43": "DSP_0_C43", - "C44": "DSP_0_C44", - "C45": "DSP_0_C45", - "C46": "DSP_0_C46", - "C47": "DSP_0_C47", - "C5": "DSP_0_C5", - "C6": "DSP_0_C6", - "C7": "DSP_0_C7", - "C8": "DSP_0_C8", - "C9": "DSP_0_C9", - "CARRYCASCIN": "DSP_0_CARRYCASCIN", - "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", - "CARRYIN": "DSP_0_CARRYIN", - "CARRYINSEL0": "DSP_0_CARRYINSEL0", - "CARRYINSEL1": "DSP_0_CARRYINSEL1", - "CARRYINSEL2": "DSP_0_CARRYINSEL2", - "CARRYOUT0": "DSP_0_CARRYOUT0", - "CARRYOUT1": "DSP_0_CARRYOUT1", - "CARRYOUT2": "DSP_0_CARRYOUT2", - "CARRYOUT3": "DSP_0_CARRYOUT3", - "CEA1": "DSP_0_CEA1", - "CEA2": "DSP_0_CEA2", - "CEAD": "DSP_0_CEAD", - "CEALUMODE": "DSP_0_CEALUMODE", - "CEB1": "DSP_0_CEB1", - "CEB2": "DSP_0_CEB2", - "CEC": "DSP_0_CEC", - "CECARRYIN": "DSP_0_CECARRYIN", - "CECTRL": "DSP_0_CECTRL", - "CED": "DSP_0_CED", - "CEINMODE": "DSP_0_CEINMODE", - "CEM": "DSP_0_CEM", - "CEP": "DSP_0_CEP", - "CLK": "DSP_0_CLK", - "D0": "DSP_0_D0", - "D1": "DSP_0_D1", - "D10": "DSP_0_D10", - "D11": "DSP_0_D11", - "D12": "DSP_0_D12", - "D13": "DSP_0_D13", - "D14": "DSP_0_D14", - "D15": "DSP_0_D15", - "D16": "DSP_0_D16", - "D17": "DSP_0_D17", - "D18": "DSP_0_D18", - "D19": "DSP_0_D19", - "D2": "DSP_0_D2", - "D20": "DSP_0_D20", - "D21": "DSP_0_D21", - "D22": "DSP_0_D22", - "D23": "DSP_0_D23", - "D24": "DSP_0_D24", - "D3": "DSP_0_D3", - "D4": "DSP_0_D4", - "D5": "DSP_0_D5", - "D6": "DSP_0_D6", - "D7": "DSP_0_D7", - "D8": "DSP_0_D8", - "D9": "DSP_0_D9", - "INMODE0": "DSP_0_INMODE0", - "INMODE1": "DSP_0_INMODE1", - "INMODE2": "DSP_0_INMODE2", - "INMODE3": "DSP_0_INMODE3", - "INMODE4": "DSP_0_INMODE4", - "MULTSIGNIN": "DSP_0_MULTSIGNIN", - "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", - "OPMODE0": "DSP_0_OPMODE0", - "OPMODE1": "DSP_0_OPMODE1", - "OPMODE2": "DSP_0_OPMODE2", - "OPMODE3": "DSP_0_OPMODE3", - "OPMODE4": "DSP_0_OPMODE4", - "OPMODE5": "DSP_0_OPMODE5", - "OPMODE6": "DSP_0_OPMODE6", - "OVERFLOW": "DSP_0_OVERFLOW", - "P0": "DSP_0_P0", - "P1": "DSP_0_P1", - "P10": "DSP_0_P10", - "P11": "DSP_0_P11", - "P12": "DSP_0_P12", - "P13": "DSP_0_P13", - "P14": "DSP_0_P14", - "P15": "DSP_0_P15", - "P16": "DSP_0_P16", - "P17": "DSP_0_P17", - "P18": "DSP_0_P18", - "P19": "DSP_0_P19", - "P2": "DSP_0_P2", - "P20": "DSP_0_P20", - "P21": "DSP_0_P21", - "P22": "DSP_0_P22", - "P23": "DSP_0_P23", - "P24": "DSP_0_P24", - "P25": "DSP_0_P25", - "P26": "DSP_0_P26", - "P27": "DSP_0_P27", - "P28": "DSP_0_P28", - "P29": "DSP_0_P29", - "P3": "DSP_0_P3", - "P30": "DSP_0_P30", - "P31": "DSP_0_P31", - "P32": "DSP_0_P32", - "P33": "DSP_0_P33", - "P34": "DSP_0_P34", - "P35": "DSP_0_P35", - "P36": "DSP_0_P36", - "P37": "DSP_0_P37", - "P38": "DSP_0_P38", - "P39": "DSP_0_P39", - "P4": "DSP_0_P4", - "P40": "DSP_0_P40", - "P41": "DSP_0_P41", - "P42": "DSP_0_P42", - "P43": "DSP_0_P43", - "P44": "DSP_0_P44", - "P45": "DSP_0_P45", - "P46": "DSP_0_P46", - "P47": "DSP_0_P47", - "P5": "DSP_0_P5", - "P6": "DSP_0_P6", - "P7": "DSP_0_P7", - "P8": "DSP_0_P8", - "P9": "DSP_0_P9", - "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", - "PATTERNDETECT": "DSP_0_PATTERNDETECT", - "PCIN0": "DSP_0_PCIN0", - "PCIN1": "DSP_0_PCIN1", - "PCIN10": "DSP_0_PCIN10", - "PCIN11": "DSP_0_PCIN11", - "PCIN12": "DSP_0_PCIN12", - "PCIN13": "DSP_0_PCIN13", - "PCIN14": "DSP_0_PCIN14", - "PCIN15": "DSP_0_PCIN15", - "PCIN16": "DSP_0_PCIN16", - "PCIN17": "DSP_0_PCIN17", - "PCIN18": "DSP_0_PCIN18", - "PCIN19": "DSP_0_PCIN19", - "PCIN2": "DSP_0_PCIN2", - "PCIN20": "DSP_0_PCIN20", - "PCIN21": "DSP_0_PCIN21", - "PCIN22": "DSP_0_PCIN22", - "PCIN23": "DSP_0_PCIN23", - "PCIN24": "DSP_0_PCIN24", - "PCIN25": "DSP_0_PCIN25", - "PCIN26": "DSP_0_PCIN26", - "PCIN27": "DSP_0_PCIN27", - "PCIN28": "DSP_0_PCIN28", - "PCIN29": "DSP_0_PCIN29", - "PCIN3": "DSP_0_PCIN3", - "PCIN30": "DSP_0_PCIN30", - "PCIN31": "DSP_0_PCIN31", - "PCIN32": "DSP_0_PCIN32", - "PCIN33": "DSP_0_PCIN33", - "PCIN34": "DSP_0_PCIN34", - "PCIN35": "DSP_0_PCIN35", - "PCIN36": "DSP_0_PCIN36", - "PCIN37": "DSP_0_PCIN37", - "PCIN38": "DSP_0_PCIN38", - "PCIN39": "DSP_0_PCIN39", - "PCIN4": "DSP_0_PCIN4", - "PCIN40": "DSP_0_PCIN40", - "PCIN41": "DSP_0_PCIN41", - "PCIN42": "DSP_0_PCIN42", - "PCIN43": "DSP_0_PCIN43", - "PCIN44": "DSP_0_PCIN44", - "PCIN45": "DSP_0_PCIN45", - "PCIN46": "DSP_0_PCIN46", - "PCIN47": "DSP_0_PCIN47", - "PCIN5": "DSP_0_PCIN5", - "PCIN6": "DSP_0_PCIN6", - "PCIN7": "DSP_0_PCIN7", - "PCIN8": "DSP_0_PCIN8", - "PCIN9": "DSP_0_PCIN9", - "PCOUT0": "DSP_0_PCOUT0", - "PCOUT1": "DSP_0_PCOUT1", - "PCOUT10": "DSP_0_PCOUT10", - "PCOUT11": "DSP_0_PCOUT11", - "PCOUT12": "DSP_0_PCOUT12", - "PCOUT13": "DSP_0_PCOUT13", - "PCOUT14": "DSP_0_PCOUT14", - "PCOUT15": "DSP_0_PCOUT15", - "PCOUT16": "DSP_0_PCOUT16", - "PCOUT17": "DSP_0_PCOUT17", - "PCOUT18": "DSP_0_PCOUT18", - "PCOUT19": "DSP_0_PCOUT19", - "PCOUT2": "DSP_0_PCOUT2", - "PCOUT20": "DSP_0_PCOUT20", - "PCOUT21": "DSP_0_PCOUT21", - "PCOUT22": "DSP_0_PCOUT22", - "PCOUT23": "DSP_0_PCOUT23", - "PCOUT24": "DSP_0_PCOUT24", - "PCOUT25": "DSP_0_PCOUT25", - "PCOUT26": "DSP_0_PCOUT26", - "PCOUT27": "DSP_0_PCOUT27", - "PCOUT28": "DSP_0_PCOUT28", - "PCOUT29": "DSP_0_PCOUT29", - "PCOUT3": "DSP_0_PCOUT3", - "PCOUT30": "DSP_0_PCOUT30", - "PCOUT31": "DSP_0_PCOUT31", - "PCOUT32": "DSP_0_PCOUT32", - "PCOUT33": "DSP_0_PCOUT33", - "PCOUT34": "DSP_0_PCOUT34", - "PCOUT35": "DSP_0_PCOUT35", - "PCOUT36": "DSP_0_PCOUT36", - "PCOUT37": "DSP_0_PCOUT37", - "PCOUT38": "DSP_0_PCOUT38", - "PCOUT39": "DSP_0_PCOUT39", - "PCOUT4": "DSP_0_PCOUT4", - "PCOUT40": "DSP_0_PCOUT40", - "PCOUT41": "DSP_0_PCOUT41", - "PCOUT42": "DSP_0_PCOUT42", - "PCOUT43": "DSP_0_PCOUT43", - "PCOUT44": "DSP_0_PCOUT44", - "PCOUT45": "DSP_0_PCOUT45", - "PCOUT46": "DSP_0_PCOUT46", - "PCOUT47": "DSP_0_PCOUT47", - "PCOUT5": "DSP_0_PCOUT5", - "PCOUT6": "DSP_0_PCOUT6", - "PCOUT7": "DSP_0_PCOUT7", - "PCOUT8": "DSP_0_PCOUT8", - "PCOUT9": "DSP_0_PCOUT9", - "RSTA": "DSP_0_RSTA", - "RSTALLCARRYIN": "DSP_0_RSTALLCARRYIN", - "RSTALUMODE": "DSP_0_RSTALUMODE", - "RSTB": "DSP_0_RSTB", - "RSTC": "DSP_0_RSTC", - "RSTCTRL": "DSP_0_RSTCTRL", - "RSTD": "DSP_0_RSTD", - "RSTINMODE": "DSP_0_RSTINMODE", - "RSTM": "DSP_0_RSTM", - "RSTP": "DSP_0_RSTP", - "UNDERFLOW": "DSP_0_UNDERFLOW" + "A0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A0" + }, + "A1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A1" + }, + "A10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A10" + }, + "A11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A11" + }, + "A12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A12" + }, + "A13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A13" + }, + "A14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A14" + }, + "A15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A15" + }, + "A16": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A16" + }, + "A17": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A17" + }, + "A18": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A18" + }, + "A19": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A19" + }, + "A2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A2" + }, + "A20": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A20" + }, + "A21": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A21" + }, + "A22": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A22" + }, + "A23": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A23" + }, + "A24": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A24" + }, + "A25": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A25" + }, + "A26": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A26" + }, + "A27": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A27" + }, + "A28": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A28" + }, + "A29": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A29" + }, + "A3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A3" + }, + "A4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A4" + }, + "A5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_A5" + }, + "A6": { + "cap": "0.000", + "delay": [ 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"BCOUT17": "DSP_1_BCOUT17", - "BCOUT2": "DSP_1_BCOUT2", - "BCOUT3": "DSP_1_BCOUT3", - "BCOUT4": "DSP_1_BCOUT4", - "BCOUT5": "DSP_1_BCOUT5", - "BCOUT6": "DSP_1_BCOUT6", - "BCOUT7": "DSP_1_BCOUT7", - "BCOUT8": "DSP_1_BCOUT8", - "BCOUT9": "DSP_1_BCOUT9", - "C0": "DSP_1_C0", - "C1": "DSP_1_C1", - "C10": "DSP_1_C10", - "C11": "DSP_1_C11", - "C12": "DSP_1_C12", - "C13": "DSP_1_C13", - "C14": "DSP_1_C14", - "C15": "DSP_1_C15", - "C16": "DSP_1_C16", - "C17": "DSP_1_C17", - "C18": "DSP_1_C18", - "C19": "DSP_1_C19", - "C2": "DSP_1_C2", - "C20": "DSP_1_C20", - "C21": "DSP_1_C21", - "C22": "DSP_1_C22", - "C23": "DSP_1_C23", - "C24": "DSP_1_C24", - "C25": "DSP_1_C25", - "C26": "DSP_1_C26", - "C27": "DSP_1_C27", - "C28": "DSP_1_C28", - "C29": "DSP_1_C29", - "C3": "DSP_1_C3", - "C30": "DSP_1_C30", - "C31": "DSP_1_C31", - "C32": "DSP_1_C32", - "C33": "DSP_1_C33", - "C34": "DSP_1_C34", - "C35": "DSP_1_C35", - "C36": "DSP_1_C36", - "C37": "DSP_1_C37", - "C38": "DSP_1_C38", - "C39": "DSP_1_C39", - "C4": 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"DSP_1_CLK", - "D0": "DSP_1_D0", - "D1": "DSP_1_D1", - "D10": "DSP_1_D10", - "D11": "DSP_1_D11", - "D12": "DSP_1_D12", - "D13": "DSP_1_D13", - "D14": "DSP_1_D14", - "D15": "DSP_1_D15", - "D16": "DSP_1_D16", - "D17": "DSP_1_D17", - "D18": "DSP_1_D18", - "D19": "DSP_1_D19", - "D2": "DSP_1_D2", - "D20": "DSP_1_D20", - "D21": "DSP_1_D21", - "D22": "DSP_1_D22", - "D23": "DSP_1_D23", - "D24": "DSP_1_D24", - "D3": "DSP_1_D3", - "D4": "DSP_1_D4", - "D5": "DSP_1_D5", - "D6": "DSP_1_D6", - "D7": "DSP_1_D7", - "D8": "DSP_1_D8", - "D9": "DSP_1_D9", - "INMODE0": "DSP_1_INMODE0", - "INMODE1": "DSP_1_INMODE1", - "INMODE2": "DSP_1_INMODE2", - "INMODE3": "DSP_1_INMODE3", - "INMODE4": "DSP_1_INMODE4", - "MULTSIGNIN": "DSP_1_MULTSIGNIN", - "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", - "OPMODE0": "DSP_1_OPMODE0", - "OPMODE1": "DSP_1_OPMODE1", - "OPMODE2": "DSP_1_OPMODE2", - "OPMODE3": "DSP_1_OPMODE3", - "OPMODE4": "DSP_1_OPMODE4", - "OPMODE5": "DSP_1_OPMODE5", - "OPMODE6": "DSP_1_OPMODE6", - "OVERFLOW": "DSP_1_OVERFLOW", - "P0": "DSP_1_P0", - "P1": "DSP_1_P1", - "P10": "DSP_1_P10", - "P11": "DSP_1_P11", - "P12": "DSP_1_P12", - "P13": "DSP_1_P13", - "P14": "DSP_1_P14", - "P15": "DSP_1_P15", - "P16": "DSP_1_P16", - "P17": "DSP_1_P17", - "P18": "DSP_1_P18", - "P19": "DSP_1_P19", - "P2": "DSP_1_P2", - "P20": "DSP_1_P20", - "P21": "DSP_1_P21", - "P22": "DSP_1_P22", - "P23": "DSP_1_P23", - "P24": "DSP_1_P24", - "P25": "DSP_1_P25", - "P26": "DSP_1_P26", - "P27": "DSP_1_P27", - "P28": "DSP_1_P28", - "P29": "DSP_1_P29", - "P3": "DSP_1_P3", - "P30": "DSP_1_P30", - "P31": "DSP_1_P31", - "P32": "DSP_1_P32", - "P33": "DSP_1_P33", - "P34": "DSP_1_P34", - "P35": "DSP_1_P35", - "P36": "DSP_1_P36", - "P37": "DSP_1_P37", - "P38": "DSP_1_P38", - "P39": "DSP_1_P39", - "P4": "DSP_1_P4", - "P40": "DSP_1_P40", - "P41": "DSP_1_P41", - "P42": "DSP_1_P42", - "P43": "DSP_1_P43", - "P44": "DSP_1_P44", - "P45": "DSP_1_P45", - "P46": "DSP_1_P46", - "P47": "DSP_1_P47", - "P5": "DSP_1_P5", - "P6": "DSP_1_P6", - "P7": "DSP_1_P7", - "P8": "DSP_1_P8", - "P9": "DSP_1_P9", - "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", - "PATTERNDETECT": "DSP_1_PATTERNDETECT", - "PCIN0": "DSP_1_PCIN0", - "PCIN1": "DSP_1_PCIN1", - "PCIN10": "DSP_1_PCIN10", - "PCIN11": "DSP_1_PCIN11", - "PCIN12": "DSP_1_PCIN12", - "PCIN13": "DSP_1_PCIN13", - "PCIN14": "DSP_1_PCIN14", - "PCIN15": "DSP_1_PCIN15", - "PCIN16": "DSP_1_PCIN16", - "PCIN17": "DSP_1_PCIN17", - "PCIN18": "DSP_1_PCIN18", - "PCIN19": "DSP_1_PCIN19", - "PCIN2": "DSP_1_PCIN2", - "PCIN20": "DSP_1_PCIN20", - "PCIN21": "DSP_1_PCIN21", - "PCIN22": "DSP_1_PCIN22", - "PCIN23": "DSP_1_PCIN23", - "PCIN24": "DSP_1_PCIN24", - "PCIN25": "DSP_1_PCIN25", - "PCIN26": "DSP_1_PCIN26", - "PCIN27": "DSP_1_PCIN27", - "PCIN28": "DSP_1_PCIN28", - "PCIN29": "DSP_1_PCIN29", - "PCIN3": "DSP_1_PCIN3", - "PCIN30": "DSP_1_PCIN30", - "PCIN31": "DSP_1_PCIN31", - "PCIN32": "DSP_1_PCIN32", - "PCIN33": "DSP_1_PCIN33", - "PCIN34": "DSP_1_PCIN34", - "PCIN35": "DSP_1_PCIN35", - "PCIN36": "DSP_1_PCIN36", - "PCIN37": "DSP_1_PCIN37", - "PCIN38": "DSP_1_PCIN38", - "PCIN39": "DSP_1_PCIN39", - "PCIN4": "DSP_1_PCIN4", - "PCIN40": "DSP_1_PCIN40", - "PCIN41": "DSP_1_PCIN41", - "PCIN42": "DSP_1_PCIN42", - "PCIN43": "DSP_1_PCIN43", - "PCIN44": "DSP_1_PCIN44", - "PCIN45": "DSP_1_PCIN45", - "PCIN46": "DSP_1_PCIN46", - "PCIN47": "DSP_1_PCIN47", - "PCIN5": "DSP_1_PCIN5", - "PCIN6": "DSP_1_PCIN6", - "PCIN7": "DSP_1_PCIN7", - "PCIN8": "DSP_1_PCIN8", - "PCIN9": "DSP_1_PCIN9", - "PCOUT0": "DSP_1_PCOUT0", - "PCOUT1": "DSP_1_PCOUT1", - "PCOUT10": "DSP_1_PCOUT10", - "PCOUT11": "DSP_1_PCOUT11", - "PCOUT12": "DSP_1_PCOUT12", - "PCOUT13": "DSP_1_PCOUT13", - "PCOUT14": "DSP_1_PCOUT14", - "PCOUT15": "DSP_1_PCOUT15", - "PCOUT16": "DSP_1_PCOUT16", - "PCOUT17": "DSP_1_PCOUT17", - "PCOUT18": "DSP_1_PCOUT18", - "PCOUT19": "DSP_1_PCOUT19", - "PCOUT2": "DSP_1_PCOUT2", - "PCOUT20": "DSP_1_PCOUT20", - "PCOUT21": "DSP_1_PCOUT21", - "PCOUT22": "DSP_1_PCOUT22", - "PCOUT23": "DSP_1_PCOUT23", - "PCOUT24": "DSP_1_PCOUT24", - "PCOUT25": "DSP_1_PCOUT25", - "PCOUT26": "DSP_1_PCOUT26", - "PCOUT27": "DSP_1_PCOUT27", - "PCOUT28": "DSP_1_PCOUT28", - "PCOUT29": "DSP_1_PCOUT29", - "PCOUT3": "DSP_1_PCOUT3", - "PCOUT30": "DSP_1_PCOUT30", - "PCOUT31": "DSP_1_PCOUT31", - "PCOUT32": "DSP_1_PCOUT32", - "PCOUT33": "DSP_1_PCOUT33", - "PCOUT34": "DSP_1_PCOUT34", - "PCOUT35": "DSP_1_PCOUT35", - "PCOUT36": "DSP_1_PCOUT36", - "PCOUT37": "DSP_1_PCOUT37", - "PCOUT38": "DSP_1_PCOUT38", - "PCOUT39": "DSP_1_PCOUT39", - "PCOUT4": "DSP_1_PCOUT4", - "PCOUT40": "DSP_1_PCOUT40", - "PCOUT41": "DSP_1_PCOUT41", - "PCOUT42": "DSP_1_PCOUT42", - "PCOUT43": "DSP_1_PCOUT43", - "PCOUT44": "DSP_1_PCOUT44", - "PCOUT45": "DSP_1_PCOUT45", - "PCOUT46": "DSP_1_PCOUT46", - "PCOUT47": "DSP_1_PCOUT47", - "PCOUT5": "DSP_1_PCOUT5", - "PCOUT6": "DSP_1_PCOUT6", - "PCOUT7": "DSP_1_PCOUT7", - "PCOUT8": "DSP_1_PCOUT8", - "PCOUT9": "DSP_1_PCOUT9", - "RSTA": "DSP_1_RSTA", - "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", - "RSTALUMODE": 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"wire": "DSP_1_RSTCTRL" + }, + "RSTD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_1_RSTD" + }, + "RSTINMODE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_1_RSTINMODE" + }, + "RSTM": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_1_RSTM" + }, + "RSTP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_1_RSTP" + }, + "UNDERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1337.678375", + "wire": "DSP_1_UNDERFLOW" + } }, "type": "DSP48E1", "x_coord": 0, @@ -6416,8 +22656,26 @@ "name": "X0Y0", "prefix": "TIEOFF", "site_pins": { - "HARD0": "DSP_GND_L", - "HARD1": "DSP_VCC_L" + "HARD0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "DSP_GND_L" + }, + "HARD1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "DSP_VCC_L" + } }, "type": "TIEOFF", "x_coord": 0, @@ -6425,2050 +22683,4834 @@ } ], "tile_type": "DSP_L", - "wires": [ - "DSP_0_A0", - "DSP_0_A1", - "DSP_0_A10", - "DSP_0_A11", - "DSP_0_A12", - "DSP_0_A13", - "DSP_0_A14", - "DSP_0_A15", - "DSP_0_A16", - "DSP_0_A17", - "DSP_0_A18", - "DSP_0_A19", - "DSP_0_A2", - "DSP_0_A20", - "DSP_0_A21", - "DSP_0_A22", - "DSP_0_A23", - "DSP_0_A24", - "DSP_0_A25", - "DSP_0_A26", - "DSP_0_A27", - "DSP_0_A28", - "DSP_0_A29", - "DSP_0_A3", - "DSP_0_A4", - "DSP_0_A5", - "DSP_0_A6", - "DSP_0_A7", - "DSP_0_A8", - "DSP_0_A9", - "DSP_0_ACIN0", - "DSP_0_ACIN1", - "DSP_0_ACIN10", - "DSP_0_ACIN11", - "DSP_0_ACIN12", - "DSP_0_ACIN13", - "DSP_0_ACIN14", - "DSP_0_ACIN15", - "DSP_0_ACIN16", - "DSP_0_ACIN17", - "DSP_0_ACIN18", - "DSP_0_ACIN19", - "DSP_0_ACIN2", - "DSP_0_ACIN20", - "DSP_0_ACIN21", - "DSP_0_ACIN22", - "DSP_0_ACIN23", - "DSP_0_ACIN24", - "DSP_0_ACIN25", - "DSP_0_ACIN26", - "DSP_0_ACIN27", - "DSP_0_ACIN28", - "DSP_0_ACIN29", - "DSP_0_ACIN3", - "DSP_0_ACIN4", - "DSP_0_ACIN5", - "DSP_0_ACIN6", - "DSP_0_ACIN7", - "DSP_0_ACIN8", - "DSP_0_ACIN9", - "DSP_0_ACOUT0", - "DSP_0_ACOUT1", - "DSP_0_ACOUT10", - "DSP_0_ACOUT11", - "DSP_0_ACOUT12", - "DSP_0_ACOUT13", - "DSP_0_ACOUT14", - "DSP_0_ACOUT15", - "DSP_0_ACOUT16", - "DSP_0_ACOUT17", - "DSP_0_ACOUT18", - "DSP_0_ACOUT19", - "DSP_0_ACOUT2", - "DSP_0_ACOUT20", - "DSP_0_ACOUT21", - "DSP_0_ACOUT22", - "DSP_0_ACOUT23", - "DSP_0_ACOUT24", - "DSP_0_ACOUT25", - "DSP_0_ACOUT26", - "DSP_0_ACOUT27", - "DSP_0_ACOUT28", - "DSP_0_ACOUT29", - "DSP_0_ACOUT3", - "DSP_0_ACOUT4", - "DSP_0_ACOUT5", - "DSP_0_ACOUT6", - "DSP_0_ACOUT7", - "DSP_0_ACOUT8", - "DSP_0_ACOUT9", - "DSP_0_ALUMODE0", - "DSP_0_ALUMODE1", - "DSP_0_ALUMODE2", - "DSP_0_ALUMODE3", - "DSP_0_B0", - "DSP_0_B1", - "DSP_0_B10", - "DSP_0_B11", - "DSP_0_B12", - "DSP_0_B13", - "DSP_0_B14", - "DSP_0_B15", - "DSP_0_B16", - "DSP_0_B17", - "DSP_0_B2", - "DSP_0_B3", - "DSP_0_B4", - "DSP_0_B5", - "DSP_0_B6", - "DSP_0_B7", - "DSP_0_B8", - "DSP_0_B9", - "DSP_0_BCIN0", - "DSP_0_BCIN1", - "DSP_0_BCIN10", - "DSP_0_BCIN11", - "DSP_0_BCIN12", - "DSP_0_BCIN13", - "DSP_0_BCIN14", - "DSP_0_BCIN15", - "DSP_0_BCIN16", - "DSP_0_BCIN17", - "DSP_0_BCIN2", - "DSP_0_BCIN3", - "DSP_0_BCIN4", - "DSP_0_BCIN5", - "DSP_0_BCIN6", - "DSP_0_BCIN7", - "DSP_0_BCIN8", - "DSP_0_BCIN9", - "DSP_0_BCOUT0", - "DSP_0_BCOUT1", - "DSP_0_BCOUT10", - "DSP_0_BCOUT11", - "DSP_0_BCOUT12", - "DSP_0_BCOUT13", - "DSP_0_BCOUT14", - "DSP_0_BCOUT15", - "DSP_0_BCOUT16", - "DSP_0_BCOUT17", - "DSP_0_BCOUT2", - "DSP_0_BCOUT3", - "DSP_0_BCOUT4", - "DSP_0_BCOUT5", - "DSP_0_BCOUT6", - "DSP_0_BCOUT7", - "DSP_0_BCOUT8", - "DSP_0_BCOUT9", - "DSP_0_C0", - "DSP_0_C1", - "DSP_0_C10", - "DSP_0_C11", - "DSP_0_C12", - "DSP_0_C13", - "DSP_0_C14", - "DSP_0_C15", - "DSP_0_C16", - "DSP_0_C17", - "DSP_0_C18", - "DSP_0_C19", - "DSP_0_C2", - "DSP_0_C20", - "DSP_0_C21", - "DSP_0_C22", - "DSP_0_C23", - "DSP_0_C24", - "DSP_0_C25", - "DSP_0_C26", - "DSP_0_C27", - "DSP_0_C28", - "DSP_0_C29", - "DSP_0_C3", - "DSP_0_C30", - "DSP_0_C31", - "DSP_0_C32", - "DSP_0_C33", - "DSP_0_C34", - "DSP_0_C35", - "DSP_0_C36", - "DSP_0_C37", - "DSP_0_C38", - "DSP_0_C39", - "DSP_0_C4", - "DSP_0_C40", - "DSP_0_C41", - "DSP_0_C42", - "DSP_0_C43", - "DSP_0_C44", - "DSP_0_C45", - "DSP_0_C46", - "DSP_0_C47", - "DSP_0_C5", - "DSP_0_C6", - "DSP_0_C7", - "DSP_0_C8", - "DSP_0_C9", - "DSP_0_CARRYCASCIN", - "DSP_0_CARRYCASCOUT", - "DSP_0_CARRYIN", - "DSP_0_CARRYINSEL0", - "DSP_0_CARRYINSEL1", - "DSP_0_CARRYINSEL2", - "DSP_0_CARRYOUT0", - "DSP_0_CARRYOUT1", - "DSP_0_CARRYOUT2", - "DSP_0_CARRYOUT3", - "DSP_0_CEA1", - "DSP_0_CEA2", - "DSP_0_CEAD", - "DSP_0_CEALUMODE", - "DSP_0_CEB1", - "DSP_0_CEB2", - "DSP_0_CEC", - "DSP_0_CECARRYIN", - "DSP_0_CECTRL", - "DSP_0_CED", - "DSP_0_CEINMODE", - "DSP_0_CEM", - "DSP_0_CEP", - "DSP_0_CLK", - "DSP_0_D0", - "DSP_0_D1", - "DSP_0_D10", - "DSP_0_D11", - "DSP_0_D12", - "DSP_0_D13", - "DSP_0_D14", - "DSP_0_D15", - "DSP_0_D16", - "DSP_0_D17", - "DSP_0_D18", - "DSP_0_D19", - "DSP_0_D2", - "DSP_0_D20", - "DSP_0_D21", - "DSP_0_D22", - "DSP_0_D23", - "DSP_0_D24", - "DSP_0_D3", - "DSP_0_D4", - "DSP_0_D5", - "DSP_0_D6", - "DSP_0_D7", - "DSP_0_D8", - "DSP_0_D9", - "DSP_0_INMODE0", - "DSP_0_INMODE1", - "DSP_0_INMODE2", - "DSP_0_INMODE3", - "DSP_0_INMODE4", - "DSP_0_MULTSIGNIN", - "DSP_0_MULTSIGNOUT", - "DSP_0_OPMODE0", - "DSP_0_OPMODE1", - "DSP_0_OPMODE2", - "DSP_0_OPMODE3", - "DSP_0_OPMODE4", - "DSP_0_OPMODE5", - "DSP_0_OPMODE6", - "DSP_0_OVERFLOW", - "DSP_0_P0", - "DSP_0_P1", - "DSP_0_P10", - "DSP_0_P11", - "DSP_0_P12", - "DSP_0_P13", - "DSP_0_P14", - "DSP_0_P15", - "DSP_0_P16", - "DSP_0_P17", - "DSP_0_P18", - "DSP_0_P19", - "DSP_0_P2", - "DSP_0_P20", - "DSP_0_P21", - "DSP_0_P22", - "DSP_0_P23", - "DSP_0_P24", - "DSP_0_P25", - "DSP_0_P26", - "DSP_0_P27", - "DSP_0_P28", - "DSP_0_P29", - "DSP_0_P3", - "DSP_0_P30", - "DSP_0_P31", - "DSP_0_P32", - "DSP_0_P33", - "DSP_0_P34", - "DSP_0_P35", - "DSP_0_P36", - "DSP_0_P37", - "DSP_0_P38", - "DSP_0_P39", - "DSP_0_P4", - "DSP_0_P40", - "DSP_0_P41", - "DSP_0_P42", - "DSP_0_P43", - "DSP_0_P44", - "DSP_0_P45", - "DSP_0_P46", - "DSP_0_P47", - "DSP_0_P5", - "DSP_0_P6", - "DSP_0_P7", - "DSP_0_P8", - "DSP_0_P9", - "DSP_0_PATTERNBDETECT", - "DSP_0_PATTERNDETECT", - "DSP_0_PCIN0", - "DSP_0_PCIN1", - "DSP_0_PCIN10", - "DSP_0_PCIN11", - "DSP_0_PCIN12", - "DSP_0_PCIN13", - "DSP_0_PCIN14", - "DSP_0_PCIN15", - "DSP_0_PCIN16", - "DSP_0_PCIN17", - "DSP_0_PCIN18", - "DSP_0_PCIN19", - "DSP_0_PCIN2", - "DSP_0_PCIN20", - "DSP_0_PCIN21", - "DSP_0_PCIN22", - "DSP_0_PCIN23", - "DSP_0_PCIN24", - "DSP_0_PCIN25", - "DSP_0_PCIN26", - "DSP_0_PCIN27", - "DSP_0_PCIN28", - "DSP_0_PCIN29", - "DSP_0_PCIN3", - "DSP_0_PCIN30", - "DSP_0_PCIN31", - "DSP_0_PCIN32", - "DSP_0_PCIN33", - "DSP_0_PCIN34", - "DSP_0_PCIN35", - "DSP_0_PCIN36", - "DSP_0_PCIN37", - "DSP_0_PCIN38", - "DSP_0_PCIN39", - "DSP_0_PCIN4", - "DSP_0_PCIN40", - "DSP_0_PCIN41", - "DSP_0_PCIN42", - "DSP_0_PCIN43", - "DSP_0_PCIN44", - "DSP_0_PCIN45", - "DSP_0_PCIN46", - "DSP_0_PCIN47", - "DSP_0_PCIN5", - "DSP_0_PCIN6", - "DSP_0_PCIN7", - "DSP_0_PCIN8", - "DSP_0_PCIN9", - "DSP_0_PCOUT0", - "DSP_0_PCOUT1", - "DSP_0_PCOUT10", - "DSP_0_PCOUT11", - "DSP_0_PCOUT12", - "DSP_0_PCOUT13", - "DSP_0_PCOUT14", - "DSP_0_PCOUT15", - "DSP_0_PCOUT16", - "DSP_0_PCOUT17", - "DSP_0_PCOUT18", - "DSP_0_PCOUT19", - "DSP_0_PCOUT2", - "DSP_0_PCOUT20", - "DSP_0_PCOUT21", - "DSP_0_PCOUT22", - "DSP_0_PCOUT23", - "DSP_0_PCOUT24", - "DSP_0_PCOUT25", - "DSP_0_PCOUT26", - "DSP_0_PCOUT27", - "DSP_0_PCOUT28", - "DSP_0_PCOUT29", - "DSP_0_PCOUT3", - "DSP_0_PCOUT30", - "DSP_0_PCOUT31", - "DSP_0_PCOUT32", - "DSP_0_PCOUT33", - "DSP_0_PCOUT34", - "DSP_0_PCOUT35", - "DSP_0_PCOUT36", - "DSP_0_PCOUT37", - "DSP_0_PCOUT38", - "DSP_0_PCOUT39", - "DSP_0_PCOUT4", - "DSP_0_PCOUT40", - "DSP_0_PCOUT41", - "DSP_0_PCOUT42", - "DSP_0_PCOUT43", - "DSP_0_PCOUT44", - "DSP_0_PCOUT45", - "DSP_0_PCOUT46", - "DSP_0_PCOUT47", - "DSP_0_PCOUT5", - "DSP_0_PCOUT6", - "DSP_0_PCOUT7", - "DSP_0_PCOUT8", - "DSP_0_PCOUT9", - "DSP_0_RSTA", - "DSP_0_RSTALLCARRYIN", - "DSP_0_RSTALUMODE", - "DSP_0_RSTB", - "DSP_0_RSTC", - "DSP_0_RSTCTRL", - "DSP_0_RSTD", - "DSP_0_RSTINMODE", - "DSP_0_RSTM", - "DSP_0_RSTP", - "DSP_0_UNDERFLOW", - "DSP_1_A0", - "DSP_1_A1", - "DSP_1_A10", - "DSP_1_A11", - "DSP_1_A12", - "DSP_1_A13", - "DSP_1_A14", - "DSP_1_A15", - "DSP_1_A16", - "DSP_1_A17", - "DSP_1_A18", - "DSP_1_A19", - "DSP_1_A2", - "DSP_1_A20", - "DSP_1_A21", - "DSP_1_A22", - "DSP_1_A23", - "DSP_1_A24", - "DSP_1_A25", - "DSP_1_A26", - "DSP_1_A27", - "DSP_1_A28", - "DSP_1_A29", - "DSP_1_A3", - "DSP_1_A4", - "DSP_1_A5", - "DSP_1_A6", - "DSP_1_A7", - "DSP_1_A8", - "DSP_1_A9", - "DSP_1_ACIN0", - "DSP_1_ACIN1", - "DSP_1_ACIN10", - "DSP_1_ACIN11", - "DSP_1_ACIN12", - "DSP_1_ACIN13", - "DSP_1_ACIN14", - "DSP_1_ACIN15", - "DSP_1_ACIN16", - "DSP_1_ACIN17", - "DSP_1_ACIN18", - "DSP_1_ACIN19", - "DSP_1_ACIN2", - "DSP_1_ACIN20", - "DSP_1_ACIN21", - "DSP_1_ACIN22", - "DSP_1_ACIN23", - "DSP_1_ACIN24", - "DSP_1_ACIN25", - "DSP_1_ACIN26", - "DSP_1_ACIN27", - "DSP_1_ACIN28", - "DSP_1_ACIN29", - "DSP_1_ACIN3", - "DSP_1_ACIN4", - "DSP_1_ACIN5", - "DSP_1_ACIN6", - "DSP_1_ACIN7", - "DSP_1_ACIN8", - "DSP_1_ACIN9", - "DSP_1_ACOUT0", - "DSP_1_ACOUT1", - "DSP_1_ACOUT10", - "DSP_1_ACOUT11", - "DSP_1_ACOUT12", - "DSP_1_ACOUT13", - "DSP_1_ACOUT14", - "DSP_1_ACOUT15", - "DSP_1_ACOUT16", - "DSP_1_ACOUT17", - "DSP_1_ACOUT18", - "DSP_1_ACOUT19", - "DSP_1_ACOUT2", - "DSP_1_ACOUT20", - "DSP_1_ACOUT21", - "DSP_1_ACOUT22", - "DSP_1_ACOUT23", - "DSP_1_ACOUT24", - "DSP_1_ACOUT25", - "DSP_1_ACOUT26", - "DSP_1_ACOUT27", - "DSP_1_ACOUT28", - "DSP_1_ACOUT29", - "DSP_1_ACOUT3", - "DSP_1_ACOUT4", - "DSP_1_ACOUT5", - "DSP_1_ACOUT6", - "DSP_1_ACOUT7", - "DSP_1_ACOUT8", - "DSP_1_ACOUT9", - "DSP_1_ALUMODE0", - "DSP_1_ALUMODE1", - "DSP_1_ALUMODE2", - "DSP_1_ALUMODE3", - "DSP_1_B0", - "DSP_1_B1", - "DSP_1_B10", - "DSP_1_B11", - "DSP_1_B12", - "DSP_1_B13", - "DSP_1_B14", - "DSP_1_B15", - "DSP_1_B16", - "DSP_1_B17", - "DSP_1_B2", - "DSP_1_B3", - "DSP_1_B4", - "DSP_1_B5", - "DSP_1_B6", - "DSP_1_B7", - "DSP_1_B8", - "DSP_1_B9", - "DSP_1_BCIN0", - "DSP_1_BCIN1", - "DSP_1_BCIN10", - "DSP_1_BCIN11", - "DSP_1_BCIN12", - "DSP_1_BCIN13", - "DSP_1_BCIN14", - "DSP_1_BCIN15", - "DSP_1_BCIN16", - "DSP_1_BCIN17", - "DSP_1_BCIN2", - "DSP_1_BCIN3", - "DSP_1_BCIN4", - "DSP_1_BCIN5", - "DSP_1_BCIN6", - "DSP_1_BCIN7", - "DSP_1_BCIN8", - "DSP_1_BCIN9", - "DSP_1_BCOUT0", - "DSP_1_BCOUT1", - "DSP_1_BCOUT10", - "DSP_1_BCOUT11", - "DSP_1_BCOUT12", - "DSP_1_BCOUT13", - "DSP_1_BCOUT14", - "DSP_1_BCOUT15", - "DSP_1_BCOUT16", - "DSP_1_BCOUT17", - "DSP_1_BCOUT2", - "DSP_1_BCOUT3", - "DSP_1_BCOUT4", - "DSP_1_BCOUT5", - "DSP_1_BCOUT6", - "DSP_1_BCOUT7", - "DSP_1_BCOUT8", - "DSP_1_BCOUT9", - "DSP_1_C0", - "DSP_1_C1", - "DSP_1_C10", - "DSP_1_C11", - "DSP_1_C12", - "DSP_1_C13", - "DSP_1_C14", - "DSP_1_C15", - "DSP_1_C16", - "DSP_1_C17", - "DSP_1_C18", - "DSP_1_C19", - "DSP_1_C2", - "DSP_1_C20", - "DSP_1_C21", - "DSP_1_C22", - "DSP_1_C23", - "DSP_1_C24", - "DSP_1_C25", - "DSP_1_C26", - "DSP_1_C27", - "DSP_1_C28", - "DSP_1_C29", - "DSP_1_C3", - "DSP_1_C30", - "DSP_1_C31", - "DSP_1_C32", - "DSP_1_C33", - "DSP_1_C34", - "DSP_1_C35", - "DSP_1_C36", - "DSP_1_C37", - "DSP_1_C38", - "DSP_1_C39", - "DSP_1_C4", - "DSP_1_C40", - "DSP_1_C41", - "DSP_1_C42", - "DSP_1_C43", - "DSP_1_C44", - "DSP_1_C45", - "DSP_1_C46", - "DSP_1_C47", - "DSP_1_C5", - "DSP_1_C6", - "DSP_1_C7", - "DSP_1_C8", - "DSP_1_C9", - "DSP_1_CARRYCASCIN", - "DSP_1_CARRYCASCOUT", - "DSP_1_CARRYIN", - "DSP_1_CARRYINSEL0", - "DSP_1_CARRYINSEL1", - "DSP_1_CARRYINSEL2", - "DSP_1_CARRYOUT0", - "DSP_1_CARRYOUT1", - "DSP_1_CARRYOUT2", - "DSP_1_CARRYOUT3", - "DSP_1_CEA1", - "DSP_1_CEA2", - "DSP_1_CEAD", - "DSP_1_CEALUMODE", - "DSP_1_CEB1", - "DSP_1_CEB2", - "DSP_1_CEC", - "DSP_1_CECARRYIN", - "DSP_1_CECTRL", - "DSP_1_CED", - "DSP_1_CEINMODE", - "DSP_1_CEM", - "DSP_1_CEP", - "DSP_1_CLK", - "DSP_1_D0", - "DSP_1_D1", - "DSP_1_D10", - "DSP_1_D11", - "DSP_1_D12", - "DSP_1_D13", - "DSP_1_D14", - "DSP_1_D15", - "DSP_1_D16", - "DSP_1_D17", - "DSP_1_D18", - "DSP_1_D19", - "DSP_1_D2", - "DSP_1_D20", - "DSP_1_D21", - "DSP_1_D22", - "DSP_1_D23", - "DSP_1_D24", - "DSP_1_D3", - "DSP_1_D4", - "DSP_1_D5", - "DSP_1_D6", - "DSP_1_D7", - "DSP_1_D8", - "DSP_1_D9", - "DSP_1_INMODE0", - "DSP_1_INMODE1", - "DSP_1_INMODE2", - "DSP_1_INMODE3", - "DSP_1_INMODE4", - "DSP_1_MULTSIGNIN", - "DSP_1_MULTSIGNOUT", - "DSP_1_OPMODE0", - "DSP_1_OPMODE1", - "DSP_1_OPMODE2", - "DSP_1_OPMODE3", - "DSP_1_OPMODE4", - "DSP_1_OPMODE5", - "DSP_1_OPMODE6", - "DSP_1_OVERFLOW", - "DSP_1_P0", - "DSP_1_P1", - "DSP_1_P10", - "DSP_1_P11", - "DSP_1_P12", - "DSP_1_P13", - "DSP_1_P14", - "DSP_1_P15", - "DSP_1_P16", - "DSP_1_P17", - "DSP_1_P18", - "DSP_1_P19", - "DSP_1_P2", - "DSP_1_P20", - "DSP_1_P21", - "DSP_1_P22", - "DSP_1_P23", - "DSP_1_P24", - "DSP_1_P25", - "DSP_1_P26", - "DSP_1_P27", - "DSP_1_P28", - "DSP_1_P29", - "DSP_1_P3", - "DSP_1_P30", - "DSP_1_P31", - "DSP_1_P32", - "DSP_1_P33", - "DSP_1_P34", - "DSP_1_P35", - "DSP_1_P36", - "DSP_1_P37", - "DSP_1_P38", - "DSP_1_P39", - "DSP_1_P4", - "DSP_1_P40", - "DSP_1_P41", - "DSP_1_P42", - "DSP_1_P43", - "DSP_1_P44", - "DSP_1_P45", - "DSP_1_P46", - "DSP_1_P47", - "DSP_1_P5", - "DSP_1_P6", - "DSP_1_P7", - "DSP_1_P8", - "DSP_1_P9", - "DSP_1_PATTERNBDETECT", - "DSP_1_PATTERNDETECT", - "DSP_1_PCIN0", - "DSP_1_PCIN1", - "DSP_1_PCIN10", - "DSP_1_PCIN11", - "DSP_1_PCIN12", - "DSP_1_PCIN13", - "DSP_1_PCIN14", - "DSP_1_PCIN15", - "DSP_1_PCIN16", - "DSP_1_PCIN17", - "DSP_1_PCIN18", - "DSP_1_PCIN19", - "DSP_1_PCIN2", - "DSP_1_PCIN20", - "DSP_1_PCIN21", - "DSP_1_PCIN22", - "DSP_1_PCIN23", - "DSP_1_PCIN24", - "DSP_1_PCIN25", - "DSP_1_PCIN26", - "DSP_1_PCIN27", - "DSP_1_PCIN28", - "DSP_1_PCIN29", - "DSP_1_PCIN3", - "DSP_1_PCIN30", - "DSP_1_PCIN31", - "DSP_1_PCIN32", - "DSP_1_PCIN33", - "DSP_1_PCIN34", - "DSP_1_PCIN35", - "DSP_1_PCIN36", - "DSP_1_PCIN37", - "DSP_1_PCIN38", - "DSP_1_PCIN39", - "DSP_1_PCIN4", - "DSP_1_PCIN40", - "DSP_1_PCIN41", - "DSP_1_PCIN42", - "DSP_1_PCIN43", - "DSP_1_PCIN44", - "DSP_1_PCIN45", - "DSP_1_PCIN46", - "DSP_1_PCIN47", - "DSP_1_PCIN5", - "DSP_1_PCIN6", - "DSP_1_PCIN7", - "DSP_1_PCIN8", - "DSP_1_PCIN9", - "DSP_1_PCOUT0", - "DSP_1_PCOUT1", - "DSP_1_PCOUT10", - "DSP_1_PCOUT11", - "DSP_1_PCOUT12", - "DSP_1_PCOUT13", - "DSP_1_PCOUT14", - "DSP_1_PCOUT15", - "DSP_1_PCOUT16", - "DSP_1_PCOUT17", - "DSP_1_PCOUT18", - "DSP_1_PCOUT19", - "DSP_1_PCOUT2", - "DSP_1_PCOUT20", - "DSP_1_PCOUT21", - "DSP_1_PCOUT22", - "DSP_1_PCOUT23", - "DSP_1_PCOUT24", - "DSP_1_PCOUT25", - "DSP_1_PCOUT26", - "DSP_1_PCOUT27", - "DSP_1_PCOUT28", - "DSP_1_PCOUT29", - "DSP_1_PCOUT3", - "DSP_1_PCOUT30", - "DSP_1_PCOUT31", - "DSP_1_PCOUT32", - "DSP_1_PCOUT33", - "DSP_1_PCOUT34", - "DSP_1_PCOUT35", - "DSP_1_PCOUT36", - "DSP_1_PCOUT37", - "DSP_1_PCOUT38", - "DSP_1_PCOUT39", - "DSP_1_PCOUT4", - "DSP_1_PCOUT40", - "DSP_1_PCOUT41", - "DSP_1_PCOUT42", - "DSP_1_PCOUT43", - "DSP_1_PCOUT44", - "DSP_1_PCOUT45", - "DSP_1_PCOUT46", - "DSP_1_PCOUT47", - "DSP_1_PCOUT5", - "DSP_1_PCOUT6", - "DSP_1_PCOUT7", - "DSP_1_PCOUT8", - "DSP_1_PCOUT9", - "DSP_1_RSTA", - "DSP_1_RSTALLCARRYIN", - "DSP_1_RSTALUMODE", - "DSP_1_RSTB", - "DSP_1_RSTC", - "DSP_1_RSTCTRL", - "DSP_1_RSTD", - "DSP_1_RSTINMODE", - "DSP_1_RSTM", - "DSP_1_RSTP", - "DSP_1_UNDERFLOW", - "DSP_ACOUT0", - "DSP_ACOUT1", - "DSP_ACOUT10", - "DSP_ACOUT11", - "DSP_ACOUT12", - "DSP_ACOUT13", - "DSP_ACOUT14", - "DSP_ACOUT15", - "DSP_ACOUT16", - "DSP_ACOUT17", - "DSP_ACOUT18", - "DSP_ACOUT19", - "DSP_ACOUT2", - "DSP_ACOUT20", - "DSP_ACOUT21", - "DSP_ACOUT22", - "DSP_ACOUT23", - "DSP_ACOUT24", - "DSP_ACOUT25", - "DSP_ACOUT26", - "DSP_ACOUT27", - "DSP_ACOUT28", - "DSP_ACOUT29", - "DSP_ACOUT3", - "DSP_ACOUT4", - "DSP_ACOUT5", - "DSP_ACOUT6", - "DSP_ACOUT7", - "DSP_ACOUT8", - "DSP_ACOUT9", - "DSP_BCOUT0", - "DSP_BCOUT1", - "DSP_BCOUT10", - "DSP_BCOUT11", - "DSP_BCOUT12", - "DSP_BCOUT13", - "DSP_BCOUT14", - "DSP_BCOUT15", - "DSP_BCOUT16", - "DSP_BCOUT17", - "DSP_BCOUT2", - "DSP_BCOUT3", - "DSP_BCOUT4", - "DSP_BCOUT5", - "DSP_BCOUT6", - "DSP_BCOUT7", - "DSP_BCOUT8", - "DSP_BCOUT9", - "DSP_BLOCK_OUTS_B0_0", - "DSP_BLOCK_OUTS_B0_1", - "DSP_BLOCK_OUTS_B0_2", - "DSP_BLOCK_OUTS_B0_3", - "DSP_BLOCK_OUTS_B0_4", - "DSP_BLOCK_OUTS_B1_0", - "DSP_BLOCK_OUTS_B1_1", - "DSP_BLOCK_OUTS_B1_2", - "DSP_BLOCK_OUTS_B1_3", - "DSP_BLOCK_OUTS_B1_4", - "DSP_BLOCK_OUTS_B2_0", - "DSP_BLOCK_OUTS_B2_1", - "DSP_BLOCK_OUTS_B2_2", - "DSP_BLOCK_OUTS_B2_3", - "DSP_BLOCK_OUTS_B2_4", - "DSP_BLOCK_OUTS_B3_0", - "DSP_BLOCK_OUTS_B3_1", - "DSP_BLOCK_OUTS_B3_2", - "DSP_BLOCK_OUTS_B3_3", - "DSP_BLOCK_OUTS_B3_4", - "DSP_BYP0_0", - "DSP_BYP0_1", - "DSP_BYP0_2", - "DSP_BYP0_3", - "DSP_BYP0_4", - "DSP_BYP1_0", - "DSP_BYP1_1", - "DSP_BYP1_2", - "DSP_BYP1_3", - "DSP_BYP1_4", - "DSP_BYP2_0", - "DSP_BYP2_1", - "DSP_BYP2_2", - "DSP_BYP2_3", - "DSP_BYP2_4", - "DSP_BYP3_0", - "DSP_BYP3_1", - "DSP_BYP3_2", - "DSP_BYP3_3", - "DSP_BYP3_4", - "DSP_BYP4_0", - "DSP_BYP4_1", - "DSP_BYP4_2", - "DSP_BYP4_3", - "DSP_BYP4_4", - "DSP_BYP5_0", - "DSP_BYP5_1", - "DSP_BYP5_2", - "DSP_BYP5_3", - "DSP_BYP5_4", - "DSP_BYP6_0", - "DSP_BYP6_1", - "DSP_BYP6_2", - "DSP_BYP6_3", - "DSP_BYP6_4", - "DSP_BYP7_0", - "DSP_BYP7_1", - "DSP_BYP7_2", - "DSP_BYP7_3", - "DSP_BYP7_4", - "DSP_CARRYCASCOUT", - "DSP_CLK0_0", - "DSP_CLK0_1", - "DSP_CLK0_2", - "DSP_CLK0_3", - "DSP_CLK0_4", - "DSP_CLK1_0", - "DSP_CLK1_1", - "DSP_CLK1_2", - "DSP_CLK1_3", - "DSP_CLK1_4", - "DSP_CTRL0_0", - "DSP_CTRL0_1", - "DSP_CTRL0_2", - "DSP_CTRL0_3", - "DSP_CTRL0_4", - "DSP_CTRL1_0", - "DSP_CTRL1_1", - "DSP_CTRL1_2", - "DSP_CTRL1_3", - "DSP_CTRL1_4", - "DSP_EE2A0_0", - "DSP_EE2A0_1", - "DSP_EE2A0_2", - "DSP_EE2A0_3", - "DSP_EE2A0_4", - "DSP_EE2A1_0", - "DSP_EE2A1_1", - "DSP_EE2A1_2", - "DSP_EE2A1_3", - "DSP_EE2A1_4", - "DSP_EE2A2_0", - "DSP_EE2A2_1", - "DSP_EE2A2_2", - "DSP_EE2A2_3", - "DSP_EE2A2_4", - "DSP_EE2A3_0", - "DSP_EE2A3_1", - "DSP_EE2A3_2", - "DSP_EE2A3_3", - "DSP_EE2A3_4", - "DSP_EE2BEG0_0", - "DSP_EE2BEG0_1", - "DSP_EE2BEG0_2", - "DSP_EE2BEG0_3", - "DSP_EE2BEG0_4", - "DSP_EE2BEG1_0", - "DSP_EE2BEG1_1", - "DSP_EE2BEG1_2", - "DSP_EE2BEG1_3", - "DSP_EE2BEG1_4", - "DSP_EE2BEG2_0", - "DSP_EE2BEG2_1", - "DSP_EE2BEG2_2", - "DSP_EE2BEG2_3", - "DSP_EE2BEG2_4", - "DSP_EE2BEG3_0", - "DSP_EE2BEG3_1", - "DSP_EE2BEG3_2", - "DSP_EE2BEG3_3", - "DSP_EE2BEG3_4", - "DSP_EE4A0_0", - "DSP_EE4A0_1", - "DSP_EE4A0_2", - "DSP_EE4A0_3", - "DSP_EE4A0_4", - "DSP_EE4A1_0", - "DSP_EE4A1_1", - "DSP_EE4A1_2", - "DSP_EE4A1_3", - "DSP_EE4A1_4", - "DSP_EE4A2_0", - "DSP_EE4A2_1", - "DSP_EE4A2_2", - "DSP_EE4A2_3", - "DSP_EE4A2_4", - "DSP_EE4A3_0", - "DSP_EE4A3_1", - "DSP_EE4A3_2", - "DSP_EE4A3_3", - "DSP_EE4A3_4", - "DSP_EE4B0_0", - "DSP_EE4B0_1", - "DSP_EE4B0_2", - "DSP_EE4B0_3", - "DSP_EE4B0_4", - "DSP_EE4B1_0", - "DSP_EE4B1_1", - "DSP_EE4B1_2", - "DSP_EE4B1_3", - "DSP_EE4B1_4", - "DSP_EE4B2_0", - "DSP_EE4B2_1", - "DSP_EE4B2_2", - "DSP_EE4B2_3", - "DSP_EE4B2_4", - "DSP_EE4B3_0", - "DSP_EE4B3_1", - "DSP_EE4B3_2", - "DSP_EE4B3_3", - "DSP_EE4B3_4", - "DSP_EE4BEG0_0", - "DSP_EE4BEG0_1", - "DSP_EE4BEG0_2", - "DSP_EE4BEG0_3", - "DSP_EE4BEG0_4", - "DSP_EE4BEG1_0", - "DSP_EE4BEG1_1", - "DSP_EE4BEG1_2", - "DSP_EE4BEG1_3", - "DSP_EE4BEG1_4", - "DSP_EE4BEG2_0", - "DSP_EE4BEG2_1", - "DSP_EE4BEG2_2", - "DSP_EE4BEG2_3", - "DSP_EE4BEG2_4", - "DSP_EE4BEG3_0", - "DSP_EE4BEG3_1", - "DSP_EE4BEG3_2", - "DSP_EE4BEG3_3", - "DSP_EE4BEG3_4", - "DSP_EE4C0_0", - "DSP_EE4C0_1", - "DSP_EE4C0_2", - "DSP_EE4C0_3", - "DSP_EE4C0_4", - "DSP_EE4C1_0", - "DSP_EE4C1_1", - "DSP_EE4C1_2", - "DSP_EE4C1_3", - "DSP_EE4C1_4", - "DSP_EE4C2_0", - "DSP_EE4C2_1", - "DSP_EE4C2_2", - "DSP_EE4C2_3", - "DSP_EE4C2_4", - "DSP_EE4C3_0", - "DSP_EE4C3_1", - "DSP_EE4C3_2", - "DSP_EE4C3_3", - "DSP_EE4C3_4", - "DSP_EL1BEG0_0", - "DSP_EL1BEG0_1", - "DSP_EL1BEG0_2", - "DSP_EL1BEG0_3", - "DSP_EL1BEG0_4", - "DSP_EL1BEG1_0", - "DSP_EL1BEG1_1", - "DSP_EL1BEG1_2", - "DSP_EL1BEG1_3", - "DSP_EL1BEG1_4", - "DSP_EL1BEG2_0", - "DSP_EL1BEG2_1", - "DSP_EL1BEG2_2", - "DSP_EL1BEG2_3", - "DSP_EL1BEG2_4", - "DSP_EL1BEG3_0", - "DSP_EL1BEG3_1", - "DSP_EL1BEG3_2", - "DSP_EL1BEG3_3", - "DSP_EL1BEG3_4", - "DSP_ER1BEG0_0", - "DSP_ER1BEG0_1", - "DSP_ER1BEG0_2", - "DSP_ER1BEG0_3", - "DSP_ER1BEG0_4", - "DSP_ER1BEG1_0", - "DSP_ER1BEG1_1", - "DSP_ER1BEG1_2", - "DSP_ER1BEG1_3", - "DSP_ER1BEG1_4", - "DSP_ER1BEG2_0", - "DSP_ER1BEG2_1", - "DSP_ER1BEG2_2", - "DSP_ER1BEG2_3", - "DSP_ER1BEG2_4", - "DSP_ER1BEG3_0", - "DSP_ER1BEG3_1", - "DSP_ER1BEG3_2", - "DSP_ER1BEG3_3", - "DSP_ER1BEG3_4", - "DSP_FAN0_0", - "DSP_FAN0_1", - "DSP_FAN0_2", - "DSP_FAN0_3", - "DSP_FAN0_4", - "DSP_FAN1_0", - "DSP_FAN1_1", - "DSP_FAN1_2", - "DSP_FAN1_3", - "DSP_FAN1_4", - "DSP_FAN2_0", - "DSP_FAN2_1", - "DSP_FAN2_2", - "DSP_FAN2_3", - "DSP_FAN2_4", - "DSP_FAN3_0", - "DSP_FAN3_1", - "DSP_FAN3_2", - "DSP_FAN3_3", - "DSP_FAN3_4", - "DSP_FAN4_0", - "DSP_FAN4_1", - "DSP_FAN4_2", - "DSP_FAN4_3", - "DSP_FAN4_4", - "DSP_FAN5_0", - "DSP_FAN5_1", - "DSP_FAN5_2", - "DSP_FAN5_3", - "DSP_FAN5_4", - "DSP_FAN6_0", - "DSP_FAN6_1", - "DSP_FAN6_2", - "DSP_FAN6_3", - "DSP_FAN6_4", - "DSP_FAN7_0", - "DSP_FAN7_1", - "DSP_FAN7_2", - "DSP_FAN7_3", - "DSP_FAN7_4", - "DSP_GND_L", - "DSP_IMUX0_0", - "DSP_IMUX0_1", - "DSP_IMUX0_2", - "DSP_IMUX0_3", - "DSP_IMUX0_4", - "DSP_IMUX10_0", - "DSP_IMUX10_1", - "DSP_IMUX10_2", - "DSP_IMUX10_3", - "DSP_IMUX10_4", - "DSP_IMUX11_0", - "DSP_IMUX11_1", - "DSP_IMUX11_2", - "DSP_IMUX11_3", - "DSP_IMUX11_4", - "DSP_IMUX12_0", - "DSP_IMUX12_1", - "DSP_IMUX12_2", - "DSP_IMUX12_3", - "DSP_IMUX12_4", - "DSP_IMUX13_0", - "DSP_IMUX13_1", - "DSP_IMUX13_2", - "DSP_IMUX13_3", - "DSP_IMUX13_4", - "DSP_IMUX14_0", - "DSP_IMUX14_1", - "DSP_IMUX14_2", - "DSP_IMUX14_3", - "DSP_IMUX14_4", - "DSP_IMUX15_0", - "DSP_IMUX15_1", - "DSP_IMUX15_2", - "DSP_IMUX15_3", - "DSP_IMUX15_4", - "DSP_IMUX16_0", - "DSP_IMUX16_1", - "DSP_IMUX16_2", - "DSP_IMUX16_3", - "DSP_IMUX16_4", - "DSP_IMUX17_0", - "DSP_IMUX17_1", - "DSP_IMUX17_2", - "DSP_IMUX17_3", - "DSP_IMUX17_4", - "DSP_IMUX18_0", - "DSP_IMUX18_1", - "DSP_IMUX18_2", - "DSP_IMUX18_3", - "DSP_IMUX18_4", - "DSP_IMUX19_0", - "DSP_IMUX19_1", - "DSP_IMUX19_2", - "DSP_IMUX19_3", - "DSP_IMUX19_4", - "DSP_IMUX1_0", - "DSP_IMUX1_1", - "DSP_IMUX1_2", - "DSP_IMUX1_3", - "DSP_IMUX1_4", - "DSP_IMUX20_0", - "DSP_IMUX20_1", - "DSP_IMUX20_2", - "DSP_IMUX20_3", - "DSP_IMUX20_4", - "DSP_IMUX21_0", - "DSP_IMUX21_1", - "DSP_IMUX21_2", - "DSP_IMUX21_3", - "DSP_IMUX21_4", - "DSP_IMUX22_0", - "DSP_IMUX22_1", - "DSP_IMUX22_2", - "DSP_IMUX22_3", - "DSP_IMUX22_4", - "DSP_IMUX23_0", - "DSP_IMUX23_1", - "DSP_IMUX23_2", - "DSP_IMUX23_3", - "DSP_IMUX23_4", - "DSP_IMUX24_0", - "DSP_IMUX24_1", - "DSP_IMUX24_2", - "DSP_IMUX24_3", - "DSP_IMUX24_4", - "DSP_IMUX25_0", - "DSP_IMUX25_1", - "DSP_IMUX25_2", - "DSP_IMUX25_3", - "DSP_IMUX25_4", - "DSP_IMUX26_0", - "DSP_IMUX26_1", - "DSP_IMUX26_2", - "DSP_IMUX26_3", - "DSP_IMUX26_4", - "DSP_IMUX27_0", - "DSP_IMUX27_1", - "DSP_IMUX27_2", - "DSP_IMUX27_3", - "DSP_IMUX27_4", - "DSP_IMUX28_0", - "DSP_IMUX28_1", - "DSP_IMUX28_2", - "DSP_IMUX28_3", - "DSP_IMUX28_4", - "DSP_IMUX29_0", - "DSP_IMUX29_1", - "DSP_IMUX29_2", - "DSP_IMUX29_3", - "DSP_IMUX29_4", - "DSP_IMUX2_0", - "DSP_IMUX2_1", - "DSP_IMUX2_2", - "DSP_IMUX2_3", - "DSP_IMUX2_4", - "DSP_IMUX30_0", - "DSP_IMUX30_1", - "DSP_IMUX30_2", - "DSP_IMUX30_3", - "DSP_IMUX30_4", - "DSP_IMUX31_0", - "DSP_IMUX31_1", - "DSP_IMUX31_2", - "DSP_IMUX31_3", - "DSP_IMUX31_4", - "DSP_IMUX32_0", - "DSP_IMUX32_1", - "DSP_IMUX32_2", - "DSP_IMUX32_3", - "DSP_IMUX32_4", - "DSP_IMUX33_0", - "DSP_IMUX33_1", - "DSP_IMUX33_2", - "DSP_IMUX33_3", - "DSP_IMUX33_4", - "DSP_IMUX34_0", - "DSP_IMUX34_1", - "DSP_IMUX34_2", - "DSP_IMUX34_3", - "DSP_IMUX34_4", - "DSP_IMUX35_0", - "DSP_IMUX35_1", - "DSP_IMUX35_2", - "DSP_IMUX35_3", - "DSP_IMUX35_4", - "DSP_IMUX36_0", - "DSP_IMUX36_1", - "DSP_IMUX36_2", - "DSP_IMUX36_3", - "DSP_IMUX36_4", - "DSP_IMUX37_0", - "DSP_IMUX37_1", - "DSP_IMUX37_2", - "DSP_IMUX37_3", - "DSP_IMUX37_4", - "DSP_IMUX38_0", - "DSP_IMUX38_1", - "DSP_IMUX38_2", - "DSP_IMUX38_3", - "DSP_IMUX38_4", - "DSP_IMUX39_0", - "DSP_IMUX39_1", - "DSP_IMUX39_2", - "DSP_IMUX39_3", - "DSP_IMUX39_4", - "DSP_IMUX3_0", - "DSP_IMUX3_1", - "DSP_IMUX3_2", - "DSP_IMUX3_3", - "DSP_IMUX3_4", - "DSP_IMUX40_0", - "DSP_IMUX40_1", - "DSP_IMUX40_2", - "DSP_IMUX40_3", - "DSP_IMUX40_4", - "DSP_IMUX41_0", - "DSP_IMUX41_1", - "DSP_IMUX41_2", - "DSP_IMUX41_3", - "DSP_IMUX41_4", - "DSP_IMUX42_0", - "DSP_IMUX42_1", - "DSP_IMUX42_2", - "DSP_IMUX42_3", - "DSP_IMUX42_4", - "DSP_IMUX43_0", - "DSP_IMUX43_1", - "DSP_IMUX43_2", - "DSP_IMUX43_3", - "DSP_IMUX43_4", - "DSP_IMUX44_0", - "DSP_IMUX44_1", - "DSP_IMUX44_2", - "DSP_IMUX44_3", - "DSP_IMUX44_4", - "DSP_IMUX45_0", - "DSP_IMUX45_1", - "DSP_IMUX45_2", - "DSP_IMUX45_3", - "DSP_IMUX45_4", - "DSP_IMUX46_0", - "DSP_IMUX46_1", - "DSP_IMUX46_2", - "DSP_IMUX46_3", - "DSP_IMUX46_4", - "DSP_IMUX47_0", - "DSP_IMUX47_1", - "DSP_IMUX47_2", - "DSP_IMUX47_3", - "DSP_IMUX47_4", - "DSP_IMUX4_0", - "DSP_IMUX4_1", - "DSP_IMUX4_2", - "DSP_IMUX4_3", - "DSP_IMUX4_4", - "DSP_IMUX5_0", - "DSP_IMUX5_1", - "DSP_IMUX5_2", - "DSP_IMUX5_3", - "DSP_IMUX5_4", - "DSP_IMUX6_0", - "DSP_IMUX6_1", - "DSP_IMUX6_2", - "DSP_IMUX6_3", - "DSP_IMUX6_4", - "DSP_IMUX7_0", - "DSP_IMUX7_1", - "DSP_IMUX7_2", - "DSP_IMUX7_3", - "DSP_IMUX7_4", - "DSP_IMUX8_0", - "DSP_IMUX8_1", - "DSP_IMUX8_2", - "DSP_IMUX8_3", - "DSP_IMUX8_4", - "DSP_IMUX9_0", - "DSP_IMUX9_1", - "DSP_IMUX9_2", - "DSP_IMUX9_3", - "DSP_IMUX9_4", - "DSP_LH10_0", - "DSP_LH10_1", - "DSP_LH10_2", - "DSP_LH10_3", - "DSP_LH10_4", - "DSP_LH11_0", - "DSP_LH11_1", - "DSP_LH11_2", - "DSP_LH11_3", - "DSP_LH11_4", - "DSP_LH12_0", - "DSP_LH12_1", - "DSP_LH12_2", - "DSP_LH12_3", - "DSP_LH12_4", - "DSP_LH1_0", - "DSP_LH1_1", - "DSP_LH1_2", - "DSP_LH1_3", - "DSP_LH1_4", - "DSP_LH2_0", - "DSP_LH2_1", - "DSP_LH2_2", - "DSP_LH2_3", - "DSP_LH2_4", - "DSP_LH3_0", - "DSP_LH3_1", - "DSP_LH3_2", - "DSP_LH3_3", - "DSP_LH3_4", - "DSP_LH4_0", - "DSP_LH4_1", - "DSP_LH4_2", - "DSP_LH4_3", - "DSP_LH4_4", - "DSP_LH5_0", - "DSP_LH5_1", - "DSP_LH5_2", - "DSP_LH5_3", - "DSP_LH5_4", - "DSP_LH6_0", - "DSP_LH6_1", - "DSP_LH6_2", - "DSP_LH6_3", - "DSP_LH6_4", - "DSP_LH7_0", - "DSP_LH7_1", - "DSP_LH7_2", - "DSP_LH7_3", - "DSP_LH7_4", - "DSP_LH8_0", - "DSP_LH8_1", - "DSP_LH8_2", - "DSP_LH8_3", - "DSP_LH8_4", - "DSP_LH9_0", - "DSP_LH9_1", - "DSP_LH9_2", - "DSP_LH9_3", - "DSP_LH9_4", - "DSP_LOGIC_OUTS_B0_0", - "DSP_LOGIC_OUTS_B0_1", - "DSP_LOGIC_OUTS_B0_2", - "DSP_LOGIC_OUTS_B0_3", - "DSP_LOGIC_OUTS_B0_4", - "DSP_LOGIC_OUTS_B10_0", - "DSP_LOGIC_OUTS_B10_1", - "DSP_LOGIC_OUTS_B10_2", - "DSP_LOGIC_OUTS_B10_3", - "DSP_LOGIC_OUTS_B10_4", - "DSP_LOGIC_OUTS_B11_0", - "DSP_LOGIC_OUTS_B11_1", - "DSP_LOGIC_OUTS_B11_2", - "DSP_LOGIC_OUTS_B11_3", - "DSP_LOGIC_OUTS_B11_4", - "DSP_LOGIC_OUTS_B12_0", - "DSP_LOGIC_OUTS_B12_1", - "DSP_LOGIC_OUTS_B12_2", - "DSP_LOGIC_OUTS_B12_3", - "DSP_LOGIC_OUTS_B12_4", - "DSP_LOGIC_OUTS_B13_0", - "DSP_LOGIC_OUTS_B13_1", - "DSP_LOGIC_OUTS_B13_2", - "DSP_LOGIC_OUTS_B13_3", - "DSP_LOGIC_OUTS_B13_4", - "DSP_LOGIC_OUTS_B14_0", - "DSP_LOGIC_OUTS_B14_1", - "DSP_LOGIC_OUTS_B14_2", - "DSP_LOGIC_OUTS_B14_3", - "DSP_LOGIC_OUTS_B14_4", - "DSP_LOGIC_OUTS_B15_0", - "DSP_LOGIC_OUTS_B15_1", - "DSP_LOGIC_OUTS_B15_2", - "DSP_LOGIC_OUTS_B15_3", - "DSP_LOGIC_OUTS_B15_4", - "DSP_LOGIC_OUTS_B16_0", - "DSP_LOGIC_OUTS_B16_1", - "DSP_LOGIC_OUTS_B16_2", - "DSP_LOGIC_OUTS_B16_3", - "DSP_LOGIC_OUTS_B16_4", - "DSP_LOGIC_OUTS_B17_0", - "DSP_LOGIC_OUTS_B17_1", - "DSP_LOGIC_OUTS_B17_2", - "DSP_LOGIC_OUTS_B17_3", - "DSP_LOGIC_OUTS_B17_4", - "DSP_LOGIC_OUTS_B18_0", - "DSP_LOGIC_OUTS_B18_1", - "DSP_LOGIC_OUTS_B18_2", - "DSP_LOGIC_OUTS_B18_3", - "DSP_LOGIC_OUTS_B18_4", - "DSP_LOGIC_OUTS_B19_0", - "DSP_LOGIC_OUTS_B19_1", - "DSP_LOGIC_OUTS_B19_2", - "DSP_LOGIC_OUTS_B19_3", - "DSP_LOGIC_OUTS_B19_4", - "DSP_LOGIC_OUTS_B1_0", - "DSP_LOGIC_OUTS_B1_1", - "DSP_LOGIC_OUTS_B1_2", - "DSP_LOGIC_OUTS_B1_3", - "DSP_LOGIC_OUTS_B1_4", - "DSP_LOGIC_OUTS_B20_0", - "DSP_LOGIC_OUTS_B20_1", - "DSP_LOGIC_OUTS_B20_2", - "DSP_LOGIC_OUTS_B20_3", - "DSP_LOGIC_OUTS_B20_4", - "DSP_LOGIC_OUTS_B21_0", - "DSP_LOGIC_OUTS_B21_1", - "DSP_LOGIC_OUTS_B21_2", - "DSP_LOGIC_OUTS_B21_3", - "DSP_LOGIC_OUTS_B21_4", - "DSP_LOGIC_OUTS_B22_0", - "DSP_LOGIC_OUTS_B22_1", - "DSP_LOGIC_OUTS_B22_2", - "DSP_LOGIC_OUTS_B22_3", - "DSP_LOGIC_OUTS_B22_4", - "DSP_LOGIC_OUTS_B23_0", - "DSP_LOGIC_OUTS_B23_1", - "DSP_LOGIC_OUTS_B23_2", - "DSP_LOGIC_OUTS_B23_3", - "DSP_LOGIC_OUTS_B23_4", - "DSP_LOGIC_OUTS_B2_0", - "DSP_LOGIC_OUTS_B2_1", - "DSP_LOGIC_OUTS_B2_2", - "DSP_LOGIC_OUTS_B2_3", - "DSP_LOGIC_OUTS_B2_4", - "DSP_LOGIC_OUTS_B3_0", - "DSP_LOGIC_OUTS_B3_1", - "DSP_LOGIC_OUTS_B3_2", - "DSP_LOGIC_OUTS_B3_3", - "DSP_LOGIC_OUTS_B3_4", - "DSP_LOGIC_OUTS_B4_0", - "DSP_LOGIC_OUTS_B4_1", - "DSP_LOGIC_OUTS_B4_2", - "DSP_LOGIC_OUTS_B4_3", - "DSP_LOGIC_OUTS_B4_4", - "DSP_LOGIC_OUTS_B5_0", - "DSP_LOGIC_OUTS_B5_1", - "DSP_LOGIC_OUTS_B5_2", - "DSP_LOGIC_OUTS_B5_3", - "DSP_LOGIC_OUTS_B5_4", - "DSP_LOGIC_OUTS_B6_0", - "DSP_LOGIC_OUTS_B6_1", - "DSP_LOGIC_OUTS_B6_2", - "DSP_LOGIC_OUTS_B6_3", - "DSP_LOGIC_OUTS_B6_4", - "DSP_LOGIC_OUTS_B7_0", - "DSP_LOGIC_OUTS_B7_1", - "DSP_LOGIC_OUTS_B7_2", - "DSP_LOGIC_OUTS_B7_3", - "DSP_LOGIC_OUTS_B7_4", - "DSP_LOGIC_OUTS_B8_0", - "DSP_LOGIC_OUTS_B8_1", - "DSP_LOGIC_OUTS_B8_2", - "DSP_LOGIC_OUTS_B8_3", - "DSP_LOGIC_OUTS_B8_4", - "DSP_LOGIC_OUTS_B9_0", - "DSP_LOGIC_OUTS_B9_1", - "DSP_LOGIC_OUTS_B9_2", - "DSP_LOGIC_OUTS_B9_3", - "DSP_LOGIC_OUTS_B9_4", - "DSP_MONITOR_N_0", - "DSP_MONITOR_N_1", - "DSP_MONITOR_N_2", - "DSP_MONITOR_N_3", - "DSP_MONITOR_N_4", - "DSP_MONITOR_P_0", - "DSP_MONITOR_P_1", - "DSP_MONITOR_P_2", - "DSP_MONITOR_P_3", - "DSP_MONITOR_P_4", - "DSP_MULTSIGNOUT", - "DSP_NE2A0_0", - "DSP_NE2A0_1", - "DSP_NE2A0_2", - "DSP_NE2A0_3", - "DSP_NE2A0_4", - "DSP_NE2A1_0", - "DSP_NE2A1_1", - "DSP_NE2A1_2", - "DSP_NE2A1_3", - "DSP_NE2A1_4", - "DSP_NE2A2_0", - "DSP_NE2A2_1", - "DSP_NE2A2_2", - "DSP_NE2A2_3", - "DSP_NE2A2_4", - "DSP_NE2A3_0", - "DSP_NE2A3_1", - "DSP_NE2A3_2", - "DSP_NE2A3_3", - "DSP_NE2A3_4", - "DSP_NE4BEG0_0", - "DSP_NE4BEG0_1", - "DSP_NE4BEG0_2", - "DSP_NE4BEG0_3", - "DSP_NE4BEG0_4", - "DSP_NE4BEG1_0", - "DSP_NE4BEG1_1", - "DSP_NE4BEG1_2", - "DSP_NE4BEG1_3", - "DSP_NE4BEG1_4", - "DSP_NE4BEG2_0", - "DSP_NE4BEG2_1", - "DSP_NE4BEG2_2", - "DSP_NE4BEG2_3", - "DSP_NE4BEG2_4", - "DSP_NE4BEG3_0", - "DSP_NE4BEG3_1", - "DSP_NE4BEG3_2", - "DSP_NE4BEG3_3", - "DSP_NE4BEG3_4", - "DSP_NE4C0_0", - "DSP_NE4C0_1", - "DSP_NE4C0_2", - "DSP_NE4C0_3", - "DSP_NE4C0_4", - "DSP_NE4C1_0", - "DSP_NE4C1_1", - "DSP_NE4C1_2", - "DSP_NE4C1_3", - "DSP_NE4C1_4", - "DSP_NE4C2_0", - "DSP_NE4C2_1", - "DSP_NE4C2_2", - "DSP_NE4C2_3", - "DSP_NE4C2_4", - "DSP_NE4C3_0", - "DSP_NE4C3_1", - "DSP_NE4C3_2", - "DSP_NE4C3_3", - "DSP_NE4C3_4", - "DSP_NW2A0_0", - "DSP_NW2A0_1", - "DSP_NW2A0_2", - "DSP_NW2A0_3", - "DSP_NW2A0_4", - "DSP_NW2A1_0", - "DSP_NW2A1_1", - "DSP_NW2A1_2", - "DSP_NW2A1_3", - "DSP_NW2A1_4", - "DSP_NW2A2_0", - "DSP_NW2A2_1", - "DSP_NW2A2_2", - "DSP_NW2A2_3", - "DSP_NW2A2_4", - "DSP_NW2A3_0", - "DSP_NW2A3_1", - "DSP_NW2A3_2", - "DSP_NW2A3_3", - "DSP_NW2A3_4", - "DSP_NW4A0_0", - "DSP_NW4A0_1", - "DSP_NW4A0_2", - "DSP_NW4A0_3", - "DSP_NW4A0_4", - "DSP_NW4A1_0", - "DSP_NW4A1_1", - "DSP_NW4A1_2", - "DSP_NW4A1_3", - "DSP_NW4A1_4", - "DSP_NW4A2_0", - "DSP_NW4A2_1", - "DSP_NW4A2_2", - "DSP_NW4A2_3", - "DSP_NW4A2_4", - "DSP_NW4A3_0", - "DSP_NW4A3_1", - "DSP_NW4A3_2", - "DSP_NW4A3_3", - "DSP_NW4A3_4", - "DSP_NW4END0_0", - "DSP_NW4END0_1", - "DSP_NW4END0_2", - "DSP_NW4END0_3", - "DSP_NW4END0_4", - "DSP_NW4END1_0", - "DSP_NW4END1_1", - "DSP_NW4END1_2", - "DSP_NW4END1_3", - "DSP_NW4END1_4", - "DSP_NW4END2_0", - "DSP_NW4END2_1", - "DSP_NW4END2_2", - "DSP_NW4END2_3", - "DSP_NW4END2_4", - "DSP_NW4END3_0", - "DSP_NW4END3_1", - "DSP_NW4END3_2", - "DSP_NW4END3_3", - "DSP_NW4END3_4", - "DSP_PCOUT0", - "DSP_PCOUT1", - "DSP_PCOUT10", - "DSP_PCOUT11", - "DSP_PCOUT12", - "DSP_PCOUT13", - "DSP_PCOUT14", - "DSP_PCOUT15", - "DSP_PCOUT16", - "DSP_PCOUT17", - "DSP_PCOUT18", - "DSP_PCOUT19", - "DSP_PCOUT2", - "DSP_PCOUT20", - "DSP_PCOUT21", - "DSP_PCOUT22", - "DSP_PCOUT23", - "DSP_PCOUT24", - "DSP_PCOUT25", - "DSP_PCOUT26", - "DSP_PCOUT27", - "DSP_PCOUT28", - "DSP_PCOUT29", - "DSP_PCOUT3", - "DSP_PCOUT30", - "DSP_PCOUT31", - "DSP_PCOUT32", - "DSP_PCOUT33", - "DSP_PCOUT34", - "DSP_PCOUT35", - "DSP_PCOUT36", - "DSP_PCOUT37", - "DSP_PCOUT38", - "DSP_PCOUT39", - "DSP_PCOUT4", - "DSP_PCOUT40", - "DSP_PCOUT41", - "DSP_PCOUT42", - "DSP_PCOUT43", - "DSP_PCOUT44", - "DSP_PCOUT45", - "DSP_PCOUT46", - "DSP_PCOUT47", - "DSP_PCOUT5", - "DSP_PCOUT6", - "DSP_PCOUT7", - "DSP_PCOUT8", - "DSP_PCOUT9", - "DSP_SE2A0_0", - "DSP_SE2A0_1", - "DSP_SE2A0_2", - "DSP_SE2A0_3", - "DSP_SE2A0_4", - "DSP_SE2A1_0", - "DSP_SE2A1_1", - "DSP_SE2A1_2", - "DSP_SE2A1_3", - "DSP_SE2A1_4", - "DSP_SE2A2_0", - "DSP_SE2A2_1", - "DSP_SE2A2_2", - "DSP_SE2A2_3", - "DSP_SE2A2_4", - "DSP_SE2A3_0", - "DSP_SE2A3_1", - "DSP_SE2A3_2", - "DSP_SE2A3_3", - "DSP_SE2A3_4", - "DSP_SE4BEG0_0", - "DSP_SE4BEG0_1", - "DSP_SE4BEG0_2", - "DSP_SE4BEG0_3", - "DSP_SE4BEG0_4", - "DSP_SE4BEG1_0", - "DSP_SE4BEG1_1", - "DSP_SE4BEG1_2", - "DSP_SE4BEG1_3", - "DSP_SE4BEG1_4", - "DSP_SE4BEG2_0", - "DSP_SE4BEG2_1", - "DSP_SE4BEG2_2", - "DSP_SE4BEG2_3", - "DSP_SE4BEG2_4", - "DSP_SE4BEG3_0", - "DSP_SE4BEG3_1", - "DSP_SE4BEG3_2", - "DSP_SE4BEG3_3", - "DSP_SE4BEG3_4", - "DSP_SE4C0_0", - "DSP_SE4C0_1", - "DSP_SE4C0_2", - "DSP_SE4C0_3", - "DSP_SE4C0_4", - "DSP_SE4C1_0", - "DSP_SE4C1_1", - "DSP_SE4C1_2", - "DSP_SE4C1_3", - "DSP_SE4C1_4", - "DSP_SE4C2_0", - "DSP_SE4C2_1", - "DSP_SE4C2_2", - "DSP_SE4C2_3", - "DSP_SE4C2_4", - "DSP_SE4C3_0", - "DSP_SE4C3_1", - "DSP_SE4C3_2", - "DSP_SE4C3_3", - "DSP_SE4C3_4", - "DSP_SW2A0_0", - "DSP_SW2A0_1", - "DSP_SW2A0_2", - "DSP_SW2A0_3", - "DSP_SW2A0_4", - "DSP_SW2A1_0", - "DSP_SW2A1_1", - "DSP_SW2A1_2", - "DSP_SW2A1_3", - "DSP_SW2A1_4", - "DSP_SW2A2_0", - "DSP_SW2A2_1", - "DSP_SW2A2_2", - "DSP_SW2A2_3", - "DSP_SW2A2_4", - "DSP_SW2A3_0", - "DSP_SW2A3_1", - "DSP_SW2A3_2", - "DSP_SW2A3_3", - "DSP_SW2A3_4", - "DSP_SW4A0_0", - "DSP_SW4A0_1", - "DSP_SW4A0_2", - "DSP_SW4A0_3", - "DSP_SW4A0_4", - "DSP_SW4A1_0", - "DSP_SW4A1_1", - "DSP_SW4A1_2", - "DSP_SW4A1_3", - "DSP_SW4A1_4", - "DSP_SW4A2_0", - "DSP_SW4A2_1", - "DSP_SW4A2_2", - "DSP_SW4A2_3", - "DSP_SW4A2_4", - "DSP_SW4A3_0", - "DSP_SW4A3_1", - "DSP_SW4A3_2", - "DSP_SW4A3_3", - "DSP_SW4A3_4", - "DSP_SW4END0_0", - "DSP_SW4END0_1", - "DSP_SW4END0_2", - "DSP_SW4END0_3", - "DSP_SW4END0_4", - "DSP_SW4END1_0", - "DSP_SW4END1_1", - "DSP_SW4END1_2", - "DSP_SW4END1_3", - "DSP_SW4END1_4", - "DSP_SW4END2_0", - "DSP_SW4END2_1", - "DSP_SW4END2_2", - "DSP_SW4END2_3", - "DSP_SW4END2_4", - "DSP_SW4END3_0", - "DSP_SW4END3_1", - "DSP_SW4END3_2", - "DSP_SW4END3_3", - "DSP_SW4END3_4", - "DSP_VCC_L", - "DSP_WL1END0_0", - "DSP_WL1END0_1", - "DSP_WL1END0_2", - "DSP_WL1END0_3", - "DSP_WL1END0_4", - "DSP_WL1END1_0", - "DSP_WL1END1_1", - "DSP_WL1END1_2", - "DSP_WL1END1_3", - "DSP_WL1END1_4", - "DSP_WL1END2_0", - "DSP_WL1END2_1", - "DSP_WL1END2_2", - "DSP_WL1END2_3", - "DSP_WL1END2_4", - "DSP_WL1END3_0", - "DSP_WL1END3_1", - "DSP_WL1END3_2", - "DSP_WL1END3_3", - "DSP_WL1END3_4", - "DSP_WR1END0_0", - "DSP_WR1END0_1", - "DSP_WR1END0_2", - "DSP_WR1END0_3", - "DSP_WR1END0_4", - "DSP_WR1END1_0", - "DSP_WR1END1_1", - "DSP_WR1END1_2", - "DSP_WR1END1_3", - "DSP_WR1END1_4", - "DSP_WR1END2_0", - "DSP_WR1END2_1", - "DSP_WR1END2_2", - "DSP_WR1END2_3", - "DSP_WR1END2_4", - "DSP_WR1END3_0", - "DSP_WR1END3_1", - "DSP_WR1END3_2", - "DSP_WR1END3_3", - "DSP_WR1END3_4", - "DSP_WW2A0_0", - "DSP_WW2A0_1", - "DSP_WW2A0_2", - "DSP_WW2A0_3", - "DSP_WW2A0_4", - "DSP_WW2A1_0", - "DSP_WW2A1_1", - "DSP_WW2A1_2", - "DSP_WW2A1_3", - "DSP_WW2A1_4", - "DSP_WW2A2_0", - "DSP_WW2A2_1", - "DSP_WW2A2_2", - "DSP_WW2A2_3", - "DSP_WW2A2_4", - "DSP_WW2A3_0", - "DSP_WW2A3_1", - "DSP_WW2A3_2", - "DSP_WW2A3_3", - "DSP_WW2A3_4", - "DSP_WW2END0_0", - "DSP_WW2END0_1", - "DSP_WW2END0_2", - "DSP_WW2END0_3", - "DSP_WW2END0_4", - "DSP_WW2END1_0", - "DSP_WW2END1_1", - "DSP_WW2END1_2", - "DSP_WW2END1_3", - "DSP_WW2END1_4", - "DSP_WW2END2_0", - "DSP_WW2END2_1", - "DSP_WW2END2_2", - "DSP_WW2END2_3", - "DSP_WW2END2_4", - "DSP_WW2END3_0", - "DSP_WW2END3_1", - "DSP_WW2END3_2", - "DSP_WW2END3_3", - "DSP_WW2END3_4", - "DSP_WW4A0_0", - "DSP_WW4A0_1", - "DSP_WW4A0_2", - "DSP_WW4A0_3", - "DSP_WW4A0_4", - "DSP_WW4A1_0", - "DSP_WW4A1_1", - "DSP_WW4A1_2", - "DSP_WW4A1_3", - "DSP_WW4A1_4", - "DSP_WW4A2_0", - "DSP_WW4A2_1", - "DSP_WW4A2_2", - "DSP_WW4A2_3", - "DSP_WW4A2_4", - "DSP_WW4A3_0", - "DSP_WW4A3_1", - "DSP_WW4A3_2", - "DSP_WW4A3_3", - "DSP_WW4A3_4", - "DSP_WW4B0_0", - "DSP_WW4B0_1", - "DSP_WW4B0_2", - "DSP_WW4B0_3", - "DSP_WW4B0_4", - "DSP_WW4B1_0", - "DSP_WW4B1_1", - "DSP_WW4B1_2", - "DSP_WW4B1_3", - "DSP_WW4B1_4", - "DSP_WW4B2_0", - "DSP_WW4B2_1", - "DSP_WW4B2_2", - "DSP_WW4B2_3", - "DSP_WW4B2_4", - "DSP_WW4B3_0", - "DSP_WW4B3_1", - "DSP_WW4B3_2", - "DSP_WW4B3_3", - "DSP_WW4B3_4", - "DSP_WW4C0_0", - "DSP_WW4C0_1", - "DSP_WW4C0_2", - "DSP_WW4C0_3", - "DSP_WW4C0_4", - "DSP_WW4C1_0", - "DSP_WW4C1_1", - "DSP_WW4C1_2", - "DSP_WW4C1_3", - "DSP_WW4C1_4", - "DSP_WW4C2_0", - "DSP_WW4C2_1", - "DSP_WW4C2_2", - "DSP_WW4C2_3", - "DSP_WW4C2_4", - "DSP_WW4C3_0", - "DSP_WW4C3_1", - "DSP_WW4C3_2", - "DSP_WW4C3_3", - "DSP_WW4C3_4", - "DSP_WW4END0_0", - "DSP_WW4END0_1", - "DSP_WW4END0_2", - "DSP_WW4END0_3", - "DSP_WW4END0_4", - "DSP_WW4END1_0", - "DSP_WW4END1_1", - "DSP_WW4END1_2", - "DSP_WW4END1_3", - "DSP_WW4END1_4", - "DSP_WW4END2_0", - "DSP_WW4END2_1", - "DSP_WW4END2_2", - "DSP_WW4END2_3", - "DSP_WW4END2_4", - "DSP_WW4END3_0", - "DSP_WW4END3_1", - "DSP_WW4END3_2", - "DSP_WW4END3_3", - "DSP_WW4END3_4" - ] + "wires": { + "DSP_0_A0": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A1": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A10": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A11": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A12": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A13": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A14": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A15": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A16": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A17": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A18": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A19": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A2": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A20": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A21": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A22": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A23": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A24": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A25": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A26": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A27": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A28": { + "cap": "53.036", + "res": "0.000" + }, + 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"DSP_WW2A3_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2A3_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2A3_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2A3_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2A3_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END0_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END0_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END0_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END0_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END0_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END1_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END1_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END1_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END1_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END1_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END2_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END2_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END2_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END2_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END2_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END3_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END3_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END3_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END3_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW2END3_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A0_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A0_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A0_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A0_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A0_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A1_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A1_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A1_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A1_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A1_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A2_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A2_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A2_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A2_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A2_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A3_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A3_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A3_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A3_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4A3_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B0_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B0_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B0_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B0_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B0_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B1_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B1_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B1_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B1_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B1_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B2_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B2_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B2_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B2_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B2_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B3_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B3_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B3_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B3_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4B3_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C0_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C0_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C0_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C0_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C0_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C1_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C1_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C1_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C1_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C1_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C2_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C2_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C2_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C2_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C2_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C3_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C3_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C3_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C3_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4C3_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END0_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END0_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END0_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END0_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END0_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END1_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END1_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END1_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END1_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END1_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END2_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END2_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END2_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END2_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END2_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_4": { + "cap": "12.700", + "res": "47.430" + } + } } diff --git a/kintex7/tile_type_DSP_R.json b/kintex7/tile_type_DSP_R.json index e0e7135..4b82be5 100644 --- a/kintex7/tile_type_DSP_R.json +++ b/kintex7/tile_type_DSP_R.json @@ -2,5560 +2,14294 @@ "pips": { "DSP_R.DSP_0_ACOUT0->DSP_1_ACIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT0" }, "DSP_R.DSP_0_ACOUT1->DSP_1_ACIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT1" }, "DSP_R.DSP_0_ACOUT10->DSP_1_ACIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT10" }, "DSP_R.DSP_0_ACOUT11->DSP_1_ACIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT11" }, "DSP_R.DSP_0_ACOUT12->DSP_1_ACIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT12" }, "DSP_R.DSP_0_ACOUT13->DSP_1_ACIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT13" }, "DSP_R.DSP_0_ACOUT14->DSP_1_ACIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT14" }, "DSP_R.DSP_0_ACOUT15->DSP_1_ACIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT15" }, "DSP_R.DSP_0_ACOUT16->DSP_1_ACIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT16" }, "DSP_R.DSP_0_ACOUT17->DSP_1_ACIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT17" }, "DSP_R.DSP_0_ACOUT18->DSP_1_ACIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT18" }, "DSP_R.DSP_0_ACOUT19->DSP_1_ACIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT19" }, "DSP_R.DSP_0_ACOUT2->DSP_1_ACIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT2" }, "DSP_R.DSP_0_ACOUT20->DSP_1_ACIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT20" }, "DSP_R.DSP_0_ACOUT21->DSP_1_ACIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT21" }, "DSP_R.DSP_0_ACOUT22->DSP_1_ACIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT22" }, "DSP_R.DSP_0_ACOUT23->DSP_1_ACIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT23" }, "DSP_R.DSP_0_ACOUT24->DSP_1_ACIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT24" }, "DSP_R.DSP_0_ACOUT25->DSP_1_ACIN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT25" }, "DSP_R.DSP_0_ACOUT26->DSP_1_ACIN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT26" }, "DSP_R.DSP_0_ACOUT27->DSP_1_ACIN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT27" }, "DSP_R.DSP_0_ACOUT28->DSP_1_ACIN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT28" }, "DSP_R.DSP_0_ACOUT29->DSP_1_ACIN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT29" }, "DSP_R.DSP_0_ACOUT3->DSP_1_ACIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT3" }, "DSP_R.DSP_0_ACOUT4->DSP_1_ACIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT4" }, "DSP_R.DSP_0_ACOUT5->DSP_1_ACIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT5" }, "DSP_R.DSP_0_ACOUT6->DSP_1_ACIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT6" }, "DSP_R.DSP_0_ACOUT7->DSP_1_ACIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT7" }, "DSP_R.DSP_0_ACOUT8->DSP_1_ACIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT8" }, "DSP_R.DSP_0_ACOUT9->DSP_1_ACIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ACIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_ACOUT9" }, "DSP_R.DSP_0_BCOUT0->DSP_1_BCIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT0" }, "DSP_R.DSP_0_BCOUT1->DSP_1_BCIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT1" }, "DSP_R.DSP_0_BCOUT10->DSP_1_BCIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT10" }, "DSP_R.DSP_0_BCOUT11->DSP_1_BCIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT11" }, "DSP_R.DSP_0_BCOUT12->DSP_1_BCIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT12" }, "DSP_R.DSP_0_BCOUT13->DSP_1_BCIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT13" }, "DSP_R.DSP_0_BCOUT14->DSP_1_BCIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT14" }, "DSP_R.DSP_0_BCOUT15->DSP_1_BCIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT15" }, "DSP_R.DSP_0_BCOUT16->DSP_1_BCIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT16" }, "DSP_R.DSP_0_BCOUT17->DSP_1_BCIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT17" }, "DSP_R.DSP_0_BCOUT2->DSP_1_BCIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT2" }, "DSP_R.DSP_0_BCOUT3->DSP_1_BCIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT3" }, "DSP_R.DSP_0_BCOUT4->DSP_1_BCIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT4" }, "DSP_R.DSP_0_BCOUT5->DSP_1_BCIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT5" }, "DSP_R.DSP_0_BCOUT6->DSP_1_BCIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT6" }, "DSP_R.DSP_0_BCOUT7->DSP_1_BCIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT7" }, "DSP_R.DSP_0_BCOUT8->DSP_1_BCIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT8" }, "DSP_R.DSP_0_BCOUT9->DSP_1_BCIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_BCIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_BCOUT9" }, "DSP_R.DSP_0_CARRYCASCOUT->DSP_1_CARRYCASCIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYCASCIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYCASCOUT" }, "DSP_R.DSP_0_CARRYOUT0->DSP_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT0" }, "DSP_R.DSP_0_CARRYOUT1->DSP_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT1" }, "DSP_R.DSP_0_CARRYOUT2->DSP_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT2" }, "DSP_R.DSP_0_CARRYOUT3->DSP_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_CARRYOUT3" }, "DSP_R.DSP_0_MULTSIGNOUT->DSP_1_MULTSIGNIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_MULTSIGNIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_MULTSIGNOUT" }, "DSP_R.DSP_0_OVERFLOW->DSP_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_OVERFLOW" }, "DSP_R.DSP_0_P0->DSP_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P0" }, "DSP_R.DSP_0_P1->DSP_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P1" }, "DSP_R.DSP_0_P10->DSP_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P10" }, "DSP_R.DSP_0_P11->DSP_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P11" }, "DSP_R.DSP_0_P12->DSP_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P12" }, "DSP_R.DSP_0_P13->DSP_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P13" }, "DSP_R.DSP_0_P14->DSP_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P14" }, "DSP_R.DSP_0_P15->DSP_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P15" }, "DSP_R.DSP_0_P16->DSP_LOGIC_OUTS_B21_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P16" }, "DSP_R.DSP_0_P17->DSP_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P17" }, "DSP_R.DSP_0_P18->DSP_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P18" }, "DSP_R.DSP_0_P19->DSP_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P19" }, "DSP_R.DSP_0_P2->DSP_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P2" }, "DSP_R.DSP_0_P20->DSP_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P20" }, "DSP_R.DSP_0_P21->DSP_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P21" }, "DSP_R.DSP_0_P22->DSP_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P22" }, "DSP_R.DSP_0_P23->DSP_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P23" }, "DSP_R.DSP_0_P24->DSP_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P24" }, "DSP_R.DSP_0_P25->DSP_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P25" }, "DSP_R.DSP_0_P26->DSP_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P26" }, "DSP_R.DSP_0_P27->DSP_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P27" }, "DSP_R.DSP_0_P28->DSP_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P28" }, "DSP_R.DSP_0_P29->DSP_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P29" }, "DSP_R.DSP_0_P3->DSP_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P3" }, "DSP_R.DSP_0_P30->DSP_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P30" }, "DSP_R.DSP_0_P31->DSP_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P31" }, "DSP_R.DSP_0_P32->DSP_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P32" }, "DSP_R.DSP_0_P33->DSP_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P33" }, "DSP_R.DSP_0_P34->DSP_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P34" }, "DSP_R.DSP_0_P35->DSP_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P35" }, "DSP_R.DSP_0_P36->DSP_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P36" }, "DSP_R.DSP_0_P37->DSP_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P37" }, "DSP_R.DSP_0_P38->DSP_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P38" }, "DSP_R.DSP_0_P39->DSP_LOGIC_OUTS_B19_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B19_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P39" }, "DSP_R.DSP_0_P4->DSP_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P4" }, "DSP_R.DSP_0_P40->DSP_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P40" }, "DSP_R.DSP_0_P41->DSP_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P41" }, "DSP_R.DSP_0_P42->DSP_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P42" }, "DSP_R.DSP_0_P43->DSP_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P43" }, "DSP_R.DSP_0_P44->DSP_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P44" }, "DSP_R.DSP_0_P45->DSP_LOGIC_OUTS_B10_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P45" }, "DSP_R.DSP_0_P46->DSP_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P46" }, "DSP_R.DSP_0_P47->DSP_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P47" }, "DSP_R.DSP_0_P5->DSP_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P5" }, "DSP_R.DSP_0_P6->DSP_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P6" }, "DSP_R.DSP_0_P7->DSP_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P7" }, "DSP_R.DSP_0_P8->DSP_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P8" }, "DSP_R.DSP_0_P9->DSP_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_P9" }, "DSP_R.DSP_0_PATTERNBDETECT->DSP_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PATTERNBDETECT" }, "DSP_R.DSP_0_PATTERNDETECT->DSP_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PATTERNDETECT" }, "DSP_R.DSP_0_PCOUT0->DSP_1_PCIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT0" }, "DSP_R.DSP_0_PCOUT1->DSP_1_PCIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT1" }, "DSP_R.DSP_0_PCOUT10->DSP_1_PCIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT10" }, "DSP_R.DSP_0_PCOUT11->DSP_1_PCIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT11" }, "DSP_R.DSP_0_PCOUT12->DSP_1_PCIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT12" }, "DSP_R.DSP_0_PCOUT13->DSP_1_PCIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT13" }, "DSP_R.DSP_0_PCOUT14->DSP_1_PCIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT14" }, "DSP_R.DSP_0_PCOUT15->DSP_1_PCIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT15" }, "DSP_R.DSP_0_PCOUT16->DSP_1_PCIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT16" }, "DSP_R.DSP_0_PCOUT17->DSP_1_PCIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT17" }, "DSP_R.DSP_0_PCOUT18->DSP_1_PCIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT18" }, "DSP_R.DSP_0_PCOUT19->DSP_1_PCIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT19" }, "DSP_R.DSP_0_PCOUT2->DSP_1_PCIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT2" }, "DSP_R.DSP_0_PCOUT20->DSP_1_PCIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT20" }, "DSP_R.DSP_0_PCOUT21->DSP_1_PCIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT21" }, "DSP_R.DSP_0_PCOUT22->DSP_1_PCIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT22" }, "DSP_R.DSP_0_PCOUT23->DSP_1_PCIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT23" }, "DSP_R.DSP_0_PCOUT24->DSP_1_PCIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT24" }, "DSP_R.DSP_0_PCOUT25->DSP_1_PCIN25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT25" }, "DSP_R.DSP_0_PCOUT26->DSP_1_PCIN26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT26" }, "DSP_R.DSP_0_PCOUT27->DSP_1_PCIN27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT27" }, "DSP_R.DSP_0_PCOUT28->DSP_1_PCIN28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT28" }, "DSP_R.DSP_0_PCOUT29->DSP_1_PCIN29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT29" }, "DSP_R.DSP_0_PCOUT3->DSP_1_PCIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT3" }, "DSP_R.DSP_0_PCOUT30->DSP_1_PCIN30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT30" }, "DSP_R.DSP_0_PCOUT31->DSP_1_PCIN31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT31" }, "DSP_R.DSP_0_PCOUT32->DSP_1_PCIN32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT32" }, "DSP_R.DSP_0_PCOUT33->DSP_1_PCIN33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT33" }, "DSP_R.DSP_0_PCOUT34->DSP_1_PCIN34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT34" }, "DSP_R.DSP_0_PCOUT35->DSP_1_PCIN35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT35" }, "DSP_R.DSP_0_PCOUT36->DSP_1_PCIN36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT36" }, "DSP_R.DSP_0_PCOUT37->DSP_1_PCIN37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT37" }, "DSP_R.DSP_0_PCOUT38->DSP_1_PCIN38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT38" }, "DSP_R.DSP_0_PCOUT39->DSP_1_PCIN39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT39" }, "DSP_R.DSP_0_PCOUT4->DSP_1_PCIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT4" }, "DSP_R.DSP_0_PCOUT40->DSP_1_PCIN40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT40" }, "DSP_R.DSP_0_PCOUT41->DSP_1_PCIN41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT41" }, "DSP_R.DSP_0_PCOUT42->DSP_1_PCIN42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT42" }, "DSP_R.DSP_0_PCOUT43->DSP_1_PCIN43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT43" }, "DSP_R.DSP_0_PCOUT44->DSP_1_PCIN44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT44" }, "DSP_R.DSP_0_PCOUT45->DSP_1_PCIN45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT45" }, "DSP_R.DSP_0_PCOUT46->DSP_1_PCIN46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT46" }, "DSP_R.DSP_0_PCOUT47->DSP_1_PCIN47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT47" }, "DSP_R.DSP_0_PCOUT5->DSP_1_PCIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT5" }, "DSP_R.DSP_0_PCOUT6->DSP_1_PCIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT6" }, "DSP_R.DSP_0_PCOUT7->DSP_1_PCIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT7" }, "DSP_R.DSP_0_PCOUT8->DSP_1_PCIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT8" }, "DSP_R.DSP_0_PCOUT9->DSP_1_PCIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_PCIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_PCOUT9" }, "DSP_R.DSP_0_UNDERFLOW->DSP_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_0_UNDERFLOW" }, "DSP_R.DSP_1_ACOUT0->DSP_ACOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT0" }, "DSP_R.DSP_1_ACOUT1->DSP_ACOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT1" }, "DSP_R.DSP_1_ACOUT10->DSP_ACOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT10" }, "DSP_R.DSP_1_ACOUT11->DSP_ACOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT11" }, "DSP_R.DSP_1_ACOUT12->DSP_ACOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT12" }, "DSP_R.DSP_1_ACOUT13->DSP_ACOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT13" }, "DSP_R.DSP_1_ACOUT14->DSP_ACOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT14" }, "DSP_R.DSP_1_ACOUT15->DSP_ACOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT15" }, "DSP_R.DSP_1_ACOUT16->DSP_ACOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT16" }, "DSP_R.DSP_1_ACOUT17->DSP_ACOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT17" }, "DSP_R.DSP_1_ACOUT18->DSP_ACOUT18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT18" }, "DSP_R.DSP_1_ACOUT19->DSP_ACOUT19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT19" }, "DSP_R.DSP_1_ACOUT2->DSP_ACOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT2" }, "DSP_R.DSP_1_ACOUT20->DSP_ACOUT20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT20" }, "DSP_R.DSP_1_ACOUT21->DSP_ACOUT21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT21" }, "DSP_R.DSP_1_ACOUT22->DSP_ACOUT22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT22" }, "DSP_R.DSP_1_ACOUT23->DSP_ACOUT23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT23" }, "DSP_R.DSP_1_ACOUT24->DSP_ACOUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT24" }, "DSP_R.DSP_1_ACOUT25->DSP_ACOUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT25" }, "DSP_R.DSP_1_ACOUT26->DSP_ACOUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT26" }, "DSP_R.DSP_1_ACOUT27->DSP_ACOUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT27" }, "DSP_R.DSP_1_ACOUT28->DSP_ACOUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT28" }, "DSP_R.DSP_1_ACOUT29->DSP_ACOUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT29" }, "DSP_R.DSP_1_ACOUT3->DSP_ACOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT3" }, "DSP_R.DSP_1_ACOUT4->DSP_ACOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT4" }, "DSP_R.DSP_1_ACOUT5->DSP_ACOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT5" }, "DSP_R.DSP_1_ACOUT6->DSP_ACOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT6" }, "DSP_R.DSP_1_ACOUT7->DSP_ACOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT7" }, "DSP_R.DSP_1_ACOUT8->DSP_ACOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT8" }, "DSP_R.DSP_1_ACOUT9->DSP_ACOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_ACOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_ACOUT9" }, "DSP_R.DSP_1_BCOUT0->DSP_BCOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT0" }, "DSP_R.DSP_1_BCOUT1->DSP_BCOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT1" }, "DSP_R.DSP_1_BCOUT10->DSP_BCOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT10" }, "DSP_R.DSP_1_BCOUT11->DSP_BCOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT11" }, "DSP_R.DSP_1_BCOUT12->DSP_BCOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT12" }, "DSP_R.DSP_1_BCOUT13->DSP_BCOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT13" }, "DSP_R.DSP_1_BCOUT14->DSP_BCOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT14" }, "DSP_R.DSP_1_BCOUT15->DSP_BCOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT15" }, "DSP_R.DSP_1_BCOUT16->DSP_BCOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT16" }, "DSP_R.DSP_1_BCOUT17->DSP_BCOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT17" }, "DSP_R.DSP_1_BCOUT2->DSP_BCOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT2" }, "DSP_R.DSP_1_BCOUT3->DSP_BCOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT3" }, "DSP_R.DSP_1_BCOUT4->DSP_BCOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT4" }, "DSP_R.DSP_1_BCOUT5->DSP_BCOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT5" }, "DSP_R.DSP_1_BCOUT6->DSP_BCOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT6" }, "DSP_R.DSP_1_BCOUT7->DSP_BCOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT7" }, "DSP_R.DSP_1_BCOUT8->DSP_BCOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT8" }, "DSP_R.DSP_1_BCOUT9->DSP_BCOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_BCOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_BCOUT9" }, "DSP_R.DSP_1_CARRYCASCOUT->DSP_CARRYCASCOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_CARRYCASCOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYCASCOUT" }, "DSP_R.DSP_1_CARRYOUT0->DSP_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT0" }, "DSP_R.DSP_1_CARRYOUT1->DSP_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT1" }, "DSP_R.DSP_1_CARRYOUT2->DSP_LOGIC_OUTS_B10_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT2" }, "DSP_R.DSP_1_CARRYOUT3->DSP_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_CARRYOUT3" }, "DSP_R.DSP_1_MULTSIGNOUT->DSP_MULTSIGNOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_MULTSIGNOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_MULTSIGNOUT" }, "DSP_R.DSP_1_OVERFLOW->DSP_LOGIC_OUTS_B8_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B8_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_OVERFLOW" }, "DSP_R.DSP_1_P0->DSP_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P0" }, "DSP_R.DSP_1_P1->DSP_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P1" }, "DSP_R.DSP_1_P10->DSP_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P10" }, "DSP_R.DSP_1_P11->DSP_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P11" }, "DSP_R.DSP_1_P12->DSP_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P12" }, "DSP_R.DSP_1_P13->DSP_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P13" }, "DSP_R.DSP_1_P14->DSP_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P14" }, "DSP_R.DSP_1_P15->DSP_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P15" }, "DSP_R.DSP_1_P16->DSP_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P16" }, "DSP_R.DSP_1_P17->DSP_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P17" }, "DSP_R.DSP_1_P18->DSP_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P18" }, "DSP_R.DSP_1_P19->DSP_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P19" }, "DSP_R.DSP_1_P2->DSP_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P2" }, "DSP_R.DSP_1_P20->DSP_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P20" }, "DSP_R.DSP_1_P21->DSP_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P21" }, "DSP_R.DSP_1_P22->DSP_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P22" }, "DSP_R.DSP_1_P23->DSP_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P23" }, "DSP_R.DSP_1_P24->DSP_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P24" }, "DSP_R.DSP_1_P25->DSP_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P25" }, "DSP_R.DSP_1_P26->DSP_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P26" }, "DSP_R.DSP_1_P27->DSP_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P27" }, "DSP_R.DSP_1_P28->DSP_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P28" }, "DSP_R.DSP_1_P29->DSP_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P29" }, "DSP_R.DSP_1_P3->DSP_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P3" }, "DSP_R.DSP_1_P30->DSP_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P30" }, "DSP_R.DSP_1_P31->DSP_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P31" }, "DSP_R.DSP_1_P32->DSP_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P32" }, "DSP_R.DSP_1_P33->DSP_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P33" }, "DSP_R.DSP_1_P34->DSP_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P34" }, "DSP_R.DSP_1_P35->DSP_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P35" }, "DSP_R.DSP_1_P36->DSP_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P36" }, "DSP_R.DSP_1_P37->DSP_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P37" }, "DSP_R.DSP_1_P38->DSP_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P38" }, "DSP_R.DSP_1_P39->DSP_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P39" }, "DSP_R.DSP_1_P4->DSP_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P4" }, "DSP_R.DSP_1_P40->DSP_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P40" }, "DSP_R.DSP_1_P41->DSP_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P41" }, "DSP_R.DSP_1_P42->DSP_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P42" }, "DSP_R.DSP_1_P43->DSP_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P43" }, "DSP_R.DSP_1_P44->DSP_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P44" }, "DSP_R.DSP_1_P45->DSP_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P45" }, "DSP_R.DSP_1_P46->DSP_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P46" }, "DSP_R.DSP_1_P47->DSP_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P47" }, "DSP_R.DSP_1_P5->DSP_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P5" }, "DSP_R.DSP_1_P6->DSP_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P6" }, "DSP_R.DSP_1_P7->DSP_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P7" }, "DSP_R.DSP_1_P8->DSP_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P8" }, "DSP_R.DSP_1_P9->DSP_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_P9" }, "DSP_R.DSP_1_PATTERNBDETECT->DSP_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PATTERNBDETECT" }, "DSP_R.DSP_1_PATTERNDETECT->DSP_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PATTERNDETECT" }, "DSP_R.DSP_1_PCOUT0->DSP_PCOUT0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT0" }, "DSP_R.DSP_1_PCOUT1->DSP_PCOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT1" }, "DSP_R.DSP_1_PCOUT10->DSP_PCOUT10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT10" }, "DSP_R.DSP_1_PCOUT11->DSP_PCOUT11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT11" }, "DSP_R.DSP_1_PCOUT12->DSP_PCOUT12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT12" }, "DSP_R.DSP_1_PCOUT13->DSP_PCOUT13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT13" }, "DSP_R.DSP_1_PCOUT14->DSP_PCOUT14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT14" }, "DSP_R.DSP_1_PCOUT15->DSP_PCOUT15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT15" }, "DSP_R.DSP_1_PCOUT16->DSP_PCOUT16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT16" }, "DSP_R.DSP_1_PCOUT17->DSP_PCOUT17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT17" }, "DSP_R.DSP_1_PCOUT18->DSP_PCOUT18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT18" }, "DSP_R.DSP_1_PCOUT19->DSP_PCOUT19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT19" }, "DSP_R.DSP_1_PCOUT2->DSP_PCOUT2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT2" }, "DSP_R.DSP_1_PCOUT20->DSP_PCOUT20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT20" }, "DSP_R.DSP_1_PCOUT21->DSP_PCOUT21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT21" }, "DSP_R.DSP_1_PCOUT22->DSP_PCOUT22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT22" }, "DSP_R.DSP_1_PCOUT23->DSP_PCOUT23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT23" }, "DSP_R.DSP_1_PCOUT24->DSP_PCOUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT24" }, "DSP_R.DSP_1_PCOUT25->DSP_PCOUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT25" }, "DSP_R.DSP_1_PCOUT26->DSP_PCOUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT26" }, "DSP_R.DSP_1_PCOUT27->DSP_PCOUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT27" }, "DSP_R.DSP_1_PCOUT28->DSP_PCOUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT28" }, "DSP_R.DSP_1_PCOUT29->DSP_PCOUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT29" }, "DSP_R.DSP_1_PCOUT3->DSP_PCOUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT3" }, "DSP_R.DSP_1_PCOUT30->DSP_PCOUT30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT30" }, "DSP_R.DSP_1_PCOUT31->DSP_PCOUT31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT31" }, "DSP_R.DSP_1_PCOUT32->DSP_PCOUT32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT32" }, "DSP_R.DSP_1_PCOUT33->DSP_PCOUT33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT33" }, "DSP_R.DSP_1_PCOUT34->DSP_PCOUT34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT34" }, "DSP_R.DSP_1_PCOUT35->DSP_PCOUT35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT35" }, "DSP_R.DSP_1_PCOUT36->DSP_PCOUT36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT36" }, "DSP_R.DSP_1_PCOUT37->DSP_PCOUT37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT37" }, "DSP_R.DSP_1_PCOUT38->DSP_PCOUT38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT38" }, "DSP_R.DSP_1_PCOUT39->DSP_PCOUT39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT39" }, "DSP_R.DSP_1_PCOUT4->DSP_PCOUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT4" }, "DSP_R.DSP_1_PCOUT40->DSP_PCOUT40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT40" }, "DSP_R.DSP_1_PCOUT41->DSP_PCOUT41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT41" }, "DSP_R.DSP_1_PCOUT42->DSP_PCOUT42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT42" }, "DSP_R.DSP_1_PCOUT43->DSP_PCOUT43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT43" }, "DSP_R.DSP_1_PCOUT44->DSP_PCOUT44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT44" }, "DSP_R.DSP_1_PCOUT45->DSP_PCOUT45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT45" }, "DSP_R.DSP_1_PCOUT46->DSP_PCOUT46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT46" }, "DSP_R.DSP_1_PCOUT47->DSP_PCOUT47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT47" }, "DSP_R.DSP_1_PCOUT5->DSP_PCOUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT5" }, "DSP_R.DSP_1_PCOUT6->DSP_PCOUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT6" }, "DSP_R.DSP_1_PCOUT7->DSP_PCOUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT7" }, "DSP_R.DSP_1_PCOUT8->DSP_PCOUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT8" }, "DSP_R.DSP_1_PCOUT9->DSP_PCOUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_PCOUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_PCOUT9" }, "DSP_R.DSP_1_UNDERFLOW->DSP_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_1_UNDERFLOW" }, "DSP_R.DSP_BYP0_0->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_0" }, "DSP_R.DSP_BYP0_1->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_1" }, "DSP_R.DSP_BYP0_2->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_2" }, "DSP_R.DSP_BYP0_3->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_3" }, "DSP_R.DSP_BYP0_4->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP0_4" }, "DSP_R.DSP_BYP1_0->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_0" }, "DSP_R.DSP_BYP1_1->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_1" }, "DSP_R.DSP_BYP1_2->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_2" }, "DSP_R.DSP_BYP1_3->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_3" }, "DSP_R.DSP_BYP1_4->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP1_4" }, "DSP_R.DSP_BYP2_0->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_0" }, "DSP_R.DSP_BYP2_1->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_1" }, "DSP_R.DSP_BYP2_2->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_2" }, "DSP_R.DSP_BYP2_3->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_3" }, "DSP_R.DSP_BYP2_4->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP2_4" }, "DSP_R.DSP_BYP3_0->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_0" }, "DSP_R.DSP_BYP3_1->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_1" }, "DSP_R.DSP_BYP3_2->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_2" }, "DSP_R.DSP_BYP3_3->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_3" }, "DSP_R.DSP_BYP3_4->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP3_4" }, "DSP_R.DSP_BYP4_0->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_0" }, "DSP_R.DSP_BYP4_1->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_1" }, "DSP_R.DSP_BYP4_2->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_2" }, "DSP_R.DSP_BYP4_3->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_3" }, "DSP_R.DSP_BYP4_4->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP4_4" }, "DSP_R.DSP_BYP5_0->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_0" }, "DSP_R.DSP_BYP5_1->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_1" }, "DSP_R.DSP_BYP5_2->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_2" }, "DSP_R.DSP_BYP5_3->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_3" }, "DSP_R.DSP_BYP5_4->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP5_4" }, "DSP_R.DSP_BYP6_0->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_0" }, "DSP_R.DSP_BYP6_1->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_1" }, "DSP_R.DSP_BYP6_2->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_2" }, "DSP_R.DSP_BYP6_3->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_3" }, "DSP_R.DSP_BYP6_4->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP6_4" }, "DSP_R.DSP_BYP7_0->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_0" }, "DSP_R.DSP_BYP7_1->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_1" }, "DSP_R.DSP_BYP7_2->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_2" }, "DSP_R.DSP_BYP7_3->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_3" }, "DSP_R.DSP_BYP7_4->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_BYP7_4" }, "DSP_R.DSP_CLK0_1->DSP_0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CLK0_1" }, "DSP_R.DSP_CLK0_3->DSP_1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CLK0_3" }, "DSP_R.DSP_CTRL0_0->DSP_0_RSTP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_0" }, "DSP_R.DSP_CTRL0_1->DSP_0_RSTC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_1" }, "DSP_R.DSP_CTRL0_2->DSP_0_RSTB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_2" }, "DSP_R.DSP_CTRL0_3->DSP_1_RSTC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_3" }, "DSP_R.DSP_CTRL0_4->DSP_1_RSTP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL0_4" }, "DSP_R.DSP_CTRL1_0->DSP_0_RSTA": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTA", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_0" }, "DSP_R.DSP_CTRL1_1->DSP_0_RSTM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_1" }, "DSP_R.DSP_CTRL1_2->DSP_1_RSTA": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTA", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_2" }, "DSP_R.DSP_CTRL1_3->DSP_1_RSTM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_3" }, "DSP_R.DSP_CTRL1_4->DSP_1_RSTB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_CTRL1_4" }, "DSP_R.DSP_FAN0_0->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_0" }, "DSP_R.DSP_FAN0_1->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_1" }, "DSP_R.DSP_FAN0_2->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_2" }, "DSP_R.DSP_FAN0_3->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_3" }, "DSP_R.DSP_FAN0_4->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN0_4" }, "DSP_R.DSP_FAN1_0->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_0" }, "DSP_R.DSP_FAN1_1->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_1" }, "DSP_R.DSP_FAN1_2->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_2" }, "DSP_R.DSP_FAN1_3->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN1_3" }, "DSP_R.DSP_FAN2_0->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_0" }, "DSP_R.DSP_FAN2_2->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_2" }, "DSP_R.DSP_FAN2_3->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_3" }, "DSP_R.DSP_FAN2_4->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN2_4" }, "DSP_R.DSP_FAN3_0->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_0" }, "DSP_R.DSP_FAN3_1->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_1" }, "DSP_R.DSP_FAN3_2->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_2" }, "DSP_R.DSP_FAN3_3->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_3" }, "DSP_R.DSP_FAN3_4->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN3_4" }, "DSP_R.DSP_FAN4_0->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_0" }, "DSP_R.DSP_FAN4_1->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_1" }, "DSP_R.DSP_FAN4_2->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_2" }, "DSP_R.DSP_FAN4_3->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_3" }, "DSP_R.DSP_FAN4_4->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN4_4" }, "DSP_R.DSP_FAN5_0->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_0" }, "DSP_R.DSP_FAN5_1->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_1" }, "DSP_R.DSP_FAN5_2->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_2" }, "DSP_R.DSP_FAN5_3->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_3" }, "DSP_R.DSP_FAN5_4->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN5_4" }, "DSP_R.DSP_FAN6_0->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_0" }, "DSP_R.DSP_FAN6_1->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_1" }, "DSP_R.DSP_FAN6_2->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_2" }, "DSP_R.DSP_FAN6_3->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_3" }, "DSP_R.DSP_FAN6_4->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN6_4" }, "DSP_R.DSP_FAN7_0->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_0" }, "DSP_R.DSP_FAN7_1->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_1" }, "DSP_R.DSP_FAN7_2->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_2" }, "DSP_R.DSP_FAN7_3->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_3" }, "DSP_R.DSP_FAN7_4->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_FAN7_4" }, "DSP_R.DSP_GND_R->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_GND_R->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_GND_R" }, "DSP_R.DSP_IMUX0_0->DSP_1_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_0" }, "DSP_R.DSP_IMUX0_1->DSP_0_CEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_1" }, "DSP_R.DSP_IMUX0_2->DSP_0_CECARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CECARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_2" }, "DSP_R.DSP_IMUX0_3->DSP_1_B15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_3" }, "DSP_R.DSP_IMUX0_4->DSP_1_ALUMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX0_4" }, "DSP_R.DSP_IMUX10_0->DSP_1_C21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_0" }, "DSP_R.DSP_IMUX10_1->DSP_1_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_1" }, "DSP_R.DSP_IMUX10_2->DSP_1_C29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_2" }, "DSP_R.DSP_IMUX10_3->DSP_1_C33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_3" }, "DSP_R.DSP_IMUX10_4->DSP_1_C39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX10_4" }, "DSP_R.DSP_IMUX11_0->DSP_1_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_0" }, "DSP_R.DSP_IMUX11_1->DSP_1_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_1" }, "DSP_R.DSP_IMUX11_2->DSP_1_A9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_2" }, "DSP_R.DSP_IMUX11_3->DSP_1_CECTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CECTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_3" }, "DSP_R.DSP_IMUX11_4->DSP_1_C46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX11_4" }, "DSP_R.DSP_IMUX12_0->DSP_1_C22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_0" }, "DSP_R.DSP_IMUX12_1->DSP_1_C26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_1" }, "DSP_R.DSP_IMUX12_2->DSP_0_OPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_2" }, "DSP_R.DSP_IMUX12_3->DSP_1_C34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_3" }, "DSP_R.DSP_IMUX12_4->DSP_1_C38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX12_4" }, "DSP_R.DSP_IMUX13_0->DSP_1_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_0" }, "DSP_R.DSP_IMUX13_1->DSP_1_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_1" }, "DSP_R.DSP_IMUX13_2->DSP_1_A10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_2" }, "DSP_R.DSP_IMUX13_3->DSP_0_ALUMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_3" }, "DSP_R.DSP_IMUX13_4->DSP_1_C18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX13_4" }, "DSP_R.DSP_IMUX14_0->DSP_1_B0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_0" }, "DSP_R.DSP_IMUX14_1->DSP_1_C24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_1" }, "DSP_R.DSP_IMUX14_2->DSP_1_B8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_2" }, "DSP_R.DSP_IMUX14_3->DSP_0_CARRYINSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_3" }, "DSP_R.DSP_IMUX14_4->DSP_1_RSTCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX14_4" }, "DSP_R.DSP_IMUX15_0->DSP_1_A0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_0" }, "DSP_R.DSP_IMUX15_1->DSP_1_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_1" }, "DSP_R.DSP_IMUX15_2->DSP_1_A8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_2" }, "DSP_R.DSP_IMUX15_3->DSP_1_CARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_3" }, "DSP_R.DSP_IMUX15_4->DSP_1_RSTALLCARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTALLCARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX15_4" }, "DSP_R.DSP_IMUX16_0->DSP_0_C41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_0" }, "DSP_R.DSP_IMUX16_1->DSP_0_B7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_1" }, "DSP_R.DSP_IMUX16_2->DSP_0_B11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_2" }, "DSP_R.DSP_IMUX16_3->DSP_1_CEB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_3" }, "DSP_R.DSP_IMUX16_4->DSP_1_OPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX16_4" }, "DSP_R.DSP_IMUX17_0->DSP_0_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_0" }, "DSP_R.DSP_IMUX17_1->DSP_0_A7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_1" }, "DSP_R.DSP_IMUX17_2->DSP_0_A11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_2" }, "DSP_R.DSP_IMUX17_3->DSP_1_CEA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_3" }, "DSP_R.DSP_IMUX17_4->DSP_1_OPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX17_4" }, "DSP_R.DSP_IMUX18_0->DSP_0_C21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_0" }, "DSP_R.DSP_IMUX18_1->DSP_0_B5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_1" }, "DSP_R.DSP_IMUX18_2->DSP_0_B9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_2" }, "DSP_R.DSP_IMUX18_3->DSP_0_C33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_3" }, "DSP_R.DSP_IMUX18_4->DSP_0_C39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX18_4" }, "DSP_R.DSP_IMUX19_0->DSP_0_A1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_0" }, "DSP_R.DSP_IMUX19_1->DSP_0_A5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_1" }, "DSP_R.DSP_IMUX19_2->DSP_0_A9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_2" }, "DSP_R.DSP_IMUX19_3->DSP_1_CEM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_3" }, "DSP_R.DSP_IMUX19_4->DSP_0_C46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX19_4" }, "DSP_R.DSP_IMUX1_0->DSP_0_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_0" }, "DSP_R.DSP_IMUX1_1->DSP_0_CEB2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEB2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_1" }, "DSP_R.DSP_IMUX1_2->DSP_0_CEM": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEM", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_2" }, "DSP_R.DSP_IMUX1_3->DSP_1_B13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_3" }, "DSP_R.DSP_IMUX1_4->DSP_0_C19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX1_4" }, "DSP_R.DSP_IMUX20_0->DSP_0_C22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_0" }, "DSP_R.DSP_IMUX20_1->DSP_0_C26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_1" }, "DSP_R.DSP_IMUX20_2->DSP_0_OPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_2" }, "DSP_R.DSP_IMUX20_3->DSP_0_C34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_3" }, "DSP_R.DSP_IMUX20_4->DSP_0_C38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX20_4" }, "DSP_R.DSP_IMUX21_0->DSP_0_A2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_0" }, "DSP_R.DSP_IMUX21_1->DSP_0_A6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_1" }, "DSP_R.DSP_IMUX21_2->DSP_0_A10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_2" }, "DSP_R.DSP_IMUX21_3->DSP_0_ALUMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_3" }, "DSP_R.DSP_IMUX21_4->DSP_0_C18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX21_4" }, "DSP_R.DSP_IMUX22_0->DSP_0_B0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_0" }, "DSP_R.DSP_IMUX22_1->DSP_0_C24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_1" }, "DSP_R.DSP_IMUX22_2->DSP_0_B8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_2" }, "DSP_R.DSP_IMUX22_3->DSP_1_C32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_3" }, "DSP_R.DSP_IMUX22_4->DSP_1_RSTALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX22_4" }, "DSP_R.DSP_IMUX23_0->DSP_0_A0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_0" }, "DSP_R.DSP_IMUX23_1->DSP_0_A4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_1" }, "DSP_R.DSP_IMUX23_2->DSP_0_A8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_2" }, "DSP_R.DSP_IMUX23_3->DSP_0_CARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_3" }, "DSP_R.DSP_IMUX23_4->DSP_1_RSTINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX23_4" }, "DSP_R.DSP_IMUX24_0->DSP_1_C23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_0" }, "DSP_R.DSP_IMUX24_1->DSP_1_C27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_1" }, "DSP_R.DSP_IMUX24_2->DSP_1_C31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_2" }, "DSP_R.DSP_IMUX24_3->DSP_1_C35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_3" }, "DSP_R.DSP_IMUX24_4->DSP_1_C37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX24_4" }, "DSP_R.DSP_IMUX25_0->DSP_1_C43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_0" }, "DSP_R.DSP_IMUX25_1->DSP_1_C7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_1" }, "DSP_R.DSP_IMUX25_2->DSP_1_C11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_2" }, "DSP_R.DSP_IMUX25_3->DSP_1_C15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_3" }, "DSP_R.DSP_IMUX25_4->DSP_1_C47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX25_4" }, "DSP_R.DSP_IMUX26_0->DSP_1_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_0" }, "DSP_R.DSP_IMUX26_1->DSP_1_C25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_1" }, "DSP_R.DSP_IMUX26_2->DSP_1_CEP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_2" }, "DSP_R.DSP_IMUX26_3->DSP_1_CECARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CECARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_3" }, "DSP_R.DSP_IMUX26_4->DSP_1_C44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX26_4" }, "DSP_R.DSP_IMUX27_0->DSP_1_C40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_0" }, "DSP_R.DSP_IMUX27_1->DSP_1_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_1" }, "DSP_R.DSP_IMUX27_2->DSP_0_OPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_2" }, "DSP_R.DSP_IMUX27_3->DSP_1_C13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_3" }, "DSP_R.DSP_IMUX27_4->DSP_1_C17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX27_4" }, "DSP_R.DSP_IMUX28_0->DSP_1_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_0" }, "DSP_R.DSP_IMUX28_1->DSP_1_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_1" }, "DSP_R.DSP_IMUX28_2->DSP_1_C30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_2" }, "DSP_R.DSP_IMUX28_3->DSP_1_OPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_3" }, "DSP_R.DSP_IMUX28_4->DSP_1_CARRYINSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX28_4" }, "DSP_R.DSP_IMUX29_0->DSP_1_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_0" }, "DSP_R.DSP_IMUX29_1->DSP_1_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_1" }, "DSP_R.DSP_IMUX29_2->DSP_1_C10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_2" }, "DSP_R.DSP_IMUX29_3->DSP_1_C14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_3" }, "DSP_R.DSP_IMUX29_4->DSP_1_C45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX29_4" }, "DSP_R.DSP_IMUX2_0->DSP_1_C42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_0" }, "DSP_R.DSP_IMUX2_1->DSP_0_RSTALLCARRYIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTALLCARRYIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_1" }, "DSP_R.DSP_IMUX2_2->DSP_0_C29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_2" }, "DSP_R.DSP_IMUX2_3->DSP_0_B15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_3" }, "DSP_R.DSP_IMUX2_4->DSP_1_B17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX2_4" }, "DSP_R.DSP_IMUX30_0->DSP_1_C20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_0" }, "DSP_R.DSP_IMUX30_1->DSP_1_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_1" }, "DSP_R.DSP_IMUX30_2->DSP_0_OPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_2" }, "DSP_R.DSP_IMUX30_3->DSP_0_CARRYINSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_3" }, "DSP_R.DSP_IMUX30_4->DSP_1_C36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX30_4" }, "DSP_R.DSP_IMUX31_0->DSP_1_C0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_0" }, "DSP_R.DSP_IMUX31_1->DSP_1_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_1" }, "DSP_R.DSP_IMUX31_2->DSP_1_C8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_2" }, "DSP_R.DSP_IMUX31_3->DSP_1_C12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_3" }, "DSP_R.DSP_IMUX31_4->DSP_1_C16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX31_4" }, "DSP_R.DSP_IMUX32_0->DSP_0_C23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_0" }, "DSP_R.DSP_IMUX32_1->DSP_0_C27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_1" }, "DSP_R.DSP_IMUX32_2->DSP_0_C31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_2" }, "DSP_R.DSP_IMUX32_3->DSP_0_C35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_3" }, "DSP_R.DSP_IMUX32_4->DSP_0_C37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX32_4" }, "DSP_R.DSP_IMUX33_0->DSP_0_C43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_0" }, "DSP_R.DSP_IMUX33_1->DSP_0_C7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_1" }, "DSP_R.DSP_IMUX33_2->DSP_0_C11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_2" }, "DSP_R.DSP_IMUX33_3->DSP_0_C15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_3" }, "DSP_R.DSP_IMUX33_4->DSP_0_C47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX33_4" }, "DSP_R.DSP_IMUX34_0->DSP_0_B1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_0" }, "DSP_R.DSP_IMUX34_1->DSP_0_C25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_1" }, "DSP_R.DSP_IMUX34_2->DSP_0_CEP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_2" }, "DSP_R.DSP_IMUX34_3->DSP_1_CEC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_3" }, "DSP_R.DSP_IMUX34_4->DSP_0_C44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX34_4" }, "DSP_R.DSP_IMUX35_0->DSP_0_C40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_0" }, "DSP_R.DSP_IMUX35_1->DSP_0_C5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_1" }, "DSP_R.DSP_IMUX35_2->DSP_0_OPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_2" }, "DSP_R.DSP_IMUX35_3->DSP_0_C13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_3" }, "DSP_R.DSP_IMUX35_4->DSP_0_C17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX35_4" }, "DSP_R.DSP_IMUX36_0->DSP_0_B2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_0" }, "DSP_R.DSP_IMUX36_1->DSP_0_B6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_1" }, "DSP_R.DSP_IMUX36_2->DSP_0_B10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_2" }, "DSP_R.DSP_IMUX36_3->DSP_1_OPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_3" }, "DSP_R.DSP_IMUX36_4->DSP_1_CARRYINSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX36_4" }, "DSP_R.DSP_IMUX37_0->DSP_0_C2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_0" }, "DSP_R.DSP_IMUX37_1->DSP_0_C6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_1" }, "DSP_R.DSP_IMUX37_2->DSP_0_C10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_2" }, "DSP_R.DSP_IMUX37_3->DSP_0_C14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_3" }, "DSP_R.DSP_IMUX37_4->DSP_0_C45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX37_4" }, "DSP_R.DSP_IMUX38_0->DSP_0_C20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_0" }, "DSP_R.DSP_IMUX38_1->DSP_0_B4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_1" }, "DSP_R.DSP_IMUX38_2->DSP_0_OPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_2" }, "DSP_R.DSP_IMUX38_3->DSP_0_C32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_3" }, "DSP_R.DSP_IMUX38_4->DSP_0_C36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX38_4" }, "DSP_R.DSP_IMUX39_0->DSP_0_C0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_0" }, "DSP_R.DSP_IMUX39_1->DSP_0_C4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_1" }, "DSP_R.DSP_IMUX39_2->DSP_0_C8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_2" }, "DSP_R.DSP_IMUX39_3->DSP_0_C12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_3" }, "DSP_R.DSP_IMUX39_4->DSP_0_C16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX39_4" }, "DSP_R.DSP_IMUX3_0->DSP_0_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_0" }, "DSP_R.DSP_IMUX3_1->DSP_0_RSTALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_1" }, "DSP_R.DSP_IMUX3_2->DSP_0_C9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_2" }, "DSP_R.DSP_IMUX3_3->DSP_0_B13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_3" }, "DSP_R.DSP_IMUX3_4->DSP_0_B17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX3_4" }, "DSP_R.DSP_IMUX40_0->DSP_0_B3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_0" }, "DSP_R.DSP_IMUX40_1->DSP_0_CEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_1" }, "DSP_R.DSP_IMUX40_2->DSP_0_CEC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_2" }, "DSP_R.DSP_IMUX40_3->DSP_1_B14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_3" }, "DSP_R.DSP_IMUX40_4->DSP_1_ALUMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX40_4" }, "DSP_R.DSP_IMUX41_0->DSP_1_C3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_0" }, "DSP_R.DSP_IMUX41_1->DSP_0_CEB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_1" }, "DSP_R.DSP_IMUX41_2->DSP_0_CECTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CECTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_2" }, "DSP_R.DSP_IMUX41_3->DSP_1_B12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_3" }, "DSP_R.DSP_IMUX41_4->DSP_1_C19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX41_4" }, "DSP_R.DSP_IMUX42_0->DSP_0_C42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_0" }, "DSP_R.DSP_IMUX42_1->DSP_0_RSTINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_1" }, "DSP_R.DSP_IMUX42_2->DSP_1_B9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_2" }, "DSP_R.DSP_IMUX42_3->DSP_0_B14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_3" }, "DSP_R.DSP_IMUX42_4->DSP_1_B16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX42_4" }, "DSP_R.DSP_IMUX43_0->DSP_1_C1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_0" }, "DSP_R.DSP_IMUX43_1->DSP_0_RSTCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_1" }, "DSP_R.DSP_IMUX43_2->DSP_1_C9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_2" }, "DSP_R.DSP_IMUX43_3->DSP_0_B12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_3" }, "DSP_R.DSP_IMUX43_4->DSP_0_B16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_B16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX43_4" }, "DSP_R.DSP_IMUX44_0->DSP_1_A22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_0" }, "DSP_R.DSP_IMUX44_1->DSP_1_A26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_1" }, "DSP_R.DSP_IMUX44_2->DSP_1_B10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_2" }, "DSP_R.DSP_IMUX44_3->DSP_1_A14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_3" }, "DSP_R.DSP_IMUX44_4->DSP_1_A18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX44_4" }, "DSP_R.DSP_IMUX45_0->DSP_1_A20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_0" }, "DSP_R.DSP_IMUX45_1->DSP_1_A24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_1" }, "DSP_R.DSP_IMUX45_2->DSP_1_A28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_2" }, "DSP_R.DSP_IMUX45_3->DSP_1_A12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_3" }, "DSP_R.DSP_IMUX45_4->DSP_1_A16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX45_4" }, "DSP_R.DSP_IMUX46_0->DSP_0_A22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_0" }, "DSP_R.DSP_IMUX46_1->DSP_0_A26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_1" }, "DSP_R.DSP_IMUX46_2->DSP_1_C28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_2" }, "DSP_R.DSP_IMUX46_3->DSP_0_A14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_3" }, "DSP_R.DSP_IMUX46_4->DSP_0_A18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX46_4" }, "DSP_R.DSP_IMUX47_0->DSP_0_A20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_0" }, "DSP_R.DSP_IMUX47_1->DSP_0_A24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_1" }, "DSP_R.DSP_IMUX47_2->DSP_0_A28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_2" }, "DSP_R.DSP_IMUX47_3->DSP_0_A12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_3" }, "DSP_R.DSP_IMUX47_4->DSP_0_A16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX47_4" }, "DSP_R.DSP_IMUX4_0->DSP_1_A23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_0" }, "DSP_R.DSP_IMUX4_1->DSP_1_A27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_1" }, "DSP_R.DSP_IMUX4_2->DSP_0_C30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_2" }, "DSP_R.DSP_IMUX4_3->DSP_1_A15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_3" }, "DSP_R.DSP_IMUX4_4->DSP_1_A19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX4_4" }, "DSP_R.DSP_IMUX5_0->DSP_1_A21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_0" }, "DSP_R.DSP_IMUX5_1->DSP_1_A25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_1" }, "DSP_R.DSP_IMUX5_2->DSP_1_A29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_2" }, "DSP_R.DSP_IMUX5_3->DSP_1_A13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_3" }, "DSP_R.DSP_IMUX5_4->DSP_1_A17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX5_4" }, "DSP_R.DSP_IMUX6_0->DSP_0_A23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_0" }, "DSP_R.DSP_IMUX6_1->DSP_0_A27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_1" }, "DSP_R.DSP_IMUX6_2->DSP_0_C28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_C28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_2" }, "DSP_R.DSP_IMUX6_3->DSP_0_A15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_3" }, "DSP_R.DSP_IMUX6_4->DSP_0_A19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX6_4" }, "DSP_R.DSP_IMUX7_0->DSP_0_A21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_0" }, "DSP_R.DSP_IMUX7_1->DSP_0_A25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_1" }, "DSP_R.DSP_IMUX7_2->DSP_0_A29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_2" }, "DSP_R.DSP_IMUX7_3->DSP_0_A13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_3" }, "DSP_R.DSP_IMUX7_4->DSP_0_A17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_A17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX7_4" }, "DSP_R.DSP_IMUX8_0->DSP_1_C41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_C41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_0" }, "DSP_R.DSP_IMUX8_1->DSP_1_B7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_1" }, "DSP_R.DSP_IMUX8_2->DSP_1_B11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_B11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_2" }, "DSP_R.DSP_IMUX8_3->DSP_1_CEB1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEB1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_3" }, "DSP_R.DSP_IMUX8_4->DSP_1_OPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX8_4" }, "DSP_R.DSP_IMUX9_0->DSP_1_A3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_0" }, "DSP_R.DSP_IMUX9_1->DSP_1_A7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_1" }, "DSP_R.DSP_IMUX9_2->DSP_1_A11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_A11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_2" }, "DSP_R.DSP_IMUX9_3->DSP_1_CEA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_3" }, "DSP_R.DSP_IMUX9_4->DSP_1_OPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_IMUX9_4" }, "DSP_R.DSP_VCC_R->DSP_0_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_0_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_0_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_ALUMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_ALUMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_ALUMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CARRYINSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CARRYINSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CEAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CEALUMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEALUMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_CEINMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_CEINMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_D9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_D9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_INMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_INMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_OPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_OPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" }, "DSP_R.DSP_VCC_R->DSP_1_RSTD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "DSP_1_RSTD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "DSP_VCC_R" } }, @@ -5564,423 +14298,4176 @@ "name": "X0Y0", "prefix": "DSP48", "site_pins": { - "A0": "DSP_0_A0", - "A1": "DSP_0_A1", - "A10": "DSP_0_A10", - "A11": "DSP_0_A11", - "A12": "DSP_0_A12", - "A13": "DSP_0_A13", - "A14": "DSP_0_A14", - "A15": "DSP_0_A15", - "A16": "DSP_0_A16", - "A17": "DSP_0_A17", - "A18": "DSP_0_A18", - "A19": "DSP_0_A19", - "A2": "DSP_0_A2", - "A20": "DSP_0_A20", - "A21": "DSP_0_A21", - "A22": "DSP_0_A22", - "A23": "DSP_0_A23", - "A24": "DSP_0_A24", - "A25": "DSP_0_A25", - "A26": "DSP_0_A26", - "A27": "DSP_0_A27", - "A28": "DSP_0_A28", - "A29": "DSP_0_A29", - "A3": "DSP_0_A3", - "A4": "DSP_0_A4", - "A5": "DSP_0_A5", - "A6": "DSP_0_A6", - "A7": "DSP_0_A7", - "A8": "DSP_0_A8", - "A9": "DSP_0_A9", - "ACIN0": "DSP_0_ACIN0", - "ACIN1": "DSP_0_ACIN1", - "ACIN10": "DSP_0_ACIN10", - "ACIN11": "DSP_0_ACIN11", - "ACIN12": "DSP_0_ACIN12", - "ACIN13": "DSP_0_ACIN13", - "ACIN14": "DSP_0_ACIN14", - "ACIN15": "DSP_0_ACIN15", - "ACIN16": "DSP_0_ACIN16", - "ACIN17": "DSP_0_ACIN17", - "ACIN18": "DSP_0_ACIN18", - "ACIN19": "DSP_0_ACIN19", - "ACIN2": "DSP_0_ACIN2", - "ACIN20": "DSP_0_ACIN20", - "ACIN21": "DSP_0_ACIN21", - "ACIN22": "DSP_0_ACIN22", - "ACIN23": "DSP_0_ACIN23", - "ACIN24": "DSP_0_ACIN24", - "ACIN25": "DSP_0_ACIN25", - "ACIN26": "DSP_0_ACIN26", - "ACIN27": "DSP_0_ACIN27", - "ACIN28": "DSP_0_ACIN28", - "ACIN29": "DSP_0_ACIN29", - "ACIN3": "DSP_0_ACIN3", - "ACIN4": "DSP_0_ACIN4", - "ACIN5": "DSP_0_ACIN5", - "ACIN6": "DSP_0_ACIN6", - "ACIN7": "DSP_0_ACIN7", - "ACIN8": "DSP_0_ACIN8", - "ACIN9": "DSP_0_ACIN9", - "ACOUT0": "DSP_0_ACOUT0", - "ACOUT1": "DSP_0_ACOUT1", - "ACOUT10": "DSP_0_ACOUT10", - "ACOUT11": "DSP_0_ACOUT11", - "ACOUT12": "DSP_0_ACOUT12", - "ACOUT13": "DSP_0_ACOUT13", - "ACOUT14": "DSP_0_ACOUT14", - "ACOUT15": "DSP_0_ACOUT15", - "ACOUT16": "DSP_0_ACOUT16", - "ACOUT17": "DSP_0_ACOUT17", - "ACOUT18": "DSP_0_ACOUT18", - "ACOUT19": "DSP_0_ACOUT19", - "ACOUT2": "DSP_0_ACOUT2", - "ACOUT20": "DSP_0_ACOUT20", - "ACOUT21": "DSP_0_ACOUT21", - "ACOUT22": "DSP_0_ACOUT22", - "ACOUT23": "DSP_0_ACOUT23", - "ACOUT24": "DSP_0_ACOUT24", - "ACOUT25": "DSP_0_ACOUT25", - "ACOUT26": "DSP_0_ACOUT26", - "ACOUT27": "DSP_0_ACOUT27", - "ACOUT28": "DSP_0_ACOUT28", - "ACOUT29": "DSP_0_ACOUT29", - "ACOUT3": "DSP_0_ACOUT3", - "ACOUT4": "DSP_0_ACOUT4", - "ACOUT5": "DSP_0_ACOUT5", - "ACOUT6": "DSP_0_ACOUT6", - "ACOUT7": "DSP_0_ACOUT7", - "ACOUT8": "DSP_0_ACOUT8", - "ACOUT9": "DSP_0_ACOUT9", - "ALUMODE0": "DSP_0_ALUMODE0", - "ALUMODE1": "DSP_0_ALUMODE1", - "ALUMODE2": "DSP_0_ALUMODE2", - "ALUMODE3": "DSP_0_ALUMODE3", - "B0": "DSP_0_B0", - "B1": "DSP_0_B1", - "B10": "DSP_0_B10", - "B11": "DSP_0_B11", - "B12": "DSP_0_B12", - "B13": "DSP_0_B13", - "B14": "DSP_0_B14", - "B15": "DSP_0_B15", - "B16": "DSP_0_B16", - "B17": "DSP_0_B17", - "B2": "DSP_0_B2", - "B3": "DSP_0_B3", - "B4": "DSP_0_B4", - "B5": "DSP_0_B5", - "B6": "DSP_0_B6", - "B7": "DSP_0_B7", - "B8": "DSP_0_B8", - "B9": "DSP_0_B9", - "BCIN0": "DSP_0_BCIN0", - "BCIN1": "DSP_0_BCIN1", - "BCIN10": "DSP_0_BCIN10", - "BCIN11": "DSP_0_BCIN11", - "BCIN12": "DSP_0_BCIN12", - "BCIN13": "DSP_0_BCIN13", - "BCIN14": "DSP_0_BCIN14", - "BCIN15": "DSP_0_BCIN15", - "BCIN16": "DSP_0_BCIN16", - "BCIN17": "DSP_0_BCIN17", - "BCIN2": "DSP_0_BCIN2", - "BCIN3": "DSP_0_BCIN3", - "BCIN4": "DSP_0_BCIN4", - "BCIN5": "DSP_0_BCIN5", - "BCIN6": "DSP_0_BCIN6", - "BCIN7": "DSP_0_BCIN7", - "BCIN8": "DSP_0_BCIN8", - "BCIN9": "DSP_0_BCIN9", - "BCOUT0": "DSP_0_BCOUT0", - "BCOUT1": "DSP_0_BCOUT1", - "BCOUT10": "DSP_0_BCOUT10", - "BCOUT11": "DSP_0_BCOUT11", - "BCOUT12": "DSP_0_BCOUT12", - "BCOUT13": "DSP_0_BCOUT13", - "BCOUT14": "DSP_0_BCOUT14", - "BCOUT15": "DSP_0_BCOUT15", - "BCOUT16": "DSP_0_BCOUT16", - "BCOUT17": "DSP_0_BCOUT17", - "BCOUT2": "DSP_0_BCOUT2", - "BCOUT3": "DSP_0_BCOUT3", - "BCOUT4": "DSP_0_BCOUT4", - "BCOUT5": "DSP_0_BCOUT5", - "BCOUT6": "DSP_0_BCOUT6", - "BCOUT7": "DSP_0_BCOUT7", - "BCOUT8": "DSP_0_BCOUT8", - "BCOUT9": "DSP_0_BCOUT9", - "C0": "DSP_0_C0", - "C1": "DSP_0_C1", - "C10": "DSP_0_C10", - "C11": "DSP_0_C11", - "C12": "DSP_0_C12", - "C13": "DSP_0_C13", - "C14": "DSP_0_C14", - "C15": "DSP_0_C15", - "C16": "DSP_0_C16", - "C17": "DSP_0_C17", - "C18": "DSP_0_C18", - "C19": "DSP_0_C19", - "C2": "DSP_0_C2", - "C20": "DSP_0_C20", - "C21": "DSP_0_C21", - "C22": "DSP_0_C22", - "C23": "DSP_0_C23", - "C24": "DSP_0_C24", - "C25": "DSP_0_C25", - "C26": "DSP_0_C26", - "C27": "DSP_0_C27", - "C28": "DSP_0_C28", - "C29": "DSP_0_C29", - "C3": "DSP_0_C3", - "C30": "DSP_0_C30", - "C31": "DSP_0_C31", - "C32": "DSP_0_C32", - "C33": "DSP_0_C33", - "C34": "DSP_0_C34", - "C35": "DSP_0_C35", - "C36": "DSP_0_C36", - "C37": "DSP_0_C37", - "C38": "DSP_0_C38", - "C39": "DSP_0_C39", - "C4": "DSP_0_C4", - "C40": "DSP_0_C40", - "C41": "DSP_0_C41", - "C42": "DSP_0_C42", - "C43": "DSP_0_C43", - "C44": "DSP_0_C44", - "C45": "DSP_0_C45", - "C46": "DSP_0_C46", - "C47": "DSP_0_C47", - "C5": "DSP_0_C5", - "C6": "DSP_0_C6", - "C7": "DSP_0_C7", - "C8": "DSP_0_C8", - "C9": "DSP_0_C9", - "CARRYCASCIN": "DSP_0_CARRYCASCIN", - "CARRYCASCOUT": "DSP_0_CARRYCASCOUT", - "CARRYIN": "DSP_0_CARRYIN", - "CARRYINSEL0": "DSP_0_CARRYINSEL0", - "CARRYINSEL1": "DSP_0_CARRYINSEL1", - "CARRYINSEL2": "DSP_0_CARRYINSEL2", - "CARRYOUT0": "DSP_0_CARRYOUT0", - "CARRYOUT1": "DSP_0_CARRYOUT1", - "CARRYOUT2": "DSP_0_CARRYOUT2", - "CARRYOUT3": "DSP_0_CARRYOUT3", - "CEA1": "DSP_0_CEA1", - "CEA2": "DSP_0_CEA2", - "CEAD": "DSP_0_CEAD", - "CEALUMODE": "DSP_0_CEALUMODE", - "CEB1": "DSP_0_CEB1", - "CEB2": "DSP_0_CEB2", - "CEC": "DSP_0_CEC", - "CECARRYIN": "DSP_0_CECARRYIN", - "CECTRL": "DSP_0_CECTRL", - "CED": "DSP_0_CED", - "CEINMODE": "DSP_0_CEINMODE", - "CEM": "DSP_0_CEM", - "CEP": "DSP_0_CEP", - "CLK": "DSP_0_CLK", - "D0": "DSP_0_D0", - "D1": "DSP_0_D1", - "D10": "DSP_0_D10", - "D11": "DSP_0_D11", - "D12": "DSP_0_D12", - "D13": "DSP_0_D13", - "D14": "DSP_0_D14", - "D15": "DSP_0_D15", - "D16": "DSP_0_D16", - "D17": "DSP_0_D17", - "D18": "DSP_0_D18", - "D19": "DSP_0_D19", - "D2": "DSP_0_D2", - "D20": "DSP_0_D20", - "D21": "DSP_0_D21", - "D22": "DSP_0_D22", - "D23": "DSP_0_D23", - "D24": "DSP_0_D24", - "D3": "DSP_0_D3", - "D4": "DSP_0_D4", - "D5": "DSP_0_D5", - "D6": "DSP_0_D6", - "D7": "DSP_0_D7", - "D8": "DSP_0_D8", - "D9": "DSP_0_D9", - "INMODE0": "DSP_0_INMODE0", - "INMODE1": "DSP_0_INMODE1", - "INMODE2": "DSP_0_INMODE2", - "INMODE3": "DSP_0_INMODE3", - "INMODE4": "DSP_0_INMODE4", - "MULTSIGNIN": "DSP_0_MULTSIGNIN", - "MULTSIGNOUT": "DSP_0_MULTSIGNOUT", - "OPMODE0": "DSP_0_OPMODE0", - "OPMODE1": "DSP_0_OPMODE1", - "OPMODE2": "DSP_0_OPMODE2", - "OPMODE3": "DSP_0_OPMODE3", - "OPMODE4": "DSP_0_OPMODE4", - "OPMODE5": "DSP_0_OPMODE5", - "OPMODE6": "DSP_0_OPMODE6", - "OVERFLOW": "DSP_0_OVERFLOW", - "P0": "DSP_0_P0", - "P1": "DSP_0_P1", - "P10": "DSP_0_P10", - "P11": "DSP_0_P11", - "P12": "DSP_0_P12", - "P13": "DSP_0_P13", - "P14": "DSP_0_P14", - "P15": "DSP_0_P15", - "P16": "DSP_0_P16", - "P17": "DSP_0_P17", - "P18": "DSP_0_P18", - "P19": "DSP_0_P19", - "P2": "DSP_0_P2", - "P20": "DSP_0_P20", - "P21": "DSP_0_P21", - "P22": "DSP_0_P22", - "P23": "DSP_0_P23", - "P24": "DSP_0_P24", - "P25": "DSP_0_P25", - "P26": "DSP_0_P26", - "P27": "DSP_0_P27", - "P28": "DSP_0_P28", - "P29": "DSP_0_P29", - "P3": "DSP_0_P3", - "P30": "DSP_0_P30", - "P31": "DSP_0_P31", - "P32": "DSP_0_P32", - "P33": "DSP_0_P33", - "P34": "DSP_0_P34", - "P35": "DSP_0_P35", - "P36": "DSP_0_P36", - "P37": "DSP_0_P37", - "P38": "DSP_0_P38", - "P39": "DSP_0_P39", - "P4": "DSP_0_P4", - "P40": "DSP_0_P40", - "P41": "DSP_0_P41", - "P42": "DSP_0_P42", - "P43": "DSP_0_P43", - "P44": "DSP_0_P44", - "P45": "DSP_0_P45", - "P46": "DSP_0_P46", - "P47": "DSP_0_P47", - "P5": "DSP_0_P5", - "P6": "DSP_0_P6", - "P7": "DSP_0_P7", - "P8": "DSP_0_P8", - "P9": "DSP_0_P9", - "PATTERNBDETECT": "DSP_0_PATTERNBDETECT", - "PATTERNDETECT": "DSP_0_PATTERNDETECT", - "PCIN0": "DSP_0_PCIN0", - "PCIN1": "DSP_0_PCIN1", - "PCIN10": "DSP_0_PCIN10", - "PCIN11": "DSP_0_PCIN11", - "PCIN12": "DSP_0_PCIN12", - "PCIN13": "DSP_0_PCIN13", - "PCIN14": "DSP_0_PCIN14", - "PCIN15": "DSP_0_PCIN15", - "PCIN16": "DSP_0_PCIN16", - "PCIN17": "DSP_0_PCIN17", - "PCIN18": "DSP_0_PCIN18", - "PCIN19": "DSP_0_PCIN19", - "PCIN2": "DSP_0_PCIN2", - "PCIN20": "DSP_0_PCIN20", - "PCIN21": "DSP_0_PCIN21", - "PCIN22": "DSP_0_PCIN22", - "PCIN23": "DSP_0_PCIN23", - "PCIN24": "DSP_0_PCIN24", - "PCIN25": "DSP_0_PCIN25", - "PCIN26": "DSP_0_PCIN26", - "PCIN27": "DSP_0_PCIN27", - "PCIN28": "DSP_0_PCIN28", - "PCIN29": "DSP_0_PCIN29", - "PCIN3": "DSP_0_PCIN3", - "PCIN30": "DSP_0_PCIN30", - "PCIN31": "DSP_0_PCIN31", - "PCIN32": "DSP_0_PCIN32", - "PCIN33": "DSP_0_PCIN33", - "PCIN34": "DSP_0_PCIN34", - "PCIN35": "DSP_0_PCIN35", - "PCIN36": "DSP_0_PCIN36", - "PCIN37": "DSP_0_PCIN37", - "PCIN38": "DSP_0_PCIN38", - "PCIN39": "DSP_0_PCIN39", - "PCIN4": "DSP_0_PCIN4", - "PCIN40": "DSP_0_PCIN40", - "PCIN41": "DSP_0_PCIN41", - "PCIN42": "DSP_0_PCIN42", - "PCIN43": "DSP_0_PCIN43", - "PCIN44": "DSP_0_PCIN44", - "PCIN45": "DSP_0_PCIN45", - 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"DSP_0_RSTM" + }, + "RSTP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_0_RSTP" + }, + "UNDERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1337.678375", + "wire": "DSP_0_UNDERFLOW" + } }, "type": "DSP48E1", "x_coord": 0, @@ -5990,423 +18477,4176 @@ "name": "X0Y1", "prefix": "DSP48", "site_pins": { - "A0": "DSP_1_A0", - "A1": "DSP_1_A1", - "A10": "DSP_1_A10", - "A11": "DSP_1_A11", - "A12": "DSP_1_A12", - "A13": "DSP_1_A13", - "A14": "DSP_1_A14", - "A15": "DSP_1_A15", - "A16": "DSP_1_A16", - "A17": "DSP_1_A17", - "A18": "DSP_1_A18", - "A19": "DSP_1_A19", - "A2": "DSP_1_A2", - "A20": "DSP_1_A20", - "A21": "DSP_1_A21", - "A22": "DSP_1_A22", - "A23": "DSP_1_A23", - "A24": "DSP_1_A24", - "A25": "DSP_1_A25", - "A26": "DSP_1_A26", - "A27": "DSP_1_A27", - "A28": "DSP_1_A28", - "A29": "DSP_1_A29", - "A3": "DSP_1_A3", - "A4": "DSP_1_A4", - "A5": "DSP_1_A5", - "A6": "DSP_1_A6", - "A7": "DSP_1_A7", - "A8": "DSP_1_A8", - "A9": "DSP_1_A9", - "ACIN0": "DSP_1_ACIN0", - "ACIN1": "DSP_1_ACIN1", - "ACIN10": "DSP_1_ACIN10", - "ACIN11": "DSP_1_ACIN11", - "ACIN12": "DSP_1_ACIN12", - "ACIN13": "DSP_1_ACIN13", - "ACIN14": "DSP_1_ACIN14", - "ACIN15": "DSP_1_ACIN15", - "ACIN16": "DSP_1_ACIN16", - "ACIN17": "DSP_1_ACIN17", - "ACIN18": "DSP_1_ACIN18", - "ACIN19": "DSP_1_ACIN19", - "ACIN2": "DSP_1_ACIN2", - "ACIN20": "DSP_1_ACIN20", - "ACIN21": "DSP_1_ACIN21", - "ACIN22": "DSP_1_ACIN22", - "ACIN23": "DSP_1_ACIN23", - "ACIN24": "DSP_1_ACIN24", - "ACIN25": "DSP_1_ACIN25", - "ACIN26": "DSP_1_ACIN26", - "ACIN27": "DSP_1_ACIN27", - "ACIN28": "DSP_1_ACIN28", - "ACIN29": "DSP_1_ACIN29", - "ACIN3": "DSP_1_ACIN3", - "ACIN4": "DSP_1_ACIN4", - "ACIN5": "DSP_1_ACIN5", - "ACIN6": "DSP_1_ACIN6", - "ACIN7": "DSP_1_ACIN7", - "ACIN8": "DSP_1_ACIN8", - "ACIN9": "DSP_1_ACIN9", - "ACOUT0": "DSP_1_ACOUT0", - "ACOUT1": "DSP_1_ACOUT1", - "ACOUT10": "DSP_1_ACOUT10", - "ACOUT11": "DSP_1_ACOUT11", - "ACOUT12": "DSP_1_ACOUT12", - "ACOUT13": "DSP_1_ACOUT13", - "ACOUT14": "DSP_1_ACOUT14", - "ACOUT15": "DSP_1_ACOUT15", - "ACOUT16": "DSP_1_ACOUT16", - "ACOUT17": "DSP_1_ACOUT17", - "ACOUT18": "DSP_1_ACOUT18", - "ACOUT19": "DSP_1_ACOUT19", - "ACOUT2": "DSP_1_ACOUT2", - "ACOUT20": "DSP_1_ACOUT20", - "ACOUT21": "DSP_1_ACOUT21", - "ACOUT22": "DSP_1_ACOUT22", - "ACOUT23": "DSP_1_ACOUT23", - "ACOUT24": "DSP_1_ACOUT24", - "ACOUT25": "DSP_1_ACOUT25", - "ACOUT26": "DSP_1_ACOUT26", - "ACOUT27": "DSP_1_ACOUT27", - "ACOUT28": "DSP_1_ACOUT28", - "ACOUT29": "DSP_1_ACOUT29", - "ACOUT3": "DSP_1_ACOUT3", - "ACOUT4": "DSP_1_ACOUT4", - "ACOUT5": "DSP_1_ACOUT5", - "ACOUT6": "DSP_1_ACOUT6", - "ACOUT7": "DSP_1_ACOUT7", - "ACOUT8": "DSP_1_ACOUT8", - "ACOUT9": "DSP_1_ACOUT9", - "ALUMODE0": "DSP_1_ALUMODE0", - "ALUMODE1": "DSP_1_ALUMODE1", - "ALUMODE2": "DSP_1_ALUMODE2", - "ALUMODE3": "DSP_1_ALUMODE3", - "B0": "DSP_1_B0", - "B1": "DSP_1_B1", - "B10": "DSP_1_B10", - "B11": "DSP_1_B11", - "B12": "DSP_1_B12", - "B13": "DSP_1_B13", - "B14": "DSP_1_B14", - "B15": "DSP_1_B15", - "B16": "DSP_1_B16", - "B17": "DSP_1_B17", - "B2": "DSP_1_B2", - "B3": "DSP_1_B3", - "B4": "DSP_1_B4", - "B5": "DSP_1_B5", - "B6": "DSP_1_B6", - "B7": "DSP_1_B7", - "B8": "DSP_1_B8", - "B9": "DSP_1_B9", - "BCIN0": "DSP_1_BCIN0", - "BCIN1": "DSP_1_BCIN1", - "BCIN10": "DSP_1_BCIN10", - "BCIN11": "DSP_1_BCIN11", - "BCIN12": "DSP_1_BCIN12", - "BCIN13": "DSP_1_BCIN13", - "BCIN14": "DSP_1_BCIN14", - "BCIN15": "DSP_1_BCIN15", - "BCIN16": "DSP_1_BCIN16", - "BCIN17": "DSP_1_BCIN17", - "BCIN2": "DSP_1_BCIN2", - "BCIN3": "DSP_1_BCIN3", - "BCIN4": "DSP_1_BCIN4", - "BCIN5": "DSP_1_BCIN5", - "BCIN6": "DSP_1_BCIN6", - "BCIN7": "DSP_1_BCIN7", - "BCIN8": "DSP_1_BCIN8", - "BCIN9": "DSP_1_BCIN9", - "BCOUT0": "DSP_1_BCOUT0", - "BCOUT1": "DSP_1_BCOUT1", - "BCOUT10": "DSP_1_BCOUT10", - "BCOUT11": "DSP_1_BCOUT11", - "BCOUT12": "DSP_1_BCOUT12", - "BCOUT13": "DSP_1_BCOUT13", - "BCOUT14": "DSP_1_BCOUT14", - "BCOUT15": "DSP_1_BCOUT15", - "BCOUT16": "DSP_1_BCOUT16", - "BCOUT17": "DSP_1_BCOUT17", - "BCOUT2": "DSP_1_BCOUT2", - "BCOUT3": "DSP_1_BCOUT3", - "BCOUT4": "DSP_1_BCOUT4", - "BCOUT5": "DSP_1_BCOUT5", - "BCOUT6": "DSP_1_BCOUT6", - "BCOUT7": "DSP_1_BCOUT7", - "BCOUT8": "DSP_1_BCOUT8", - "BCOUT9": "DSP_1_BCOUT9", - "C0": "DSP_1_C0", - "C1": "DSP_1_C1", - "C10": "DSP_1_C10", - "C11": "DSP_1_C11", - "C12": "DSP_1_C12", - "C13": "DSP_1_C13", - "C14": "DSP_1_C14", - "C15": "DSP_1_C15", - "C16": "DSP_1_C16", - "C17": "DSP_1_C17", - "C18": "DSP_1_C18", - "C19": "DSP_1_C19", - "C2": "DSP_1_C2", - "C20": "DSP_1_C20", - "C21": "DSP_1_C21", - "C22": "DSP_1_C22", - "C23": "DSP_1_C23", - "C24": "DSP_1_C24", - "C25": "DSP_1_C25", - "C26": "DSP_1_C26", - "C27": "DSP_1_C27", - "C28": "DSP_1_C28", - "C29": "DSP_1_C29", - "C3": "DSP_1_C3", - "C30": "DSP_1_C30", - "C31": "DSP_1_C31", - "C32": "DSP_1_C32", - "C33": "DSP_1_C33", - "C34": "DSP_1_C34", - "C35": "DSP_1_C35", - "C36": "DSP_1_C36", - "C37": "DSP_1_C37", - "C38": "DSP_1_C38", - "C39": "DSP_1_C39", - "C4": "DSP_1_C4", - "C40": "DSP_1_C40", - "C41": "DSP_1_C41", - "C42": "DSP_1_C42", - "C43": "DSP_1_C43", - "C44": "DSP_1_C44", - "C45": "DSP_1_C45", - "C46": "DSP_1_C46", - "C47": "DSP_1_C47", - "C5": "DSP_1_C5", - "C6": "DSP_1_C6", - "C7": "DSP_1_C7", - "C8": "DSP_1_C8", - "C9": "DSP_1_C9", - "CARRYCASCIN": "DSP_1_CARRYCASCIN", - "CARRYCASCOUT": "DSP_1_CARRYCASCOUT", - "CARRYIN": "DSP_1_CARRYIN", - "CARRYINSEL0": "DSP_1_CARRYINSEL0", - "CARRYINSEL1": "DSP_1_CARRYINSEL1", - "CARRYINSEL2": "DSP_1_CARRYINSEL2", - "CARRYOUT0": "DSP_1_CARRYOUT0", - "CARRYOUT1": "DSP_1_CARRYOUT1", - "CARRYOUT2": "DSP_1_CARRYOUT2", - "CARRYOUT3": "DSP_1_CARRYOUT3", - "CEA1": "DSP_1_CEA1", - "CEA2": "DSP_1_CEA2", - "CEAD": "DSP_1_CEAD", - "CEALUMODE": "DSP_1_CEALUMODE", - "CEB1": "DSP_1_CEB1", - "CEB2": "DSP_1_CEB2", - "CEC": "DSP_1_CEC", - "CECARRYIN": "DSP_1_CECARRYIN", - "CECTRL": "DSP_1_CECTRL", - "CED": "DSP_1_CED", - "CEINMODE": "DSP_1_CEINMODE", - "CEM": "DSP_1_CEM", - "CEP": "DSP_1_CEP", - "CLK": "DSP_1_CLK", - "D0": "DSP_1_D0", - "D1": "DSP_1_D1", - "D10": "DSP_1_D10", - "D11": "DSP_1_D11", - "D12": "DSP_1_D12", - "D13": "DSP_1_D13", - "D14": "DSP_1_D14", - "D15": "DSP_1_D15", - "D16": "DSP_1_D16", - "D17": "DSP_1_D17", - "D18": "DSP_1_D18", - "D19": "DSP_1_D19", - "D2": "DSP_1_D2", - "D20": "DSP_1_D20", - "D21": "DSP_1_D21", - "D22": "DSP_1_D22", - "D23": "DSP_1_D23", - "D24": "DSP_1_D24", - "D3": "DSP_1_D3", - "D4": "DSP_1_D4", - "D5": "DSP_1_D5", - "D6": "DSP_1_D6", - "D7": "DSP_1_D7", - "D8": "DSP_1_D8", - "D9": "DSP_1_D9", - "INMODE0": "DSP_1_INMODE0", - "INMODE1": "DSP_1_INMODE1", - "INMODE2": "DSP_1_INMODE2", - "INMODE3": "DSP_1_INMODE3", - "INMODE4": "DSP_1_INMODE4", - "MULTSIGNIN": "DSP_1_MULTSIGNIN", - "MULTSIGNOUT": "DSP_1_MULTSIGNOUT", - "OPMODE0": "DSP_1_OPMODE0", - "OPMODE1": "DSP_1_OPMODE1", - "OPMODE2": "DSP_1_OPMODE2", - "OPMODE3": "DSP_1_OPMODE3", - "OPMODE4": "DSP_1_OPMODE4", - "OPMODE5": "DSP_1_OPMODE5", - "OPMODE6": "DSP_1_OPMODE6", - "OVERFLOW": "DSP_1_OVERFLOW", - "P0": "DSP_1_P0", - "P1": "DSP_1_P1", - "P10": "DSP_1_P10", - "P11": "DSP_1_P11", - "P12": "DSP_1_P12", - "P13": "DSP_1_P13", - "P14": "DSP_1_P14", - "P15": "DSP_1_P15", - "P16": "DSP_1_P16", - "P17": "DSP_1_P17", - "P18": "DSP_1_P18", - "P19": "DSP_1_P19", - "P2": "DSP_1_P2", - "P20": "DSP_1_P20", - "P21": "DSP_1_P21", - "P22": "DSP_1_P22", - "P23": "DSP_1_P23", - "P24": "DSP_1_P24", - "P25": "DSP_1_P25", - "P26": "DSP_1_P26", - "P27": "DSP_1_P27", - "P28": "DSP_1_P28", - "P29": "DSP_1_P29", - "P3": "DSP_1_P3", - "P30": "DSP_1_P30", - "P31": "DSP_1_P31", - "P32": "DSP_1_P32", - "P33": "DSP_1_P33", - "P34": "DSP_1_P34", - "P35": "DSP_1_P35", - "P36": "DSP_1_P36", - "P37": "DSP_1_P37", - "P38": "DSP_1_P38", - "P39": "DSP_1_P39", - "P4": "DSP_1_P4", - "P40": "DSP_1_P40", - "P41": "DSP_1_P41", - "P42": "DSP_1_P42", - "P43": "DSP_1_P43", - "P44": "DSP_1_P44", - "P45": "DSP_1_P45", - "P46": "DSP_1_P46", - "P47": "DSP_1_P47", - "P5": "DSP_1_P5", - "P6": "DSP_1_P6", - "P7": "DSP_1_P7", - "P8": "DSP_1_P8", - "P9": "DSP_1_P9", - "PATTERNBDETECT": "DSP_1_PATTERNBDETECT", - "PATTERNDETECT": "DSP_1_PATTERNDETECT", - "PCIN0": "DSP_1_PCIN0", - "PCIN1": "DSP_1_PCIN1", - "PCIN10": "DSP_1_PCIN10", - "PCIN11": "DSP_1_PCIN11", - "PCIN12": "DSP_1_PCIN12", - "PCIN13": "DSP_1_PCIN13", - "PCIN14": "DSP_1_PCIN14", - "PCIN15": "DSP_1_PCIN15", - "PCIN16": "DSP_1_PCIN16", - "PCIN17": "DSP_1_PCIN17", - "PCIN18": "DSP_1_PCIN18", - "PCIN19": "DSP_1_PCIN19", - "PCIN2": "DSP_1_PCIN2", - "PCIN20": "DSP_1_PCIN20", - "PCIN21": "DSP_1_PCIN21", - "PCIN22": "DSP_1_PCIN22", - "PCIN23": "DSP_1_PCIN23", - "PCIN24": "DSP_1_PCIN24", - "PCIN25": "DSP_1_PCIN25", - "PCIN26": "DSP_1_PCIN26", - "PCIN27": "DSP_1_PCIN27", - "PCIN28": "DSP_1_PCIN28", - "PCIN29": "DSP_1_PCIN29", - "PCIN3": "DSP_1_PCIN3", - "PCIN30": "DSP_1_PCIN30", - "PCIN31": "DSP_1_PCIN31", - "PCIN32": "DSP_1_PCIN32", - "PCIN33": "DSP_1_PCIN33", - "PCIN34": "DSP_1_PCIN34", - "PCIN35": "DSP_1_PCIN35", - "PCIN36": "DSP_1_PCIN36", - "PCIN37": "DSP_1_PCIN37", - "PCIN38": "DSP_1_PCIN38", - "PCIN39": "DSP_1_PCIN39", - "PCIN4": "DSP_1_PCIN4", - "PCIN40": "DSP_1_PCIN40", - "PCIN41": "DSP_1_PCIN41", - "PCIN42": "DSP_1_PCIN42", - "PCIN43": "DSP_1_PCIN43", - "PCIN44": "DSP_1_PCIN44", - "PCIN45": "DSP_1_PCIN45", - "PCIN46": "DSP_1_PCIN46", - "PCIN47": "DSP_1_PCIN47", - "PCIN5": "DSP_1_PCIN5", - "PCIN6": "DSP_1_PCIN6", - "PCIN7": "DSP_1_PCIN7", - "PCIN8": "DSP_1_PCIN8", - "PCIN9": "DSP_1_PCIN9", - "PCOUT0": "DSP_1_PCOUT0", - "PCOUT1": "DSP_1_PCOUT1", - "PCOUT10": "DSP_1_PCOUT10", - "PCOUT11": "DSP_1_PCOUT11", - "PCOUT12": "DSP_1_PCOUT12", - "PCOUT13": "DSP_1_PCOUT13", - "PCOUT14": "DSP_1_PCOUT14", - "PCOUT15": "DSP_1_PCOUT15", - "PCOUT16": "DSP_1_PCOUT16", - "PCOUT17": "DSP_1_PCOUT17", - "PCOUT18": "DSP_1_PCOUT18", - "PCOUT19": "DSP_1_PCOUT19", - "PCOUT2": "DSP_1_PCOUT2", - "PCOUT20": "DSP_1_PCOUT20", - "PCOUT21": "DSP_1_PCOUT21", - "PCOUT22": "DSP_1_PCOUT22", - "PCOUT23": "DSP_1_PCOUT23", - "PCOUT24": "DSP_1_PCOUT24", - "PCOUT25": "DSP_1_PCOUT25", - "PCOUT26": "DSP_1_PCOUT26", - "PCOUT27": "DSP_1_PCOUT27", - "PCOUT28": "DSP_1_PCOUT28", - "PCOUT29": "DSP_1_PCOUT29", - "PCOUT3": "DSP_1_PCOUT3", - "PCOUT30": "DSP_1_PCOUT30", - "PCOUT31": "DSP_1_PCOUT31", - "PCOUT32": "DSP_1_PCOUT32", - "PCOUT33": "DSP_1_PCOUT33", - "PCOUT34": "DSP_1_PCOUT34", - "PCOUT35": "DSP_1_PCOUT35", - "PCOUT36": "DSP_1_PCOUT36", - "PCOUT37": "DSP_1_PCOUT37", - "PCOUT38": "DSP_1_PCOUT38", - "PCOUT39": "DSP_1_PCOUT39", - "PCOUT4": "DSP_1_PCOUT4", - "PCOUT40": "DSP_1_PCOUT40", - "PCOUT41": "DSP_1_PCOUT41", - "PCOUT42": "DSP_1_PCOUT42", - "PCOUT43": "DSP_1_PCOUT43", - "PCOUT44": "DSP_1_PCOUT44", - "PCOUT45": "DSP_1_PCOUT45", - "PCOUT46": "DSP_1_PCOUT46", - "PCOUT47": "DSP_1_PCOUT47", - "PCOUT5": "DSP_1_PCOUT5", - "PCOUT6": "DSP_1_PCOUT6", - "PCOUT7": "DSP_1_PCOUT7", - "PCOUT8": "DSP_1_PCOUT8", - "PCOUT9": "DSP_1_PCOUT9", - "RSTA": "DSP_1_RSTA", - "RSTALLCARRYIN": "DSP_1_RSTALLCARRYIN", - "RSTALUMODE": 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"wire": "DSP_1_RSTCTRL" + }, + "RSTD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_1_RSTD" + }, + "RSTINMODE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_1_RSTINMODE" + }, + "RSTM": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_1_RSTM" + }, + "RSTP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "DSP_1_RSTP" + }, + "UNDERFLOW": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "1337.678375", + "wire": "DSP_1_UNDERFLOW" + } }, "type": "DSP48E1", "x_coord": 0, @@ -6416,8 +22656,26 @@ "name": "X0Y0", "prefix": "TIEOFF", "site_pins": { - "HARD0": "DSP_GND_R", - "HARD1": "DSP_VCC_R" + "HARD0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "DSP_GND_R" + }, + "HARD1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "DSP_VCC_R" + } }, "type": "TIEOFF", "x_coord": 0, @@ -6425,2050 +22683,4834 @@ } ], "tile_type": "DSP_R", - "wires": [ - "DSP_0_A0", - "DSP_0_A1", - "DSP_0_A10", - "DSP_0_A11", - "DSP_0_A12", - "DSP_0_A13", - "DSP_0_A14", - "DSP_0_A15", - "DSP_0_A16", - "DSP_0_A17", - "DSP_0_A18", - "DSP_0_A19", - "DSP_0_A2", - "DSP_0_A20", - "DSP_0_A21", - "DSP_0_A22", - "DSP_0_A23", - "DSP_0_A24", - "DSP_0_A25", - "DSP_0_A26", - "DSP_0_A27", - "DSP_0_A28", - "DSP_0_A29", - "DSP_0_A3", - "DSP_0_A4", - "DSP_0_A5", - "DSP_0_A6", - "DSP_0_A7", - "DSP_0_A8", - "DSP_0_A9", - "DSP_0_ACIN0", - "DSP_0_ACIN1", - "DSP_0_ACIN10", - "DSP_0_ACIN11", - "DSP_0_ACIN12", - "DSP_0_ACIN13", - "DSP_0_ACIN14", - "DSP_0_ACIN15", - "DSP_0_ACIN16", - "DSP_0_ACIN17", - "DSP_0_ACIN18", - "DSP_0_ACIN19", - "DSP_0_ACIN2", - "DSP_0_ACIN20", - "DSP_0_ACIN21", - "DSP_0_ACIN22", - "DSP_0_ACIN23", - "DSP_0_ACIN24", - "DSP_0_ACIN25", - "DSP_0_ACIN26", - "DSP_0_ACIN27", - "DSP_0_ACIN28", - "DSP_0_ACIN29", - "DSP_0_ACIN3", - "DSP_0_ACIN4", - "DSP_0_ACIN5", - "DSP_0_ACIN6", - "DSP_0_ACIN7", - "DSP_0_ACIN8", - "DSP_0_ACIN9", - "DSP_0_ACOUT0", - "DSP_0_ACOUT1", - "DSP_0_ACOUT10", - "DSP_0_ACOUT11", - "DSP_0_ACOUT12", - "DSP_0_ACOUT13", - "DSP_0_ACOUT14", - "DSP_0_ACOUT15", - "DSP_0_ACOUT16", - "DSP_0_ACOUT17", - "DSP_0_ACOUT18", - "DSP_0_ACOUT19", - "DSP_0_ACOUT2", - "DSP_0_ACOUT20", - "DSP_0_ACOUT21", - "DSP_0_ACOUT22", - "DSP_0_ACOUT23", - "DSP_0_ACOUT24", - "DSP_0_ACOUT25", - "DSP_0_ACOUT26", - "DSP_0_ACOUT27", - "DSP_0_ACOUT28", - "DSP_0_ACOUT29", - "DSP_0_ACOUT3", - "DSP_0_ACOUT4", - "DSP_0_ACOUT5", - "DSP_0_ACOUT6", - "DSP_0_ACOUT7", - "DSP_0_ACOUT8", - "DSP_0_ACOUT9", - "DSP_0_ALUMODE0", - "DSP_0_ALUMODE1", - "DSP_0_ALUMODE2", - "DSP_0_ALUMODE3", - "DSP_0_B0", - "DSP_0_B1", - "DSP_0_B10", - "DSP_0_B11", - "DSP_0_B12", - "DSP_0_B13", - "DSP_0_B14", - "DSP_0_B15", - "DSP_0_B16", - "DSP_0_B17", - "DSP_0_B2", - "DSP_0_B3", - "DSP_0_B4", - "DSP_0_B5", - "DSP_0_B6", - "DSP_0_B7", - "DSP_0_B8", - "DSP_0_B9", - "DSP_0_BCIN0", - "DSP_0_BCIN1", - "DSP_0_BCIN10", - "DSP_0_BCIN11", - "DSP_0_BCIN12", - "DSP_0_BCIN13", - "DSP_0_BCIN14", - "DSP_0_BCIN15", - "DSP_0_BCIN16", - "DSP_0_BCIN17", - "DSP_0_BCIN2", - "DSP_0_BCIN3", - "DSP_0_BCIN4", - "DSP_0_BCIN5", - "DSP_0_BCIN6", - "DSP_0_BCIN7", - "DSP_0_BCIN8", - "DSP_0_BCIN9", - "DSP_0_BCOUT0", - "DSP_0_BCOUT1", - "DSP_0_BCOUT10", - "DSP_0_BCOUT11", - "DSP_0_BCOUT12", - "DSP_0_BCOUT13", - "DSP_0_BCOUT14", - "DSP_0_BCOUT15", - "DSP_0_BCOUT16", - "DSP_0_BCOUT17", - "DSP_0_BCOUT2", - "DSP_0_BCOUT3", - "DSP_0_BCOUT4", - "DSP_0_BCOUT5", - "DSP_0_BCOUT6", - "DSP_0_BCOUT7", - "DSP_0_BCOUT8", - "DSP_0_BCOUT9", - "DSP_0_C0", - "DSP_0_C1", - "DSP_0_C10", - "DSP_0_C11", - "DSP_0_C12", - "DSP_0_C13", - "DSP_0_C14", - "DSP_0_C15", - "DSP_0_C16", - "DSP_0_C17", - "DSP_0_C18", - "DSP_0_C19", - "DSP_0_C2", - "DSP_0_C20", - "DSP_0_C21", - "DSP_0_C22", - "DSP_0_C23", - "DSP_0_C24", - "DSP_0_C25", - "DSP_0_C26", - "DSP_0_C27", - "DSP_0_C28", - "DSP_0_C29", - "DSP_0_C3", - "DSP_0_C30", - "DSP_0_C31", - "DSP_0_C32", - "DSP_0_C33", - "DSP_0_C34", - "DSP_0_C35", - "DSP_0_C36", - "DSP_0_C37", - "DSP_0_C38", - "DSP_0_C39", - "DSP_0_C4", - "DSP_0_C40", - "DSP_0_C41", - "DSP_0_C42", - "DSP_0_C43", - "DSP_0_C44", - "DSP_0_C45", - "DSP_0_C46", - "DSP_0_C47", - "DSP_0_C5", - "DSP_0_C6", - "DSP_0_C7", - "DSP_0_C8", - "DSP_0_C9", - "DSP_0_CARRYCASCIN", - "DSP_0_CARRYCASCOUT", - "DSP_0_CARRYIN", - "DSP_0_CARRYINSEL0", - "DSP_0_CARRYINSEL1", - "DSP_0_CARRYINSEL2", - "DSP_0_CARRYOUT0", - "DSP_0_CARRYOUT1", - "DSP_0_CARRYOUT2", - "DSP_0_CARRYOUT3", - "DSP_0_CEA1", - "DSP_0_CEA2", - "DSP_0_CEAD", - "DSP_0_CEALUMODE", - "DSP_0_CEB1", - "DSP_0_CEB2", - "DSP_0_CEC", - "DSP_0_CECARRYIN", - "DSP_0_CECTRL", - "DSP_0_CED", - "DSP_0_CEINMODE", - "DSP_0_CEM", - "DSP_0_CEP", - "DSP_0_CLK", - "DSP_0_D0", - "DSP_0_D1", - "DSP_0_D10", - "DSP_0_D11", - "DSP_0_D12", - "DSP_0_D13", - "DSP_0_D14", - "DSP_0_D15", - "DSP_0_D16", - "DSP_0_D17", - "DSP_0_D18", - "DSP_0_D19", - "DSP_0_D2", - "DSP_0_D20", - "DSP_0_D21", - "DSP_0_D22", - "DSP_0_D23", - "DSP_0_D24", - "DSP_0_D3", - "DSP_0_D4", - "DSP_0_D5", - "DSP_0_D6", - "DSP_0_D7", - "DSP_0_D8", - "DSP_0_D9", - "DSP_0_INMODE0", - "DSP_0_INMODE1", - "DSP_0_INMODE2", - "DSP_0_INMODE3", - "DSP_0_INMODE4", - "DSP_0_MULTSIGNIN", - "DSP_0_MULTSIGNOUT", - "DSP_0_OPMODE0", - "DSP_0_OPMODE1", - "DSP_0_OPMODE2", - "DSP_0_OPMODE3", - "DSP_0_OPMODE4", - "DSP_0_OPMODE5", - "DSP_0_OPMODE6", - "DSP_0_OVERFLOW", - "DSP_0_P0", - "DSP_0_P1", - "DSP_0_P10", - "DSP_0_P11", - "DSP_0_P12", - "DSP_0_P13", - "DSP_0_P14", - "DSP_0_P15", - "DSP_0_P16", - "DSP_0_P17", - "DSP_0_P18", - "DSP_0_P19", - "DSP_0_P2", - "DSP_0_P20", - "DSP_0_P21", - "DSP_0_P22", - "DSP_0_P23", - "DSP_0_P24", - "DSP_0_P25", - "DSP_0_P26", - "DSP_0_P27", - "DSP_0_P28", - "DSP_0_P29", - "DSP_0_P3", - "DSP_0_P30", - "DSP_0_P31", - "DSP_0_P32", - "DSP_0_P33", - "DSP_0_P34", - "DSP_0_P35", - "DSP_0_P36", - "DSP_0_P37", - "DSP_0_P38", - "DSP_0_P39", - "DSP_0_P4", - "DSP_0_P40", - "DSP_0_P41", - "DSP_0_P42", - "DSP_0_P43", - "DSP_0_P44", - "DSP_0_P45", - "DSP_0_P46", - "DSP_0_P47", - "DSP_0_P5", - "DSP_0_P6", - "DSP_0_P7", - "DSP_0_P8", - "DSP_0_P9", - "DSP_0_PATTERNBDETECT", - "DSP_0_PATTERNDETECT", - "DSP_0_PCIN0", - "DSP_0_PCIN1", - "DSP_0_PCIN10", - "DSP_0_PCIN11", - "DSP_0_PCIN12", - "DSP_0_PCIN13", - "DSP_0_PCIN14", - "DSP_0_PCIN15", - "DSP_0_PCIN16", - "DSP_0_PCIN17", - "DSP_0_PCIN18", - "DSP_0_PCIN19", - "DSP_0_PCIN2", - "DSP_0_PCIN20", - "DSP_0_PCIN21", - "DSP_0_PCIN22", - "DSP_0_PCIN23", - "DSP_0_PCIN24", - "DSP_0_PCIN25", - "DSP_0_PCIN26", - "DSP_0_PCIN27", - "DSP_0_PCIN28", - "DSP_0_PCIN29", - "DSP_0_PCIN3", - "DSP_0_PCIN30", - "DSP_0_PCIN31", - "DSP_0_PCIN32", - "DSP_0_PCIN33", - "DSP_0_PCIN34", - "DSP_0_PCIN35", - "DSP_0_PCIN36", - "DSP_0_PCIN37", - "DSP_0_PCIN38", - "DSP_0_PCIN39", - "DSP_0_PCIN4", - "DSP_0_PCIN40", - "DSP_0_PCIN41", - "DSP_0_PCIN42", - "DSP_0_PCIN43", - "DSP_0_PCIN44", - "DSP_0_PCIN45", - "DSP_0_PCIN46", - "DSP_0_PCIN47", - "DSP_0_PCIN5", - "DSP_0_PCIN6", - "DSP_0_PCIN7", - "DSP_0_PCIN8", - "DSP_0_PCIN9", - "DSP_0_PCOUT0", - "DSP_0_PCOUT1", - "DSP_0_PCOUT10", - "DSP_0_PCOUT11", - "DSP_0_PCOUT12", - "DSP_0_PCOUT13", - "DSP_0_PCOUT14", - "DSP_0_PCOUT15", - "DSP_0_PCOUT16", - "DSP_0_PCOUT17", - "DSP_0_PCOUT18", - "DSP_0_PCOUT19", - "DSP_0_PCOUT2", - "DSP_0_PCOUT20", - "DSP_0_PCOUT21", - "DSP_0_PCOUT22", - "DSP_0_PCOUT23", - "DSP_0_PCOUT24", - "DSP_0_PCOUT25", - "DSP_0_PCOUT26", - "DSP_0_PCOUT27", - "DSP_0_PCOUT28", - "DSP_0_PCOUT29", - "DSP_0_PCOUT3", - "DSP_0_PCOUT30", - "DSP_0_PCOUT31", - "DSP_0_PCOUT32", - "DSP_0_PCOUT33", - "DSP_0_PCOUT34", - "DSP_0_PCOUT35", - "DSP_0_PCOUT36", - "DSP_0_PCOUT37", - "DSP_0_PCOUT38", - "DSP_0_PCOUT39", - "DSP_0_PCOUT4", - "DSP_0_PCOUT40", - "DSP_0_PCOUT41", - "DSP_0_PCOUT42", - "DSP_0_PCOUT43", - "DSP_0_PCOUT44", - "DSP_0_PCOUT45", - "DSP_0_PCOUT46", - "DSP_0_PCOUT47", - "DSP_0_PCOUT5", - "DSP_0_PCOUT6", - "DSP_0_PCOUT7", - "DSP_0_PCOUT8", - "DSP_0_PCOUT9", - "DSP_0_RSTA", - "DSP_0_RSTALLCARRYIN", - "DSP_0_RSTALUMODE", - "DSP_0_RSTB", - "DSP_0_RSTC", - "DSP_0_RSTCTRL", - "DSP_0_RSTD", - "DSP_0_RSTINMODE", - "DSP_0_RSTM", - "DSP_0_RSTP", - "DSP_0_UNDERFLOW", - "DSP_1_A0", - "DSP_1_A1", - "DSP_1_A10", - "DSP_1_A11", - "DSP_1_A12", - "DSP_1_A13", - "DSP_1_A14", - "DSP_1_A15", - "DSP_1_A16", - "DSP_1_A17", - "DSP_1_A18", - "DSP_1_A19", - "DSP_1_A2", - "DSP_1_A20", - "DSP_1_A21", - "DSP_1_A22", - "DSP_1_A23", - "DSP_1_A24", - "DSP_1_A25", - "DSP_1_A26", - "DSP_1_A27", - "DSP_1_A28", - "DSP_1_A29", - "DSP_1_A3", - "DSP_1_A4", - "DSP_1_A5", - "DSP_1_A6", - "DSP_1_A7", - "DSP_1_A8", - "DSP_1_A9", - "DSP_1_ACIN0", - "DSP_1_ACIN1", - "DSP_1_ACIN10", - "DSP_1_ACIN11", - "DSP_1_ACIN12", - "DSP_1_ACIN13", - "DSP_1_ACIN14", - "DSP_1_ACIN15", - "DSP_1_ACIN16", - "DSP_1_ACIN17", - "DSP_1_ACIN18", - "DSP_1_ACIN19", - "DSP_1_ACIN2", - "DSP_1_ACIN20", - "DSP_1_ACIN21", - "DSP_1_ACIN22", - "DSP_1_ACIN23", - "DSP_1_ACIN24", - "DSP_1_ACIN25", - "DSP_1_ACIN26", - "DSP_1_ACIN27", - "DSP_1_ACIN28", - "DSP_1_ACIN29", - "DSP_1_ACIN3", - "DSP_1_ACIN4", - "DSP_1_ACIN5", - "DSP_1_ACIN6", - "DSP_1_ACIN7", - "DSP_1_ACIN8", - "DSP_1_ACIN9", - "DSP_1_ACOUT0", - "DSP_1_ACOUT1", - "DSP_1_ACOUT10", - "DSP_1_ACOUT11", - "DSP_1_ACOUT12", - "DSP_1_ACOUT13", - "DSP_1_ACOUT14", - "DSP_1_ACOUT15", - "DSP_1_ACOUT16", - "DSP_1_ACOUT17", - "DSP_1_ACOUT18", - "DSP_1_ACOUT19", - "DSP_1_ACOUT2", - "DSP_1_ACOUT20", - "DSP_1_ACOUT21", - "DSP_1_ACOUT22", - "DSP_1_ACOUT23", - "DSP_1_ACOUT24", - "DSP_1_ACOUT25", - "DSP_1_ACOUT26", - "DSP_1_ACOUT27", - "DSP_1_ACOUT28", - "DSP_1_ACOUT29", - "DSP_1_ACOUT3", - "DSP_1_ACOUT4", - "DSP_1_ACOUT5", - "DSP_1_ACOUT6", - "DSP_1_ACOUT7", - "DSP_1_ACOUT8", - "DSP_1_ACOUT9", - "DSP_1_ALUMODE0", - "DSP_1_ALUMODE1", - "DSP_1_ALUMODE2", - "DSP_1_ALUMODE3", - "DSP_1_B0", - "DSP_1_B1", - "DSP_1_B10", - "DSP_1_B11", - "DSP_1_B12", - "DSP_1_B13", - "DSP_1_B14", - "DSP_1_B15", - "DSP_1_B16", - "DSP_1_B17", - "DSP_1_B2", - "DSP_1_B3", - "DSP_1_B4", - "DSP_1_B5", - "DSP_1_B6", - "DSP_1_B7", - "DSP_1_B8", - "DSP_1_B9", - "DSP_1_BCIN0", - "DSP_1_BCIN1", - "DSP_1_BCIN10", - "DSP_1_BCIN11", - "DSP_1_BCIN12", - "DSP_1_BCIN13", - "DSP_1_BCIN14", - "DSP_1_BCIN15", - "DSP_1_BCIN16", - "DSP_1_BCIN17", - "DSP_1_BCIN2", - "DSP_1_BCIN3", - "DSP_1_BCIN4", - "DSP_1_BCIN5", - "DSP_1_BCIN6", - "DSP_1_BCIN7", - "DSP_1_BCIN8", - "DSP_1_BCIN9", - "DSP_1_BCOUT0", - "DSP_1_BCOUT1", - "DSP_1_BCOUT10", - "DSP_1_BCOUT11", - "DSP_1_BCOUT12", - "DSP_1_BCOUT13", - "DSP_1_BCOUT14", - "DSP_1_BCOUT15", - "DSP_1_BCOUT16", - "DSP_1_BCOUT17", - "DSP_1_BCOUT2", - "DSP_1_BCOUT3", - "DSP_1_BCOUT4", - "DSP_1_BCOUT5", - "DSP_1_BCOUT6", - "DSP_1_BCOUT7", - "DSP_1_BCOUT8", - "DSP_1_BCOUT9", - "DSP_1_C0", - "DSP_1_C1", - "DSP_1_C10", - "DSP_1_C11", - "DSP_1_C12", - "DSP_1_C13", - "DSP_1_C14", - "DSP_1_C15", - "DSP_1_C16", - "DSP_1_C17", - "DSP_1_C18", - "DSP_1_C19", - "DSP_1_C2", - "DSP_1_C20", - "DSP_1_C21", - "DSP_1_C22", - "DSP_1_C23", - "DSP_1_C24", - "DSP_1_C25", - "DSP_1_C26", - "DSP_1_C27", - "DSP_1_C28", - "DSP_1_C29", - "DSP_1_C3", - "DSP_1_C30", - "DSP_1_C31", - "DSP_1_C32", - "DSP_1_C33", - "DSP_1_C34", - "DSP_1_C35", - "DSP_1_C36", - "DSP_1_C37", - "DSP_1_C38", - "DSP_1_C39", - "DSP_1_C4", - "DSP_1_C40", - "DSP_1_C41", - "DSP_1_C42", - "DSP_1_C43", - "DSP_1_C44", - "DSP_1_C45", - "DSP_1_C46", - "DSP_1_C47", - "DSP_1_C5", - "DSP_1_C6", - "DSP_1_C7", - "DSP_1_C8", - "DSP_1_C9", - "DSP_1_CARRYCASCIN", - "DSP_1_CARRYCASCOUT", - "DSP_1_CARRYIN", - "DSP_1_CARRYINSEL0", - "DSP_1_CARRYINSEL1", - "DSP_1_CARRYINSEL2", - "DSP_1_CARRYOUT0", - "DSP_1_CARRYOUT1", - "DSP_1_CARRYOUT2", - "DSP_1_CARRYOUT3", - "DSP_1_CEA1", - "DSP_1_CEA2", - "DSP_1_CEAD", - "DSP_1_CEALUMODE", - "DSP_1_CEB1", - "DSP_1_CEB2", - "DSP_1_CEC", - "DSP_1_CECARRYIN", - "DSP_1_CECTRL", - "DSP_1_CED", - "DSP_1_CEINMODE", - "DSP_1_CEM", - "DSP_1_CEP", - "DSP_1_CLK", - "DSP_1_D0", - "DSP_1_D1", - "DSP_1_D10", - "DSP_1_D11", - "DSP_1_D12", - "DSP_1_D13", - "DSP_1_D14", - "DSP_1_D15", - "DSP_1_D16", - "DSP_1_D17", - "DSP_1_D18", - "DSP_1_D19", - "DSP_1_D2", - "DSP_1_D20", - "DSP_1_D21", - "DSP_1_D22", - "DSP_1_D23", - "DSP_1_D24", - "DSP_1_D3", - "DSP_1_D4", - "DSP_1_D5", - "DSP_1_D6", - "DSP_1_D7", - "DSP_1_D8", - "DSP_1_D9", - "DSP_1_INMODE0", - "DSP_1_INMODE1", - "DSP_1_INMODE2", - "DSP_1_INMODE3", - "DSP_1_INMODE4", - "DSP_1_MULTSIGNIN", - "DSP_1_MULTSIGNOUT", - "DSP_1_OPMODE0", - "DSP_1_OPMODE1", - "DSP_1_OPMODE2", - "DSP_1_OPMODE3", - "DSP_1_OPMODE4", - "DSP_1_OPMODE5", - "DSP_1_OPMODE6", - "DSP_1_OVERFLOW", - "DSP_1_P0", - "DSP_1_P1", - "DSP_1_P10", - "DSP_1_P11", - "DSP_1_P12", - "DSP_1_P13", - "DSP_1_P14", - "DSP_1_P15", - "DSP_1_P16", - "DSP_1_P17", - "DSP_1_P18", - "DSP_1_P19", - "DSP_1_P2", - "DSP_1_P20", - "DSP_1_P21", - "DSP_1_P22", - "DSP_1_P23", - "DSP_1_P24", - "DSP_1_P25", - "DSP_1_P26", - "DSP_1_P27", - "DSP_1_P28", - "DSP_1_P29", - "DSP_1_P3", - "DSP_1_P30", - "DSP_1_P31", - "DSP_1_P32", - "DSP_1_P33", - "DSP_1_P34", - "DSP_1_P35", - "DSP_1_P36", - "DSP_1_P37", - "DSP_1_P38", - "DSP_1_P39", - "DSP_1_P4", - "DSP_1_P40", - "DSP_1_P41", - "DSP_1_P42", - "DSP_1_P43", - "DSP_1_P44", - "DSP_1_P45", - "DSP_1_P46", - "DSP_1_P47", - "DSP_1_P5", - "DSP_1_P6", - "DSP_1_P7", - "DSP_1_P8", - "DSP_1_P9", - "DSP_1_PATTERNBDETECT", - "DSP_1_PATTERNDETECT", - "DSP_1_PCIN0", - "DSP_1_PCIN1", - "DSP_1_PCIN10", - "DSP_1_PCIN11", - "DSP_1_PCIN12", - "DSP_1_PCIN13", - "DSP_1_PCIN14", - "DSP_1_PCIN15", - "DSP_1_PCIN16", - "DSP_1_PCIN17", - "DSP_1_PCIN18", - "DSP_1_PCIN19", - "DSP_1_PCIN2", - "DSP_1_PCIN20", - "DSP_1_PCIN21", - "DSP_1_PCIN22", - "DSP_1_PCIN23", - "DSP_1_PCIN24", - "DSP_1_PCIN25", - "DSP_1_PCIN26", - "DSP_1_PCIN27", - "DSP_1_PCIN28", - "DSP_1_PCIN29", - "DSP_1_PCIN3", - "DSP_1_PCIN30", - "DSP_1_PCIN31", - "DSP_1_PCIN32", - "DSP_1_PCIN33", - "DSP_1_PCIN34", - "DSP_1_PCIN35", - "DSP_1_PCIN36", - "DSP_1_PCIN37", - "DSP_1_PCIN38", - "DSP_1_PCIN39", - "DSP_1_PCIN4", - "DSP_1_PCIN40", - "DSP_1_PCIN41", - "DSP_1_PCIN42", - "DSP_1_PCIN43", - "DSP_1_PCIN44", - "DSP_1_PCIN45", - "DSP_1_PCIN46", - "DSP_1_PCIN47", - "DSP_1_PCIN5", - "DSP_1_PCIN6", - "DSP_1_PCIN7", - "DSP_1_PCIN8", - "DSP_1_PCIN9", - "DSP_1_PCOUT0", - "DSP_1_PCOUT1", - "DSP_1_PCOUT10", - "DSP_1_PCOUT11", - "DSP_1_PCOUT12", - "DSP_1_PCOUT13", - "DSP_1_PCOUT14", - "DSP_1_PCOUT15", - "DSP_1_PCOUT16", - "DSP_1_PCOUT17", - "DSP_1_PCOUT18", - "DSP_1_PCOUT19", - "DSP_1_PCOUT2", - "DSP_1_PCOUT20", - "DSP_1_PCOUT21", - "DSP_1_PCOUT22", - "DSP_1_PCOUT23", - "DSP_1_PCOUT24", - "DSP_1_PCOUT25", - "DSP_1_PCOUT26", - "DSP_1_PCOUT27", - "DSP_1_PCOUT28", - "DSP_1_PCOUT29", - "DSP_1_PCOUT3", - "DSP_1_PCOUT30", - "DSP_1_PCOUT31", - "DSP_1_PCOUT32", - "DSP_1_PCOUT33", - "DSP_1_PCOUT34", - "DSP_1_PCOUT35", - "DSP_1_PCOUT36", - "DSP_1_PCOUT37", - "DSP_1_PCOUT38", - "DSP_1_PCOUT39", - "DSP_1_PCOUT4", - "DSP_1_PCOUT40", - "DSP_1_PCOUT41", - "DSP_1_PCOUT42", - "DSP_1_PCOUT43", - "DSP_1_PCOUT44", - "DSP_1_PCOUT45", - "DSP_1_PCOUT46", - "DSP_1_PCOUT47", - "DSP_1_PCOUT5", - "DSP_1_PCOUT6", - "DSP_1_PCOUT7", - "DSP_1_PCOUT8", - "DSP_1_PCOUT9", - "DSP_1_RSTA", - "DSP_1_RSTALLCARRYIN", - "DSP_1_RSTALUMODE", - "DSP_1_RSTB", - "DSP_1_RSTC", - "DSP_1_RSTCTRL", - "DSP_1_RSTD", - "DSP_1_RSTINMODE", - "DSP_1_RSTM", - "DSP_1_RSTP", - "DSP_1_UNDERFLOW", - "DSP_ACOUT0", - "DSP_ACOUT1", - "DSP_ACOUT10", - "DSP_ACOUT11", - "DSP_ACOUT12", - "DSP_ACOUT13", - "DSP_ACOUT14", - "DSP_ACOUT15", - "DSP_ACOUT16", - "DSP_ACOUT17", - "DSP_ACOUT18", - "DSP_ACOUT19", - "DSP_ACOUT2", - "DSP_ACOUT20", - "DSP_ACOUT21", - "DSP_ACOUT22", - "DSP_ACOUT23", - "DSP_ACOUT24", - "DSP_ACOUT25", - "DSP_ACOUT26", - "DSP_ACOUT27", - "DSP_ACOUT28", - "DSP_ACOUT29", - "DSP_ACOUT3", - "DSP_ACOUT4", - "DSP_ACOUT5", - "DSP_ACOUT6", - "DSP_ACOUT7", - "DSP_ACOUT8", - "DSP_ACOUT9", - "DSP_BCOUT0", - "DSP_BCOUT1", - "DSP_BCOUT10", - "DSP_BCOUT11", - "DSP_BCOUT12", - "DSP_BCOUT13", - "DSP_BCOUT14", - "DSP_BCOUT15", - "DSP_BCOUT16", - "DSP_BCOUT17", - "DSP_BCOUT2", - "DSP_BCOUT3", - "DSP_BCOUT4", - "DSP_BCOUT5", - "DSP_BCOUT6", - "DSP_BCOUT7", - "DSP_BCOUT8", - "DSP_BCOUT9", - "DSP_BLOCK_OUTS_B0_0", - "DSP_BLOCK_OUTS_B0_1", - "DSP_BLOCK_OUTS_B0_2", - "DSP_BLOCK_OUTS_B0_3", - "DSP_BLOCK_OUTS_B0_4", - "DSP_BLOCK_OUTS_B1_0", - "DSP_BLOCK_OUTS_B1_1", - "DSP_BLOCK_OUTS_B1_2", - "DSP_BLOCK_OUTS_B1_3", - "DSP_BLOCK_OUTS_B1_4", - "DSP_BLOCK_OUTS_B2_0", - "DSP_BLOCK_OUTS_B2_1", - "DSP_BLOCK_OUTS_B2_2", - "DSP_BLOCK_OUTS_B2_3", - "DSP_BLOCK_OUTS_B2_4", - "DSP_BLOCK_OUTS_B3_0", - "DSP_BLOCK_OUTS_B3_1", - "DSP_BLOCK_OUTS_B3_2", - "DSP_BLOCK_OUTS_B3_3", - "DSP_BLOCK_OUTS_B3_4", - "DSP_BYP0_0", - "DSP_BYP0_1", - "DSP_BYP0_2", - "DSP_BYP0_3", - "DSP_BYP0_4", - "DSP_BYP1_0", - "DSP_BYP1_1", - "DSP_BYP1_2", - "DSP_BYP1_3", - "DSP_BYP1_4", - "DSP_BYP2_0", - "DSP_BYP2_1", - "DSP_BYP2_2", - "DSP_BYP2_3", - "DSP_BYP2_4", - "DSP_BYP3_0", - "DSP_BYP3_1", - "DSP_BYP3_2", - "DSP_BYP3_3", - "DSP_BYP3_4", - "DSP_BYP4_0", - "DSP_BYP4_1", - "DSP_BYP4_2", - "DSP_BYP4_3", - "DSP_BYP4_4", - "DSP_BYP5_0", - "DSP_BYP5_1", - "DSP_BYP5_2", - "DSP_BYP5_3", - "DSP_BYP5_4", - "DSP_BYP6_0", - "DSP_BYP6_1", - "DSP_BYP6_2", - "DSP_BYP6_3", - "DSP_BYP6_4", - "DSP_BYP7_0", - "DSP_BYP7_1", - "DSP_BYP7_2", - "DSP_BYP7_3", - "DSP_BYP7_4", - "DSP_CARRYCASCOUT", - "DSP_CLK0_0", - "DSP_CLK0_1", - "DSP_CLK0_2", - "DSP_CLK0_3", - "DSP_CLK0_4", - "DSP_CLK1_0", - "DSP_CLK1_1", - "DSP_CLK1_2", - "DSP_CLK1_3", - "DSP_CLK1_4", - "DSP_CTRL0_0", - "DSP_CTRL0_1", - "DSP_CTRL0_2", - "DSP_CTRL0_3", - "DSP_CTRL0_4", - "DSP_CTRL1_0", - "DSP_CTRL1_1", - "DSP_CTRL1_2", - "DSP_CTRL1_3", - "DSP_CTRL1_4", - "DSP_EE2A0_0", - "DSP_EE2A0_1", - "DSP_EE2A0_2", - "DSP_EE2A0_3", - "DSP_EE2A0_4", - "DSP_EE2A1_0", - "DSP_EE2A1_1", - "DSP_EE2A1_2", - "DSP_EE2A1_3", - "DSP_EE2A1_4", - "DSP_EE2A2_0", - "DSP_EE2A2_1", - "DSP_EE2A2_2", - "DSP_EE2A2_3", - "DSP_EE2A2_4", - "DSP_EE2A3_0", - "DSP_EE2A3_1", - "DSP_EE2A3_2", - "DSP_EE2A3_3", - "DSP_EE2A3_4", - "DSP_EE2BEG0_0", - "DSP_EE2BEG0_1", - "DSP_EE2BEG0_2", - "DSP_EE2BEG0_3", - "DSP_EE2BEG0_4", - "DSP_EE2BEG1_0", - "DSP_EE2BEG1_1", - "DSP_EE2BEG1_2", - "DSP_EE2BEG1_3", - "DSP_EE2BEG1_4", - "DSP_EE2BEG2_0", - "DSP_EE2BEG2_1", - "DSP_EE2BEG2_2", - "DSP_EE2BEG2_3", - "DSP_EE2BEG2_4", - "DSP_EE2BEG3_0", - "DSP_EE2BEG3_1", - "DSP_EE2BEG3_2", - "DSP_EE2BEG3_3", - "DSP_EE2BEG3_4", - "DSP_EE4A0_0", - "DSP_EE4A0_1", - "DSP_EE4A0_2", - "DSP_EE4A0_3", - "DSP_EE4A0_4", - "DSP_EE4A1_0", - "DSP_EE4A1_1", - "DSP_EE4A1_2", - "DSP_EE4A1_3", - "DSP_EE4A1_4", - "DSP_EE4A2_0", - "DSP_EE4A2_1", - "DSP_EE4A2_2", - "DSP_EE4A2_3", - "DSP_EE4A2_4", - "DSP_EE4A3_0", - "DSP_EE4A3_1", - "DSP_EE4A3_2", - "DSP_EE4A3_3", - "DSP_EE4A3_4", - "DSP_EE4B0_0", - "DSP_EE4B0_1", - "DSP_EE4B0_2", - "DSP_EE4B0_3", - "DSP_EE4B0_4", - "DSP_EE4B1_0", - "DSP_EE4B1_1", - "DSP_EE4B1_2", - "DSP_EE4B1_3", - "DSP_EE4B1_4", - "DSP_EE4B2_0", - "DSP_EE4B2_1", - "DSP_EE4B2_2", - "DSP_EE4B2_3", - "DSP_EE4B2_4", - "DSP_EE4B3_0", - "DSP_EE4B3_1", - "DSP_EE4B3_2", - "DSP_EE4B3_3", - "DSP_EE4B3_4", - "DSP_EE4BEG0_0", - "DSP_EE4BEG0_1", - "DSP_EE4BEG0_2", - "DSP_EE4BEG0_3", - "DSP_EE4BEG0_4", - "DSP_EE4BEG1_0", - "DSP_EE4BEG1_1", - "DSP_EE4BEG1_2", - "DSP_EE4BEG1_3", - "DSP_EE4BEG1_4", - "DSP_EE4BEG2_0", - "DSP_EE4BEG2_1", - "DSP_EE4BEG2_2", - "DSP_EE4BEG2_3", - "DSP_EE4BEG2_4", - "DSP_EE4BEG3_0", - "DSP_EE4BEG3_1", - "DSP_EE4BEG3_2", - "DSP_EE4BEG3_3", - "DSP_EE4BEG3_4", - "DSP_EE4C0_0", - "DSP_EE4C0_1", - "DSP_EE4C0_2", - "DSP_EE4C0_3", - "DSP_EE4C0_4", - "DSP_EE4C1_0", - "DSP_EE4C1_1", - "DSP_EE4C1_2", - "DSP_EE4C1_3", - "DSP_EE4C1_4", - "DSP_EE4C2_0", - "DSP_EE4C2_1", - "DSP_EE4C2_2", - "DSP_EE4C2_3", - "DSP_EE4C2_4", - "DSP_EE4C3_0", - "DSP_EE4C3_1", - "DSP_EE4C3_2", - "DSP_EE4C3_3", - "DSP_EE4C3_4", - "DSP_EL1BEG0_0", - "DSP_EL1BEG0_1", - "DSP_EL1BEG0_2", - "DSP_EL1BEG0_3", - "DSP_EL1BEG0_4", - "DSP_EL1BEG1_0", - "DSP_EL1BEG1_1", - "DSP_EL1BEG1_2", - "DSP_EL1BEG1_3", - "DSP_EL1BEG1_4", - "DSP_EL1BEG2_0", - "DSP_EL1BEG2_1", - "DSP_EL1BEG2_2", - "DSP_EL1BEG2_3", - "DSP_EL1BEG2_4", - "DSP_EL1BEG3_0", - "DSP_EL1BEG3_1", - "DSP_EL1BEG3_2", - "DSP_EL1BEG3_3", - "DSP_EL1BEG3_4", - "DSP_ER1BEG0_0", - "DSP_ER1BEG0_1", - "DSP_ER1BEG0_2", - "DSP_ER1BEG0_3", - "DSP_ER1BEG0_4", - "DSP_ER1BEG1_0", - "DSP_ER1BEG1_1", - "DSP_ER1BEG1_2", - "DSP_ER1BEG1_3", - "DSP_ER1BEG1_4", - "DSP_ER1BEG2_0", - "DSP_ER1BEG2_1", - "DSP_ER1BEG2_2", - "DSP_ER1BEG2_3", - "DSP_ER1BEG2_4", - "DSP_ER1BEG3_0", - "DSP_ER1BEG3_1", - "DSP_ER1BEG3_2", - "DSP_ER1BEG3_3", - "DSP_ER1BEG3_4", - "DSP_FAN0_0", - "DSP_FAN0_1", - "DSP_FAN0_2", - "DSP_FAN0_3", - "DSP_FAN0_4", - "DSP_FAN1_0", - "DSP_FAN1_1", - "DSP_FAN1_2", - "DSP_FAN1_3", - "DSP_FAN1_4", - "DSP_FAN2_0", - "DSP_FAN2_1", - "DSP_FAN2_2", - "DSP_FAN2_3", - "DSP_FAN2_4", - "DSP_FAN3_0", - "DSP_FAN3_1", - "DSP_FAN3_2", - "DSP_FAN3_3", - "DSP_FAN3_4", - "DSP_FAN4_0", - "DSP_FAN4_1", - "DSP_FAN4_2", - "DSP_FAN4_3", - "DSP_FAN4_4", - "DSP_FAN5_0", - "DSP_FAN5_1", - "DSP_FAN5_2", - "DSP_FAN5_3", - "DSP_FAN5_4", - "DSP_FAN6_0", - "DSP_FAN6_1", - "DSP_FAN6_2", - "DSP_FAN6_3", - "DSP_FAN6_4", - "DSP_FAN7_0", - "DSP_FAN7_1", - "DSP_FAN7_2", - "DSP_FAN7_3", - "DSP_FAN7_4", - "DSP_GND_R", - "DSP_IMUX0_0", - "DSP_IMUX0_1", - "DSP_IMUX0_2", - "DSP_IMUX0_3", - "DSP_IMUX0_4", - "DSP_IMUX10_0", - "DSP_IMUX10_1", - "DSP_IMUX10_2", - "DSP_IMUX10_3", - "DSP_IMUX10_4", - "DSP_IMUX11_0", - "DSP_IMUX11_1", - "DSP_IMUX11_2", - "DSP_IMUX11_3", - "DSP_IMUX11_4", - "DSP_IMUX12_0", - "DSP_IMUX12_1", - "DSP_IMUX12_2", - "DSP_IMUX12_3", - "DSP_IMUX12_4", - "DSP_IMUX13_0", - "DSP_IMUX13_1", - "DSP_IMUX13_2", - "DSP_IMUX13_3", - "DSP_IMUX13_4", - "DSP_IMUX14_0", - "DSP_IMUX14_1", - "DSP_IMUX14_2", - "DSP_IMUX14_3", - "DSP_IMUX14_4", - "DSP_IMUX15_0", - "DSP_IMUX15_1", - "DSP_IMUX15_2", - "DSP_IMUX15_3", - "DSP_IMUX15_4", - "DSP_IMUX16_0", - "DSP_IMUX16_1", - "DSP_IMUX16_2", - "DSP_IMUX16_3", - "DSP_IMUX16_4", - "DSP_IMUX17_0", - "DSP_IMUX17_1", - "DSP_IMUX17_2", - "DSP_IMUX17_3", - "DSP_IMUX17_4", - "DSP_IMUX18_0", - "DSP_IMUX18_1", - "DSP_IMUX18_2", - "DSP_IMUX18_3", - "DSP_IMUX18_4", - "DSP_IMUX19_0", - "DSP_IMUX19_1", - "DSP_IMUX19_2", - "DSP_IMUX19_3", - "DSP_IMUX19_4", - "DSP_IMUX1_0", - "DSP_IMUX1_1", - "DSP_IMUX1_2", - "DSP_IMUX1_3", - "DSP_IMUX1_4", - "DSP_IMUX20_0", - "DSP_IMUX20_1", - "DSP_IMUX20_2", - "DSP_IMUX20_3", - "DSP_IMUX20_4", - "DSP_IMUX21_0", - "DSP_IMUX21_1", - "DSP_IMUX21_2", - "DSP_IMUX21_3", - "DSP_IMUX21_4", - "DSP_IMUX22_0", - "DSP_IMUX22_1", - "DSP_IMUX22_2", - "DSP_IMUX22_3", - "DSP_IMUX22_4", - "DSP_IMUX23_0", - "DSP_IMUX23_1", - "DSP_IMUX23_2", - "DSP_IMUX23_3", - "DSP_IMUX23_4", - "DSP_IMUX24_0", - "DSP_IMUX24_1", - "DSP_IMUX24_2", - "DSP_IMUX24_3", - "DSP_IMUX24_4", - "DSP_IMUX25_0", - "DSP_IMUX25_1", - "DSP_IMUX25_2", - "DSP_IMUX25_3", - "DSP_IMUX25_4", - "DSP_IMUX26_0", - "DSP_IMUX26_1", - "DSP_IMUX26_2", - "DSP_IMUX26_3", - "DSP_IMUX26_4", - "DSP_IMUX27_0", - "DSP_IMUX27_1", - "DSP_IMUX27_2", - "DSP_IMUX27_3", - "DSP_IMUX27_4", - "DSP_IMUX28_0", - "DSP_IMUX28_1", - "DSP_IMUX28_2", - "DSP_IMUX28_3", - "DSP_IMUX28_4", - "DSP_IMUX29_0", - "DSP_IMUX29_1", - "DSP_IMUX29_2", - "DSP_IMUX29_3", - "DSP_IMUX29_4", - "DSP_IMUX2_0", - "DSP_IMUX2_1", - "DSP_IMUX2_2", - "DSP_IMUX2_3", - "DSP_IMUX2_4", - "DSP_IMUX30_0", - "DSP_IMUX30_1", - "DSP_IMUX30_2", - "DSP_IMUX30_3", - "DSP_IMUX30_4", - "DSP_IMUX31_0", - "DSP_IMUX31_1", - "DSP_IMUX31_2", - "DSP_IMUX31_3", - "DSP_IMUX31_4", - "DSP_IMUX32_0", - "DSP_IMUX32_1", - "DSP_IMUX32_2", - "DSP_IMUX32_3", - "DSP_IMUX32_4", - "DSP_IMUX33_0", - "DSP_IMUX33_1", - "DSP_IMUX33_2", - "DSP_IMUX33_3", - "DSP_IMUX33_4", - "DSP_IMUX34_0", - "DSP_IMUX34_1", - "DSP_IMUX34_2", - "DSP_IMUX34_3", - "DSP_IMUX34_4", - "DSP_IMUX35_0", - "DSP_IMUX35_1", - "DSP_IMUX35_2", - "DSP_IMUX35_3", - "DSP_IMUX35_4", - "DSP_IMUX36_0", - "DSP_IMUX36_1", - "DSP_IMUX36_2", - "DSP_IMUX36_3", - "DSP_IMUX36_4", - "DSP_IMUX37_0", - "DSP_IMUX37_1", - "DSP_IMUX37_2", - "DSP_IMUX37_3", - "DSP_IMUX37_4", - "DSP_IMUX38_0", - "DSP_IMUX38_1", - "DSP_IMUX38_2", - "DSP_IMUX38_3", - "DSP_IMUX38_4", - "DSP_IMUX39_0", - "DSP_IMUX39_1", - "DSP_IMUX39_2", - "DSP_IMUX39_3", - "DSP_IMUX39_4", - "DSP_IMUX3_0", - "DSP_IMUX3_1", - "DSP_IMUX3_2", - "DSP_IMUX3_3", - "DSP_IMUX3_4", - "DSP_IMUX40_0", - "DSP_IMUX40_1", - "DSP_IMUX40_2", - "DSP_IMUX40_3", - "DSP_IMUX40_4", - "DSP_IMUX41_0", - "DSP_IMUX41_1", - "DSP_IMUX41_2", - "DSP_IMUX41_3", - "DSP_IMUX41_4", - "DSP_IMUX42_0", - "DSP_IMUX42_1", - "DSP_IMUX42_2", - "DSP_IMUX42_3", - "DSP_IMUX42_4", - "DSP_IMUX43_0", - "DSP_IMUX43_1", - "DSP_IMUX43_2", - "DSP_IMUX43_3", - "DSP_IMUX43_4", - "DSP_IMUX44_0", - "DSP_IMUX44_1", - "DSP_IMUX44_2", - "DSP_IMUX44_3", - "DSP_IMUX44_4", - "DSP_IMUX45_0", - "DSP_IMUX45_1", - "DSP_IMUX45_2", - "DSP_IMUX45_3", - "DSP_IMUX45_4", - "DSP_IMUX46_0", - "DSP_IMUX46_1", - "DSP_IMUX46_2", - "DSP_IMUX46_3", - "DSP_IMUX46_4", - "DSP_IMUX47_0", - "DSP_IMUX47_1", - "DSP_IMUX47_2", - "DSP_IMUX47_3", - "DSP_IMUX47_4", - "DSP_IMUX4_0", - "DSP_IMUX4_1", - "DSP_IMUX4_2", - "DSP_IMUX4_3", - "DSP_IMUX4_4", - "DSP_IMUX5_0", - "DSP_IMUX5_1", - "DSP_IMUX5_2", - "DSP_IMUX5_3", - "DSP_IMUX5_4", - "DSP_IMUX6_0", - "DSP_IMUX6_1", - "DSP_IMUX6_2", - "DSP_IMUX6_3", - "DSP_IMUX6_4", - "DSP_IMUX7_0", - "DSP_IMUX7_1", - "DSP_IMUX7_2", - "DSP_IMUX7_3", - "DSP_IMUX7_4", - "DSP_IMUX8_0", - "DSP_IMUX8_1", - "DSP_IMUX8_2", - "DSP_IMUX8_3", - "DSP_IMUX8_4", - "DSP_IMUX9_0", - "DSP_IMUX9_1", - "DSP_IMUX9_2", - "DSP_IMUX9_3", - "DSP_IMUX9_4", - "DSP_LH10_0", - "DSP_LH10_1", - "DSP_LH10_2", - "DSP_LH10_3", - "DSP_LH10_4", - "DSP_LH11_0", - "DSP_LH11_1", - "DSP_LH11_2", - "DSP_LH11_3", - "DSP_LH11_4", - "DSP_LH12_0", - "DSP_LH12_1", - "DSP_LH12_2", - "DSP_LH12_3", - "DSP_LH12_4", - "DSP_LH1_0", - "DSP_LH1_1", - "DSP_LH1_2", - "DSP_LH1_3", - "DSP_LH1_4", - "DSP_LH2_0", - "DSP_LH2_1", - "DSP_LH2_2", - "DSP_LH2_3", - "DSP_LH2_4", - "DSP_LH3_0", - "DSP_LH3_1", - "DSP_LH3_2", - "DSP_LH3_3", - "DSP_LH3_4", - "DSP_LH4_0", - "DSP_LH4_1", - "DSP_LH4_2", - "DSP_LH4_3", - "DSP_LH4_4", - "DSP_LH5_0", - "DSP_LH5_1", - "DSP_LH5_2", - "DSP_LH5_3", - "DSP_LH5_4", - "DSP_LH6_0", - "DSP_LH6_1", - "DSP_LH6_2", - "DSP_LH6_3", - "DSP_LH6_4", - "DSP_LH7_0", - "DSP_LH7_1", - "DSP_LH7_2", - "DSP_LH7_3", - "DSP_LH7_4", - "DSP_LH8_0", - "DSP_LH8_1", - "DSP_LH8_2", - "DSP_LH8_3", - "DSP_LH8_4", - "DSP_LH9_0", - "DSP_LH9_1", - "DSP_LH9_2", - "DSP_LH9_3", - "DSP_LH9_4", - "DSP_LOGIC_OUTS_B0_0", - "DSP_LOGIC_OUTS_B0_1", - "DSP_LOGIC_OUTS_B0_2", - "DSP_LOGIC_OUTS_B0_3", - "DSP_LOGIC_OUTS_B0_4", - "DSP_LOGIC_OUTS_B10_0", - "DSP_LOGIC_OUTS_B10_1", - "DSP_LOGIC_OUTS_B10_2", - "DSP_LOGIC_OUTS_B10_3", - "DSP_LOGIC_OUTS_B10_4", - "DSP_LOGIC_OUTS_B11_0", - "DSP_LOGIC_OUTS_B11_1", - "DSP_LOGIC_OUTS_B11_2", - "DSP_LOGIC_OUTS_B11_3", - "DSP_LOGIC_OUTS_B11_4", - "DSP_LOGIC_OUTS_B12_0", - "DSP_LOGIC_OUTS_B12_1", - "DSP_LOGIC_OUTS_B12_2", - "DSP_LOGIC_OUTS_B12_3", - "DSP_LOGIC_OUTS_B12_4", - "DSP_LOGIC_OUTS_B13_0", - "DSP_LOGIC_OUTS_B13_1", - "DSP_LOGIC_OUTS_B13_2", - "DSP_LOGIC_OUTS_B13_3", - "DSP_LOGIC_OUTS_B13_4", - "DSP_LOGIC_OUTS_B14_0", - "DSP_LOGIC_OUTS_B14_1", - "DSP_LOGIC_OUTS_B14_2", - "DSP_LOGIC_OUTS_B14_3", - "DSP_LOGIC_OUTS_B14_4", - "DSP_LOGIC_OUTS_B15_0", - "DSP_LOGIC_OUTS_B15_1", - "DSP_LOGIC_OUTS_B15_2", - "DSP_LOGIC_OUTS_B15_3", - "DSP_LOGIC_OUTS_B15_4", - "DSP_LOGIC_OUTS_B16_0", - "DSP_LOGIC_OUTS_B16_1", - "DSP_LOGIC_OUTS_B16_2", - "DSP_LOGIC_OUTS_B16_3", - "DSP_LOGIC_OUTS_B16_4", - "DSP_LOGIC_OUTS_B17_0", - "DSP_LOGIC_OUTS_B17_1", - "DSP_LOGIC_OUTS_B17_2", - "DSP_LOGIC_OUTS_B17_3", - "DSP_LOGIC_OUTS_B17_4", - "DSP_LOGIC_OUTS_B18_0", - "DSP_LOGIC_OUTS_B18_1", - "DSP_LOGIC_OUTS_B18_2", - "DSP_LOGIC_OUTS_B18_3", - "DSP_LOGIC_OUTS_B18_4", - "DSP_LOGIC_OUTS_B19_0", - "DSP_LOGIC_OUTS_B19_1", - "DSP_LOGIC_OUTS_B19_2", - "DSP_LOGIC_OUTS_B19_3", - "DSP_LOGIC_OUTS_B19_4", - "DSP_LOGIC_OUTS_B1_0", - "DSP_LOGIC_OUTS_B1_1", - "DSP_LOGIC_OUTS_B1_2", - "DSP_LOGIC_OUTS_B1_3", - "DSP_LOGIC_OUTS_B1_4", - "DSP_LOGIC_OUTS_B20_0", - "DSP_LOGIC_OUTS_B20_1", - "DSP_LOGIC_OUTS_B20_2", - "DSP_LOGIC_OUTS_B20_3", - "DSP_LOGIC_OUTS_B20_4", - "DSP_LOGIC_OUTS_B21_0", - "DSP_LOGIC_OUTS_B21_1", - "DSP_LOGIC_OUTS_B21_2", - "DSP_LOGIC_OUTS_B21_3", - "DSP_LOGIC_OUTS_B21_4", - "DSP_LOGIC_OUTS_B22_0", - "DSP_LOGIC_OUTS_B22_1", - "DSP_LOGIC_OUTS_B22_2", - "DSP_LOGIC_OUTS_B22_3", - "DSP_LOGIC_OUTS_B22_4", - "DSP_LOGIC_OUTS_B23_0", - "DSP_LOGIC_OUTS_B23_1", - "DSP_LOGIC_OUTS_B23_2", - "DSP_LOGIC_OUTS_B23_3", - "DSP_LOGIC_OUTS_B23_4", - "DSP_LOGIC_OUTS_B2_0", - "DSP_LOGIC_OUTS_B2_1", - "DSP_LOGIC_OUTS_B2_2", - "DSP_LOGIC_OUTS_B2_3", - "DSP_LOGIC_OUTS_B2_4", - "DSP_LOGIC_OUTS_B3_0", - "DSP_LOGIC_OUTS_B3_1", - "DSP_LOGIC_OUTS_B3_2", - "DSP_LOGIC_OUTS_B3_3", - "DSP_LOGIC_OUTS_B3_4", - "DSP_LOGIC_OUTS_B4_0", - "DSP_LOGIC_OUTS_B4_1", - "DSP_LOGIC_OUTS_B4_2", - "DSP_LOGIC_OUTS_B4_3", - "DSP_LOGIC_OUTS_B4_4", - "DSP_LOGIC_OUTS_B5_0", - "DSP_LOGIC_OUTS_B5_1", - "DSP_LOGIC_OUTS_B5_2", - "DSP_LOGIC_OUTS_B5_3", - "DSP_LOGIC_OUTS_B5_4", - "DSP_LOGIC_OUTS_B6_0", - "DSP_LOGIC_OUTS_B6_1", - "DSP_LOGIC_OUTS_B6_2", - "DSP_LOGIC_OUTS_B6_3", - "DSP_LOGIC_OUTS_B6_4", - "DSP_LOGIC_OUTS_B7_0", - "DSP_LOGIC_OUTS_B7_1", - "DSP_LOGIC_OUTS_B7_2", - "DSP_LOGIC_OUTS_B7_3", - "DSP_LOGIC_OUTS_B7_4", - "DSP_LOGIC_OUTS_B8_0", - "DSP_LOGIC_OUTS_B8_1", - "DSP_LOGIC_OUTS_B8_2", - "DSP_LOGIC_OUTS_B8_3", - "DSP_LOGIC_OUTS_B8_4", - "DSP_LOGIC_OUTS_B9_0", - "DSP_LOGIC_OUTS_B9_1", - "DSP_LOGIC_OUTS_B9_2", - "DSP_LOGIC_OUTS_B9_3", - "DSP_LOGIC_OUTS_B9_4", - "DSP_MONITOR_N_0", - "DSP_MONITOR_N_1", - "DSP_MONITOR_N_2", - "DSP_MONITOR_N_3", - "DSP_MONITOR_N_4", - "DSP_MONITOR_P_0", - "DSP_MONITOR_P_1", - "DSP_MONITOR_P_2", - "DSP_MONITOR_P_3", - "DSP_MONITOR_P_4", - "DSP_MULTSIGNOUT", - "DSP_NE2A0_0", - "DSP_NE2A0_1", - "DSP_NE2A0_2", - "DSP_NE2A0_3", - "DSP_NE2A0_4", - "DSP_NE2A1_0", - "DSP_NE2A1_1", - "DSP_NE2A1_2", - "DSP_NE2A1_3", - "DSP_NE2A1_4", - "DSP_NE2A2_0", - "DSP_NE2A2_1", - "DSP_NE2A2_2", - "DSP_NE2A2_3", - "DSP_NE2A2_4", - "DSP_NE2A3_0", - "DSP_NE2A3_1", - "DSP_NE2A3_2", - "DSP_NE2A3_3", - "DSP_NE2A3_4", - "DSP_NE4BEG0_0", - "DSP_NE4BEG0_1", - "DSP_NE4BEG0_2", - "DSP_NE4BEG0_3", - "DSP_NE4BEG0_4", - "DSP_NE4BEG1_0", - "DSP_NE4BEG1_1", - "DSP_NE4BEG1_2", - "DSP_NE4BEG1_3", - "DSP_NE4BEG1_4", - "DSP_NE4BEG2_0", - "DSP_NE4BEG2_1", - "DSP_NE4BEG2_2", - "DSP_NE4BEG2_3", - "DSP_NE4BEG2_4", - "DSP_NE4BEG3_0", - "DSP_NE4BEG3_1", - "DSP_NE4BEG3_2", - "DSP_NE4BEG3_3", - "DSP_NE4BEG3_4", - "DSP_NE4C0_0", - "DSP_NE4C0_1", - "DSP_NE4C0_2", - "DSP_NE4C0_3", - "DSP_NE4C0_4", - "DSP_NE4C1_0", - "DSP_NE4C1_1", - "DSP_NE4C1_2", - "DSP_NE4C1_3", - "DSP_NE4C1_4", - "DSP_NE4C2_0", - "DSP_NE4C2_1", - "DSP_NE4C2_2", - "DSP_NE4C2_3", - "DSP_NE4C2_4", - "DSP_NE4C3_0", - "DSP_NE4C3_1", - "DSP_NE4C3_2", - "DSP_NE4C3_3", - "DSP_NE4C3_4", - "DSP_NW2A0_0", - "DSP_NW2A0_1", - "DSP_NW2A0_2", - "DSP_NW2A0_3", - "DSP_NW2A0_4", - "DSP_NW2A1_0", - "DSP_NW2A1_1", - "DSP_NW2A1_2", - "DSP_NW2A1_3", - "DSP_NW2A1_4", - "DSP_NW2A2_0", - "DSP_NW2A2_1", - "DSP_NW2A2_2", - "DSP_NW2A2_3", - "DSP_NW2A2_4", - "DSP_NW2A3_0", - "DSP_NW2A3_1", - "DSP_NW2A3_2", - "DSP_NW2A3_3", - "DSP_NW2A3_4", - "DSP_NW4A0_0", - "DSP_NW4A0_1", - "DSP_NW4A0_2", - "DSP_NW4A0_3", - "DSP_NW4A0_4", - "DSP_NW4A1_0", - "DSP_NW4A1_1", - "DSP_NW4A1_2", - "DSP_NW4A1_3", - "DSP_NW4A1_4", - "DSP_NW4A2_0", - "DSP_NW4A2_1", - "DSP_NW4A2_2", - "DSP_NW4A2_3", - "DSP_NW4A2_4", - "DSP_NW4A3_0", - "DSP_NW4A3_1", - "DSP_NW4A3_2", - "DSP_NW4A3_3", - "DSP_NW4A3_4", - "DSP_NW4END0_0", - "DSP_NW4END0_1", - "DSP_NW4END0_2", - "DSP_NW4END0_3", - "DSP_NW4END0_4", - "DSP_NW4END1_0", - "DSP_NW4END1_1", - "DSP_NW4END1_2", - "DSP_NW4END1_3", - "DSP_NW4END1_4", - "DSP_NW4END2_0", - "DSP_NW4END2_1", - "DSP_NW4END2_2", - "DSP_NW4END2_3", - "DSP_NW4END2_4", - "DSP_NW4END3_0", - "DSP_NW4END3_1", - "DSP_NW4END3_2", - "DSP_NW4END3_3", - "DSP_NW4END3_4", - "DSP_PCOUT0", - "DSP_PCOUT1", - "DSP_PCOUT10", - "DSP_PCOUT11", - "DSP_PCOUT12", - "DSP_PCOUT13", - "DSP_PCOUT14", - "DSP_PCOUT15", - "DSP_PCOUT16", - "DSP_PCOUT17", - "DSP_PCOUT18", - "DSP_PCOUT19", - "DSP_PCOUT2", - "DSP_PCOUT20", - "DSP_PCOUT21", - "DSP_PCOUT22", - "DSP_PCOUT23", - "DSP_PCOUT24", - "DSP_PCOUT25", - "DSP_PCOUT26", - "DSP_PCOUT27", - "DSP_PCOUT28", - "DSP_PCOUT29", - "DSP_PCOUT3", - "DSP_PCOUT30", - "DSP_PCOUT31", - "DSP_PCOUT32", - "DSP_PCOUT33", - "DSP_PCOUT34", - "DSP_PCOUT35", - "DSP_PCOUT36", - "DSP_PCOUT37", - "DSP_PCOUT38", - "DSP_PCOUT39", - "DSP_PCOUT4", - "DSP_PCOUT40", - "DSP_PCOUT41", - "DSP_PCOUT42", - "DSP_PCOUT43", - "DSP_PCOUT44", - "DSP_PCOUT45", - "DSP_PCOUT46", - "DSP_PCOUT47", - "DSP_PCOUT5", - "DSP_PCOUT6", - "DSP_PCOUT7", - "DSP_PCOUT8", - "DSP_PCOUT9", - "DSP_SE2A0_0", - "DSP_SE2A0_1", - "DSP_SE2A0_2", - "DSP_SE2A0_3", - "DSP_SE2A0_4", - "DSP_SE2A1_0", - "DSP_SE2A1_1", - "DSP_SE2A1_2", - "DSP_SE2A1_3", - "DSP_SE2A1_4", - "DSP_SE2A2_0", - "DSP_SE2A2_1", - "DSP_SE2A2_2", - "DSP_SE2A2_3", - "DSP_SE2A2_4", - "DSP_SE2A3_0", - "DSP_SE2A3_1", - "DSP_SE2A3_2", - "DSP_SE2A3_3", - "DSP_SE2A3_4", - "DSP_SE4BEG0_0", - "DSP_SE4BEG0_1", - "DSP_SE4BEG0_2", - "DSP_SE4BEG0_3", - "DSP_SE4BEG0_4", - "DSP_SE4BEG1_0", - "DSP_SE4BEG1_1", - "DSP_SE4BEG1_2", - "DSP_SE4BEG1_3", - "DSP_SE4BEG1_4", - "DSP_SE4BEG2_0", - "DSP_SE4BEG2_1", - "DSP_SE4BEG2_2", - "DSP_SE4BEG2_3", - "DSP_SE4BEG2_4", - "DSP_SE4BEG3_0", - "DSP_SE4BEG3_1", - "DSP_SE4BEG3_2", - "DSP_SE4BEG3_3", - "DSP_SE4BEG3_4", - "DSP_SE4C0_0", - "DSP_SE4C0_1", - "DSP_SE4C0_2", - "DSP_SE4C0_3", - "DSP_SE4C0_4", - "DSP_SE4C1_0", - "DSP_SE4C1_1", - "DSP_SE4C1_2", - "DSP_SE4C1_3", - "DSP_SE4C1_4", - "DSP_SE4C2_0", - "DSP_SE4C2_1", - "DSP_SE4C2_2", - "DSP_SE4C2_3", - "DSP_SE4C2_4", - "DSP_SE4C3_0", - "DSP_SE4C3_1", - "DSP_SE4C3_2", - "DSP_SE4C3_3", - "DSP_SE4C3_4", - "DSP_SW2A0_0", - "DSP_SW2A0_1", - "DSP_SW2A0_2", - "DSP_SW2A0_3", - "DSP_SW2A0_4", - "DSP_SW2A1_0", - "DSP_SW2A1_1", - "DSP_SW2A1_2", - "DSP_SW2A1_3", - "DSP_SW2A1_4", - "DSP_SW2A2_0", - "DSP_SW2A2_1", - "DSP_SW2A2_2", - "DSP_SW2A2_3", - "DSP_SW2A2_4", - "DSP_SW2A3_0", - "DSP_SW2A3_1", - "DSP_SW2A3_2", - "DSP_SW2A3_3", - "DSP_SW2A3_4", - "DSP_SW4A0_0", - "DSP_SW4A0_1", - "DSP_SW4A0_2", - "DSP_SW4A0_3", - "DSP_SW4A0_4", - "DSP_SW4A1_0", - "DSP_SW4A1_1", - "DSP_SW4A1_2", - "DSP_SW4A1_3", - "DSP_SW4A1_4", - "DSP_SW4A2_0", - "DSP_SW4A2_1", - "DSP_SW4A2_2", - "DSP_SW4A2_3", - "DSP_SW4A2_4", - "DSP_SW4A3_0", - "DSP_SW4A3_1", - "DSP_SW4A3_2", - "DSP_SW4A3_3", - "DSP_SW4A3_4", - "DSP_SW4END0_0", - "DSP_SW4END0_1", - "DSP_SW4END0_2", - "DSP_SW4END0_3", - "DSP_SW4END0_4", - "DSP_SW4END1_0", - "DSP_SW4END1_1", - "DSP_SW4END1_2", - "DSP_SW4END1_3", - "DSP_SW4END1_4", - "DSP_SW4END2_0", - "DSP_SW4END2_1", - "DSP_SW4END2_2", - "DSP_SW4END2_3", - "DSP_SW4END2_4", - "DSP_SW4END3_0", - "DSP_SW4END3_1", - "DSP_SW4END3_2", - "DSP_SW4END3_3", - "DSP_SW4END3_4", - "DSP_VCC_R", - "DSP_WL1END0_0", - "DSP_WL1END0_1", - "DSP_WL1END0_2", - "DSP_WL1END0_3", - "DSP_WL1END0_4", - "DSP_WL1END1_0", - "DSP_WL1END1_1", - "DSP_WL1END1_2", - "DSP_WL1END1_3", - "DSP_WL1END1_4", - "DSP_WL1END2_0", - "DSP_WL1END2_1", - "DSP_WL1END2_2", - "DSP_WL1END2_3", - "DSP_WL1END2_4", - "DSP_WL1END3_0", - "DSP_WL1END3_1", - "DSP_WL1END3_2", - "DSP_WL1END3_3", - "DSP_WL1END3_4", - "DSP_WR1END0_0", - "DSP_WR1END0_1", - "DSP_WR1END0_2", - "DSP_WR1END0_3", - "DSP_WR1END0_4", - "DSP_WR1END1_0", - "DSP_WR1END1_1", - "DSP_WR1END1_2", - "DSP_WR1END1_3", - "DSP_WR1END1_4", - "DSP_WR1END2_0", - "DSP_WR1END2_1", - "DSP_WR1END2_2", - "DSP_WR1END2_3", - "DSP_WR1END2_4", - "DSP_WR1END3_0", - "DSP_WR1END3_1", - "DSP_WR1END3_2", - "DSP_WR1END3_3", - "DSP_WR1END3_4", - "DSP_WW2A0_0", - "DSP_WW2A0_1", - "DSP_WW2A0_2", - "DSP_WW2A0_3", - "DSP_WW2A0_4", - "DSP_WW2A1_0", - "DSP_WW2A1_1", - "DSP_WW2A1_2", - "DSP_WW2A1_3", - "DSP_WW2A1_4", - "DSP_WW2A2_0", - "DSP_WW2A2_1", - "DSP_WW2A2_2", - "DSP_WW2A2_3", - "DSP_WW2A2_4", - "DSP_WW2A3_0", - "DSP_WW2A3_1", - "DSP_WW2A3_2", - "DSP_WW2A3_3", - "DSP_WW2A3_4", - "DSP_WW2END0_0", - "DSP_WW2END0_1", - "DSP_WW2END0_2", - "DSP_WW2END0_3", - "DSP_WW2END0_4", - "DSP_WW2END1_0", - "DSP_WW2END1_1", - "DSP_WW2END1_2", - "DSP_WW2END1_3", - "DSP_WW2END1_4", - "DSP_WW2END2_0", - "DSP_WW2END2_1", - "DSP_WW2END2_2", - "DSP_WW2END2_3", - "DSP_WW2END2_4", - "DSP_WW2END3_0", - "DSP_WW2END3_1", - "DSP_WW2END3_2", - "DSP_WW2END3_3", - "DSP_WW2END3_4", - "DSP_WW4A0_0", - "DSP_WW4A0_1", - "DSP_WW4A0_2", - "DSP_WW4A0_3", - "DSP_WW4A0_4", - "DSP_WW4A1_0", - "DSP_WW4A1_1", - "DSP_WW4A1_2", - "DSP_WW4A1_3", - "DSP_WW4A1_4", - "DSP_WW4A2_0", - "DSP_WW4A2_1", - "DSP_WW4A2_2", - "DSP_WW4A2_3", - "DSP_WW4A2_4", - "DSP_WW4A3_0", - "DSP_WW4A3_1", - "DSP_WW4A3_2", - "DSP_WW4A3_3", - "DSP_WW4A3_4", - "DSP_WW4B0_0", - "DSP_WW4B0_1", - "DSP_WW4B0_2", - "DSP_WW4B0_3", - "DSP_WW4B0_4", - "DSP_WW4B1_0", - "DSP_WW4B1_1", - "DSP_WW4B1_2", - "DSP_WW4B1_3", - "DSP_WW4B1_4", - "DSP_WW4B2_0", - "DSP_WW4B2_1", - "DSP_WW4B2_2", - "DSP_WW4B2_3", - "DSP_WW4B2_4", - "DSP_WW4B3_0", - "DSP_WW4B3_1", - "DSP_WW4B3_2", - "DSP_WW4B3_3", - "DSP_WW4B3_4", - "DSP_WW4C0_0", - "DSP_WW4C0_1", - "DSP_WW4C0_2", - "DSP_WW4C0_3", - "DSP_WW4C0_4", - "DSP_WW4C1_0", - "DSP_WW4C1_1", - "DSP_WW4C1_2", - "DSP_WW4C1_3", - "DSP_WW4C1_4", - "DSP_WW4C2_0", - "DSP_WW4C2_1", - "DSP_WW4C2_2", - "DSP_WW4C2_3", - "DSP_WW4C2_4", - "DSP_WW4C3_0", - "DSP_WW4C3_1", - "DSP_WW4C3_2", - "DSP_WW4C3_3", - "DSP_WW4C3_4", - "DSP_WW4END0_0", - "DSP_WW4END0_1", - "DSP_WW4END0_2", - "DSP_WW4END0_3", - "DSP_WW4END0_4", - "DSP_WW4END1_0", - "DSP_WW4END1_1", - "DSP_WW4END1_2", - "DSP_WW4END1_3", - "DSP_WW4END1_4", - "DSP_WW4END2_0", - "DSP_WW4END2_1", - "DSP_WW4END2_2", - "DSP_WW4END2_3", - "DSP_WW4END2_4", - "DSP_WW4END3_0", - "DSP_WW4END3_1", - "DSP_WW4END3_2", - "DSP_WW4END3_3", - "DSP_WW4END3_4" - ] + "wires": { + "DSP_0_A0": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A1": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A10": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A11": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A12": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A13": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A14": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A15": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A16": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A17": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A18": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A19": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A2": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A20": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A21": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A22": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A23": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A24": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A25": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A26": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A27": { + "cap": "53.036", + "res": "0.000" + }, + "DSP_0_A28": { + "cap": "53.036", + "res": "0.000" + }, + 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"DSP_WW4END2_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END2_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END2_4": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_0": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_1": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_2": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_3": { + "cap": "12.700", + "res": "47.430" + }, + "DSP_WW4END3_4": { + "cap": "12.700", + "res": "47.430" + } + } } diff --git a/kintex7/tile_type_GTX_CHANNEL_0.json b/kintex7/tile_type_GTX_CHANNEL_0.json index 00dc7c4..68bd56b 100644 --- a/kintex7/tile_type_GTX_CHANNEL_0.json +++ b/kintex7/tile_type_GTX_CHANNEL_0.json @@ -2,4398 +2,11306 @@ "pips": { "GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLFBCLKLOST" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLLOCK->GTXE2_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLLOCK" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_CPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLREFCLKLOST" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT0->GTXE2_LOGIC_OUTS_B9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT1->GTXE2_LOGIC_OUTS_B9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT2->GTXE2_LOGIC_OUTS_B9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT3->GTXE2_LOGIC_OUTS_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT4->GTXE2_LOGIC_OUTS_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT5->GTXE2_LOGIC_OUTS_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT6->GTXE2_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DMONITOROUT7->GTXE2_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT7" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO0->GTXE2_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO1->GTXE2_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO10->GTXE2_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO10" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO11->GTXE2_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO11" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO12->GTXE2_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO12" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO13->GTXE2_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO13" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO14->GTXE2_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO14" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO15->GTXE2_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO15" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO2->GTXE2_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO3->GTXE2_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO4->GTXE2_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO5->GTXE2_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO6->GTXE2_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO7->GTXE2_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO7" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO8->GTXE2_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO8" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPDO9->GTXE2_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO9" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_DRPRDY->GTXE2_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPRDY" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_EYESCANDATAERROR->GTXE2_LOGIC_OUTS_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_EYESCANDATAERROR" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_GTREFCLKMONITOR->GTXE2_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTREFCLKMONITOR" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_GTRXOUTCLK_0->GTXE2_CHANNEL_RXOUTCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLK_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTRXOUTCLK_0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_GTTXOUTCLK_0->GTXE2_CHANNEL_TXOUTCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLK_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTTXOUTCLK_0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_NORTHREFCLK0->GTXE2_CHANNEL_GTNORTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_NORTHREFCLK0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_NORTHREFCLK1->GTXE2_CHANNEL_GTNORTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_NORTHREFCLK1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT0->GTXE2_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT1->GTXE2_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT10->GTXE2_LOGIC_OUTS_B13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT10" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT11->GTXE2_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT11" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT12->GTXE2_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT12" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT13->GTXE2_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT13" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT14->GTXE2_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT14" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT15->GTXE2_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT15" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT2->GTXE2_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT3->GTXE2_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT4->GTXE2_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT5->GTXE2_LOGIC_OUTS_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT6->GTXE2_LOGIC_OUTS_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT7->GTXE2_LOGIC_OUTS_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT7" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT8->GTXE2_LOGIC_OUTS_B13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT8" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PCSRSVDOUT9->GTXE2_LOGIC_OUTS_B13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT9" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_PHYSTATUS->GTXE2_LOGIC_OUTS_B10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PHYSTATUS" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_QPLLCLK->GTXE2_CHANNEL_GTQPLLCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTQPLLCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_QPLLCLK" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_QPLLREFCLK->GTXE2_CHANNEL_GTQPLLREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTQPLLREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_QPLLREFCLK" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_REFCLK0->GTXE2_CHANNEL_GTREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_REFCLK0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_REFCLK1->GTXE2_CHANNEL_GTREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_REFCLK1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFSTATUS0->GTXE2_LOGIC_OUTS_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFSTATUS1->GTXE2_LOGIC_OUTS_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBUFSTATUS2->GTXE2_LOGIC_OUTS_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBYTEISALIGNED->GTXE2_LOGIC_OUTS_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBYTEISALIGNED" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXBYTEREALIGN->GTXE2_LOGIC_OUTS_B10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBYTEREALIGN" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCDRLOCK->GTXE2_LOGIC_OUTS_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCDRLOCK" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHANBONDSEQ->GTXE2_LOGIC_OUTS_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANBONDSEQ" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHANISALIGNED->GTXE2_LOGIC_OUTS_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANISALIGNED" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHANREALIGN->GTXE2_LOGIC_OUTS_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANREALIGN" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA0->GTXE2_LOGIC_OUTS_B15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA1->GTXE2_LOGIC_OUTS_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA2->GTXE2_LOGIC_OUTS_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA3->GTXE2_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA4->GTXE2_LOGIC_OUTS_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA5->GTXE2_LOGIC_OUTS_B15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA6->GTXE2_LOGIC_OUTS_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISCOMMA7->GTXE2_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA7" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK0->GTXE2_LOGIC_OUTS_B12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK1->GTXE2_LOGIC_OUTS_B12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK2->GTXE2_LOGIC_OUTS_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK3->GTXE2_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK4->GTXE2_LOGIC_OUTS_B12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK5->GTXE2_LOGIC_OUTS_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK6->GTXE2_LOGIC_OUTS_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHARISK7->GTXE2_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK7" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO0->GTXE2_LOGIC_OUTS_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO1->GTXE2_LOGIC_OUTS_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO2->GTXE2_LOGIC_OUTS_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO3->GTXE2_LOGIC_OUTS_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCHBONDO4->GTXE2_LOGIC_OUTS_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCLKCORCNT0->GTXE2_LOGIC_OUTS_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCLKCORCNT1->GTXE2_LOGIC_OUTS_B20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMINITDET->GTXE2_LOGIC_OUTS_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMINITDET" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMMADET->GTXE2_LOGIC_OUTS_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMMADET" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMSASDET->GTXE2_LOGIC_OUTS_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMSASDET" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXCOMWAKEDET->GTXE2_LOGIC_OUTS_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMWAKEDET" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA0->GTXE2_LOGIC_OUTS_B6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA1->GTXE2_LOGIC_OUTS_B2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA10->GTXE2_LOGIC_OUTS_B4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA10" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA11->GTXE2_LOGIC_OUTS_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA11" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA12->GTXE2_LOGIC_OUTS_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA12" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA13->GTXE2_LOGIC_OUTS_B7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA13" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA14->GTXE2_LOGIC_OUTS_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA14" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA15->GTXE2_LOGIC_OUTS_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA15" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA16->GTXE2_LOGIC_OUTS_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA16" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA17->GTXE2_LOGIC_OUTS_B2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA17" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA18->GTXE2_LOGIC_OUTS_B4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA18" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA19->GTXE2_LOGIC_OUTS_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA19" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA2->GTXE2_LOGIC_OUTS_B4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA20->GTXE2_LOGIC_OUTS_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA20" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA21->GTXE2_LOGIC_OUTS_B7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA21" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA22->GTXE2_LOGIC_OUTS_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA22" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA23->GTXE2_LOGIC_OUTS_B5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA23" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA24->GTXE2_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA24" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA25->GTXE2_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA25" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA26->GTXE2_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA26" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA27->GTXE2_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA27" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA28->GTXE2_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA28" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA29->GTXE2_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA29" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA3->GTXE2_LOGIC_OUTS_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA30->GTXE2_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA30" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA31->GTXE2_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA31" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA32->GTXE2_LOGIC_OUTS_B3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA32" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA33->GTXE2_LOGIC_OUTS_B7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA33" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA34->GTXE2_LOGIC_OUTS_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA34" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA35->GTXE2_LOGIC_OUTS_B5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA35" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA36->GTXE2_LOGIC_OUTS_B6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA36" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA37->GTXE2_LOGIC_OUTS_B2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA37" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA38->GTXE2_LOGIC_OUTS_B4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA38" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA39->GTXE2_LOGIC_OUTS_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA39" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA4->GTXE2_LOGIC_OUTS_B3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA40->GTXE2_LOGIC_OUTS_B3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA40" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA41->GTXE2_LOGIC_OUTS_B7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA41" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA42->GTXE2_LOGIC_OUTS_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA42" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA43->GTXE2_LOGIC_OUTS_B5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA43" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA44->GTXE2_LOGIC_OUTS_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA44" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA45->GTXE2_LOGIC_OUTS_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA45" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA46->GTXE2_LOGIC_OUTS_B4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA46" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA47->GTXE2_LOGIC_OUTS_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA47" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA48->GTXE2_LOGIC_OUTS_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA48" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA49->GTXE2_LOGIC_OUTS_B7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA49" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA5->GTXE2_LOGIC_OUTS_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA50->GTXE2_LOGIC_OUTS_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA50" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA51->GTXE2_LOGIC_OUTS_B5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA51" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA52->GTXE2_LOGIC_OUTS_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA52" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA53->GTXE2_LOGIC_OUTS_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA53" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA54->GTXE2_LOGIC_OUTS_B4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA54" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA55->GTXE2_LOGIC_OUTS_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA55" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA56->GTXE2_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA56" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA57->GTXE2_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA57" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA58->GTXE2_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA58" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA59->GTXE2_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA59" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA6->GTXE2_LOGIC_OUTS_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA60->GTXE2_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA60" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA61->GTXE2_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA61" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA62->GTXE2_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA62" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA63->GTXE2_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA63" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA7->GTXE2_LOGIC_OUTS_B5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA7" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA8->GTXE2_LOGIC_OUTS_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA8" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATA9->GTXE2_LOGIC_OUTS_B2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA9" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDATAVALID->GTXE2_LOGIC_OUTS_B19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATAVALID" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR0->GTXE2_LOGIC_OUTS_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR1->GTXE2_LOGIC_OUTS_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR2->GTXE2_LOGIC_OUTS_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR3->GTXE2_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR4->GTXE2_LOGIC_OUTS_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR5->GTXE2_LOGIC_OUTS_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR6->GTXE2_LOGIC_OUTS_B22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDISPERR7->GTXE2_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR7" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDLYSRESETDONE" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXELECIDLE->GTXE2_LOGIC_OUTS_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXELECIDLE" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADER0->GTXE2_LOGIC_OUTS_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADER1->GTXE2_LOGIC_OUTS_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADER2->GTXE2_LOGIC_OUTS_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXHEADERVALID->GTXE2_LOGIC_OUTS_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADERVALID" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT0->GTXE2_LOGIC_OUTS_B8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT1->GTXE2_LOGIC_OUTS_B8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT2->GTXE2_LOGIC_OUTS_B8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT3->GTXE2_LOGIC_OUTS_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT4->GTXE2_LOGIC_OUTS_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT5->GTXE2_LOGIC_OUTS_B8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXMONITOROUT6->GTXE2_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE0->GTXE2_LOGIC_OUTS_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE1->GTXE2_LOGIC_OUTS_B14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE2->GTXE2_LOGIC_OUTS_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE3->GTXE2_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE4->GTXE2_LOGIC_OUTS_B14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE5->GTXE2_LOGIC_OUTS_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE6->GTXE2_LOGIC_OUTS_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXNOTINTABLE7->GTXE2_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE7" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXN_PAD->GTXE2_CHANNEL_RXN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXN_PAD" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXOUTCLKPCS->GTXE2_LOGIC_OUTS_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXOUTCLKPCS" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHALIGNDONE" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR0->GTXE2_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR1->GTXE2_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR2->GTXE2_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR3->GTXE2_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHMONITOR4->GTXE2_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR0->GTXE2_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR1->GTXE2_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR2->GTXE2_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR3->GTXE2_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPHSLIPMONITOR4->GTXE2_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXPRBSERR->GTXE2_LOGIC_OUTS_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPRBSERR" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXP_PAD->GTXE2_CHANNEL_RXP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXP_PAD" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXQPISENN->GTXE2_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXQPISENN" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXQPISENP->GTXE2_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXQPISENP" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXRATEDONE->GTXE2_LOGIC_OUTS_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXRATEDONE" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXRESETDONE->GTXE2_LOGIC_OUTS_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXRESETDONE" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTARTOFSEQ->GTXE2_LOGIC_OUTS_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTARTOFSEQ" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTATUS0->GTXE2_LOGIC_OUTS_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTATUS1->GTXE2_LOGIC_OUTS_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXSTATUS2->GTXE2_LOGIC_OUTS_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_RXVALID->GTXE2_LOGIC_OUTS_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXVALID" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_SOUTHREFCLK0->GTXE2_CHANNEL_GTSOUTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_SOUTHREFCLK1->GTXE2_CHANNEL_GTSOUTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT0->GTXE2_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT1->GTXE2_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT2->GTXE2_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT2" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT3->GTXE2_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT3" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT4->GTXE2_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT4" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT5->GTXE2_LOGIC_OUTS_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT5" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT6->GTXE2_LOGIC_OUTS_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT6" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT7->GTXE2_LOGIC_OUTS_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT7" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT8->GTXE2_LOGIC_OUTS_B11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT8" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TSTOUT9->GTXE2_LOGIC_OUTS_B11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT9" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXBUFSTATUS0->GTXE2_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS0" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXBUFSTATUS1->GTXE2_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS1" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXCOMFINISH->GTXE2_LOGIC_OUTS_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXCOMFINISH" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXDLYSRESETDONE" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXGEARBOXREADY->GTXE2_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXGEARBOXREADY" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXN->GTXE2_CHANNEL_TXN_PAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXN_PAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXN" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXOUTCLKPCS->GTXE2_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXOUTCLKPCS" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXP->GTXE2_CHANNEL_TXP_PAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXP_PAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXP" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXPHALIGNDONE" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXPHINITDONE->GTXE2_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXPHINITDONE" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXQPISENN->GTXE2_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXQPISENN" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXQPISENP->GTXE2_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXQPISENP" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXRATEDONE->GTXE2_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXRATEDONE" }, "GTX_CHANNEL_0.GTXE2_CHANNEL_TXRESETDONE->GTXE2_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXRESETDONE" }, "GTX_CHANNEL_0.GTXE2_CLK0_2->GTXE2_CHANNEL_CPLLLOCKDETCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_2" }, "GTX_CHANNEL_0.GTXE2_CLK0_4->GTXE2_CHANNEL_TXUSRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_4" }, "GTX_CHANNEL_0.GTXE2_CLK0_5->GTXE2_CHANNEL_TXUSRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSRCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_5" }, "GTX_CHANNEL_0.GTXE2_CLK0_6->GTXE2_CHANNEL_RXUSRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_6" }, "GTX_CHANNEL_0.GTXE2_CLK0_7->GTXE2_CHANNEL_RXUSRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSRCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_7" }, "GTX_CHANNEL_0.GTXE2_CLK1_1->GTXE2_CHANNEL_DRPCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_1" }, "GTX_CHANNEL_0.GTXE2_CLK1_2->GTXE2_CHANNEL_TXPHDLYTSTCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_2" }, "GTX_CHANNEL_0.GTXE2_CLK1_4->GTXE2_CHANNEL_CLKRSVD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_4" }, "GTX_CHANNEL_0.GTXE2_CLK1_5->GTXE2_CHANNEL_CLKRSVD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_5" }, "GTX_CHANNEL_0.GTXE2_CLK1_6->GTXE2_CHANNEL_GTGREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTGREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_6" }, "GTX_CHANNEL_0.GTXE2_CLK1_7->GTXE2_CHANNEL_CLKRSVD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_7" }, "GTX_CHANNEL_0.GTXE2_CLK1_8->GTXE2_CHANNEL_CLKRSVD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_8" }, "GTX_CHANNEL_0.GTXE2_CTRL0_10->GTXE2_CHANNEL_GTRESETSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRESETSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_10" }, "GTX_CHANNEL_0.GTXE2_CTRL0_3->GTXE2_CHANNEL_CPLLRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_3" }, "GTX_CHANNEL_0.GTXE2_CTRL0_5->GTXE2_CHANNEL_GTTXRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTTXRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_5" }, "GTX_CHANNEL_0.GTXE2_CTRL0_6->GTXE2_CHANNEL_RXDLYSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_6" }, "GTX_CHANNEL_0.GTXE2_CTRL0_7->GTXE2_CHANNEL_RXCDRFREQRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRFREQRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_7" }, "GTX_CHANNEL_0.GTXE2_CTRL0_8->GTXE2_CHANNEL_GTRXRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRXRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_8" }, "GTX_CHANNEL_0.GTXE2_CTRL0_9->GTXE2_CHANNEL_RXDFELPMRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELPMRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_9" }, "GTX_CHANNEL_0.GTXE2_CTRL1_1->GTXE2_CHANNEL_RXPHDLYRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHDLYRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_1" }, "GTX_CHANNEL_0.GTXE2_CTRL1_10->GTXE2_CHANNEL_RXOOBRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOOBRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_10" }, "GTX_CHANNEL_0.GTXE2_CTRL1_3->GTXE2_CHANNEL_TXPMARESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPMARESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_3" }, "GTX_CHANNEL_0.GTXE2_CTRL1_5->GTXE2_CHANNEL_CFGRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CFGRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_5" }, "GTX_CHANNEL_0.GTXE2_CTRL1_6->GTXE2_CHANNEL_RXBUFRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXBUFRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_6" }, "GTX_CHANNEL_0.GTXE2_CTRL1_7->GTXE2_CHANNEL_RXPMARESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPMARESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_7" }, "GTX_CHANNEL_0.GTXE2_CTRL1_8->GTXE2_CHANNEL_RXCDRRESETRSV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRRESETRSV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_8" }, "GTX_CHANNEL_0.GTXE2_CTRL1_9->GTXE2_CHANNEL_RXCDRRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_9" }, "GTX_CHANNEL_0.GTXE2_IMUX0_10->GTXE2_CHANNEL_RXELECIDLEMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_10" }, "GTX_CHANNEL_0.GTXE2_IMUX0_2->GTXE2_CHANNEL_TX8B10BEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_2" }, "GTX_CHANNEL_0.GTXE2_IMUX0_3->GTXE2_CHANNEL_TXMAINCURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_3" }, "GTX_CHANNEL_0.GTXE2_IMUX0_5->GTXE2_CHANNEL_TXSEQUENCE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_5" }, "GTX_CHANNEL_0.GTXE2_IMUX0_6->GTXE2_CHANNEL_PMARSVDIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_6" }, "GTX_CHANNEL_0.GTXE2_IMUX0_7->GTXE2_CHANNEL_PMARSVDIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_7" }, "GTX_CHANNEL_0.GTXE2_IMUX0_8->GTXE2_CHANNEL_PMARSVDIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_8" }, "GTX_CHANNEL_0.GTXE2_IMUX0_9->GTXE2_CHANNEL_PMARSVDIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_9" }, "GTX_CHANNEL_0.GTXE2_IMUX10_0->GTXE2_CHANNEL_TXCHARDISPVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_0" }, "GTX_CHANNEL_0.GTXE2_IMUX10_1->GTXE2_CHANNEL_TXPDELECIDLEMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_1" }, "GTX_CHANNEL_0.GTXE2_IMUX10_2->GTXE2_CHANNEL_TXCHARDISPVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_2" }, "GTX_CHANNEL_0.GTXE2_IMUX10_4->GTXE2_CHANNEL_TXCHARDISPVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_4" }, "GTX_CHANNEL_0.GTXE2_IMUX10_5->GTXE2_CHANNEL_TXUSERRDY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSERRDY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_5" }, "GTX_CHANNEL_0.GTXE2_IMUX10_6->GTXE2_CHANNEL_TXCHARDISPVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_6" }, "GTX_CHANNEL_0.GTXE2_IMUX10_7->GTXE2_CHANNEL_TXBUFDIFFCTRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_7" }, "GTX_CHANNEL_0.GTXE2_IMUX10_9->GTXE2_CHANNEL_RXQPIEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXQPIEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_9" }, "GTX_CHANNEL_0.GTXE2_IMUX11_10->GTXE2_CHANNEL_RXLPMLFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMLFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_10" }, "GTX_CHANNEL_0.GTXE2_IMUX11_2->GTXE2_CHANNEL_CPLLREFCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_2" }, "GTX_CHANNEL_0.GTXE2_IMUX11_5->GTXE2_CHANNEL_TXDLYHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_5" }, "GTX_CHANNEL_0.GTXE2_IMUX11_6->GTXE2_CHANNEL_RXRATE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_6" }, "GTX_CHANNEL_0.GTXE2_IMUX11_8->GTXE2_CHANNEL_RXDFEVSEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVSEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_8" }, "GTX_CHANNEL_0.GTXE2_IMUX12_1->GTXE2_CHANNEL_TXCOMWAKE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMWAKE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_1" }, "GTX_CHANNEL_0.GTXE2_IMUX12_10->GTXE2_CHANNEL_RXDFETAP3OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_10" }, "GTX_CHANNEL_0.GTXE2_IMUX12_2->GTXE2_CHANNEL_TXHEADER1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_2" }, "GTX_CHANNEL_0.GTXE2_IMUX12_4->GTXE2_CHANNEL_TXPHOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_4" }, "GTX_CHANNEL_0.GTXE2_IMUX12_5->GTXE2_CHANNEL_TXDLYOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_5" }, "GTX_CHANNEL_0.GTXE2_IMUX12_7->GTXE2_CHANNEL_TXBUFDIFFCTRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_7" }, "GTX_CHANNEL_0.GTXE2_IMUX12_8->GTXE2_CHANNEL_RXSLIDE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSLIDE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_8" }, "GTX_CHANNEL_0.GTXE2_IMUX12_9->GTXE2_CHANNEL_RX8B10BEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RX8B10BEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_9" }, "GTX_CHANNEL_0.GTXE2_IMUX13_1->GTXE2_CHANNEL_TXQPISTRONGPDOWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_1" }, "GTX_CHANNEL_0.GTXE2_IMUX13_10->GTXE2_CHANNEL_RXPRBSCNTRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSCNTRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_10" }, "GTX_CHANNEL_0.GTXE2_IMUX13_2->GTXE2_CHANNEL_TXHEADER0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_2" }, "GTX_CHANNEL_0.GTXE2_IMUX13_7->GTXE2_CHANNEL_TXBUFDIFFCTRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_7" }, "GTX_CHANNEL_0.GTXE2_IMUX13_8->GTXE2_CHANNEL_RXOSOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOSOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_8" }, "GTX_CHANNEL_0.GTXE2_IMUX13_9->GTXE2_CHANNEL_RXDFETAP5OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_9" }, "GTX_CHANNEL_0.GTXE2_IMUX14_10->GTXE2_CHANNEL_RXPHOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_10" }, "GTX_CHANNEL_0.GTXE2_IMUX14_2->GTXE2_CHANNEL_CPLLREFCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_2" }, "GTX_CHANNEL_0.GTXE2_IMUX14_5->GTXE2_CHANNEL_TXDLYEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_5" }, "GTX_CHANNEL_0.GTXE2_IMUX14_6->GTXE2_CHANNEL_RXRATE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_6" }, "GTX_CHANNEL_0.GTXE2_IMUX14_7->GTXE2_CHANNEL_RXPCSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPCSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_7" }, "GTX_CHANNEL_0.GTXE2_IMUX14_8->GTXE2_CHANNEL_RXCDROVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDROVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_8" }, "GTX_CHANNEL_0.GTXE2_IMUX14_9->GTXE2_CHANNEL_RXPHALIGN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHALIGN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_9" }, "GTX_CHANNEL_0.GTXE2_IMUX15_1->GTXE2_CHANNEL_TX8B10BBYPASS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_1" }, "GTX_CHANNEL_0.GTXE2_IMUX15_2->GTXE2_CHANNEL_CPLLREFCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_2" }, "GTX_CHANNEL_0.GTXE2_IMUX15_3->GTXE2_CHANNEL_TX8B10BBYPASS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_3" }, "GTX_CHANNEL_0.GTXE2_IMUX15_4->GTXE2_CHANNEL_TXPRBSFORCEERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSFORCEERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_4" }, "GTX_CHANNEL_0.GTXE2_IMUX15_5->GTXE2_CHANNEL_TX8B10BBYPASS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_5" }, "GTX_CHANNEL_0.GTXE2_IMUX15_6->GTXE2_CHANNEL_RXRATE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_6" }, "GTX_CHANNEL_0.GTXE2_IMUX15_7->GTXE2_CHANNEL_TX8B10BBYPASS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_7" }, "GTX_CHANNEL_0.GTXE2_IMUX16_0->GTXE2_CHANNEL_TXDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_0" }, "GTX_CHANNEL_0.GTXE2_IMUX16_1->GTXE2_CHANNEL_TXDATA56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_1" }, "GTX_CHANNEL_0.GTXE2_IMUX16_10->GTXE2_CHANNEL_RXDFECM1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFECM1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_10" }, "GTX_CHANNEL_0.GTXE2_IMUX16_2->GTXE2_CHANNEL_TXDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_2" }, "GTX_CHANNEL_0.GTXE2_IMUX16_3->GTXE2_CHANNEL_TXDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_3" }, "GTX_CHANNEL_0.GTXE2_IMUX16_4->GTXE2_CHANNEL_TXDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_4" }, "GTX_CHANNEL_0.GTXE2_IMUX16_5->GTXE2_CHANNEL_TXDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_5" }, "GTX_CHANNEL_0.GTXE2_IMUX16_6->GTXE2_CHANNEL_TXDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_6" }, "GTX_CHANNEL_0.GTXE2_IMUX16_7->GTXE2_CHANNEL_TXDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_7" }, "GTX_CHANNEL_0.GTXE2_IMUX17_0->GTXE2_CHANNEL_TXDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_0" }, "GTX_CHANNEL_0.GTXE2_IMUX17_1->GTXE2_CHANNEL_TXDATA57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_1" }, "GTX_CHANNEL_0.GTXE2_IMUX17_2->GTXE2_CHANNEL_TXDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_2" }, "GTX_CHANNEL_0.GTXE2_IMUX17_3->GTXE2_CHANNEL_TXDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_3" }, "GTX_CHANNEL_0.GTXE2_IMUX17_4->GTXE2_CHANNEL_TXDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_4" }, "GTX_CHANNEL_0.GTXE2_IMUX17_5->GTXE2_CHANNEL_TXDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_5" }, "GTX_CHANNEL_0.GTXE2_IMUX17_6->GTXE2_CHANNEL_TXDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_6" }, "GTX_CHANNEL_0.GTXE2_IMUX17_7->GTXE2_CHANNEL_TXDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_7" }, "GTX_CHANNEL_0.GTXE2_IMUX17_9->GTXE2_CHANNEL_RXCHBONDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_9" }, "GTX_CHANNEL_0.GTXE2_IMUX18_0->GTXE2_CHANNEL_TXDATA60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_0" }, "GTX_CHANNEL_0.GTXE2_IMUX18_1->GTXE2_CHANNEL_TXDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_1" }, "GTX_CHANNEL_0.GTXE2_IMUX18_10->GTXE2_CHANNEL_RXCHBONDLEVEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_10" }, "GTX_CHANNEL_0.GTXE2_IMUX18_2->GTXE2_CHANNEL_TXDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_2" }, "GTX_CHANNEL_0.GTXE2_IMUX18_3->GTXE2_CHANNEL_TXDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_3" }, "GTX_CHANNEL_0.GTXE2_IMUX18_4->GTXE2_CHANNEL_TXDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_4" }, "GTX_CHANNEL_0.GTXE2_IMUX18_5->GTXE2_CHANNEL_TXDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_5" }, "GTX_CHANNEL_0.GTXE2_IMUX18_6->GTXE2_CHANNEL_TXDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_6" }, "GTX_CHANNEL_0.GTXE2_IMUX18_7->GTXE2_CHANNEL_TXDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_7" }, "GTX_CHANNEL_0.GTXE2_IMUX18_9->GTXE2_CHANNEL_RXCHBONDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_9" }, "GTX_CHANNEL_0.GTXE2_IMUX19_0->GTXE2_CHANNEL_TXDATA61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_0" }, "GTX_CHANNEL_0.GTXE2_IMUX19_1->GTXE2_CHANNEL_TXDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_1" }, "GTX_CHANNEL_0.GTXE2_IMUX19_10->GTXE2_CHANNEL_RXCHBONDLEVEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_10" }, "GTX_CHANNEL_0.GTXE2_IMUX19_2->GTXE2_CHANNEL_TXDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_2" }, "GTX_CHANNEL_0.GTXE2_IMUX19_3->GTXE2_CHANNEL_TXDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_3" }, "GTX_CHANNEL_0.GTXE2_IMUX19_4->GTXE2_CHANNEL_TXDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_4" }, "GTX_CHANNEL_0.GTXE2_IMUX19_5->GTXE2_CHANNEL_TXDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_5" }, "GTX_CHANNEL_0.GTXE2_IMUX19_6->GTXE2_CHANNEL_TXDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_6" }, "GTX_CHANNEL_0.GTXE2_IMUX19_7->GTXE2_CHANNEL_TXDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_7" }, "GTX_CHANNEL_0.GTXE2_IMUX19_8->GTXE2_CHANNEL_RXDFEVPHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVPHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_8" }, "GTX_CHANNEL_0.GTXE2_IMUX19_9->GTXE2_CHANNEL_RXCHBONDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_9" }, "GTX_CHANNEL_0.GTXE2_IMUX1_10->GTXE2_CHANNEL_RXELECIDLEMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_10" }, "GTX_CHANNEL_0.GTXE2_IMUX1_2->GTXE2_CHANNEL_RXMONITORSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_2" }, "GTX_CHANNEL_0.GTXE2_IMUX1_3->GTXE2_CHANNEL_TXMAINCURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_3" }, "GTX_CHANNEL_0.GTXE2_IMUX1_4->GTXE2_CHANNEL_TXMAINCURSOR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_4" }, "GTX_CHANNEL_0.GTXE2_IMUX1_5->GTXE2_CHANNEL_TXSEQUENCE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_5" }, "GTX_CHANNEL_0.GTXE2_IMUX1_6->GTXE2_CHANNEL_TXSEQUENCE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_6" }, "GTX_CHANNEL_0.GTXE2_IMUX1_7->GTXE2_CHANNEL_PMARSVDIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_7" }, "GTX_CHANNEL_0.GTXE2_IMUX1_8->GTXE2_CHANNEL_TXOUTCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_8" }, "GTX_CHANNEL_0.GTXE2_IMUX1_9->GTXE2_CHANNEL_PMARSVDIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_9" }, "GTX_CHANNEL_0.GTXE2_IMUX20_0->GTXE2_CHANNEL_TXDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_0" }, "GTX_CHANNEL_0.GTXE2_IMUX20_1->GTXE2_CHANNEL_TXDATA58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_1" }, "GTX_CHANNEL_0.GTXE2_IMUX20_2->GTXE2_CHANNEL_TXDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_2" }, "GTX_CHANNEL_0.GTXE2_IMUX20_3->GTXE2_CHANNEL_TXDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_3" }, "GTX_CHANNEL_0.GTXE2_IMUX20_4->GTXE2_CHANNEL_TXDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_4" }, "GTX_CHANNEL_0.GTXE2_IMUX20_5->GTXE2_CHANNEL_TXDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_5" }, "GTX_CHANNEL_0.GTXE2_IMUX20_6->GTXE2_CHANNEL_TXDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_6" }, "GTX_CHANNEL_0.GTXE2_IMUX20_7->GTXE2_CHANNEL_TXDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_7" }, "GTX_CHANNEL_0.GTXE2_IMUX21_0->GTXE2_CHANNEL_TXDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_0" }, "GTX_CHANNEL_0.GTXE2_IMUX21_1->GTXE2_CHANNEL_TXDATA59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_1" }, "GTX_CHANNEL_0.GTXE2_IMUX21_10->GTXE2_CHANNEL_RXDFEAGCOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_10" }, "GTX_CHANNEL_0.GTXE2_IMUX21_2->GTXE2_CHANNEL_TXDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_2" }, "GTX_CHANNEL_0.GTXE2_IMUX21_3->GTXE2_CHANNEL_TXDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_3" }, "GTX_CHANNEL_0.GTXE2_IMUX21_4->GTXE2_CHANNEL_TXDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_4" }, "GTX_CHANNEL_0.GTXE2_IMUX21_5->GTXE2_CHANNEL_TXDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_5" }, "GTX_CHANNEL_0.GTXE2_IMUX21_6->GTXE2_CHANNEL_TXDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_6" }, "GTX_CHANNEL_0.GTXE2_IMUX21_7->GTXE2_CHANNEL_TXDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_7" }, "GTX_CHANNEL_0.GTXE2_IMUX21_8->GTXE2_CHANNEL_RXDFEXYDOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_8" }, "GTX_CHANNEL_0.GTXE2_IMUX21_9->GTXE2_CHANNEL_RXDFETAP4OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_9" }, "GTX_CHANNEL_0.GTXE2_IMUX22_0->GTXE2_CHANNEL_TXDATA62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_0" }, "GTX_CHANNEL_0.GTXE2_IMUX22_1->GTXE2_CHANNEL_TXDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_1" }, "GTX_CHANNEL_0.GTXE2_IMUX22_10->GTXE2_CHANNEL_RXCHBONDLEVEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_10" }, "GTX_CHANNEL_0.GTXE2_IMUX22_2->GTXE2_CHANNEL_TXDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_2" }, "GTX_CHANNEL_0.GTXE2_IMUX22_3->GTXE2_CHANNEL_TXDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_3" }, "GTX_CHANNEL_0.GTXE2_IMUX22_4->GTXE2_CHANNEL_TXDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_4" }, "GTX_CHANNEL_0.GTXE2_IMUX22_5->GTXE2_CHANNEL_TXDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_5" }, "GTX_CHANNEL_0.GTXE2_IMUX22_6->GTXE2_CHANNEL_TXDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_6" }, "GTX_CHANNEL_0.GTXE2_IMUX22_7->GTXE2_CHANNEL_TXDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_7" }, "GTX_CHANNEL_0.GTXE2_IMUX22_8->GTXE2_CHANNEL_RXPRBSSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_8" }, "GTX_CHANNEL_0.GTXE2_IMUX22_9->GTXE2_CHANNEL_RXCHBONDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_9" }, "GTX_CHANNEL_0.GTXE2_IMUX23_0->GTXE2_CHANNEL_TXDATA63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_0" }, "GTX_CHANNEL_0.GTXE2_IMUX23_1->GTXE2_CHANNEL_TXDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_1" }, "GTX_CHANNEL_0.GTXE2_IMUX23_10->GTXE2_CHANNEL_RXCHBONDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_10" }, "GTX_CHANNEL_0.GTXE2_IMUX23_2->GTXE2_CHANNEL_TXDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_2" }, "GTX_CHANNEL_0.GTXE2_IMUX23_3->GTXE2_CHANNEL_TXDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_3" }, "GTX_CHANNEL_0.GTXE2_IMUX23_4->GTXE2_CHANNEL_TXDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_4" }, "GTX_CHANNEL_0.GTXE2_IMUX23_5->GTXE2_CHANNEL_TXDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_5" }, "GTX_CHANNEL_0.GTXE2_IMUX23_6->GTXE2_CHANNEL_TXDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_6" }, "GTX_CHANNEL_0.GTXE2_IMUX23_7->GTXE2_CHANNEL_TXDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_7" }, "GTX_CHANNEL_0.GTXE2_IMUX23_8->GTXE2_CHANNEL_RXPRBSSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_8" }, "GTX_CHANNEL_0.GTXE2_IMUX23_9->GTXE2_CHANNEL_RXCHBONDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_9" }, "GTX_CHANNEL_0.GTXE2_IMUX24_1->GTXE2_CHANNEL_TSTIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_1" }, "GTX_CHANNEL_0.GTXE2_IMUX24_10->GTXE2_CHANNEL_TSTIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_10" }, "GTX_CHANNEL_0.GTXE2_IMUX24_2->GTXE2_CHANNEL_TSTIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_2" }, "GTX_CHANNEL_0.GTXE2_IMUX24_3->GTXE2_CHANNEL_TSTIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_3" }, "GTX_CHANNEL_0.GTXE2_IMUX24_4->GTXE2_CHANNEL_TSTIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_4" }, "GTX_CHANNEL_0.GTXE2_IMUX24_5->GTXE2_CHANNEL_TSTIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_5" }, "GTX_CHANNEL_0.GTXE2_IMUX24_6->GTXE2_CHANNEL_TSTIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_6" }, "GTX_CHANNEL_0.GTXE2_IMUX24_7->GTXE2_CHANNEL_TSTIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_7" }, "GTX_CHANNEL_0.GTXE2_IMUX24_8->GTXE2_CHANNEL_TSTIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_8" }, "GTX_CHANNEL_0.GTXE2_IMUX24_9->GTXE2_CHANNEL_TSTIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_9" }, "GTX_CHANNEL_0.GTXE2_IMUX25_10->GTXE2_CHANNEL_PCSRSVDIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_10" }, "GTX_CHANNEL_0.GTXE2_IMUX25_2->GTXE2_CHANNEL_TXPHALIGN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHALIGN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_2" }, "GTX_CHANNEL_0.GTXE2_IMUX25_3->GTXE2_CHANNEL_PCSRSVDIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_3" }, "GTX_CHANNEL_0.GTXE2_IMUX25_4->GTXE2_CHANNEL_PCSRSVDIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_4" }, "GTX_CHANNEL_0.GTXE2_IMUX25_5->GTXE2_CHANNEL_PCSRSVDIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_5" }, "GTX_CHANNEL_0.GTXE2_IMUX25_6->GTXE2_CHANNEL_PCSRSVDIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_6" }, "GTX_CHANNEL_0.GTXE2_IMUX25_7->GTXE2_CHANNEL_PCSRSVDIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_7" }, "GTX_CHANNEL_0.GTXE2_IMUX25_8->GTXE2_CHANNEL_PCSRSVDIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_8" }, "GTX_CHANNEL_0.GTXE2_IMUX25_9->GTXE2_CHANNEL_PCSRSVDIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_9" }, "GTX_CHANNEL_0.GTXE2_IMUX26_10->GTXE2_CHANNEL_GTRSVD15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_10" }, "GTX_CHANNEL_0.GTXE2_IMUX26_3->GTXE2_CHANNEL_GTRSVD8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_3" }, "GTX_CHANNEL_0.GTXE2_IMUX26_4->GTXE2_CHANNEL_GTRSVD9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_4" }, "GTX_CHANNEL_0.GTXE2_IMUX26_5->GTXE2_CHANNEL_GTRSVD10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_5" }, "GTX_CHANNEL_0.GTXE2_IMUX26_6->GTXE2_CHANNEL_GTRSVD11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_6" }, "GTX_CHANNEL_0.GTXE2_IMUX26_7->GTXE2_CHANNEL_GTRSVD12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_7" }, "GTX_CHANNEL_0.GTXE2_IMUX26_8->GTXE2_CHANNEL_GTRSVD13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_8" }, "GTX_CHANNEL_0.GTXE2_IMUX26_9->GTXE2_CHANNEL_GTRSVD14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_9" }, "GTX_CHANNEL_0.GTXE2_IMUX27_10->GTXE2_CHANNEL_RXLPMHFOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_10" }, "GTX_CHANNEL_0.GTXE2_IMUX27_5->GTXE2_CHANNEL_TXPHINIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHINIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_5" }, "GTX_CHANNEL_0.GTXE2_IMUX27_7->GTXE2_CHANNEL_RXPOLARITY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPOLARITY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_7" }, "GTX_CHANNEL_0.GTXE2_IMUX27_8->GTXE2_CHANNEL_RXDFEVPOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_8" }, "GTX_CHANNEL_0.GTXE2_IMUX27_9->GTXE2_CHANNEL_RXDFELFOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELFOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_9" }, "GTX_CHANNEL_0.GTXE2_IMUX28_1->GTXE2_CHANNEL_TXCOMSAS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMSAS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_1" }, "GTX_CHANNEL_0.GTXE2_IMUX28_10->GTXE2_CHANNEL_RXDFETAP2OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_10" }, "GTX_CHANNEL_0.GTXE2_IMUX28_2->GTXE2_CHANNEL_CPLLLOCKEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLLOCKEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_2" }, "GTX_CHANNEL_0.GTXE2_IMUX28_3->GTXE2_CHANNEL_DRPWE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPWE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_3" }, "GTX_CHANNEL_0.GTXE2_IMUX28_4->GTXE2_CHANNEL_TXSYSCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_4" }, "GTX_CHANNEL_0.GTXE2_IMUX28_5->GTXE2_CHANNEL_TXSYSCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_5" }, "GTX_CHANNEL_0.GTXE2_IMUX28_6->GTXE2_CHANNEL_RXDLYEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_6" }, "GTX_CHANNEL_0.GTXE2_IMUX28_8->GTXE2_CHANNEL_RXPD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_8" }, "GTX_CHANNEL_0.GTXE2_IMUX29_0->GTXE2_CHANNEL_TXCHARDISPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_0" }, "GTX_CHANNEL_0.GTXE2_IMUX29_1->GTXE2_CHANNEL_TXCHARISK7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_1" }, "GTX_CHANNEL_0.GTXE2_IMUX29_10->GTXE2_CHANNEL_RXDFEAGCHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEAGCHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_10" }, "GTX_CHANNEL_0.GTXE2_IMUX29_2->GTXE2_CHANNEL_TXCHARDISPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_2" }, "GTX_CHANNEL_0.GTXE2_IMUX29_3->GTXE2_CHANNEL_TXCHARISK6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_3" }, "GTX_CHANNEL_0.GTXE2_IMUX29_4->GTXE2_CHANNEL_TXCHARDISPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_4" }, "GTX_CHANNEL_0.GTXE2_IMUX29_5->GTXE2_CHANNEL_TXCHARISK5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_5" }, "GTX_CHANNEL_0.GTXE2_IMUX29_6->GTXE2_CHANNEL_TXCHARDISPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_6" }, "GTX_CHANNEL_0.GTXE2_IMUX29_7->GTXE2_CHANNEL_TXCHARISK4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_7" }, "GTX_CHANNEL_0.GTXE2_IMUX29_8->GTXE2_CHANNEL_RXOSHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOSHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_8" }, "GTX_CHANNEL_0.GTXE2_IMUX29_9->GTXE2_CHANNEL_RXDFETAP5HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP5HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_9" }, "GTX_CHANNEL_0.GTXE2_IMUX2_10->GTXE2_CHANNEL_RXOUTCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_10" }, "GTX_CHANNEL_0.GTXE2_IMUX2_3->GTXE2_CHANNEL_DRPADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_3" }, "GTX_CHANNEL_0.GTXE2_IMUX2_4->GTXE2_CHANNEL_TXPOSTCURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_4" }, "GTX_CHANNEL_0.GTXE2_IMUX2_5->GTXE2_CHANNEL_TXDIFFCTRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_5" }, "GTX_CHANNEL_0.GTXE2_IMUX2_6->GTXE2_CHANNEL_TXPRECURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_6" }, "GTX_CHANNEL_0.GTXE2_IMUX2_8->GTXE2_CHANNEL_RXGEARBOXSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXGEARBOXSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_8" }, "GTX_CHANNEL_0.GTXE2_IMUX2_9->GTXE2_CHANNEL_RXMCOMMAALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_9" }, "GTX_CHANNEL_0.GTXE2_IMUX30_10->GTXE2_CHANNEL_RXCHBONDSLAVE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDSLAVE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_10" }, "GTX_CHANNEL_0.GTXE2_IMUX30_3->GTXE2_CHANNEL_TXPOLARITY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOLARITY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_3" }, "GTX_CHANNEL_0.GTXE2_IMUX30_7->GTXE2_CHANNEL_TXPCSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPCSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_7" }, "GTX_CHANNEL_0.GTXE2_IMUX30_8->GTXE2_CHANNEL_RXCDRHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_8" }, "GTX_CHANNEL_0.GTXE2_IMUX30_9->GTXE2_CHANNEL_RXCHBONDMASTER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDMASTER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_9" }, "GTX_CHANNEL_0.GTXE2_IMUX31_0->GTXE2_CHANNEL_TXCHARDISPMODE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_0" }, "GTX_CHANNEL_0.GTXE2_IMUX31_1->GTXE2_CHANNEL_TXCHARISK3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_1" }, "GTX_CHANNEL_0.GTXE2_IMUX31_2->GTXE2_CHANNEL_TXCHARDISPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_2" }, "GTX_CHANNEL_0.GTXE2_IMUX31_3->GTXE2_CHANNEL_TXCHARISK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_3" }, "GTX_CHANNEL_0.GTXE2_IMUX31_4->GTXE2_CHANNEL_TXCHARDISPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_4" }, "GTX_CHANNEL_0.GTXE2_IMUX31_5->GTXE2_CHANNEL_TXCHARISK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_5" }, "GTX_CHANNEL_0.GTXE2_IMUX31_6->GTXE2_CHANNEL_TXCHARDISPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_6" }, "GTX_CHANNEL_0.GTXE2_IMUX31_7->GTXE2_CHANNEL_TXCHARISK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_7" }, "GTX_CHANNEL_0.GTXE2_IMUX31_8->GTXE2_CHANNEL_EYESCANTRIGGER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANTRIGGER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_8" }, "GTX_CHANNEL_0.GTXE2_IMUX32_0->GTXE2_CHANNEL_DRPDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_0" }, "GTX_CHANNEL_0.GTXE2_IMUX32_1->GTXE2_CHANNEL_DRPDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_1" }, "GTX_CHANNEL_0.GTXE2_IMUX32_2->GTXE2_CHANNEL_TXINHIBIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXINHIBIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_2" }, "GTX_CHANNEL_0.GTXE2_IMUX32_8->GTXE2_CHANNEL_RXDLYBYPASS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYBYPASS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_8" }, "GTX_CHANNEL_0.GTXE2_IMUX33_0->GTXE2_CHANNEL_DRPDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_0" }, "GTX_CHANNEL_0.GTXE2_IMUX33_1->GTXE2_CHANNEL_DRPDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_1" }, "GTX_CHANNEL_0.GTXE2_IMUX33_2->GTXE2_CHANNEL_TXPHALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_2" }, "GTX_CHANNEL_0.GTXE2_IMUX34_0->GTXE2_CHANNEL_DRPDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_0" }, "GTX_CHANNEL_0.GTXE2_IMUX34_1->GTXE2_CHANNEL_DRPDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_1" }, "GTX_CHANNEL_0.GTXE2_IMUX34_10->GTXE2_CHANNEL_PCSRSVDIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_10" }, "GTX_CHANNEL_0.GTXE2_IMUX34_2->GTXE2_CHANNEL_DRPADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_2" }, "GTX_CHANNEL_0.GTXE2_IMUX34_3->GTXE2_CHANNEL_DRPADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_3" }, "GTX_CHANNEL_0.GTXE2_IMUX34_4->GTXE2_CHANNEL_SETERRSTATUS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_SETERRSTATUS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_4" }, "GTX_CHANNEL_0.GTXE2_IMUX34_8->GTXE2_CHANNEL_RXLPMEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_8" }, "GTX_CHANNEL_0.GTXE2_IMUX34_9->GTXE2_CHANNEL_RXPCOMMAALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_9" }, "GTX_CHANNEL_0.GTXE2_IMUX35_0->GTXE2_CHANNEL_DRPDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_0" }, "GTX_CHANNEL_0.GTXE2_IMUX35_1->GTXE2_CHANNEL_DRPDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_1" }, "GTX_CHANNEL_0.GTXE2_IMUX35_10->GTXE2_CHANNEL_PCSRSVDIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_10" }, "GTX_CHANNEL_0.GTXE2_IMUX35_2->GTXE2_CHANNEL_DRPADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_2" }, "GTX_CHANNEL_0.GTXE2_IMUX35_3->GTXE2_CHANNEL_DRPADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_3" }, "GTX_CHANNEL_0.GTXE2_IMUX35_4->GTXE2_CHANNEL_TXMARGIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_4" }, "GTX_CHANNEL_0.GTXE2_IMUX35_5->GTXE2_CHANNEL_TXDEEMPH": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDEEMPH", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_5" }, "GTX_CHANNEL_0.GTXE2_IMUX35_6->GTXE2_CHANNEL_TXPD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_6" }, "GTX_CHANNEL_0.GTXE2_IMUX35_8->GTXE2_CHANNEL_RXDFEUTOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_8" }, "GTX_CHANNEL_0.GTXE2_IMUX35_9->GTXE2_CHANNEL_RXDFELFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_9" }, "GTX_CHANNEL_0.GTXE2_IMUX36_0->GTXE2_CHANNEL_DRPDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_0" }, "GTX_CHANNEL_0.GTXE2_IMUX36_1->GTXE2_CHANNEL_DRPDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_1" }, "GTX_CHANNEL_0.GTXE2_IMUX36_10->GTXE2_CHANNEL_RXDFETAP3HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP3HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_10" }, "GTX_CHANNEL_0.GTXE2_IMUX36_2->GTXE2_CHANNEL_CPLLPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_2" }, "GTX_CHANNEL_0.GTXE2_IMUX36_5->GTXE2_CHANNEL_TXPHDLYRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_5" }, "GTX_CHANNEL_0.GTXE2_IMUX37_0->GTXE2_CHANNEL_DRPDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_0" }, "GTX_CHANNEL_0.GTXE2_IMUX37_1->GTXE2_CHANNEL_DRPDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_1" }, "GTX_CHANNEL_0.GTXE2_IMUX37_3->GTXE2_CHANNEL_TXPHDLYPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_3" }, "GTX_CHANNEL_0.GTXE2_IMUX37_4->GTXE2_CHANNEL_TXDIFFPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_4" }, "GTX_CHANNEL_0.GTXE2_IMUX37_8->GTXE2_CHANNEL_RXDFEXYDHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_8" }, "GTX_CHANNEL_0.GTXE2_IMUX37_9->GTXE2_CHANNEL_RXDFETAP4HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP4HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_9" }, "GTX_CHANNEL_0.GTXE2_IMUX38_0->GTXE2_CHANNEL_DRPDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_0" }, "GTX_CHANNEL_0.GTXE2_IMUX38_1->GTXE2_CHANNEL_DRPDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_1" }, "GTX_CHANNEL_0.GTXE2_IMUX38_10->GTXE2_CHANNEL_PCSRSVDIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_10" }, "GTX_CHANNEL_0.GTXE2_IMUX38_2->GTXE2_CHANNEL_DRPADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_2" }, "GTX_CHANNEL_0.GTXE2_IMUX38_3->GTXE2_CHANNEL_DRPADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_3" }, "GTX_CHANNEL_0.GTXE2_IMUX38_4->GTXE2_CHANNEL_TXMARGIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_4" }, "GTX_CHANNEL_0.GTXE2_IMUX38_5->GTXE2_CHANNEL_TXSWING": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSWING", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_5" }, "GTX_CHANNEL_0.GTXE2_IMUX38_6->GTXE2_CHANNEL_TXPD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_6" }, "GTX_CHANNEL_0.GTXE2_IMUX38_7->GTXE2_CHANNEL_RXDLYOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_7" }, "GTX_CHANNEL_0.GTXE2_IMUX38_8->GTXE2_CHANNEL_RXPRBSSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_8" }, "GTX_CHANNEL_0.GTXE2_IMUX39_0->GTXE2_CHANNEL_DRPDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_0" }, "GTX_CHANNEL_0.GTXE2_IMUX39_1->GTXE2_CHANNEL_DRPDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_1" }, "GTX_CHANNEL_0.GTXE2_IMUX39_10->GTXE2_CHANNEL_PCSRSVDIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_10" }, "GTX_CHANNEL_0.GTXE2_IMUX39_2->GTXE2_CHANNEL_DRPADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_2" }, "GTX_CHANNEL_0.GTXE2_IMUX39_3->GTXE2_CHANNEL_DRPADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_3" }, "GTX_CHANNEL_0.GTXE2_IMUX39_4->GTXE2_CHANNEL_TXMARGIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_4" }, "GTX_CHANNEL_0.GTXE2_IMUX39_5->GTXE2_CHANNEL_TXDETECTRX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDETECTRX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_5" }, "GTX_CHANNEL_0.GTXE2_IMUX39_6->GTXE2_CHANNEL_TXELECIDLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXELECIDLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_6" }, "GTX_CHANNEL_0.GTXE2_IMUX39_9->GTXE2_CHANNEL_PCSRSVDIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_9" }, "GTX_CHANNEL_0.GTXE2_IMUX3_10->GTXE2_CHANNEL_RXLPMLFKLOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_10" }, "GTX_CHANNEL_0.GTXE2_IMUX3_3->GTXE2_CHANNEL_TXSTARTSEQ": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSTARTSEQ", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_3" }, "GTX_CHANNEL_0.GTXE2_IMUX3_4->GTXE2_CHANNEL_TXPOSTCURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_4" }, "GTX_CHANNEL_0.GTXE2_IMUX3_5->GTXE2_CHANNEL_TXDIFFCTRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_5" }, "GTX_CHANNEL_0.GTXE2_IMUX3_6->GTXE2_CHANNEL_TXPRECURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_6" }, "GTX_CHANNEL_0.GTXE2_IMUX3_7->GTXE2_CHANNEL_RXPD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_7" }, "GTX_CHANNEL_0.GTXE2_IMUX3_8->GTXE2_CHANNEL_TXPRBSSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_8" }, "GTX_CHANNEL_0.GTXE2_IMUX3_9->GTXE2_CHANNEL_RXDFEUTHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEUTHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_9" }, "GTX_CHANNEL_0.GTXE2_IMUX40_1->GTXE2_CHANNEL_TSTIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_1" }, "GTX_CHANNEL_0.GTXE2_IMUX40_10->GTXE2_CHANNEL_TSTIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_10" }, "GTX_CHANNEL_0.GTXE2_IMUX40_2->GTXE2_CHANNEL_TSTIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_2" }, "GTX_CHANNEL_0.GTXE2_IMUX40_3->GTXE2_CHANNEL_TSTIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_3" }, "GTX_CHANNEL_0.GTXE2_IMUX40_4->GTXE2_CHANNEL_TSTIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_4" }, "GTX_CHANNEL_0.GTXE2_IMUX40_5->GTXE2_CHANNEL_TSTIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_5" }, "GTX_CHANNEL_0.GTXE2_IMUX40_6->GTXE2_CHANNEL_TSTIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_6" }, "GTX_CHANNEL_0.GTXE2_IMUX40_7->GTXE2_CHANNEL_TSTIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_7" }, "GTX_CHANNEL_0.GTXE2_IMUX40_8->GTXE2_CHANNEL_TSTIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_8" }, "GTX_CHANNEL_0.GTXE2_IMUX40_9->GTXE2_CHANNEL_TSTIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_9" }, "GTX_CHANNEL_0.GTXE2_IMUX41_0->GTXE2_CHANNEL_EYESCANMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_0" }, "GTX_CHANNEL_0.GTXE2_IMUX41_1->GTXE2_CHANNEL_TXPOSTCURSORINV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSORINV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_1" }, "GTX_CHANNEL_0.GTXE2_IMUX41_5->GTXE2_CHANNEL_RESETOVRD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RESETOVRD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_5" }, "GTX_CHANNEL_0.GTXE2_IMUX41_6->GTXE2_CHANNEL_RXPHALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_6" }, "GTX_CHANNEL_0.GTXE2_IMUX42_10->GTXE2_CHANNEL_GTRSVD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_10" }, "GTX_CHANNEL_0.GTXE2_IMUX42_2->GTXE2_CHANNEL_RXSYSCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_2" }, "GTX_CHANNEL_0.GTXE2_IMUX42_3->GTXE2_CHANNEL_GTRSVD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_3" }, "GTX_CHANNEL_0.GTXE2_IMUX42_4->GTXE2_CHANNEL_GTRSVD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_4" }, "GTX_CHANNEL_0.GTXE2_IMUX42_5->GTXE2_CHANNEL_GTRSVD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_5" }, "GTX_CHANNEL_0.GTXE2_IMUX42_6->GTXE2_CHANNEL_GTRSVD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_6" }, "GTX_CHANNEL_0.GTXE2_IMUX42_7->GTXE2_CHANNEL_GTRSVD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_7" }, "GTX_CHANNEL_0.GTXE2_IMUX42_8->GTXE2_CHANNEL_GTRSVD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_8" }, "GTX_CHANNEL_0.GTXE2_IMUX42_9->GTXE2_CHANNEL_GTRSVD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_9" }, "GTX_CHANNEL_0.GTXE2_IMUX43_10->GTXE2_CHANNEL_RXLPMHFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMHFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_10" }, "GTX_CHANNEL_0.GTXE2_IMUX43_5->GTXE2_CHANNEL_TXDLYUPDOWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYUPDOWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_5" }, "GTX_CHANNEL_0.GTXE2_IMUX43_6->GTXE2_CHANNEL_TXRATE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_6" }, "GTX_CHANNEL_0.GTXE2_IMUX43_9->GTXE2_CHANNEL_LOOPBACK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_9" }, "GTX_CHANNEL_0.GTXE2_IMUX44_1->GTXE2_CHANNEL_TXCOMINIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMINIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_1" }, "GTX_CHANNEL_0.GTXE2_IMUX44_10->GTXE2_CHANNEL_RXDFETAP2HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP2HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_10" }, "GTX_CHANNEL_0.GTXE2_IMUX44_3->GTXE2_CHANNEL_DRPEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_3" }, "GTX_CHANNEL_0.GTXE2_IMUX44_5->GTXE2_CHANNEL_TXDLYBYPASS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYBYPASS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_5" }, "GTX_CHANNEL_0.GTXE2_IMUX44_8->GTXE2_CHANNEL_RXUSERRDY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSERRDY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_8" }, "GTX_CHANNEL_0.GTXE2_IMUX44_9->GTXE2_CHANNEL_RXCOMMADETEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCOMMADETEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_9" }, "GTX_CHANNEL_0.GTXE2_IMUX45_1->GTXE2_CHANNEL_TXQPIWEAKPUP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPIWEAKPUP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_1" }, "GTX_CHANNEL_0.GTXE2_IMUX45_10->GTXE2_CHANNEL_RXMONITORSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_10" }, "GTX_CHANNEL_0.GTXE2_IMUX45_2->GTXE2_CHANNEL_RXSYSCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_2" }, "GTX_CHANNEL_0.GTXE2_IMUX45_3->GTXE2_CHANNEL_TXDLYSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_3" }, "GTX_CHANNEL_0.GTXE2_IMUX45_8->GTXE2_CHANNEL_EYESCANRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_8" }, "GTX_CHANNEL_0.GTXE2_IMUX45_9->GTXE2_CHANNEL_RXDFEXYDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_9" }, "GTX_CHANNEL_0.GTXE2_IMUX46_6->GTXE2_CHANNEL_TXRATE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX46_6" }, "GTX_CHANNEL_0.GTXE2_IMUX46_9->GTXE2_CHANNEL_LOOPBACK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX46_9" }, "GTX_CHANNEL_0.GTXE2_IMUX47_6->GTXE2_CHANNEL_TXRATE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX47_6" }, "GTX_CHANNEL_0.GTXE2_IMUX47_9->GTXE2_CHANNEL_LOOPBACK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX47_9" }, "GTX_CHANNEL_0.GTXE2_IMUX4_1->GTXE2_CHANNEL_TXPRECURSORINV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSORINV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_1" }, "GTX_CHANNEL_0.GTXE2_IMUX4_10->GTXE2_CHANNEL_RXOUTCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_10" }, "GTX_CHANNEL_0.GTXE2_IMUX4_3->GTXE2_CHANNEL_TXMAINCURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_3" }, "GTX_CHANNEL_0.GTXE2_IMUX4_4->GTXE2_CHANNEL_TXMAINCURSOR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_4" }, "GTX_CHANNEL_0.GTXE2_IMUX4_5->GTXE2_CHANNEL_TXSEQUENCE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_5" }, "GTX_CHANNEL_0.GTXE2_IMUX4_6->GTXE2_CHANNEL_TXSEQUENCE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_6" }, "GTX_CHANNEL_0.GTXE2_IMUX4_7->GTXE2_CHANNEL_PMARSVDIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_7" }, "GTX_CHANNEL_0.GTXE2_IMUX4_8->GTXE2_CHANNEL_TXOUTCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_8" }, "GTX_CHANNEL_0.GTXE2_IMUX4_9->GTXE2_CHANNEL_PMARSVDIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_9" }, "GTX_CHANNEL_0.GTXE2_IMUX5_1->GTXE2_CHANNEL_TXQPIBIASEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPIBIASEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_1" }, "GTX_CHANNEL_0.GTXE2_IMUX5_10->GTXE2_CHANNEL_RXOUTCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_10" }, "GTX_CHANNEL_0.GTXE2_IMUX5_3->GTXE2_CHANNEL_TXMAINCURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_3" }, "GTX_CHANNEL_0.GTXE2_IMUX5_4->GTXE2_CHANNEL_TXMAINCURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_4" }, "GTX_CHANNEL_0.GTXE2_IMUX5_5->GTXE2_CHANNEL_TXSEQUENCE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_5" }, "GTX_CHANNEL_0.GTXE2_IMUX5_6->GTXE2_CHANNEL_TXSEQUENCE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_6" }, "GTX_CHANNEL_0.GTXE2_IMUX5_7->GTXE2_CHANNEL_PMARSVDIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_7" }, "GTX_CHANNEL_0.GTXE2_IMUX5_8->GTXE2_CHANNEL_TXOUTCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_8" }, "GTX_CHANNEL_0.GTXE2_IMUX5_9->GTXE2_CHANNEL_PMARSVDIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_9" }, "GTX_CHANNEL_0.GTXE2_IMUX6_4->GTXE2_CHANNEL_TXPOSTCURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_4" }, "GTX_CHANNEL_0.GTXE2_IMUX6_5->GTXE2_CHANNEL_TXDIFFCTRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_5" }, "GTX_CHANNEL_0.GTXE2_IMUX6_6->GTXE2_CHANNEL_TXPRECURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_6" }, "GTX_CHANNEL_0.GTXE2_IMUX6_8->GTXE2_CHANNEL_TXPRBSSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_8" }, "GTX_CHANNEL_0.GTXE2_IMUX7_0->GTXE2_CHANNEL_TXPISOPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPISOPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_0" }, "GTX_CHANNEL_0.GTXE2_IMUX7_3->GTXE2_CHANNEL_TXPOSTCURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_3" }, "GTX_CHANNEL_0.GTXE2_IMUX7_4->GTXE2_CHANNEL_TXPOSTCURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_4" }, "GTX_CHANNEL_0.GTXE2_IMUX7_5->GTXE2_CHANNEL_TXDIFFCTRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_5" }, "GTX_CHANNEL_0.GTXE2_IMUX7_6->GTXE2_CHANNEL_TXPRECURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_6" }, "GTX_CHANNEL_0.GTXE2_IMUX7_7->GTXE2_CHANNEL_TXPRECURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_7" }, "GTX_CHANNEL_0.GTXE2_IMUX7_8->GTXE2_CHANNEL_TXPRBSSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_8" }, "GTX_CHANNEL_0.GTXE2_IMUX8_0->GTXE2_CHANNEL_TXCHARDISPVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_0" }, "GTX_CHANNEL_0.GTXE2_IMUX8_1->GTXE2_CHANNEL_TX8B10BBYPASS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_1" }, "GTX_CHANNEL_0.GTXE2_IMUX8_2->GTXE2_CHANNEL_TXCHARDISPVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_2" }, "GTX_CHANNEL_0.GTXE2_IMUX8_3->GTXE2_CHANNEL_TX8B10BBYPASS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_3" }, "GTX_CHANNEL_0.GTXE2_IMUX8_4->GTXE2_CHANNEL_TXCHARDISPVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_4" }, "GTX_CHANNEL_0.GTXE2_IMUX8_5->GTXE2_CHANNEL_TX8B10BBYPASS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_5" }, "GTX_CHANNEL_0.GTXE2_IMUX8_6->GTXE2_CHANNEL_TXCHARDISPVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_6" }, "GTX_CHANNEL_0.GTXE2_IMUX8_7->GTXE2_CHANNEL_TX8B10BBYPASS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_7" }, "GTX_CHANNEL_0.GTXE2_IMUX8_8->GTXE2_CHANNEL_RXDDIEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDDIEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_8" }, "GTX_CHANNEL_0.GTXE2_IMUX9_1->GTXE2_CHANNEL_RXPHDLYPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHDLYPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_1" }, "GTX_CHANNEL_0.GTXE2_IMUX9_10->GTXE2_CHANNEL_PCSRSVDIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_10" }, "GTX_CHANNEL_0.GTXE2_IMUX9_2->GTXE2_CHANNEL_TXHEADER2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_2" }, "GTX_CHANNEL_0.GTXE2_IMUX9_3->GTXE2_CHANNEL_PCSRSVDIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_3" }, "GTX_CHANNEL_0.GTXE2_IMUX9_4->GTXE2_CHANNEL_PCSRSVDIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_4" }, "GTX_CHANNEL_0.GTXE2_IMUX9_5->GTXE2_CHANNEL_PCSRSVDIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_5" }, "GTX_CHANNEL_0.GTXE2_IMUX9_6->GTXE2_CHANNEL_PCSRSVDIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_6" }, "GTX_CHANNEL_0.GTXE2_IMUX9_7->GTXE2_CHANNEL_PCSRSVDIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_7" }, "GTX_CHANNEL_0.GTXE2_IMUX9_8->GTXE2_CHANNEL_PCSRSVDIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_8" }, "GTX_CHANNEL_0.GTXE2_IMUX9_9->GTXE2_CHANNEL_PCSRSVDIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_9" } }, @@ -4402,690 +11310,6846 @@ "name": "X0Y0", "prefix": "GTXE2_CHANNEL", "site_pins": { - "CFGRESET": "GTXE2_CHANNEL_CFGRESET", - "CLKRSVD0": "GTXE2_CHANNEL_CLKRSVD0", - "CLKRSVD1": "GTXE2_CHANNEL_CLKRSVD1", - "CLKRSVD2": "GTXE2_CHANNEL_CLKRSVD2", - "CLKRSVD3": "GTXE2_CHANNEL_CLKRSVD3", - "CPLLFBCLKLOST": "GTXE2_CHANNEL_CPLLFBCLKLOST", - "CPLLLOCK": "GTXE2_CHANNEL_CPLLLOCK", - "CPLLLOCKDETCLK": "GTXE2_CHANNEL_CPLLLOCKDETCLK", - "CPLLLOCKEN": "GTXE2_CHANNEL_CPLLLOCKEN", - "CPLLPD": "GTXE2_CHANNEL_CPLLPD", - "CPLLREFCLKLOST": "GTXE2_CHANNEL_CPLLREFCLKLOST", - "CPLLREFCLKSEL0": "GTXE2_CHANNEL_CPLLREFCLKSEL0", - "CPLLREFCLKSEL1": "GTXE2_CHANNEL_CPLLREFCLKSEL1", - "CPLLREFCLKSEL2": "GTXE2_CHANNEL_CPLLREFCLKSEL2", - "CPLLRESET": "GTXE2_CHANNEL_CPLLRESET", - "DMONITOROUT0": "GTXE2_CHANNEL_DMONITOROUT0", - "DMONITOROUT1": "GTXE2_CHANNEL_DMONITOROUT1", - "DMONITOROUT2": "GTXE2_CHANNEL_DMONITOROUT2", - "DMONITOROUT3": "GTXE2_CHANNEL_DMONITOROUT3", - "DMONITOROUT4": "GTXE2_CHANNEL_DMONITOROUT4", - "DMONITOROUT5": "GTXE2_CHANNEL_DMONITOROUT5", - "DMONITOROUT6": "GTXE2_CHANNEL_DMONITOROUT6", - "DMONITOROUT7": "GTXE2_CHANNEL_DMONITOROUT7", - "DRPADDR0": "GTXE2_CHANNEL_DRPADDR0", - "DRPADDR1": "GTXE2_CHANNEL_DRPADDR1", - "DRPADDR2": "GTXE2_CHANNEL_DRPADDR2", - "DRPADDR3": "GTXE2_CHANNEL_DRPADDR3", - "DRPADDR4": "GTXE2_CHANNEL_DRPADDR4", - "DRPADDR5": "GTXE2_CHANNEL_DRPADDR5", - "DRPADDR6": "GTXE2_CHANNEL_DRPADDR6", - "DRPADDR7": "GTXE2_CHANNEL_DRPADDR7", - "DRPADDR8": "GTXE2_CHANNEL_DRPADDR8", - "DRPCLK": "GTXE2_CHANNEL_DRPCLK", - "DRPDI0": "GTXE2_CHANNEL_DRPDI0", - "DRPDI1": "GTXE2_CHANNEL_DRPDI1", - "DRPDI10": "GTXE2_CHANNEL_DRPDI10", - "DRPDI11": "GTXE2_CHANNEL_DRPDI11", - "DRPDI12": "GTXE2_CHANNEL_DRPDI12", - "DRPDI13": "GTXE2_CHANNEL_DRPDI13", - "DRPDI14": "GTXE2_CHANNEL_DRPDI14", - "DRPDI15": "GTXE2_CHANNEL_DRPDI15", - "DRPDI2": "GTXE2_CHANNEL_DRPDI2", - "DRPDI3": "GTXE2_CHANNEL_DRPDI3", - "DRPDI4": "GTXE2_CHANNEL_DRPDI4", - "DRPDI5": "GTXE2_CHANNEL_DRPDI5", - "DRPDI6": "GTXE2_CHANNEL_DRPDI6", - "DRPDI7": "GTXE2_CHANNEL_DRPDI7", - "DRPDI8": "GTXE2_CHANNEL_DRPDI8", - "DRPDI9": "GTXE2_CHANNEL_DRPDI9", - "DRPDO0": "GTXE2_CHANNEL_DRPDO0", - "DRPDO1": "GTXE2_CHANNEL_DRPDO1", - "DRPDO10": "GTXE2_CHANNEL_DRPDO10", - "DRPDO11": "GTXE2_CHANNEL_DRPDO11", - "DRPDO12": "GTXE2_CHANNEL_DRPDO12", - "DRPDO13": "GTXE2_CHANNEL_DRPDO13", - "DRPDO14": "GTXE2_CHANNEL_DRPDO14", - "DRPDO15": "GTXE2_CHANNEL_DRPDO15", - "DRPDO2": "GTXE2_CHANNEL_DRPDO2", - "DRPDO3": "GTXE2_CHANNEL_DRPDO3", - "DRPDO4": "GTXE2_CHANNEL_DRPDO4", - "DRPDO5": "GTXE2_CHANNEL_DRPDO5", - "DRPDO6": "GTXE2_CHANNEL_DRPDO6", - "DRPDO7": "GTXE2_CHANNEL_DRPDO7", - "DRPDO8": "GTXE2_CHANNEL_DRPDO8", - "DRPDO9": "GTXE2_CHANNEL_DRPDO9", - "DRPEN": "GTXE2_CHANNEL_DRPEN", - "DRPRDY": "GTXE2_CHANNEL_DRPRDY", - "DRPWE": "GTXE2_CHANNEL_DRPWE", - "EDTBYPASS": "GTXE2_CHANNEL_EDTBYPASS", - "EDTCLOCK": "GTXE2_CHANNEL_EDTCLOCK", - "EDTCONFIGURATION": "GTXE2_CHANNEL_EDTCONFIGURATION", - "EDTSINGLEBYPASSCHAIN": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", - "EDTUPDATE": "GTXE2_CHANNEL_EDTUPDATE", - "EYESCANDATAERROR": "GTXE2_CHANNEL_EYESCANDATAERROR", - "EYESCANMODE": "GTXE2_CHANNEL_EYESCANMODE", - "EYESCANRESET": "GTXE2_CHANNEL_EYESCANRESET", - "EYESCANTRIGGER": "GTXE2_CHANNEL_EYESCANTRIGGER", - "GTGREFCLK": "GTXE2_CHANNEL_GTGREFCLK", - "GTNORTHREFCLK0": "GTXE2_CHANNEL_GTNORTHREFCLK0", - "GTNORTHREFCLK1": "GTXE2_CHANNEL_GTNORTHREFCLK1", - "GTREFCLK0": "GTXE2_CHANNEL_GTREFCLK0", - "GTREFCLK1": "GTXE2_CHANNEL_GTREFCLK1", - "GTREFCLKMONITOR": "GTXE2_CHANNEL_GTREFCLKMONITOR", - "GTRESETSEL": "GTXE2_CHANNEL_GTRESETSEL", - "GTRSVD0": "GTXE2_CHANNEL_GTRSVD0", - "GTRSVD1": "GTXE2_CHANNEL_GTRSVD1", - "GTRSVD10": "GTXE2_CHANNEL_GTRSVD10", - "GTRSVD11": "GTXE2_CHANNEL_GTRSVD11", - "GTRSVD12": "GTXE2_CHANNEL_GTRSVD12", - "GTRSVD13": "GTXE2_CHANNEL_GTRSVD13", - "GTRSVD14": "GTXE2_CHANNEL_GTRSVD14", - "GTRSVD15": "GTXE2_CHANNEL_GTRSVD15", - "GTRSVD2": "GTXE2_CHANNEL_GTRSVD2", - "GTRSVD3": "GTXE2_CHANNEL_GTRSVD3", - "GTRSVD4": "GTXE2_CHANNEL_GTRSVD4", - "GTRSVD5": "GTXE2_CHANNEL_GTRSVD5", - "GTRSVD6": "GTXE2_CHANNEL_GTRSVD6", - "GTRSVD7": "GTXE2_CHANNEL_GTRSVD7", - "GTRSVD8": "GTXE2_CHANNEL_GTRSVD8", - "GTRSVD9": "GTXE2_CHANNEL_GTRSVD9", - "GTRXRESET": "GTXE2_CHANNEL_GTRXRESET", - "GTSOUTHREFCLK0": "GTXE2_CHANNEL_GTSOUTHREFCLK0", - "GTSOUTHREFCLK1": "GTXE2_CHANNEL_GTSOUTHREFCLK1", - "GTTXRESET": "GTXE2_CHANNEL_GTTXRESET", - "GTXRXN": "GTXE2_CHANNEL_RXN", - "GTXRXP": "GTXE2_CHANNEL_RXP", - "GTXTXN": "GTXE2_CHANNEL_TXN", - "GTXTXP": "GTXE2_CHANNEL_TXP", - "LOOPBACK0": "GTXE2_CHANNEL_LOOPBACK0", - "LOOPBACK1": "GTXE2_CHANNEL_LOOPBACK1", - "LOOPBACK2": "GTXE2_CHANNEL_LOOPBACK2", - "PCSRSVDIN0": "GTXE2_CHANNEL_PCSRSVDIN0", - "PCSRSVDIN1": "GTXE2_CHANNEL_PCSRSVDIN1", - "PCSRSVDIN10": "GTXE2_CHANNEL_PCSRSVDIN10", - "PCSRSVDIN11": "GTXE2_CHANNEL_PCSRSVDIN11", - "PCSRSVDIN12": "GTXE2_CHANNEL_PCSRSVDIN12", - "PCSRSVDIN13": "GTXE2_CHANNEL_PCSRSVDIN13", - "PCSRSVDIN14": "GTXE2_CHANNEL_PCSRSVDIN14", - "PCSRSVDIN15": "GTXE2_CHANNEL_PCSRSVDIN15", - "PCSRSVDIN2": "GTXE2_CHANNEL_PCSRSVDIN2", - "PCSRSVDIN20": "GTXE2_CHANNEL_PCSRSVDIN20", - "PCSRSVDIN21": "GTXE2_CHANNEL_PCSRSVDIN21", - "PCSRSVDIN22": "GTXE2_CHANNEL_PCSRSVDIN22", - "PCSRSVDIN23": "GTXE2_CHANNEL_PCSRSVDIN23", - "PCSRSVDIN24": "GTXE2_CHANNEL_PCSRSVDIN24", - "PCSRSVDIN3": "GTXE2_CHANNEL_PCSRSVDIN3", - "PCSRSVDIN4": "GTXE2_CHANNEL_PCSRSVDIN4", - "PCSRSVDIN5": "GTXE2_CHANNEL_PCSRSVDIN5", - "PCSRSVDIN6": "GTXE2_CHANNEL_PCSRSVDIN6", - "PCSRSVDIN7": "GTXE2_CHANNEL_PCSRSVDIN7", - "PCSRSVDIN8": "GTXE2_CHANNEL_PCSRSVDIN8", - "PCSRSVDIN9": "GTXE2_CHANNEL_PCSRSVDIN9", - "PCSRSVDOUT0": "GTXE2_CHANNEL_PCSRSVDOUT0", - "PCSRSVDOUT1": "GTXE2_CHANNEL_PCSRSVDOUT1", - "PCSRSVDOUT10": "GTXE2_CHANNEL_PCSRSVDOUT10", - "PCSRSVDOUT11": "GTXE2_CHANNEL_PCSRSVDOUT11", - "PCSRSVDOUT12": "GTXE2_CHANNEL_PCSRSVDOUT12", - "PCSRSVDOUT13": "GTXE2_CHANNEL_PCSRSVDOUT13", - "PCSRSVDOUT14": "GTXE2_CHANNEL_PCSRSVDOUT14", - "PCSRSVDOUT15": "GTXE2_CHANNEL_PCSRSVDOUT15", - "PCSRSVDOUT2": "GTXE2_CHANNEL_PCSRSVDOUT2", - "PCSRSVDOUT3": "GTXE2_CHANNEL_PCSRSVDOUT3", - "PCSRSVDOUT4": "GTXE2_CHANNEL_PCSRSVDOUT4", - "PCSRSVDOUT5": "GTXE2_CHANNEL_PCSRSVDOUT5", - "PCSRSVDOUT6": "GTXE2_CHANNEL_PCSRSVDOUT6", - "PCSRSVDOUT7": "GTXE2_CHANNEL_PCSRSVDOUT7", - "PCSRSVDOUT8": "GTXE2_CHANNEL_PCSRSVDOUT8", - "PCSRSVDOUT9": "GTXE2_CHANNEL_PCSRSVDOUT9", - "PHYSTATUS": "GTXE2_CHANNEL_PHYSTATUS", - "PMARSVDIN0": "GTXE2_CHANNEL_PMARSVDIN0", - "PMARSVDIN1": "GTXE2_CHANNEL_PMARSVDIN1", - "PMARSVDIN2": "GTXE2_CHANNEL_PMARSVDIN2", - "PMARSVDIN20": "GTXE2_CHANNEL_PMARSVDIN20", - "PMARSVDIN21": "GTXE2_CHANNEL_PMARSVDIN21", - "PMARSVDIN22": "GTXE2_CHANNEL_PMARSVDIN22", - "PMARSVDIN23": "GTXE2_CHANNEL_PMARSVDIN23", - "PMARSVDIN24": "GTXE2_CHANNEL_PMARSVDIN24", - "PMARSVDIN3": "GTXE2_CHANNEL_PMARSVDIN3", - "PMARSVDIN4": "GTXE2_CHANNEL_PMARSVDIN4", - "PMASCANCLK0": "GTXE2_CHANNEL_PMASCANCLK0", - "PMASCANCLK1": "GTXE2_CHANNEL_PMASCANCLK1", - "PMASCANCLK2": "GTXE2_CHANNEL_PMASCANCLK2", - "PMASCANCLK3": "GTXE2_CHANNEL_PMASCANCLK3", - "PMASCANCLK4": "GTXE2_CHANNEL_PMASCANCLK4", - "PMASCANENB": "GTXE2_CHANNEL_PMASCANENB", - "PMASCANIN0": "GTXE2_CHANNEL_PMASCANIN0", - "PMASCANIN1": "GTXE2_CHANNEL_PMASCANIN1", - "PMASCANIN2": "GTXE2_CHANNEL_PMASCANIN2", - "PMASCANIN3": "GTXE2_CHANNEL_PMASCANIN3", - "PMASCANIN4": "GTXE2_CHANNEL_PMASCANIN4", - "PMASCANMODEB": "GTXE2_CHANNEL_PMASCANMODEB", - "PMASCANOUT0": "GTXE2_CHANNEL_PMASCANOUT0", - "PMASCANOUT1": "GTXE2_CHANNEL_PMASCANOUT1", - "PMASCANOUT2": "GTXE2_CHANNEL_PMASCANOUT2", - "PMASCANOUT3": "GTXE2_CHANNEL_PMASCANOUT3", - "PMASCANOUT4": "GTXE2_CHANNEL_PMASCANOUT4", - "PMASCANRSTEN": "GTXE2_CHANNEL_PMASCANRSTEN", - "QPLLCLK": "GTXE2_CHANNEL_GTQPLLCLK", - "QPLLREFCLK": "GTXE2_CHANNEL_GTQPLLREFCLK", - "RESETOVRD": "GTXE2_CHANNEL_RESETOVRD", - "RX8B10BEN": "GTXE2_CHANNEL_RX8B10BEN", - "RXBUFRESET": "GTXE2_CHANNEL_RXBUFRESET", - "RXBUFSTATUS0": "GTXE2_CHANNEL_RXBUFSTATUS0", - "RXBUFSTATUS1": "GTXE2_CHANNEL_RXBUFSTATUS1", - "RXBUFSTATUS2": "GTXE2_CHANNEL_RXBUFSTATUS2", - "RXBYTEISALIGNED": "GTXE2_CHANNEL_RXBYTEISALIGNED", - "RXBYTEREALIGN": "GTXE2_CHANNEL_RXBYTEREALIGN", - "RXCDRFREQRESET": "GTXE2_CHANNEL_RXCDRFREQRESET", - "RXCDRHOLD": "GTXE2_CHANNEL_RXCDRHOLD", - "RXCDRLOCK": "GTXE2_CHANNEL_RXCDRLOCK", - "RXCDROVRDEN": "GTXE2_CHANNEL_RXCDROVRDEN", - "RXCDRRESET": "GTXE2_CHANNEL_RXCDRRESET", - "RXCDRRESETRSV": "GTXE2_CHANNEL_RXCDRRESETRSV", - "RXCHANBONDSEQ": "GTXE2_CHANNEL_RXCHANBONDSEQ", - "RXCHANISALIGNED": "GTXE2_CHANNEL_RXCHANISALIGNED", - "RXCHANREALIGN": "GTXE2_CHANNEL_RXCHANREALIGN", - "RXCHARISCOMMA0": "GTXE2_CHANNEL_RXCHARISCOMMA0", - "RXCHARISCOMMA1": "GTXE2_CHANNEL_RXCHARISCOMMA1", - "RXCHARISCOMMA2": "GTXE2_CHANNEL_RXCHARISCOMMA2", - "RXCHARISCOMMA3": "GTXE2_CHANNEL_RXCHARISCOMMA3", - "RXCHARISCOMMA4": "GTXE2_CHANNEL_RXCHARISCOMMA4", - "RXCHARISCOMMA5": "GTXE2_CHANNEL_RXCHARISCOMMA5", - "RXCHARISCOMMA6": "GTXE2_CHANNEL_RXCHARISCOMMA6", - "RXCHARISCOMMA7": "GTXE2_CHANNEL_RXCHARISCOMMA7", - "RXCHARISK0": "GTXE2_CHANNEL_RXCHARISK0", - "RXCHARISK1": "GTXE2_CHANNEL_RXCHARISK1", - "RXCHARISK2": "GTXE2_CHANNEL_RXCHARISK2", - "RXCHARISK3": "GTXE2_CHANNEL_RXCHARISK3", - "RXCHARISK4": "GTXE2_CHANNEL_RXCHARISK4", - "RXCHARISK5": "GTXE2_CHANNEL_RXCHARISK5", - "RXCHARISK6": "GTXE2_CHANNEL_RXCHARISK6", - "RXCHARISK7": "GTXE2_CHANNEL_RXCHARISK7", - "RXCHBONDEN": "GTXE2_CHANNEL_RXCHBONDEN", - "RXCHBONDI0": "GTXE2_CHANNEL_RXCHBONDI0", - "RXCHBONDI1": "GTXE2_CHANNEL_RXCHBONDI1", - "RXCHBONDI2": "GTXE2_CHANNEL_RXCHBONDI2", - "RXCHBONDI3": "GTXE2_CHANNEL_RXCHBONDI3", - "RXCHBONDI4": "GTXE2_CHANNEL_RXCHBONDI4", - "RXCHBONDLEVEL0": "GTXE2_CHANNEL_RXCHBONDLEVEL0", - "RXCHBONDLEVEL1": "GTXE2_CHANNEL_RXCHBONDLEVEL1", - "RXCHBONDLEVEL2": "GTXE2_CHANNEL_RXCHBONDLEVEL2", - "RXCHBONDMASTER": "GTXE2_CHANNEL_RXCHBONDMASTER", - "RXCHBONDO0": "GTXE2_CHANNEL_RXCHBONDO0", - "RXCHBONDO1": "GTXE2_CHANNEL_RXCHBONDO1", - "RXCHBONDO2": "GTXE2_CHANNEL_RXCHBONDO2", - "RXCHBONDO3": "GTXE2_CHANNEL_RXCHBONDO3", - "RXCHBONDO4": "GTXE2_CHANNEL_RXCHBONDO4", - "RXCHBONDSLAVE": "GTXE2_CHANNEL_RXCHBONDSLAVE", - "RXCLKCORCNT0": "GTXE2_CHANNEL_RXCLKCORCNT0", - "RXCLKCORCNT1": "GTXE2_CHANNEL_RXCLKCORCNT1", - "RXCOMINITDET": "GTXE2_CHANNEL_RXCOMINITDET", - "RXCOMMADET": "GTXE2_CHANNEL_RXCOMMADET", - "RXCOMMADETEN": "GTXE2_CHANNEL_RXCOMMADETEN", - "RXCOMSASDET": "GTXE2_CHANNEL_RXCOMSASDET", - "RXCOMWAKEDET": "GTXE2_CHANNEL_RXCOMWAKEDET", - "RXDATA0": "GTXE2_CHANNEL_RXDATA0", - "RXDATA1": "GTXE2_CHANNEL_RXDATA1", - "RXDATA10": "GTXE2_CHANNEL_RXDATA10", - "RXDATA11": "GTXE2_CHANNEL_RXDATA11", - "RXDATA12": "GTXE2_CHANNEL_RXDATA12", - "RXDATA13": "GTXE2_CHANNEL_RXDATA13", - "RXDATA14": "GTXE2_CHANNEL_RXDATA14", - "RXDATA15": "GTXE2_CHANNEL_RXDATA15", - "RXDATA16": "GTXE2_CHANNEL_RXDATA16", - "RXDATA17": "GTXE2_CHANNEL_RXDATA17", - "RXDATA18": "GTXE2_CHANNEL_RXDATA18", - "RXDATA19": "GTXE2_CHANNEL_RXDATA19", - "RXDATA2": "GTXE2_CHANNEL_RXDATA2", - "RXDATA20": "GTXE2_CHANNEL_RXDATA20", - "RXDATA21": "GTXE2_CHANNEL_RXDATA21", - "RXDATA22": "GTXE2_CHANNEL_RXDATA22", - "RXDATA23": "GTXE2_CHANNEL_RXDATA23", - "RXDATA24": "GTXE2_CHANNEL_RXDATA24", - "RXDATA25": "GTXE2_CHANNEL_RXDATA25", - "RXDATA26": "GTXE2_CHANNEL_RXDATA26", - "RXDATA27": "GTXE2_CHANNEL_RXDATA27", - "RXDATA28": "GTXE2_CHANNEL_RXDATA28", - "RXDATA29": "GTXE2_CHANNEL_RXDATA29", - "RXDATA3": "GTXE2_CHANNEL_RXDATA3", - "RXDATA30": "GTXE2_CHANNEL_RXDATA30", - "RXDATA31": "GTXE2_CHANNEL_RXDATA31", - "RXDATA32": "GTXE2_CHANNEL_RXDATA32", - "RXDATA33": "GTXE2_CHANNEL_RXDATA33", - "RXDATA34": "GTXE2_CHANNEL_RXDATA34", - "RXDATA35": "GTXE2_CHANNEL_RXDATA35", - "RXDATA36": "GTXE2_CHANNEL_RXDATA36", - "RXDATA37": "GTXE2_CHANNEL_RXDATA37", - "RXDATA38": "GTXE2_CHANNEL_RXDATA38", - "RXDATA39": "GTXE2_CHANNEL_RXDATA39", - "RXDATA4": "GTXE2_CHANNEL_RXDATA4", - "RXDATA40": "GTXE2_CHANNEL_RXDATA40", - "RXDATA41": "GTXE2_CHANNEL_RXDATA41", - "RXDATA42": "GTXE2_CHANNEL_RXDATA42", - "RXDATA43": "GTXE2_CHANNEL_RXDATA43", - "RXDATA44": "GTXE2_CHANNEL_RXDATA44", - "RXDATA45": "GTXE2_CHANNEL_RXDATA45", - "RXDATA46": "GTXE2_CHANNEL_RXDATA46", - "RXDATA47": "GTXE2_CHANNEL_RXDATA47", - "RXDATA48": "GTXE2_CHANNEL_RXDATA48", - "RXDATA49": "GTXE2_CHANNEL_RXDATA49", - "RXDATA5": "GTXE2_CHANNEL_RXDATA5", - "RXDATA50": "GTXE2_CHANNEL_RXDATA50", - "RXDATA51": "GTXE2_CHANNEL_RXDATA51", - "RXDATA52": "GTXE2_CHANNEL_RXDATA52", - "RXDATA53": "GTXE2_CHANNEL_RXDATA53", - "RXDATA54": "GTXE2_CHANNEL_RXDATA54", - "RXDATA55": "GTXE2_CHANNEL_RXDATA55", - "RXDATA56": "GTXE2_CHANNEL_RXDATA56", - "RXDATA57": "GTXE2_CHANNEL_RXDATA57", - "RXDATA58": "GTXE2_CHANNEL_RXDATA58", - "RXDATA59": "GTXE2_CHANNEL_RXDATA59", - "RXDATA6": "GTXE2_CHANNEL_RXDATA6", - "RXDATA60": "GTXE2_CHANNEL_RXDATA60", - "RXDATA61": "GTXE2_CHANNEL_RXDATA61", - "RXDATA62": "GTXE2_CHANNEL_RXDATA62", - "RXDATA63": "GTXE2_CHANNEL_RXDATA63", - "RXDATA7": "GTXE2_CHANNEL_RXDATA7", - "RXDATA8": "GTXE2_CHANNEL_RXDATA8", - "RXDATA9": "GTXE2_CHANNEL_RXDATA9", - "RXDATAVALID": "GTXE2_CHANNEL_RXDATAVALID", - "RXDDIEN": "GTXE2_CHANNEL_RXDDIEN", - "RXDEBUGPULSE": "GTXE2_CHANNEL_RXDEBUGPULSE", - "RXDFEAGCHOLD": "GTXE2_CHANNEL_RXDFEAGCHOLD", - "RXDFEAGCOVRDEN": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", - "RXDFECM1EN": "GTXE2_CHANNEL_RXDFECM1EN", - "RXDFELFHOLD": "GTXE2_CHANNEL_RXDFELFHOLD", - "RXDFELFOVRDEN": "GTXE2_CHANNEL_RXDFELFOVRDEN", - "RXDFELPMRESET": "GTXE2_CHANNEL_RXDFELPMRESET", - "RXDFETAP2HOLD": "GTXE2_CHANNEL_RXDFETAP2HOLD", - "RXDFETAP2OVRDEN": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", - "RXDFETAP3HOLD": "GTXE2_CHANNEL_RXDFETAP3HOLD", - "RXDFETAP3OVRDEN": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", - "RXDFETAP4HOLD": "GTXE2_CHANNEL_RXDFETAP4HOLD", - "RXDFETAP4OVRDEN": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", - "RXDFETAP5HOLD": "GTXE2_CHANNEL_RXDFETAP5HOLD", - "RXDFETAP5OVRDEN": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", - "RXDFEUTHOLD": "GTXE2_CHANNEL_RXDFEUTHOLD", - "RXDFEUTOVRDEN": "GTXE2_CHANNEL_RXDFEUTOVRDEN", - "RXDFEVPHOLD": "GTXE2_CHANNEL_RXDFEVPHOLD", - "RXDFEVPOVRDEN": "GTXE2_CHANNEL_RXDFEVPOVRDEN", - "RXDFEVSEN": "GTXE2_CHANNEL_RXDFEVSEN", - "RXDFEXYDEN": "GTXE2_CHANNEL_RXDFEXYDEN", - "RXDFEXYDHOLD": "GTXE2_CHANNEL_RXDFEXYDHOLD", - "RXDFEXYDOVRDEN": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", - "RXDISPERR0": "GTXE2_CHANNEL_RXDISPERR0", - "RXDISPERR1": "GTXE2_CHANNEL_RXDISPERR1", - "RXDISPERR2": "GTXE2_CHANNEL_RXDISPERR2", - "RXDISPERR3": "GTXE2_CHANNEL_RXDISPERR3", - "RXDISPERR4": "GTXE2_CHANNEL_RXDISPERR4", - "RXDISPERR5": "GTXE2_CHANNEL_RXDISPERR5", - "RXDISPERR6": "GTXE2_CHANNEL_RXDISPERR6", - "RXDISPERR7": "GTXE2_CHANNEL_RXDISPERR7", - "RXDLYBYPASS": "GTXE2_CHANNEL_RXDLYBYPASS", - "RXDLYEN": "GTXE2_CHANNEL_RXDLYEN", - "RXDLYOVRDEN": "GTXE2_CHANNEL_RXDLYOVRDEN", - "RXDLYSRESET": "GTXE2_CHANNEL_RXDLYSRESET", - "RXDLYSRESETDONE": "GTXE2_CHANNEL_RXDLYSRESETDONE", - "RXDLYTESTENB": "GTXE2_CHANNEL_RXDLYTESTENB", - "RXELECIDLE": "GTXE2_CHANNEL_RXELECIDLE", - "RXELECIDLEMODE0": "GTXE2_CHANNEL_RXELECIDLEMODE0", - "RXELECIDLEMODE1": "GTXE2_CHANNEL_RXELECIDLEMODE1", - "RXGEARBOXSLIP": "GTXE2_CHANNEL_RXGEARBOXSLIP", - "RXHEADER0": "GTXE2_CHANNEL_RXHEADER0", - "RXHEADER1": "GTXE2_CHANNEL_RXHEADER1", - "RXHEADER2": "GTXE2_CHANNEL_RXHEADER2", - "RXHEADERVALID": "GTXE2_CHANNEL_RXHEADERVALID", - "RXLPMEN": "GTXE2_CHANNEL_RXLPMEN", - "RXLPMHFHOLD": "GTXE2_CHANNEL_RXLPMHFHOLD", - "RXLPMHFOVRDEN": "GTXE2_CHANNEL_RXLPMHFOVRDEN", - "RXLPMLFHOLD": "GTXE2_CHANNEL_RXLPMLFHOLD", - "RXLPMLFKLOVRDEN": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", - "RXMCOMMAALIGNEN": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", - "RXMONITOROUT0": "GTXE2_CHANNEL_RXMONITOROUT0", - "RXMONITOROUT1": "GTXE2_CHANNEL_RXMONITOROUT1", - "RXMONITOROUT2": "GTXE2_CHANNEL_RXMONITOROUT2", - "RXMONITOROUT3": "GTXE2_CHANNEL_RXMONITOROUT3", - "RXMONITOROUT4": "GTXE2_CHANNEL_RXMONITOROUT4", - "RXMONITOROUT5": "GTXE2_CHANNEL_RXMONITOROUT5", - "RXMONITOROUT6": "GTXE2_CHANNEL_RXMONITOROUT6", - "RXMONITORSEL0": "GTXE2_CHANNEL_RXMONITORSEL0", - "RXMONITORSEL1": "GTXE2_CHANNEL_RXMONITORSEL1", - "RXNOTINTABLE0": "GTXE2_CHANNEL_RXNOTINTABLE0", - "RXNOTINTABLE1": "GTXE2_CHANNEL_RXNOTINTABLE1", - "RXNOTINTABLE2": "GTXE2_CHANNEL_RXNOTINTABLE2", - "RXNOTINTABLE3": "GTXE2_CHANNEL_RXNOTINTABLE3", - "RXNOTINTABLE4": "GTXE2_CHANNEL_RXNOTINTABLE4", - "RXNOTINTABLE5": "GTXE2_CHANNEL_RXNOTINTABLE5", - "RXNOTINTABLE6": "GTXE2_CHANNEL_RXNOTINTABLE6", - "RXNOTINTABLE7": "GTXE2_CHANNEL_RXNOTINTABLE7", - "RXOOBRESET": "GTXE2_CHANNEL_RXOOBRESET", - "RXOSHOLD": "GTXE2_CHANNEL_RXOSHOLD", - "RXOSOVRDEN": "GTXE2_CHANNEL_RXOSOVRDEN", - "RXOUTCLK": "GTXE2_CHANNEL_GTRXOUTCLK_0", - "RXOUTCLKFABRIC": "GTXE2_CHANNEL_RXOUTCLKFABRIC", - "RXOUTCLKPCS": "GTXE2_CHANNEL_RXOUTCLKPCS", - "RXOUTCLKSEL0": "GTXE2_CHANNEL_RXOUTCLKSEL0", - "RXOUTCLKSEL1": "GTXE2_CHANNEL_RXOUTCLKSEL1", - "RXOUTCLKSEL2": "GTXE2_CHANNEL_RXOUTCLKSEL2", - "RXPCD1DONE": "GTXE2_CHANNEL_RXPCD1DONE", - "RXPCOMMAALIGNEN": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", - "RXPCSRESET": "GTXE2_CHANNEL_RXPCSRESET", - "RXPD0": "GTXE2_CHANNEL_RXPD0", - "RXPD1": "GTXE2_CHANNEL_RXPD1", - "RXPHALIGN": "GTXE2_CHANNEL_RXPHALIGN", - "RXPHALIGNDONE": "GTXE2_CHANNEL_RXPHALIGNDONE", - "RXPHALIGNEN": "GTXE2_CHANNEL_RXPHALIGNEN", - "RXPHDLYPD": "GTXE2_CHANNEL_RXPHDLYPD", - "RXPHDLYRESET": "GTXE2_CHANNEL_RXPHDLYRESET", - "RXPHMONITOR0": "GTXE2_CHANNEL_RXPHMONITOR0", - "RXPHMONITOR1": "GTXE2_CHANNEL_RXPHMONITOR1", - "RXPHMONITOR2": "GTXE2_CHANNEL_RXPHMONITOR2", - "RXPHMONITOR3": "GTXE2_CHANNEL_RXPHMONITOR3", - "RXPHMONITOR4": "GTXE2_CHANNEL_RXPHMONITOR4", - "RXPHOVRDEN": "GTXE2_CHANNEL_RXPHOVRDEN", - "RXPHSLIPMONITOR0": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", - "RXPHSLIPMONITOR1": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", - "RXPHSLIPMONITOR2": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", - "RXPHSLIPMONITOR3": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", - "RXPHSLIPMONITOR4": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", - "RXPMARESET": "GTXE2_CHANNEL_RXPMARESET", - "RXPOLARITY": "GTXE2_CHANNEL_RXPOLARITY", - "RXPRBSCNTRESET": "GTXE2_CHANNEL_RXPRBSCNTRESET", - "RXPRBSERR": "GTXE2_CHANNEL_RXPRBSERR", - "RXPRBSSEL0": "GTXE2_CHANNEL_RXPRBSSEL0", - "RXPRBSSEL1": "GTXE2_CHANNEL_RXPRBSSEL1", - "RXPRBSSEL2": "GTXE2_CHANNEL_RXPRBSSEL2", - "RXQPIEN": "GTXE2_CHANNEL_RXQPIEN", - "RXQPISENN": "GTXE2_CHANNEL_RXQPISENN", - "RXQPISENP": "GTXE2_CHANNEL_RXQPISENP", - "RXRATE0": "GTXE2_CHANNEL_RXRATE0", - "RXRATE1": "GTXE2_CHANNEL_RXRATE1", - "RXRATE2": "GTXE2_CHANNEL_RXRATE2", - "RXRATEDONE": "GTXE2_CHANNEL_RXRATEDONE", - "RXRESETDONE": "GTXE2_CHANNEL_RXRESETDONE", - "RXSLIDE": "GTXE2_CHANNEL_RXSLIDE", - "RXSTARTOFSEQ": "GTXE2_CHANNEL_RXSTARTOFSEQ", - "RXSTATUS0": "GTXE2_CHANNEL_RXSTATUS0", - "RXSTATUS1": "GTXE2_CHANNEL_RXSTATUS1", - "RXSTATUS2": "GTXE2_CHANNEL_RXSTATUS2", - "RXSYSCLKSEL0": "GTXE2_CHANNEL_RXSYSCLKSEL0", - "RXSYSCLKSEL1": "GTXE2_CHANNEL_RXSYSCLKSEL1", - "RXUSERRDY": "GTXE2_CHANNEL_RXUSERRDY", - "RXUSRCLK": "GTXE2_CHANNEL_RXUSRCLK", - "RXUSRCLK2": "GTXE2_CHANNEL_RXUSRCLK2", - "RXVALID": "GTXE2_CHANNEL_RXVALID", - "SCANCLK": "GTXE2_CHANNEL_SCANCLK", - "SCANENB": "GTXE2_CHANNEL_SCANENB", - "SCANIN0": "GTXE2_CHANNEL_SCANIN0", - "SCANIN1": "GTXE2_CHANNEL_SCANIN1", - "SCANIN2": "GTXE2_CHANNEL_SCANIN2", - "SCANIN3": "GTXE2_CHANNEL_SCANIN3", - "SCANIN4": "GTXE2_CHANNEL_SCANIN4", - "SCANMODEB": "GTXE2_CHANNEL_SCANMODEB", - "SCANOUT0": "GTXE2_CHANNEL_SCANOUT0", - "SCANOUT1": "GTXE2_CHANNEL_SCANOUT1", - "SCANOUT2": "GTXE2_CHANNEL_SCANOUT2", - "SCANOUT3": "GTXE2_CHANNEL_SCANOUT3", - "SCANOUT4": "GTXE2_CHANNEL_SCANOUT4", - "SETERRSTATUS": "GTXE2_CHANNEL_SETERRSTATUS", - "TSTCLK0": "GTXE2_CHANNEL_TSTCLK0", - "TSTCLK1": "GTXE2_CHANNEL_TSTCLK1", - "TSTIN0": "GTXE2_CHANNEL_TSTIN0", - "TSTIN1": "GTXE2_CHANNEL_TSTIN1", - "TSTIN10": "GTXE2_CHANNEL_TSTIN10", - "TSTIN11": "GTXE2_CHANNEL_TSTIN11", - "TSTIN12": "GTXE2_CHANNEL_TSTIN12", - "TSTIN13": "GTXE2_CHANNEL_TSTIN13", - "TSTIN14": "GTXE2_CHANNEL_TSTIN14", - "TSTIN15": "GTXE2_CHANNEL_TSTIN15", - "TSTIN16": "GTXE2_CHANNEL_TSTIN16", - "TSTIN17": "GTXE2_CHANNEL_TSTIN17", - "TSTIN18": "GTXE2_CHANNEL_TSTIN18", - "TSTIN19": "GTXE2_CHANNEL_TSTIN19", - "TSTIN2": "GTXE2_CHANNEL_TSTIN2", - "TSTIN3": "GTXE2_CHANNEL_TSTIN3", - "TSTIN4": "GTXE2_CHANNEL_TSTIN4", - "TSTIN5": "GTXE2_CHANNEL_TSTIN5", - "TSTIN6": "GTXE2_CHANNEL_TSTIN6", - "TSTIN7": "GTXE2_CHANNEL_TSTIN7", - "TSTIN8": "GTXE2_CHANNEL_TSTIN8", - "TSTIN9": "GTXE2_CHANNEL_TSTIN9", - "TSTOUT0": "GTXE2_CHANNEL_TSTOUT0", - "TSTOUT1": "GTXE2_CHANNEL_TSTOUT1", - "TSTOUT2": "GTXE2_CHANNEL_TSTOUT2", - "TSTOUT3": "GTXE2_CHANNEL_TSTOUT3", - "TSTOUT4": "GTXE2_CHANNEL_TSTOUT4", - "TSTOUT5": "GTXE2_CHANNEL_TSTOUT5", - "TSTOUT6": "GTXE2_CHANNEL_TSTOUT6", - "TSTOUT7": "GTXE2_CHANNEL_TSTOUT7", - "TSTOUT8": "GTXE2_CHANNEL_TSTOUT8", - "TSTOUT9": "GTXE2_CHANNEL_TSTOUT9", - "TSTPD0": "GTXE2_CHANNEL_TSTPD0", - "TSTPD1": "GTXE2_CHANNEL_TSTPD1", - "TSTPD2": "GTXE2_CHANNEL_TSTPD2", - "TSTPD3": "GTXE2_CHANNEL_TSTPD3", - "TSTPD4": "GTXE2_CHANNEL_TSTPD4", - "TSTPDOVRDB": "GTXE2_CHANNEL_TSTPDOVRDB", - "TX8B10BBYPASS0": "GTXE2_CHANNEL_TX8B10BBYPASS0", - "TX8B10BBYPASS1": "GTXE2_CHANNEL_TX8B10BBYPASS1", - "TX8B10BBYPASS2": "GTXE2_CHANNEL_TX8B10BBYPASS2", - "TX8B10BBYPASS3": "GTXE2_CHANNEL_TX8B10BBYPASS3", - "TX8B10BBYPASS4": "GTXE2_CHANNEL_TX8B10BBYPASS4", - "TX8B10BBYPASS5": "GTXE2_CHANNEL_TX8B10BBYPASS5", - "TX8B10BBYPASS6": "GTXE2_CHANNEL_TX8B10BBYPASS6", - "TX8B10BBYPASS7": "GTXE2_CHANNEL_TX8B10BBYPASS7", - "TX8B10BEN": "GTXE2_CHANNEL_TX8B10BEN", - "TXBUFDIFFCTRL0": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", - "TXBUFDIFFCTRL1": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", - "TXBUFDIFFCTRL2": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", - "TXBUFSTATUS0": "GTXE2_CHANNEL_TXBUFSTATUS0", - "TXBUFSTATUS1": "GTXE2_CHANNEL_TXBUFSTATUS1", - "TXCHARDISPMODE0": "GTXE2_CHANNEL_TXCHARDISPMODE0", - "TXCHARDISPMODE1": "GTXE2_CHANNEL_TXCHARDISPMODE1", - "TXCHARDISPMODE2": "GTXE2_CHANNEL_TXCHARDISPMODE2", - "TXCHARDISPMODE3": "GTXE2_CHANNEL_TXCHARDISPMODE3", - "TXCHARDISPMODE4": "GTXE2_CHANNEL_TXCHARDISPMODE4", - "TXCHARDISPMODE5": "GTXE2_CHANNEL_TXCHARDISPMODE5", - "TXCHARDISPMODE6": "GTXE2_CHANNEL_TXCHARDISPMODE6", - "TXCHARDISPMODE7": "GTXE2_CHANNEL_TXCHARDISPMODE7", - "TXCHARDISPVAL0": "GTXE2_CHANNEL_TXCHARDISPVAL0", - "TXCHARDISPVAL1": "GTXE2_CHANNEL_TXCHARDISPVAL1", - "TXCHARDISPVAL2": "GTXE2_CHANNEL_TXCHARDISPVAL2", - "TXCHARDISPVAL3": "GTXE2_CHANNEL_TXCHARDISPVAL3", - "TXCHARDISPVAL4": "GTXE2_CHANNEL_TXCHARDISPVAL4", - "TXCHARDISPVAL5": "GTXE2_CHANNEL_TXCHARDISPVAL5", - "TXCHARDISPVAL6": "GTXE2_CHANNEL_TXCHARDISPVAL6", - "TXCHARDISPVAL7": "GTXE2_CHANNEL_TXCHARDISPVAL7", - "TXCHARISK0": "GTXE2_CHANNEL_TXCHARISK0", - "TXCHARISK1": "GTXE2_CHANNEL_TXCHARISK1", - "TXCHARISK2": "GTXE2_CHANNEL_TXCHARISK2", - "TXCHARISK3": "GTXE2_CHANNEL_TXCHARISK3", - "TXCHARISK4": "GTXE2_CHANNEL_TXCHARISK4", - "TXCHARISK5": "GTXE2_CHANNEL_TXCHARISK5", - "TXCHARISK6": "GTXE2_CHANNEL_TXCHARISK6", - "TXCHARISK7": "GTXE2_CHANNEL_TXCHARISK7", - "TXCOMFINISH": "GTXE2_CHANNEL_TXCOMFINISH", - "TXCOMINIT": "GTXE2_CHANNEL_TXCOMINIT", - "TXCOMSAS": "GTXE2_CHANNEL_TXCOMSAS", - "TXCOMWAKE": "GTXE2_CHANNEL_TXCOMWAKE", - "TXDATA0": "GTXE2_CHANNEL_TXDATA0", - "TXDATA1": "GTXE2_CHANNEL_TXDATA1", - "TXDATA10": "GTXE2_CHANNEL_TXDATA10", - "TXDATA11": "GTXE2_CHANNEL_TXDATA11", - "TXDATA12": "GTXE2_CHANNEL_TXDATA12", - "TXDATA13": "GTXE2_CHANNEL_TXDATA13", - "TXDATA14": "GTXE2_CHANNEL_TXDATA14", - "TXDATA15": "GTXE2_CHANNEL_TXDATA15", - "TXDATA16": "GTXE2_CHANNEL_TXDATA16", - "TXDATA17": "GTXE2_CHANNEL_TXDATA17", - "TXDATA18": "GTXE2_CHANNEL_TXDATA18", - "TXDATA19": "GTXE2_CHANNEL_TXDATA19", - "TXDATA2": "GTXE2_CHANNEL_TXDATA2", - "TXDATA20": "GTXE2_CHANNEL_TXDATA20", - "TXDATA21": "GTXE2_CHANNEL_TXDATA21", - "TXDATA22": "GTXE2_CHANNEL_TXDATA22", - "TXDATA23": "GTXE2_CHANNEL_TXDATA23", - "TXDATA24": "GTXE2_CHANNEL_TXDATA24", - "TXDATA25": "GTXE2_CHANNEL_TXDATA25", - "TXDATA26": "GTXE2_CHANNEL_TXDATA26", - "TXDATA27": "GTXE2_CHANNEL_TXDATA27", - "TXDATA28": "GTXE2_CHANNEL_TXDATA28", - "TXDATA29": "GTXE2_CHANNEL_TXDATA29", - "TXDATA3": "GTXE2_CHANNEL_TXDATA3", - "TXDATA30": "GTXE2_CHANNEL_TXDATA30", - "TXDATA31": "GTXE2_CHANNEL_TXDATA31", - "TXDATA32": "GTXE2_CHANNEL_TXDATA32", - "TXDATA33": "GTXE2_CHANNEL_TXDATA33", - "TXDATA34": "GTXE2_CHANNEL_TXDATA34", - "TXDATA35": "GTXE2_CHANNEL_TXDATA35", - "TXDATA36": "GTXE2_CHANNEL_TXDATA36", - "TXDATA37": "GTXE2_CHANNEL_TXDATA37", - "TXDATA38": "GTXE2_CHANNEL_TXDATA38", - "TXDATA39": "GTXE2_CHANNEL_TXDATA39", - "TXDATA4": "GTXE2_CHANNEL_TXDATA4", - "TXDATA40": "GTXE2_CHANNEL_TXDATA40", - "TXDATA41": "GTXE2_CHANNEL_TXDATA41", - "TXDATA42": "GTXE2_CHANNEL_TXDATA42", - "TXDATA43": "GTXE2_CHANNEL_TXDATA43", - "TXDATA44": "GTXE2_CHANNEL_TXDATA44", - "TXDATA45": "GTXE2_CHANNEL_TXDATA45", - "TXDATA46": "GTXE2_CHANNEL_TXDATA46", - "TXDATA47": "GTXE2_CHANNEL_TXDATA47", - "TXDATA48": "GTXE2_CHANNEL_TXDATA48", - "TXDATA49": "GTXE2_CHANNEL_TXDATA49", - "TXDATA5": "GTXE2_CHANNEL_TXDATA5", - "TXDATA50": "GTXE2_CHANNEL_TXDATA50", - "TXDATA51": "GTXE2_CHANNEL_TXDATA51", - "TXDATA52": "GTXE2_CHANNEL_TXDATA52", - "TXDATA53": "GTXE2_CHANNEL_TXDATA53", - "TXDATA54": "GTXE2_CHANNEL_TXDATA54", - "TXDATA55": "GTXE2_CHANNEL_TXDATA55", - "TXDATA56": "GTXE2_CHANNEL_TXDATA56", - "TXDATA57": "GTXE2_CHANNEL_TXDATA57", - "TXDATA58": "GTXE2_CHANNEL_TXDATA58", - "TXDATA59": "GTXE2_CHANNEL_TXDATA59", - "TXDATA6": "GTXE2_CHANNEL_TXDATA6", - "TXDATA60": "GTXE2_CHANNEL_TXDATA60", - "TXDATA61": "GTXE2_CHANNEL_TXDATA61", - "TXDATA62": "GTXE2_CHANNEL_TXDATA62", - "TXDATA63": "GTXE2_CHANNEL_TXDATA63", - "TXDATA7": "GTXE2_CHANNEL_TXDATA7", - "TXDATA8": "GTXE2_CHANNEL_TXDATA8", - "TXDATA9": "GTXE2_CHANNEL_TXDATA9", - "TXDEEMPH": "GTXE2_CHANNEL_TXDEEMPH", - "TXDETECTRX": "GTXE2_CHANNEL_TXDETECTRX", - "TXDIFFCTRL0": "GTXE2_CHANNEL_TXDIFFCTRL0", - "TXDIFFCTRL1": "GTXE2_CHANNEL_TXDIFFCTRL1", - "TXDIFFCTRL2": "GTXE2_CHANNEL_TXDIFFCTRL2", - "TXDIFFCTRL3": "GTXE2_CHANNEL_TXDIFFCTRL3", - "TXDIFFPD": "GTXE2_CHANNEL_TXDIFFPD", - "TXDLYBYPASS": "GTXE2_CHANNEL_TXDLYBYPASS", - "TXDLYEN": "GTXE2_CHANNEL_TXDLYEN", - "TXDLYHOLD": "GTXE2_CHANNEL_TXDLYHOLD", - "TXDLYOVRDEN": "GTXE2_CHANNEL_TXDLYOVRDEN", - "TXDLYSRESET": "GTXE2_CHANNEL_TXDLYSRESET", - "TXDLYSRESETDONE": "GTXE2_CHANNEL_TXDLYSRESETDONE", - "TXDLYTESTENB": "GTXE2_CHANNEL_TXDLYTESTENB", - "TXDLYUPDOWN": "GTXE2_CHANNEL_TXDLYUPDOWN", - "TXELECIDLE": "GTXE2_CHANNEL_TXELECIDLE", - "TXGEARBOXREADY": "GTXE2_CHANNEL_TXGEARBOXREADY", - "TXHEADER0": "GTXE2_CHANNEL_TXHEADER0", - "TXHEADER1": "GTXE2_CHANNEL_TXHEADER1", - "TXHEADER2": "GTXE2_CHANNEL_TXHEADER2", - "TXINHIBIT": "GTXE2_CHANNEL_TXINHIBIT", - "TXMAINCURSOR0": "GTXE2_CHANNEL_TXMAINCURSOR0", - "TXMAINCURSOR1": "GTXE2_CHANNEL_TXMAINCURSOR1", - "TXMAINCURSOR2": "GTXE2_CHANNEL_TXMAINCURSOR2", - "TXMAINCURSOR3": "GTXE2_CHANNEL_TXMAINCURSOR3", - "TXMAINCURSOR4": "GTXE2_CHANNEL_TXMAINCURSOR4", - "TXMAINCURSOR5": "GTXE2_CHANNEL_TXMAINCURSOR5", - "TXMAINCURSOR6": "GTXE2_CHANNEL_TXMAINCURSOR6", - "TXMARGIN0": "GTXE2_CHANNEL_TXMARGIN0", - "TXMARGIN1": "GTXE2_CHANNEL_TXMARGIN1", - "TXMARGIN2": "GTXE2_CHANNEL_TXMARGIN2", - "TXOUTCLK": "GTXE2_CHANNEL_GTTXOUTCLK_0", - "TXOUTCLKFABRIC": "GTXE2_CHANNEL_TXOUTCLKFABRIC", - "TXOUTCLKPCS": "GTXE2_CHANNEL_TXOUTCLKPCS", - "TXOUTCLKSEL0": "GTXE2_CHANNEL_TXOUTCLKSEL0", - "TXOUTCLKSEL1": "GTXE2_CHANNEL_TXOUTCLKSEL1", - "TXOUTCLKSEL2": "GTXE2_CHANNEL_TXOUTCLKSEL2", - "TXPCSRESET": "GTXE2_CHANNEL_TXPCSRESET", - "TXPD0": "GTXE2_CHANNEL_TXPD0", - "TXPD1": "GTXE2_CHANNEL_TXPD1", - "TXPDELECIDLEMODE": "GTXE2_CHANNEL_TXPDELECIDLEMODE", - "TXPHALIGN": "GTXE2_CHANNEL_TXPHALIGN", - "TXPHALIGNDONE": "GTXE2_CHANNEL_TXPHALIGNDONE", - "TXPHALIGNEN": "GTXE2_CHANNEL_TXPHALIGNEN", - "TXPHDLYPD": "GTXE2_CHANNEL_TXPHDLYPD", - "TXPHDLYRESET": "GTXE2_CHANNEL_TXPHDLYRESET", - "TXPHDLYTSTCLK": "GTXE2_CHANNEL_TXPHDLYTSTCLK", - "TXPHINIT": "GTXE2_CHANNEL_TXPHINIT", - "TXPHINITDONE": "GTXE2_CHANNEL_TXPHINITDONE", - "TXPHOVRDEN": "GTXE2_CHANNEL_TXPHOVRDEN", - "TXPISOPD": "GTXE2_CHANNEL_TXPISOPD", - "TXPMARESET": "GTXE2_CHANNEL_TXPMARESET", - "TXPOLARITY": "GTXE2_CHANNEL_TXPOLARITY", - "TXPOSTCURSOR0": "GTXE2_CHANNEL_TXPOSTCURSOR0", - "TXPOSTCURSOR1": "GTXE2_CHANNEL_TXPOSTCURSOR1", - "TXPOSTCURSOR2": "GTXE2_CHANNEL_TXPOSTCURSOR2", - "TXPOSTCURSOR3": "GTXE2_CHANNEL_TXPOSTCURSOR3", - "TXPOSTCURSOR4": "GTXE2_CHANNEL_TXPOSTCURSOR4", - "TXPOSTCURSORINV": "GTXE2_CHANNEL_TXPOSTCURSORINV", - "TXPRBSFORCEERR": "GTXE2_CHANNEL_TXPRBSFORCEERR", - "TXPRBSSEL0": "GTXE2_CHANNEL_TXPRBSSEL0", - "TXPRBSSEL1": "GTXE2_CHANNEL_TXPRBSSEL1", - "TXPRBSSEL2": "GTXE2_CHANNEL_TXPRBSSEL2", - "TXPRECURSOR0": "GTXE2_CHANNEL_TXPRECURSOR0", - "TXPRECURSOR1": "GTXE2_CHANNEL_TXPRECURSOR1", - "TXPRECURSOR2": "GTXE2_CHANNEL_TXPRECURSOR2", - "TXPRECURSOR3": "GTXE2_CHANNEL_TXPRECURSOR3", - "TXPRECURSOR4": "GTXE2_CHANNEL_TXPRECURSOR4", - "TXPRECURSORINV": "GTXE2_CHANNEL_TXPRECURSORINV", - "TXQPIBIASEN": "GTXE2_CHANNEL_TXQPIBIASEN", - "TXQPISENN": "GTXE2_CHANNEL_TXQPISENN", - "TXQPISENP": "GTXE2_CHANNEL_TXQPISENP", - "TXQPISTRONGPDOWN": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", - "TXQPIWEAKPUP": "GTXE2_CHANNEL_TXQPIWEAKPUP", - "TXRATE0": "GTXE2_CHANNEL_TXRATE0", - "TXRATE1": "GTXE2_CHANNEL_TXRATE1", - "TXRATE2": "GTXE2_CHANNEL_TXRATE2", - "TXRATEDONE": "GTXE2_CHANNEL_TXRATEDONE", - "TXRESETDONE": "GTXE2_CHANNEL_TXRESETDONE", - "TXRUNDISP0": "GTXE2_CHANNEL_TXRUNDISP0", - "TXRUNDISP1": "GTXE2_CHANNEL_TXRUNDISP1", - "TXRUNDISP2": "GTXE2_CHANNEL_TXRUNDISP2", - "TXRUNDISP3": "GTXE2_CHANNEL_TXRUNDISP3", - "TXRUNDISP4": "GTXE2_CHANNEL_TXRUNDISP4", - "TXRUNDISP5": "GTXE2_CHANNEL_TXRUNDISP5", - "TXRUNDISP6": "GTXE2_CHANNEL_TXRUNDISP6", - "TXRUNDISP7": "GTXE2_CHANNEL_TXRUNDISP7", - "TXSEQUENCE0": "GTXE2_CHANNEL_TXSEQUENCE0", - "TXSEQUENCE1": "GTXE2_CHANNEL_TXSEQUENCE1", - "TXSEQUENCE2": "GTXE2_CHANNEL_TXSEQUENCE2", - "TXSEQUENCE3": "GTXE2_CHANNEL_TXSEQUENCE3", - "TXSEQUENCE4": "GTXE2_CHANNEL_TXSEQUENCE4", - "TXSEQUENCE5": "GTXE2_CHANNEL_TXSEQUENCE5", - "TXSEQUENCE6": "GTXE2_CHANNEL_TXSEQUENCE6", - "TXSTARTSEQ": "GTXE2_CHANNEL_TXSTARTSEQ", - "TXSWING": "GTXE2_CHANNEL_TXSWING", - "TXSYSCLKSEL0": "GTXE2_CHANNEL_TXSYSCLKSEL0", - "TXSYSCLKSEL1": "GTXE2_CHANNEL_TXSYSCLKSEL1", - "TXUSERRDY": "GTXE2_CHANNEL_TXUSERRDY", - "TXUSRCLK": "GTXE2_CHANNEL_TXUSRCLK", - "TXUSRCLK2": "GTXE2_CHANNEL_TXUSRCLK2" + "CFGRESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CFGRESET" + }, + "CLKRSVD0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD0" + }, + "CLKRSVD1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD1" + }, + "CLKRSVD2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD2" + }, + "CLKRSVD3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD3" + }, + "CPLLFBCLKLOST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_CPLLFBCLKLOST" + }, + "CPLLLOCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_CPLLLOCK" + }, + "CPLLLOCKDETCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK" + }, + "CPLLLOCKEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CPLLLOCKEN" + }, + "CPLLPD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CPLLPD" + }, + "CPLLREFCLKLOST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_CPLLREFCLKLOST" + }, + "CPLLREFCLKSEL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0" + }, + "CPLLREFCLKSEL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1" + }, + "CPLLREFCLKSEL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2" + }, + "CPLLRESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CPLLRESET" + }, + "DMONITOROUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DMONITOROUT0" + }, + "DMONITOROUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DMONITOROUT1" + }, + "DMONITOROUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DMONITOROUT2" + }, + "DMONITOROUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DMONITOROUT3" + }, + "DMONITOROUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DMONITOROUT4" + }, + "DMONITOROUT5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DMONITOROUT5" + }, + "DMONITOROUT6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DMONITOROUT6" + }, + "DMONITOROUT7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DMONITOROUT7" + }, + "DRPADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPADDR0" + }, + "DRPADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPADDR1" + }, + "DRPADDR2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPADDR2" + }, + "DRPADDR3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPADDR3" + }, + "DRPADDR4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPADDR4" + }, + "DRPADDR5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPADDR5" + }, + "DRPADDR6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPADDR6" + }, + "DRPADDR7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPADDR7" + }, + "DRPADDR8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPADDR8" + }, + "DRPCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPCLK" + }, + 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"0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPDI15" + }, + "DRPDI2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPDI2" + }, + "DRPDI3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPDI3" + }, + "DRPDI4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPDI4" + }, + "DRPDI5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPDI5" + }, + "DRPDI6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPDI6" + }, + "DRPDI7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPDI7" + }, + "DRPDI8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPDI8" + }, + "DRPDI9": { + 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"0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DRPDO8" + }, + "DRPDO9": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DRPDO9" + }, + "DRPEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPEN" + }, + "DRPRDY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_DRPRDY" + }, + "DRPWE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_DRPWE" + }, + "EDTBYPASS": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_EDTBYPASS" + }, + "EDTCLOCK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_EDTCLOCK" + }, + "EDTCONFIGURATION": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_EDTCONFIGURATION" + }, + "EDTSINGLEBYPASSCHAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN" + }, + "EDTUPDATE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_EDTUPDATE" + }, + "EYESCANDATAERROR": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_EYESCANDATAERROR" + }, + "EYESCANMODE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_EYESCANMODE" + }, + "EYESCANRESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_EYESCANRESET" + }, + "EYESCANTRIGGER": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_EYESCANTRIGGER" + }, + "GTGREFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": 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}, + "TXRESETDONE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRESETDONE" + }, + "TXRUNDISP0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP0" + }, + "TXRUNDISP1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP1" + }, + "TXRUNDISP2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP2" + }, + "TXRUNDISP3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP3" + }, + "TXRUNDISP4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP4" + }, + "TXRUNDISP5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP5" + }, + "TXRUNDISP6": { + "delay": [ + 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"0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE5" + }, + "TXSEQUENCE6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE6" + }, + "TXSTARTSEQ": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSTARTSEQ" + }, + "TXSWING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSWING" + }, + "TXSYSCLKSEL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSYSCLKSEL0" + }, + "TXSYSCLKSEL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSYSCLKSEL1" + }, + "TXUSERRDY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSERRDY" + }, + "TXUSRCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSRCLK" + }, + "TXUSRCLK2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSRCLK2" + } }, "type": "GTXE2_CHANNEL", "x_coord": 0, @@ -5095,7 +18159,16 @@ "name": "X0Y0", "prefix": "IPAD", "site_pins": { - "O": "GTXE2_CHANNEL_RXN_PAD" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "GTXE2_CHANNEL_RXN_PAD" + } }, "type": "IPAD", "x_coord": 0, @@ -5105,7 +18178,16 @@ "name": "X0Y1", "prefix": "IPAD", "site_pins": { - "O": "GTXE2_CHANNEL_RXP_PAD" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "GTXE2_CHANNEL_RXP_PAD" + } }, "type": "IPAD", "x_coord": 0, @@ -5115,7 +18197,16 @@ "name": "X0Y0", "prefix": "OPAD", "site_pins": { - "I": "GTXE2_CHANNEL_TXN_PAD" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXN_PAD" + } }, "type": "OPAD", "x_coord": 0, @@ -5125,7 +18216,16 @@ "name": "X0Y1", "prefix": "OPAD", "site_pins": { - "I": "GTXE2_CHANNEL_TXP_PAD" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXP_PAD" + } }, "type": "OPAD", "x_coord": 0, @@ -5133,1722 +18233,5310 @@ } ], "tile_type": "GTX_CHANNEL_0", - "wires": [ - "GTXE2_BYP0_0", - "GTXE2_BYP0_1", - "GTXE2_BYP0_10", - "GTXE2_BYP0_2", - "GTXE2_BYP0_3", - "GTXE2_BYP0_4", - "GTXE2_BYP0_5", - "GTXE2_BYP0_6", - "GTXE2_BYP0_7", - "GTXE2_BYP0_8", - "GTXE2_BYP0_9", - "GTXE2_BYP1_0", - "GTXE2_BYP1_1", - "GTXE2_BYP1_10", - "GTXE2_BYP1_2", - "GTXE2_BYP1_3", - "GTXE2_BYP1_4", - "GTXE2_BYP1_5", - "GTXE2_BYP1_6", - "GTXE2_BYP1_7", - "GTXE2_BYP1_8", - "GTXE2_BYP1_9", - "GTXE2_BYP2_0", - "GTXE2_BYP2_1", - "GTXE2_BYP2_10", - "GTXE2_BYP2_2", - "GTXE2_BYP2_3", - "GTXE2_BYP2_4", - "GTXE2_BYP2_5", - "GTXE2_BYP2_6", - "GTXE2_BYP2_7", - "GTXE2_BYP2_8", - "GTXE2_BYP2_9", - "GTXE2_BYP3_0", - "GTXE2_BYP3_1", - "GTXE2_BYP3_10", - "GTXE2_BYP3_2", - "GTXE2_BYP3_3", - "GTXE2_BYP3_4", - "GTXE2_BYP3_5", - "GTXE2_BYP3_6", - "GTXE2_BYP3_7", - "GTXE2_BYP3_8", - "GTXE2_BYP3_9", - "GTXE2_BYP4_0", - "GTXE2_BYP4_1", - "GTXE2_BYP4_10", - "GTXE2_BYP4_2", - "GTXE2_BYP4_3", - "GTXE2_BYP4_4", - "GTXE2_BYP4_5", - "GTXE2_BYP4_6", - "GTXE2_BYP4_7", - "GTXE2_BYP4_8", - "GTXE2_BYP4_9", - "GTXE2_BYP5_0", - "GTXE2_BYP5_1", - "GTXE2_BYP5_10", - "GTXE2_BYP5_2", - "GTXE2_BYP5_3", - "GTXE2_BYP5_4", - "GTXE2_BYP5_5", - "GTXE2_BYP5_6", - "GTXE2_BYP5_7", - "GTXE2_BYP5_8", - "GTXE2_BYP5_9", - "GTXE2_BYP6_0", - "GTXE2_BYP6_1", - "GTXE2_BYP6_10", - "GTXE2_BYP6_2", - "GTXE2_BYP6_3", - "GTXE2_BYP6_4", - "GTXE2_BYP6_5", - "GTXE2_BYP6_6", - "GTXE2_BYP6_7", - "GTXE2_BYP6_8", - "GTXE2_BYP6_9", - "GTXE2_BYP7_0", - "GTXE2_BYP7_1", - "GTXE2_BYP7_10", - "GTXE2_BYP7_2", - "GTXE2_BYP7_3", - "GTXE2_BYP7_4", - "GTXE2_BYP7_5", - "GTXE2_BYP7_6", - "GTXE2_BYP7_7", - "GTXE2_BYP7_8", - "GTXE2_BYP7_9", - "GTXE2_CHANNEL_CFGRESET", - "GTXE2_CHANNEL_CLKRSVD0", - "GTXE2_CHANNEL_CLKRSVD1", - "GTXE2_CHANNEL_CLKRSVD2", - "GTXE2_CHANNEL_CLKRSVD3", - "GTXE2_CHANNEL_CPLLFBCLKLOST", - "GTXE2_CHANNEL_CPLLLOCK", - "GTXE2_CHANNEL_CPLLLOCKDETCLK", - "GTXE2_CHANNEL_CPLLLOCKEN", - "GTXE2_CHANNEL_CPLLPD", - "GTXE2_CHANNEL_CPLLREFCLKLOST", - "GTXE2_CHANNEL_CPLLREFCLKSEL0", - "GTXE2_CHANNEL_CPLLREFCLKSEL1", - "GTXE2_CHANNEL_CPLLREFCLKSEL2", - "GTXE2_CHANNEL_CPLLRESET", - "GTXE2_CHANNEL_DMONITOROUT0", - "GTXE2_CHANNEL_DMONITOROUT1", - "GTXE2_CHANNEL_DMONITOROUT2", - "GTXE2_CHANNEL_DMONITOROUT3", - "GTXE2_CHANNEL_DMONITOROUT4", - "GTXE2_CHANNEL_DMONITOROUT5", - "GTXE2_CHANNEL_DMONITOROUT6", - "GTXE2_CHANNEL_DMONITOROUT7", - "GTXE2_CHANNEL_DRPADDR0", - "GTXE2_CHANNEL_DRPADDR1", - "GTXE2_CHANNEL_DRPADDR2", - "GTXE2_CHANNEL_DRPADDR3", - "GTXE2_CHANNEL_DRPADDR4", - "GTXE2_CHANNEL_DRPADDR5", - "GTXE2_CHANNEL_DRPADDR6", - "GTXE2_CHANNEL_DRPADDR7", - "GTXE2_CHANNEL_DRPADDR8", - "GTXE2_CHANNEL_DRPCLK", - "GTXE2_CHANNEL_DRPDI0", - "GTXE2_CHANNEL_DRPDI1", - "GTXE2_CHANNEL_DRPDI10", - "GTXE2_CHANNEL_DRPDI11", - "GTXE2_CHANNEL_DRPDI12", - "GTXE2_CHANNEL_DRPDI13", - "GTXE2_CHANNEL_DRPDI14", - "GTXE2_CHANNEL_DRPDI15", - "GTXE2_CHANNEL_DRPDI2", - "GTXE2_CHANNEL_DRPDI3", - "GTXE2_CHANNEL_DRPDI4", - "GTXE2_CHANNEL_DRPDI5", - "GTXE2_CHANNEL_DRPDI6", - "GTXE2_CHANNEL_DRPDI7", - "GTXE2_CHANNEL_DRPDI8", - "GTXE2_CHANNEL_DRPDI9", - "GTXE2_CHANNEL_DRPDO0", - "GTXE2_CHANNEL_DRPDO1", - "GTXE2_CHANNEL_DRPDO10", - "GTXE2_CHANNEL_DRPDO11", - "GTXE2_CHANNEL_DRPDO12", - "GTXE2_CHANNEL_DRPDO13", - "GTXE2_CHANNEL_DRPDO14", - "GTXE2_CHANNEL_DRPDO15", - "GTXE2_CHANNEL_DRPDO2", - "GTXE2_CHANNEL_DRPDO3", - "GTXE2_CHANNEL_DRPDO4", - "GTXE2_CHANNEL_DRPDO5", - "GTXE2_CHANNEL_DRPDO6", - "GTXE2_CHANNEL_DRPDO7", - "GTXE2_CHANNEL_DRPDO8", - "GTXE2_CHANNEL_DRPDO9", - "GTXE2_CHANNEL_DRPEN", - "GTXE2_CHANNEL_DRPRDY", - "GTXE2_CHANNEL_DRPWE", - "GTXE2_CHANNEL_EDTBYPASS", - "GTXE2_CHANNEL_EDTCLOCK", - "GTXE2_CHANNEL_EDTCONFIGURATION", - "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", - "GTXE2_CHANNEL_EDTUPDATE", - "GTXE2_CHANNEL_EYESCANDATAERROR", - "GTXE2_CHANNEL_EYESCANMODE", - "GTXE2_CHANNEL_EYESCANRESET", - "GTXE2_CHANNEL_EYESCANTRIGGER", - "GTXE2_CHANNEL_GTGREFCLK", - "GTXE2_CHANNEL_GTNORTHREFCLK0", - "GTXE2_CHANNEL_GTNORTHREFCLK1", - "GTXE2_CHANNEL_GTQPLLCLK", - "GTXE2_CHANNEL_GTQPLLREFCLK", - "GTXE2_CHANNEL_GTREFCLK0", - "GTXE2_CHANNEL_GTREFCLK1", - "GTXE2_CHANNEL_GTREFCLKMONITOR", - "GTXE2_CHANNEL_GTRESETSEL", - "GTXE2_CHANNEL_GTRSVD0", - "GTXE2_CHANNEL_GTRSVD1", - "GTXE2_CHANNEL_GTRSVD10", - "GTXE2_CHANNEL_GTRSVD11", - "GTXE2_CHANNEL_GTRSVD12", - "GTXE2_CHANNEL_GTRSVD13", - "GTXE2_CHANNEL_GTRSVD14", - "GTXE2_CHANNEL_GTRSVD15", - "GTXE2_CHANNEL_GTRSVD2", - "GTXE2_CHANNEL_GTRSVD3", - "GTXE2_CHANNEL_GTRSVD4", - "GTXE2_CHANNEL_GTRSVD5", - "GTXE2_CHANNEL_GTRSVD6", - "GTXE2_CHANNEL_GTRSVD7", - "GTXE2_CHANNEL_GTRSVD8", - "GTXE2_CHANNEL_GTRSVD9", - "GTXE2_CHANNEL_GTRXOUTCLK_0", - "GTXE2_CHANNEL_GTRXRESET", - "GTXE2_CHANNEL_GTSOUTHREFCLK0", - "GTXE2_CHANNEL_GTSOUTHREFCLK1", - "GTXE2_CHANNEL_GTTXOUTCLK_0", - "GTXE2_CHANNEL_GTTXRESET", - "GTXE2_CHANNEL_LOOPBACK0", - "GTXE2_CHANNEL_LOOPBACK1", - "GTXE2_CHANNEL_LOOPBACK2", - "GTXE2_CHANNEL_NORTHREFCLK0", - "GTXE2_CHANNEL_NORTHREFCLK1", - "GTXE2_CHANNEL_PCSRSVDIN0", - "GTXE2_CHANNEL_PCSRSVDIN1", - "GTXE2_CHANNEL_PCSRSVDIN10", - "GTXE2_CHANNEL_PCSRSVDIN11", - "GTXE2_CHANNEL_PCSRSVDIN12", - "GTXE2_CHANNEL_PCSRSVDIN13", - "GTXE2_CHANNEL_PCSRSVDIN14", - "GTXE2_CHANNEL_PCSRSVDIN15", - "GTXE2_CHANNEL_PCSRSVDIN2", - "GTXE2_CHANNEL_PCSRSVDIN20", - "GTXE2_CHANNEL_PCSRSVDIN21", - "GTXE2_CHANNEL_PCSRSVDIN22", - "GTXE2_CHANNEL_PCSRSVDIN23", - "GTXE2_CHANNEL_PCSRSVDIN24", - "GTXE2_CHANNEL_PCSRSVDIN3", - "GTXE2_CHANNEL_PCSRSVDIN4", - "GTXE2_CHANNEL_PCSRSVDIN5", - "GTXE2_CHANNEL_PCSRSVDIN6", - "GTXE2_CHANNEL_PCSRSVDIN7", - "GTXE2_CHANNEL_PCSRSVDIN8", - "GTXE2_CHANNEL_PCSRSVDIN9", - "GTXE2_CHANNEL_PCSRSVDOUT0", - "GTXE2_CHANNEL_PCSRSVDOUT1", - "GTXE2_CHANNEL_PCSRSVDOUT10", - "GTXE2_CHANNEL_PCSRSVDOUT11", - "GTXE2_CHANNEL_PCSRSVDOUT12", - "GTXE2_CHANNEL_PCSRSVDOUT13", - "GTXE2_CHANNEL_PCSRSVDOUT14", - "GTXE2_CHANNEL_PCSRSVDOUT15", - "GTXE2_CHANNEL_PCSRSVDOUT2", - "GTXE2_CHANNEL_PCSRSVDOUT3", - "GTXE2_CHANNEL_PCSRSVDOUT4", - "GTXE2_CHANNEL_PCSRSVDOUT5", - "GTXE2_CHANNEL_PCSRSVDOUT6", - "GTXE2_CHANNEL_PCSRSVDOUT7", - "GTXE2_CHANNEL_PCSRSVDOUT8", - "GTXE2_CHANNEL_PCSRSVDOUT9", - "GTXE2_CHANNEL_PHYSTATUS", - "GTXE2_CHANNEL_PMARSVDIN0", - "GTXE2_CHANNEL_PMARSVDIN1", - "GTXE2_CHANNEL_PMARSVDIN2", - "GTXE2_CHANNEL_PMARSVDIN20", - "GTXE2_CHANNEL_PMARSVDIN21", - "GTXE2_CHANNEL_PMARSVDIN22", - "GTXE2_CHANNEL_PMARSVDIN23", - "GTXE2_CHANNEL_PMARSVDIN24", - "GTXE2_CHANNEL_PMARSVDIN3", - "GTXE2_CHANNEL_PMARSVDIN4", - "GTXE2_CHANNEL_PMASCANCLK0", - "GTXE2_CHANNEL_PMASCANCLK1", - "GTXE2_CHANNEL_PMASCANCLK2", - "GTXE2_CHANNEL_PMASCANCLK3", - "GTXE2_CHANNEL_PMASCANCLK4", - "GTXE2_CHANNEL_PMASCANENB", - "GTXE2_CHANNEL_PMASCANIN0", - "GTXE2_CHANNEL_PMASCANIN1", - "GTXE2_CHANNEL_PMASCANIN2", - "GTXE2_CHANNEL_PMASCANIN3", - "GTXE2_CHANNEL_PMASCANIN4", - "GTXE2_CHANNEL_PMASCANMODEB", - "GTXE2_CHANNEL_PMASCANOUT0", - "GTXE2_CHANNEL_PMASCANOUT1", - "GTXE2_CHANNEL_PMASCANOUT2", - "GTXE2_CHANNEL_PMASCANOUT3", - "GTXE2_CHANNEL_PMASCANOUT4", - "GTXE2_CHANNEL_PMASCANRSTEN", - "GTXE2_CHANNEL_QPLLCLK", - "GTXE2_CHANNEL_QPLLREFCLK", - "GTXE2_CHANNEL_REFCLK0", - "GTXE2_CHANNEL_REFCLK1", - "GTXE2_CHANNEL_RESETOVRD", - "GTXE2_CHANNEL_RX8B10BEN", - "GTXE2_CHANNEL_RXBUFRESET", - "GTXE2_CHANNEL_RXBUFSTATUS0", - "GTXE2_CHANNEL_RXBUFSTATUS1", - "GTXE2_CHANNEL_RXBUFSTATUS2", - "GTXE2_CHANNEL_RXBYTEISALIGNED", - "GTXE2_CHANNEL_RXBYTEREALIGN", - "GTXE2_CHANNEL_RXCDRFREQRESET", - "GTXE2_CHANNEL_RXCDRHOLD", - "GTXE2_CHANNEL_RXCDRLOCK", - "GTXE2_CHANNEL_RXCDROVRDEN", - "GTXE2_CHANNEL_RXCDRRESET", - "GTXE2_CHANNEL_RXCDRRESETRSV", - "GTXE2_CHANNEL_RXCHANBONDSEQ", - "GTXE2_CHANNEL_RXCHANISALIGNED", - "GTXE2_CHANNEL_RXCHANREALIGN", - "GTXE2_CHANNEL_RXCHARISCOMMA0", - "GTXE2_CHANNEL_RXCHARISCOMMA1", - "GTXE2_CHANNEL_RXCHARISCOMMA2", - "GTXE2_CHANNEL_RXCHARISCOMMA3", - "GTXE2_CHANNEL_RXCHARISCOMMA4", - "GTXE2_CHANNEL_RXCHARISCOMMA5", - "GTXE2_CHANNEL_RXCHARISCOMMA6", - "GTXE2_CHANNEL_RXCHARISCOMMA7", - "GTXE2_CHANNEL_RXCHARISK0", - "GTXE2_CHANNEL_RXCHARISK1", - "GTXE2_CHANNEL_RXCHARISK2", - "GTXE2_CHANNEL_RXCHARISK3", - "GTXE2_CHANNEL_RXCHARISK4", - "GTXE2_CHANNEL_RXCHARISK5", - "GTXE2_CHANNEL_RXCHARISK6", - "GTXE2_CHANNEL_RXCHARISK7", - "GTXE2_CHANNEL_RXCHBONDEN", - "GTXE2_CHANNEL_RXCHBONDI0", - "GTXE2_CHANNEL_RXCHBONDI1", - "GTXE2_CHANNEL_RXCHBONDI2", - "GTXE2_CHANNEL_RXCHBONDI3", - "GTXE2_CHANNEL_RXCHBONDI4", - "GTXE2_CHANNEL_RXCHBONDLEVEL0", - "GTXE2_CHANNEL_RXCHBONDLEVEL1", - "GTXE2_CHANNEL_RXCHBONDLEVEL2", - "GTXE2_CHANNEL_RXCHBONDMASTER", - "GTXE2_CHANNEL_RXCHBONDO0", - "GTXE2_CHANNEL_RXCHBONDO1", - "GTXE2_CHANNEL_RXCHBONDO2", - "GTXE2_CHANNEL_RXCHBONDO3", - "GTXE2_CHANNEL_RXCHBONDO4", - "GTXE2_CHANNEL_RXCHBONDSLAVE", - "GTXE2_CHANNEL_RXCLKCORCNT0", - "GTXE2_CHANNEL_RXCLKCORCNT1", - "GTXE2_CHANNEL_RXCOMINITDET", - "GTXE2_CHANNEL_RXCOMMADET", - "GTXE2_CHANNEL_RXCOMMADETEN", - "GTXE2_CHANNEL_RXCOMSASDET", - "GTXE2_CHANNEL_RXCOMWAKEDET", - "GTXE2_CHANNEL_RXDATA0", - "GTXE2_CHANNEL_RXDATA1", - "GTXE2_CHANNEL_RXDATA10", - "GTXE2_CHANNEL_RXDATA11", - "GTXE2_CHANNEL_RXDATA12", - "GTXE2_CHANNEL_RXDATA13", - "GTXE2_CHANNEL_RXDATA14", - "GTXE2_CHANNEL_RXDATA15", - "GTXE2_CHANNEL_RXDATA16", - "GTXE2_CHANNEL_RXDATA17", - "GTXE2_CHANNEL_RXDATA18", - "GTXE2_CHANNEL_RXDATA19", - "GTXE2_CHANNEL_RXDATA2", - "GTXE2_CHANNEL_RXDATA20", - "GTXE2_CHANNEL_RXDATA21", - "GTXE2_CHANNEL_RXDATA22", - "GTXE2_CHANNEL_RXDATA23", - "GTXE2_CHANNEL_RXDATA24", - "GTXE2_CHANNEL_RXDATA25", - "GTXE2_CHANNEL_RXDATA26", - "GTXE2_CHANNEL_RXDATA27", - "GTXE2_CHANNEL_RXDATA28", - "GTXE2_CHANNEL_RXDATA29", - "GTXE2_CHANNEL_RXDATA3", - "GTXE2_CHANNEL_RXDATA30", - "GTXE2_CHANNEL_RXDATA31", - "GTXE2_CHANNEL_RXDATA32", - "GTXE2_CHANNEL_RXDATA33", - "GTXE2_CHANNEL_RXDATA34", - "GTXE2_CHANNEL_RXDATA35", - "GTXE2_CHANNEL_RXDATA36", - "GTXE2_CHANNEL_RXDATA37", - "GTXE2_CHANNEL_RXDATA38", - "GTXE2_CHANNEL_RXDATA39", - "GTXE2_CHANNEL_RXDATA4", - "GTXE2_CHANNEL_RXDATA40", - "GTXE2_CHANNEL_RXDATA41", - "GTXE2_CHANNEL_RXDATA42", - "GTXE2_CHANNEL_RXDATA43", - "GTXE2_CHANNEL_RXDATA44", - "GTXE2_CHANNEL_RXDATA45", - "GTXE2_CHANNEL_RXDATA46", - "GTXE2_CHANNEL_RXDATA47", - "GTXE2_CHANNEL_RXDATA48", - "GTXE2_CHANNEL_RXDATA49", - "GTXE2_CHANNEL_RXDATA5", - "GTXE2_CHANNEL_RXDATA50", - "GTXE2_CHANNEL_RXDATA51", - "GTXE2_CHANNEL_RXDATA52", - "GTXE2_CHANNEL_RXDATA53", - "GTXE2_CHANNEL_RXDATA54", - "GTXE2_CHANNEL_RXDATA55", - "GTXE2_CHANNEL_RXDATA56", - "GTXE2_CHANNEL_RXDATA57", - "GTXE2_CHANNEL_RXDATA58", - "GTXE2_CHANNEL_RXDATA59", - "GTXE2_CHANNEL_RXDATA6", - "GTXE2_CHANNEL_RXDATA60", - "GTXE2_CHANNEL_RXDATA61", - "GTXE2_CHANNEL_RXDATA62", - "GTXE2_CHANNEL_RXDATA63", - "GTXE2_CHANNEL_RXDATA7", - "GTXE2_CHANNEL_RXDATA8", - "GTXE2_CHANNEL_RXDATA9", - "GTXE2_CHANNEL_RXDATAVALID", - "GTXE2_CHANNEL_RXDDIEN", - "GTXE2_CHANNEL_RXDEBUGPULSE", - "GTXE2_CHANNEL_RXDFEAGCHOLD", - "GTXE2_CHANNEL_RXDFEAGCOVRDEN", - "GTXE2_CHANNEL_RXDFECM1EN", - "GTXE2_CHANNEL_RXDFELFHOLD", - "GTXE2_CHANNEL_RXDFELFOVRDEN", - "GTXE2_CHANNEL_RXDFELPMRESET", - "GTXE2_CHANNEL_RXDFETAP2HOLD", - "GTXE2_CHANNEL_RXDFETAP2OVRDEN", - "GTXE2_CHANNEL_RXDFETAP3HOLD", - "GTXE2_CHANNEL_RXDFETAP3OVRDEN", - "GTXE2_CHANNEL_RXDFETAP4HOLD", - "GTXE2_CHANNEL_RXDFETAP4OVRDEN", - "GTXE2_CHANNEL_RXDFETAP5HOLD", - "GTXE2_CHANNEL_RXDFETAP5OVRDEN", - "GTXE2_CHANNEL_RXDFEUTHOLD", - "GTXE2_CHANNEL_RXDFEUTOVRDEN", - "GTXE2_CHANNEL_RXDFEVPHOLD", - "GTXE2_CHANNEL_RXDFEVPOVRDEN", - "GTXE2_CHANNEL_RXDFEVSEN", - "GTXE2_CHANNEL_RXDFEXYDEN", - "GTXE2_CHANNEL_RXDFEXYDHOLD", - "GTXE2_CHANNEL_RXDFEXYDOVRDEN", - "GTXE2_CHANNEL_RXDISPERR0", - "GTXE2_CHANNEL_RXDISPERR1", - "GTXE2_CHANNEL_RXDISPERR2", - "GTXE2_CHANNEL_RXDISPERR3", - "GTXE2_CHANNEL_RXDISPERR4", - "GTXE2_CHANNEL_RXDISPERR5", - "GTXE2_CHANNEL_RXDISPERR6", - "GTXE2_CHANNEL_RXDISPERR7", - "GTXE2_CHANNEL_RXDLYBYPASS", - "GTXE2_CHANNEL_RXDLYEN", - "GTXE2_CHANNEL_RXDLYOVRDEN", - "GTXE2_CHANNEL_RXDLYSRESET", - "GTXE2_CHANNEL_RXDLYSRESETDONE", - "GTXE2_CHANNEL_RXDLYTESTENB", - "GTXE2_CHANNEL_RXELECIDLE", - "GTXE2_CHANNEL_RXELECIDLEMODE0", - "GTXE2_CHANNEL_RXELECIDLEMODE1", - "GTXE2_CHANNEL_RXGEARBOXSLIP", - "GTXE2_CHANNEL_RXHEADER0", - "GTXE2_CHANNEL_RXHEADER1", - "GTXE2_CHANNEL_RXHEADER2", - "GTXE2_CHANNEL_RXHEADERVALID", - "GTXE2_CHANNEL_RXLPMEN", - "GTXE2_CHANNEL_RXLPMHFHOLD", - "GTXE2_CHANNEL_RXLPMHFOVRDEN", - "GTXE2_CHANNEL_RXLPMLFHOLD", - "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", - "GTXE2_CHANNEL_RXMCOMMAALIGNEN", - "GTXE2_CHANNEL_RXMONITOROUT0", - "GTXE2_CHANNEL_RXMONITOROUT1", - "GTXE2_CHANNEL_RXMONITOROUT2", - "GTXE2_CHANNEL_RXMONITOROUT3", - "GTXE2_CHANNEL_RXMONITOROUT4", - "GTXE2_CHANNEL_RXMONITOROUT5", - "GTXE2_CHANNEL_RXMONITOROUT6", - "GTXE2_CHANNEL_RXMONITORSEL0", - "GTXE2_CHANNEL_RXMONITORSEL1", - "GTXE2_CHANNEL_RXN", - "GTXE2_CHANNEL_RXNOTINTABLE0", - "GTXE2_CHANNEL_RXNOTINTABLE1", - "GTXE2_CHANNEL_RXNOTINTABLE2", - "GTXE2_CHANNEL_RXNOTINTABLE3", - "GTXE2_CHANNEL_RXNOTINTABLE4", - "GTXE2_CHANNEL_RXNOTINTABLE5", - "GTXE2_CHANNEL_RXNOTINTABLE6", - "GTXE2_CHANNEL_RXNOTINTABLE7", - "GTXE2_CHANNEL_RXN_PAD", - "GTXE2_CHANNEL_RXOOBRESET", - "GTXE2_CHANNEL_RXOSHOLD", - "GTXE2_CHANNEL_RXOSOVRDEN", - "GTXE2_CHANNEL_RXOUTCLKFABRIC", - "GTXE2_CHANNEL_RXOUTCLKPCS", - "GTXE2_CHANNEL_RXOUTCLKSEL0", - "GTXE2_CHANNEL_RXOUTCLKSEL1", - "GTXE2_CHANNEL_RXOUTCLKSEL2", - "GTXE2_CHANNEL_RXOUTCLK_0", - "GTXE2_CHANNEL_RXOUTCLK_1", - "GTXE2_CHANNEL_RXOUTCLK_2", - "GTXE2_CHANNEL_RXOUTCLK_3", - "GTXE2_CHANNEL_RXP", - "GTXE2_CHANNEL_RXPCD1DONE", - "GTXE2_CHANNEL_RXPCOMMAALIGNEN", - "GTXE2_CHANNEL_RXPCSRESET", - "GTXE2_CHANNEL_RXPD0", - "GTXE2_CHANNEL_RXPD1", - "GTXE2_CHANNEL_RXPHALIGN", - "GTXE2_CHANNEL_RXPHALIGNDONE", - "GTXE2_CHANNEL_RXPHALIGNEN", - "GTXE2_CHANNEL_RXPHDLYPD", - "GTXE2_CHANNEL_RXPHDLYRESET", - "GTXE2_CHANNEL_RXPHMONITOR0", - "GTXE2_CHANNEL_RXPHMONITOR1", - "GTXE2_CHANNEL_RXPHMONITOR2", - "GTXE2_CHANNEL_RXPHMONITOR3", - "GTXE2_CHANNEL_RXPHMONITOR4", - "GTXE2_CHANNEL_RXPHOVRDEN", - "GTXE2_CHANNEL_RXPHSLIPMONITOR0", - "GTXE2_CHANNEL_RXPHSLIPMONITOR1", - "GTXE2_CHANNEL_RXPHSLIPMONITOR2", - "GTXE2_CHANNEL_RXPHSLIPMONITOR3", - "GTXE2_CHANNEL_RXPHSLIPMONITOR4", - "GTXE2_CHANNEL_RXPMARESET", - "GTXE2_CHANNEL_RXPOLARITY", - "GTXE2_CHANNEL_RXPRBSCNTRESET", - "GTXE2_CHANNEL_RXPRBSERR", - "GTXE2_CHANNEL_RXPRBSSEL0", - "GTXE2_CHANNEL_RXPRBSSEL1", - "GTXE2_CHANNEL_RXPRBSSEL2", - "GTXE2_CHANNEL_RXP_PAD", - "GTXE2_CHANNEL_RXQPIEN", - "GTXE2_CHANNEL_RXQPISENN", - "GTXE2_CHANNEL_RXQPISENP", - "GTXE2_CHANNEL_RXRATE0", - "GTXE2_CHANNEL_RXRATE1", - "GTXE2_CHANNEL_RXRATE2", - "GTXE2_CHANNEL_RXRATEDONE", - "GTXE2_CHANNEL_RXRESETDONE", - "GTXE2_CHANNEL_RXSLIDE", - "GTXE2_CHANNEL_RXSTARTOFSEQ", - "GTXE2_CHANNEL_RXSTATUS0", - "GTXE2_CHANNEL_RXSTATUS1", - "GTXE2_CHANNEL_RXSTATUS2", - "GTXE2_CHANNEL_RXSYSCLKSEL0", - "GTXE2_CHANNEL_RXSYSCLKSEL1", - "GTXE2_CHANNEL_RXUSERRDY", - "GTXE2_CHANNEL_RXUSRCLK", - "GTXE2_CHANNEL_RXUSRCLK2", - "GTXE2_CHANNEL_RXVALID", - "GTXE2_CHANNEL_SCANCLK", - "GTXE2_CHANNEL_SCANENB", - "GTXE2_CHANNEL_SCANIN0", - "GTXE2_CHANNEL_SCANIN1", - "GTXE2_CHANNEL_SCANIN2", - "GTXE2_CHANNEL_SCANIN3", - "GTXE2_CHANNEL_SCANIN4", - "GTXE2_CHANNEL_SCANMODEB", - "GTXE2_CHANNEL_SCANOUT0", - "GTXE2_CHANNEL_SCANOUT1", - "GTXE2_CHANNEL_SCANOUT2", - "GTXE2_CHANNEL_SCANOUT3", - "GTXE2_CHANNEL_SCANOUT4", - "GTXE2_CHANNEL_SETERRSTATUS", - "GTXE2_CHANNEL_SOUTHREFCLK0", - "GTXE2_CHANNEL_SOUTHREFCLK1", - "GTXE2_CHANNEL_TSTCLK0", - "GTXE2_CHANNEL_TSTCLK1", - "GTXE2_CHANNEL_TSTIN0", - "GTXE2_CHANNEL_TSTIN1", - "GTXE2_CHANNEL_TSTIN10", - "GTXE2_CHANNEL_TSTIN11", - "GTXE2_CHANNEL_TSTIN12", - "GTXE2_CHANNEL_TSTIN13", - "GTXE2_CHANNEL_TSTIN14", - "GTXE2_CHANNEL_TSTIN15", - "GTXE2_CHANNEL_TSTIN16", - "GTXE2_CHANNEL_TSTIN17", - "GTXE2_CHANNEL_TSTIN18", - "GTXE2_CHANNEL_TSTIN19", - "GTXE2_CHANNEL_TSTIN2", - "GTXE2_CHANNEL_TSTIN3", - "GTXE2_CHANNEL_TSTIN4", - "GTXE2_CHANNEL_TSTIN5", - "GTXE2_CHANNEL_TSTIN6", - "GTXE2_CHANNEL_TSTIN7", - "GTXE2_CHANNEL_TSTIN8", - "GTXE2_CHANNEL_TSTIN9", - "GTXE2_CHANNEL_TSTOUT0", - "GTXE2_CHANNEL_TSTOUT1", - "GTXE2_CHANNEL_TSTOUT2", - "GTXE2_CHANNEL_TSTOUT3", - "GTXE2_CHANNEL_TSTOUT4", - "GTXE2_CHANNEL_TSTOUT5", - "GTXE2_CHANNEL_TSTOUT6", - "GTXE2_CHANNEL_TSTOUT7", - "GTXE2_CHANNEL_TSTOUT8", - "GTXE2_CHANNEL_TSTOUT9", - "GTXE2_CHANNEL_TSTPD0", - "GTXE2_CHANNEL_TSTPD1", - "GTXE2_CHANNEL_TSTPD2", - "GTXE2_CHANNEL_TSTPD3", - "GTXE2_CHANNEL_TSTPD4", - "GTXE2_CHANNEL_TSTPDOVRDB", - "GTXE2_CHANNEL_TX8B10BBYPASS0", - "GTXE2_CHANNEL_TX8B10BBYPASS1", - "GTXE2_CHANNEL_TX8B10BBYPASS2", - "GTXE2_CHANNEL_TX8B10BBYPASS3", - "GTXE2_CHANNEL_TX8B10BBYPASS4", - "GTXE2_CHANNEL_TX8B10BBYPASS5", - "GTXE2_CHANNEL_TX8B10BBYPASS6", - "GTXE2_CHANNEL_TX8B10BBYPASS7", - "GTXE2_CHANNEL_TX8B10BEN", - "GTXE2_CHANNEL_TXBUFDIFFCTRL0", - "GTXE2_CHANNEL_TXBUFDIFFCTRL1", - "GTXE2_CHANNEL_TXBUFDIFFCTRL2", - "GTXE2_CHANNEL_TXBUFSTATUS0", - "GTXE2_CHANNEL_TXBUFSTATUS1", - "GTXE2_CHANNEL_TXCHARDISPMODE0", - "GTXE2_CHANNEL_TXCHARDISPMODE1", - "GTXE2_CHANNEL_TXCHARDISPMODE2", - "GTXE2_CHANNEL_TXCHARDISPMODE3", - "GTXE2_CHANNEL_TXCHARDISPMODE4", - "GTXE2_CHANNEL_TXCHARDISPMODE5", - "GTXE2_CHANNEL_TXCHARDISPMODE6", - "GTXE2_CHANNEL_TXCHARDISPMODE7", - "GTXE2_CHANNEL_TXCHARDISPVAL0", - "GTXE2_CHANNEL_TXCHARDISPVAL1", - "GTXE2_CHANNEL_TXCHARDISPVAL2", - "GTXE2_CHANNEL_TXCHARDISPVAL3", - "GTXE2_CHANNEL_TXCHARDISPVAL4", - "GTXE2_CHANNEL_TXCHARDISPVAL5", - "GTXE2_CHANNEL_TXCHARDISPVAL6", - "GTXE2_CHANNEL_TXCHARDISPVAL7", - "GTXE2_CHANNEL_TXCHARISK0", - "GTXE2_CHANNEL_TXCHARISK1", - "GTXE2_CHANNEL_TXCHARISK2", - "GTXE2_CHANNEL_TXCHARISK3", - "GTXE2_CHANNEL_TXCHARISK4", - "GTXE2_CHANNEL_TXCHARISK5", - "GTXE2_CHANNEL_TXCHARISK6", - "GTXE2_CHANNEL_TXCHARISK7", - "GTXE2_CHANNEL_TXCOMFINISH", - "GTXE2_CHANNEL_TXCOMINIT", - "GTXE2_CHANNEL_TXCOMSAS", - "GTXE2_CHANNEL_TXCOMWAKE", - "GTXE2_CHANNEL_TXDATA0", - "GTXE2_CHANNEL_TXDATA1", - "GTXE2_CHANNEL_TXDATA10", - "GTXE2_CHANNEL_TXDATA11", - "GTXE2_CHANNEL_TXDATA12", - "GTXE2_CHANNEL_TXDATA13", - "GTXE2_CHANNEL_TXDATA14", - "GTXE2_CHANNEL_TXDATA15", - "GTXE2_CHANNEL_TXDATA16", - "GTXE2_CHANNEL_TXDATA17", - "GTXE2_CHANNEL_TXDATA18", - "GTXE2_CHANNEL_TXDATA19", - "GTXE2_CHANNEL_TXDATA2", - "GTXE2_CHANNEL_TXDATA20", - "GTXE2_CHANNEL_TXDATA21", - "GTXE2_CHANNEL_TXDATA22", - "GTXE2_CHANNEL_TXDATA23", - "GTXE2_CHANNEL_TXDATA24", - "GTXE2_CHANNEL_TXDATA25", - "GTXE2_CHANNEL_TXDATA26", - "GTXE2_CHANNEL_TXDATA27", - "GTXE2_CHANNEL_TXDATA28", - "GTXE2_CHANNEL_TXDATA29", - "GTXE2_CHANNEL_TXDATA3", - "GTXE2_CHANNEL_TXDATA30", - "GTXE2_CHANNEL_TXDATA31", - "GTXE2_CHANNEL_TXDATA32", - "GTXE2_CHANNEL_TXDATA33", - "GTXE2_CHANNEL_TXDATA34", - "GTXE2_CHANNEL_TXDATA35", - "GTXE2_CHANNEL_TXDATA36", - "GTXE2_CHANNEL_TXDATA37", - "GTXE2_CHANNEL_TXDATA38", - "GTXE2_CHANNEL_TXDATA39", - "GTXE2_CHANNEL_TXDATA4", - "GTXE2_CHANNEL_TXDATA40", - "GTXE2_CHANNEL_TXDATA41", - "GTXE2_CHANNEL_TXDATA42", - "GTXE2_CHANNEL_TXDATA43", - "GTXE2_CHANNEL_TXDATA44", - "GTXE2_CHANNEL_TXDATA45", - "GTXE2_CHANNEL_TXDATA46", - "GTXE2_CHANNEL_TXDATA47", - "GTXE2_CHANNEL_TXDATA48", - "GTXE2_CHANNEL_TXDATA49", - "GTXE2_CHANNEL_TXDATA5", - "GTXE2_CHANNEL_TXDATA50", - "GTXE2_CHANNEL_TXDATA51", - "GTXE2_CHANNEL_TXDATA52", - "GTXE2_CHANNEL_TXDATA53", - "GTXE2_CHANNEL_TXDATA54", - "GTXE2_CHANNEL_TXDATA55", - "GTXE2_CHANNEL_TXDATA56", - "GTXE2_CHANNEL_TXDATA57", - "GTXE2_CHANNEL_TXDATA58", - "GTXE2_CHANNEL_TXDATA59", - "GTXE2_CHANNEL_TXDATA6", - "GTXE2_CHANNEL_TXDATA60", - "GTXE2_CHANNEL_TXDATA61", - "GTXE2_CHANNEL_TXDATA62", - "GTXE2_CHANNEL_TXDATA63", - "GTXE2_CHANNEL_TXDATA7", - "GTXE2_CHANNEL_TXDATA8", - "GTXE2_CHANNEL_TXDATA9", - "GTXE2_CHANNEL_TXDEEMPH", - "GTXE2_CHANNEL_TXDETECTRX", - "GTXE2_CHANNEL_TXDIFFCTRL0", - "GTXE2_CHANNEL_TXDIFFCTRL1", - "GTXE2_CHANNEL_TXDIFFCTRL2", - "GTXE2_CHANNEL_TXDIFFCTRL3", - "GTXE2_CHANNEL_TXDIFFPD", - "GTXE2_CHANNEL_TXDLYBYPASS", - "GTXE2_CHANNEL_TXDLYEN", - "GTXE2_CHANNEL_TXDLYHOLD", - "GTXE2_CHANNEL_TXDLYOVRDEN", - "GTXE2_CHANNEL_TXDLYSRESET", - "GTXE2_CHANNEL_TXDLYSRESETDONE", - "GTXE2_CHANNEL_TXDLYTESTENB", - "GTXE2_CHANNEL_TXDLYUPDOWN", - "GTXE2_CHANNEL_TXELECIDLE", - "GTXE2_CHANNEL_TXGEARBOXREADY", - "GTXE2_CHANNEL_TXHEADER0", - "GTXE2_CHANNEL_TXHEADER1", - "GTXE2_CHANNEL_TXHEADER2", - "GTXE2_CHANNEL_TXINHIBIT", - "GTXE2_CHANNEL_TXMAINCURSOR0", - "GTXE2_CHANNEL_TXMAINCURSOR1", - "GTXE2_CHANNEL_TXMAINCURSOR2", - "GTXE2_CHANNEL_TXMAINCURSOR3", - "GTXE2_CHANNEL_TXMAINCURSOR4", - "GTXE2_CHANNEL_TXMAINCURSOR5", - "GTXE2_CHANNEL_TXMAINCURSOR6", - "GTXE2_CHANNEL_TXMARGIN0", - "GTXE2_CHANNEL_TXMARGIN1", - "GTXE2_CHANNEL_TXMARGIN2", - "GTXE2_CHANNEL_TXN", - "GTXE2_CHANNEL_TXN_PAD", - "GTXE2_CHANNEL_TXOUTCLKFABRIC", - "GTXE2_CHANNEL_TXOUTCLKPCS", - "GTXE2_CHANNEL_TXOUTCLKSEL0", - "GTXE2_CHANNEL_TXOUTCLKSEL1", - "GTXE2_CHANNEL_TXOUTCLKSEL2", - "GTXE2_CHANNEL_TXOUTCLK_0", - "GTXE2_CHANNEL_TXOUTCLK_1", - "GTXE2_CHANNEL_TXOUTCLK_2", - "GTXE2_CHANNEL_TXOUTCLK_3", - "GTXE2_CHANNEL_TXP", - "GTXE2_CHANNEL_TXPCSRESET", - "GTXE2_CHANNEL_TXPD0", - "GTXE2_CHANNEL_TXPD1", - "GTXE2_CHANNEL_TXPDELECIDLEMODE", - "GTXE2_CHANNEL_TXPHALIGN", - "GTXE2_CHANNEL_TXPHALIGNDONE", - "GTXE2_CHANNEL_TXPHALIGNEN", - "GTXE2_CHANNEL_TXPHDLYPD", - "GTXE2_CHANNEL_TXPHDLYRESET", - "GTXE2_CHANNEL_TXPHDLYTSTCLK", - "GTXE2_CHANNEL_TXPHINIT", - "GTXE2_CHANNEL_TXPHINITDONE", - "GTXE2_CHANNEL_TXPHOVRDEN", - "GTXE2_CHANNEL_TXPISOPD", - "GTXE2_CHANNEL_TXPMARESET", - "GTXE2_CHANNEL_TXPOLARITY", - "GTXE2_CHANNEL_TXPOSTCURSOR0", - "GTXE2_CHANNEL_TXPOSTCURSOR1", - "GTXE2_CHANNEL_TXPOSTCURSOR2", - "GTXE2_CHANNEL_TXPOSTCURSOR3", - "GTXE2_CHANNEL_TXPOSTCURSOR4", - "GTXE2_CHANNEL_TXPOSTCURSORINV", - "GTXE2_CHANNEL_TXPRBSFORCEERR", - "GTXE2_CHANNEL_TXPRBSSEL0", - "GTXE2_CHANNEL_TXPRBSSEL1", - "GTXE2_CHANNEL_TXPRBSSEL2", - "GTXE2_CHANNEL_TXPRECURSOR0", - "GTXE2_CHANNEL_TXPRECURSOR1", - "GTXE2_CHANNEL_TXPRECURSOR2", - "GTXE2_CHANNEL_TXPRECURSOR3", - "GTXE2_CHANNEL_TXPRECURSOR4", - "GTXE2_CHANNEL_TXPRECURSORINV", - "GTXE2_CHANNEL_TXP_PAD", - "GTXE2_CHANNEL_TXQPIBIASEN", - "GTXE2_CHANNEL_TXQPISENN", - "GTXE2_CHANNEL_TXQPISENP", - "GTXE2_CHANNEL_TXQPISTRONGPDOWN", - "GTXE2_CHANNEL_TXQPIWEAKPUP", - "GTXE2_CHANNEL_TXRATE0", - "GTXE2_CHANNEL_TXRATE1", - "GTXE2_CHANNEL_TXRATE2", - "GTXE2_CHANNEL_TXRATEDONE", - "GTXE2_CHANNEL_TXRESETDONE", - "GTXE2_CHANNEL_TXRUNDISP0", - "GTXE2_CHANNEL_TXRUNDISP1", - "GTXE2_CHANNEL_TXRUNDISP2", - "GTXE2_CHANNEL_TXRUNDISP3", - "GTXE2_CHANNEL_TXRUNDISP4", - "GTXE2_CHANNEL_TXRUNDISP5", - "GTXE2_CHANNEL_TXRUNDISP6", - "GTXE2_CHANNEL_TXRUNDISP7", - "GTXE2_CHANNEL_TXSEQUENCE0", - "GTXE2_CHANNEL_TXSEQUENCE1", - "GTXE2_CHANNEL_TXSEQUENCE2", - "GTXE2_CHANNEL_TXSEQUENCE3", - "GTXE2_CHANNEL_TXSEQUENCE4", - "GTXE2_CHANNEL_TXSEQUENCE5", - "GTXE2_CHANNEL_TXSEQUENCE6", - "GTXE2_CHANNEL_TXSTARTSEQ", - "GTXE2_CHANNEL_TXSWING", - "GTXE2_CHANNEL_TXSYSCLKSEL0", - "GTXE2_CHANNEL_TXSYSCLKSEL1", - "GTXE2_CHANNEL_TXUSERRDY", - "GTXE2_CHANNEL_TXUSRCLK", - "GTXE2_CHANNEL_TXUSRCLK2", - "GTXE2_CLK0_0", - "GTXE2_CLK0_1", - "GTXE2_CLK0_10", - "GTXE2_CLK0_2", - "GTXE2_CLK0_3", - "GTXE2_CLK0_4", - "GTXE2_CLK0_5", - "GTXE2_CLK0_6", - "GTXE2_CLK0_7", - "GTXE2_CLK0_8", - "GTXE2_CLK0_9", - "GTXE2_CLK1_0", - "GTXE2_CLK1_1", - "GTXE2_CLK1_10", - "GTXE2_CLK1_2", - "GTXE2_CLK1_3", - "GTXE2_CLK1_4", - "GTXE2_CLK1_5", - "GTXE2_CLK1_6", - "GTXE2_CLK1_7", - "GTXE2_CLK1_8", - "GTXE2_CLK1_9", - "GTXE2_CTRL0_0", - "GTXE2_CTRL0_1", - "GTXE2_CTRL0_10", - "GTXE2_CTRL0_2", - "GTXE2_CTRL0_3", - "GTXE2_CTRL0_4", - "GTXE2_CTRL0_5", - "GTXE2_CTRL0_6", - "GTXE2_CTRL0_7", - "GTXE2_CTRL0_8", - "GTXE2_CTRL0_9", - "GTXE2_CTRL1_0", - "GTXE2_CTRL1_1", - "GTXE2_CTRL1_10", - "GTXE2_CTRL1_2", - "GTXE2_CTRL1_3", - "GTXE2_CTRL1_4", - "GTXE2_CTRL1_5", - "GTXE2_CTRL1_6", - "GTXE2_CTRL1_7", - "GTXE2_CTRL1_8", - "GTXE2_CTRL1_9", - "GTXE2_FAN0_0", - "GTXE2_FAN0_1", - "GTXE2_FAN0_10", - "GTXE2_FAN0_2", - "GTXE2_FAN0_3", - "GTXE2_FAN0_4", - "GTXE2_FAN0_5", - "GTXE2_FAN0_6", - "GTXE2_FAN0_7", - "GTXE2_FAN0_8", - "GTXE2_FAN0_9", - "GTXE2_FAN1_0", - "GTXE2_FAN1_1", - "GTXE2_FAN1_10", - "GTXE2_FAN1_2", - "GTXE2_FAN1_3", - "GTXE2_FAN1_4", - "GTXE2_FAN1_5", - "GTXE2_FAN1_6", - "GTXE2_FAN1_7", - "GTXE2_FAN1_8", - "GTXE2_FAN1_9", - "GTXE2_FAN2_0", - "GTXE2_FAN2_1", - "GTXE2_FAN2_10", - "GTXE2_FAN2_2", - "GTXE2_FAN2_3", - "GTXE2_FAN2_4", - "GTXE2_FAN2_5", - "GTXE2_FAN2_6", - "GTXE2_FAN2_7", - "GTXE2_FAN2_8", - "GTXE2_FAN2_9", - "GTXE2_FAN3_0", - "GTXE2_FAN3_1", - "GTXE2_FAN3_10", - "GTXE2_FAN3_2", - "GTXE2_FAN3_3", - "GTXE2_FAN3_4", - "GTXE2_FAN3_5", - "GTXE2_FAN3_6", - "GTXE2_FAN3_7", - "GTXE2_FAN3_8", - "GTXE2_FAN3_9", - "GTXE2_FAN4_0", - "GTXE2_FAN4_1", - "GTXE2_FAN4_10", - "GTXE2_FAN4_2", - "GTXE2_FAN4_3", - "GTXE2_FAN4_4", - "GTXE2_FAN4_5", - "GTXE2_FAN4_6", - "GTXE2_FAN4_7", - "GTXE2_FAN4_8", - "GTXE2_FAN4_9", - "GTXE2_FAN5_0", - "GTXE2_FAN5_1", - "GTXE2_FAN5_10", - "GTXE2_FAN5_2", - "GTXE2_FAN5_3", - "GTXE2_FAN5_4", - "GTXE2_FAN5_5", - "GTXE2_FAN5_6", - "GTXE2_FAN5_7", - "GTXE2_FAN5_8", - "GTXE2_FAN5_9", - "GTXE2_FAN6_0", - "GTXE2_FAN6_1", - "GTXE2_FAN6_10", - "GTXE2_FAN6_2", - "GTXE2_FAN6_3", - "GTXE2_FAN6_4", - "GTXE2_FAN6_5", - "GTXE2_FAN6_6", - "GTXE2_FAN6_7", - "GTXE2_FAN6_8", - "GTXE2_FAN6_9", - "GTXE2_FAN7_0", - "GTXE2_FAN7_1", - "GTXE2_FAN7_10", - "GTXE2_FAN7_2", - "GTXE2_FAN7_3", - "GTXE2_FAN7_4", - "GTXE2_FAN7_5", - "GTXE2_FAN7_6", - "GTXE2_FAN7_7", - "GTXE2_FAN7_8", - "GTXE2_FAN7_9", - "GTXE2_IMUX0_0", - "GTXE2_IMUX0_1", - "GTXE2_IMUX0_10", - "GTXE2_IMUX0_2", - "GTXE2_IMUX0_3", - "GTXE2_IMUX0_4", - "GTXE2_IMUX0_5", - "GTXE2_IMUX0_6", - "GTXE2_IMUX0_7", - "GTXE2_IMUX0_8", - "GTXE2_IMUX0_9", - "GTXE2_IMUX10_0", - "GTXE2_IMUX10_1", - "GTXE2_IMUX10_10", - "GTXE2_IMUX10_2", - "GTXE2_IMUX10_3", - "GTXE2_IMUX10_4", - "GTXE2_IMUX10_5", - "GTXE2_IMUX10_6", - "GTXE2_IMUX10_7", - "GTXE2_IMUX10_8", - "GTXE2_IMUX10_9", - "GTXE2_IMUX11_0", - "GTXE2_IMUX11_1", - "GTXE2_IMUX11_10", - "GTXE2_IMUX11_2", - "GTXE2_IMUX11_3", - "GTXE2_IMUX11_4", - "GTXE2_IMUX11_5", - "GTXE2_IMUX11_6", - "GTXE2_IMUX11_7", - "GTXE2_IMUX11_8", - "GTXE2_IMUX11_9", - "GTXE2_IMUX12_0", - "GTXE2_IMUX12_1", - "GTXE2_IMUX12_10", - "GTXE2_IMUX12_2", - "GTXE2_IMUX12_3", - "GTXE2_IMUX12_4", - "GTXE2_IMUX12_5", - "GTXE2_IMUX12_6", - "GTXE2_IMUX12_7", - "GTXE2_IMUX12_8", - "GTXE2_IMUX12_9", - "GTXE2_IMUX13_0", - "GTXE2_IMUX13_1", - "GTXE2_IMUX13_10", - "GTXE2_IMUX13_2", - "GTXE2_IMUX13_3", - "GTXE2_IMUX13_4", - "GTXE2_IMUX13_5", - "GTXE2_IMUX13_6", - "GTXE2_IMUX13_7", - "GTXE2_IMUX13_8", - "GTXE2_IMUX13_9", - "GTXE2_IMUX14_0", - "GTXE2_IMUX14_1", - "GTXE2_IMUX14_10", - "GTXE2_IMUX14_2", - "GTXE2_IMUX14_3", - "GTXE2_IMUX14_4", - "GTXE2_IMUX14_5", - "GTXE2_IMUX14_6", - "GTXE2_IMUX14_7", - "GTXE2_IMUX14_8", - "GTXE2_IMUX14_9", - "GTXE2_IMUX15_0", - "GTXE2_IMUX15_1", - "GTXE2_IMUX15_10", - "GTXE2_IMUX15_2", - "GTXE2_IMUX15_3", - "GTXE2_IMUX15_4", - "GTXE2_IMUX15_5", - "GTXE2_IMUX15_6", - "GTXE2_IMUX15_7", - "GTXE2_IMUX15_8", - "GTXE2_IMUX15_9", - "GTXE2_IMUX16_0", - "GTXE2_IMUX16_1", - "GTXE2_IMUX16_10", - "GTXE2_IMUX16_2", - "GTXE2_IMUX16_3", - "GTXE2_IMUX16_4", - "GTXE2_IMUX16_5", - "GTXE2_IMUX16_6", - "GTXE2_IMUX16_7", - "GTXE2_IMUX16_8", - "GTXE2_IMUX16_9", - "GTXE2_IMUX17_0", - "GTXE2_IMUX17_1", - "GTXE2_IMUX17_10", - "GTXE2_IMUX17_2", - "GTXE2_IMUX17_3", - "GTXE2_IMUX17_4", - "GTXE2_IMUX17_5", - "GTXE2_IMUX17_6", - "GTXE2_IMUX17_7", - "GTXE2_IMUX17_8", - "GTXE2_IMUX17_9", - "GTXE2_IMUX18_0", - "GTXE2_IMUX18_1", - "GTXE2_IMUX18_10", - "GTXE2_IMUX18_2", - "GTXE2_IMUX18_3", - "GTXE2_IMUX18_4", - "GTXE2_IMUX18_5", - "GTXE2_IMUX18_6", - "GTXE2_IMUX18_7", - "GTXE2_IMUX18_8", - "GTXE2_IMUX18_9", - "GTXE2_IMUX19_0", - "GTXE2_IMUX19_1", - "GTXE2_IMUX19_10", - "GTXE2_IMUX19_2", - "GTXE2_IMUX19_3", - "GTXE2_IMUX19_4", - "GTXE2_IMUX19_5", - "GTXE2_IMUX19_6", - "GTXE2_IMUX19_7", - "GTXE2_IMUX19_8", - "GTXE2_IMUX19_9", - "GTXE2_IMUX1_0", - "GTXE2_IMUX1_1", - "GTXE2_IMUX1_10", - "GTXE2_IMUX1_2", - "GTXE2_IMUX1_3", - "GTXE2_IMUX1_4", - "GTXE2_IMUX1_5", - "GTXE2_IMUX1_6", - "GTXE2_IMUX1_7", - "GTXE2_IMUX1_8", - "GTXE2_IMUX1_9", - "GTXE2_IMUX20_0", - "GTXE2_IMUX20_1", - "GTXE2_IMUX20_10", - "GTXE2_IMUX20_2", - "GTXE2_IMUX20_3", - "GTXE2_IMUX20_4", - "GTXE2_IMUX20_5", - "GTXE2_IMUX20_6", - "GTXE2_IMUX20_7", - "GTXE2_IMUX20_8", - "GTXE2_IMUX20_9", - "GTXE2_IMUX21_0", - "GTXE2_IMUX21_1", - "GTXE2_IMUX21_10", - "GTXE2_IMUX21_2", - "GTXE2_IMUX21_3", - "GTXE2_IMUX21_4", - "GTXE2_IMUX21_5", - "GTXE2_IMUX21_6", - "GTXE2_IMUX21_7", - "GTXE2_IMUX21_8", - "GTXE2_IMUX21_9", - "GTXE2_IMUX22_0", - "GTXE2_IMUX22_1", - "GTXE2_IMUX22_10", - "GTXE2_IMUX22_2", - "GTXE2_IMUX22_3", - "GTXE2_IMUX22_4", - "GTXE2_IMUX22_5", - "GTXE2_IMUX22_6", - "GTXE2_IMUX22_7", - "GTXE2_IMUX22_8", - "GTXE2_IMUX22_9", - "GTXE2_IMUX23_0", - "GTXE2_IMUX23_1", - "GTXE2_IMUX23_10", - "GTXE2_IMUX23_2", - "GTXE2_IMUX23_3", - "GTXE2_IMUX23_4", - "GTXE2_IMUX23_5", - "GTXE2_IMUX23_6", - "GTXE2_IMUX23_7", - "GTXE2_IMUX23_8", - "GTXE2_IMUX23_9", - "GTXE2_IMUX24_0", - "GTXE2_IMUX24_1", - "GTXE2_IMUX24_10", - "GTXE2_IMUX24_2", - "GTXE2_IMUX24_3", - "GTXE2_IMUX24_4", - "GTXE2_IMUX24_5", - "GTXE2_IMUX24_6", - "GTXE2_IMUX24_7", - "GTXE2_IMUX24_8", - "GTXE2_IMUX24_9", - "GTXE2_IMUX25_0", - "GTXE2_IMUX25_1", - "GTXE2_IMUX25_10", - "GTXE2_IMUX25_2", - "GTXE2_IMUX25_3", - "GTXE2_IMUX25_4", - "GTXE2_IMUX25_5", - "GTXE2_IMUX25_6", - "GTXE2_IMUX25_7", - "GTXE2_IMUX25_8", - "GTXE2_IMUX25_9", - "GTXE2_IMUX26_0", - "GTXE2_IMUX26_1", - "GTXE2_IMUX26_10", - "GTXE2_IMUX26_2", - "GTXE2_IMUX26_3", - "GTXE2_IMUX26_4", - "GTXE2_IMUX26_5", - "GTXE2_IMUX26_6", - "GTXE2_IMUX26_7", - "GTXE2_IMUX26_8", - "GTXE2_IMUX26_9", - "GTXE2_IMUX27_0", - "GTXE2_IMUX27_1", - "GTXE2_IMUX27_10", - "GTXE2_IMUX27_2", - "GTXE2_IMUX27_3", - "GTXE2_IMUX27_4", - "GTXE2_IMUX27_5", - "GTXE2_IMUX27_6", - "GTXE2_IMUX27_7", - "GTXE2_IMUX27_8", - "GTXE2_IMUX27_9", - "GTXE2_IMUX28_0", - "GTXE2_IMUX28_1", - "GTXE2_IMUX28_10", - "GTXE2_IMUX28_2", - "GTXE2_IMUX28_3", - "GTXE2_IMUX28_4", - "GTXE2_IMUX28_5", - "GTXE2_IMUX28_6", - "GTXE2_IMUX28_7", - "GTXE2_IMUX28_8", - "GTXE2_IMUX28_9", - "GTXE2_IMUX29_0", - "GTXE2_IMUX29_1", - "GTXE2_IMUX29_10", - "GTXE2_IMUX29_2", - "GTXE2_IMUX29_3", - "GTXE2_IMUX29_4", - "GTXE2_IMUX29_5", - "GTXE2_IMUX29_6", - "GTXE2_IMUX29_7", - "GTXE2_IMUX29_8", - "GTXE2_IMUX29_9", - "GTXE2_IMUX2_0", - "GTXE2_IMUX2_1", - "GTXE2_IMUX2_10", - "GTXE2_IMUX2_2", - "GTXE2_IMUX2_3", - "GTXE2_IMUX2_4", - "GTXE2_IMUX2_5", - "GTXE2_IMUX2_6", - "GTXE2_IMUX2_7", - "GTXE2_IMUX2_8", - "GTXE2_IMUX2_9", - "GTXE2_IMUX30_0", - "GTXE2_IMUX30_1", - "GTXE2_IMUX30_10", - "GTXE2_IMUX30_2", - "GTXE2_IMUX30_3", - "GTXE2_IMUX30_4", - "GTXE2_IMUX30_5", - "GTXE2_IMUX30_6", - "GTXE2_IMUX30_7", - "GTXE2_IMUX30_8", - "GTXE2_IMUX30_9", - "GTXE2_IMUX31_0", - "GTXE2_IMUX31_1", - "GTXE2_IMUX31_10", - "GTXE2_IMUX31_2", - "GTXE2_IMUX31_3", - "GTXE2_IMUX31_4", - "GTXE2_IMUX31_5", - "GTXE2_IMUX31_6", - "GTXE2_IMUX31_7", - "GTXE2_IMUX31_8", - "GTXE2_IMUX31_9", - "GTXE2_IMUX32_0", - "GTXE2_IMUX32_1", - "GTXE2_IMUX32_10", - "GTXE2_IMUX32_2", - "GTXE2_IMUX32_3", - "GTXE2_IMUX32_4", - "GTXE2_IMUX32_5", - "GTXE2_IMUX32_6", - "GTXE2_IMUX32_7", - "GTXE2_IMUX32_8", - "GTXE2_IMUX32_9", - "GTXE2_IMUX33_0", - "GTXE2_IMUX33_1", - "GTXE2_IMUX33_10", - "GTXE2_IMUX33_2", - "GTXE2_IMUX33_3", - "GTXE2_IMUX33_4", - "GTXE2_IMUX33_5", - "GTXE2_IMUX33_6", - "GTXE2_IMUX33_7", - "GTXE2_IMUX33_8", - "GTXE2_IMUX33_9", - "GTXE2_IMUX34_0", - "GTXE2_IMUX34_1", - "GTXE2_IMUX34_10", - "GTXE2_IMUX34_2", - "GTXE2_IMUX34_3", - "GTXE2_IMUX34_4", - "GTXE2_IMUX34_5", - "GTXE2_IMUX34_6", - "GTXE2_IMUX34_7", - "GTXE2_IMUX34_8", - "GTXE2_IMUX34_9", - "GTXE2_IMUX35_0", - "GTXE2_IMUX35_1", - "GTXE2_IMUX35_10", - "GTXE2_IMUX35_2", - "GTXE2_IMUX35_3", - "GTXE2_IMUX35_4", - "GTXE2_IMUX35_5", - "GTXE2_IMUX35_6", - "GTXE2_IMUX35_7", - "GTXE2_IMUX35_8", - "GTXE2_IMUX35_9", - "GTXE2_IMUX36_0", - "GTXE2_IMUX36_1", - "GTXE2_IMUX36_10", - "GTXE2_IMUX36_2", - "GTXE2_IMUX36_3", - "GTXE2_IMUX36_4", - "GTXE2_IMUX36_5", - "GTXE2_IMUX36_6", - "GTXE2_IMUX36_7", - "GTXE2_IMUX36_8", - "GTXE2_IMUX36_9", - "GTXE2_IMUX37_0", - "GTXE2_IMUX37_1", - "GTXE2_IMUX37_10", - "GTXE2_IMUX37_2", - "GTXE2_IMUX37_3", - "GTXE2_IMUX37_4", - "GTXE2_IMUX37_5", - "GTXE2_IMUX37_6", - "GTXE2_IMUX37_7", - "GTXE2_IMUX37_8", - "GTXE2_IMUX37_9", - "GTXE2_IMUX38_0", - "GTXE2_IMUX38_1", - "GTXE2_IMUX38_10", - "GTXE2_IMUX38_2", - "GTXE2_IMUX38_3", - "GTXE2_IMUX38_4", - "GTXE2_IMUX38_5", - "GTXE2_IMUX38_6", - "GTXE2_IMUX38_7", - "GTXE2_IMUX38_8", - "GTXE2_IMUX38_9", - "GTXE2_IMUX39_0", - "GTXE2_IMUX39_1", - "GTXE2_IMUX39_10", - "GTXE2_IMUX39_2", - "GTXE2_IMUX39_3", - "GTXE2_IMUX39_4", - "GTXE2_IMUX39_5", - "GTXE2_IMUX39_6", - "GTXE2_IMUX39_7", - "GTXE2_IMUX39_8", - "GTXE2_IMUX39_9", - "GTXE2_IMUX3_0", - "GTXE2_IMUX3_1", - "GTXE2_IMUX3_10", - "GTXE2_IMUX3_2", - "GTXE2_IMUX3_3", - "GTXE2_IMUX3_4", - "GTXE2_IMUX3_5", - "GTXE2_IMUX3_6", - "GTXE2_IMUX3_7", - "GTXE2_IMUX3_8", - "GTXE2_IMUX3_9", - "GTXE2_IMUX40_0", - "GTXE2_IMUX40_1", - "GTXE2_IMUX40_10", - "GTXE2_IMUX40_2", - "GTXE2_IMUX40_3", - "GTXE2_IMUX40_4", - "GTXE2_IMUX40_5", - "GTXE2_IMUX40_6", - "GTXE2_IMUX40_7", - "GTXE2_IMUX40_8", - "GTXE2_IMUX40_9", - "GTXE2_IMUX41_0", - "GTXE2_IMUX41_1", - "GTXE2_IMUX41_10", - "GTXE2_IMUX41_2", - "GTXE2_IMUX41_3", - "GTXE2_IMUX41_4", - "GTXE2_IMUX41_5", - "GTXE2_IMUX41_6", - "GTXE2_IMUX41_7", - "GTXE2_IMUX41_8", - "GTXE2_IMUX41_9", - "GTXE2_IMUX42_0", - "GTXE2_IMUX42_1", - "GTXE2_IMUX42_10", - "GTXE2_IMUX42_2", - "GTXE2_IMUX42_3", - "GTXE2_IMUX42_4", - "GTXE2_IMUX42_5", - "GTXE2_IMUX42_6", - "GTXE2_IMUX42_7", - "GTXE2_IMUX42_8", - "GTXE2_IMUX42_9", - "GTXE2_IMUX43_0", - "GTXE2_IMUX43_1", - "GTXE2_IMUX43_10", - "GTXE2_IMUX43_2", - "GTXE2_IMUX43_3", - "GTXE2_IMUX43_4", - "GTXE2_IMUX43_5", - "GTXE2_IMUX43_6", - "GTXE2_IMUX43_7", - "GTXE2_IMUX43_8", - "GTXE2_IMUX43_9", - "GTXE2_IMUX44_0", - "GTXE2_IMUX44_1", - "GTXE2_IMUX44_10", - "GTXE2_IMUX44_2", - "GTXE2_IMUX44_3", - "GTXE2_IMUX44_4", - "GTXE2_IMUX44_5", - "GTXE2_IMUX44_6", - "GTXE2_IMUX44_7", - "GTXE2_IMUX44_8", - "GTXE2_IMUX44_9", - "GTXE2_IMUX45_0", - "GTXE2_IMUX45_1", - "GTXE2_IMUX45_10", - "GTXE2_IMUX45_2", - "GTXE2_IMUX45_3", - "GTXE2_IMUX45_4", - "GTXE2_IMUX45_5", - "GTXE2_IMUX45_6", - "GTXE2_IMUX45_7", - "GTXE2_IMUX45_8", - "GTXE2_IMUX45_9", - "GTXE2_IMUX46_0", - "GTXE2_IMUX46_1", - "GTXE2_IMUX46_10", - "GTXE2_IMUX46_2", - "GTXE2_IMUX46_3", - "GTXE2_IMUX46_4", - "GTXE2_IMUX46_5", - "GTXE2_IMUX46_6", - "GTXE2_IMUX46_7", - "GTXE2_IMUX46_8", - "GTXE2_IMUX46_9", - "GTXE2_IMUX47_0", - "GTXE2_IMUX47_1", - "GTXE2_IMUX47_10", - "GTXE2_IMUX47_2", - "GTXE2_IMUX47_3", - "GTXE2_IMUX47_4", - "GTXE2_IMUX47_5", - "GTXE2_IMUX47_6", - "GTXE2_IMUX47_7", - "GTXE2_IMUX47_8", - "GTXE2_IMUX47_9", - "GTXE2_IMUX4_0", - "GTXE2_IMUX4_1", - "GTXE2_IMUX4_10", - "GTXE2_IMUX4_2", - "GTXE2_IMUX4_3", - "GTXE2_IMUX4_4", - "GTXE2_IMUX4_5", - "GTXE2_IMUX4_6", - "GTXE2_IMUX4_7", - "GTXE2_IMUX4_8", - "GTXE2_IMUX4_9", - "GTXE2_IMUX5_0", - "GTXE2_IMUX5_1", - "GTXE2_IMUX5_10", - "GTXE2_IMUX5_2", - "GTXE2_IMUX5_3", - "GTXE2_IMUX5_4", - "GTXE2_IMUX5_5", - "GTXE2_IMUX5_6", - "GTXE2_IMUX5_7", - "GTXE2_IMUX5_8", - "GTXE2_IMUX5_9", - "GTXE2_IMUX6_0", - "GTXE2_IMUX6_1", - "GTXE2_IMUX6_10", - "GTXE2_IMUX6_2", - "GTXE2_IMUX6_3", - "GTXE2_IMUX6_4", - "GTXE2_IMUX6_5", - "GTXE2_IMUX6_6", - "GTXE2_IMUX6_7", - "GTXE2_IMUX6_8", - "GTXE2_IMUX6_9", - "GTXE2_IMUX7_0", - "GTXE2_IMUX7_1", - "GTXE2_IMUX7_10", - "GTXE2_IMUX7_2", - "GTXE2_IMUX7_3", - "GTXE2_IMUX7_4", - "GTXE2_IMUX7_5", - "GTXE2_IMUX7_6", - "GTXE2_IMUX7_7", - "GTXE2_IMUX7_8", - "GTXE2_IMUX7_9", - "GTXE2_IMUX8_0", - "GTXE2_IMUX8_1", - "GTXE2_IMUX8_10", - "GTXE2_IMUX8_2", - "GTXE2_IMUX8_3", - "GTXE2_IMUX8_4", - "GTXE2_IMUX8_5", - "GTXE2_IMUX8_6", - "GTXE2_IMUX8_7", - "GTXE2_IMUX8_8", - "GTXE2_IMUX8_9", - "GTXE2_IMUX9_0", - "GTXE2_IMUX9_1", - "GTXE2_IMUX9_10", - "GTXE2_IMUX9_2", - "GTXE2_IMUX9_3", - "GTXE2_IMUX9_4", - "GTXE2_IMUX9_5", - "GTXE2_IMUX9_6", - "GTXE2_IMUX9_7", - "GTXE2_IMUX9_8", - "GTXE2_IMUX9_9", - "GTXE2_LOGIC_OUTS_B0_0", - "GTXE2_LOGIC_OUTS_B0_1", - "GTXE2_LOGIC_OUTS_B0_10", - "GTXE2_LOGIC_OUTS_B0_2", - "GTXE2_LOGIC_OUTS_B0_3", - "GTXE2_LOGIC_OUTS_B0_4", - "GTXE2_LOGIC_OUTS_B0_5", - "GTXE2_LOGIC_OUTS_B0_6", - "GTXE2_LOGIC_OUTS_B0_7", - "GTXE2_LOGIC_OUTS_B0_8", - "GTXE2_LOGIC_OUTS_B0_9", - "GTXE2_LOGIC_OUTS_B10_0", - "GTXE2_LOGIC_OUTS_B10_1", - "GTXE2_LOGIC_OUTS_B10_10", - "GTXE2_LOGIC_OUTS_B10_2", - "GTXE2_LOGIC_OUTS_B10_3", - "GTXE2_LOGIC_OUTS_B10_4", - "GTXE2_LOGIC_OUTS_B10_5", - "GTXE2_LOGIC_OUTS_B10_6", - "GTXE2_LOGIC_OUTS_B10_7", - "GTXE2_LOGIC_OUTS_B10_8", - "GTXE2_LOGIC_OUTS_B10_9", - "GTXE2_LOGIC_OUTS_B11_0", - "GTXE2_LOGIC_OUTS_B11_1", - "GTXE2_LOGIC_OUTS_B11_10", - "GTXE2_LOGIC_OUTS_B11_2", - "GTXE2_LOGIC_OUTS_B11_3", - "GTXE2_LOGIC_OUTS_B11_4", - "GTXE2_LOGIC_OUTS_B11_5", - "GTXE2_LOGIC_OUTS_B11_6", - "GTXE2_LOGIC_OUTS_B11_7", - "GTXE2_LOGIC_OUTS_B11_8", - "GTXE2_LOGIC_OUTS_B11_9", - "GTXE2_LOGIC_OUTS_B12_0", - "GTXE2_LOGIC_OUTS_B12_1", - "GTXE2_LOGIC_OUTS_B12_10", - "GTXE2_LOGIC_OUTS_B12_2", - "GTXE2_LOGIC_OUTS_B12_3", - "GTXE2_LOGIC_OUTS_B12_4", - "GTXE2_LOGIC_OUTS_B12_5", - "GTXE2_LOGIC_OUTS_B12_6", - "GTXE2_LOGIC_OUTS_B12_7", - "GTXE2_LOGIC_OUTS_B12_8", - "GTXE2_LOGIC_OUTS_B12_9", - "GTXE2_LOGIC_OUTS_B13_0", - "GTXE2_LOGIC_OUTS_B13_1", - "GTXE2_LOGIC_OUTS_B13_10", - "GTXE2_LOGIC_OUTS_B13_2", - "GTXE2_LOGIC_OUTS_B13_3", - "GTXE2_LOGIC_OUTS_B13_4", - "GTXE2_LOGIC_OUTS_B13_5", - "GTXE2_LOGIC_OUTS_B13_6", - "GTXE2_LOGIC_OUTS_B13_7", - "GTXE2_LOGIC_OUTS_B13_8", - "GTXE2_LOGIC_OUTS_B13_9", - "GTXE2_LOGIC_OUTS_B14_0", - "GTXE2_LOGIC_OUTS_B14_1", - "GTXE2_LOGIC_OUTS_B14_10", - "GTXE2_LOGIC_OUTS_B14_2", - "GTXE2_LOGIC_OUTS_B14_3", - "GTXE2_LOGIC_OUTS_B14_4", - "GTXE2_LOGIC_OUTS_B14_5", - "GTXE2_LOGIC_OUTS_B14_6", - "GTXE2_LOGIC_OUTS_B14_7", - "GTXE2_LOGIC_OUTS_B14_8", - "GTXE2_LOGIC_OUTS_B14_9", - "GTXE2_LOGIC_OUTS_B15_0", - "GTXE2_LOGIC_OUTS_B15_1", - "GTXE2_LOGIC_OUTS_B15_10", - "GTXE2_LOGIC_OUTS_B15_2", - "GTXE2_LOGIC_OUTS_B15_3", - "GTXE2_LOGIC_OUTS_B15_4", - "GTXE2_LOGIC_OUTS_B15_5", - "GTXE2_LOGIC_OUTS_B15_6", - "GTXE2_LOGIC_OUTS_B15_7", - "GTXE2_LOGIC_OUTS_B15_8", - "GTXE2_LOGIC_OUTS_B15_9", - "GTXE2_LOGIC_OUTS_B16_0", - "GTXE2_LOGIC_OUTS_B16_1", - "GTXE2_LOGIC_OUTS_B16_10", - "GTXE2_LOGIC_OUTS_B16_2", - "GTXE2_LOGIC_OUTS_B16_3", - "GTXE2_LOGIC_OUTS_B16_4", - "GTXE2_LOGIC_OUTS_B16_5", - "GTXE2_LOGIC_OUTS_B16_6", - "GTXE2_LOGIC_OUTS_B16_7", - "GTXE2_LOGIC_OUTS_B16_8", - "GTXE2_LOGIC_OUTS_B16_9", - "GTXE2_LOGIC_OUTS_B17_0", - "GTXE2_LOGIC_OUTS_B17_1", - "GTXE2_LOGIC_OUTS_B17_10", - "GTXE2_LOGIC_OUTS_B17_2", - "GTXE2_LOGIC_OUTS_B17_3", - "GTXE2_LOGIC_OUTS_B17_4", - "GTXE2_LOGIC_OUTS_B17_5", - "GTXE2_LOGIC_OUTS_B17_6", - "GTXE2_LOGIC_OUTS_B17_7", - "GTXE2_LOGIC_OUTS_B17_8", - "GTXE2_LOGIC_OUTS_B17_9", - "GTXE2_LOGIC_OUTS_B18_0", - "GTXE2_LOGIC_OUTS_B18_1", - "GTXE2_LOGIC_OUTS_B18_10", - "GTXE2_LOGIC_OUTS_B18_2", - "GTXE2_LOGIC_OUTS_B18_3", - "GTXE2_LOGIC_OUTS_B18_4", - "GTXE2_LOGIC_OUTS_B18_5", - "GTXE2_LOGIC_OUTS_B18_6", - "GTXE2_LOGIC_OUTS_B18_7", - "GTXE2_LOGIC_OUTS_B18_8", - "GTXE2_LOGIC_OUTS_B18_9", - "GTXE2_LOGIC_OUTS_B19_0", - "GTXE2_LOGIC_OUTS_B19_1", - "GTXE2_LOGIC_OUTS_B19_10", - "GTXE2_LOGIC_OUTS_B19_2", - "GTXE2_LOGIC_OUTS_B19_3", - "GTXE2_LOGIC_OUTS_B19_4", - "GTXE2_LOGIC_OUTS_B19_5", - "GTXE2_LOGIC_OUTS_B19_6", - "GTXE2_LOGIC_OUTS_B19_7", - "GTXE2_LOGIC_OUTS_B19_8", - "GTXE2_LOGIC_OUTS_B19_9", - "GTXE2_LOGIC_OUTS_B1_0", - "GTXE2_LOGIC_OUTS_B1_1", - "GTXE2_LOGIC_OUTS_B1_10", - "GTXE2_LOGIC_OUTS_B1_2", - "GTXE2_LOGIC_OUTS_B1_3", - "GTXE2_LOGIC_OUTS_B1_4", - "GTXE2_LOGIC_OUTS_B1_5", - "GTXE2_LOGIC_OUTS_B1_6", - "GTXE2_LOGIC_OUTS_B1_7", - "GTXE2_LOGIC_OUTS_B1_8", - "GTXE2_LOGIC_OUTS_B1_9", - "GTXE2_LOGIC_OUTS_B20_0", - "GTXE2_LOGIC_OUTS_B20_1", - "GTXE2_LOGIC_OUTS_B20_10", - "GTXE2_LOGIC_OUTS_B20_2", - "GTXE2_LOGIC_OUTS_B20_3", - "GTXE2_LOGIC_OUTS_B20_4", - "GTXE2_LOGIC_OUTS_B20_5", - "GTXE2_LOGIC_OUTS_B20_6", - "GTXE2_LOGIC_OUTS_B20_7", - "GTXE2_LOGIC_OUTS_B20_8", - "GTXE2_LOGIC_OUTS_B20_9", - "GTXE2_LOGIC_OUTS_B21_0", - "GTXE2_LOGIC_OUTS_B21_1", - "GTXE2_LOGIC_OUTS_B21_10", - "GTXE2_LOGIC_OUTS_B21_2", - "GTXE2_LOGIC_OUTS_B21_3", - "GTXE2_LOGIC_OUTS_B21_4", - "GTXE2_LOGIC_OUTS_B21_5", - "GTXE2_LOGIC_OUTS_B21_6", - "GTXE2_LOGIC_OUTS_B21_7", - "GTXE2_LOGIC_OUTS_B21_8", - "GTXE2_LOGIC_OUTS_B21_9", - "GTXE2_LOGIC_OUTS_B22_0", - "GTXE2_LOGIC_OUTS_B22_1", - "GTXE2_LOGIC_OUTS_B22_10", - "GTXE2_LOGIC_OUTS_B22_2", - "GTXE2_LOGIC_OUTS_B22_3", - "GTXE2_LOGIC_OUTS_B22_4", - "GTXE2_LOGIC_OUTS_B22_5", - "GTXE2_LOGIC_OUTS_B22_6", - "GTXE2_LOGIC_OUTS_B22_7", - "GTXE2_LOGIC_OUTS_B22_8", - "GTXE2_LOGIC_OUTS_B22_9", - "GTXE2_LOGIC_OUTS_B23_0", - "GTXE2_LOGIC_OUTS_B23_1", - "GTXE2_LOGIC_OUTS_B23_10", - "GTXE2_LOGIC_OUTS_B23_2", - "GTXE2_LOGIC_OUTS_B23_3", - "GTXE2_LOGIC_OUTS_B23_4", - "GTXE2_LOGIC_OUTS_B23_5", - "GTXE2_LOGIC_OUTS_B23_6", - "GTXE2_LOGIC_OUTS_B23_7", - "GTXE2_LOGIC_OUTS_B23_8", - "GTXE2_LOGIC_OUTS_B23_9", - "GTXE2_LOGIC_OUTS_B2_0", - "GTXE2_LOGIC_OUTS_B2_1", - "GTXE2_LOGIC_OUTS_B2_10", - "GTXE2_LOGIC_OUTS_B2_2", - "GTXE2_LOGIC_OUTS_B2_3", - "GTXE2_LOGIC_OUTS_B2_4", - "GTXE2_LOGIC_OUTS_B2_5", - "GTXE2_LOGIC_OUTS_B2_6", - "GTXE2_LOGIC_OUTS_B2_7", - "GTXE2_LOGIC_OUTS_B2_8", - "GTXE2_LOGIC_OUTS_B2_9", - "GTXE2_LOGIC_OUTS_B3_0", - "GTXE2_LOGIC_OUTS_B3_1", - "GTXE2_LOGIC_OUTS_B3_10", - "GTXE2_LOGIC_OUTS_B3_2", - "GTXE2_LOGIC_OUTS_B3_3", - "GTXE2_LOGIC_OUTS_B3_4", - "GTXE2_LOGIC_OUTS_B3_5", - "GTXE2_LOGIC_OUTS_B3_6", - "GTXE2_LOGIC_OUTS_B3_7", - "GTXE2_LOGIC_OUTS_B3_8", - "GTXE2_LOGIC_OUTS_B3_9", - "GTXE2_LOGIC_OUTS_B4_0", - "GTXE2_LOGIC_OUTS_B4_1", - "GTXE2_LOGIC_OUTS_B4_10", - "GTXE2_LOGIC_OUTS_B4_2", - "GTXE2_LOGIC_OUTS_B4_3", - "GTXE2_LOGIC_OUTS_B4_4", - "GTXE2_LOGIC_OUTS_B4_5", - "GTXE2_LOGIC_OUTS_B4_6", - "GTXE2_LOGIC_OUTS_B4_7", - "GTXE2_LOGIC_OUTS_B4_8", - "GTXE2_LOGIC_OUTS_B4_9", - "GTXE2_LOGIC_OUTS_B5_0", - "GTXE2_LOGIC_OUTS_B5_1", - "GTXE2_LOGIC_OUTS_B5_10", - "GTXE2_LOGIC_OUTS_B5_2", - "GTXE2_LOGIC_OUTS_B5_3", - "GTXE2_LOGIC_OUTS_B5_4", - "GTXE2_LOGIC_OUTS_B5_5", - "GTXE2_LOGIC_OUTS_B5_6", - "GTXE2_LOGIC_OUTS_B5_7", - "GTXE2_LOGIC_OUTS_B5_8", - "GTXE2_LOGIC_OUTS_B5_9", - "GTXE2_LOGIC_OUTS_B6_0", - "GTXE2_LOGIC_OUTS_B6_1", - "GTXE2_LOGIC_OUTS_B6_10", - "GTXE2_LOGIC_OUTS_B6_2", - "GTXE2_LOGIC_OUTS_B6_3", - "GTXE2_LOGIC_OUTS_B6_4", - "GTXE2_LOGIC_OUTS_B6_5", - "GTXE2_LOGIC_OUTS_B6_6", - "GTXE2_LOGIC_OUTS_B6_7", - "GTXE2_LOGIC_OUTS_B6_8", - "GTXE2_LOGIC_OUTS_B6_9", - "GTXE2_LOGIC_OUTS_B7_0", - "GTXE2_LOGIC_OUTS_B7_1", - "GTXE2_LOGIC_OUTS_B7_10", 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"GTXE2_LOGIC_OUTS_B6_7": null, + "GTXE2_LOGIC_OUTS_B6_8": null, + "GTXE2_LOGIC_OUTS_B6_9": null, + "GTXE2_LOGIC_OUTS_B7_0": null, + "GTXE2_LOGIC_OUTS_B7_1": null, + "GTXE2_LOGIC_OUTS_B7_10": null, + "GTXE2_LOGIC_OUTS_B7_2": null, + "GTXE2_LOGIC_OUTS_B7_3": null, + "GTXE2_LOGIC_OUTS_B7_4": null, + "GTXE2_LOGIC_OUTS_B7_5": null, + "GTXE2_LOGIC_OUTS_B7_6": null, + "GTXE2_LOGIC_OUTS_B7_7": null, + "GTXE2_LOGIC_OUTS_B7_8": null, + "GTXE2_LOGIC_OUTS_B7_9": null, + "GTXE2_LOGIC_OUTS_B8_0": null, + "GTXE2_LOGIC_OUTS_B8_1": null, + "GTXE2_LOGIC_OUTS_B8_10": null, + "GTXE2_LOGIC_OUTS_B8_2": null, + "GTXE2_LOGIC_OUTS_B8_3": null, + "GTXE2_LOGIC_OUTS_B8_4": null, + "GTXE2_LOGIC_OUTS_B8_5": null, + "GTXE2_LOGIC_OUTS_B8_6": null, + "GTXE2_LOGIC_OUTS_B8_7": null, + "GTXE2_LOGIC_OUTS_B8_8": null, + "GTXE2_LOGIC_OUTS_B8_9": null, + "GTXE2_LOGIC_OUTS_B9_0": null, + "GTXE2_LOGIC_OUTS_B9_1": null, + "GTXE2_LOGIC_OUTS_B9_10": null, + "GTXE2_LOGIC_OUTS_B9_2": null, + "GTXE2_LOGIC_OUTS_B9_3": null, + "GTXE2_LOGIC_OUTS_B9_4": null, + "GTXE2_LOGIC_OUTS_B9_5": null, + "GTXE2_LOGIC_OUTS_B9_6": null, + "GTXE2_LOGIC_OUTS_B9_7": null, + "GTXE2_LOGIC_OUTS_B9_8": null, + "GTXE2_LOGIC_OUTS_B9_9": null + } } diff --git a/kintex7/tile_type_GTX_CHANNEL_1.json b/kintex7/tile_type_GTX_CHANNEL_1.json index 6c78af8..d30b43d 100644 --- a/kintex7/tile_type_GTX_CHANNEL_1.json +++ b/kintex7/tile_type_GTX_CHANNEL_1.json @@ -2,4398 +2,11306 @@ "pips": { "GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLFBCLKLOST" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLLOCK->GTXE2_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLLOCK" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_CPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLREFCLKLOST" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT0->GTXE2_LOGIC_OUTS_B9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT1->GTXE2_LOGIC_OUTS_B9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT2->GTXE2_LOGIC_OUTS_B9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT3->GTXE2_LOGIC_OUTS_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT4->GTXE2_LOGIC_OUTS_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT5->GTXE2_LOGIC_OUTS_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT6->GTXE2_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DMONITOROUT7->GTXE2_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT7" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO0->GTXE2_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO1->GTXE2_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO10->GTXE2_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO10" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO11->GTXE2_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO11" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO12->GTXE2_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO12" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO13->GTXE2_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO13" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO14->GTXE2_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO14" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO15->GTXE2_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO15" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO2->GTXE2_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO3->GTXE2_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO4->GTXE2_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO5->GTXE2_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO6->GTXE2_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO7->GTXE2_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO7" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO8->GTXE2_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO8" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPDO9->GTXE2_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO9" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_DRPRDY->GTXE2_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPRDY" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_EYESCANDATAERROR->GTXE2_LOGIC_OUTS_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_EYESCANDATAERROR" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_GTREFCLKMONITOR->GTXE2_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTREFCLKMONITOR" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_GTRXOUTCLK_1->GTXE2_CHANNEL_RXOUTCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLK_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTRXOUTCLK_1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_GTTXOUTCLK_1->GTXE2_CHANNEL_TXOUTCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLK_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTTXOUTCLK_1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_NORTHREFCLK0->GTXE2_CHANNEL_GTNORTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_NORTHREFCLK0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_NORTHREFCLK1->GTXE2_CHANNEL_GTNORTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_NORTHREFCLK1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT0->GTXE2_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT1->GTXE2_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT10->GTXE2_LOGIC_OUTS_B13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT10" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT11->GTXE2_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT11" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT12->GTXE2_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT12" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT13->GTXE2_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT13" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT14->GTXE2_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT14" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT15->GTXE2_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT15" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT2->GTXE2_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT3->GTXE2_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT4->GTXE2_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT5->GTXE2_LOGIC_OUTS_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT6->GTXE2_LOGIC_OUTS_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT7->GTXE2_LOGIC_OUTS_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT7" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT8->GTXE2_LOGIC_OUTS_B13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT8" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PCSRSVDOUT9->GTXE2_LOGIC_OUTS_B13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT9" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_PHYSTATUS->GTXE2_LOGIC_OUTS_B10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PHYSTATUS" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_QPLLCLK->GTXE2_CHANNEL_GTQPLLCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTQPLLCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_QPLLCLK" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_QPLLREFCLK->GTXE2_CHANNEL_GTQPLLREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTQPLLREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_QPLLREFCLK" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_REFCLK0->GTXE2_CHANNEL_GTREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_REFCLK0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_REFCLK1->GTXE2_CHANNEL_GTREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_REFCLK1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBUFSTATUS0->GTXE2_LOGIC_OUTS_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBUFSTATUS1->GTXE2_LOGIC_OUTS_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBUFSTATUS2->GTXE2_LOGIC_OUTS_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBYTEISALIGNED->GTXE2_LOGIC_OUTS_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBYTEISALIGNED" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXBYTEREALIGN->GTXE2_LOGIC_OUTS_B10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBYTEREALIGN" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCDRLOCK->GTXE2_LOGIC_OUTS_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCDRLOCK" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHANBONDSEQ->GTXE2_LOGIC_OUTS_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANBONDSEQ" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHANISALIGNED->GTXE2_LOGIC_OUTS_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANISALIGNED" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHANREALIGN->GTXE2_LOGIC_OUTS_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANREALIGN" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA0->GTXE2_LOGIC_OUTS_B15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA1->GTXE2_LOGIC_OUTS_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA2->GTXE2_LOGIC_OUTS_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA3->GTXE2_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA4->GTXE2_LOGIC_OUTS_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA5->GTXE2_LOGIC_OUTS_B15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA6->GTXE2_LOGIC_OUTS_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISCOMMA7->GTXE2_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA7" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK0->GTXE2_LOGIC_OUTS_B12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK1->GTXE2_LOGIC_OUTS_B12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK2->GTXE2_LOGIC_OUTS_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK3->GTXE2_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK4->GTXE2_LOGIC_OUTS_B12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK5->GTXE2_LOGIC_OUTS_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK6->GTXE2_LOGIC_OUTS_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHARISK7->GTXE2_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK7" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO0->GTXE2_LOGIC_OUTS_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO1->GTXE2_LOGIC_OUTS_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO2->GTXE2_LOGIC_OUTS_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO3->GTXE2_LOGIC_OUTS_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCHBONDO4->GTXE2_LOGIC_OUTS_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCLKCORCNT0->GTXE2_LOGIC_OUTS_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCLKCORCNT1->GTXE2_LOGIC_OUTS_B20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCOMINITDET->GTXE2_LOGIC_OUTS_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMINITDET" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCOMMADET->GTXE2_LOGIC_OUTS_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMMADET" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCOMSASDET->GTXE2_LOGIC_OUTS_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMSASDET" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXCOMWAKEDET->GTXE2_LOGIC_OUTS_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMWAKEDET" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA0->GTXE2_LOGIC_OUTS_B6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA1->GTXE2_LOGIC_OUTS_B2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA10->GTXE2_LOGIC_OUTS_B4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA10" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA11->GTXE2_LOGIC_OUTS_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA11" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA12->GTXE2_LOGIC_OUTS_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA12" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA13->GTXE2_LOGIC_OUTS_B7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA13" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA14->GTXE2_LOGIC_OUTS_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA14" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA15->GTXE2_LOGIC_OUTS_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA15" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA16->GTXE2_LOGIC_OUTS_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA16" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA17->GTXE2_LOGIC_OUTS_B2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA17" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA18->GTXE2_LOGIC_OUTS_B4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA18" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA19->GTXE2_LOGIC_OUTS_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA19" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA2->GTXE2_LOGIC_OUTS_B4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA20->GTXE2_LOGIC_OUTS_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA20" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA21->GTXE2_LOGIC_OUTS_B7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA21" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA22->GTXE2_LOGIC_OUTS_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA22" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA23->GTXE2_LOGIC_OUTS_B5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA23" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA24->GTXE2_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA24" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA25->GTXE2_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA25" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA26->GTXE2_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA26" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA27->GTXE2_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA27" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA28->GTXE2_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA28" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA29->GTXE2_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA29" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA3->GTXE2_LOGIC_OUTS_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA30->GTXE2_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA30" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA31->GTXE2_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA31" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA32->GTXE2_LOGIC_OUTS_B3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA32" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA33->GTXE2_LOGIC_OUTS_B7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA33" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA34->GTXE2_LOGIC_OUTS_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA34" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA35->GTXE2_LOGIC_OUTS_B5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA35" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA36->GTXE2_LOGIC_OUTS_B6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA36" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA37->GTXE2_LOGIC_OUTS_B2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA37" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA38->GTXE2_LOGIC_OUTS_B4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA38" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA39->GTXE2_LOGIC_OUTS_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA39" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA4->GTXE2_LOGIC_OUTS_B3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA40->GTXE2_LOGIC_OUTS_B3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA40" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA41->GTXE2_LOGIC_OUTS_B7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA41" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA42->GTXE2_LOGIC_OUTS_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA42" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA43->GTXE2_LOGIC_OUTS_B5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA43" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA44->GTXE2_LOGIC_OUTS_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA44" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA45->GTXE2_LOGIC_OUTS_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA45" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA46->GTXE2_LOGIC_OUTS_B4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA46" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA47->GTXE2_LOGIC_OUTS_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA47" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA48->GTXE2_LOGIC_OUTS_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA48" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA49->GTXE2_LOGIC_OUTS_B7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA49" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA5->GTXE2_LOGIC_OUTS_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA50->GTXE2_LOGIC_OUTS_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA50" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA51->GTXE2_LOGIC_OUTS_B5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA51" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA52->GTXE2_LOGIC_OUTS_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA52" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA53->GTXE2_LOGIC_OUTS_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA53" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA54->GTXE2_LOGIC_OUTS_B4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA54" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA55->GTXE2_LOGIC_OUTS_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA55" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA56->GTXE2_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA56" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA57->GTXE2_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA57" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA58->GTXE2_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA58" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA59->GTXE2_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA59" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA6->GTXE2_LOGIC_OUTS_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA60->GTXE2_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA60" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA61->GTXE2_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA61" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA62->GTXE2_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA62" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA63->GTXE2_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA63" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA7->GTXE2_LOGIC_OUTS_B5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA7" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA8->GTXE2_LOGIC_OUTS_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA8" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATA9->GTXE2_LOGIC_OUTS_B2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA9" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDATAVALID->GTXE2_LOGIC_OUTS_B19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATAVALID" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR0->GTXE2_LOGIC_OUTS_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR1->GTXE2_LOGIC_OUTS_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR2->GTXE2_LOGIC_OUTS_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR3->GTXE2_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR4->GTXE2_LOGIC_OUTS_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR5->GTXE2_LOGIC_OUTS_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR6->GTXE2_LOGIC_OUTS_B22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDISPERR7->GTXE2_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR7" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDLYSRESETDONE" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXELECIDLE->GTXE2_LOGIC_OUTS_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXELECIDLE" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXHEADER0->GTXE2_LOGIC_OUTS_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXHEADER1->GTXE2_LOGIC_OUTS_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXHEADER2->GTXE2_LOGIC_OUTS_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXHEADERVALID->GTXE2_LOGIC_OUTS_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADERVALID" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT0->GTXE2_LOGIC_OUTS_B8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT1->GTXE2_LOGIC_OUTS_B8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT2->GTXE2_LOGIC_OUTS_B8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT3->GTXE2_LOGIC_OUTS_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT4->GTXE2_LOGIC_OUTS_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT5->GTXE2_LOGIC_OUTS_B8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXMONITOROUT6->GTXE2_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE0->GTXE2_LOGIC_OUTS_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE1->GTXE2_LOGIC_OUTS_B14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE2->GTXE2_LOGIC_OUTS_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE3->GTXE2_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE4->GTXE2_LOGIC_OUTS_B14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE5->GTXE2_LOGIC_OUTS_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE6->GTXE2_LOGIC_OUTS_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXNOTINTABLE7->GTXE2_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE7" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXN_PAD->GTXE2_CHANNEL_RXN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXN_PAD" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXOUTCLKPCS->GTXE2_LOGIC_OUTS_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXOUTCLKPCS" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHALIGNDONE" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR0->GTXE2_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR1->GTXE2_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR2->GTXE2_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR3->GTXE2_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHMONITOR4->GTXE2_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR0->GTXE2_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR1->GTXE2_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR2->GTXE2_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR3->GTXE2_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPHSLIPMONITOR4->GTXE2_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXPRBSERR->GTXE2_LOGIC_OUTS_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPRBSERR" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXP_PAD->GTXE2_CHANNEL_RXP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXP_PAD" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXQPISENN->GTXE2_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXQPISENN" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXQPISENP->GTXE2_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXQPISENP" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXRATEDONE->GTXE2_LOGIC_OUTS_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXRATEDONE" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXRESETDONE->GTXE2_LOGIC_OUTS_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXRESETDONE" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXSTARTOFSEQ->GTXE2_LOGIC_OUTS_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTARTOFSEQ" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXSTATUS0->GTXE2_LOGIC_OUTS_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXSTATUS1->GTXE2_LOGIC_OUTS_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXSTATUS2->GTXE2_LOGIC_OUTS_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_RXVALID->GTXE2_LOGIC_OUTS_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXVALID" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_SOUTHREFCLK0->GTXE2_CHANNEL_GTSOUTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_SOUTHREFCLK1->GTXE2_CHANNEL_GTSOUTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT0->GTXE2_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT1->GTXE2_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT2->GTXE2_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT2" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT3->GTXE2_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT3" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT4->GTXE2_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT4" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT5->GTXE2_LOGIC_OUTS_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT5" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT6->GTXE2_LOGIC_OUTS_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT6" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT7->GTXE2_LOGIC_OUTS_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT7" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT8->GTXE2_LOGIC_OUTS_B11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT8" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TSTOUT9->GTXE2_LOGIC_OUTS_B11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT9" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXBUFSTATUS0->GTXE2_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS0" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXBUFSTATUS1->GTXE2_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS1" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXCOMFINISH->GTXE2_LOGIC_OUTS_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXCOMFINISH" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXDLYSRESETDONE" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXGEARBOXREADY->GTXE2_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXGEARBOXREADY" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXN->GTXE2_CHANNEL_TXN_PAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXN_PAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXN" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXOUTCLKPCS->GTXE2_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXOUTCLKPCS" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXP->GTXE2_CHANNEL_TXP_PAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXP_PAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXP" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXPHALIGNDONE" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXPHINITDONE->GTXE2_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXPHINITDONE" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXQPISENN->GTXE2_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXQPISENN" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXQPISENP->GTXE2_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXQPISENP" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXRATEDONE->GTXE2_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXRATEDONE" }, "GTX_CHANNEL_1.GTXE2_CHANNEL_TXRESETDONE->GTXE2_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXRESETDONE" }, "GTX_CHANNEL_1.GTXE2_CLK0_2->GTXE2_CHANNEL_CPLLLOCKDETCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_2" }, "GTX_CHANNEL_1.GTXE2_CLK0_4->GTXE2_CHANNEL_TXUSRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_4" }, "GTX_CHANNEL_1.GTXE2_CLK0_5->GTXE2_CHANNEL_TXUSRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSRCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_5" }, "GTX_CHANNEL_1.GTXE2_CLK0_6->GTXE2_CHANNEL_RXUSRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_6" }, "GTX_CHANNEL_1.GTXE2_CLK0_7->GTXE2_CHANNEL_RXUSRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSRCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_7" }, "GTX_CHANNEL_1.GTXE2_CLK1_1->GTXE2_CHANNEL_DRPCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_1" }, "GTX_CHANNEL_1.GTXE2_CLK1_2->GTXE2_CHANNEL_TXPHDLYTSTCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_2" }, "GTX_CHANNEL_1.GTXE2_CLK1_4->GTXE2_CHANNEL_CLKRSVD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_4" }, "GTX_CHANNEL_1.GTXE2_CLK1_5->GTXE2_CHANNEL_CLKRSVD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_5" }, "GTX_CHANNEL_1.GTXE2_CLK1_6->GTXE2_CHANNEL_GTGREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTGREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_6" }, "GTX_CHANNEL_1.GTXE2_CLK1_7->GTXE2_CHANNEL_CLKRSVD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_7" }, "GTX_CHANNEL_1.GTXE2_CLK1_8->GTXE2_CHANNEL_CLKRSVD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_8" }, "GTX_CHANNEL_1.GTXE2_CTRL0_10->GTXE2_CHANNEL_GTRESETSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRESETSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_10" }, "GTX_CHANNEL_1.GTXE2_CTRL0_3->GTXE2_CHANNEL_CPLLRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_3" }, "GTX_CHANNEL_1.GTXE2_CTRL0_5->GTXE2_CHANNEL_GTTXRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTTXRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_5" }, "GTX_CHANNEL_1.GTXE2_CTRL0_6->GTXE2_CHANNEL_RXDLYSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_6" }, "GTX_CHANNEL_1.GTXE2_CTRL0_7->GTXE2_CHANNEL_RXCDRFREQRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRFREQRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_7" }, "GTX_CHANNEL_1.GTXE2_CTRL0_8->GTXE2_CHANNEL_GTRXRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRXRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_8" }, "GTX_CHANNEL_1.GTXE2_CTRL0_9->GTXE2_CHANNEL_RXDFELPMRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELPMRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_9" }, "GTX_CHANNEL_1.GTXE2_CTRL1_1->GTXE2_CHANNEL_RXPHDLYRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHDLYRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_1" }, "GTX_CHANNEL_1.GTXE2_CTRL1_10->GTXE2_CHANNEL_RXOOBRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOOBRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_10" }, "GTX_CHANNEL_1.GTXE2_CTRL1_3->GTXE2_CHANNEL_TXPMARESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPMARESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_3" }, "GTX_CHANNEL_1.GTXE2_CTRL1_5->GTXE2_CHANNEL_CFGRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CFGRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_5" }, "GTX_CHANNEL_1.GTXE2_CTRL1_6->GTXE2_CHANNEL_RXBUFRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXBUFRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_6" }, "GTX_CHANNEL_1.GTXE2_CTRL1_7->GTXE2_CHANNEL_RXPMARESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPMARESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_7" }, "GTX_CHANNEL_1.GTXE2_CTRL1_8->GTXE2_CHANNEL_RXCDRRESETRSV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRRESETRSV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_8" }, "GTX_CHANNEL_1.GTXE2_CTRL1_9->GTXE2_CHANNEL_RXCDRRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_9" }, "GTX_CHANNEL_1.GTXE2_IMUX0_10->GTXE2_CHANNEL_RXELECIDLEMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_10" }, "GTX_CHANNEL_1.GTXE2_IMUX0_2->GTXE2_CHANNEL_TX8B10BEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_2" }, "GTX_CHANNEL_1.GTXE2_IMUX0_3->GTXE2_CHANNEL_TXMAINCURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_3" }, "GTX_CHANNEL_1.GTXE2_IMUX0_5->GTXE2_CHANNEL_TXSEQUENCE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_5" }, "GTX_CHANNEL_1.GTXE2_IMUX0_6->GTXE2_CHANNEL_PMARSVDIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_6" }, "GTX_CHANNEL_1.GTXE2_IMUX0_7->GTXE2_CHANNEL_PMARSVDIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_7" }, "GTX_CHANNEL_1.GTXE2_IMUX0_8->GTXE2_CHANNEL_PMARSVDIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_8" }, "GTX_CHANNEL_1.GTXE2_IMUX0_9->GTXE2_CHANNEL_PMARSVDIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_9" }, "GTX_CHANNEL_1.GTXE2_IMUX10_0->GTXE2_CHANNEL_TXCHARDISPVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_0" }, "GTX_CHANNEL_1.GTXE2_IMUX10_1->GTXE2_CHANNEL_TXPDELECIDLEMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_1" }, "GTX_CHANNEL_1.GTXE2_IMUX10_2->GTXE2_CHANNEL_TXCHARDISPVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_2" }, "GTX_CHANNEL_1.GTXE2_IMUX10_4->GTXE2_CHANNEL_TXCHARDISPVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_4" }, "GTX_CHANNEL_1.GTXE2_IMUX10_5->GTXE2_CHANNEL_TXUSERRDY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSERRDY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_5" }, "GTX_CHANNEL_1.GTXE2_IMUX10_6->GTXE2_CHANNEL_TXCHARDISPVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_6" }, "GTX_CHANNEL_1.GTXE2_IMUX10_7->GTXE2_CHANNEL_TXBUFDIFFCTRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_7" }, "GTX_CHANNEL_1.GTXE2_IMUX10_9->GTXE2_CHANNEL_RXQPIEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXQPIEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_9" }, "GTX_CHANNEL_1.GTXE2_IMUX11_10->GTXE2_CHANNEL_RXLPMLFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMLFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_10" }, "GTX_CHANNEL_1.GTXE2_IMUX11_2->GTXE2_CHANNEL_CPLLREFCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_2" }, "GTX_CHANNEL_1.GTXE2_IMUX11_5->GTXE2_CHANNEL_TXDLYHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_5" }, "GTX_CHANNEL_1.GTXE2_IMUX11_6->GTXE2_CHANNEL_RXRATE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_6" }, "GTX_CHANNEL_1.GTXE2_IMUX11_8->GTXE2_CHANNEL_RXDFEVSEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVSEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_8" }, "GTX_CHANNEL_1.GTXE2_IMUX12_1->GTXE2_CHANNEL_TXCOMWAKE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMWAKE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_1" }, "GTX_CHANNEL_1.GTXE2_IMUX12_10->GTXE2_CHANNEL_RXDFETAP3OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_10" }, "GTX_CHANNEL_1.GTXE2_IMUX12_2->GTXE2_CHANNEL_TXHEADER1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_2" }, "GTX_CHANNEL_1.GTXE2_IMUX12_4->GTXE2_CHANNEL_TXPHOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_4" }, "GTX_CHANNEL_1.GTXE2_IMUX12_5->GTXE2_CHANNEL_TXDLYOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_5" }, "GTX_CHANNEL_1.GTXE2_IMUX12_7->GTXE2_CHANNEL_TXBUFDIFFCTRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_7" }, "GTX_CHANNEL_1.GTXE2_IMUX12_8->GTXE2_CHANNEL_RXSLIDE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSLIDE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_8" }, "GTX_CHANNEL_1.GTXE2_IMUX12_9->GTXE2_CHANNEL_RX8B10BEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RX8B10BEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_9" }, "GTX_CHANNEL_1.GTXE2_IMUX13_1->GTXE2_CHANNEL_TXQPISTRONGPDOWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_1" }, "GTX_CHANNEL_1.GTXE2_IMUX13_10->GTXE2_CHANNEL_RXPRBSCNTRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSCNTRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_10" }, "GTX_CHANNEL_1.GTXE2_IMUX13_2->GTXE2_CHANNEL_TXHEADER0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_2" }, "GTX_CHANNEL_1.GTXE2_IMUX13_7->GTXE2_CHANNEL_TXBUFDIFFCTRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_7" }, "GTX_CHANNEL_1.GTXE2_IMUX13_8->GTXE2_CHANNEL_RXOSOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOSOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_8" }, "GTX_CHANNEL_1.GTXE2_IMUX13_9->GTXE2_CHANNEL_RXDFETAP5OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_9" }, "GTX_CHANNEL_1.GTXE2_IMUX14_10->GTXE2_CHANNEL_RXPHOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_10" }, "GTX_CHANNEL_1.GTXE2_IMUX14_2->GTXE2_CHANNEL_CPLLREFCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_2" }, "GTX_CHANNEL_1.GTXE2_IMUX14_5->GTXE2_CHANNEL_TXDLYEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_5" }, "GTX_CHANNEL_1.GTXE2_IMUX14_6->GTXE2_CHANNEL_RXRATE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_6" }, "GTX_CHANNEL_1.GTXE2_IMUX14_7->GTXE2_CHANNEL_RXPCSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPCSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_7" }, "GTX_CHANNEL_1.GTXE2_IMUX14_8->GTXE2_CHANNEL_RXCDROVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDROVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_8" }, "GTX_CHANNEL_1.GTXE2_IMUX14_9->GTXE2_CHANNEL_RXPHALIGN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHALIGN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_9" }, "GTX_CHANNEL_1.GTXE2_IMUX15_1->GTXE2_CHANNEL_TX8B10BBYPASS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_1" }, "GTX_CHANNEL_1.GTXE2_IMUX15_2->GTXE2_CHANNEL_CPLLREFCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_2" }, "GTX_CHANNEL_1.GTXE2_IMUX15_3->GTXE2_CHANNEL_TX8B10BBYPASS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_3" }, "GTX_CHANNEL_1.GTXE2_IMUX15_4->GTXE2_CHANNEL_TXPRBSFORCEERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSFORCEERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_4" }, "GTX_CHANNEL_1.GTXE2_IMUX15_5->GTXE2_CHANNEL_TX8B10BBYPASS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_5" }, "GTX_CHANNEL_1.GTXE2_IMUX15_6->GTXE2_CHANNEL_RXRATE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_6" }, "GTX_CHANNEL_1.GTXE2_IMUX15_7->GTXE2_CHANNEL_TX8B10BBYPASS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_7" }, "GTX_CHANNEL_1.GTXE2_IMUX16_0->GTXE2_CHANNEL_TXDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_0" }, "GTX_CHANNEL_1.GTXE2_IMUX16_1->GTXE2_CHANNEL_TXDATA56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_1" }, "GTX_CHANNEL_1.GTXE2_IMUX16_10->GTXE2_CHANNEL_RXDFECM1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFECM1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_10" }, "GTX_CHANNEL_1.GTXE2_IMUX16_2->GTXE2_CHANNEL_TXDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_2" }, "GTX_CHANNEL_1.GTXE2_IMUX16_3->GTXE2_CHANNEL_TXDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_3" }, "GTX_CHANNEL_1.GTXE2_IMUX16_4->GTXE2_CHANNEL_TXDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_4" }, "GTX_CHANNEL_1.GTXE2_IMUX16_5->GTXE2_CHANNEL_TXDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_5" }, "GTX_CHANNEL_1.GTXE2_IMUX16_6->GTXE2_CHANNEL_TXDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_6" }, "GTX_CHANNEL_1.GTXE2_IMUX16_7->GTXE2_CHANNEL_TXDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_7" }, "GTX_CHANNEL_1.GTXE2_IMUX17_0->GTXE2_CHANNEL_TXDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_0" }, "GTX_CHANNEL_1.GTXE2_IMUX17_1->GTXE2_CHANNEL_TXDATA57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_1" }, "GTX_CHANNEL_1.GTXE2_IMUX17_2->GTXE2_CHANNEL_TXDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_2" }, "GTX_CHANNEL_1.GTXE2_IMUX17_3->GTXE2_CHANNEL_TXDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_3" }, "GTX_CHANNEL_1.GTXE2_IMUX17_4->GTXE2_CHANNEL_TXDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_4" }, "GTX_CHANNEL_1.GTXE2_IMUX17_5->GTXE2_CHANNEL_TXDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_5" }, "GTX_CHANNEL_1.GTXE2_IMUX17_6->GTXE2_CHANNEL_TXDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_6" }, "GTX_CHANNEL_1.GTXE2_IMUX17_7->GTXE2_CHANNEL_TXDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_7" }, "GTX_CHANNEL_1.GTXE2_IMUX17_9->GTXE2_CHANNEL_RXCHBONDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_9" }, "GTX_CHANNEL_1.GTXE2_IMUX18_0->GTXE2_CHANNEL_TXDATA60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_0" }, "GTX_CHANNEL_1.GTXE2_IMUX18_1->GTXE2_CHANNEL_TXDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_1" }, "GTX_CHANNEL_1.GTXE2_IMUX18_10->GTXE2_CHANNEL_RXCHBONDLEVEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_10" }, "GTX_CHANNEL_1.GTXE2_IMUX18_2->GTXE2_CHANNEL_TXDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_2" }, "GTX_CHANNEL_1.GTXE2_IMUX18_3->GTXE2_CHANNEL_TXDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_3" }, "GTX_CHANNEL_1.GTXE2_IMUX18_4->GTXE2_CHANNEL_TXDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_4" }, "GTX_CHANNEL_1.GTXE2_IMUX18_5->GTXE2_CHANNEL_TXDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_5" }, "GTX_CHANNEL_1.GTXE2_IMUX18_6->GTXE2_CHANNEL_TXDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_6" }, "GTX_CHANNEL_1.GTXE2_IMUX18_7->GTXE2_CHANNEL_TXDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_7" }, "GTX_CHANNEL_1.GTXE2_IMUX18_9->GTXE2_CHANNEL_RXCHBONDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_9" }, "GTX_CHANNEL_1.GTXE2_IMUX19_0->GTXE2_CHANNEL_TXDATA61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_0" }, "GTX_CHANNEL_1.GTXE2_IMUX19_1->GTXE2_CHANNEL_TXDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_1" }, "GTX_CHANNEL_1.GTXE2_IMUX19_10->GTXE2_CHANNEL_RXCHBONDLEVEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_10" }, "GTX_CHANNEL_1.GTXE2_IMUX19_2->GTXE2_CHANNEL_TXDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_2" }, "GTX_CHANNEL_1.GTXE2_IMUX19_3->GTXE2_CHANNEL_TXDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_3" }, "GTX_CHANNEL_1.GTXE2_IMUX19_4->GTXE2_CHANNEL_TXDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_4" }, "GTX_CHANNEL_1.GTXE2_IMUX19_5->GTXE2_CHANNEL_TXDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_5" }, "GTX_CHANNEL_1.GTXE2_IMUX19_6->GTXE2_CHANNEL_TXDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_6" }, "GTX_CHANNEL_1.GTXE2_IMUX19_7->GTXE2_CHANNEL_TXDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_7" }, "GTX_CHANNEL_1.GTXE2_IMUX19_8->GTXE2_CHANNEL_RXDFEVPHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVPHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_8" }, "GTX_CHANNEL_1.GTXE2_IMUX19_9->GTXE2_CHANNEL_RXCHBONDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_9" }, "GTX_CHANNEL_1.GTXE2_IMUX1_10->GTXE2_CHANNEL_RXELECIDLEMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_10" }, "GTX_CHANNEL_1.GTXE2_IMUX1_2->GTXE2_CHANNEL_RXMONITORSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_2" }, "GTX_CHANNEL_1.GTXE2_IMUX1_3->GTXE2_CHANNEL_TXMAINCURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_3" }, "GTX_CHANNEL_1.GTXE2_IMUX1_4->GTXE2_CHANNEL_TXMAINCURSOR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_4" }, "GTX_CHANNEL_1.GTXE2_IMUX1_5->GTXE2_CHANNEL_TXSEQUENCE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_5" }, "GTX_CHANNEL_1.GTXE2_IMUX1_6->GTXE2_CHANNEL_TXSEQUENCE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_6" }, "GTX_CHANNEL_1.GTXE2_IMUX1_7->GTXE2_CHANNEL_PMARSVDIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_7" }, "GTX_CHANNEL_1.GTXE2_IMUX1_8->GTXE2_CHANNEL_TXOUTCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_8" }, "GTX_CHANNEL_1.GTXE2_IMUX1_9->GTXE2_CHANNEL_PMARSVDIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_9" }, "GTX_CHANNEL_1.GTXE2_IMUX20_0->GTXE2_CHANNEL_TXDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_0" }, "GTX_CHANNEL_1.GTXE2_IMUX20_1->GTXE2_CHANNEL_TXDATA58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_1" }, "GTX_CHANNEL_1.GTXE2_IMUX20_2->GTXE2_CHANNEL_TXDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_2" }, "GTX_CHANNEL_1.GTXE2_IMUX20_3->GTXE2_CHANNEL_TXDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_3" }, "GTX_CHANNEL_1.GTXE2_IMUX20_4->GTXE2_CHANNEL_TXDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_4" }, "GTX_CHANNEL_1.GTXE2_IMUX20_5->GTXE2_CHANNEL_TXDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_5" }, "GTX_CHANNEL_1.GTXE2_IMUX20_6->GTXE2_CHANNEL_TXDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_6" }, "GTX_CHANNEL_1.GTXE2_IMUX20_7->GTXE2_CHANNEL_TXDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_7" }, "GTX_CHANNEL_1.GTXE2_IMUX21_0->GTXE2_CHANNEL_TXDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_0" }, "GTX_CHANNEL_1.GTXE2_IMUX21_1->GTXE2_CHANNEL_TXDATA59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_1" }, "GTX_CHANNEL_1.GTXE2_IMUX21_10->GTXE2_CHANNEL_RXDFEAGCOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_10" }, "GTX_CHANNEL_1.GTXE2_IMUX21_2->GTXE2_CHANNEL_TXDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_2" }, "GTX_CHANNEL_1.GTXE2_IMUX21_3->GTXE2_CHANNEL_TXDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_3" }, "GTX_CHANNEL_1.GTXE2_IMUX21_4->GTXE2_CHANNEL_TXDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_4" }, "GTX_CHANNEL_1.GTXE2_IMUX21_5->GTXE2_CHANNEL_TXDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_5" }, "GTX_CHANNEL_1.GTXE2_IMUX21_6->GTXE2_CHANNEL_TXDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_6" }, "GTX_CHANNEL_1.GTXE2_IMUX21_7->GTXE2_CHANNEL_TXDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_7" }, "GTX_CHANNEL_1.GTXE2_IMUX21_8->GTXE2_CHANNEL_RXDFEXYDOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_8" }, "GTX_CHANNEL_1.GTXE2_IMUX21_9->GTXE2_CHANNEL_RXDFETAP4OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_9" }, "GTX_CHANNEL_1.GTXE2_IMUX22_0->GTXE2_CHANNEL_TXDATA62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_0" }, "GTX_CHANNEL_1.GTXE2_IMUX22_1->GTXE2_CHANNEL_TXDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_1" }, "GTX_CHANNEL_1.GTXE2_IMUX22_10->GTXE2_CHANNEL_RXCHBONDLEVEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_10" }, "GTX_CHANNEL_1.GTXE2_IMUX22_2->GTXE2_CHANNEL_TXDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_2" }, "GTX_CHANNEL_1.GTXE2_IMUX22_3->GTXE2_CHANNEL_TXDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_3" }, "GTX_CHANNEL_1.GTXE2_IMUX22_4->GTXE2_CHANNEL_TXDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_4" }, "GTX_CHANNEL_1.GTXE2_IMUX22_5->GTXE2_CHANNEL_TXDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_5" }, "GTX_CHANNEL_1.GTXE2_IMUX22_6->GTXE2_CHANNEL_TXDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_6" }, "GTX_CHANNEL_1.GTXE2_IMUX22_7->GTXE2_CHANNEL_TXDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_7" }, "GTX_CHANNEL_1.GTXE2_IMUX22_8->GTXE2_CHANNEL_RXPRBSSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_8" }, "GTX_CHANNEL_1.GTXE2_IMUX22_9->GTXE2_CHANNEL_RXCHBONDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_9" }, "GTX_CHANNEL_1.GTXE2_IMUX23_0->GTXE2_CHANNEL_TXDATA63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_0" }, "GTX_CHANNEL_1.GTXE2_IMUX23_1->GTXE2_CHANNEL_TXDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_1" }, "GTX_CHANNEL_1.GTXE2_IMUX23_10->GTXE2_CHANNEL_RXCHBONDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_10" }, "GTX_CHANNEL_1.GTXE2_IMUX23_2->GTXE2_CHANNEL_TXDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_2" }, "GTX_CHANNEL_1.GTXE2_IMUX23_3->GTXE2_CHANNEL_TXDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_3" }, "GTX_CHANNEL_1.GTXE2_IMUX23_4->GTXE2_CHANNEL_TXDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_4" }, "GTX_CHANNEL_1.GTXE2_IMUX23_5->GTXE2_CHANNEL_TXDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_5" }, "GTX_CHANNEL_1.GTXE2_IMUX23_6->GTXE2_CHANNEL_TXDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_6" }, "GTX_CHANNEL_1.GTXE2_IMUX23_7->GTXE2_CHANNEL_TXDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_7" }, "GTX_CHANNEL_1.GTXE2_IMUX23_8->GTXE2_CHANNEL_RXPRBSSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_8" }, "GTX_CHANNEL_1.GTXE2_IMUX23_9->GTXE2_CHANNEL_RXCHBONDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_9" }, "GTX_CHANNEL_1.GTXE2_IMUX24_1->GTXE2_CHANNEL_TSTIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_1" }, "GTX_CHANNEL_1.GTXE2_IMUX24_10->GTXE2_CHANNEL_TSTIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_10" }, "GTX_CHANNEL_1.GTXE2_IMUX24_2->GTXE2_CHANNEL_TSTIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_2" }, "GTX_CHANNEL_1.GTXE2_IMUX24_3->GTXE2_CHANNEL_TSTIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_3" }, "GTX_CHANNEL_1.GTXE2_IMUX24_4->GTXE2_CHANNEL_TSTIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_4" }, "GTX_CHANNEL_1.GTXE2_IMUX24_5->GTXE2_CHANNEL_TSTIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_5" }, "GTX_CHANNEL_1.GTXE2_IMUX24_6->GTXE2_CHANNEL_TSTIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_6" }, "GTX_CHANNEL_1.GTXE2_IMUX24_7->GTXE2_CHANNEL_TSTIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_7" }, "GTX_CHANNEL_1.GTXE2_IMUX24_8->GTXE2_CHANNEL_TSTIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_8" }, "GTX_CHANNEL_1.GTXE2_IMUX24_9->GTXE2_CHANNEL_TSTIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_9" }, "GTX_CHANNEL_1.GTXE2_IMUX25_10->GTXE2_CHANNEL_PCSRSVDIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_10" }, "GTX_CHANNEL_1.GTXE2_IMUX25_2->GTXE2_CHANNEL_TXPHALIGN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHALIGN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_2" }, "GTX_CHANNEL_1.GTXE2_IMUX25_3->GTXE2_CHANNEL_PCSRSVDIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_3" }, "GTX_CHANNEL_1.GTXE2_IMUX25_4->GTXE2_CHANNEL_PCSRSVDIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_4" }, "GTX_CHANNEL_1.GTXE2_IMUX25_5->GTXE2_CHANNEL_PCSRSVDIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_5" }, "GTX_CHANNEL_1.GTXE2_IMUX25_6->GTXE2_CHANNEL_PCSRSVDIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_6" }, "GTX_CHANNEL_1.GTXE2_IMUX25_7->GTXE2_CHANNEL_PCSRSVDIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_7" }, "GTX_CHANNEL_1.GTXE2_IMUX25_8->GTXE2_CHANNEL_PCSRSVDIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_8" }, "GTX_CHANNEL_1.GTXE2_IMUX25_9->GTXE2_CHANNEL_PCSRSVDIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_9" }, "GTX_CHANNEL_1.GTXE2_IMUX26_10->GTXE2_CHANNEL_GTRSVD15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_10" }, "GTX_CHANNEL_1.GTXE2_IMUX26_3->GTXE2_CHANNEL_GTRSVD8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_3" }, "GTX_CHANNEL_1.GTXE2_IMUX26_4->GTXE2_CHANNEL_GTRSVD9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_4" }, "GTX_CHANNEL_1.GTXE2_IMUX26_5->GTXE2_CHANNEL_GTRSVD10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_5" }, "GTX_CHANNEL_1.GTXE2_IMUX26_6->GTXE2_CHANNEL_GTRSVD11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_6" }, "GTX_CHANNEL_1.GTXE2_IMUX26_7->GTXE2_CHANNEL_GTRSVD12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_7" }, "GTX_CHANNEL_1.GTXE2_IMUX26_8->GTXE2_CHANNEL_GTRSVD13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_8" }, "GTX_CHANNEL_1.GTXE2_IMUX26_9->GTXE2_CHANNEL_GTRSVD14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_9" }, "GTX_CHANNEL_1.GTXE2_IMUX27_10->GTXE2_CHANNEL_RXLPMHFOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_10" }, "GTX_CHANNEL_1.GTXE2_IMUX27_5->GTXE2_CHANNEL_TXPHINIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHINIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_5" }, "GTX_CHANNEL_1.GTXE2_IMUX27_7->GTXE2_CHANNEL_RXPOLARITY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPOLARITY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_7" }, "GTX_CHANNEL_1.GTXE2_IMUX27_8->GTXE2_CHANNEL_RXDFEVPOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_8" }, "GTX_CHANNEL_1.GTXE2_IMUX27_9->GTXE2_CHANNEL_RXDFELFOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELFOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_9" }, "GTX_CHANNEL_1.GTXE2_IMUX28_1->GTXE2_CHANNEL_TXCOMSAS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMSAS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_1" }, "GTX_CHANNEL_1.GTXE2_IMUX28_10->GTXE2_CHANNEL_RXDFETAP2OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_10" }, "GTX_CHANNEL_1.GTXE2_IMUX28_2->GTXE2_CHANNEL_CPLLLOCKEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLLOCKEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_2" }, "GTX_CHANNEL_1.GTXE2_IMUX28_3->GTXE2_CHANNEL_DRPWE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPWE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_3" }, "GTX_CHANNEL_1.GTXE2_IMUX28_4->GTXE2_CHANNEL_TXSYSCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_4" }, "GTX_CHANNEL_1.GTXE2_IMUX28_5->GTXE2_CHANNEL_TXSYSCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_5" }, "GTX_CHANNEL_1.GTXE2_IMUX28_6->GTXE2_CHANNEL_RXDLYEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_6" }, "GTX_CHANNEL_1.GTXE2_IMUX28_8->GTXE2_CHANNEL_RXPD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_8" }, "GTX_CHANNEL_1.GTXE2_IMUX29_0->GTXE2_CHANNEL_TXCHARDISPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_0" }, "GTX_CHANNEL_1.GTXE2_IMUX29_1->GTXE2_CHANNEL_TXCHARISK7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_1" }, "GTX_CHANNEL_1.GTXE2_IMUX29_10->GTXE2_CHANNEL_RXDFEAGCHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEAGCHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_10" }, "GTX_CHANNEL_1.GTXE2_IMUX29_2->GTXE2_CHANNEL_TXCHARDISPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_2" }, "GTX_CHANNEL_1.GTXE2_IMUX29_3->GTXE2_CHANNEL_TXCHARISK6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_3" }, "GTX_CHANNEL_1.GTXE2_IMUX29_4->GTXE2_CHANNEL_TXCHARDISPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_4" }, "GTX_CHANNEL_1.GTXE2_IMUX29_5->GTXE2_CHANNEL_TXCHARISK5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_5" }, "GTX_CHANNEL_1.GTXE2_IMUX29_6->GTXE2_CHANNEL_TXCHARDISPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_6" }, "GTX_CHANNEL_1.GTXE2_IMUX29_7->GTXE2_CHANNEL_TXCHARISK4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_7" }, "GTX_CHANNEL_1.GTXE2_IMUX29_8->GTXE2_CHANNEL_RXOSHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOSHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_8" }, "GTX_CHANNEL_1.GTXE2_IMUX29_9->GTXE2_CHANNEL_RXDFETAP5HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP5HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_9" }, "GTX_CHANNEL_1.GTXE2_IMUX2_10->GTXE2_CHANNEL_RXOUTCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_10" }, "GTX_CHANNEL_1.GTXE2_IMUX2_3->GTXE2_CHANNEL_DRPADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_3" }, "GTX_CHANNEL_1.GTXE2_IMUX2_4->GTXE2_CHANNEL_TXPOSTCURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_4" }, "GTX_CHANNEL_1.GTXE2_IMUX2_5->GTXE2_CHANNEL_TXDIFFCTRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_5" }, "GTX_CHANNEL_1.GTXE2_IMUX2_6->GTXE2_CHANNEL_TXPRECURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_6" }, "GTX_CHANNEL_1.GTXE2_IMUX2_8->GTXE2_CHANNEL_RXGEARBOXSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXGEARBOXSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_8" }, "GTX_CHANNEL_1.GTXE2_IMUX2_9->GTXE2_CHANNEL_RXMCOMMAALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_9" }, "GTX_CHANNEL_1.GTXE2_IMUX30_10->GTXE2_CHANNEL_RXCHBONDSLAVE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDSLAVE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_10" }, "GTX_CHANNEL_1.GTXE2_IMUX30_3->GTXE2_CHANNEL_TXPOLARITY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOLARITY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_3" }, "GTX_CHANNEL_1.GTXE2_IMUX30_7->GTXE2_CHANNEL_TXPCSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPCSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_7" }, "GTX_CHANNEL_1.GTXE2_IMUX30_8->GTXE2_CHANNEL_RXCDRHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_8" }, "GTX_CHANNEL_1.GTXE2_IMUX30_9->GTXE2_CHANNEL_RXCHBONDMASTER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDMASTER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_9" }, "GTX_CHANNEL_1.GTXE2_IMUX31_0->GTXE2_CHANNEL_TXCHARDISPMODE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_0" }, "GTX_CHANNEL_1.GTXE2_IMUX31_1->GTXE2_CHANNEL_TXCHARISK3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_1" }, "GTX_CHANNEL_1.GTXE2_IMUX31_2->GTXE2_CHANNEL_TXCHARDISPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_2" }, "GTX_CHANNEL_1.GTXE2_IMUX31_3->GTXE2_CHANNEL_TXCHARISK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_3" }, "GTX_CHANNEL_1.GTXE2_IMUX31_4->GTXE2_CHANNEL_TXCHARDISPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_4" }, "GTX_CHANNEL_1.GTXE2_IMUX31_5->GTXE2_CHANNEL_TXCHARISK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_5" }, "GTX_CHANNEL_1.GTXE2_IMUX31_6->GTXE2_CHANNEL_TXCHARDISPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_6" }, "GTX_CHANNEL_1.GTXE2_IMUX31_7->GTXE2_CHANNEL_TXCHARISK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_7" }, "GTX_CHANNEL_1.GTXE2_IMUX31_8->GTXE2_CHANNEL_EYESCANTRIGGER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANTRIGGER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_8" }, "GTX_CHANNEL_1.GTXE2_IMUX32_0->GTXE2_CHANNEL_DRPDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_0" }, "GTX_CHANNEL_1.GTXE2_IMUX32_1->GTXE2_CHANNEL_DRPDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_1" }, "GTX_CHANNEL_1.GTXE2_IMUX32_2->GTXE2_CHANNEL_TXINHIBIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXINHIBIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_2" }, "GTX_CHANNEL_1.GTXE2_IMUX32_8->GTXE2_CHANNEL_RXDLYBYPASS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYBYPASS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_8" }, "GTX_CHANNEL_1.GTXE2_IMUX33_0->GTXE2_CHANNEL_DRPDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_0" }, "GTX_CHANNEL_1.GTXE2_IMUX33_1->GTXE2_CHANNEL_DRPDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_1" }, "GTX_CHANNEL_1.GTXE2_IMUX33_2->GTXE2_CHANNEL_TXPHALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_2" }, "GTX_CHANNEL_1.GTXE2_IMUX34_0->GTXE2_CHANNEL_DRPDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_0" }, "GTX_CHANNEL_1.GTXE2_IMUX34_1->GTXE2_CHANNEL_DRPDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_1" }, "GTX_CHANNEL_1.GTXE2_IMUX34_10->GTXE2_CHANNEL_PCSRSVDIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_10" }, "GTX_CHANNEL_1.GTXE2_IMUX34_2->GTXE2_CHANNEL_DRPADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_2" }, "GTX_CHANNEL_1.GTXE2_IMUX34_3->GTXE2_CHANNEL_DRPADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_3" }, "GTX_CHANNEL_1.GTXE2_IMUX34_4->GTXE2_CHANNEL_SETERRSTATUS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_SETERRSTATUS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_4" }, "GTX_CHANNEL_1.GTXE2_IMUX34_8->GTXE2_CHANNEL_RXLPMEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_8" }, "GTX_CHANNEL_1.GTXE2_IMUX34_9->GTXE2_CHANNEL_RXPCOMMAALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_9" }, "GTX_CHANNEL_1.GTXE2_IMUX35_0->GTXE2_CHANNEL_DRPDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_0" }, "GTX_CHANNEL_1.GTXE2_IMUX35_1->GTXE2_CHANNEL_DRPDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_1" }, "GTX_CHANNEL_1.GTXE2_IMUX35_10->GTXE2_CHANNEL_PCSRSVDIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_10" }, "GTX_CHANNEL_1.GTXE2_IMUX35_2->GTXE2_CHANNEL_DRPADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_2" }, "GTX_CHANNEL_1.GTXE2_IMUX35_3->GTXE2_CHANNEL_DRPADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_3" }, "GTX_CHANNEL_1.GTXE2_IMUX35_4->GTXE2_CHANNEL_TXMARGIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_4" }, "GTX_CHANNEL_1.GTXE2_IMUX35_5->GTXE2_CHANNEL_TXDEEMPH": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDEEMPH", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_5" }, "GTX_CHANNEL_1.GTXE2_IMUX35_6->GTXE2_CHANNEL_TXPD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_6" }, "GTX_CHANNEL_1.GTXE2_IMUX35_8->GTXE2_CHANNEL_RXDFEUTOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_8" }, "GTX_CHANNEL_1.GTXE2_IMUX35_9->GTXE2_CHANNEL_RXDFELFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_9" }, "GTX_CHANNEL_1.GTXE2_IMUX36_0->GTXE2_CHANNEL_DRPDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_0" }, "GTX_CHANNEL_1.GTXE2_IMUX36_1->GTXE2_CHANNEL_DRPDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_1" }, "GTX_CHANNEL_1.GTXE2_IMUX36_10->GTXE2_CHANNEL_RXDFETAP3HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP3HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_10" }, "GTX_CHANNEL_1.GTXE2_IMUX36_2->GTXE2_CHANNEL_CPLLPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_2" }, "GTX_CHANNEL_1.GTXE2_IMUX36_5->GTXE2_CHANNEL_TXPHDLYRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_5" }, "GTX_CHANNEL_1.GTXE2_IMUX37_0->GTXE2_CHANNEL_DRPDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_0" }, "GTX_CHANNEL_1.GTXE2_IMUX37_1->GTXE2_CHANNEL_DRPDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_1" }, "GTX_CHANNEL_1.GTXE2_IMUX37_3->GTXE2_CHANNEL_TXPHDLYPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_3" }, "GTX_CHANNEL_1.GTXE2_IMUX37_4->GTXE2_CHANNEL_TXDIFFPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_4" }, "GTX_CHANNEL_1.GTXE2_IMUX37_8->GTXE2_CHANNEL_RXDFEXYDHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_8" }, "GTX_CHANNEL_1.GTXE2_IMUX37_9->GTXE2_CHANNEL_RXDFETAP4HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP4HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_9" }, "GTX_CHANNEL_1.GTXE2_IMUX38_0->GTXE2_CHANNEL_DRPDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_0" }, "GTX_CHANNEL_1.GTXE2_IMUX38_1->GTXE2_CHANNEL_DRPDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_1" }, "GTX_CHANNEL_1.GTXE2_IMUX38_10->GTXE2_CHANNEL_PCSRSVDIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_10" }, "GTX_CHANNEL_1.GTXE2_IMUX38_2->GTXE2_CHANNEL_DRPADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_2" }, "GTX_CHANNEL_1.GTXE2_IMUX38_3->GTXE2_CHANNEL_DRPADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_3" }, "GTX_CHANNEL_1.GTXE2_IMUX38_4->GTXE2_CHANNEL_TXMARGIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_4" }, "GTX_CHANNEL_1.GTXE2_IMUX38_5->GTXE2_CHANNEL_TXSWING": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSWING", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_5" }, "GTX_CHANNEL_1.GTXE2_IMUX38_6->GTXE2_CHANNEL_TXPD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_6" }, "GTX_CHANNEL_1.GTXE2_IMUX38_7->GTXE2_CHANNEL_RXDLYOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_7" }, "GTX_CHANNEL_1.GTXE2_IMUX38_8->GTXE2_CHANNEL_RXPRBSSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_8" }, "GTX_CHANNEL_1.GTXE2_IMUX39_0->GTXE2_CHANNEL_DRPDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_0" }, "GTX_CHANNEL_1.GTXE2_IMUX39_1->GTXE2_CHANNEL_DRPDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_1" }, "GTX_CHANNEL_1.GTXE2_IMUX39_10->GTXE2_CHANNEL_PCSRSVDIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_10" }, "GTX_CHANNEL_1.GTXE2_IMUX39_2->GTXE2_CHANNEL_DRPADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_2" }, "GTX_CHANNEL_1.GTXE2_IMUX39_3->GTXE2_CHANNEL_DRPADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_3" }, "GTX_CHANNEL_1.GTXE2_IMUX39_4->GTXE2_CHANNEL_TXMARGIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_4" }, "GTX_CHANNEL_1.GTXE2_IMUX39_5->GTXE2_CHANNEL_TXDETECTRX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDETECTRX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_5" }, "GTX_CHANNEL_1.GTXE2_IMUX39_6->GTXE2_CHANNEL_TXELECIDLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXELECIDLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_6" }, "GTX_CHANNEL_1.GTXE2_IMUX39_9->GTXE2_CHANNEL_PCSRSVDIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_9" }, "GTX_CHANNEL_1.GTXE2_IMUX3_10->GTXE2_CHANNEL_RXLPMLFKLOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_10" }, "GTX_CHANNEL_1.GTXE2_IMUX3_3->GTXE2_CHANNEL_TXSTARTSEQ": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSTARTSEQ", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_3" }, "GTX_CHANNEL_1.GTXE2_IMUX3_4->GTXE2_CHANNEL_TXPOSTCURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_4" }, "GTX_CHANNEL_1.GTXE2_IMUX3_5->GTXE2_CHANNEL_TXDIFFCTRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_5" }, "GTX_CHANNEL_1.GTXE2_IMUX3_6->GTXE2_CHANNEL_TXPRECURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_6" }, "GTX_CHANNEL_1.GTXE2_IMUX3_7->GTXE2_CHANNEL_RXPD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_7" }, "GTX_CHANNEL_1.GTXE2_IMUX3_8->GTXE2_CHANNEL_TXPRBSSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_8" }, "GTX_CHANNEL_1.GTXE2_IMUX3_9->GTXE2_CHANNEL_RXDFEUTHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEUTHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_9" }, "GTX_CHANNEL_1.GTXE2_IMUX40_1->GTXE2_CHANNEL_TSTIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_1" }, "GTX_CHANNEL_1.GTXE2_IMUX40_10->GTXE2_CHANNEL_TSTIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_10" }, "GTX_CHANNEL_1.GTXE2_IMUX40_2->GTXE2_CHANNEL_TSTIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_2" }, "GTX_CHANNEL_1.GTXE2_IMUX40_3->GTXE2_CHANNEL_TSTIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_3" }, "GTX_CHANNEL_1.GTXE2_IMUX40_4->GTXE2_CHANNEL_TSTIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_4" }, "GTX_CHANNEL_1.GTXE2_IMUX40_5->GTXE2_CHANNEL_TSTIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_5" }, "GTX_CHANNEL_1.GTXE2_IMUX40_6->GTXE2_CHANNEL_TSTIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_6" }, "GTX_CHANNEL_1.GTXE2_IMUX40_7->GTXE2_CHANNEL_TSTIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_7" }, "GTX_CHANNEL_1.GTXE2_IMUX40_8->GTXE2_CHANNEL_TSTIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_8" }, "GTX_CHANNEL_1.GTXE2_IMUX40_9->GTXE2_CHANNEL_TSTIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_9" }, "GTX_CHANNEL_1.GTXE2_IMUX41_0->GTXE2_CHANNEL_EYESCANMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_0" }, "GTX_CHANNEL_1.GTXE2_IMUX41_1->GTXE2_CHANNEL_TXPOSTCURSORINV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSORINV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_1" }, "GTX_CHANNEL_1.GTXE2_IMUX41_5->GTXE2_CHANNEL_RESETOVRD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RESETOVRD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_5" }, "GTX_CHANNEL_1.GTXE2_IMUX41_6->GTXE2_CHANNEL_RXPHALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_6" }, "GTX_CHANNEL_1.GTXE2_IMUX42_10->GTXE2_CHANNEL_GTRSVD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_10" }, "GTX_CHANNEL_1.GTXE2_IMUX42_2->GTXE2_CHANNEL_RXSYSCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_2" }, "GTX_CHANNEL_1.GTXE2_IMUX42_3->GTXE2_CHANNEL_GTRSVD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_3" }, "GTX_CHANNEL_1.GTXE2_IMUX42_4->GTXE2_CHANNEL_GTRSVD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_4" }, "GTX_CHANNEL_1.GTXE2_IMUX42_5->GTXE2_CHANNEL_GTRSVD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_5" }, "GTX_CHANNEL_1.GTXE2_IMUX42_6->GTXE2_CHANNEL_GTRSVD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_6" }, "GTX_CHANNEL_1.GTXE2_IMUX42_7->GTXE2_CHANNEL_GTRSVD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_7" }, "GTX_CHANNEL_1.GTXE2_IMUX42_8->GTXE2_CHANNEL_GTRSVD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_8" }, "GTX_CHANNEL_1.GTXE2_IMUX42_9->GTXE2_CHANNEL_GTRSVD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_9" }, "GTX_CHANNEL_1.GTXE2_IMUX43_10->GTXE2_CHANNEL_RXLPMHFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMHFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_10" }, "GTX_CHANNEL_1.GTXE2_IMUX43_5->GTXE2_CHANNEL_TXDLYUPDOWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYUPDOWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_5" }, "GTX_CHANNEL_1.GTXE2_IMUX43_6->GTXE2_CHANNEL_TXRATE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_6" }, "GTX_CHANNEL_1.GTXE2_IMUX43_9->GTXE2_CHANNEL_LOOPBACK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_9" }, "GTX_CHANNEL_1.GTXE2_IMUX44_1->GTXE2_CHANNEL_TXCOMINIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMINIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_1" }, "GTX_CHANNEL_1.GTXE2_IMUX44_10->GTXE2_CHANNEL_RXDFETAP2HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP2HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_10" }, "GTX_CHANNEL_1.GTXE2_IMUX44_3->GTXE2_CHANNEL_DRPEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_3" }, "GTX_CHANNEL_1.GTXE2_IMUX44_5->GTXE2_CHANNEL_TXDLYBYPASS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYBYPASS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_5" }, "GTX_CHANNEL_1.GTXE2_IMUX44_8->GTXE2_CHANNEL_RXUSERRDY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSERRDY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_8" }, "GTX_CHANNEL_1.GTXE2_IMUX44_9->GTXE2_CHANNEL_RXCOMMADETEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCOMMADETEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_9" }, "GTX_CHANNEL_1.GTXE2_IMUX45_1->GTXE2_CHANNEL_TXQPIWEAKPUP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPIWEAKPUP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_1" }, "GTX_CHANNEL_1.GTXE2_IMUX45_10->GTXE2_CHANNEL_RXMONITORSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_10" }, "GTX_CHANNEL_1.GTXE2_IMUX45_2->GTXE2_CHANNEL_RXSYSCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_2" }, "GTX_CHANNEL_1.GTXE2_IMUX45_3->GTXE2_CHANNEL_TXDLYSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_3" }, "GTX_CHANNEL_1.GTXE2_IMUX45_8->GTXE2_CHANNEL_EYESCANRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_8" }, "GTX_CHANNEL_1.GTXE2_IMUX45_9->GTXE2_CHANNEL_RXDFEXYDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_9" }, "GTX_CHANNEL_1.GTXE2_IMUX46_6->GTXE2_CHANNEL_TXRATE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX46_6" }, "GTX_CHANNEL_1.GTXE2_IMUX46_9->GTXE2_CHANNEL_LOOPBACK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX46_9" }, "GTX_CHANNEL_1.GTXE2_IMUX47_6->GTXE2_CHANNEL_TXRATE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX47_6" }, "GTX_CHANNEL_1.GTXE2_IMUX47_9->GTXE2_CHANNEL_LOOPBACK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX47_9" }, "GTX_CHANNEL_1.GTXE2_IMUX4_1->GTXE2_CHANNEL_TXPRECURSORINV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSORINV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_1" }, "GTX_CHANNEL_1.GTXE2_IMUX4_10->GTXE2_CHANNEL_RXOUTCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_10" }, "GTX_CHANNEL_1.GTXE2_IMUX4_3->GTXE2_CHANNEL_TXMAINCURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_3" }, "GTX_CHANNEL_1.GTXE2_IMUX4_4->GTXE2_CHANNEL_TXMAINCURSOR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_4" }, "GTX_CHANNEL_1.GTXE2_IMUX4_5->GTXE2_CHANNEL_TXSEQUENCE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_5" }, "GTX_CHANNEL_1.GTXE2_IMUX4_6->GTXE2_CHANNEL_TXSEQUENCE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_6" }, "GTX_CHANNEL_1.GTXE2_IMUX4_7->GTXE2_CHANNEL_PMARSVDIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_7" }, "GTX_CHANNEL_1.GTXE2_IMUX4_8->GTXE2_CHANNEL_TXOUTCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_8" }, "GTX_CHANNEL_1.GTXE2_IMUX4_9->GTXE2_CHANNEL_PMARSVDIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_9" }, "GTX_CHANNEL_1.GTXE2_IMUX5_1->GTXE2_CHANNEL_TXQPIBIASEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPIBIASEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_1" }, "GTX_CHANNEL_1.GTXE2_IMUX5_10->GTXE2_CHANNEL_RXOUTCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_10" }, "GTX_CHANNEL_1.GTXE2_IMUX5_3->GTXE2_CHANNEL_TXMAINCURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_3" }, "GTX_CHANNEL_1.GTXE2_IMUX5_4->GTXE2_CHANNEL_TXMAINCURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_4" }, "GTX_CHANNEL_1.GTXE2_IMUX5_5->GTXE2_CHANNEL_TXSEQUENCE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_5" }, "GTX_CHANNEL_1.GTXE2_IMUX5_6->GTXE2_CHANNEL_TXSEQUENCE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_6" }, "GTX_CHANNEL_1.GTXE2_IMUX5_7->GTXE2_CHANNEL_PMARSVDIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_7" }, "GTX_CHANNEL_1.GTXE2_IMUX5_8->GTXE2_CHANNEL_TXOUTCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_8" }, "GTX_CHANNEL_1.GTXE2_IMUX5_9->GTXE2_CHANNEL_PMARSVDIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_9" }, "GTX_CHANNEL_1.GTXE2_IMUX6_4->GTXE2_CHANNEL_TXPOSTCURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_4" }, "GTX_CHANNEL_1.GTXE2_IMUX6_5->GTXE2_CHANNEL_TXDIFFCTRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_5" }, "GTX_CHANNEL_1.GTXE2_IMUX6_6->GTXE2_CHANNEL_TXPRECURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_6" }, "GTX_CHANNEL_1.GTXE2_IMUX6_8->GTXE2_CHANNEL_TXPRBSSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_8" }, "GTX_CHANNEL_1.GTXE2_IMUX7_0->GTXE2_CHANNEL_TXPISOPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPISOPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_0" }, "GTX_CHANNEL_1.GTXE2_IMUX7_3->GTXE2_CHANNEL_TXPOSTCURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_3" }, "GTX_CHANNEL_1.GTXE2_IMUX7_4->GTXE2_CHANNEL_TXPOSTCURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_4" }, "GTX_CHANNEL_1.GTXE2_IMUX7_5->GTXE2_CHANNEL_TXDIFFCTRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_5" }, "GTX_CHANNEL_1.GTXE2_IMUX7_6->GTXE2_CHANNEL_TXPRECURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_6" }, "GTX_CHANNEL_1.GTXE2_IMUX7_7->GTXE2_CHANNEL_TXPRECURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_7" }, "GTX_CHANNEL_1.GTXE2_IMUX7_8->GTXE2_CHANNEL_TXPRBSSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_8" }, "GTX_CHANNEL_1.GTXE2_IMUX8_0->GTXE2_CHANNEL_TXCHARDISPVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_0" }, "GTX_CHANNEL_1.GTXE2_IMUX8_1->GTXE2_CHANNEL_TX8B10BBYPASS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_1" }, "GTX_CHANNEL_1.GTXE2_IMUX8_2->GTXE2_CHANNEL_TXCHARDISPVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_2" }, "GTX_CHANNEL_1.GTXE2_IMUX8_3->GTXE2_CHANNEL_TX8B10BBYPASS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_3" }, "GTX_CHANNEL_1.GTXE2_IMUX8_4->GTXE2_CHANNEL_TXCHARDISPVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_4" }, "GTX_CHANNEL_1.GTXE2_IMUX8_5->GTXE2_CHANNEL_TX8B10BBYPASS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_5" }, "GTX_CHANNEL_1.GTXE2_IMUX8_6->GTXE2_CHANNEL_TXCHARDISPVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_6" }, "GTX_CHANNEL_1.GTXE2_IMUX8_7->GTXE2_CHANNEL_TX8B10BBYPASS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_7" }, "GTX_CHANNEL_1.GTXE2_IMUX8_8->GTXE2_CHANNEL_RXDDIEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDDIEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_8" }, "GTX_CHANNEL_1.GTXE2_IMUX9_1->GTXE2_CHANNEL_RXPHDLYPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHDLYPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_1" }, "GTX_CHANNEL_1.GTXE2_IMUX9_10->GTXE2_CHANNEL_PCSRSVDIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_10" }, "GTX_CHANNEL_1.GTXE2_IMUX9_2->GTXE2_CHANNEL_TXHEADER2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_2" }, "GTX_CHANNEL_1.GTXE2_IMUX9_3->GTXE2_CHANNEL_PCSRSVDIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_3" }, "GTX_CHANNEL_1.GTXE2_IMUX9_4->GTXE2_CHANNEL_PCSRSVDIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_4" }, "GTX_CHANNEL_1.GTXE2_IMUX9_5->GTXE2_CHANNEL_PCSRSVDIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_5" }, "GTX_CHANNEL_1.GTXE2_IMUX9_6->GTXE2_CHANNEL_PCSRSVDIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_6" }, "GTX_CHANNEL_1.GTXE2_IMUX9_7->GTXE2_CHANNEL_PCSRSVDIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_7" }, "GTX_CHANNEL_1.GTXE2_IMUX9_8->GTXE2_CHANNEL_PCSRSVDIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_8" }, "GTX_CHANNEL_1.GTXE2_IMUX9_9->GTXE2_CHANNEL_PCSRSVDIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_9" } }, @@ -4402,690 +11310,6846 @@ "name": "X0Y0", "prefix": "GTXE2_CHANNEL", "site_pins": { - "CFGRESET": "GTXE2_CHANNEL_CFGRESET", - "CLKRSVD0": "GTXE2_CHANNEL_CLKRSVD0", - "CLKRSVD1": "GTXE2_CHANNEL_CLKRSVD1", - "CLKRSVD2": "GTXE2_CHANNEL_CLKRSVD2", - "CLKRSVD3": "GTXE2_CHANNEL_CLKRSVD3", - "CPLLFBCLKLOST": "GTXE2_CHANNEL_CPLLFBCLKLOST", - "CPLLLOCK": "GTXE2_CHANNEL_CPLLLOCK", - "CPLLLOCKDETCLK": "GTXE2_CHANNEL_CPLLLOCKDETCLK", - "CPLLLOCKEN": "GTXE2_CHANNEL_CPLLLOCKEN", - "CPLLPD": "GTXE2_CHANNEL_CPLLPD", - "CPLLREFCLKLOST": "GTXE2_CHANNEL_CPLLREFCLKLOST", - "CPLLREFCLKSEL0": "GTXE2_CHANNEL_CPLLREFCLKSEL0", - "CPLLREFCLKSEL1": "GTXE2_CHANNEL_CPLLREFCLKSEL1", - "CPLLREFCLKSEL2": "GTXE2_CHANNEL_CPLLREFCLKSEL2", - "CPLLRESET": "GTXE2_CHANNEL_CPLLRESET", - "DMONITOROUT0": "GTXE2_CHANNEL_DMONITOROUT0", - "DMONITOROUT1": "GTXE2_CHANNEL_DMONITOROUT1", - "DMONITOROUT2": "GTXE2_CHANNEL_DMONITOROUT2", - "DMONITOROUT3": "GTXE2_CHANNEL_DMONITOROUT3", - "DMONITOROUT4": "GTXE2_CHANNEL_DMONITOROUT4", - "DMONITOROUT5": "GTXE2_CHANNEL_DMONITOROUT5", - "DMONITOROUT6": "GTXE2_CHANNEL_DMONITOROUT6", - "DMONITOROUT7": "GTXE2_CHANNEL_DMONITOROUT7", - "DRPADDR0": "GTXE2_CHANNEL_DRPADDR0", - "DRPADDR1": "GTXE2_CHANNEL_DRPADDR1", - "DRPADDR2": "GTXE2_CHANNEL_DRPADDR2", - "DRPADDR3": "GTXE2_CHANNEL_DRPADDR3", - "DRPADDR4": "GTXE2_CHANNEL_DRPADDR4", - "DRPADDR5": "GTXE2_CHANNEL_DRPADDR5", - "DRPADDR6": "GTXE2_CHANNEL_DRPADDR6", - "DRPADDR7": "GTXE2_CHANNEL_DRPADDR7", - "DRPADDR8": "GTXE2_CHANNEL_DRPADDR8", - "DRPCLK": "GTXE2_CHANNEL_DRPCLK", - "DRPDI0": "GTXE2_CHANNEL_DRPDI0", - "DRPDI1": "GTXE2_CHANNEL_DRPDI1", - "DRPDI10": "GTXE2_CHANNEL_DRPDI10", - "DRPDI11": "GTXE2_CHANNEL_DRPDI11", - "DRPDI12": "GTXE2_CHANNEL_DRPDI12", - "DRPDI13": "GTXE2_CHANNEL_DRPDI13", - "DRPDI14": "GTXE2_CHANNEL_DRPDI14", - "DRPDI15": "GTXE2_CHANNEL_DRPDI15", - "DRPDI2": "GTXE2_CHANNEL_DRPDI2", - "DRPDI3": "GTXE2_CHANNEL_DRPDI3", - "DRPDI4": "GTXE2_CHANNEL_DRPDI4", - "DRPDI5": "GTXE2_CHANNEL_DRPDI5", - "DRPDI6": "GTXE2_CHANNEL_DRPDI6", - "DRPDI7": "GTXE2_CHANNEL_DRPDI7", - "DRPDI8": "GTXE2_CHANNEL_DRPDI8", - "DRPDI9": "GTXE2_CHANNEL_DRPDI9", - "DRPDO0": "GTXE2_CHANNEL_DRPDO0", - "DRPDO1": "GTXE2_CHANNEL_DRPDO1", - "DRPDO10": "GTXE2_CHANNEL_DRPDO10", - "DRPDO11": "GTXE2_CHANNEL_DRPDO11", - "DRPDO12": "GTXE2_CHANNEL_DRPDO12", - "DRPDO13": "GTXE2_CHANNEL_DRPDO13", - "DRPDO14": "GTXE2_CHANNEL_DRPDO14", - "DRPDO15": "GTXE2_CHANNEL_DRPDO15", - "DRPDO2": "GTXE2_CHANNEL_DRPDO2", - "DRPDO3": "GTXE2_CHANNEL_DRPDO3", - "DRPDO4": "GTXE2_CHANNEL_DRPDO4", - "DRPDO5": "GTXE2_CHANNEL_DRPDO5", - "DRPDO6": "GTXE2_CHANNEL_DRPDO6", - "DRPDO7": "GTXE2_CHANNEL_DRPDO7", - "DRPDO8": "GTXE2_CHANNEL_DRPDO8", - "DRPDO9": "GTXE2_CHANNEL_DRPDO9", - "DRPEN": "GTXE2_CHANNEL_DRPEN", - "DRPRDY": "GTXE2_CHANNEL_DRPRDY", - "DRPWE": "GTXE2_CHANNEL_DRPWE", - "EDTBYPASS": "GTXE2_CHANNEL_EDTBYPASS", - "EDTCLOCK": "GTXE2_CHANNEL_EDTCLOCK", - "EDTCONFIGURATION": "GTXE2_CHANNEL_EDTCONFIGURATION", - "EDTSINGLEBYPASSCHAIN": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", - "EDTUPDATE": "GTXE2_CHANNEL_EDTUPDATE", - "EYESCANDATAERROR": "GTXE2_CHANNEL_EYESCANDATAERROR", - "EYESCANMODE": "GTXE2_CHANNEL_EYESCANMODE", - "EYESCANRESET": "GTXE2_CHANNEL_EYESCANRESET", - "EYESCANTRIGGER": "GTXE2_CHANNEL_EYESCANTRIGGER", - "GTGREFCLK": "GTXE2_CHANNEL_GTGREFCLK", - "GTNORTHREFCLK0": "GTXE2_CHANNEL_GTNORTHREFCLK0", - "GTNORTHREFCLK1": "GTXE2_CHANNEL_GTNORTHREFCLK1", - "GTREFCLK0": "GTXE2_CHANNEL_GTREFCLK0", - "GTREFCLK1": "GTXE2_CHANNEL_GTREFCLK1", - "GTREFCLKMONITOR": "GTXE2_CHANNEL_GTREFCLKMONITOR", - "GTRESETSEL": "GTXE2_CHANNEL_GTRESETSEL", - "GTRSVD0": "GTXE2_CHANNEL_GTRSVD0", - "GTRSVD1": "GTXE2_CHANNEL_GTRSVD1", - "GTRSVD10": "GTXE2_CHANNEL_GTRSVD10", - "GTRSVD11": "GTXE2_CHANNEL_GTRSVD11", - "GTRSVD12": "GTXE2_CHANNEL_GTRSVD12", - "GTRSVD13": "GTXE2_CHANNEL_GTRSVD13", - "GTRSVD14": "GTXE2_CHANNEL_GTRSVD14", - "GTRSVD15": "GTXE2_CHANNEL_GTRSVD15", - "GTRSVD2": "GTXE2_CHANNEL_GTRSVD2", - "GTRSVD3": "GTXE2_CHANNEL_GTRSVD3", - "GTRSVD4": "GTXE2_CHANNEL_GTRSVD4", - "GTRSVD5": "GTXE2_CHANNEL_GTRSVD5", - "GTRSVD6": "GTXE2_CHANNEL_GTRSVD6", - "GTRSVD7": "GTXE2_CHANNEL_GTRSVD7", - "GTRSVD8": "GTXE2_CHANNEL_GTRSVD8", - "GTRSVD9": "GTXE2_CHANNEL_GTRSVD9", - "GTRXRESET": "GTXE2_CHANNEL_GTRXRESET", - "GTSOUTHREFCLK0": "GTXE2_CHANNEL_GTSOUTHREFCLK0", - "GTSOUTHREFCLK1": "GTXE2_CHANNEL_GTSOUTHREFCLK1", - "GTTXRESET": "GTXE2_CHANNEL_GTTXRESET", - "GTXRXN": "GTXE2_CHANNEL_RXN", - "GTXRXP": "GTXE2_CHANNEL_RXP", - "GTXTXN": "GTXE2_CHANNEL_TXN", - "GTXTXP": "GTXE2_CHANNEL_TXP", - "LOOPBACK0": "GTXE2_CHANNEL_LOOPBACK0", - "LOOPBACK1": "GTXE2_CHANNEL_LOOPBACK1", - "LOOPBACK2": "GTXE2_CHANNEL_LOOPBACK2", - "PCSRSVDIN0": "GTXE2_CHANNEL_PCSRSVDIN0", - "PCSRSVDIN1": "GTXE2_CHANNEL_PCSRSVDIN1", - "PCSRSVDIN10": "GTXE2_CHANNEL_PCSRSVDIN10", - "PCSRSVDIN11": "GTXE2_CHANNEL_PCSRSVDIN11", - "PCSRSVDIN12": "GTXE2_CHANNEL_PCSRSVDIN12", - "PCSRSVDIN13": "GTXE2_CHANNEL_PCSRSVDIN13", - "PCSRSVDIN14": "GTXE2_CHANNEL_PCSRSVDIN14", - "PCSRSVDIN15": "GTXE2_CHANNEL_PCSRSVDIN15", - "PCSRSVDIN2": "GTXE2_CHANNEL_PCSRSVDIN2", - "PCSRSVDIN20": "GTXE2_CHANNEL_PCSRSVDIN20", - "PCSRSVDIN21": "GTXE2_CHANNEL_PCSRSVDIN21", - "PCSRSVDIN22": "GTXE2_CHANNEL_PCSRSVDIN22", - "PCSRSVDIN23": "GTXE2_CHANNEL_PCSRSVDIN23", - "PCSRSVDIN24": "GTXE2_CHANNEL_PCSRSVDIN24", - "PCSRSVDIN3": "GTXE2_CHANNEL_PCSRSVDIN3", - "PCSRSVDIN4": "GTXE2_CHANNEL_PCSRSVDIN4", - "PCSRSVDIN5": "GTXE2_CHANNEL_PCSRSVDIN5", - "PCSRSVDIN6": "GTXE2_CHANNEL_PCSRSVDIN6", - "PCSRSVDIN7": "GTXE2_CHANNEL_PCSRSVDIN7", - "PCSRSVDIN8": "GTXE2_CHANNEL_PCSRSVDIN8", - "PCSRSVDIN9": "GTXE2_CHANNEL_PCSRSVDIN9", - "PCSRSVDOUT0": "GTXE2_CHANNEL_PCSRSVDOUT0", - "PCSRSVDOUT1": "GTXE2_CHANNEL_PCSRSVDOUT1", - "PCSRSVDOUT10": "GTXE2_CHANNEL_PCSRSVDOUT10", - "PCSRSVDOUT11": "GTXE2_CHANNEL_PCSRSVDOUT11", - "PCSRSVDOUT12": "GTXE2_CHANNEL_PCSRSVDOUT12", - "PCSRSVDOUT13": "GTXE2_CHANNEL_PCSRSVDOUT13", - "PCSRSVDOUT14": "GTXE2_CHANNEL_PCSRSVDOUT14", - "PCSRSVDOUT15": "GTXE2_CHANNEL_PCSRSVDOUT15", - "PCSRSVDOUT2": "GTXE2_CHANNEL_PCSRSVDOUT2", - "PCSRSVDOUT3": "GTXE2_CHANNEL_PCSRSVDOUT3", - "PCSRSVDOUT4": "GTXE2_CHANNEL_PCSRSVDOUT4", - "PCSRSVDOUT5": "GTXE2_CHANNEL_PCSRSVDOUT5", - "PCSRSVDOUT6": "GTXE2_CHANNEL_PCSRSVDOUT6", - "PCSRSVDOUT7": "GTXE2_CHANNEL_PCSRSVDOUT7", - "PCSRSVDOUT8": "GTXE2_CHANNEL_PCSRSVDOUT8", - "PCSRSVDOUT9": "GTXE2_CHANNEL_PCSRSVDOUT9", - "PHYSTATUS": "GTXE2_CHANNEL_PHYSTATUS", - "PMARSVDIN0": "GTXE2_CHANNEL_PMARSVDIN0", - "PMARSVDIN1": "GTXE2_CHANNEL_PMARSVDIN1", - "PMARSVDIN2": "GTXE2_CHANNEL_PMARSVDIN2", - "PMARSVDIN20": "GTXE2_CHANNEL_PMARSVDIN20", - "PMARSVDIN21": "GTXE2_CHANNEL_PMARSVDIN21", - "PMARSVDIN22": "GTXE2_CHANNEL_PMARSVDIN22", - "PMARSVDIN23": "GTXE2_CHANNEL_PMARSVDIN23", - "PMARSVDIN24": "GTXE2_CHANNEL_PMARSVDIN24", - "PMARSVDIN3": "GTXE2_CHANNEL_PMARSVDIN3", - "PMARSVDIN4": "GTXE2_CHANNEL_PMARSVDIN4", - "PMASCANCLK0": "GTXE2_CHANNEL_PMASCANCLK0", - "PMASCANCLK1": "GTXE2_CHANNEL_PMASCANCLK1", - "PMASCANCLK2": "GTXE2_CHANNEL_PMASCANCLK2", - "PMASCANCLK3": "GTXE2_CHANNEL_PMASCANCLK3", - "PMASCANCLK4": "GTXE2_CHANNEL_PMASCANCLK4", - "PMASCANENB": "GTXE2_CHANNEL_PMASCANENB", - "PMASCANIN0": "GTXE2_CHANNEL_PMASCANIN0", - "PMASCANIN1": "GTXE2_CHANNEL_PMASCANIN1", - "PMASCANIN2": "GTXE2_CHANNEL_PMASCANIN2", - "PMASCANIN3": "GTXE2_CHANNEL_PMASCANIN3", - "PMASCANIN4": "GTXE2_CHANNEL_PMASCANIN4", - "PMASCANMODEB": "GTXE2_CHANNEL_PMASCANMODEB", - "PMASCANOUT0": "GTXE2_CHANNEL_PMASCANOUT0", - "PMASCANOUT1": "GTXE2_CHANNEL_PMASCANOUT1", - "PMASCANOUT2": "GTXE2_CHANNEL_PMASCANOUT2", - "PMASCANOUT3": "GTXE2_CHANNEL_PMASCANOUT3", - "PMASCANOUT4": "GTXE2_CHANNEL_PMASCANOUT4", - "PMASCANRSTEN": "GTXE2_CHANNEL_PMASCANRSTEN", - "QPLLCLK": "GTXE2_CHANNEL_GTQPLLCLK", - "QPLLREFCLK": "GTXE2_CHANNEL_GTQPLLREFCLK", - "RESETOVRD": "GTXE2_CHANNEL_RESETOVRD", - "RX8B10BEN": "GTXE2_CHANNEL_RX8B10BEN", - "RXBUFRESET": "GTXE2_CHANNEL_RXBUFRESET", - "RXBUFSTATUS0": "GTXE2_CHANNEL_RXBUFSTATUS0", - "RXBUFSTATUS1": "GTXE2_CHANNEL_RXBUFSTATUS1", - "RXBUFSTATUS2": "GTXE2_CHANNEL_RXBUFSTATUS2", - "RXBYTEISALIGNED": "GTXE2_CHANNEL_RXBYTEISALIGNED", - "RXBYTEREALIGN": "GTXE2_CHANNEL_RXBYTEREALIGN", - "RXCDRFREQRESET": "GTXE2_CHANNEL_RXCDRFREQRESET", - "RXCDRHOLD": "GTXE2_CHANNEL_RXCDRHOLD", - "RXCDRLOCK": "GTXE2_CHANNEL_RXCDRLOCK", - "RXCDROVRDEN": "GTXE2_CHANNEL_RXCDROVRDEN", - "RXCDRRESET": "GTXE2_CHANNEL_RXCDRRESET", - "RXCDRRESETRSV": "GTXE2_CHANNEL_RXCDRRESETRSV", - "RXCHANBONDSEQ": "GTXE2_CHANNEL_RXCHANBONDSEQ", - "RXCHANISALIGNED": "GTXE2_CHANNEL_RXCHANISALIGNED", - "RXCHANREALIGN": "GTXE2_CHANNEL_RXCHANREALIGN", - "RXCHARISCOMMA0": "GTXE2_CHANNEL_RXCHARISCOMMA0", - "RXCHARISCOMMA1": "GTXE2_CHANNEL_RXCHARISCOMMA1", - "RXCHARISCOMMA2": "GTXE2_CHANNEL_RXCHARISCOMMA2", - "RXCHARISCOMMA3": "GTXE2_CHANNEL_RXCHARISCOMMA3", - "RXCHARISCOMMA4": "GTXE2_CHANNEL_RXCHARISCOMMA4", - "RXCHARISCOMMA5": "GTXE2_CHANNEL_RXCHARISCOMMA5", - "RXCHARISCOMMA6": "GTXE2_CHANNEL_RXCHARISCOMMA6", - "RXCHARISCOMMA7": "GTXE2_CHANNEL_RXCHARISCOMMA7", - "RXCHARISK0": "GTXE2_CHANNEL_RXCHARISK0", - "RXCHARISK1": "GTXE2_CHANNEL_RXCHARISK1", - "RXCHARISK2": "GTXE2_CHANNEL_RXCHARISK2", - "RXCHARISK3": "GTXE2_CHANNEL_RXCHARISK3", - "RXCHARISK4": "GTXE2_CHANNEL_RXCHARISK4", - "RXCHARISK5": "GTXE2_CHANNEL_RXCHARISK5", - "RXCHARISK6": "GTXE2_CHANNEL_RXCHARISK6", - "RXCHARISK7": "GTXE2_CHANNEL_RXCHARISK7", - "RXCHBONDEN": "GTXE2_CHANNEL_RXCHBONDEN", - "RXCHBONDI0": "GTXE2_CHANNEL_RXCHBONDI0", - "RXCHBONDI1": "GTXE2_CHANNEL_RXCHBONDI1", - "RXCHBONDI2": "GTXE2_CHANNEL_RXCHBONDI2", - "RXCHBONDI3": "GTXE2_CHANNEL_RXCHBONDI3", - "RXCHBONDI4": "GTXE2_CHANNEL_RXCHBONDI4", - "RXCHBONDLEVEL0": "GTXE2_CHANNEL_RXCHBONDLEVEL0", - "RXCHBONDLEVEL1": "GTXE2_CHANNEL_RXCHBONDLEVEL1", - "RXCHBONDLEVEL2": "GTXE2_CHANNEL_RXCHBONDLEVEL2", - "RXCHBONDMASTER": "GTXE2_CHANNEL_RXCHBONDMASTER", - "RXCHBONDO0": "GTXE2_CHANNEL_RXCHBONDO0", - "RXCHBONDO1": "GTXE2_CHANNEL_RXCHBONDO1", - "RXCHBONDO2": "GTXE2_CHANNEL_RXCHBONDO2", - "RXCHBONDO3": "GTXE2_CHANNEL_RXCHBONDO3", - "RXCHBONDO4": "GTXE2_CHANNEL_RXCHBONDO4", - "RXCHBONDSLAVE": "GTXE2_CHANNEL_RXCHBONDSLAVE", - "RXCLKCORCNT0": "GTXE2_CHANNEL_RXCLKCORCNT0", - "RXCLKCORCNT1": "GTXE2_CHANNEL_RXCLKCORCNT1", - "RXCOMINITDET": "GTXE2_CHANNEL_RXCOMINITDET", - "RXCOMMADET": "GTXE2_CHANNEL_RXCOMMADET", - "RXCOMMADETEN": "GTXE2_CHANNEL_RXCOMMADETEN", - "RXCOMSASDET": "GTXE2_CHANNEL_RXCOMSASDET", - "RXCOMWAKEDET": "GTXE2_CHANNEL_RXCOMWAKEDET", - "RXDATA0": "GTXE2_CHANNEL_RXDATA0", - "RXDATA1": "GTXE2_CHANNEL_RXDATA1", - "RXDATA10": "GTXE2_CHANNEL_RXDATA10", - "RXDATA11": "GTXE2_CHANNEL_RXDATA11", - "RXDATA12": "GTXE2_CHANNEL_RXDATA12", - "RXDATA13": "GTXE2_CHANNEL_RXDATA13", - "RXDATA14": "GTXE2_CHANNEL_RXDATA14", - "RXDATA15": "GTXE2_CHANNEL_RXDATA15", - "RXDATA16": "GTXE2_CHANNEL_RXDATA16", - "RXDATA17": "GTXE2_CHANNEL_RXDATA17", - "RXDATA18": "GTXE2_CHANNEL_RXDATA18", - "RXDATA19": "GTXE2_CHANNEL_RXDATA19", - "RXDATA2": "GTXE2_CHANNEL_RXDATA2", - "RXDATA20": "GTXE2_CHANNEL_RXDATA20", - "RXDATA21": "GTXE2_CHANNEL_RXDATA21", - "RXDATA22": "GTXE2_CHANNEL_RXDATA22", - "RXDATA23": "GTXE2_CHANNEL_RXDATA23", - "RXDATA24": "GTXE2_CHANNEL_RXDATA24", - "RXDATA25": "GTXE2_CHANNEL_RXDATA25", - "RXDATA26": "GTXE2_CHANNEL_RXDATA26", - "RXDATA27": "GTXE2_CHANNEL_RXDATA27", - "RXDATA28": "GTXE2_CHANNEL_RXDATA28", - "RXDATA29": "GTXE2_CHANNEL_RXDATA29", - "RXDATA3": "GTXE2_CHANNEL_RXDATA3", - "RXDATA30": "GTXE2_CHANNEL_RXDATA30", - "RXDATA31": "GTXE2_CHANNEL_RXDATA31", - "RXDATA32": "GTXE2_CHANNEL_RXDATA32", - "RXDATA33": "GTXE2_CHANNEL_RXDATA33", - "RXDATA34": "GTXE2_CHANNEL_RXDATA34", - "RXDATA35": "GTXE2_CHANNEL_RXDATA35", - "RXDATA36": "GTXE2_CHANNEL_RXDATA36", - "RXDATA37": "GTXE2_CHANNEL_RXDATA37", - "RXDATA38": "GTXE2_CHANNEL_RXDATA38", - "RXDATA39": "GTXE2_CHANNEL_RXDATA39", - "RXDATA4": "GTXE2_CHANNEL_RXDATA4", - "RXDATA40": "GTXE2_CHANNEL_RXDATA40", - "RXDATA41": "GTXE2_CHANNEL_RXDATA41", - "RXDATA42": "GTXE2_CHANNEL_RXDATA42", - "RXDATA43": "GTXE2_CHANNEL_RXDATA43", - "RXDATA44": "GTXE2_CHANNEL_RXDATA44", - "RXDATA45": "GTXE2_CHANNEL_RXDATA45", - "RXDATA46": "GTXE2_CHANNEL_RXDATA46", - "RXDATA47": "GTXE2_CHANNEL_RXDATA47", - "RXDATA48": "GTXE2_CHANNEL_RXDATA48", - "RXDATA49": "GTXE2_CHANNEL_RXDATA49", - "RXDATA5": "GTXE2_CHANNEL_RXDATA5", - "RXDATA50": "GTXE2_CHANNEL_RXDATA50", - "RXDATA51": "GTXE2_CHANNEL_RXDATA51", - "RXDATA52": "GTXE2_CHANNEL_RXDATA52", - "RXDATA53": "GTXE2_CHANNEL_RXDATA53", - "RXDATA54": "GTXE2_CHANNEL_RXDATA54", - "RXDATA55": "GTXE2_CHANNEL_RXDATA55", - "RXDATA56": "GTXE2_CHANNEL_RXDATA56", - "RXDATA57": "GTXE2_CHANNEL_RXDATA57", - "RXDATA58": "GTXE2_CHANNEL_RXDATA58", - "RXDATA59": "GTXE2_CHANNEL_RXDATA59", - "RXDATA6": "GTXE2_CHANNEL_RXDATA6", - "RXDATA60": "GTXE2_CHANNEL_RXDATA60", - "RXDATA61": "GTXE2_CHANNEL_RXDATA61", - "RXDATA62": "GTXE2_CHANNEL_RXDATA62", - "RXDATA63": "GTXE2_CHANNEL_RXDATA63", - "RXDATA7": "GTXE2_CHANNEL_RXDATA7", - "RXDATA8": "GTXE2_CHANNEL_RXDATA8", - "RXDATA9": "GTXE2_CHANNEL_RXDATA9", - "RXDATAVALID": "GTXE2_CHANNEL_RXDATAVALID", - "RXDDIEN": "GTXE2_CHANNEL_RXDDIEN", - "RXDEBUGPULSE": "GTXE2_CHANNEL_RXDEBUGPULSE", - "RXDFEAGCHOLD": "GTXE2_CHANNEL_RXDFEAGCHOLD", - "RXDFEAGCOVRDEN": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", - "RXDFECM1EN": "GTXE2_CHANNEL_RXDFECM1EN", - "RXDFELFHOLD": "GTXE2_CHANNEL_RXDFELFHOLD", - "RXDFELFOVRDEN": "GTXE2_CHANNEL_RXDFELFOVRDEN", - "RXDFELPMRESET": "GTXE2_CHANNEL_RXDFELPMRESET", - "RXDFETAP2HOLD": "GTXE2_CHANNEL_RXDFETAP2HOLD", - "RXDFETAP2OVRDEN": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", - "RXDFETAP3HOLD": "GTXE2_CHANNEL_RXDFETAP3HOLD", - "RXDFETAP3OVRDEN": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", - "RXDFETAP4HOLD": "GTXE2_CHANNEL_RXDFETAP4HOLD", - "RXDFETAP4OVRDEN": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", - "RXDFETAP5HOLD": "GTXE2_CHANNEL_RXDFETAP5HOLD", - "RXDFETAP5OVRDEN": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", - "RXDFEUTHOLD": "GTXE2_CHANNEL_RXDFEUTHOLD", - "RXDFEUTOVRDEN": "GTXE2_CHANNEL_RXDFEUTOVRDEN", - "RXDFEVPHOLD": "GTXE2_CHANNEL_RXDFEVPHOLD", - "RXDFEVPOVRDEN": "GTXE2_CHANNEL_RXDFEVPOVRDEN", - "RXDFEVSEN": "GTXE2_CHANNEL_RXDFEVSEN", - "RXDFEXYDEN": "GTXE2_CHANNEL_RXDFEXYDEN", - "RXDFEXYDHOLD": "GTXE2_CHANNEL_RXDFEXYDHOLD", - "RXDFEXYDOVRDEN": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", - "RXDISPERR0": "GTXE2_CHANNEL_RXDISPERR0", - "RXDISPERR1": "GTXE2_CHANNEL_RXDISPERR1", - "RXDISPERR2": "GTXE2_CHANNEL_RXDISPERR2", - "RXDISPERR3": "GTXE2_CHANNEL_RXDISPERR3", - "RXDISPERR4": "GTXE2_CHANNEL_RXDISPERR4", - "RXDISPERR5": "GTXE2_CHANNEL_RXDISPERR5", - "RXDISPERR6": "GTXE2_CHANNEL_RXDISPERR6", - "RXDISPERR7": "GTXE2_CHANNEL_RXDISPERR7", - "RXDLYBYPASS": "GTXE2_CHANNEL_RXDLYBYPASS", - "RXDLYEN": "GTXE2_CHANNEL_RXDLYEN", - "RXDLYOVRDEN": "GTXE2_CHANNEL_RXDLYOVRDEN", - "RXDLYSRESET": "GTXE2_CHANNEL_RXDLYSRESET", - "RXDLYSRESETDONE": "GTXE2_CHANNEL_RXDLYSRESETDONE", - "RXDLYTESTENB": "GTXE2_CHANNEL_RXDLYTESTENB", - "RXELECIDLE": "GTXE2_CHANNEL_RXELECIDLE", - "RXELECIDLEMODE0": "GTXE2_CHANNEL_RXELECIDLEMODE0", - "RXELECIDLEMODE1": "GTXE2_CHANNEL_RXELECIDLEMODE1", - "RXGEARBOXSLIP": "GTXE2_CHANNEL_RXGEARBOXSLIP", - "RXHEADER0": "GTXE2_CHANNEL_RXHEADER0", - "RXHEADER1": "GTXE2_CHANNEL_RXHEADER1", - "RXHEADER2": "GTXE2_CHANNEL_RXHEADER2", - "RXHEADERVALID": "GTXE2_CHANNEL_RXHEADERVALID", - "RXLPMEN": "GTXE2_CHANNEL_RXLPMEN", - "RXLPMHFHOLD": "GTXE2_CHANNEL_RXLPMHFHOLD", - "RXLPMHFOVRDEN": "GTXE2_CHANNEL_RXLPMHFOVRDEN", - "RXLPMLFHOLD": "GTXE2_CHANNEL_RXLPMLFHOLD", - "RXLPMLFKLOVRDEN": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", - "RXMCOMMAALIGNEN": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", - "RXMONITOROUT0": "GTXE2_CHANNEL_RXMONITOROUT0", - "RXMONITOROUT1": "GTXE2_CHANNEL_RXMONITOROUT1", - "RXMONITOROUT2": "GTXE2_CHANNEL_RXMONITOROUT2", - "RXMONITOROUT3": "GTXE2_CHANNEL_RXMONITOROUT3", - "RXMONITOROUT4": "GTXE2_CHANNEL_RXMONITOROUT4", - "RXMONITOROUT5": "GTXE2_CHANNEL_RXMONITOROUT5", - "RXMONITOROUT6": "GTXE2_CHANNEL_RXMONITOROUT6", - "RXMONITORSEL0": "GTXE2_CHANNEL_RXMONITORSEL0", - "RXMONITORSEL1": "GTXE2_CHANNEL_RXMONITORSEL1", - "RXNOTINTABLE0": "GTXE2_CHANNEL_RXNOTINTABLE0", - "RXNOTINTABLE1": "GTXE2_CHANNEL_RXNOTINTABLE1", - "RXNOTINTABLE2": "GTXE2_CHANNEL_RXNOTINTABLE2", - "RXNOTINTABLE3": "GTXE2_CHANNEL_RXNOTINTABLE3", - "RXNOTINTABLE4": "GTXE2_CHANNEL_RXNOTINTABLE4", - "RXNOTINTABLE5": "GTXE2_CHANNEL_RXNOTINTABLE5", - "RXNOTINTABLE6": "GTXE2_CHANNEL_RXNOTINTABLE6", - "RXNOTINTABLE7": "GTXE2_CHANNEL_RXNOTINTABLE7", - "RXOOBRESET": "GTXE2_CHANNEL_RXOOBRESET", - "RXOSHOLD": "GTXE2_CHANNEL_RXOSHOLD", - "RXOSOVRDEN": "GTXE2_CHANNEL_RXOSOVRDEN", - "RXOUTCLK": "GTXE2_CHANNEL_GTRXOUTCLK_1", - "RXOUTCLKFABRIC": "GTXE2_CHANNEL_RXOUTCLKFABRIC", - "RXOUTCLKPCS": "GTXE2_CHANNEL_RXOUTCLKPCS", - "RXOUTCLKSEL0": "GTXE2_CHANNEL_RXOUTCLKSEL0", - "RXOUTCLKSEL1": "GTXE2_CHANNEL_RXOUTCLKSEL1", - "RXOUTCLKSEL2": "GTXE2_CHANNEL_RXOUTCLKSEL2", - "RXPCD1DONE": "GTXE2_CHANNEL_RXPCD1DONE", - "RXPCOMMAALIGNEN": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", - "RXPCSRESET": "GTXE2_CHANNEL_RXPCSRESET", - "RXPD0": "GTXE2_CHANNEL_RXPD0", - "RXPD1": "GTXE2_CHANNEL_RXPD1", - "RXPHALIGN": "GTXE2_CHANNEL_RXPHALIGN", - "RXPHALIGNDONE": "GTXE2_CHANNEL_RXPHALIGNDONE", - "RXPHALIGNEN": "GTXE2_CHANNEL_RXPHALIGNEN", - "RXPHDLYPD": "GTXE2_CHANNEL_RXPHDLYPD", - "RXPHDLYRESET": "GTXE2_CHANNEL_RXPHDLYRESET", - "RXPHMONITOR0": "GTXE2_CHANNEL_RXPHMONITOR0", - "RXPHMONITOR1": "GTXE2_CHANNEL_RXPHMONITOR1", - "RXPHMONITOR2": "GTXE2_CHANNEL_RXPHMONITOR2", - "RXPHMONITOR3": "GTXE2_CHANNEL_RXPHMONITOR3", - "RXPHMONITOR4": "GTXE2_CHANNEL_RXPHMONITOR4", - "RXPHOVRDEN": "GTXE2_CHANNEL_RXPHOVRDEN", - "RXPHSLIPMONITOR0": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", - "RXPHSLIPMONITOR1": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", - "RXPHSLIPMONITOR2": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", - "RXPHSLIPMONITOR3": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", - "RXPHSLIPMONITOR4": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", - "RXPMARESET": "GTXE2_CHANNEL_RXPMARESET", - "RXPOLARITY": "GTXE2_CHANNEL_RXPOLARITY", - "RXPRBSCNTRESET": "GTXE2_CHANNEL_RXPRBSCNTRESET", - "RXPRBSERR": "GTXE2_CHANNEL_RXPRBSERR", - "RXPRBSSEL0": "GTXE2_CHANNEL_RXPRBSSEL0", - "RXPRBSSEL1": "GTXE2_CHANNEL_RXPRBSSEL1", - "RXPRBSSEL2": "GTXE2_CHANNEL_RXPRBSSEL2", - "RXQPIEN": "GTXE2_CHANNEL_RXQPIEN", - "RXQPISENN": "GTXE2_CHANNEL_RXQPISENN", - "RXQPISENP": "GTXE2_CHANNEL_RXQPISENP", - "RXRATE0": "GTXE2_CHANNEL_RXRATE0", - "RXRATE1": "GTXE2_CHANNEL_RXRATE1", - "RXRATE2": "GTXE2_CHANNEL_RXRATE2", - "RXRATEDONE": "GTXE2_CHANNEL_RXRATEDONE", - "RXRESETDONE": "GTXE2_CHANNEL_RXRESETDONE", - "RXSLIDE": "GTXE2_CHANNEL_RXSLIDE", - "RXSTARTOFSEQ": "GTXE2_CHANNEL_RXSTARTOFSEQ", - "RXSTATUS0": "GTXE2_CHANNEL_RXSTATUS0", - "RXSTATUS1": "GTXE2_CHANNEL_RXSTATUS1", - "RXSTATUS2": "GTXE2_CHANNEL_RXSTATUS2", - "RXSYSCLKSEL0": "GTXE2_CHANNEL_RXSYSCLKSEL0", - "RXSYSCLKSEL1": "GTXE2_CHANNEL_RXSYSCLKSEL1", - "RXUSERRDY": "GTXE2_CHANNEL_RXUSERRDY", - "RXUSRCLK": "GTXE2_CHANNEL_RXUSRCLK", - "RXUSRCLK2": "GTXE2_CHANNEL_RXUSRCLK2", - "RXVALID": "GTXE2_CHANNEL_RXVALID", - "SCANCLK": "GTXE2_CHANNEL_SCANCLK", - "SCANENB": "GTXE2_CHANNEL_SCANENB", - "SCANIN0": "GTXE2_CHANNEL_SCANIN0", - "SCANIN1": "GTXE2_CHANNEL_SCANIN1", - "SCANIN2": "GTXE2_CHANNEL_SCANIN2", - "SCANIN3": "GTXE2_CHANNEL_SCANIN3", - "SCANIN4": "GTXE2_CHANNEL_SCANIN4", - "SCANMODEB": "GTXE2_CHANNEL_SCANMODEB", - "SCANOUT0": "GTXE2_CHANNEL_SCANOUT0", - "SCANOUT1": "GTXE2_CHANNEL_SCANOUT1", - "SCANOUT2": "GTXE2_CHANNEL_SCANOUT2", - "SCANOUT3": "GTXE2_CHANNEL_SCANOUT3", - "SCANOUT4": "GTXE2_CHANNEL_SCANOUT4", - "SETERRSTATUS": "GTXE2_CHANNEL_SETERRSTATUS", - "TSTCLK0": "GTXE2_CHANNEL_TSTCLK0", - "TSTCLK1": "GTXE2_CHANNEL_TSTCLK1", - "TSTIN0": "GTXE2_CHANNEL_TSTIN0", - "TSTIN1": "GTXE2_CHANNEL_TSTIN1", - "TSTIN10": "GTXE2_CHANNEL_TSTIN10", - "TSTIN11": "GTXE2_CHANNEL_TSTIN11", - "TSTIN12": "GTXE2_CHANNEL_TSTIN12", - "TSTIN13": "GTXE2_CHANNEL_TSTIN13", - "TSTIN14": "GTXE2_CHANNEL_TSTIN14", - "TSTIN15": "GTXE2_CHANNEL_TSTIN15", - "TSTIN16": "GTXE2_CHANNEL_TSTIN16", - "TSTIN17": "GTXE2_CHANNEL_TSTIN17", - "TSTIN18": "GTXE2_CHANNEL_TSTIN18", - "TSTIN19": "GTXE2_CHANNEL_TSTIN19", - "TSTIN2": "GTXE2_CHANNEL_TSTIN2", - "TSTIN3": "GTXE2_CHANNEL_TSTIN3", - "TSTIN4": "GTXE2_CHANNEL_TSTIN4", - "TSTIN5": "GTXE2_CHANNEL_TSTIN5", - "TSTIN6": "GTXE2_CHANNEL_TSTIN6", - "TSTIN7": "GTXE2_CHANNEL_TSTIN7", - "TSTIN8": "GTXE2_CHANNEL_TSTIN8", - "TSTIN9": "GTXE2_CHANNEL_TSTIN9", - "TSTOUT0": "GTXE2_CHANNEL_TSTOUT0", - "TSTOUT1": "GTXE2_CHANNEL_TSTOUT1", - "TSTOUT2": "GTXE2_CHANNEL_TSTOUT2", - "TSTOUT3": "GTXE2_CHANNEL_TSTOUT3", - "TSTOUT4": "GTXE2_CHANNEL_TSTOUT4", - "TSTOUT5": "GTXE2_CHANNEL_TSTOUT5", - "TSTOUT6": "GTXE2_CHANNEL_TSTOUT6", - "TSTOUT7": "GTXE2_CHANNEL_TSTOUT7", - "TSTOUT8": "GTXE2_CHANNEL_TSTOUT8", - "TSTOUT9": "GTXE2_CHANNEL_TSTOUT9", - "TSTPD0": "GTXE2_CHANNEL_TSTPD0", - "TSTPD1": "GTXE2_CHANNEL_TSTPD1", - "TSTPD2": "GTXE2_CHANNEL_TSTPD2", - "TSTPD3": "GTXE2_CHANNEL_TSTPD3", - "TSTPD4": "GTXE2_CHANNEL_TSTPD4", - "TSTPDOVRDB": "GTXE2_CHANNEL_TSTPDOVRDB", - "TX8B10BBYPASS0": "GTXE2_CHANNEL_TX8B10BBYPASS0", - "TX8B10BBYPASS1": "GTXE2_CHANNEL_TX8B10BBYPASS1", - "TX8B10BBYPASS2": "GTXE2_CHANNEL_TX8B10BBYPASS2", - "TX8B10BBYPASS3": "GTXE2_CHANNEL_TX8B10BBYPASS3", - "TX8B10BBYPASS4": "GTXE2_CHANNEL_TX8B10BBYPASS4", - "TX8B10BBYPASS5": "GTXE2_CHANNEL_TX8B10BBYPASS5", - "TX8B10BBYPASS6": "GTXE2_CHANNEL_TX8B10BBYPASS6", - "TX8B10BBYPASS7": "GTXE2_CHANNEL_TX8B10BBYPASS7", - "TX8B10BEN": "GTXE2_CHANNEL_TX8B10BEN", - "TXBUFDIFFCTRL0": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", - "TXBUFDIFFCTRL1": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", - "TXBUFDIFFCTRL2": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", - "TXBUFSTATUS0": "GTXE2_CHANNEL_TXBUFSTATUS0", - "TXBUFSTATUS1": "GTXE2_CHANNEL_TXBUFSTATUS1", - "TXCHARDISPMODE0": "GTXE2_CHANNEL_TXCHARDISPMODE0", - "TXCHARDISPMODE1": "GTXE2_CHANNEL_TXCHARDISPMODE1", - "TXCHARDISPMODE2": "GTXE2_CHANNEL_TXCHARDISPMODE2", - "TXCHARDISPMODE3": "GTXE2_CHANNEL_TXCHARDISPMODE3", - "TXCHARDISPMODE4": "GTXE2_CHANNEL_TXCHARDISPMODE4", - "TXCHARDISPMODE5": "GTXE2_CHANNEL_TXCHARDISPMODE5", - "TXCHARDISPMODE6": "GTXE2_CHANNEL_TXCHARDISPMODE6", - "TXCHARDISPMODE7": "GTXE2_CHANNEL_TXCHARDISPMODE7", - "TXCHARDISPVAL0": "GTXE2_CHANNEL_TXCHARDISPVAL0", - "TXCHARDISPVAL1": "GTXE2_CHANNEL_TXCHARDISPVAL1", - "TXCHARDISPVAL2": "GTXE2_CHANNEL_TXCHARDISPVAL2", - "TXCHARDISPVAL3": "GTXE2_CHANNEL_TXCHARDISPVAL3", - "TXCHARDISPVAL4": "GTXE2_CHANNEL_TXCHARDISPVAL4", - "TXCHARDISPVAL5": "GTXE2_CHANNEL_TXCHARDISPVAL5", - "TXCHARDISPVAL6": "GTXE2_CHANNEL_TXCHARDISPVAL6", - "TXCHARDISPVAL7": "GTXE2_CHANNEL_TXCHARDISPVAL7", - "TXCHARISK0": "GTXE2_CHANNEL_TXCHARISK0", - "TXCHARISK1": "GTXE2_CHANNEL_TXCHARISK1", - "TXCHARISK2": "GTXE2_CHANNEL_TXCHARISK2", - "TXCHARISK3": "GTXE2_CHANNEL_TXCHARISK3", - "TXCHARISK4": "GTXE2_CHANNEL_TXCHARISK4", - "TXCHARISK5": "GTXE2_CHANNEL_TXCHARISK5", - "TXCHARISK6": "GTXE2_CHANNEL_TXCHARISK6", - "TXCHARISK7": "GTXE2_CHANNEL_TXCHARISK7", - "TXCOMFINISH": "GTXE2_CHANNEL_TXCOMFINISH", - "TXCOMINIT": "GTXE2_CHANNEL_TXCOMINIT", - "TXCOMSAS": "GTXE2_CHANNEL_TXCOMSAS", - "TXCOMWAKE": "GTXE2_CHANNEL_TXCOMWAKE", - "TXDATA0": "GTXE2_CHANNEL_TXDATA0", - "TXDATA1": "GTXE2_CHANNEL_TXDATA1", - "TXDATA10": "GTXE2_CHANNEL_TXDATA10", - "TXDATA11": "GTXE2_CHANNEL_TXDATA11", - "TXDATA12": "GTXE2_CHANNEL_TXDATA12", - "TXDATA13": "GTXE2_CHANNEL_TXDATA13", - "TXDATA14": "GTXE2_CHANNEL_TXDATA14", - "TXDATA15": "GTXE2_CHANNEL_TXDATA15", - "TXDATA16": "GTXE2_CHANNEL_TXDATA16", - "TXDATA17": "GTXE2_CHANNEL_TXDATA17", - "TXDATA18": "GTXE2_CHANNEL_TXDATA18", - "TXDATA19": "GTXE2_CHANNEL_TXDATA19", - "TXDATA2": "GTXE2_CHANNEL_TXDATA2", - "TXDATA20": "GTXE2_CHANNEL_TXDATA20", - "TXDATA21": "GTXE2_CHANNEL_TXDATA21", - "TXDATA22": "GTXE2_CHANNEL_TXDATA22", - "TXDATA23": "GTXE2_CHANNEL_TXDATA23", - "TXDATA24": "GTXE2_CHANNEL_TXDATA24", - "TXDATA25": "GTXE2_CHANNEL_TXDATA25", - "TXDATA26": "GTXE2_CHANNEL_TXDATA26", - "TXDATA27": "GTXE2_CHANNEL_TXDATA27", - "TXDATA28": "GTXE2_CHANNEL_TXDATA28", - "TXDATA29": "GTXE2_CHANNEL_TXDATA29", - "TXDATA3": "GTXE2_CHANNEL_TXDATA3", - "TXDATA30": "GTXE2_CHANNEL_TXDATA30", - "TXDATA31": "GTXE2_CHANNEL_TXDATA31", - "TXDATA32": "GTXE2_CHANNEL_TXDATA32", - "TXDATA33": "GTXE2_CHANNEL_TXDATA33", - "TXDATA34": "GTXE2_CHANNEL_TXDATA34", - "TXDATA35": "GTXE2_CHANNEL_TXDATA35", - "TXDATA36": "GTXE2_CHANNEL_TXDATA36", - "TXDATA37": "GTXE2_CHANNEL_TXDATA37", - "TXDATA38": "GTXE2_CHANNEL_TXDATA38", - "TXDATA39": "GTXE2_CHANNEL_TXDATA39", - "TXDATA4": "GTXE2_CHANNEL_TXDATA4", - "TXDATA40": "GTXE2_CHANNEL_TXDATA40", - "TXDATA41": "GTXE2_CHANNEL_TXDATA41", - "TXDATA42": "GTXE2_CHANNEL_TXDATA42", - "TXDATA43": "GTXE2_CHANNEL_TXDATA43", - "TXDATA44": "GTXE2_CHANNEL_TXDATA44", - "TXDATA45": "GTXE2_CHANNEL_TXDATA45", - "TXDATA46": "GTXE2_CHANNEL_TXDATA46", - "TXDATA47": "GTXE2_CHANNEL_TXDATA47", - "TXDATA48": "GTXE2_CHANNEL_TXDATA48", - "TXDATA49": "GTXE2_CHANNEL_TXDATA49", - "TXDATA5": "GTXE2_CHANNEL_TXDATA5", - "TXDATA50": "GTXE2_CHANNEL_TXDATA50", - "TXDATA51": "GTXE2_CHANNEL_TXDATA51", - "TXDATA52": "GTXE2_CHANNEL_TXDATA52", - "TXDATA53": "GTXE2_CHANNEL_TXDATA53", - "TXDATA54": "GTXE2_CHANNEL_TXDATA54", - "TXDATA55": "GTXE2_CHANNEL_TXDATA55", - "TXDATA56": "GTXE2_CHANNEL_TXDATA56", - "TXDATA57": "GTXE2_CHANNEL_TXDATA57", - "TXDATA58": "GTXE2_CHANNEL_TXDATA58", - "TXDATA59": "GTXE2_CHANNEL_TXDATA59", - "TXDATA6": "GTXE2_CHANNEL_TXDATA6", - "TXDATA60": "GTXE2_CHANNEL_TXDATA60", - "TXDATA61": "GTXE2_CHANNEL_TXDATA61", - "TXDATA62": "GTXE2_CHANNEL_TXDATA62", - "TXDATA63": "GTXE2_CHANNEL_TXDATA63", - "TXDATA7": "GTXE2_CHANNEL_TXDATA7", - "TXDATA8": "GTXE2_CHANNEL_TXDATA8", - "TXDATA9": "GTXE2_CHANNEL_TXDATA9", - "TXDEEMPH": "GTXE2_CHANNEL_TXDEEMPH", - "TXDETECTRX": "GTXE2_CHANNEL_TXDETECTRX", - "TXDIFFCTRL0": "GTXE2_CHANNEL_TXDIFFCTRL0", - "TXDIFFCTRL1": "GTXE2_CHANNEL_TXDIFFCTRL1", - "TXDIFFCTRL2": "GTXE2_CHANNEL_TXDIFFCTRL2", - "TXDIFFCTRL3": "GTXE2_CHANNEL_TXDIFFCTRL3", - "TXDIFFPD": "GTXE2_CHANNEL_TXDIFFPD", - "TXDLYBYPASS": "GTXE2_CHANNEL_TXDLYBYPASS", - "TXDLYEN": "GTXE2_CHANNEL_TXDLYEN", - "TXDLYHOLD": "GTXE2_CHANNEL_TXDLYHOLD", - "TXDLYOVRDEN": "GTXE2_CHANNEL_TXDLYOVRDEN", - "TXDLYSRESET": "GTXE2_CHANNEL_TXDLYSRESET", - "TXDLYSRESETDONE": "GTXE2_CHANNEL_TXDLYSRESETDONE", - "TXDLYTESTENB": "GTXE2_CHANNEL_TXDLYTESTENB", - "TXDLYUPDOWN": "GTXE2_CHANNEL_TXDLYUPDOWN", - "TXELECIDLE": "GTXE2_CHANNEL_TXELECIDLE", - "TXGEARBOXREADY": "GTXE2_CHANNEL_TXGEARBOXREADY", - "TXHEADER0": "GTXE2_CHANNEL_TXHEADER0", - "TXHEADER1": "GTXE2_CHANNEL_TXHEADER1", - "TXHEADER2": "GTXE2_CHANNEL_TXHEADER2", - "TXINHIBIT": "GTXE2_CHANNEL_TXINHIBIT", - "TXMAINCURSOR0": "GTXE2_CHANNEL_TXMAINCURSOR0", - "TXMAINCURSOR1": "GTXE2_CHANNEL_TXMAINCURSOR1", - "TXMAINCURSOR2": "GTXE2_CHANNEL_TXMAINCURSOR2", - "TXMAINCURSOR3": "GTXE2_CHANNEL_TXMAINCURSOR3", - "TXMAINCURSOR4": "GTXE2_CHANNEL_TXMAINCURSOR4", - "TXMAINCURSOR5": "GTXE2_CHANNEL_TXMAINCURSOR5", - "TXMAINCURSOR6": "GTXE2_CHANNEL_TXMAINCURSOR6", - "TXMARGIN0": "GTXE2_CHANNEL_TXMARGIN0", - "TXMARGIN1": "GTXE2_CHANNEL_TXMARGIN1", - "TXMARGIN2": "GTXE2_CHANNEL_TXMARGIN2", - "TXOUTCLK": "GTXE2_CHANNEL_GTTXOUTCLK_1", - "TXOUTCLKFABRIC": "GTXE2_CHANNEL_TXOUTCLKFABRIC", - "TXOUTCLKPCS": "GTXE2_CHANNEL_TXOUTCLKPCS", - "TXOUTCLKSEL0": "GTXE2_CHANNEL_TXOUTCLKSEL0", - "TXOUTCLKSEL1": "GTXE2_CHANNEL_TXOUTCLKSEL1", - "TXOUTCLKSEL2": "GTXE2_CHANNEL_TXOUTCLKSEL2", - "TXPCSRESET": "GTXE2_CHANNEL_TXPCSRESET", - "TXPD0": "GTXE2_CHANNEL_TXPD0", - "TXPD1": "GTXE2_CHANNEL_TXPD1", - "TXPDELECIDLEMODE": "GTXE2_CHANNEL_TXPDELECIDLEMODE", - "TXPHALIGN": "GTXE2_CHANNEL_TXPHALIGN", - "TXPHALIGNDONE": "GTXE2_CHANNEL_TXPHALIGNDONE", - "TXPHALIGNEN": "GTXE2_CHANNEL_TXPHALIGNEN", - "TXPHDLYPD": "GTXE2_CHANNEL_TXPHDLYPD", - "TXPHDLYRESET": "GTXE2_CHANNEL_TXPHDLYRESET", - "TXPHDLYTSTCLK": "GTXE2_CHANNEL_TXPHDLYTSTCLK", - "TXPHINIT": "GTXE2_CHANNEL_TXPHINIT", - "TXPHINITDONE": "GTXE2_CHANNEL_TXPHINITDONE", - "TXPHOVRDEN": "GTXE2_CHANNEL_TXPHOVRDEN", - "TXPISOPD": "GTXE2_CHANNEL_TXPISOPD", - "TXPMARESET": "GTXE2_CHANNEL_TXPMARESET", - "TXPOLARITY": "GTXE2_CHANNEL_TXPOLARITY", - "TXPOSTCURSOR0": "GTXE2_CHANNEL_TXPOSTCURSOR0", - "TXPOSTCURSOR1": "GTXE2_CHANNEL_TXPOSTCURSOR1", - "TXPOSTCURSOR2": "GTXE2_CHANNEL_TXPOSTCURSOR2", - "TXPOSTCURSOR3": "GTXE2_CHANNEL_TXPOSTCURSOR3", - "TXPOSTCURSOR4": "GTXE2_CHANNEL_TXPOSTCURSOR4", - "TXPOSTCURSORINV": "GTXE2_CHANNEL_TXPOSTCURSORINV", - "TXPRBSFORCEERR": "GTXE2_CHANNEL_TXPRBSFORCEERR", - "TXPRBSSEL0": "GTXE2_CHANNEL_TXPRBSSEL0", - "TXPRBSSEL1": "GTXE2_CHANNEL_TXPRBSSEL1", - "TXPRBSSEL2": "GTXE2_CHANNEL_TXPRBSSEL2", - "TXPRECURSOR0": "GTXE2_CHANNEL_TXPRECURSOR0", - "TXPRECURSOR1": "GTXE2_CHANNEL_TXPRECURSOR1", - "TXPRECURSOR2": "GTXE2_CHANNEL_TXPRECURSOR2", - "TXPRECURSOR3": "GTXE2_CHANNEL_TXPRECURSOR3", - "TXPRECURSOR4": "GTXE2_CHANNEL_TXPRECURSOR4", - "TXPRECURSORINV": "GTXE2_CHANNEL_TXPRECURSORINV", - "TXQPIBIASEN": "GTXE2_CHANNEL_TXQPIBIASEN", - "TXQPISENN": "GTXE2_CHANNEL_TXQPISENN", - "TXQPISENP": "GTXE2_CHANNEL_TXQPISENP", - "TXQPISTRONGPDOWN": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", - "TXQPIWEAKPUP": "GTXE2_CHANNEL_TXQPIWEAKPUP", - "TXRATE0": "GTXE2_CHANNEL_TXRATE0", - "TXRATE1": "GTXE2_CHANNEL_TXRATE1", - "TXRATE2": "GTXE2_CHANNEL_TXRATE2", - "TXRATEDONE": "GTXE2_CHANNEL_TXRATEDONE", - "TXRESETDONE": "GTXE2_CHANNEL_TXRESETDONE", - "TXRUNDISP0": "GTXE2_CHANNEL_TXRUNDISP0", - "TXRUNDISP1": "GTXE2_CHANNEL_TXRUNDISP1", - "TXRUNDISP2": "GTXE2_CHANNEL_TXRUNDISP2", - "TXRUNDISP3": "GTXE2_CHANNEL_TXRUNDISP3", - "TXRUNDISP4": "GTXE2_CHANNEL_TXRUNDISP4", - "TXRUNDISP5": "GTXE2_CHANNEL_TXRUNDISP5", - "TXRUNDISP6": "GTXE2_CHANNEL_TXRUNDISP6", - "TXRUNDISP7": "GTXE2_CHANNEL_TXRUNDISP7", - "TXSEQUENCE0": "GTXE2_CHANNEL_TXSEQUENCE0", - "TXSEQUENCE1": "GTXE2_CHANNEL_TXSEQUENCE1", - "TXSEQUENCE2": "GTXE2_CHANNEL_TXSEQUENCE2", - "TXSEQUENCE3": "GTXE2_CHANNEL_TXSEQUENCE3", - "TXSEQUENCE4": "GTXE2_CHANNEL_TXSEQUENCE4", - "TXSEQUENCE5": "GTXE2_CHANNEL_TXSEQUENCE5", - "TXSEQUENCE6": "GTXE2_CHANNEL_TXSEQUENCE6", - "TXSTARTSEQ": "GTXE2_CHANNEL_TXSTARTSEQ", - "TXSWING": "GTXE2_CHANNEL_TXSWING", - "TXSYSCLKSEL0": "GTXE2_CHANNEL_TXSYSCLKSEL0", - "TXSYSCLKSEL1": "GTXE2_CHANNEL_TXSYSCLKSEL1", - "TXUSERRDY": "GTXE2_CHANNEL_TXUSERRDY", - "TXUSRCLK": "GTXE2_CHANNEL_TXUSRCLK", - "TXUSRCLK2": "GTXE2_CHANNEL_TXUSRCLK2" + "CFGRESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CFGRESET" + }, + "CLKRSVD0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD0" + }, + "CLKRSVD1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD1" + }, + "CLKRSVD2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD2" + }, + "CLKRSVD3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + 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"wire": "GTXE2_CHANNEL_TXQPISENN" + }, + "TXQPISENP": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXQPISENP" + }, + "TXQPISTRONGPDOWN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN" + }, + "TXQPIWEAKPUP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXQPIWEAKPUP" + }, + "TXRATE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXRATE0" + }, + "TXRATE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXRATE1" + }, + "TXRATE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXRATE2" + }, + "TXRATEDONE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRATEDONE" + }, + "TXRESETDONE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRESETDONE" + }, + "TXRUNDISP0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP0" + }, + "TXRUNDISP1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP1" + }, + "TXRUNDISP2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP2" + }, + "TXRUNDISP3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP3" + }, + "TXRUNDISP4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP4" + }, + "TXRUNDISP5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP5" + }, + "TXRUNDISP6": { + "delay": [ + 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"0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE5" + }, + "TXSEQUENCE6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE6" + }, + "TXSTARTSEQ": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSTARTSEQ" + }, + "TXSWING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSWING" + }, + "TXSYSCLKSEL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSYSCLKSEL0" + }, + "TXSYSCLKSEL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSYSCLKSEL1" + }, + "TXUSERRDY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSERRDY" + }, + "TXUSRCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSRCLK" + }, + "TXUSRCLK2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSRCLK2" + } }, "type": "GTXE2_CHANNEL", "x_coord": 0, @@ -5095,7 +18159,16 @@ "name": "X0Y0", "prefix": "IPAD", "site_pins": { - "O": "GTXE2_CHANNEL_RXN_PAD" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "GTXE2_CHANNEL_RXN_PAD" + } }, "type": "IPAD", "x_coord": 0, @@ -5105,7 +18178,16 @@ "name": "X0Y1", "prefix": "IPAD", "site_pins": { - "O": "GTXE2_CHANNEL_RXP_PAD" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "GTXE2_CHANNEL_RXP_PAD" + } }, "type": "IPAD", "x_coord": 0, @@ -5115,7 +18197,16 @@ "name": "X0Y0", "prefix": "OPAD", "site_pins": { - "I": "GTXE2_CHANNEL_TXN_PAD" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXN_PAD" + } }, "type": "OPAD", "x_coord": 0, @@ -5125,7 +18216,16 @@ "name": "X0Y1", "prefix": "OPAD", "site_pins": { - "I": "GTXE2_CHANNEL_TXP_PAD" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXP_PAD" + } }, "type": "OPAD", "x_coord": 0, @@ -5133,1722 +18233,5310 @@ } ], "tile_type": "GTX_CHANNEL_1", - "wires": [ - "GTXE2_BYP0_0", - "GTXE2_BYP0_1", - "GTXE2_BYP0_10", - "GTXE2_BYP0_2", - "GTXE2_BYP0_3", - "GTXE2_BYP0_4", - "GTXE2_BYP0_5", - "GTXE2_BYP0_6", - "GTXE2_BYP0_7", - "GTXE2_BYP0_8", - "GTXE2_BYP0_9", - "GTXE2_BYP1_0", - "GTXE2_BYP1_1", - "GTXE2_BYP1_10", - "GTXE2_BYP1_2", - "GTXE2_BYP1_3", - "GTXE2_BYP1_4", - "GTXE2_BYP1_5", - "GTXE2_BYP1_6", - "GTXE2_BYP1_7", - "GTXE2_BYP1_8", - "GTXE2_BYP1_9", - "GTXE2_BYP2_0", - "GTXE2_BYP2_1", - "GTXE2_BYP2_10", - "GTXE2_BYP2_2", - "GTXE2_BYP2_3", - "GTXE2_BYP2_4", - "GTXE2_BYP2_5", - "GTXE2_BYP2_6", - "GTXE2_BYP2_7", - "GTXE2_BYP2_8", - "GTXE2_BYP2_9", - "GTXE2_BYP3_0", - "GTXE2_BYP3_1", - "GTXE2_BYP3_10", - "GTXE2_BYP3_2", - "GTXE2_BYP3_3", - "GTXE2_BYP3_4", - "GTXE2_BYP3_5", - "GTXE2_BYP3_6", - "GTXE2_BYP3_7", - "GTXE2_BYP3_8", - "GTXE2_BYP3_9", - "GTXE2_BYP4_0", - "GTXE2_BYP4_1", - "GTXE2_BYP4_10", - "GTXE2_BYP4_2", - "GTXE2_BYP4_3", - "GTXE2_BYP4_4", - "GTXE2_BYP4_5", - "GTXE2_BYP4_6", - "GTXE2_BYP4_7", - "GTXE2_BYP4_8", - "GTXE2_BYP4_9", - "GTXE2_BYP5_0", - "GTXE2_BYP5_1", - "GTXE2_BYP5_10", - "GTXE2_BYP5_2", - "GTXE2_BYP5_3", - "GTXE2_BYP5_4", - "GTXE2_BYP5_5", - "GTXE2_BYP5_6", - "GTXE2_BYP5_7", - "GTXE2_BYP5_8", - "GTXE2_BYP5_9", - "GTXE2_BYP6_0", - "GTXE2_BYP6_1", - "GTXE2_BYP6_10", - "GTXE2_BYP6_2", - "GTXE2_BYP6_3", - "GTXE2_BYP6_4", - "GTXE2_BYP6_5", - "GTXE2_BYP6_6", - "GTXE2_BYP6_7", - "GTXE2_BYP6_8", - "GTXE2_BYP6_9", - "GTXE2_BYP7_0", - "GTXE2_BYP7_1", - "GTXE2_BYP7_10", - "GTXE2_BYP7_2", - "GTXE2_BYP7_3", - "GTXE2_BYP7_4", - "GTXE2_BYP7_5", - "GTXE2_BYP7_6", - "GTXE2_BYP7_7", - "GTXE2_BYP7_8", - "GTXE2_BYP7_9", - "GTXE2_CHANNEL_CFGRESET", - "GTXE2_CHANNEL_CLKRSVD0", - "GTXE2_CHANNEL_CLKRSVD1", - "GTXE2_CHANNEL_CLKRSVD2", - "GTXE2_CHANNEL_CLKRSVD3", - "GTXE2_CHANNEL_CPLLFBCLKLOST", - "GTXE2_CHANNEL_CPLLLOCK", - "GTXE2_CHANNEL_CPLLLOCKDETCLK", - "GTXE2_CHANNEL_CPLLLOCKEN", - "GTXE2_CHANNEL_CPLLPD", - "GTXE2_CHANNEL_CPLLREFCLKLOST", - "GTXE2_CHANNEL_CPLLREFCLKSEL0", - "GTXE2_CHANNEL_CPLLREFCLKSEL1", - "GTXE2_CHANNEL_CPLLREFCLKSEL2", - "GTXE2_CHANNEL_CPLLRESET", - "GTXE2_CHANNEL_DMONITOROUT0", - "GTXE2_CHANNEL_DMONITOROUT1", - "GTXE2_CHANNEL_DMONITOROUT2", - "GTXE2_CHANNEL_DMONITOROUT3", - "GTXE2_CHANNEL_DMONITOROUT4", - "GTXE2_CHANNEL_DMONITOROUT5", - "GTXE2_CHANNEL_DMONITOROUT6", - "GTXE2_CHANNEL_DMONITOROUT7", - "GTXE2_CHANNEL_DRPADDR0", - "GTXE2_CHANNEL_DRPADDR1", - "GTXE2_CHANNEL_DRPADDR2", - "GTXE2_CHANNEL_DRPADDR3", - "GTXE2_CHANNEL_DRPADDR4", - "GTXE2_CHANNEL_DRPADDR5", - "GTXE2_CHANNEL_DRPADDR6", - "GTXE2_CHANNEL_DRPADDR7", - "GTXE2_CHANNEL_DRPADDR8", - "GTXE2_CHANNEL_DRPCLK", - "GTXE2_CHANNEL_DRPDI0", - "GTXE2_CHANNEL_DRPDI1", - "GTXE2_CHANNEL_DRPDI10", - "GTXE2_CHANNEL_DRPDI11", - "GTXE2_CHANNEL_DRPDI12", - "GTXE2_CHANNEL_DRPDI13", - "GTXE2_CHANNEL_DRPDI14", - "GTXE2_CHANNEL_DRPDI15", - "GTXE2_CHANNEL_DRPDI2", - "GTXE2_CHANNEL_DRPDI3", - "GTXE2_CHANNEL_DRPDI4", - "GTXE2_CHANNEL_DRPDI5", - "GTXE2_CHANNEL_DRPDI6", - "GTXE2_CHANNEL_DRPDI7", - "GTXE2_CHANNEL_DRPDI8", - "GTXE2_CHANNEL_DRPDI9", - "GTXE2_CHANNEL_DRPDO0", - "GTXE2_CHANNEL_DRPDO1", - "GTXE2_CHANNEL_DRPDO10", - "GTXE2_CHANNEL_DRPDO11", - "GTXE2_CHANNEL_DRPDO12", - "GTXE2_CHANNEL_DRPDO13", - "GTXE2_CHANNEL_DRPDO14", - "GTXE2_CHANNEL_DRPDO15", - "GTXE2_CHANNEL_DRPDO2", - "GTXE2_CHANNEL_DRPDO3", - "GTXE2_CHANNEL_DRPDO4", - "GTXE2_CHANNEL_DRPDO5", - "GTXE2_CHANNEL_DRPDO6", - "GTXE2_CHANNEL_DRPDO7", - "GTXE2_CHANNEL_DRPDO8", - "GTXE2_CHANNEL_DRPDO9", - "GTXE2_CHANNEL_DRPEN", - "GTXE2_CHANNEL_DRPRDY", - "GTXE2_CHANNEL_DRPWE", - "GTXE2_CHANNEL_EDTBYPASS", - "GTXE2_CHANNEL_EDTCLOCK", - "GTXE2_CHANNEL_EDTCONFIGURATION", - "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", - "GTXE2_CHANNEL_EDTUPDATE", - "GTXE2_CHANNEL_EYESCANDATAERROR", - "GTXE2_CHANNEL_EYESCANMODE", - "GTXE2_CHANNEL_EYESCANRESET", - "GTXE2_CHANNEL_EYESCANTRIGGER", - "GTXE2_CHANNEL_GTGREFCLK", - "GTXE2_CHANNEL_GTNORTHREFCLK0", - "GTXE2_CHANNEL_GTNORTHREFCLK1", - "GTXE2_CHANNEL_GTQPLLCLK", - "GTXE2_CHANNEL_GTQPLLREFCLK", - "GTXE2_CHANNEL_GTREFCLK0", - "GTXE2_CHANNEL_GTREFCLK1", - "GTXE2_CHANNEL_GTREFCLKMONITOR", - "GTXE2_CHANNEL_GTRESETSEL", - "GTXE2_CHANNEL_GTRSVD0", - "GTXE2_CHANNEL_GTRSVD1", - "GTXE2_CHANNEL_GTRSVD10", - "GTXE2_CHANNEL_GTRSVD11", - "GTXE2_CHANNEL_GTRSVD12", - "GTXE2_CHANNEL_GTRSVD13", - "GTXE2_CHANNEL_GTRSVD14", - "GTXE2_CHANNEL_GTRSVD15", - "GTXE2_CHANNEL_GTRSVD2", - "GTXE2_CHANNEL_GTRSVD3", - "GTXE2_CHANNEL_GTRSVD4", - "GTXE2_CHANNEL_GTRSVD5", - "GTXE2_CHANNEL_GTRSVD6", - "GTXE2_CHANNEL_GTRSVD7", - "GTXE2_CHANNEL_GTRSVD8", - "GTXE2_CHANNEL_GTRSVD9", - "GTXE2_CHANNEL_GTRXOUTCLK_1", - "GTXE2_CHANNEL_GTRXRESET", - "GTXE2_CHANNEL_GTSOUTHREFCLK0", - "GTXE2_CHANNEL_GTSOUTHREFCLK1", - "GTXE2_CHANNEL_GTTXOUTCLK_1", - "GTXE2_CHANNEL_GTTXRESET", - "GTXE2_CHANNEL_LOOPBACK0", - "GTXE2_CHANNEL_LOOPBACK1", - "GTXE2_CHANNEL_LOOPBACK2", - "GTXE2_CHANNEL_NORTHREFCLK0", - "GTXE2_CHANNEL_NORTHREFCLK1", - "GTXE2_CHANNEL_PCSRSVDIN0", - "GTXE2_CHANNEL_PCSRSVDIN1", - "GTXE2_CHANNEL_PCSRSVDIN10", - "GTXE2_CHANNEL_PCSRSVDIN11", - "GTXE2_CHANNEL_PCSRSVDIN12", - "GTXE2_CHANNEL_PCSRSVDIN13", - "GTXE2_CHANNEL_PCSRSVDIN14", - "GTXE2_CHANNEL_PCSRSVDIN15", - "GTXE2_CHANNEL_PCSRSVDIN2", - "GTXE2_CHANNEL_PCSRSVDIN20", - "GTXE2_CHANNEL_PCSRSVDIN21", - "GTXE2_CHANNEL_PCSRSVDIN22", - "GTXE2_CHANNEL_PCSRSVDIN23", - "GTXE2_CHANNEL_PCSRSVDIN24", - "GTXE2_CHANNEL_PCSRSVDIN3", - "GTXE2_CHANNEL_PCSRSVDIN4", - "GTXE2_CHANNEL_PCSRSVDIN5", - "GTXE2_CHANNEL_PCSRSVDIN6", - "GTXE2_CHANNEL_PCSRSVDIN7", - "GTXE2_CHANNEL_PCSRSVDIN8", - "GTXE2_CHANNEL_PCSRSVDIN9", - "GTXE2_CHANNEL_PCSRSVDOUT0", - "GTXE2_CHANNEL_PCSRSVDOUT1", - "GTXE2_CHANNEL_PCSRSVDOUT10", - "GTXE2_CHANNEL_PCSRSVDOUT11", - "GTXE2_CHANNEL_PCSRSVDOUT12", - "GTXE2_CHANNEL_PCSRSVDOUT13", - "GTXE2_CHANNEL_PCSRSVDOUT14", - "GTXE2_CHANNEL_PCSRSVDOUT15", - "GTXE2_CHANNEL_PCSRSVDOUT2", - "GTXE2_CHANNEL_PCSRSVDOUT3", - "GTXE2_CHANNEL_PCSRSVDOUT4", - "GTXE2_CHANNEL_PCSRSVDOUT5", - "GTXE2_CHANNEL_PCSRSVDOUT6", - "GTXE2_CHANNEL_PCSRSVDOUT7", - "GTXE2_CHANNEL_PCSRSVDOUT8", - "GTXE2_CHANNEL_PCSRSVDOUT9", - "GTXE2_CHANNEL_PHYSTATUS", - "GTXE2_CHANNEL_PMARSVDIN0", - "GTXE2_CHANNEL_PMARSVDIN1", - "GTXE2_CHANNEL_PMARSVDIN2", - "GTXE2_CHANNEL_PMARSVDIN20", - "GTXE2_CHANNEL_PMARSVDIN21", - "GTXE2_CHANNEL_PMARSVDIN22", - "GTXE2_CHANNEL_PMARSVDIN23", - "GTXE2_CHANNEL_PMARSVDIN24", - "GTXE2_CHANNEL_PMARSVDIN3", - "GTXE2_CHANNEL_PMARSVDIN4", - "GTXE2_CHANNEL_PMASCANCLK0", - "GTXE2_CHANNEL_PMASCANCLK1", - "GTXE2_CHANNEL_PMASCANCLK2", - "GTXE2_CHANNEL_PMASCANCLK3", - "GTXE2_CHANNEL_PMASCANCLK4", - "GTXE2_CHANNEL_PMASCANENB", - "GTXE2_CHANNEL_PMASCANIN0", - "GTXE2_CHANNEL_PMASCANIN1", - "GTXE2_CHANNEL_PMASCANIN2", - "GTXE2_CHANNEL_PMASCANIN3", - "GTXE2_CHANNEL_PMASCANIN4", - "GTXE2_CHANNEL_PMASCANMODEB", - "GTXE2_CHANNEL_PMASCANOUT0", - "GTXE2_CHANNEL_PMASCANOUT1", - "GTXE2_CHANNEL_PMASCANOUT2", - "GTXE2_CHANNEL_PMASCANOUT3", - "GTXE2_CHANNEL_PMASCANOUT4", - "GTXE2_CHANNEL_PMASCANRSTEN", - "GTXE2_CHANNEL_QPLLCLK", - "GTXE2_CHANNEL_QPLLREFCLK", - "GTXE2_CHANNEL_REFCLK0", - "GTXE2_CHANNEL_REFCLK1", - "GTXE2_CHANNEL_RESETOVRD", - "GTXE2_CHANNEL_RX8B10BEN", - "GTXE2_CHANNEL_RXBUFRESET", - "GTXE2_CHANNEL_RXBUFSTATUS0", - "GTXE2_CHANNEL_RXBUFSTATUS1", - "GTXE2_CHANNEL_RXBUFSTATUS2", - "GTXE2_CHANNEL_RXBYTEISALIGNED", - "GTXE2_CHANNEL_RXBYTEREALIGN", - "GTXE2_CHANNEL_RXCDRFREQRESET", - "GTXE2_CHANNEL_RXCDRHOLD", - "GTXE2_CHANNEL_RXCDRLOCK", - "GTXE2_CHANNEL_RXCDROVRDEN", - "GTXE2_CHANNEL_RXCDRRESET", - "GTXE2_CHANNEL_RXCDRRESETRSV", - "GTXE2_CHANNEL_RXCHANBONDSEQ", - "GTXE2_CHANNEL_RXCHANISALIGNED", - "GTXE2_CHANNEL_RXCHANREALIGN", - "GTXE2_CHANNEL_RXCHARISCOMMA0", - "GTXE2_CHANNEL_RXCHARISCOMMA1", - "GTXE2_CHANNEL_RXCHARISCOMMA2", - "GTXE2_CHANNEL_RXCHARISCOMMA3", - "GTXE2_CHANNEL_RXCHARISCOMMA4", - "GTXE2_CHANNEL_RXCHARISCOMMA5", - "GTXE2_CHANNEL_RXCHARISCOMMA6", - "GTXE2_CHANNEL_RXCHARISCOMMA7", - "GTXE2_CHANNEL_RXCHARISK0", - "GTXE2_CHANNEL_RXCHARISK1", - "GTXE2_CHANNEL_RXCHARISK2", - "GTXE2_CHANNEL_RXCHARISK3", - "GTXE2_CHANNEL_RXCHARISK4", - "GTXE2_CHANNEL_RXCHARISK5", - "GTXE2_CHANNEL_RXCHARISK6", - "GTXE2_CHANNEL_RXCHARISK7", - "GTXE2_CHANNEL_RXCHBONDEN", - "GTXE2_CHANNEL_RXCHBONDI0", - "GTXE2_CHANNEL_RXCHBONDI1", - "GTXE2_CHANNEL_RXCHBONDI2", - "GTXE2_CHANNEL_RXCHBONDI3", - "GTXE2_CHANNEL_RXCHBONDI4", - "GTXE2_CHANNEL_RXCHBONDLEVEL0", - "GTXE2_CHANNEL_RXCHBONDLEVEL1", - "GTXE2_CHANNEL_RXCHBONDLEVEL2", - "GTXE2_CHANNEL_RXCHBONDMASTER", - "GTXE2_CHANNEL_RXCHBONDO0", - "GTXE2_CHANNEL_RXCHBONDO1", - "GTXE2_CHANNEL_RXCHBONDO2", - "GTXE2_CHANNEL_RXCHBONDO3", - "GTXE2_CHANNEL_RXCHBONDO4", - "GTXE2_CHANNEL_RXCHBONDSLAVE", - "GTXE2_CHANNEL_RXCLKCORCNT0", - "GTXE2_CHANNEL_RXCLKCORCNT1", - "GTXE2_CHANNEL_RXCOMINITDET", - "GTXE2_CHANNEL_RXCOMMADET", - "GTXE2_CHANNEL_RXCOMMADETEN", - "GTXE2_CHANNEL_RXCOMSASDET", - "GTXE2_CHANNEL_RXCOMWAKEDET", - "GTXE2_CHANNEL_RXDATA0", - "GTXE2_CHANNEL_RXDATA1", - "GTXE2_CHANNEL_RXDATA10", - "GTXE2_CHANNEL_RXDATA11", - "GTXE2_CHANNEL_RXDATA12", - "GTXE2_CHANNEL_RXDATA13", - "GTXE2_CHANNEL_RXDATA14", - "GTXE2_CHANNEL_RXDATA15", - "GTXE2_CHANNEL_RXDATA16", - "GTXE2_CHANNEL_RXDATA17", - "GTXE2_CHANNEL_RXDATA18", - "GTXE2_CHANNEL_RXDATA19", - "GTXE2_CHANNEL_RXDATA2", - "GTXE2_CHANNEL_RXDATA20", - "GTXE2_CHANNEL_RXDATA21", - "GTXE2_CHANNEL_RXDATA22", - "GTXE2_CHANNEL_RXDATA23", - "GTXE2_CHANNEL_RXDATA24", - "GTXE2_CHANNEL_RXDATA25", - "GTXE2_CHANNEL_RXDATA26", - "GTXE2_CHANNEL_RXDATA27", - "GTXE2_CHANNEL_RXDATA28", - "GTXE2_CHANNEL_RXDATA29", - "GTXE2_CHANNEL_RXDATA3", - "GTXE2_CHANNEL_RXDATA30", - "GTXE2_CHANNEL_RXDATA31", - "GTXE2_CHANNEL_RXDATA32", - "GTXE2_CHANNEL_RXDATA33", - "GTXE2_CHANNEL_RXDATA34", - "GTXE2_CHANNEL_RXDATA35", - "GTXE2_CHANNEL_RXDATA36", - "GTXE2_CHANNEL_RXDATA37", - "GTXE2_CHANNEL_RXDATA38", - "GTXE2_CHANNEL_RXDATA39", - "GTXE2_CHANNEL_RXDATA4", - "GTXE2_CHANNEL_RXDATA40", - "GTXE2_CHANNEL_RXDATA41", - "GTXE2_CHANNEL_RXDATA42", - "GTXE2_CHANNEL_RXDATA43", - "GTXE2_CHANNEL_RXDATA44", - "GTXE2_CHANNEL_RXDATA45", - "GTXE2_CHANNEL_RXDATA46", - "GTXE2_CHANNEL_RXDATA47", - "GTXE2_CHANNEL_RXDATA48", - "GTXE2_CHANNEL_RXDATA49", - "GTXE2_CHANNEL_RXDATA5", - "GTXE2_CHANNEL_RXDATA50", - "GTXE2_CHANNEL_RXDATA51", - "GTXE2_CHANNEL_RXDATA52", - "GTXE2_CHANNEL_RXDATA53", - "GTXE2_CHANNEL_RXDATA54", - "GTXE2_CHANNEL_RXDATA55", - "GTXE2_CHANNEL_RXDATA56", - "GTXE2_CHANNEL_RXDATA57", - "GTXE2_CHANNEL_RXDATA58", - "GTXE2_CHANNEL_RXDATA59", - "GTXE2_CHANNEL_RXDATA6", - "GTXE2_CHANNEL_RXDATA60", - "GTXE2_CHANNEL_RXDATA61", - "GTXE2_CHANNEL_RXDATA62", - "GTXE2_CHANNEL_RXDATA63", - "GTXE2_CHANNEL_RXDATA7", - "GTXE2_CHANNEL_RXDATA8", - "GTXE2_CHANNEL_RXDATA9", - "GTXE2_CHANNEL_RXDATAVALID", - "GTXE2_CHANNEL_RXDDIEN", - "GTXE2_CHANNEL_RXDEBUGPULSE", - "GTXE2_CHANNEL_RXDFEAGCHOLD", - "GTXE2_CHANNEL_RXDFEAGCOVRDEN", - "GTXE2_CHANNEL_RXDFECM1EN", - "GTXE2_CHANNEL_RXDFELFHOLD", - "GTXE2_CHANNEL_RXDFELFOVRDEN", - "GTXE2_CHANNEL_RXDFELPMRESET", - "GTXE2_CHANNEL_RXDFETAP2HOLD", - "GTXE2_CHANNEL_RXDFETAP2OVRDEN", - "GTXE2_CHANNEL_RXDFETAP3HOLD", - "GTXE2_CHANNEL_RXDFETAP3OVRDEN", - "GTXE2_CHANNEL_RXDFETAP4HOLD", - "GTXE2_CHANNEL_RXDFETAP4OVRDEN", - "GTXE2_CHANNEL_RXDFETAP5HOLD", - "GTXE2_CHANNEL_RXDFETAP5OVRDEN", - "GTXE2_CHANNEL_RXDFEUTHOLD", - "GTXE2_CHANNEL_RXDFEUTOVRDEN", - "GTXE2_CHANNEL_RXDFEVPHOLD", - "GTXE2_CHANNEL_RXDFEVPOVRDEN", - "GTXE2_CHANNEL_RXDFEVSEN", - "GTXE2_CHANNEL_RXDFEXYDEN", - "GTXE2_CHANNEL_RXDFEXYDHOLD", - "GTXE2_CHANNEL_RXDFEXYDOVRDEN", - "GTXE2_CHANNEL_RXDISPERR0", - "GTXE2_CHANNEL_RXDISPERR1", - "GTXE2_CHANNEL_RXDISPERR2", - "GTXE2_CHANNEL_RXDISPERR3", - "GTXE2_CHANNEL_RXDISPERR4", - "GTXE2_CHANNEL_RXDISPERR5", - "GTXE2_CHANNEL_RXDISPERR6", - "GTXE2_CHANNEL_RXDISPERR7", - "GTXE2_CHANNEL_RXDLYBYPASS", - "GTXE2_CHANNEL_RXDLYEN", - "GTXE2_CHANNEL_RXDLYOVRDEN", - "GTXE2_CHANNEL_RXDLYSRESET", - "GTXE2_CHANNEL_RXDLYSRESETDONE", - "GTXE2_CHANNEL_RXDLYTESTENB", - "GTXE2_CHANNEL_RXELECIDLE", - "GTXE2_CHANNEL_RXELECIDLEMODE0", - "GTXE2_CHANNEL_RXELECIDLEMODE1", - "GTXE2_CHANNEL_RXGEARBOXSLIP", - "GTXE2_CHANNEL_RXHEADER0", - "GTXE2_CHANNEL_RXHEADER1", - "GTXE2_CHANNEL_RXHEADER2", - "GTXE2_CHANNEL_RXHEADERVALID", - "GTXE2_CHANNEL_RXLPMEN", - "GTXE2_CHANNEL_RXLPMHFHOLD", - "GTXE2_CHANNEL_RXLPMHFOVRDEN", - "GTXE2_CHANNEL_RXLPMLFHOLD", - "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", - "GTXE2_CHANNEL_RXMCOMMAALIGNEN", - "GTXE2_CHANNEL_RXMONITOROUT0", - "GTXE2_CHANNEL_RXMONITOROUT1", - "GTXE2_CHANNEL_RXMONITOROUT2", - "GTXE2_CHANNEL_RXMONITOROUT3", - "GTXE2_CHANNEL_RXMONITOROUT4", - "GTXE2_CHANNEL_RXMONITOROUT5", - "GTXE2_CHANNEL_RXMONITOROUT6", - "GTXE2_CHANNEL_RXMONITORSEL0", - "GTXE2_CHANNEL_RXMONITORSEL1", - "GTXE2_CHANNEL_RXN", - "GTXE2_CHANNEL_RXNOTINTABLE0", - "GTXE2_CHANNEL_RXNOTINTABLE1", - "GTXE2_CHANNEL_RXNOTINTABLE2", - "GTXE2_CHANNEL_RXNOTINTABLE3", - "GTXE2_CHANNEL_RXNOTINTABLE4", - "GTXE2_CHANNEL_RXNOTINTABLE5", - "GTXE2_CHANNEL_RXNOTINTABLE6", - "GTXE2_CHANNEL_RXNOTINTABLE7", - "GTXE2_CHANNEL_RXN_PAD", - "GTXE2_CHANNEL_RXOOBRESET", - "GTXE2_CHANNEL_RXOSHOLD", - "GTXE2_CHANNEL_RXOSOVRDEN", - "GTXE2_CHANNEL_RXOUTCLKFABRIC", - "GTXE2_CHANNEL_RXOUTCLKPCS", - "GTXE2_CHANNEL_RXOUTCLKSEL0", - "GTXE2_CHANNEL_RXOUTCLKSEL1", - "GTXE2_CHANNEL_RXOUTCLKSEL2", - "GTXE2_CHANNEL_RXOUTCLK_0", - "GTXE2_CHANNEL_RXOUTCLK_1", - "GTXE2_CHANNEL_RXOUTCLK_2", - "GTXE2_CHANNEL_RXOUTCLK_3", - "GTXE2_CHANNEL_RXP", - "GTXE2_CHANNEL_RXPCD1DONE", - "GTXE2_CHANNEL_RXPCOMMAALIGNEN", - "GTXE2_CHANNEL_RXPCSRESET", - "GTXE2_CHANNEL_RXPD0", - "GTXE2_CHANNEL_RXPD1", - "GTXE2_CHANNEL_RXPHALIGN", - "GTXE2_CHANNEL_RXPHALIGNDONE", - "GTXE2_CHANNEL_RXPHALIGNEN", - "GTXE2_CHANNEL_RXPHDLYPD", - "GTXE2_CHANNEL_RXPHDLYRESET", - "GTXE2_CHANNEL_RXPHMONITOR0", - "GTXE2_CHANNEL_RXPHMONITOR1", - "GTXE2_CHANNEL_RXPHMONITOR2", - "GTXE2_CHANNEL_RXPHMONITOR3", - "GTXE2_CHANNEL_RXPHMONITOR4", - "GTXE2_CHANNEL_RXPHOVRDEN", - "GTXE2_CHANNEL_RXPHSLIPMONITOR0", - "GTXE2_CHANNEL_RXPHSLIPMONITOR1", - "GTXE2_CHANNEL_RXPHSLIPMONITOR2", - "GTXE2_CHANNEL_RXPHSLIPMONITOR3", - "GTXE2_CHANNEL_RXPHSLIPMONITOR4", - "GTXE2_CHANNEL_RXPMARESET", - "GTXE2_CHANNEL_RXPOLARITY", - "GTXE2_CHANNEL_RXPRBSCNTRESET", - "GTXE2_CHANNEL_RXPRBSERR", - "GTXE2_CHANNEL_RXPRBSSEL0", - "GTXE2_CHANNEL_RXPRBSSEL1", - "GTXE2_CHANNEL_RXPRBSSEL2", - "GTXE2_CHANNEL_RXP_PAD", - "GTXE2_CHANNEL_RXQPIEN", - "GTXE2_CHANNEL_RXQPISENN", - "GTXE2_CHANNEL_RXQPISENP", - "GTXE2_CHANNEL_RXRATE0", - "GTXE2_CHANNEL_RXRATE1", - "GTXE2_CHANNEL_RXRATE2", - "GTXE2_CHANNEL_RXRATEDONE", - "GTXE2_CHANNEL_RXRESETDONE", - "GTXE2_CHANNEL_RXSLIDE", - "GTXE2_CHANNEL_RXSTARTOFSEQ", - "GTXE2_CHANNEL_RXSTATUS0", - "GTXE2_CHANNEL_RXSTATUS1", - "GTXE2_CHANNEL_RXSTATUS2", - "GTXE2_CHANNEL_RXSYSCLKSEL0", - "GTXE2_CHANNEL_RXSYSCLKSEL1", - "GTXE2_CHANNEL_RXUSERRDY", - "GTXE2_CHANNEL_RXUSRCLK", - "GTXE2_CHANNEL_RXUSRCLK2", - "GTXE2_CHANNEL_RXVALID", - "GTXE2_CHANNEL_SCANCLK", - "GTXE2_CHANNEL_SCANENB", - "GTXE2_CHANNEL_SCANIN0", - "GTXE2_CHANNEL_SCANIN1", - "GTXE2_CHANNEL_SCANIN2", - "GTXE2_CHANNEL_SCANIN3", - "GTXE2_CHANNEL_SCANIN4", - "GTXE2_CHANNEL_SCANMODEB", - "GTXE2_CHANNEL_SCANOUT0", - "GTXE2_CHANNEL_SCANOUT1", - "GTXE2_CHANNEL_SCANOUT2", - "GTXE2_CHANNEL_SCANOUT3", - "GTXE2_CHANNEL_SCANOUT4", - "GTXE2_CHANNEL_SETERRSTATUS", - "GTXE2_CHANNEL_SOUTHREFCLK0", - "GTXE2_CHANNEL_SOUTHREFCLK1", - "GTXE2_CHANNEL_TSTCLK0", - "GTXE2_CHANNEL_TSTCLK1", - "GTXE2_CHANNEL_TSTIN0", - "GTXE2_CHANNEL_TSTIN1", - "GTXE2_CHANNEL_TSTIN10", - "GTXE2_CHANNEL_TSTIN11", - "GTXE2_CHANNEL_TSTIN12", - "GTXE2_CHANNEL_TSTIN13", - "GTXE2_CHANNEL_TSTIN14", - "GTXE2_CHANNEL_TSTIN15", - "GTXE2_CHANNEL_TSTIN16", - "GTXE2_CHANNEL_TSTIN17", - "GTXE2_CHANNEL_TSTIN18", - "GTXE2_CHANNEL_TSTIN19", - "GTXE2_CHANNEL_TSTIN2", - "GTXE2_CHANNEL_TSTIN3", - "GTXE2_CHANNEL_TSTIN4", - "GTXE2_CHANNEL_TSTIN5", - "GTXE2_CHANNEL_TSTIN6", - "GTXE2_CHANNEL_TSTIN7", - "GTXE2_CHANNEL_TSTIN8", - "GTXE2_CHANNEL_TSTIN9", - "GTXE2_CHANNEL_TSTOUT0", - "GTXE2_CHANNEL_TSTOUT1", - "GTXE2_CHANNEL_TSTOUT2", - "GTXE2_CHANNEL_TSTOUT3", - "GTXE2_CHANNEL_TSTOUT4", - "GTXE2_CHANNEL_TSTOUT5", - "GTXE2_CHANNEL_TSTOUT6", - "GTXE2_CHANNEL_TSTOUT7", - "GTXE2_CHANNEL_TSTOUT8", - "GTXE2_CHANNEL_TSTOUT9", - "GTXE2_CHANNEL_TSTPD0", - "GTXE2_CHANNEL_TSTPD1", - "GTXE2_CHANNEL_TSTPD2", - "GTXE2_CHANNEL_TSTPD3", - "GTXE2_CHANNEL_TSTPD4", - "GTXE2_CHANNEL_TSTPDOVRDB", - "GTXE2_CHANNEL_TX8B10BBYPASS0", - "GTXE2_CHANNEL_TX8B10BBYPASS1", - "GTXE2_CHANNEL_TX8B10BBYPASS2", - "GTXE2_CHANNEL_TX8B10BBYPASS3", - "GTXE2_CHANNEL_TX8B10BBYPASS4", - "GTXE2_CHANNEL_TX8B10BBYPASS5", - "GTXE2_CHANNEL_TX8B10BBYPASS6", - "GTXE2_CHANNEL_TX8B10BBYPASS7", - "GTXE2_CHANNEL_TX8B10BEN", - "GTXE2_CHANNEL_TXBUFDIFFCTRL0", - "GTXE2_CHANNEL_TXBUFDIFFCTRL1", - "GTXE2_CHANNEL_TXBUFDIFFCTRL2", - "GTXE2_CHANNEL_TXBUFSTATUS0", - "GTXE2_CHANNEL_TXBUFSTATUS1", - "GTXE2_CHANNEL_TXCHARDISPMODE0", - "GTXE2_CHANNEL_TXCHARDISPMODE1", - "GTXE2_CHANNEL_TXCHARDISPMODE2", - "GTXE2_CHANNEL_TXCHARDISPMODE3", - "GTXE2_CHANNEL_TXCHARDISPMODE4", - "GTXE2_CHANNEL_TXCHARDISPMODE5", - "GTXE2_CHANNEL_TXCHARDISPMODE6", - "GTXE2_CHANNEL_TXCHARDISPMODE7", - "GTXE2_CHANNEL_TXCHARDISPVAL0", - "GTXE2_CHANNEL_TXCHARDISPVAL1", - "GTXE2_CHANNEL_TXCHARDISPVAL2", - "GTXE2_CHANNEL_TXCHARDISPVAL3", - "GTXE2_CHANNEL_TXCHARDISPVAL4", - "GTXE2_CHANNEL_TXCHARDISPVAL5", - "GTXE2_CHANNEL_TXCHARDISPVAL6", - "GTXE2_CHANNEL_TXCHARDISPVAL7", - "GTXE2_CHANNEL_TXCHARISK0", - "GTXE2_CHANNEL_TXCHARISK1", - "GTXE2_CHANNEL_TXCHARISK2", - "GTXE2_CHANNEL_TXCHARISK3", - "GTXE2_CHANNEL_TXCHARISK4", - "GTXE2_CHANNEL_TXCHARISK5", - "GTXE2_CHANNEL_TXCHARISK6", - "GTXE2_CHANNEL_TXCHARISK7", - "GTXE2_CHANNEL_TXCOMFINISH", - "GTXE2_CHANNEL_TXCOMINIT", - "GTXE2_CHANNEL_TXCOMSAS", - "GTXE2_CHANNEL_TXCOMWAKE", - "GTXE2_CHANNEL_TXDATA0", - "GTXE2_CHANNEL_TXDATA1", - "GTXE2_CHANNEL_TXDATA10", - "GTXE2_CHANNEL_TXDATA11", - "GTXE2_CHANNEL_TXDATA12", - "GTXE2_CHANNEL_TXDATA13", - "GTXE2_CHANNEL_TXDATA14", - "GTXE2_CHANNEL_TXDATA15", - "GTXE2_CHANNEL_TXDATA16", - "GTXE2_CHANNEL_TXDATA17", - "GTXE2_CHANNEL_TXDATA18", - "GTXE2_CHANNEL_TXDATA19", - "GTXE2_CHANNEL_TXDATA2", - "GTXE2_CHANNEL_TXDATA20", - "GTXE2_CHANNEL_TXDATA21", - "GTXE2_CHANNEL_TXDATA22", - "GTXE2_CHANNEL_TXDATA23", - "GTXE2_CHANNEL_TXDATA24", - "GTXE2_CHANNEL_TXDATA25", - "GTXE2_CHANNEL_TXDATA26", - "GTXE2_CHANNEL_TXDATA27", - "GTXE2_CHANNEL_TXDATA28", - "GTXE2_CHANNEL_TXDATA29", - "GTXE2_CHANNEL_TXDATA3", - "GTXE2_CHANNEL_TXDATA30", - "GTXE2_CHANNEL_TXDATA31", - "GTXE2_CHANNEL_TXDATA32", - "GTXE2_CHANNEL_TXDATA33", - "GTXE2_CHANNEL_TXDATA34", - "GTXE2_CHANNEL_TXDATA35", - "GTXE2_CHANNEL_TXDATA36", - "GTXE2_CHANNEL_TXDATA37", - "GTXE2_CHANNEL_TXDATA38", - "GTXE2_CHANNEL_TXDATA39", - "GTXE2_CHANNEL_TXDATA4", - "GTXE2_CHANNEL_TXDATA40", - "GTXE2_CHANNEL_TXDATA41", - "GTXE2_CHANNEL_TXDATA42", - "GTXE2_CHANNEL_TXDATA43", - "GTXE2_CHANNEL_TXDATA44", - "GTXE2_CHANNEL_TXDATA45", - "GTXE2_CHANNEL_TXDATA46", - "GTXE2_CHANNEL_TXDATA47", - "GTXE2_CHANNEL_TXDATA48", - "GTXE2_CHANNEL_TXDATA49", - "GTXE2_CHANNEL_TXDATA5", - "GTXE2_CHANNEL_TXDATA50", - "GTXE2_CHANNEL_TXDATA51", - "GTXE2_CHANNEL_TXDATA52", - "GTXE2_CHANNEL_TXDATA53", - "GTXE2_CHANNEL_TXDATA54", - "GTXE2_CHANNEL_TXDATA55", - "GTXE2_CHANNEL_TXDATA56", - "GTXE2_CHANNEL_TXDATA57", - "GTXE2_CHANNEL_TXDATA58", - "GTXE2_CHANNEL_TXDATA59", - "GTXE2_CHANNEL_TXDATA6", - "GTXE2_CHANNEL_TXDATA60", - "GTXE2_CHANNEL_TXDATA61", - "GTXE2_CHANNEL_TXDATA62", - "GTXE2_CHANNEL_TXDATA63", - "GTXE2_CHANNEL_TXDATA7", - "GTXE2_CHANNEL_TXDATA8", - "GTXE2_CHANNEL_TXDATA9", - "GTXE2_CHANNEL_TXDEEMPH", - "GTXE2_CHANNEL_TXDETECTRX", - "GTXE2_CHANNEL_TXDIFFCTRL0", - "GTXE2_CHANNEL_TXDIFFCTRL1", - "GTXE2_CHANNEL_TXDIFFCTRL2", - "GTXE2_CHANNEL_TXDIFFCTRL3", - "GTXE2_CHANNEL_TXDIFFPD", - "GTXE2_CHANNEL_TXDLYBYPASS", - "GTXE2_CHANNEL_TXDLYEN", - "GTXE2_CHANNEL_TXDLYHOLD", - "GTXE2_CHANNEL_TXDLYOVRDEN", - "GTXE2_CHANNEL_TXDLYSRESET", - "GTXE2_CHANNEL_TXDLYSRESETDONE", - "GTXE2_CHANNEL_TXDLYTESTENB", - "GTXE2_CHANNEL_TXDLYUPDOWN", - "GTXE2_CHANNEL_TXELECIDLE", - "GTXE2_CHANNEL_TXGEARBOXREADY", - "GTXE2_CHANNEL_TXHEADER0", - "GTXE2_CHANNEL_TXHEADER1", - "GTXE2_CHANNEL_TXHEADER2", - "GTXE2_CHANNEL_TXINHIBIT", - "GTXE2_CHANNEL_TXMAINCURSOR0", - "GTXE2_CHANNEL_TXMAINCURSOR1", - "GTXE2_CHANNEL_TXMAINCURSOR2", - "GTXE2_CHANNEL_TXMAINCURSOR3", - "GTXE2_CHANNEL_TXMAINCURSOR4", - "GTXE2_CHANNEL_TXMAINCURSOR5", - "GTXE2_CHANNEL_TXMAINCURSOR6", - "GTXE2_CHANNEL_TXMARGIN0", - "GTXE2_CHANNEL_TXMARGIN1", - "GTXE2_CHANNEL_TXMARGIN2", - "GTXE2_CHANNEL_TXN", - "GTXE2_CHANNEL_TXN_PAD", - "GTXE2_CHANNEL_TXOUTCLKFABRIC", - "GTXE2_CHANNEL_TXOUTCLKPCS", - "GTXE2_CHANNEL_TXOUTCLKSEL0", - "GTXE2_CHANNEL_TXOUTCLKSEL1", - "GTXE2_CHANNEL_TXOUTCLKSEL2", - "GTXE2_CHANNEL_TXOUTCLK_0", - "GTXE2_CHANNEL_TXOUTCLK_1", - "GTXE2_CHANNEL_TXOUTCLK_2", - "GTXE2_CHANNEL_TXOUTCLK_3", - "GTXE2_CHANNEL_TXP", - "GTXE2_CHANNEL_TXPCSRESET", - "GTXE2_CHANNEL_TXPD0", - "GTXE2_CHANNEL_TXPD1", - "GTXE2_CHANNEL_TXPDELECIDLEMODE", - "GTXE2_CHANNEL_TXPHALIGN", - "GTXE2_CHANNEL_TXPHALIGNDONE", - "GTXE2_CHANNEL_TXPHALIGNEN", - "GTXE2_CHANNEL_TXPHDLYPD", - "GTXE2_CHANNEL_TXPHDLYRESET", - "GTXE2_CHANNEL_TXPHDLYTSTCLK", - "GTXE2_CHANNEL_TXPHINIT", - "GTXE2_CHANNEL_TXPHINITDONE", - "GTXE2_CHANNEL_TXPHOVRDEN", - "GTXE2_CHANNEL_TXPISOPD", - "GTXE2_CHANNEL_TXPMARESET", - "GTXE2_CHANNEL_TXPOLARITY", - "GTXE2_CHANNEL_TXPOSTCURSOR0", - "GTXE2_CHANNEL_TXPOSTCURSOR1", - "GTXE2_CHANNEL_TXPOSTCURSOR2", - "GTXE2_CHANNEL_TXPOSTCURSOR3", - "GTXE2_CHANNEL_TXPOSTCURSOR4", - "GTXE2_CHANNEL_TXPOSTCURSORINV", - "GTXE2_CHANNEL_TXPRBSFORCEERR", - "GTXE2_CHANNEL_TXPRBSSEL0", - "GTXE2_CHANNEL_TXPRBSSEL1", - "GTXE2_CHANNEL_TXPRBSSEL2", - "GTXE2_CHANNEL_TXPRECURSOR0", - "GTXE2_CHANNEL_TXPRECURSOR1", - "GTXE2_CHANNEL_TXPRECURSOR2", - "GTXE2_CHANNEL_TXPRECURSOR3", - "GTXE2_CHANNEL_TXPRECURSOR4", - "GTXE2_CHANNEL_TXPRECURSORINV", - "GTXE2_CHANNEL_TXP_PAD", - "GTXE2_CHANNEL_TXQPIBIASEN", - "GTXE2_CHANNEL_TXQPISENN", - "GTXE2_CHANNEL_TXQPISENP", - "GTXE2_CHANNEL_TXQPISTRONGPDOWN", - "GTXE2_CHANNEL_TXQPIWEAKPUP", - "GTXE2_CHANNEL_TXRATE0", - "GTXE2_CHANNEL_TXRATE1", - "GTXE2_CHANNEL_TXRATE2", - "GTXE2_CHANNEL_TXRATEDONE", - "GTXE2_CHANNEL_TXRESETDONE", - "GTXE2_CHANNEL_TXRUNDISP0", - "GTXE2_CHANNEL_TXRUNDISP1", - "GTXE2_CHANNEL_TXRUNDISP2", - "GTXE2_CHANNEL_TXRUNDISP3", - "GTXE2_CHANNEL_TXRUNDISP4", - "GTXE2_CHANNEL_TXRUNDISP5", - "GTXE2_CHANNEL_TXRUNDISP6", - "GTXE2_CHANNEL_TXRUNDISP7", - "GTXE2_CHANNEL_TXSEQUENCE0", - "GTXE2_CHANNEL_TXSEQUENCE1", - "GTXE2_CHANNEL_TXSEQUENCE2", - "GTXE2_CHANNEL_TXSEQUENCE3", - "GTXE2_CHANNEL_TXSEQUENCE4", - "GTXE2_CHANNEL_TXSEQUENCE5", - "GTXE2_CHANNEL_TXSEQUENCE6", - "GTXE2_CHANNEL_TXSTARTSEQ", - "GTXE2_CHANNEL_TXSWING", - "GTXE2_CHANNEL_TXSYSCLKSEL0", - "GTXE2_CHANNEL_TXSYSCLKSEL1", - "GTXE2_CHANNEL_TXUSERRDY", - "GTXE2_CHANNEL_TXUSRCLK", - "GTXE2_CHANNEL_TXUSRCLK2", - "GTXE2_CLK0_0", - "GTXE2_CLK0_1", - "GTXE2_CLK0_10", - "GTXE2_CLK0_2", - "GTXE2_CLK0_3", - "GTXE2_CLK0_4", - "GTXE2_CLK0_5", - "GTXE2_CLK0_6", - "GTXE2_CLK0_7", - "GTXE2_CLK0_8", - "GTXE2_CLK0_9", - "GTXE2_CLK1_0", - "GTXE2_CLK1_1", - "GTXE2_CLK1_10", - "GTXE2_CLK1_2", - "GTXE2_CLK1_3", - "GTXE2_CLK1_4", - "GTXE2_CLK1_5", - "GTXE2_CLK1_6", - "GTXE2_CLK1_7", - "GTXE2_CLK1_8", - "GTXE2_CLK1_9", - "GTXE2_CTRL0_0", - "GTXE2_CTRL0_1", - "GTXE2_CTRL0_10", - "GTXE2_CTRL0_2", - "GTXE2_CTRL0_3", - "GTXE2_CTRL0_4", - "GTXE2_CTRL0_5", - "GTXE2_CTRL0_6", - "GTXE2_CTRL0_7", - "GTXE2_CTRL0_8", - "GTXE2_CTRL0_9", - "GTXE2_CTRL1_0", - "GTXE2_CTRL1_1", - "GTXE2_CTRL1_10", - "GTXE2_CTRL1_2", - "GTXE2_CTRL1_3", - "GTXE2_CTRL1_4", - "GTXE2_CTRL1_5", - "GTXE2_CTRL1_6", - "GTXE2_CTRL1_7", - "GTXE2_CTRL1_8", - "GTXE2_CTRL1_9", - "GTXE2_FAN0_0", - "GTXE2_FAN0_1", - "GTXE2_FAN0_10", - "GTXE2_FAN0_2", - "GTXE2_FAN0_3", - "GTXE2_FAN0_4", - "GTXE2_FAN0_5", - "GTXE2_FAN0_6", - "GTXE2_FAN0_7", - "GTXE2_FAN0_8", - "GTXE2_FAN0_9", - "GTXE2_FAN1_0", - "GTXE2_FAN1_1", - "GTXE2_FAN1_10", - "GTXE2_FAN1_2", - "GTXE2_FAN1_3", - "GTXE2_FAN1_4", - "GTXE2_FAN1_5", - "GTXE2_FAN1_6", - "GTXE2_FAN1_7", - "GTXE2_FAN1_8", - "GTXE2_FAN1_9", - "GTXE2_FAN2_0", - "GTXE2_FAN2_1", - "GTXE2_FAN2_10", - "GTXE2_FAN2_2", - "GTXE2_FAN2_3", - "GTXE2_FAN2_4", - "GTXE2_FAN2_5", - "GTXE2_FAN2_6", - "GTXE2_FAN2_7", - "GTXE2_FAN2_8", - "GTXE2_FAN2_9", - "GTXE2_FAN3_0", - "GTXE2_FAN3_1", - "GTXE2_FAN3_10", - "GTXE2_FAN3_2", - "GTXE2_FAN3_3", - "GTXE2_FAN3_4", - "GTXE2_FAN3_5", - "GTXE2_FAN3_6", - "GTXE2_FAN3_7", - "GTXE2_FAN3_8", - "GTXE2_FAN3_9", - "GTXE2_FAN4_0", - "GTXE2_FAN4_1", - "GTXE2_FAN4_10", - "GTXE2_FAN4_2", - "GTXE2_FAN4_3", - "GTXE2_FAN4_4", - "GTXE2_FAN4_5", - "GTXE2_FAN4_6", - "GTXE2_FAN4_7", - "GTXE2_FAN4_8", - "GTXE2_FAN4_9", - "GTXE2_FAN5_0", - "GTXE2_FAN5_1", - "GTXE2_FAN5_10", - "GTXE2_FAN5_2", - "GTXE2_FAN5_3", - "GTXE2_FAN5_4", - "GTXE2_FAN5_5", - "GTXE2_FAN5_6", - "GTXE2_FAN5_7", - "GTXE2_FAN5_8", - "GTXE2_FAN5_9", - "GTXE2_FAN6_0", - "GTXE2_FAN6_1", - "GTXE2_FAN6_10", - "GTXE2_FAN6_2", - "GTXE2_FAN6_3", - "GTXE2_FAN6_4", - "GTXE2_FAN6_5", - "GTXE2_FAN6_6", - "GTXE2_FAN6_7", - "GTXE2_FAN6_8", - "GTXE2_FAN6_9", - "GTXE2_FAN7_0", - "GTXE2_FAN7_1", - "GTXE2_FAN7_10", - "GTXE2_FAN7_2", - "GTXE2_FAN7_3", - "GTXE2_FAN7_4", - "GTXE2_FAN7_5", - "GTXE2_FAN7_6", - "GTXE2_FAN7_7", - "GTXE2_FAN7_8", - "GTXE2_FAN7_9", - "GTXE2_IMUX0_0", - "GTXE2_IMUX0_1", - "GTXE2_IMUX0_10", - "GTXE2_IMUX0_2", - "GTXE2_IMUX0_3", - "GTXE2_IMUX0_4", - "GTXE2_IMUX0_5", - "GTXE2_IMUX0_6", - "GTXE2_IMUX0_7", - "GTXE2_IMUX0_8", - "GTXE2_IMUX0_9", - "GTXE2_IMUX10_0", - "GTXE2_IMUX10_1", - "GTXE2_IMUX10_10", - "GTXE2_IMUX10_2", - "GTXE2_IMUX10_3", - "GTXE2_IMUX10_4", - "GTXE2_IMUX10_5", - "GTXE2_IMUX10_6", - "GTXE2_IMUX10_7", - "GTXE2_IMUX10_8", - "GTXE2_IMUX10_9", - "GTXE2_IMUX11_0", - "GTXE2_IMUX11_1", - "GTXE2_IMUX11_10", - "GTXE2_IMUX11_2", - "GTXE2_IMUX11_3", - "GTXE2_IMUX11_4", - "GTXE2_IMUX11_5", - "GTXE2_IMUX11_6", - "GTXE2_IMUX11_7", - "GTXE2_IMUX11_8", - "GTXE2_IMUX11_9", - "GTXE2_IMUX12_0", - "GTXE2_IMUX12_1", - "GTXE2_IMUX12_10", - "GTXE2_IMUX12_2", - "GTXE2_IMUX12_3", - "GTXE2_IMUX12_4", - "GTXE2_IMUX12_5", - "GTXE2_IMUX12_6", - "GTXE2_IMUX12_7", - "GTXE2_IMUX12_8", - "GTXE2_IMUX12_9", - "GTXE2_IMUX13_0", - "GTXE2_IMUX13_1", - "GTXE2_IMUX13_10", - "GTXE2_IMUX13_2", - "GTXE2_IMUX13_3", - "GTXE2_IMUX13_4", - "GTXE2_IMUX13_5", - "GTXE2_IMUX13_6", - "GTXE2_IMUX13_7", - "GTXE2_IMUX13_8", - "GTXE2_IMUX13_9", - "GTXE2_IMUX14_0", - "GTXE2_IMUX14_1", - "GTXE2_IMUX14_10", - "GTXE2_IMUX14_2", - "GTXE2_IMUX14_3", - "GTXE2_IMUX14_4", - "GTXE2_IMUX14_5", - "GTXE2_IMUX14_6", - "GTXE2_IMUX14_7", - "GTXE2_IMUX14_8", - "GTXE2_IMUX14_9", - "GTXE2_IMUX15_0", - "GTXE2_IMUX15_1", - "GTXE2_IMUX15_10", - "GTXE2_IMUX15_2", - "GTXE2_IMUX15_3", - "GTXE2_IMUX15_4", - "GTXE2_IMUX15_5", - "GTXE2_IMUX15_6", - "GTXE2_IMUX15_7", - "GTXE2_IMUX15_8", - "GTXE2_IMUX15_9", - "GTXE2_IMUX16_0", - "GTXE2_IMUX16_1", - "GTXE2_IMUX16_10", - "GTXE2_IMUX16_2", - "GTXE2_IMUX16_3", - "GTXE2_IMUX16_4", - "GTXE2_IMUX16_5", - "GTXE2_IMUX16_6", - "GTXE2_IMUX16_7", - "GTXE2_IMUX16_8", - "GTXE2_IMUX16_9", - "GTXE2_IMUX17_0", - "GTXE2_IMUX17_1", - "GTXE2_IMUX17_10", - "GTXE2_IMUX17_2", - "GTXE2_IMUX17_3", - "GTXE2_IMUX17_4", - "GTXE2_IMUX17_5", - "GTXE2_IMUX17_6", - "GTXE2_IMUX17_7", - "GTXE2_IMUX17_8", - "GTXE2_IMUX17_9", - "GTXE2_IMUX18_0", - "GTXE2_IMUX18_1", - "GTXE2_IMUX18_10", - "GTXE2_IMUX18_2", - "GTXE2_IMUX18_3", - "GTXE2_IMUX18_4", - "GTXE2_IMUX18_5", - "GTXE2_IMUX18_6", - "GTXE2_IMUX18_7", - "GTXE2_IMUX18_8", - "GTXE2_IMUX18_9", - "GTXE2_IMUX19_0", - "GTXE2_IMUX19_1", - "GTXE2_IMUX19_10", - "GTXE2_IMUX19_2", - "GTXE2_IMUX19_3", - "GTXE2_IMUX19_4", - "GTXE2_IMUX19_5", - "GTXE2_IMUX19_6", - "GTXE2_IMUX19_7", - "GTXE2_IMUX19_8", - "GTXE2_IMUX19_9", - "GTXE2_IMUX1_0", - "GTXE2_IMUX1_1", - "GTXE2_IMUX1_10", - "GTXE2_IMUX1_2", - "GTXE2_IMUX1_3", - "GTXE2_IMUX1_4", - "GTXE2_IMUX1_5", - "GTXE2_IMUX1_6", - "GTXE2_IMUX1_7", - "GTXE2_IMUX1_8", - "GTXE2_IMUX1_9", - "GTXE2_IMUX20_0", - "GTXE2_IMUX20_1", - "GTXE2_IMUX20_10", - "GTXE2_IMUX20_2", - "GTXE2_IMUX20_3", - "GTXE2_IMUX20_4", - "GTXE2_IMUX20_5", - "GTXE2_IMUX20_6", - "GTXE2_IMUX20_7", - "GTXE2_IMUX20_8", - "GTXE2_IMUX20_9", - "GTXE2_IMUX21_0", - "GTXE2_IMUX21_1", - "GTXE2_IMUX21_10", - "GTXE2_IMUX21_2", - "GTXE2_IMUX21_3", - "GTXE2_IMUX21_4", - "GTXE2_IMUX21_5", - "GTXE2_IMUX21_6", - "GTXE2_IMUX21_7", - "GTXE2_IMUX21_8", - "GTXE2_IMUX21_9", - "GTXE2_IMUX22_0", - "GTXE2_IMUX22_1", - "GTXE2_IMUX22_10", - "GTXE2_IMUX22_2", - "GTXE2_IMUX22_3", - "GTXE2_IMUX22_4", - "GTXE2_IMUX22_5", - "GTXE2_IMUX22_6", - "GTXE2_IMUX22_7", - "GTXE2_IMUX22_8", - "GTXE2_IMUX22_9", - "GTXE2_IMUX23_0", - "GTXE2_IMUX23_1", - "GTXE2_IMUX23_10", - "GTXE2_IMUX23_2", - "GTXE2_IMUX23_3", - "GTXE2_IMUX23_4", - "GTXE2_IMUX23_5", - "GTXE2_IMUX23_6", - "GTXE2_IMUX23_7", - "GTXE2_IMUX23_8", - "GTXE2_IMUX23_9", - "GTXE2_IMUX24_0", - "GTXE2_IMUX24_1", - "GTXE2_IMUX24_10", - "GTXE2_IMUX24_2", - "GTXE2_IMUX24_3", - "GTXE2_IMUX24_4", - "GTXE2_IMUX24_5", - "GTXE2_IMUX24_6", - "GTXE2_IMUX24_7", - "GTXE2_IMUX24_8", - "GTXE2_IMUX24_9", - "GTXE2_IMUX25_0", - "GTXE2_IMUX25_1", - "GTXE2_IMUX25_10", - "GTXE2_IMUX25_2", - "GTXE2_IMUX25_3", - "GTXE2_IMUX25_4", - "GTXE2_IMUX25_5", - "GTXE2_IMUX25_6", - "GTXE2_IMUX25_7", - "GTXE2_IMUX25_8", - "GTXE2_IMUX25_9", - "GTXE2_IMUX26_0", - "GTXE2_IMUX26_1", - "GTXE2_IMUX26_10", - "GTXE2_IMUX26_2", - "GTXE2_IMUX26_3", - "GTXE2_IMUX26_4", - "GTXE2_IMUX26_5", - "GTXE2_IMUX26_6", - "GTXE2_IMUX26_7", - "GTXE2_IMUX26_8", - "GTXE2_IMUX26_9", - "GTXE2_IMUX27_0", - "GTXE2_IMUX27_1", - "GTXE2_IMUX27_10", - "GTXE2_IMUX27_2", - "GTXE2_IMUX27_3", - "GTXE2_IMUX27_4", - "GTXE2_IMUX27_5", - "GTXE2_IMUX27_6", - "GTXE2_IMUX27_7", - "GTXE2_IMUX27_8", - "GTXE2_IMUX27_9", - "GTXE2_IMUX28_0", - "GTXE2_IMUX28_1", - "GTXE2_IMUX28_10", - "GTXE2_IMUX28_2", - "GTXE2_IMUX28_3", - "GTXE2_IMUX28_4", - "GTXE2_IMUX28_5", - "GTXE2_IMUX28_6", - "GTXE2_IMUX28_7", - "GTXE2_IMUX28_8", - "GTXE2_IMUX28_9", - "GTXE2_IMUX29_0", - "GTXE2_IMUX29_1", - "GTXE2_IMUX29_10", - "GTXE2_IMUX29_2", - "GTXE2_IMUX29_3", - "GTXE2_IMUX29_4", - "GTXE2_IMUX29_5", - "GTXE2_IMUX29_6", - "GTXE2_IMUX29_7", - "GTXE2_IMUX29_8", - "GTXE2_IMUX29_9", - "GTXE2_IMUX2_0", - "GTXE2_IMUX2_1", - "GTXE2_IMUX2_10", - "GTXE2_IMUX2_2", - "GTXE2_IMUX2_3", - "GTXE2_IMUX2_4", - "GTXE2_IMUX2_5", - "GTXE2_IMUX2_6", - "GTXE2_IMUX2_7", - "GTXE2_IMUX2_8", - "GTXE2_IMUX2_9", - "GTXE2_IMUX30_0", - "GTXE2_IMUX30_1", - "GTXE2_IMUX30_10", - "GTXE2_IMUX30_2", - "GTXE2_IMUX30_3", - "GTXE2_IMUX30_4", - "GTXE2_IMUX30_5", - "GTXE2_IMUX30_6", - "GTXE2_IMUX30_7", - "GTXE2_IMUX30_8", - "GTXE2_IMUX30_9", - "GTXE2_IMUX31_0", - "GTXE2_IMUX31_1", - "GTXE2_IMUX31_10", - "GTXE2_IMUX31_2", - "GTXE2_IMUX31_3", - "GTXE2_IMUX31_4", - "GTXE2_IMUX31_5", - "GTXE2_IMUX31_6", - "GTXE2_IMUX31_7", - "GTXE2_IMUX31_8", - "GTXE2_IMUX31_9", - "GTXE2_IMUX32_0", - "GTXE2_IMUX32_1", - "GTXE2_IMUX32_10", - "GTXE2_IMUX32_2", - "GTXE2_IMUX32_3", - "GTXE2_IMUX32_4", - "GTXE2_IMUX32_5", - "GTXE2_IMUX32_6", - "GTXE2_IMUX32_7", - "GTXE2_IMUX32_8", - "GTXE2_IMUX32_9", - "GTXE2_IMUX33_0", - "GTXE2_IMUX33_1", - "GTXE2_IMUX33_10", - "GTXE2_IMUX33_2", - "GTXE2_IMUX33_3", - "GTXE2_IMUX33_4", - "GTXE2_IMUX33_5", - "GTXE2_IMUX33_6", - "GTXE2_IMUX33_7", - "GTXE2_IMUX33_8", - "GTXE2_IMUX33_9", - "GTXE2_IMUX34_0", - "GTXE2_IMUX34_1", - "GTXE2_IMUX34_10", - "GTXE2_IMUX34_2", - "GTXE2_IMUX34_3", - "GTXE2_IMUX34_4", - "GTXE2_IMUX34_5", - "GTXE2_IMUX34_6", - "GTXE2_IMUX34_7", - "GTXE2_IMUX34_8", - "GTXE2_IMUX34_9", - "GTXE2_IMUX35_0", - "GTXE2_IMUX35_1", - "GTXE2_IMUX35_10", - "GTXE2_IMUX35_2", - "GTXE2_IMUX35_3", - "GTXE2_IMUX35_4", - "GTXE2_IMUX35_5", - "GTXE2_IMUX35_6", - "GTXE2_IMUX35_7", - "GTXE2_IMUX35_8", - "GTXE2_IMUX35_9", - "GTXE2_IMUX36_0", - "GTXE2_IMUX36_1", - "GTXE2_IMUX36_10", - "GTXE2_IMUX36_2", - "GTXE2_IMUX36_3", - "GTXE2_IMUX36_4", - "GTXE2_IMUX36_5", - "GTXE2_IMUX36_6", - "GTXE2_IMUX36_7", - "GTXE2_IMUX36_8", - "GTXE2_IMUX36_9", - "GTXE2_IMUX37_0", - "GTXE2_IMUX37_1", - "GTXE2_IMUX37_10", - "GTXE2_IMUX37_2", - "GTXE2_IMUX37_3", - "GTXE2_IMUX37_4", - "GTXE2_IMUX37_5", - "GTXE2_IMUX37_6", - "GTXE2_IMUX37_7", - "GTXE2_IMUX37_8", - "GTXE2_IMUX37_9", - "GTXE2_IMUX38_0", - "GTXE2_IMUX38_1", - "GTXE2_IMUX38_10", - "GTXE2_IMUX38_2", - "GTXE2_IMUX38_3", - "GTXE2_IMUX38_4", - "GTXE2_IMUX38_5", - "GTXE2_IMUX38_6", - "GTXE2_IMUX38_7", - "GTXE2_IMUX38_8", - "GTXE2_IMUX38_9", - "GTXE2_IMUX39_0", - "GTXE2_IMUX39_1", - "GTXE2_IMUX39_10", - "GTXE2_IMUX39_2", - "GTXE2_IMUX39_3", - "GTXE2_IMUX39_4", - "GTXE2_IMUX39_5", - "GTXE2_IMUX39_6", - "GTXE2_IMUX39_7", - "GTXE2_IMUX39_8", - "GTXE2_IMUX39_9", - "GTXE2_IMUX3_0", - "GTXE2_IMUX3_1", - "GTXE2_IMUX3_10", - "GTXE2_IMUX3_2", - "GTXE2_IMUX3_3", - "GTXE2_IMUX3_4", - "GTXE2_IMUX3_5", - "GTXE2_IMUX3_6", - "GTXE2_IMUX3_7", - "GTXE2_IMUX3_8", - "GTXE2_IMUX3_9", - "GTXE2_IMUX40_0", - "GTXE2_IMUX40_1", - "GTXE2_IMUX40_10", - "GTXE2_IMUX40_2", - "GTXE2_IMUX40_3", - "GTXE2_IMUX40_4", - "GTXE2_IMUX40_5", - "GTXE2_IMUX40_6", - "GTXE2_IMUX40_7", - "GTXE2_IMUX40_8", - "GTXE2_IMUX40_9", - "GTXE2_IMUX41_0", - "GTXE2_IMUX41_1", - "GTXE2_IMUX41_10", - "GTXE2_IMUX41_2", - "GTXE2_IMUX41_3", - "GTXE2_IMUX41_4", - "GTXE2_IMUX41_5", - "GTXE2_IMUX41_6", - "GTXE2_IMUX41_7", - "GTXE2_IMUX41_8", - "GTXE2_IMUX41_9", - "GTXE2_IMUX42_0", - "GTXE2_IMUX42_1", - "GTXE2_IMUX42_10", - "GTXE2_IMUX42_2", - "GTXE2_IMUX42_3", - "GTXE2_IMUX42_4", - "GTXE2_IMUX42_5", - "GTXE2_IMUX42_6", - "GTXE2_IMUX42_7", - "GTXE2_IMUX42_8", - "GTXE2_IMUX42_9", - "GTXE2_IMUX43_0", - "GTXE2_IMUX43_1", - "GTXE2_IMUX43_10", - "GTXE2_IMUX43_2", - "GTXE2_IMUX43_3", - "GTXE2_IMUX43_4", - "GTXE2_IMUX43_5", - "GTXE2_IMUX43_6", - "GTXE2_IMUX43_7", - "GTXE2_IMUX43_8", - "GTXE2_IMUX43_9", - "GTXE2_IMUX44_0", - "GTXE2_IMUX44_1", - "GTXE2_IMUX44_10", - "GTXE2_IMUX44_2", - "GTXE2_IMUX44_3", - "GTXE2_IMUX44_4", - "GTXE2_IMUX44_5", - "GTXE2_IMUX44_6", - "GTXE2_IMUX44_7", - "GTXE2_IMUX44_8", - "GTXE2_IMUX44_9", - "GTXE2_IMUX45_0", - "GTXE2_IMUX45_1", - "GTXE2_IMUX45_10", - "GTXE2_IMUX45_2", - "GTXE2_IMUX45_3", - "GTXE2_IMUX45_4", - "GTXE2_IMUX45_5", - "GTXE2_IMUX45_6", - "GTXE2_IMUX45_7", - "GTXE2_IMUX45_8", - "GTXE2_IMUX45_9", - "GTXE2_IMUX46_0", - "GTXE2_IMUX46_1", - "GTXE2_IMUX46_10", - "GTXE2_IMUX46_2", - "GTXE2_IMUX46_3", - "GTXE2_IMUX46_4", - "GTXE2_IMUX46_5", - "GTXE2_IMUX46_6", - "GTXE2_IMUX46_7", - "GTXE2_IMUX46_8", - "GTXE2_IMUX46_9", - "GTXE2_IMUX47_0", - "GTXE2_IMUX47_1", - "GTXE2_IMUX47_10", - "GTXE2_IMUX47_2", - "GTXE2_IMUX47_3", - "GTXE2_IMUX47_4", - "GTXE2_IMUX47_5", - "GTXE2_IMUX47_6", - "GTXE2_IMUX47_7", - "GTXE2_IMUX47_8", - "GTXE2_IMUX47_9", - "GTXE2_IMUX4_0", - "GTXE2_IMUX4_1", - "GTXE2_IMUX4_10", - "GTXE2_IMUX4_2", - "GTXE2_IMUX4_3", - "GTXE2_IMUX4_4", - "GTXE2_IMUX4_5", - "GTXE2_IMUX4_6", - "GTXE2_IMUX4_7", - "GTXE2_IMUX4_8", - "GTXE2_IMUX4_9", - "GTXE2_IMUX5_0", - "GTXE2_IMUX5_1", - "GTXE2_IMUX5_10", - "GTXE2_IMUX5_2", - "GTXE2_IMUX5_3", - "GTXE2_IMUX5_4", - "GTXE2_IMUX5_5", - "GTXE2_IMUX5_6", - "GTXE2_IMUX5_7", - "GTXE2_IMUX5_8", - "GTXE2_IMUX5_9", - "GTXE2_IMUX6_0", - "GTXE2_IMUX6_1", - "GTXE2_IMUX6_10", - "GTXE2_IMUX6_2", - "GTXE2_IMUX6_3", - "GTXE2_IMUX6_4", - "GTXE2_IMUX6_5", - "GTXE2_IMUX6_6", - "GTXE2_IMUX6_7", - "GTXE2_IMUX6_8", - "GTXE2_IMUX6_9", - "GTXE2_IMUX7_0", - "GTXE2_IMUX7_1", - "GTXE2_IMUX7_10", - "GTXE2_IMUX7_2", - "GTXE2_IMUX7_3", - "GTXE2_IMUX7_4", - "GTXE2_IMUX7_5", - "GTXE2_IMUX7_6", - "GTXE2_IMUX7_7", - "GTXE2_IMUX7_8", - "GTXE2_IMUX7_9", - "GTXE2_IMUX8_0", - "GTXE2_IMUX8_1", - "GTXE2_IMUX8_10", - "GTXE2_IMUX8_2", - "GTXE2_IMUX8_3", - "GTXE2_IMUX8_4", - "GTXE2_IMUX8_5", - "GTXE2_IMUX8_6", - "GTXE2_IMUX8_7", - "GTXE2_IMUX8_8", - "GTXE2_IMUX8_9", - "GTXE2_IMUX9_0", - "GTXE2_IMUX9_1", - "GTXE2_IMUX9_10", - "GTXE2_IMUX9_2", - "GTXE2_IMUX9_3", - "GTXE2_IMUX9_4", - "GTXE2_IMUX9_5", - "GTXE2_IMUX9_6", - "GTXE2_IMUX9_7", - "GTXE2_IMUX9_8", - "GTXE2_IMUX9_9", - "GTXE2_LOGIC_OUTS_B0_0", - "GTXE2_LOGIC_OUTS_B0_1", - "GTXE2_LOGIC_OUTS_B0_10", - "GTXE2_LOGIC_OUTS_B0_2", - "GTXE2_LOGIC_OUTS_B0_3", - "GTXE2_LOGIC_OUTS_B0_4", - "GTXE2_LOGIC_OUTS_B0_5", - "GTXE2_LOGIC_OUTS_B0_6", - "GTXE2_LOGIC_OUTS_B0_7", - "GTXE2_LOGIC_OUTS_B0_8", - "GTXE2_LOGIC_OUTS_B0_9", - "GTXE2_LOGIC_OUTS_B10_0", - "GTXE2_LOGIC_OUTS_B10_1", - "GTXE2_LOGIC_OUTS_B10_10", - "GTXE2_LOGIC_OUTS_B10_2", - "GTXE2_LOGIC_OUTS_B10_3", - "GTXE2_LOGIC_OUTS_B10_4", - "GTXE2_LOGIC_OUTS_B10_5", - "GTXE2_LOGIC_OUTS_B10_6", - "GTXE2_LOGIC_OUTS_B10_7", - "GTXE2_LOGIC_OUTS_B10_8", - "GTXE2_LOGIC_OUTS_B10_9", - "GTXE2_LOGIC_OUTS_B11_0", - "GTXE2_LOGIC_OUTS_B11_1", - "GTXE2_LOGIC_OUTS_B11_10", - "GTXE2_LOGIC_OUTS_B11_2", - "GTXE2_LOGIC_OUTS_B11_3", - "GTXE2_LOGIC_OUTS_B11_4", - "GTXE2_LOGIC_OUTS_B11_5", - "GTXE2_LOGIC_OUTS_B11_6", - "GTXE2_LOGIC_OUTS_B11_7", - "GTXE2_LOGIC_OUTS_B11_8", - "GTXE2_LOGIC_OUTS_B11_9", - "GTXE2_LOGIC_OUTS_B12_0", - "GTXE2_LOGIC_OUTS_B12_1", - "GTXE2_LOGIC_OUTS_B12_10", - "GTXE2_LOGIC_OUTS_B12_2", - "GTXE2_LOGIC_OUTS_B12_3", - "GTXE2_LOGIC_OUTS_B12_4", - "GTXE2_LOGIC_OUTS_B12_5", - "GTXE2_LOGIC_OUTS_B12_6", - "GTXE2_LOGIC_OUTS_B12_7", - "GTXE2_LOGIC_OUTS_B12_8", - "GTXE2_LOGIC_OUTS_B12_9", - "GTXE2_LOGIC_OUTS_B13_0", - "GTXE2_LOGIC_OUTS_B13_1", - "GTXE2_LOGIC_OUTS_B13_10", - "GTXE2_LOGIC_OUTS_B13_2", - "GTXE2_LOGIC_OUTS_B13_3", - "GTXE2_LOGIC_OUTS_B13_4", - "GTXE2_LOGIC_OUTS_B13_5", - "GTXE2_LOGIC_OUTS_B13_6", - "GTXE2_LOGIC_OUTS_B13_7", - "GTXE2_LOGIC_OUTS_B13_8", - "GTXE2_LOGIC_OUTS_B13_9", - "GTXE2_LOGIC_OUTS_B14_0", - "GTXE2_LOGIC_OUTS_B14_1", - "GTXE2_LOGIC_OUTS_B14_10", - "GTXE2_LOGIC_OUTS_B14_2", - "GTXE2_LOGIC_OUTS_B14_3", - "GTXE2_LOGIC_OUTS_B14_4", - "GTXE2_LOGIC_OUTS_B14_5", - "GTXE2_LOGIC_OUTS_B14_6", - "GTXE2_LOGIC_OUTS_B14_7", - "GTXE2_LOGIC_OUTS_B14_8", - "GTXE2_LOGIC_OUTS_B14_9", - "GTXE2_LOGIC_OUTS_B15_0", - "GTXE2_LOGIC_OUTS_B15_1", - "GTXE2_LOGIC_OUTS_B15_10", - "GTXE2_LOGIC_OUTS_B15_2", - "GTXE2_LOGIC_OUTS_B15_3", - "GTXE2_LOGIC_OUTS_B15_4", - "GTXE2_LOGIC_OUTS_B15_5", - "GTXE2_LOGIC_OUTS_B15_6", - "GTXE2_LOGIC_OUTS_B15_7", - "GTXE2_LOGIC_OUTS_B15_8", - "GTXE2_LOGIC_OUTS_B15_9", - "GTXE2_LOGIC_OUTS_B16_0", - "GTXE2_LOGIC_OUTS_B16_1", - "GTXE2_LOGIC_OUTS_B16_10", - "GTXE2_LOGIC_OUTS_B16_2", - "GTXE2_LOGIC_OUTS_B16_3", - "GTXE2_LOGIC_OUTS_B16_4", - "GTXE2_LOGIC_OUTS_B16_5", - "GTXE2_LOGIC_OUTS_B16_6", - "GTXE2_LOGIC_OUTS_B16_7", - "GTXE2_LOGIC_OUTS_B16_8", - "GTXE2_LOGIC_OUTS_B16_9", - "GTXE2_LOGIC_OUTS_B17_0", - "GTXE2_LOGIC_OUTS_B17_1", - "GTXE2_LOGIC_OUTS_B17_10", - "GTXE2_LOGIC_OUTS_B17_2", - "GTXE2_LOGIC_OUTS_B17_3", - "GTXE2_LOGIC_OUTS_B17_4", - "GTXE2_LOGIC_OUTS_B17_5", - "GTXE2_LOGIC_OUTS_B17_6", - "GTXE2_LOGIC_OUTS_B17_7", - "GTXE2_LOGIC_OUTS_B17_8", - "GTXE2_LOGIC_OUTS_B17_9", - "GTXE2_LOGIC_OUTS_B18_0", - "GTXE2_LOGIC_OUTS_B18_1", - "GTXE2_LOGIC_OUTS_B18_10", - "GTXE2_LOGIC_OUTS_B18_2", - "GTXE2_LOGIC_OUTS_B18_3", - "GTXE2_LOGIC_OUTS_B18_4", - "GTXE2_LOGIC_OUTS_B18_5", - "GTXE2_LOGIC_OUTS_B18_6", - "GTXE2_LOGIC_OUTS_B18_7", - "GTXE2_LOGIC_OUTS_B18_8", - "GTXE2_LOGIC_OUTS_B18_9", - "GTXE2_LOGIC_OUTS_B19_0", - "GTXE2_LOGIC_OUTS_B19_1", - "GTXE2_LOGIC_OUTS_B19_10", - "GTXE2_LOGIC_OUTS_B19_2", - "GTXE2_LOGIC_OUTS_B19_3", - "GTXE2_LOGIC_OUTS_B19_4", - "GTXE2_LOGIC_OUTS_B19_5", - "GTXE2_LOGIC_OUTS_B19_6", - "GTXE2_LOGIC_OUTS_B19_7", - "GTXE2_LOGIC_OUTS_B19_8", - "GTXE2_LOGIC_OUTS_B19_9", - "GTXE2_LOGIC_OUTS_B1_0", - "GTXE2_LOGIC_OUTS_B1_1", - "GTXE2_LOGIC_OUTS_B1_10", - "GTXE2_LOGIC_OUTS_B1_2", - "GTXE2_LOGIC_OUTS_B1_3", - "GTXE2_LOGIC_OUTS_B1_4", - "GTXE2_LOGIC_OUTS_B1_5", - "GTXE2_LOGIC_OUTS_B1_6", - "GTXE2_LOGIC_OUTS_B1_7", - "GTXE2_LOGIC_OUTS_B1_8", - "GTXE2_LOGIC_OUTS_B1_9", - "GTXE2_LOGIC_OUTS_B20_0", - "GTXE2_LOGIC_OUTS_B20_1", - "GTXE2_LOGIC_OUTS_B20_10", - "GTXE2_LOGIC_OUTS_B20_2", - "GTXE2_LOGIC_OUTS_B20_3", - "GTXE2_LOGIC_OUTS_B20_4", - "GTXE2_LOGIC_OUTS_B20_5", - "GTXE2_LOGIC_OUTS_B20_6", - "GTXE2_LOGIC_OUTS_B20_7", - "GTXE2_LOGIC_OUTS_B20_8", - "GTXE2_LOGIC_OUTS_B20_9", - "GTXE2_LOGIC_OUTS_B21_0", - "GTXE2_LOGIC_OUTS_B21_1", - "GTXE2_LOGIC_OUTS_B21_10", - "GTXE2_LOGIC_OUTS_B21_2", - "GTXE2_LOGIC_OUTS_B21_3", - "GTXE2_LOGIC_OUTS_B21_4", - "GTXE2_LOGIC_OUTS_B21_5", - "GTXE2_LOGIC_OUTS_B21_6", - "GTXE2_LOGIC_OUTS_B21_7", - "GTXE2_LOGIC_OUTS_B21_8", - "GTXE2_LOGIC_OUTS_B21_9", - "GTXE2_LOGIC_OUTS_B22_0", - "GTXE2_LOGIC_OUTS_B22_1", - "GTXE2_LOGIC_OUTS_B22_10", - "GTXE2_LOGIC_OUTS_B22_2", - "GTXE2_LOGIC_OUTS_B22_3", - "GTXE2_LOGIC_OUTS_B22_4", - "GTXE2_LOGIC_OUTS_B22_5", - "GTXE2_LOGIC_OUTS_B22_6", - "GTXE2_LOGIC_OUTS_B22_7", - "GTXE2_LOGIC_OUTS_B22_8", - "GTXE2_LOGIC_OUTS_B22_9", - "GTXE2_LOGIC_OUTS_B23_0", - "GTXE2_LOGIC_OUTS_B23_1", - "GTXE2_LOGIC_OUTS_B23_10", - "GTXE2_LOGIC_OUTS_B23_2", - "GTXE2_LOGIC_OUTS_B23_3", - "GTXE2_LOGIC_OUTS_B23_4", - "GTXE2_LOGIC_OUTS_B23_5", - "GTXE2_LOGIC_OUTS_B23_6", - "GTXE2_LOGIC_OUTS_B23_7", - "GTXE2_LOGIC_OUTS_B23_8", - "GTXE2_LOGIC_OUTS_B23_9", - "GTXE2_LOGIC_OUTS_B2_0", - "GTXE2_LOGIC_OUTS_B2_1", - "GTXE2_LOGIC_OUTS_B2_10", - "GTXE2_LOGIC_OUTS_B2_2", - "GTXE2_LOGIC_OUTS_B2_3", - "GTXE2_LOGIC_OUTS_B2_4", - "GTXE2_LOGIC_OUTS_B2_5", - "GTXE2_LOGIC_OUTS_B2_6", - "GTXE2_LOGIC_OUTS_B2_7", - "GTXE2_LOGIC_OUTS_B2_8", - "GTXE2_LOGIC_OUTS_B2_9", - "GTXE2_LOGIC_OUTS_B3_0", - "GTXE2_LOGIC_OUTS_B3_1", - "GTXE2_LOGIC_OUTS_B3_10", - "GTXE2_LOGIC_OUTS_B3_2", - "GTXE2_LOGIC_OUTS_B3_3", - "GTXE2_LOGIC_OUTS_B3_4", - "GTXE2_LOGIC_OUTS_B3_5", - "GTXE2_LOGIC_OUTS_B3_6", - "GTXE2_LOGIC_OUTS_B3_7", - "GTXE2_LOGIC_OUTS_B3_8", - "GTXE2_LOGIC_OUTS_B3_9", - "GTXE2_LOGIC_OUTS_B4_0", - "GTXE2_LOGIC_OUTS_B4_1", - "GTXE2_LOGIC_OUTS_B4_10", - "GTXE2_LOGIC_OUTS_B4_2", - "GTXE2_LOGIC_OUTS_B4_3", - "GTXE2_LOGIC_OUTS_B4_4", - "GTXE2_LOGIC_OUTS_B4_5", - "GTXE2_LOGIC_OUTS_B4_6", - "GTXE2_LOGIC_OUTS_B4_7", - "GTXE2_LOGIC_OUTS_B4_8", - "GTXE2_LOGIC_OUTS_B4_9", - "GTXE2_LOGIC_OUTS_B5_0", - "GTXE2_LOGIC_OUTS_B5_1", - "GTXE2_LOGIC_OUTS_B5_10", - "GTXE2_LOGIC_OUTS_B5_2", - "GTXE2_LOGIC_OUTS_B5_3", - "GTXE2_LOGIC_OUTS_B5_4", - "GTXE2_LOGIC_OUTS_B5_5", - "GTXE2_LOGIC_OUTS_B5_6", - "GTXE2_LOGIC_OUTS_B5_7", - "GTXE2_LOGIC_OUTS_B5_8", - "GTXE2_LOGIC_OUTS_B5_9", - "GTXE2_LOGIC_OUTS_B6_0", - "GTXE2_LOGIC_OUTS_B6_1", - "GTXE2_LOGIC_OUTS_B6_10", - "GTXE2_LOGIC_OUTS_B6_2", - "GTXE2_LOGIC_OUTS_B6_3", - "GTXE2_LOGIC_OUTS_B6_4", - "GTXE2_LOGIC_OUTS_B6_5", - "GTXE2_LOGIC_OUTS_B6_6", - "GTXE2_LOGIC_OUTS_B6_7", - "GTXE2_LOGIC_OUTS_B6_8", - "GTXE2_LOGIC_OUTS_B6_9", - "GTXE2_LOGIC_OUTS_B7_0", - "GTXE2_LOGIC_OUTS_B7_1", - "GTXE2_LOGIC_OUTS_B7_10", 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"GTXE2_LOGIC_OUTS_B6_7": null, + "GTXE2_LOGIC_OUTS_B6_8": null, + "GTXE2_LOGIC_OUTS_B6_9": null, + "GTXE2_LOGIC_OUTS_B7_0": null, + "GTXE2_LOGIC_OUTS_B7_1": null, + "GTXE2_LOGIC_OUTS_B7_10": null, + "GTXE2_LOGIC_OUTS_B7_2": null, + "GTXE2_LOGIC_OUTS_B7_3": null, + "GTXE2_LOGIC_OUTS_B7_4": null, + "GTXE2_LOGIC_OUTS_B7_5": null, + "GTXE2_LOGIC_OUTS_B7_6": null, + "GTXE2_LOGIC_OUTS_B7_7": null, + "GTXE2_LOGIC_OUTS_B7_8": null, + "GTXE2_LOGIC_OUTS_B7_9": null, + "GTXE2_LOGIC_OUTS_B8_0": null, + "GTXE2_LOGIC_OUTS_B8_1": null, + "GTXE2_LOGIC_OUTS_B8_10": null, + "GTXE2_LOGIC_OUTS_B8_2": null, + "GTXE2_LOGIC_OUTS_B8_3": null, + "GTXE2_LOGIC_OUTS_B8_4": null, + "GTXE2_LOGIC_OUTS_B8_5": null, + "GTXE2_LOGIC_OUTS_B8_6": null, + "GTXE2_LOGIC_OUTS_B8_7": null, + "GTXE2_LOGIC_OUTS_B8_8": null, + "GTXE2_LOGIC_OUTS_B8_9": null, + "GTXE2_LOGIC_OUTS_B9_0": null, + "GTXE2_LOGIC_OUTS_B9_1": null, + "GTXE2_LOGIC_OUTS_B9_10": null, + "GTXE2_LOGIC_OUTS_B9_2": null, + "GTXE2_LOGIC_OUTS_B9_3": null, + "GTXE2_LOGIC_OUTS_B9_4": null, + "GTXE2_LOGIC_OUTS_B9_5": null, + "GTXE2_LOGIC_OUTS_B9_6": null, + "GTXE2_LOGIC_OUTS_B9_7": null, + "GTXE2_LOGIC_OUTS_B9_8": null, + "GTXE2_LOGIC_OUTS_B9_9": null + } } diff --git a/kintex7/tile_type_GTX_CHANNEL_2.json b/kintex7/tile_type_GTX_CHANNEL_2.json index 7fa128e..1c64882 100644 --- a/kintex7/tile_type_GTX_CHANNEL_2.json +++ b/kintex7/tile_type_GTX_CHANNEL_2.json @@ -2,4398 +2,11306 @@ "pips": { "GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLFBCLKLOST" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLLOCK->GTXE2_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLLOCK" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_CPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLREFCLKLOST" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT0->GTXE2_LOGIC_OUTS_B9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT1->GTXE2_LOGIC_OUTS_B9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT2->GTXE2_LOGIC_OUTS_B9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT3->GTXE2_LOGIC_OUTS_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT4->GTXE2_LOGIC_OUTS_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT5->GTXE2_LOGIC_OUTS_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT6->GTXE2_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DMONITOROUT7->GTXE2_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT7" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO0->GTXE2_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO1->GTXE2_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO10->GTXE2_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO10" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO11->GTXE2_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO11" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO12->GTXE2_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO12" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO13->GTXE2_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO13" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO14->GTXE2_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO14" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO15->GTXE2_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO15" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO2->GTXE2_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO3->GTXE2_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO4->GTXE2_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO5->GTXE2_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO6->GTXE2_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO7->GTXE2_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO7" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO8->GTXE2_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO8" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPDO9->GTXE2_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO9" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_DRPRDY->GTXE2_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPRDY" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_EYESCANDATAERROR->GTXE2_LOGIC_OUTS_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_EYESCANDATAERROR" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_GTREFCLKMONITOR->GTXE2_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTREFCLKMONITOR" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_GTRXOUTCLK_2->GTXE2_CHANNEL_RXOUTCLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLK_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTRXOUTCLK_2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_GTTXOUTCLK_2->GTXE2_CHANNEL_TXOUTCLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLK_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTTXOUTCLK_2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_NORTHREFCLK0->GTXE2_CHANNEL_GTNORTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_NORTHREFCLK0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_NORTHREFCLK1->GTXE2_CHANNEL_GTNORTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_NORTHREFCLK1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT0->GTXE2_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT1->GTXE2_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT10->GTXE2_LOGIC_OUTS_B13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT10" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT11->GTXE2_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT11" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT12->GTXE2_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT12" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT13->GTXE2_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT13" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT14->GTXE2_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT14" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT15->GTXE2_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT15" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT2->GTXE2_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT3->GTXE2_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT4->GTXE2_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT5->GTXE2_LOGIC_OUTS_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT6->GTXE2_LOGIC_OUTS_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT7->GTXE2_LOGIC_OUTS_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT7" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT8->GTXE2_LOGIC_OUTS_B13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT8" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PCSRSVDOUT9->GTXE2_LOGIC_OUTS_B13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT9" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_PHYSTATUS->GTXE2_LOGIC_OUTS_B10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PHYSTATUS" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_QPLLCLK->GTXE2_CHANNEL_GTQPLLCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTQPLLCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_QPLLCLK" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_QPLLREFCLK->GTXE2_CHANNEL_GTQPLLREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTQPLLREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_QPLLREFCLK" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_REFCLK0->GTXE2_CHANNEL_GTREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_REFCLK0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_REFCLK1->GTXE2_CHANNEL_GTREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_REFCLK1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBUFSTATUS0->GTXE2_LOGIC_OUTS_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBUFSTATUS1->GTXE2_LOGIC_OUTS_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBUFSTATUS2->GTXE2_LOGIC_OUTS_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBYTEISALIGNED->GTXE2_LOGIC_OUTS_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBYTEISALIGNED" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXBYTEREALIGN->GTXE2_LOGIC_OUTS_B10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBYTEREALIGN" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCDRLOCK->GTXE2_LOGIC_OUTS_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCDRLOCK" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHANBONDSEQ->GTXE2_LOGIC_OUTS_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANBONDSEQ" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHANISALIGNED->GTXE2_LOGIC_OUTS_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANISALIGNED" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHANREALIGN->GTXE2_LOGIC_OUTS_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANREALIGN" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA0->GTXE2_LOGIC_OUTS_B15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA1->GTXE2_LOGIC_OUTS_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA2->GTXE2_LOGIC_OUTS_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA3->GTXE2_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA4->GTXE2_LOGIC_OUTS_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA5->GTXE2_LOGIC_OUTS_B15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA6->GTXE2_LOGIC_OUTS_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISCOMMA7->GTXE2_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA7" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK0->GTXE2_LOGIC_OUTS_B12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK1->GTXE2_LOGIC_OUTS_B12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK2->GTXE2_LOGIC_OUTS_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK3->GTXE2_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK4->GTXE2_LOGIC_OUTS_B12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK5->GTXE2_LOGIC_OUTS_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK6->GTXE2_LOGIC_OUTS_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHARISK7->GTXE2_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK7" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO0->GTXE2_LOGIC_OUTS_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO1->GTXE2_LOGIC_OUTS_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO2->GTXE2_LOGIC_OUTS_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO3->GTXE2_LOGIC_OUTS_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCHBONDO4->GTXE2_LOGIC_OUTS_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCLKCORCNT0->GTXE2_LOGIC_OUTS_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCLKCORCNT1->GTXE2_LOGIC_OUTS_B20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCOMINITDET->GTXE2_LOGIC_OUTS_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMINITDET" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCOMMADET->GTXE2_LOGIC_OUTS_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMMADET" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCOMSASDET->GTXE2_LOGIC_OUTS_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMSASDET" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXCOMWAKEDET->GTXE2_LOGIC_OUTS_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMWAKEDET" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA0->GTXE2_LOGIC_OUTS_B6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA1->GTXE2_LOGIC_OUTS_B2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA10->GTXE2_LOGIC_OUTS_B4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA10" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA11->GTXE2_LOGIC_OUTS_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA11" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA12->GTXE2_LOGIC_OUTS_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA12" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA13->GTXE2_LOGIC_OUTS_B7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA13" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA14->GTXE2_LOGIC_OUTS_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA14" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA15->GTXE2_LOGIC_OUTS_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA15" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA16->GTXE2_LOGIC_OUTS_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA16" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA17->GTXE2_LOGIC_OUTS_B2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA17" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA18->GTXE2_LOGIC_OUTS_B4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA18" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA19->GTXE2_LOGIC_OUTS_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA19" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA2->GTXE2_LOGIC_OUTS_B4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA20->GTXE2_LOGIC_OUTS_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA20" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA21->GTXE2_LOGIC_OUTS_B7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA21" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA22->GTXE2_LOGIC_OUTS_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA22" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA23->GTXE2_LOGIC_OUTS_B5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA23" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA24->GTXE2_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA24" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA25->GTXE2_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA25" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA26->GTXE2_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA26" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA27->GTXE2_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA27" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA28->GTXE2_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA28" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA29->GTXE2_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA29" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA3->GTXE2_LOGIC_OUTS_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA30->GTXE2_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA30" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA31->GTXE2_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA31" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA32->GTXE2_LOGIC_OUTS_B3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA32" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA33->GTXE2_LOGIC_OUTS_B7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA33" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA34->GTXE2_LOGIC_OUTS_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA34" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA35->GTXE2_LOGIC_OUTS_B5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA35" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA36->GTXE2_LOGIC_OUTS_B6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA36" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA37->GTXE2_LOGIC_OUTS_B2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA37" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA38->GTXE2_LOGIC_OUTS_B4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA38" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA39->GTXE2_LOGIC_OUTS_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA39" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA4->GTXE2_LOGIC_OUTS_B3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA40->GTXE2_LOGIC_OUTS_B3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA40" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA41->GTXE2_LOGIC_OUTS_B7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA41" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA42->GTXE2_LOGIC_OUTS_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA42" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA43->GTXE2_LOGIC_OUTS_B5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA43" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA44->GTXE2_LOGIC_OUTS_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA44" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA45->GTXE2_LOGIC_OUTS_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA45" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA46->GTXE2_LOGIC_OUTS_B4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA46" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA47->GTXE2_LOGIC_OUTS_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA47" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA48->GTXE2_LOGIC_OUTS_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA48" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA49->GTXE2_LOGIC_OUTS_B7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA49" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA5->GTXE2_LOGIC_OUTS_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA50->GTXE2_LOGIC_OUTS_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA50" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA51->GTXE2_LOGIC_OUTS_B5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA51" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA52->GTXE2_LOGIC_OUTS_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA52" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA53->GTXE2_LOGIC_OUTS_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA53" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA54->GTXE2_LOGIC_OUTS_B4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA54" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA55->GTXE2_LOGIC_OUTS_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA55" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA56->GTXE2_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA56" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA57->GTXE2_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA57" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA58->GTXE2_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA58" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA59->GTXE2_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA59" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA6->GTXE2_LOGIC_OUTS_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA60->GTXE2_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA60" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA61->GTXE2_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA61" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA62->GTXE2_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA62" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA63->GTXE2_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA63" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA7->GTXE2_LOGIC_OUTS_B5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA7" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA8->GTXE2_LOGIC_OUTS_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA8" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATA9->GTXE2_LOGIC_OUTS_B2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA9" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDATAVALID->GTXE2_LOGIC_OUTS_B19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATAVALID" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR0->GTXE2_LOGIC_OUTS_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR1->GTXE2_LOGIC_OUTS_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR2->GTXE2_LOGIC_OUTS_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR3->GTXE2_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR4->GTXE2_LOGIC_OUTS_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR5->GTXE2_LOGIC_OUTS_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR6->GTXE2_LOGIC_OUTS_B22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDISPERR7->GTXE2_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR7" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDLYSRESETDONE" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXELECIDLE->GTXE2_LOGIC_OUTS_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXELECIDLE" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXHEADER0->GTXE2_LOGIC_OUTS_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXHEADER1->GTXE2_LOGIC_OUTS_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXHEADER2->GTXE2_LOGIC_OUTS_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXHEADERVALID->GTXE2_LOGIC_OUTS_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADERVALID" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT0->GTXE2_LOGIC_OUTS_B8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT1->GTXE2_LOGIC_OUTS_B8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT2->GTXE2_LOGIC_OUTS_B8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT3->GTXE2_LOGIC_OUTS_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT4->GTXE2_LOGIC_OUTS_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT5->GTXE2_LOGIC_OUTS_B8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXMONITOROUT6->GTXE2_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE0->GTXE2_LOGIC_OUTS_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE1->GTXE2_LOGIC_OUTS_B14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE2->GTXE2_LOGIC_OUTS_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE3->GTXE2_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE4->GTXE2_LOGIC_OUTS_B14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE5->GTXE2_LOGIC_OUTS_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE6->GTXE2_LOGIC_OUTS_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXNOTINTABLE7->GTXE2_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE7" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXN_PAD->GTXE2_CHANNEL_RXN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXN_PAD" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXOUTCLKPCS->GTXE2_LOGIC_OUTS_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXOUTCLKPCS" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHALIGNDONE" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR0->GTXE2_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR1->GTXE2_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR2->GTXE2_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR3->GTXE2_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHMONITOR4->GTXE2_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR0->GTXE2_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR1->GTXE2_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR2->GTXE2_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR3->GTXE2_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPHSLIPMONITOR4->GTXE2_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXPRBSERR->GTXE2_LOGIC_OUTS_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPRBSERR" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXP_PAD->GTXE2_CHANNEL_RXP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXP_PAD" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXQPISENN->GTXE2_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXQPISENN" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXQPISENP->GTXE2_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXQPISENP" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXRATEDONE->GTXE2_LOGIC_OUTS_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXRATEDONE" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXRESETDONE->GTXE2_LOGIC_OUTS_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXRESETDONE" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXSTARTOFSEQ->GTXE2_LOGIC_OUTS_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTARTOFSEQ" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXSTATUS0->GTXE2_LOGIC_OUTS_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXSTATUS1->GTXE2_LOGIC_OUTS_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXSTATUS2->GTXE2_LOGIC_OUTS_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_RXVALID->GTXE2_LOGIC_OUTS_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXVALID" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_SOUTHREFCLK0->GTXE2_CHANNEL_GTSOUTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_SOUTHREFCLK1->GTXE2_CHANNEL_GTSOUTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT0->GTXE2_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT1->GTXE2_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT2->GTXE2_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT2" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT3->GTXE2_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT3" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT4->GTXE2_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT4" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT5->GTXE2_LOGIC_OUTS_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT5" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT6->GTXE2_LOGIC_OUTS_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT6" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT7->GTXE2_LOGIC_OUTS_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT7" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT8->GTXE2_LOGIC_OUTS_B11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT8" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TSTOUT9->GTXE2_LOGIC_OUTS_B11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT9" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXBUFSTATUS0->GTXE2_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS0" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXBUFSTATUS1->GTXE2_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS1" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXCOMFINISH->GTXE2_LOGIC_OUTS_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXCOMFINISH" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXDLYSRESETDONE" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXGEARBOXREADY->GTXE2_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXGEARBOXREADY" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXN->GTXE2_CHANNEL_TXN_PAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXN_PAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXN" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXOUTCLKPCS->GTXE2_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXOUTCLKPCS" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXP->GTXE2_CHANNEL_TXP_PAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXP_PAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXP" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXPHALIGNDONE" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXPHINITDONE->GTXE2_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXPHINITDONE" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXQPISENN->GTXE2_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXQPISENN" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXQPISENP->GTXE2_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXQPISENP" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXRATEDONE->GTXE2_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXRATEDONE" }, "GTX_CHANNEL_2.GTXE2_CHANNEL_TXRESETDONE->GTXE2_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXRESETDONE" }, "GTX_CHANNEL_2.GTXE2_CLK0_2->GTXE2_CHANNEL_CPLLLOCKDETCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_2" }, "GTX_CHANNEL_2.GTXE2_CLK0_4->GTXE2_CHANNEL_TXUSRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_4" }, "GTX_CHANNEL_2.GTXE2_CLK0_5->GTXE2_CHANNEL_TXUSRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSRCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_5" }, "GTX_CHANNEL_2.GTXE2_CLK0_6->GTXE2_CHANNEL_RXUSRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_6" }, "GTX_CHANNEL_2.GTXE2_CLK0_7->GTXE2_CHANNEL_RXUSRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSRCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_7" }, "GTX_CHANNEL_2.GTXE2_CLK1_1->GTXE2_CHANNEL_DRPCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_1" }, "GTX_CHANNEL_2.GTXE2_CLK1_2->GTXE2_CHANNEL_TXPHDLYTSTCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_2" }, "GTX_CHANNEL_2.GTXE2_CLK1_4->GTXE2_CHANNEL_CLKRSVD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_4" }, "GTX_CHANNEL_2.GTXE2_CLK1_5->GTXE2_CHANNEL_CLKRSVD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_5" }, "GTX_CHANNEL_2.GTXE2_CLK1_6->GTXE2_CHANNEL_GTGREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTGREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_6" }, "GTX_CHANNEL_2.GTXE2_CLK1_7->GTXE2_CHANNEL_CLKRSVD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_7" }, "GTX_CHANNEL_2.GTXE2_CLK1_8->GTXE2_CHANNEL_CLKRSVD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_8" }, "GTX_CHANNEL_2.GTXE2_CTRL0_10->GTXE2_CHANNEL_GTRESETSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRESETSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_10" }, "GTX_CHANNEL_2.GTXE2_CTRL0_3->GTXE2_CHANNEL_CPLLRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_3" }, "GTX_CHANNEL_2.GTXE2_CTRL0_5->GTXE2_CHANNEL_GTTXRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTTXRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_5" }, "GTX_CHANNEL_2.GTXE2_CTRL0_6->GTXE2_CHANNEL_RXDLYSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_6" }, "GTX_CHANNEL_2.GTXE2_CTRL0_7->GTXE2_CHANNEL_RXCDRFREQRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRFREQRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_7" }, "GTX_CHANNEL_2.GTXE2_CTRL0_8->GTXE2_CHANNEL_GTRXRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRXRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_8" }, "GTX_CHANNEL_2.GTXE2_CTRL0_9->GTXE2_CHANNEL_RXDFELPMRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELPMRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_9" }, "GTX_CHANNEL_2.GTXE2_CTRL1_1->GTXE2_CHANNEL_RXPHDLYRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHDLYRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_1" }, "GTX_CHANNEL_2.GTXE2_CTRL1_10->GTXE2_CHANNEL_RXOOBRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOOBRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_10" }, "GTX_CHANNEL_2.GTXE2_CTRL1_3->GTXE2_CHANNEL_TXPMARESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPMARESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_3" }, "GTX_CHANNEL_2.GTXE2_CTRL1_5->GTXE2_CHANNEL_CFGRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CFGRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_5" }, "GTX_CHANNEL_2.GTXE2_CTRL1_6->GTXE2_CHANNEL_RXBUFRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXBUFRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_6" }, "GTX_CHANNEL_2.GTXE2_CTRL1_7->GTXE2_CHANNEL_RXPMARESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPMARESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_7" }, "GTX_CHANNEL_2.GTXE2_CTRL1_8->GTXE2_CHANNEL_RXCDRRESETRSV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRRESETRSV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_8" }, "GTX_CHANNEL_2.GTXE2_CTRL1_9->GTXE2_CHANNEL_RXCDRRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_9" }, "GTX_CHANNEL_2.GTXE2_IMUX0_10->GTXE2_CHANNEL_RXELECIDLEMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_10" }, "GTX_CHANNEL_2.GTXE2_IMUX0_2->GTXE2_CHANNEL_TX8B10BEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_2" }, "GTX_CHANNEL_2.GTXE2_IMUX0_3->GTXE2_CHANNEL_TXMAINCURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_3" }, "GTX_CHANNEL_2.GTXE2_IMUX0_5->GTXE2_CHANNEL_TXSEQUENCE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_5" }, "GTX_CHANNEL_2.GTXE2_IMUX0_6->GTXE2_CHANNEL_PMARSVDIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_6" }, "GTX_CHANNEL_2.GTXE2_IMUX0_7->GTXE2_CHANNEL_PMARSVDIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_7" }, "GTX_CHANNEL_2.GTXE2_IMUX0_8->GTXE2_CHANNEL_PMARSVDIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_8" }, "GTX_CHANNEL_2.GTXE2_IMUX0_9->GTXE2_CHANNEL_PMARSVDIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_9" }, "GTX_CHANNEL_2.GTXE2_IMUX10_0->GTXE2_CHANNEL_TXCHARDISPVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_0" }, "GTX_CHANNEL_2.GTXE2_IMUX10_1->GTXE2_CHANNEL_TXPDELECIDLEMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_1" }, "GTX_CHANNEL_2.GTXE2_IMUX10_2->GTXE2_CHANNEL_TXCHARDISPVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_2" }, "GTX_CHANNEL_2.GTXE2_IMUX10_4->GTXE2_CHANNEL_TXCHARDISPVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_4" }, "GTX_CHANNEL_2.GTXE2_IMUX10_5->GTXE2_CHANNEL_TXUSERRDY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSERRDY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_5" }, "GTX_CHANNEL_2.GTXE2_IMUX10_6->GTXE2_CHANNEL_TXCHARDISPVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_6" }, "GTX_CHANNEL_2.GTXE2_IMUX10_7->GTXE2_CHANNEL_TXBUFDIFFCTRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_7" }, "GTX_CHANNEL_2.GTXE2_IMUX10_9->GTXE2_CHANNEL_RXQPIEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXQPIEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_9" }, "GTX_CHANNEL_2.GTXE2_IMUX11_10->GTXE2_CHANNEL_RXLPMLFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMLFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_10" }, "GTX_CHANNEL_2.GTXE2_IMUX11_2->GTXE2_CHANNEL_CPLLREFCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_2" }, "GTX_CHANNEL_2.GTXE2_IMUX11_5->GTXE2_CHANNEL_TXDLYHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_5" }, "GTX_CHANNEL_2.GTXE2_IMUX11_6->GTXE2_CHANNEL_RXRATE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_6" }, "GTX_CHANNEL_2.GTXE2_IMUX11_8->GTXE2_CHANNEL_RXDFEVSEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVSEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_8" }, "GTX_CHANNEL_2.GTXE2_IMUX12_1->GTXE2_CHANNEL_TXCOMWAKE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMWAKE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_1" }, "GTX_CHANNEL_2.GTXE2_IMUX12_10->GTXE2_CHANNEL_RXDFETAP3OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_10" }, "GTX_CHANNEL_2.GTXE2_IMUX12_2->GTXE2_CHANNEL_TXHEADER1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_2" }, "GTX_CHANNEL_2.GTXE2_IMUX12_4->GTXE2_CHANNEL_TXPHOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_4" }, "GTX_CHANNEL_2.GTXE2_IMUX12_5->GTXE2_CHANNEL_TXDLYOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_5" }, "GTX_CHANNEL_2.GTXE2_IMUX12_7->GTXE2_CHANNEL_TXBUFDIFFCTRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_7" }, "GTX_CHANNEL_2.GTXE2_IMUX12_8->GTXE2_CHANNEL_RXSLIDE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSLIDE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_8" }, "GTX_CHANNEL_2.GTXE2_IMUX12_9->GTXE2_CHANNEL_RX8B10BEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RX8B10BEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_9" }, "GTX_CHANNEL_2.GTXE2_IMUX13_1->GTXE2_CHANNEL_TXQPISTRONGPDOWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_1" }, "GTX_CHANNEL_2.GTXE2_IMUX13_10->GTXE2_CHANNEL_RXPRBSCNTRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSCNTRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_10" }, "GTX_CHANNEL_2.GTXE2_IMUX13_2->GTXE2_CHANNEL_TXHEADER0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_2" }, "GTX_CHANNEL_2.GTXE2_IMUX13_7->GTXE2_CHANNEL_TXBUFDIFFCTRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_7" }, "GTX_CHANNEL_2.GTXE2_IMUX13_8->GTXE2_CHANNEL_RXOSOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOSOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_8" }, "GTX_CHANNEL_2.GTXE2_IMUX13_9->GTXE2_CHANNEL_RXDFETAP5OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_9" }, "GTX_CHANNEL_2.GTXE2_IMUX14_10->GTXE2_CHANNEL_RXPHOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_10" }, "GTX_CHANNEL_2.GTXE2_IMUX14_2->GTXE2_CHANNEL_CPLLREFCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_2" }, "GTX_CHANNEL_2.GTXE2_IMUX14_5->GTXE2_CHANNEL_TXDLYEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_5" }, "GTX_CHANNEL_2.GTXE2_IMUX14_6->GTXE2_CHANNEL_RXRATE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_6" }, "GTX_CHANNEL_2.GTXE2_IMUX14_7->GTXE2_CHANNEL_RXPCSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPCSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_7" }, "GTX_CHANNEL_2.GTXE2_IMUX14_8->GTXE2_CHANNEL_RXCDROVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDROVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_8" }, "GTX_CHANNEL_2.GTXE2_IMUX14_9->GTXE2_CHANNEL_RXPHALIGN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHALIGN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_9" }, "GTX_CHANNEL_2.GTXE2_IMUX15_1->GTXE2_CHANNEL_TX8B10BBYPASS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_1" }, "GTX_CHANNEL_2.GTXE2_IMUX15_2->GTXE2_CHANNEL_CPLLREFCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_2" }, "GTX_CHANNEL_2.GTXE2_IMUX15_3->GTXE2_CHANNEL_TX8B10BBYPASS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_3" }, "GTX_CHANNEL_2.GTXE2_IMUX15_4->GTXE2_CHANNEL_TXPRBSFORCEERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSFORCEERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_4" }, "GTX_CHANNEL_2.GTXE2_IMUX15_5->GTXE2_CHANNEL_TX8B10BBYPASS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_5" }, "GTX_CHANNEL_2.GTXE2_IMUX15_6->GTXE2_CHANNEL_RXRATE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_6" }, "GTX_CHANNEL_2.GTXE2_IMUX15_7->GTXE2_CHANNEL_TX8B10BBYPASS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_7" }, "GTX_CHANNEL_2.GTXE2_IMUX16_0->GTXE2_CHANNEL_TXDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_0" }, "GTX_CHANNEL_2.GTXE2_IMUX16_1->GTXE2_CHANNEL_TXDATA56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_1" }, "GTX_CHANNEL_2.GTXE2_IMUX16_10->GTXE2_CHANNEL_RXDFECM1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFECM1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_10" }, "GTX_CHANNEL_2.GTXE2_IMUX16_2->GTXE2_CHANNEL_TXDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_2" }, "GTX_CHANNEL_2.GTXE2_IMUX16_3->GTXE2_CHANNEL_TXDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_3" }, "GTX_CHANNEL_2.GTXE2_IMUX16_4->GTXE2_CHANNEL_TXDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_4" }, "GTX_CHANNEL_2.GTXE2_IMUX16_5->GTXE2_CHANNEL_TXDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_5" }, "GTX_CHANNEL_2.GTXE2_IMUX16_6->GTXE2_CHANNEL_TXDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_6" }, "GTX_CHANNEL_2.GTXE2_IMUX16_7->GTXE2_CHANNEL_TXDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_7" }, "GTX_CHANNEL_2.GTXE2_IMUX17_0->GTXE2_CHANNEL_TXDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_0" }, "GTX_CHANNEL_2.GTXE2_IMUX17_1->GTXE2_CHANNEL_TXDATA57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_1" }, "GTX_CHANNEL_2.GTXE2_IMUX17_2->GTXE2_CHANNEL_TXDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_2" }, "GTX_CHANNEL_2.GTXE2_IMUX17_3->GTXE2_CHANNEL_TXDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_3" }, "GTX_CHANNEL_2.GTXE2_IMUX17_4->GTXE2_CHANNEL_TXDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_4" }, "GTX_CHANNEL_2.GTXE2_IMUX17_5->GTXE2_CHANNEL_TXDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_5" }, "GTX_CHANNEL_2.GTXE2_IMUX17_6->GTXE2_CHANNEL_TXDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_6" }, "GTX_CHANNEL_2.GTXE2_IMUX17_7->GTXE2_CHANNEL_TXDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_7" }, "GTX_CHANNEL_2.GTXE2_IMUX17_9->GTXE2_CHANNEL_RXCHBONDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_9" }, "GTX_CHANNEL_2.GTXE2_IMUX18_0->GTXE2_CHANNEL_TXDATA60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_0" }, "GTX_CHANNEL_2.GTXE2_IMUX18_1->GTXE2_CHANNEL_TXDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_1" }, "GTX_CHANNEL_2.GTXE2_IMUX18_10->GTXE2_CHANNEL_RXCHBONDLEVEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_10" }, "GTX_CHANNEL_2.GTXE2_IMUX18_2->GTXE2_CHANNEL_TXDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_2" }, "GTX_CHANNEL_2.GTXE2_IMUX18_3->GTXE2_CHANNEL_TXDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_3" }, "GTX_CHANNEL_2.GTXE2_IMUX18_4->GTXE2_CHANNEL_TXDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_4" }, "GTX_CHANNEL_2.GTXE2_IMUX18_5->GTXE2_CHANNEL_TXDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_5" }, "GTX_CHANNEL_2.GTXE2_IMUX18_6->GTXE2_CHANNEL_TXDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_6" }, "GTX_CHANNEL_2.GTXE2_IMUX18_7->GTXE2_CHANNEL_TXDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_7" }, "GTX_CHANNEL_2.GTXE2_IMUX18_9->GTXE2_CHANNEL_RXCHBONDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_9" }, "GTX_CHANNEL_2.GTXE2_IMUX19_0->GTXE2_CHANNEL_TXDATA61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_0" }, "GTX_CHANNEL_2.GTXE2_IMUX19_1->GTXE2_CHANNEL_TXDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_1" }, "GTX_CHANNEL_2.GTXE2_IMUX19_10->GTXE2_CHANNEL_RXCHBONDLEVEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_10" }, "GTX_CHANNEL_2.GTXE2_IMUX19_2->GTXE2_CHANNEL_TXDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_2" }, "GTX_CHANNEL_2.GTXE2_IMUX19_3->GTXE2_CHANNEL_TXDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_3" }, "GTX_CHANNEL_2.GTXE2_IMUX19_4->GTXE2_CHANNEL_TXDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_4" }, "GTX_CHANNEL_2.GTXE2_IMUX19_5->GTXE2_CHANNEL_TXDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_5" }, "GTX_CHANNEL_2.GTXE2_IMUX19_6->GTXE2_CHANNEL_TXDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_6" }, "GTX_CHANNEL_2.GTXE2_IMUX19_7->GTXE2_CHANNEL_TXDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_7" }, "GTX_CHANNEL_2.GTXE2_IMUX19_8->GTXE2_CHANNEL_RXDFEVPHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVPHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_8" }, "GTX_CHANNEL_2.GTXE2_IMUX19_9->GTXE2_CHANNEL_RXCHBONDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_9" }, "GTX_CHANNEL_2.GTXE2_IMUX1_10->GTXE2_CHANNEL_RXELECIDLEMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_10" }, "GTX_CHANNEL_2.GTXE2_IMUX1_2->GTXE2_CHANNEL_RXMONITORSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_2" }, "GTX_CHANNEL_2.GTXE2_IMUX1_3->GTXE2_CHANNEL_TXMAINCURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_3" }, "GTX_CHANNEL_2.GTXE2_IMUX1_4->GTXE2_CHANNEL_TXMAINCURSOR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_4" }, "GTX_CHANNEL_2.GTXE2_IMUX1_5->GTXE2_CHANNEL_TXSEQUENCE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_5" }, "GTX_CHANNEL_2.GTXE2_IMUX1_6->GTXE2_CHANNEL_TXSEQUENCE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_6" }, "GTX_CHANNEL_2.GTXE2_IMUX1_7->GTXE2_CHANNEL_PMARSVDIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_7" }, "GTX_CHANNEL_2.GTXE2_IMUX1_8->GTXE2_CHANNEL_TXOUTCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_8" }, "GTX_CHANNEL_2.GTXE2_IMUX1_9->GTXE2_CHANNEL_PMARSVDIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_9" }, "GTX_CHANNEL_2.GTXE2_IMUX20_0->GTXE2_CHANNEL_TXDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_0" }, "GTX_CHANNEL_2.GTXE2_IMUX20_1->GTXE2_CHANNEL_TXDATA58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_1" }, "GTX_CHANNEL_2.GTXE2_IMUX20_2->GTXE2_CHANNEL_TXDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_2" }, "GTX_CHANNEL_2.GTXE2_IMUX20_3->GTXE2_CHANNEL_TXDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_3" }, "GTX_CHANNEL_2.GTXE2_IMUX20_4->GTXE2_CHANNEL_TXDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_4" }, "GTX_CHANNEL_2.GTXE2_IMUX20_5->GTXE2_CHANNEL_TXDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_5" }, "GTX_CHANNEL_2.GTXE2_IMUX20_6->GTXE2_CHANNEL_TXDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_6" }, "GTX_CHANNEL_2.GTXE2_IMUX20_7->GTXE2_CHANNEL_TXDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_7" }, "GTX_CHANNEL_2.GTXE2_IMUX21_0->GTXE2_CHANNEL_TXDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_0" }, "GTX_CHANNEL_2.GTXE2_IMUX21_1->GTXE2_CHANNEL_TXDATA59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_1" }, "GTX_CHANNEL_2.GTXE2_IMUX21_10->GTXE2_CHANNEL_RXDFEAGCOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_10" }, "GTX_CHANNEL_2.GTXE2_IMUX21_2->GTXE2_CHANNEL_TXDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_2" }, "GTX_CHANNEL_2.GTXE2_IMUX21_3->GTXE2_CHANNEL_TXDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_3" }, "GTX_CHANNEL_2.GTXE2_IMUX21_4->GTXE2_CHANNEL_TXDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_4" }, "GTX_CHANNEL_2.GTXE2_IMUX21_5->GTXE2_CHANNEL_TXDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_5" }, "GTX_CHANNEL_2.GTXE2_IMUX21_6->GTXE2_CHANNEL_TXDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_6" }, "GTX_CHANNEL_2.GTXE2_IMUX21_7->GTXE2_CHANNEL_TXDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_7" }, "GTX_CHANNEL_2.GTXE2_IMUX21_8->GTXE2_CHANNEL_RXDFEXYDOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_8" }, "GTX_CHANNEL_2.GTXE2_IMUX21_9->GTXE2_CHANNEL_RXDFETAP4OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_9" }, "GTX_CHANNEL_2.GTXE2_IMUX22_0->GTXE2_CHANNEL_TXDATA62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_0" }, "GTX_CHANNEL_2.GTXE2_IMUX22_1->GTXE2_CHANNEL_TXDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_1" }, "GTX_CHANNEL_2.GTXE2_IMUX22_10->GTXE2_CHANNEL_RXCHBONDLEVEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_10" }, "GTX_CHANNEL_2.GTXE2_IMUX22_2->GTXE2_CHANNEL_TXDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_2" }, "GTX_CHANNEL_2.GTXE2_IMUX22_3->GTXE2_CHANNEL_TXDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_3" }, "GTX_CHANNEL_2.GTXE2_IMUX22_4->GTXE2_CHANNEL_TXDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_4" }, "GTX_CHANNEL_2.GTXE2_IMUX22_5->GTXE2_CHANNEL_TXDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_5" }, "GTX_CHANNEL_2.GTXE2_IMUX22_6->GTXE2_CHANNEL_TXDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_6" }, "GTX_CHANNEL_2.GTXE2_IMUX22_7->GTXE2_CHANNEL_TXDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_7" }, "GTX_CHANNEL_2.GTXE2_IMUX22_8->GTXE2_CHANNEL_RXPRBSSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_8" }, "GTX_CHANNEL_2.GTXE2_IMUX22_9->GTXE2_CHANNEL_RXCHBONDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_9" }, "GTX_CHANNEL_2.GTXE2_IMUX23_0->GTXE2_CHANNEL_TXDATA63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_0" }, "GTX_CHANNEL_2.GTXE2_IMUX23_1->GTXE2_CHANNEL_TXDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_1" }, "GTX_CHANNEL_2.GTXE2_IMUX23_10->GTXE2_CHANNEL_RXCHBONDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_10" }, "GTX_CHANNEL_2.GTXE2_IMUX23_2->GTXE2_CHANNEL_TXDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_2" }, "GTX_CHANNEL_2.GTXE2_IMUX23_3->GTXE2_CHANNEL_TXDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_3" }, "GTX_CHANNEL_2.GTXE2_IMUX23_4->GTXE2_CHANNEL_TXDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_4" }, "GTX_CHANNEL_2.GTXE2_IMUX23_5->GTXE2_CHANNEL_TXDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_5" }, "GTX_CHANNEL_2.GTXE2_IMUX23_6->GTXE2_CHANNEL_TXDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_6" }, "GTX_CHANNEL_2.GTXE2_IMUX23_7->GTXE2_CHANNEL_TXDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_7" }, "GTX_CHANNEL_2.GTXE2_IMUX23_8->GTXE2_CHANNEL_RXPRBSSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_8" }, "GTX_CHANNEL_2.GTXE2_IMUX23_9->GTXE2_CHANNEL_RXCHBONDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_9" }, "GTX_CHANNEL_2.GTXE2_IMUX24_1->GTXE2_CHANNEL_TSTIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_1" }, "GTX_CHANNEL_2.GTXE2_IMUX24_10->GTXE2_CHANNEL_TSTIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_10" }, "GTX_CHANNEL_2.GTXE2_IMUX24_2->GTXE2_CHANNEL_TSTIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_2" }, "GTX_CHANNEL_2.GTXE2_IMUX24_3->GTXE2_CHANNEL_TSTIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_3" }, "GTX_CHANNEL_2.GTXE2_IMUX24_4->GTXE2_CHANNEL_TSTIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_4" }, "GTX_CHANNEL_2.GTXE2_IMUX24_5->GTXE2_CHANNEL_TSTIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_5" }, "GTX_CHANNEL_2.GTXE2_IMUX24_6->GTXE2_CHANNEL_TSTIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_6" }, "GTX_CHANNEL_2.GTXE2_IMUX24_7->GTXE2_CHANNEL_TSTIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_7" }, "GTX_CHANNEL_2.GTXE2_IMUX24_8->GTXE2_CHANNEL_TSTIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_8" }, "GTX_CHANNEL_2.GTXE2_IMUX24_9->GTXE2_CHANNEL_TSTIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_9" }, "GTX_CHANNEL_2.GTXE2_IMUX25_10->GTXE2_CHANNEL_PCSRSVDIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_10" }, "GTX_CHANNEL_2.GTXE2_IMUX25_2->GTXE2_CHANNEL_TXPHALIGN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHALIGN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_2" }, "GTX_CHANNEL_2.GTXE2_IMUX25_3->GTXE2_CHANNEL_PCSRSVDIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_3" }, "GTX_CHANNEL_2.GTXE2_IMUX25_4->GTXE2_CHANNEL_PCSRSVDIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_4" }, "GTX_CHANNEL_2.GTXE2_IMUX25_5->GTXE2_CHANNEL_PCSRSVDIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_5" }, "GTX_CHANNEL_2.GTXE2_IMUX25_6->GTXE2_CHANNEL_PCSRSVDIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_6" }, "GTX_CHANNEL_2.GTXE2_IMUX25_7->GTXE2_CHANNEL_PCSRSVDIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_7" }, "GTX_CHANNEL_2.GTXE2_IMUX25_8->GTXE2_CHANNEL_PCSRSVDIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_8" }, "GTX_CHANNEL_2.GTXE2_IMUX25_9->GTXE2_CHANNEL_PCSRSVDIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_9" }, "GTX_CHANNEL_2.GTXE2_IMUX26_10->GTXE2_CHANNEL_GTRSVD15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_10" }, "GTX_CHANNEL_2.GTXE2_IMUX26_3->GTXE2_CHANNEL_GTRSVD8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_3" }, "GTX_CHANNEL_2.GTXE2_IMUX26_4->GTXE2_CHANNEL_GTRSVD9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_4" }, "GTX_CHANNEL_2.GTXE2_IMUX26_5->GTXE2_CHANNEL_GTRSVD10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_5" }, "GTX_CHANNEL_2.GTXE2_IMUX26_6->GTXE2_CHANNEL_GTRSVD11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_6" }, "GTX_CHANNEL_2.GTXE2_IMUX26_7->GTXE2_CHANNEL_GTRSVD12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_7" }, "GTX_CHANNEL_2.GTXE2_IMUX26_8->GTXE2_CHANNEL_GTRSVD13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_8" }, "GTX_CHANNEL_2.GTXE2_IMUX26_9->GTXE2_CHANNEL_GTRSVD14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_9" }, "GTX_CHANNEL_2.GTXE2_IMUX27_10->GTXE2_CHANNEL_RXLPMHFOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_10" }, "GTX_CHANNEL_2.GTXE2_IMUX27_5->GTXE2_CHANNEL_TXPHINIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHINIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_5" }, "GTX_CHANNEL_2.GTXE2_IMUX27_7->GTXE2_CHANNEL_RXPOLARITY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPOLARITY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_7" }, "GTX_CHANNEL_2.GTXE2_IMUX27_8->GTXE2_CHANNEL_RXDFEVPOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_8" }, "GTX_CHANNEL_2.GTXE2_IMUX27_9->GTXE2_CHANNEL_RXDFELFOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELFOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_9" }, "GTX_CHANNEL_2.GTXE2_IMUX28_1->GTXE2_CHANNEL_TXCOMSAS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMSAS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_1" }, "GTX_CHANNEL_2.GTXE2_IMUX28_10->GTXE2_CHANNEL_RXDFETAP2OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_10" }, "GTX_CHANNEL_2.GTXE2_IMUX28_2->GTXE2_CHANNEL_CPLLLOCKEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLLOCKEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_2" }, "GTX_CHANNEL_2.GTXE2_IMUX28_3->GTXE2_CHANNEL_DRPWE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPWE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_3" }, "GTX_CHANNEL_2.GTXE2_IMUX28_4->GTXE2_CHANNEL_TXSYSCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_4" }, "GTX_CHANNEL_2.GTXE2_IMUX28_5->GTXE2_CHANNEL_TXSYSCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_5" }, "GTX_CHANNEL_2.GTXE2_IMUX28_6->GTXE2_CHANNEL_RXDLYEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_6" }, "GTX_CHANNEL_2.GTXE2_IMUX28_8->GTXE2_CHANNEL_RXPD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_8" }, "GTX_CHANNEL_2.GTXE2_IMUX29_0->GTXE2_CHANNEL_TXCHARDISPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_0" }, "GTX_CHANNEL_2.GTXE2_IMUX29_1->GTXE2_CHANNEL_TXCHARISK7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_1" }, "GTX_CHANNEL_2.GTXE2_IMUX29_10->GTXE2_CHANNEL_RXDFEAGCHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEAGCHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_10" }, "GTX_CHANNEL_2.GTXE2_IMUX29_2->GTXE2_CHANNEL_TXCHARDISPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_2" }, "GTX_CHANNEL_2.GTXE2_IMUX29_3->GTXE2_CHANNEL_TXCHARISK6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_3" }, "GTX_CHANNEL_2.GTXE2_IMUX29_4->GTXE2_CHANNEL_TXCHARDISPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_4" }, "GTX_CHANNEL_2.GTXE2_IMUX29_5->GTXE2_CHANNEL_TXCHARISK5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_5" }, "GTX_CHANNEL_2.GTXE2_IMUX29_6->GTXE2_CHANNEL_TXCHARDISPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_6" }, "GTX_CHANNEL_2.GTXE2_IMUX29_7->GTXE2_CHANNEL_TXCHARISK4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_7" }, "GTX_CHANNEL_2.GTXE2_IMUX29_8->GTXE2_CHANNEL_RXOSHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOSHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_8" }, "GTX_CHANNEL_2.GTXE2_IMUX29_9->GTXE2_CHANNEL_RXDFETAP5HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP5HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_9" }, "GTX_CHANNEL_2.GTXE2_IMUX2_10->GTXE2_CHANNEL_RXOUTCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_10" }, "GTX_CHANNEL_2.GTXE2_IMUX2_3->GTXE2_CHANNEL_DRPADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_3" }, "GTX_CHANNEL_2.GTXE2_IMUX2_4->GTXE2_CHANNEL_TXPOSTCURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_4" }, "GTX_CHANNEL_2.GTXE2_IMUX2_5->GTXE2_CHANNEL_TXDIFFCTRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_5" }, "GTX_CHANNEL_2.GTXE2_IMUX2_6->GTXE2_CHANNEL_TXPRECURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_6" }, "GTX_CHANNEL_2.GTXE2_IMUX2_8->GTXE2_CHANNEL_RXGEARBOXSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXGEARBOXSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_8" }, "GTX_CHANNEL_2.GTXE2_IMUX2_9->GTXE2_CHANNEL_RXMCOMMAALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_9" }, "GTX_CHANNEL_2.GTXE2_IMUX30_10->GTXE2_CHANNEL_RXCHBONDSLAVE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDSLAVE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_10" }, "GTX_CHANNEL_2.GTXE2_IMUX30_3->GTXE2_CHANNEL_TXPOLARITY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOLARITY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_3" }, "GTX_CHANNEL_2.GTXE2_IMUX30_7->GTXE2_CHANNEL_TXPCSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPCSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_7" }, "GTX_CHANNEL_2.GTXE2_IMUX30_8->GTXE2_CHANNEL_RXCDRHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_8" }, "GTX_CHANNEL_2.GTXE2_IMUX30_9->GTXE2_CHANNEL_RXCHBONDMASTER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDMASTER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_9" }, "GTX_CHANNEL_2.GTXE2_IMUX31_0->GTXE2_CHANNEL_TXCHARDISPMODE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_0" }, "GTX_CHANNEL_2.GTXE2_IMUX31_1->GTXE2_CHANNEL_TXCHARISK3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_1" }, "GTX_CHANNEL_2.GTXE2_IMUX31_2->GTXE2_CHANNEL_TXCHARDISPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_2" }, "GTX_CHANNEL_2.GTXE2_IMUX31_3->GTXE2_CHANNEL_TXCHARISK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_3" }, "GTX_CHANNEL_2.GTXE2_IMUX31_4->GTXE2_CHANNEL_TXCHARDISPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_4" }, "GTX_CHANNEL_2.GTXE2_IMUX31_5->GTXE2_CHANNEL_TXCHARISK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_5" }, "GTX_CHANNEL_2.GTXE2_IMUX31_6->GTXE2_CHANNEL_TXCHARDISPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_6" }, "GTX_CHANNEL_2.GTXE2_IMUX31_7->GTXE2_CHANNEL_TXCHARISK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_7" }, "GTX_CHANNEL_2.GTXE2_IMUX31_8->GTXE2_CHANNEL_EYESCANTRIGGER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANTRIGGER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_8" }, "GTX_CHANNEL_2.GTXE2_IMUX32_0->GTXE2_CHANNEL_DRPDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_0" }, "GTX_CHANNEL_2.GTXE2_IMUX32_1->GTXE2_CHANNEL_DRPDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_1" }, "GTX_CHANNEL_2.GTXE2_IMUX32_2->GTXE2_CHANNEL_TXINHIBIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXINHIBIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_2" }, "GTX_CHANNEL_2.GTXE2_IMUX32_8->GTXE2_CHANNEL_RXDLYBYPASS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYBYPASS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_8" }, "GTX_CHANNEL_2.GTXE2_IMUX33_0->GTXE2_CHANNEL_DRPDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_0" }, "GTX_CHANNEL_2.GTXE2_IMUX33_1->GTXE2_CHANNEL_DRPDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_1" }, "GTX_CHANNEL_2.GTXE2_IMUX33_2->GTXE2_CHANNEL_TXPHALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_2" }, "GTX_CHANNEL_2.GTXE2_IMUX34_0->GTXE2_CHANNEL_DRPDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_0" }, "GTX_CHANNEL_2.GTXE2_IMUX34_1->GTXE2_CHANNEL_DRPDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_1" }, "GTX_CHANNEL_2.GTXE2_IMUX34_10->GTXE2_CHANNEL_PCSRSVDIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_10" }, "GTX_CHANNEL_2.GTXE2_IMUX34_2->GTXE2_CHANNEL_DRPADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_2" }, "GTX_CHANNEL_2.GTXE2_IMUX34_3->GTXE2_CHANNEL_DRPADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_3" }, "GTX_CHANNEL_2.GTXE2_IMUX34_4->GTXE2_CHANNEL_SETERRSTATUS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_SETERRSTATUS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_4" }, "GTX_CHANNEL_2.GTXE2_IMUX34_8->GTXE2_CHANNEL_RXLPMEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_8" }, "GTX_CHANNEL_2.GTXE2_IMUX34_9->GTXE2_CHANNEL_RXPCOMMAALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_9" }, "GTX_CHANNEL_2.GTXE2_IMUX35_0->GTXE2_CHANNEL_DRPDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_0" }, "GTX_CHANNEL_2.GTXE2_IMUX35_1->GTXE2_CHANNEL_DRPDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_1" }, "GTX_CHANNEL_2.GTXE2_IMUX35_10->GTXE2_CHANNEL_PCSRSVDIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_10" }, "GTX_CHANNEL_2.GTXE2_IMUX35_2->GTXE2_CHANNEL_DRPADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_2" }, "GTX_CHANNEL_2.GTXE2_IMUX35_3->GTXE2_CHANNEL_DRPADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_3" }, "GTX_CHANNEL_2.GTXE2_IMUX35_4->GTXE2_CHANNEL_TXMARGIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_4" }, "GTX_CHANNEL_2.GTXE2_IMUX35_5->GTXE2_CHANNEL_TXDEEMPH": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDEEMPH", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_5" }, "GTX_CHANNEL_2.GTXE2_IMUX35_6->GTXE2_CHANNEL_TXPD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_6" }, "GTX_CHANNEL_2.GTXE2_IMUX35_8->GTXE2_CHANNEL_RXDFEUTOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_8" }, "GTX_CHANNEL_2.GTXE2_IMUX35_9->GTXE2_CHANNEL_RXDFELFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_9" }, "GTX_CHANNEL_2.GTXE2_IMUX36_0->GTXE2_CHANNEL_DRPDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_0" }, "GTX_CHANNEL_2.GTXE2_IMUX36_1->GTXE2_CHANNEL_DRPDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_1" }, "GTX_CHANNEL_2.GTXE2_IMUX36_10->GTXE2_CHANNEL_RXDFETAP3HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP3HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_10" }, "GTX_CHANNEL_2.GTXE2_IMUX36_2->GTXE2_CHANNEL_CPLLPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_2" }, "GTX_CHANNEL_2.GTXE2_IMUX36_5->GTXE2_CHANNEL_TXPHDLYRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_5" }, "GTX_CHANNEL_2.GTXE2_IMUX37_0->GTXE2_CHANNEL_DRPDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_0" }, "GTX_CHANNEL_2.GTXE2_IMUX37_1->GTXE2_CHANNEL_DRPDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_1" }, "GTX_CHANNEL_2.GTXE2_IMUX37_3->GTXE2_CHANNEL_TXPHDLYPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_3" }, "GTX_CHANNEL_2.GTXE2_IMUX37_4->GTXE2_CHANNEL_TXDIFFPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_4" }, "GTX_CHANNEL_2.GTXE2_IMUX37_8->GTXE2_CHANNEL_RXDFEXYDHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_8" }, "GTX_CHANNEL_2.GTXE2_IMUX37_9->GTXE2_CHANNEL_RXDFETAP4HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP4HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_9" }, "GTX_CHANNEL_2.GTXE2_IMUX38_0->GTXE2_CHANNEL_DRPDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_0" }, "GTX_CHANNEL_2.GTXE2_IMUX38_1->GTXE2_CHANNEL_DRPDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_1" }, "GTX_CHANNEL_2.GTXE2_IMUX38_10->GTXE2_CHANNEL_PCSRSVDIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_10" }, "GTX_CHANNEL_2.GTXE2_IMUX38_2->GTXE2_CHANNEL_DRPADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_2" }, "GTX_CHANNEL_2.GTXE2_IMUX38_3->GTXE2_CHANNEL_DRPADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_3" }, "GTX_CHANNEL_2.GTXE2_IMUX38_4->GTXE2_CHANNEL_TXMARGIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_4" }, "GTX_CHANNEL_2.GTXE2_IMUX38_5->GTXE2_CHANNEL_TXSWING": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSWING", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_5" }, "GTX_CHANNEL_2.GTXE2_IMUX38_6->GTXE2_CHANNEL_TXPD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_6" }, "GTX_CHANNEL_2.GTXE2_IMUX38_7->GTXE2_CHANNEL_RXDLYOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_7" }, "GTX_CHANNEL_2.GTXE2_IMUX38_8->GTXE2_CHANNEL_RXPRBSSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_8" }, "GTX_CHANNEL_2.GTXE2_IMUX39_0->GTXE2_CHANNEL_DRPDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_0" }, "GTX_CHANNEL_2.GTXE2_IMUX39_1->GTXE2_CHANNEL_DRPDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_1" }, "GTX_CHANNEL_2.GTXE2_IMUX39_10->GTXE2_CHANNEL_PCSRSVDIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_10" }, "GTX_CHANNEL_2.GTXE2_IMUX39_2->GTXE2_CHANNEL_DRPADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_2" }, "GTX_CHANNEL_2.GTXE2_IMUX39_3->GTXE2_CHANNEL_DRPADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_3" }, "GTX_CHANNEL_2.GTXE2_IMUX39_4->GTXE2_CHANNEL_TXMARGIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_4" }, "GTX_CHANNEL_2.GTXE2_IMUX39_5->GTXE2_CHANNEL_TXDETECTRX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDETECTRX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_5" }, "GTX_CHANNEL_2.GTXE2_IMUX39_6->GTXE2_CHANNEL_TXELECIDLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXELECIDLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_6" }, "GTX_CHANNEL_2.GTXE2_IMUX39_9->GTXE2_CHANNEL_PCSRSVDIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_9" }, "GTX_CHANNEL_2.GTXE2_IMUX3_10->GTXE2_CHANNEL_RXLPMLFKLOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_10" }, "GTX_CHANNEL_2.GTXE2_IMUX3_3->GTXE2_CHANNEL_TXSTARTSEQ": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSTARTSEQ", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_3" }, "GTX_CHANNEL_2.GTXE2_IMUX3_4->GTXE2_CHANNEL_TXPOSTCURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_4" }, "GTX_CHANNEL_2.GTXE2_IMUX3_5->GTXE2_CHANNEL_TXDIFFCTRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_5" }, "GTX_CHANNEL_2.GTXE2_IMUX3_6->GTXE2_CHANNEL_TXPRECURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_6" }, "GTX_CHANNEL_2.GTXE2_IMUX3_7->GTXE2_CHANNEL_RXPD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_7" }, "GTX_CHANNEL_2.GTXE2_IMUX3_8->GTXE2_CHANNEL_TXPRBSSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_8" }, "GTX_CHANNEL_2.GTXE2_IMUX3_9->GTXE2_CHANNEL_RXDFEUTHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEUTHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_9" }, "GTX_CHANNEL_2.GTXE2_IMUX40_1->GTXE2_CHANNEL_TSTIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_1" }, "GTX_CHANNEL_2.GTXE2_IMUX40_10->GTXE2_CHANNEL_TSTIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_10" }, "GTX_CHANNEL_2.GTXE2_IMUX40_2->GTXE2_CHANNEL_TSTIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_2" }, "GTX_CHANNEL_2.GTXE2_IMUX40_3->GTXE2_CHANNEL_TSTIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_3" }, "GTX_CHANNEL_2.GTXE2_IMUX40_4->GTXE2_CHANNEL_TSTIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_4" }, "GTX_CHANNEL_2.GTXE2_IMUX40_5->GTXE2_CHANNEL_TSTIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_5" }, "GTX_CHANNEL_2.GTXE2_IMUX40_6->GTXE2_CHANNEL_TSTIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_6" }, "GTX_CHANNEL_2.GTXE2_IMUX40_7->GTXE2_CHANNEL_TSTIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_7" }, "GTX_CHANNEL_2.GTXE2_IMUX40_8->GTXE2_CHANNEL_TSTIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_8" }, "GTX_CHANNEL_2.GTXE2_IMUX40_9->GTXE2_CHANNEL_TSTIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_9" }, "GTX_CHANNEL_2.GTXE2_IMUX41_0->GTXE2_CHANNEL_EYESCANMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_0" }, "GTX_CHANNEL_2.GTXE2_IMUX41_1->GTXE2_CHANNEL_TXPOSTCURSORINV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSORINV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_1" }, "GTX_CHANNEL_2.GTXE2_IMUX41_5->GTXE2_CHANNEL_RESETOVRD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RESETOVRD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_5" }, "GTX_CHANNEL_2.GTXE2_IMUX41_6->GTXE2_CHANNEL_RXPHALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_6" }, "GTX_CHANNEL_2.GTXE2_IMUX42_10->GTXE2_CHANNEL_GTRSVD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_10" }, "GTX_CHANNEL_2.GTXE2_IMUX42_2->GTXE2_CHANNEL_RXSYSCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_2" }, "GTX_CHANNEL_2.GTXE2_IMUX42_3->GTXE2_CHANNEL_GTRSVD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_3" }, "GTX_CHANNEL_2.GTXE2_IMUX42_4->GTXE2_CHANNEL_GTRSVD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_4" }, "GTX_CHANNEL_2.GTXE2_IMUX42_5->GTXE2_CHANNEL_GTRSVD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_5" }, "GTX_CHANNEL_2.GTXE2_IMUX42_6->GTXE2_CHANNEL_GTRSVD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_6" }, "GTX_CHANNEL_2.GTXE2_IMUX42_7->GTXE2_CHANNEL_GTRSVD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_7" }, "GTX_CHANNEL_2.GTXE2_IMUX42_8->GTXE2_CHANNEL_GTRSVD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_8" }, "GTX_CHANNEL_2.GTXE2_IMUX42_9->GTXE2_CHANNEL_GTRSVD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_9" }, "GTX_CHANNEL_2.GTXE2_IMUX43_10->GTXE2_CHANNEL_RXLPMHFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMHFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_10" }, "GTX_CHANNEL_2.GTXE2_IMUX43_5->GTXE2_CHANNEL_TXDLYUPDOWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYUPDOWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_5" }, "GTX_CHANNEL_2.GTXE2_IMUX43_6->GTXE2_CHANNEL_TXRATE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_6" }, "GTX_CHANNEL_2.GTXE2_IMUX43_9->GTXE2_CHANNEL_LOOPBACK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_9" }, "GTX_CHANNEL_2.GTXE2_IMUX44_1->GTXE2_CHANNEL_TXCOMINIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMINIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_1" }, "GTX_CHANNEL_2.GTXE2_IMUX44_10->GTXE2_CHANNEL_RXDFETAP2HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP2HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_10" }, "GTX_CHANNEL_2.GTXE2_IMUX44_3->GTXE2_CHANNEL_DRPEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_3" }, "GTX_CHANNEL_2.GTXE2_IMUX44_5->GTXE2_CHANNEL_TXDLYBYPASS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYBYPASS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_5" }, "GTX_CHANNEL_2.GTXE2_IMUX44_8->GTXE2_CHANNEL_RXUSERRDY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSERRDY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_8" }, "GTX_CHANNEL_2.GTXE2_IMUX44_9->GTXE2_CHANNEL_RXCOMMADETEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCOMMADETEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_9" }, "GTX_CHANNEL_2.GTXE2_IMUX45_1->GTXE2_CHANNEL_TXQPIWEAKPUP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPIWEAKPUP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_1" }, "GTX_CHANNEL_2.GTXE2_IMUX45_10->GTXE2_CHANNEL_RXMONITORSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_10" }, "GTX_CHANNEL_2.GTXE2_IMUX45_2->GTXE2_CHANNEL_RXSYSCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_2" }, "GTX_CHANNEL_2.GTXE2_IMUX45_3->GTXE2_CHANNEL_TXDLYSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_3" }, "GTX_CHANNEL_2.GTXE2_IMUX45_8->GTXE2_CHANNEL_EYESCANRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_8" }, "GTX_CHANNEL_2.GTXE2_IMUX45_9->GTXE2_CHANNEL_RXDFEXYDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_9" }, "GTX_CHANNEL_2.GTXE2_IMUX46_6->GTXE2_CHANNEL_TXRATE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX46_6" }, "GTX_CHANNEL_2.GTXE2_IMUX46_9->GTXE2_CHANNEL_LOOPBACK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX46_9" }, "GTX_CHANNEL_2.GTXE2_IMUX47_6->GTXE2_CHANNEL_TXRATE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX47_6" }, "GTX_CHANNEL_2.GTXE2_IMUX47_9->GTXE2_CHANNEL_LOOPBACK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX47_9" }, "GTX_CHANNEL_2.GTXE2_IMUX4_1->GTXE2_CHANNEL_TXPRECURSORINV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSORINV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_1" }, "GTX_CHANNEL_2.GTXE2_IMUX4_10->GTXE2_CHANNEL_RXOUTCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_10" }, "GTX_CHANNEL_2.GTXE2_IMUX4_3->GTXE2_CHANNEL_TXMAINCURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_3" }, "GTX_CHANNEL_2.GTXE2_IMUX4_4->GTXE2_CHANNEL_TXMAINCURSOR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_4" }, "GTX_CHANNEL_2.GTXE2_IMUX4_5->GTXE2_CHANNEL_TXSEQUENCE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_5" }, "GTX_CHANNEL_2.GTXE2_IMUX4_6->GTXE2_CHANNEL_TXSEQUENCE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_6" }, "GTX_CHANNEL_2.GTXE2_IMUX4_7->GTXE2_CHANNEL_PMARSVDIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_7" }, "GTX_CHANNEL_2.GTXE2_IMUX4_8->GTXE2_CHANNEL_TXOUTCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_8" }, "GTX_CHANNEL_2.GTXE2_IMUX4_9->GTXE2_CHANNEL_PMARSVDIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_9" }, "GTX_CHANNEL_2.GTXE2_IMUX5_1->GTXE2_CHANNEL_TXQPIBIASEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPIBIASEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_1" }, "GTX_CHANNEL_2.GTXE2_IMUX5_10->GTXE2_CHANNEL_RXOUTCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_10" }, "GTX_CHANNEL_2.GTXE2_IMUX5_3->GTXE2_CHANNEL_TXMAINCURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_3" }, "GTX_CHANNEL_2.GTXE2_IMUX5_4->GTXE2_CHANNEL_TXMAINCURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_4" }, "GTX_CHANNEL_2.GTXE2_IMUX5_5->GTXE2_CHANNEL_TXSEQUENCE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_5" }, "GTX_CHANNEL_2.GTXE2_IMUX5_6->GTXE2_CHANNEL_TXSEQUENCE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_6" }, "GTX_CHANNEL_2.GTXE2_IMUX5_7->GTXE2_CHANNEL_PMARSVDIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_7" }, "GTX_CHANNEL_2.GTXE2_IMUX5_8->GTXE2_CHANNEL_TXOUTCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_8" }, "GTX_CHANNEL_2.GTXE2_IMUX5_9->GTXE2_CHANNEL_PMARSVDIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_9" }, "GTX_CHANNEL_2.GTXE2_IMUX6_4->GTXE2_CHANNEL_TXPOSTCURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_4" }, "GTX_CHANNEL_2.GTXE2_IMUX6_5->GTXE2_CHANNEL_TXDIFFCTRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_5" }, "GTX_CHANNEL_2.GTXE2_IMUX6_6->GTXE2_CHANNEL_TXPRECURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_6" }, "GTX_CHANNEL_2.GTXE2_IMUX6_8->GTXE2_CHANNEL_TXPRBSSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_8" }, "GTX_CHANNEL_2.GTXE2_IMUX7_0->GTXE2_CHANNEL_TXPISOPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPISOPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_0" }, "GTX_CHANNEL_2.GTXE2_IMUX7_3->GTXE2_CHANNEL_TXPOSTCURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_3" }, "GTX_CHANNEL_2.GTXE2_IMUX7_4->GTXE2_CHANNEL_TXPOSTCURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_4" }, "GTX_CHANNEL_2.GTXE2_IMUX7_5->GTXE2_CHANNEL_TXDIFFCTRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_5" }, "GTX_CHANNEL_2.GTXE2_IMUX7_6->GTXE2_CHANNEL_TXPRECURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_6" }, "GTX_CHANNEL_2.GTXE2_IMUX7_7->GTXE2_CHANNEL_TXPRECURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_7" }, "GTX_CHANNEL_2.GTXE2_IMUX7_8->GTXE2_CHANNEL_TXPRBSSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_8" }, "GTX_CHANNEL_2.GTXE2_IMUX8_0->GTXE2_CHANNEL_TXCHARDISPVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_0" }, "GTX_CHANNEL_2.GTXE2_IMUX8_1->GTXE2_CHANNEL_TX8B10BBYPASS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_1" }, "GTX_CHANNEL_2.GTXE2_IMUX8_2->GTXE2_CHANNEL_TXCHARDISPVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_2" }, "GTX_CHANNEL_2.GTXE2_IMUX8_3->GTXE2_CHANNEL_TX8B10BBYPASS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_3" }, "GTX_CHANNEL_2.GTXE2_IMUX8_4->GTXE2_CHANNEL_TXCHARDISPVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_4" }, "GTX_CHANNEL_2.GTXE2_IMUX8_5->GTXE2_CHANNEL_TX8B10BBYPASS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_5" }, "GTX_CHANNEL_2.GTXE2_IMUX8_6->GTXE2_CHANNEL_TXCHARDISPVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_6" }, "GTX_CHANNEL_2.GTXE2_IMUX8_7->GTXE2_CHANNEL_TX8B10BBYPASS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_7" }, "GTX_CHANNEL_2.GTXE2_IMUX8_8->GTXE2_CHANNEL_RXDDIEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDDIEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_8" }, "GTX_CHANNEL_2.GTXE2_IMUX9_1->GTXE2_CHANNEL_RXPHDLYPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHDLYPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_1" }, "GTX_CHANNEL_2.GTXE2_IMUX9_10->GTXE2_CHANNEL_PCSRSVDIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_10" }, "GTX_CHANNEL_2.GTXE2_IMUX9_2->GTXE2_CHANNEL_TXHEADER2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_2" }, "GTX_CHANNEL_2.GTXE2_IMUX9_3->GTXE2_CHANNEL_PCSRSVDIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_3" }, "GTX_CHANNEL_2.GTXE2_IMUX9_4->GTXE2_CHANNEL_PCSRSVDIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_4" }, "GTX_CHANNEL_2.GTXE2_IMUX9_5->GTXE2_CHANNEL_PCSRSVDIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_5" }, "GTX_CHANNEL_2.GTXE2_IMUX9_6->GTXE2_CHANNEL_PCSRSVDIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_6" }, "GTX_CHANNEL_2.GTXE2_IMUX9_7->GTXE2_CHANNEL_PCSRSVDIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_7" }, "GTX_CHANNEL_2.GTXE2_IMUX9_8->GTXE2_CHANNEL_PCSRSVDIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_8" }, "GTX_CHANNEL_2.GTXE2_IMUX9_9->GTXE2_CHANNEL_PCSRSVDIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_9" } }, @@ -4402,690 +11310,6846 @@ "name": "X0Y0", "prefix": "GTXE2_CHANNEL", "site_pins": { - "CFGRESET": "GTXE2_CHANNEL_CFGRESET", - "CLKRSVD0": "GTXE2_CHANNEL_CLKRSVD0", - "CLKRSVD1": "GTXE2_CHANNEL_CLKRSVD1", - "CLKRSVD2": "GTXE2_CHANNEL_CLKRSVD2", - "CLKRSVD3": "GTXE2_CHANNEL_CLKRSVD3", - "CPLLFBCLKLOST": "GTXE2_CHANNEL_CPLLFBCLKLOST", - "CPLLLOCK": "GTXE2_CHANNEL_CPLLLOCK", - "CPLLLOCKDETCLK": "GTXE2_CHANNEL_CPLLLOCKDETCLK", - "CPLLLOCKEN": "GTXE2_CHANNEL_CPLLLOCKEN", - "CPLLPD": "GTXE2_CHANNEL_CPLLPD", - "CPLLREFCLKLOST": "GTXE2_CHANNEL_CPLLREFCLKLOST", - "CPLLREFCLKSEL0": "GTXE2_CHANNEL_CPLLREFCLKSEL0", - "CPLLREFCLKSEL1": "GTXE2_CHANNEL_CPLLREFCLKSEL1", - "CPLLREFCLKSEL2": "GTXE2_CHANNEL_CPLLREFCLKSEL2", - "CPLLRESET": "GTXE2_CHANNEL_CPLLRESET", - "DMONITOROUT0": "GTXE2_CHANNEL_DMONITOROUT0", - "DMONITOROUT1": "GTXE2_CHANNEL_DMONITOROUT1", - "DMONITOROUT2": "GTXE2_CHANNEL_DMONITOROUT2", - "DMONITOROUT3": "GTXE2_CHANNEL_DMONITOROUT3", - "DMONITOROUT4": "GTXE2_CHANNEL_DMONITOROUT4", - "DMONITOROUT5": "GTXE2_CHANNEL_DMONITOROUT5", - "DMONITOROUT6": "GTXE2_CHANNEL_DMONITOROUT6", - "DMONITOROUT7": "GTXE2_CHANNEL_DMONITOROUT7", - "DRPADDR0": "GTXE2_CHANNEL_DRPADDR0", - "DRPADDR1": "GTXE2_CHANNEL_DRPADDR1", - "DRPADDR2": "GTXE2_CHANNEL_DRPADDR2", - "DRPADDR3": "GTXE2_CHANNEL_DRPADDR3", - "DRPADDR4": "GTXE2_CHANNEL_DRPADDR4", - "DRPADDR5": "GTXE2_CHANNEL_DRPADDR5", - "DRPADDR6": "GTXE2_CHANNEL_DRPADDR6", - "DRPADDR7": "GTXE2_CHANNEL_DRPADDR7", - "DRPADDR8": "GTXE2_CHANNEL_DRPADDR8", - "DRPCLK": "GTXE2_CHANNEL_DRPCLK", - "DRPDI0": "GTXE2_CHANNEL_DRPDI0", - "DRPDI1": "GTXE2_CHANNEL_DRPDI1", - "DRPDI10": "GTXE2_CHANNEL_DRPDI10", - "DRPDI11": "GTXE2_CHANNEL_DRPDI11", - "DRPDI12": "GTXE2_CHANNEL_DRPDI12", - "DRPDI13": "GTXE2_CHANNEL_DRPDI13", - "DRPDI14": "GTXE2_CHANNEL_DRPDI14", - "DRPDI15": "GTXE2_CHANNEL_DRPDI15", - "DRPDI2": "GTXE2_CHANNEL_DRPDI2", - "DRPDI3": "GTXE2_CHANNEL_DRPDI3", - "DRPDI4": "GTXE2_CHANNEL_DRPDI4", - "DRPDI5": "GTXE2_CHANNEL_DRPDI5", - "DRPDI6": "GTXE2_CHANNEL_DRPDI6", - "DRPDI7": "GTXE2_CHANNEL_DRPDI7", - "DRPDI8": "GTXE2_CHANNEL_DRPDI8", - "DRPDI9": "GTXE2_CHANNEL_DRPDI9", - "DRPDO0": "GTXE2_CHANNEL_DRPDO0", - "DRPDO1": "GTXE2_CHANNEL_DRPDO1", - "DRPDO10": "GTXE2_CHANNEL_DRPDO10", - "DRPDO11": "GTXE2_CHANNEL_DRPDO11", - "DRPDO12": "GTXE2_CHANNEL_DRPDO12", - "DRPDO13": "GTXE2_CHANNEL_DRPDO13", - "DRPDO14": "GTXE2_CHANNEL_DRPDO14", - "DRPDO15": "GTXE2_CHANNEL_DRPDO15", - "DRPDO2": "GTXE2_CHANNEL_DRPDO2", - "DRPDO3": "GTXE2_CHANNEL_DRPDO3", - "DRPDO4": "GTXE2_CHANNEL_DRPDO4", - "DRPDO5": "GTXE2_CHANNEL_DRPDO5", - "DRPDO6": "GTXE2_CHANNEL_DRPDO6", - "DRPDO7": "GTXE2_CHANNEL_DRPDO7", - "DRPDO8": "GTXE2_CHANNEL_DRPDO8", - "DRPDO9": "GTXE2_CHANNEL_DRPDO9", - "DRPEN": "GTXE2_CHANNEL_DRPEN", - "DRPRDY": "GTXE2_CHANNEL_DRPRDY", - "DRPWE": "GTXE2_CHANNEL_DRPWE", - "EDTBYPASS": "GTXE2_CHANNEL_EDTBYPASS", - "EDTCLOCK": "GTXE2_CHANNEL_EDTCLOCK", - "EDTCONFIGURATION": "GTXE2_CHANNEL_EDTCONFIGURATION", - "EDTSINGLEBYPASSCHAIN": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", - "EDTUPDATE": "GTXE2_CHANNEL_EDTUPDATE", - "EYESCANDATAERROR": "GTXE2_CHANNEL_EYESCANDATAERROR", - "EYESCANMODE": "GTXE2_CHANNEL_EYESCANMODE", - "EYESCANRESET": "GTXE2_CHANNEL_EYESCANRESET", - "EYESCANTRIGGER": "GTXE2_CHANNEL_EYESCANTRIGGER", - "GTGREFCLK": "GTXE2_CHANNEL_GTGREFCLK", - "GTNORTHREFCLK0": "GTXE2_CHANNEL_GTNORTHREFCLK0", - "GTNORTHREFCLK1": "GTXE2_CHANNEL_GTNORTHREFCLK1", - "GTREFCLK0": "GTXE2_CHANNEL_GTREFCLK0", - "GTREFCLK1": "GTXE2_CHANNEL_GTREFCLK1", - "GTREFCLKMONITOR": "GTXE2_CHANNEL_GTREFCLKMONITOR", - "GTRESETSEL": "GTXE2_CHANNEL_GTRESETSEL", - "GTRSVD0": "GTXE2_CHANNEL_GTRSVD0", - "GTRSVD1": "GTXE2_CHANNEL_GTRSVD1", - "GTRSVD10": "GTXE2_CHANNEL_GTRSVD10", - "GTRSVD11": "GTXE2_CHANNEL_GTRSVD11", - "GTRSVD12": "GTXE2_CHANNEL_GTRSVD12", - "GTRSVD13": "GTXE2_CHANNEL_GTRSVD13", - "GTRSVD14": "GTXE2_CHANNEL_GTRSVD14", - "GTRSVD15": "GTXE2_CHANNEL_GTRSVD15", - "GTRSVD2": "GTXE2_CHANNEL_GTRSVD2", - "GTRSVD3": "GTXE2_CHANNEL_GTRSVD3", - "GTRSVD4": "GTXE2_CHANNEL_GTRSVD4", - "GTRSVD5": "GTXE2_CHANNEL_GTRSVD5", - "GTRSVD6": "GTXE2_CHANNEL_GTRSVD6", - "GTRSVD7": "GTXE2_CHANNEL_GTRSVD7", - "GTRSVD8": "GTXE2_CHANNEL_GTRSVD8", - "GTRSVD9": "GTXE2_CHANNEL_GTRSVD9", - "GTRXRESET": "GTXE2_CHANNEL_GTRXRESET", - "GTSOUTHREFCLK0": "GTXE2_CHANNEL_GTSOUTHREFCLK0", - "GTSOUTHREFCLK1": "GTXE2_CHANNEL_GTSOUTHREFCLK1", - "GTTXRESET": "GTXE2_CHANNEL_GTTXRESET", - "GTXRXN": "GTXE2_CHANNEL_RXN", - "GTXRXP": "GTXE2_CHANNEL_RXP", - "GTXTXN": "GTXE2_CHANNEL_TXN", - "GTXTXP": "GTXE2_CHANNEL_TXP", - "LOOPBACK0": "GTXE2_CHANNEL_LOOPBACK0", - "LOOPBACK1": "GTXE2_CHANNEL_LOOPBACK1", - "LOOPBACK2": "GTXE2_CHANNEL_LOOPBACK2", - "PCSRSVDIN0": "GTXE2_CHANNEL_PCSRSVDIN0", - "PCSRSVDIN1": "GTXE2_CHANNEL_PCSRSVDIN1", - "PCSRSVDIN10": "GTXE2_CHANNEL_PCSRSVDIN10", - "PCSRSVDIN11": "GTXE2_CHANNEL_PCSRSVDIN11", - "PCSRSVDIN12": "GTXE2_CHANNEL_PCSRSVDIN12", - "PCSRSVDIN13": "GTXE2_CHANNEL_PCSRSVDIN13", - "PCSRSVDIN14": "GTXE2_CHANNEL_PCSRSVDIN14", - "PCSRSVDIN15": "GTXE2_CHANNEL_PCSRSVDIN15", - "PCSRSVDIN2": "GTXE2_CHANNEL_PCSRSVDIN2", - "PCSRSVDIN20": "GTXE2_CHANNEL_PCSRSVDIN20", - "PCSRSVDIN21": "GTXE2_CHANNEL_PCSRSVDIN21", - "PCSRSVDIN22": "GTXE2_CHANNEL_PCSRSVDIN22", - "PCSRSVDIN23": "GTXE2_CHANNEL_PCSRSVDIN23", - "PCSRSVDIN24": "GTXE2_CHANNEL_PCSRSVDIN24", - "PCSRSVDIN3": "GTXE2_CHANNEL_PCSRSVDIN3", - "PCSRSVDIN4": "GTXE2_CHANNEL_PCSRSVDIN4", - "PCSRSVDIN5": "GTXE2_CHANNEL_PCSRSVDIN5", - "PCSRSVDIN6": "GTXE2_CHANNEL_PCSRSVDIN6", - "PCSRSVDIN7": "GTXE2_CHANNEL_PCSRSVDIN7", - "PCSRSVDIN8": "GTXE2_CHANNEL_PCSRSVDIN8", - "PCSRSVDIN9": "GTXE2_CHANNEL_PCSRSVDIN9", - "PCSRSVDOUT0": "GTXE2_CHANNEL_PCSRSVDOUT0", - "PCSRSVDOUT1": "GTXE2_CHANNEL_PCSRSVDOUT1", - "PCSRSVDOUT10": "GTXE2_CHANNEL_PCSRSVDOUT10", - "PCSRSVDOUT11": "GTXE2_CHANNEL_PCSRSVDOUT11", - "PCSRSVDOUT12": "GTXE2_CHANNEL_PCSRSVDOUT12", - "PCSRSVDOUT13": "GTXE2_CHANNEL_PCSRSVDOUT13", - "PCSRSVDOUT14": "GTXE2_CHANNEL_PCSRSVDOUT14", - "PCSRSVDOUT15": "GTXE2_CHANNEL_PCSRSVDOUT15", - "PCSRSVDOUT2": "GTXE2_CHANNEL_PCSRSVDOUT2", - "PCSRSVDOUT3": "GTXE2_CHANNEL_PCSRSVDOUT3", - "PCSRSVDOUT4": "GTXE2_CHANNEL_PCSRSVDOUT4", - "PCSRSVDOUT5": "GTXE2_CHANNEL_PCSRSVDOUT5", - "PCSRSVDOUT6": "GTXE2_CHANNEL_PCSRSVDOUT6", - "PCSRSVDOUT7": "GTXE2_CHANNEL_PCSRSVDOUT7", - "PCSRSVDOUT8": "GTXE2_CHANNEL_PCSRSVDOUT8", - "PCSRSVDOUT9": "GTXE2_CHANNEL_PCSRSVDOUT9", - "PHYSTATUS": "GTXE2_CHANNEL_PHYSTATUS", - "PMARSVDIN0": "GTXE2_CHANNEL_PMARSVDIN0", - "PMARSVDIN1": "GTXE2_CHANNEL_PMARSVDIN1", - "PMARSVDIN2": "GTXE2_CHANNEL_PMARSVDIN2", - "PMARSVDIN20": "GTXE2_CHANNEL_PMARSVDIN20", - "PMARSVDIN21": "GTXE2_CHANNEL_PMARSVDIN21", - "PMARSVDIN22": "GTXE2_CHANNEL_PMARSVDIN22", - "PMARSVDIN23": "GTXE2_CHANNEL_PMARSVDIN23", - "PMARSVDIN24": "GTXE2_CHANNEL_PMARSVDIN24", - "PMARSVDIN3": "GTXE2_CHANNEL_PMARSVDIN3", - "PMARSVDIN4": "GTXE2_CHANNEL_PMARSVDIN4", - "PMASCANCLK0": "GTXE2_CHANNEL_PMASCANCLK0", - "PMASCANCLK1": "GTXE2_CHANNEL_PMASCANCLK1", - "PMASCANCLK2": "GTXE2_CHANNEL_PMASCANCLK2", - "PMASCANCLK3": "GTXE2_CHANNEL_PMASCANCLK3", - "PMASCANCLK4": "GTXE2_CHANNEL_PMASCANCLK4", - "PMASCANENB": "GTXE2_CHANNEL_PMASCANENB", - "PMASCANIN0": "GTXE2_CHANNEL_PMASCANIN0", - "PMASCANIN1": "GTXE2_CHANNEL_PMASCANIN1", - "PMASCANIN2": "GTXE2_CHANNEL_PMASCANIN2", - "PMASCANIN3": "GTXE2_CHANNEL_PMASCANIN3", - "PMASCANIN4": "GTXE2_CHANNEL_PMASCANIN4", - "PMASCANMODEB": "GTXE2_CHANNEL_PMASCANMODEB", - "PMASCANOUT0": "GTXE2_CHANNEL_PMASCANOUT0", - "PMASCANOUT1": "GTXE2_CHANNEL_PMASCANOUT1", - "PMASCANOUT2": "GTXE2_CHANNEL_PMASCANOUT2", - "PMASCANOUT3": "GTXE2_CHANNEL_PMASCANOUT3", - "PMASCANOUT4": "GTXE2_CHANNEL_PMASCANOUT4", - "PMASCANRSTEN": "GTXE2_CHANNEL_PMASCANRSTEN", - "QPLLCLK": "GTXE2_CHANNEL_GTQPLLCLK", - "QPLLREFCLK": "GTXE2_CHANNEL_GTQPLLREFCLK", - "RESETOVRD": "GTXE2_CHANNEL_RESETOVRD", - "RX8B10BEN": "GTXE2_CHANNEL_RX8B10BEN", - "RXBUFRESET": "GTXE2_CHANNEL_RXBUFRESET", - "RXBUFSTATUS0": "GTXE2_CHANNEL_RXBUFSTATUS0", - "RXBUFSTATUS1": "GTXE2_CHANNEL_RXBUFSTATUS1", - "RXBUFSTATUS2": "GTXE2_CHANNEL_RXBUFSTATUS2", - "RXBYTEISALIGNED": "GTXE2_CHANNEL_RXBYTEISALIGNED", - "RXBYTEREALIGN": "GTXE2_CHANNEL_RXBYTEREALIGN", - "RXCDRFREQRESET": "GTXE2_CHANNEL_RXCDRFREQRESET", - "RXCDRHOLD": "GTXE2_CHANNEL_RXCDRHOLD", - "RXCDRLOCK": "GTXE2_CHANNEL_RXCDRLOCK", - "RXCDROVRDEN": "GTXE2_CHANNEL_RXCDROVRDEN", - "RXCDRRESET": "GTXE2_CHANNEL_RXCDRRESET", - "RXCDRRESETRSV": "GTXE2_CHANNEL_RXCDRRESETRSV", - "RXCHANBONDSEQ": "GTXE2_CHANNEL_RXCHANBONDSEQ", - "RXCHANISALIGNED": "GTXE2_CHANNEL_RXCHANISALIGNED", - "RXCHANREALIGN": "GTXE2_CHANNEL_RXCHANREALIGN", - "RXCHARISCOMMA0": "GTXE2_CHANNEL_RXCHARISCOMMA0", - "RXCHARISCOMMA1": "GTXE2_CHANNEL_RXCHARISCOMMA1", - "RXCHARISCOMMA2": "GTXE2_CHANNEL_RXCHARISCOMMA2", - "RXCHARISCOMMA3": "GTXE2_CHANNEL_RXCHARISCOMMA3", - "RXCHARISCOMMA4": "GTXE2_CHANNEL_RXCHARISCOMMA4", - "RXCHARISCOMMA5": "GTXE2_CHANNEL_RXCHARISCOMMA5", - "RXCHARISCOMMA6": "GTXE2_CHANNEL_RXCHARISCOMMA6", - "RXCHARISCOMMA7": "GTXE2_CHANNEL_RXCHARISCOMMA7", - "RXCHARISK0": "GTXE2_CHANNEL_RXCHARISK0", - "RXCHARISK1": "GTXE2_CHANNEL_RXCHARISK1", - "RXCHARISK2": "GTXE2_CHANNEL_RXCHARISK2", - "RXCHARISK3": "GTXE2_CHANNEL_RXCHARISK3", - "RXCHARISK4": "GTXE2_CHANNEL_RXCHARISK4", - "RXCHARISK5": "GTXE2_CHANNEL_RXCHARISK5", - "RXCHARISK6": "GTXE2_CHANNEL_RXCHARISK6", - "RXCHARISK7": "GTXE2_CHANNEL_RXCHARISK7", - "RXCHBONDEN": "GTXE2_CHANNEL_RXCHBONDEN", - "RXCHBONDI0": "GTXE2_CHANNEL_RXCHBONDI0", - "RXCHBONDI1": "GTXE2_CHANNEL_RXCHBONDI1", - "RXCHBONDI2": "GTXE2_CHANNEL_RXCHBONDI2", - "RXCHBONDI3": "GTXE2_CHANNEL_RXCHBONDI3", - "RXCHBONDI4": "GTXE2_CHANNEL_RXCHBONDI4", - "RXCHBONDLEVEL0": "GTXE2_CHANNEL_RXCHBONDLEVEL0", - "RXCHBONDLEVEL1": "GTXE2_CHANNEL_RXCHBONDLEVEL1", - "RXCHBONDLEVEL2": "GTXE2_CHANNEL_RXCHBONDLEVEL2", - "RXCHBONDMASTER": "GTXE2_CHANNEL_RXCHBONDMASTER", - "RXCHBONDO0": "GTXE2_CHANNEL_RXCHBONDO0", - "RXCHBONDO1": "GTXE2_CHANNEL_RXCHBONDO1", - "RXCHBONDO2": "GTXE2_CHANNEL_RXCHBONDO2", - "RXCHBONDO3": "GTXE2_CHANNEL_RXCHBONDO3", - "RXCHBONDO4": "GTXE2_CHANNEL_RXCHBONDO4", - "RXCHBONDSLAVE": "GTXE2_CHANNEL_RXCHBONDSLAVE", - "RXCLKCORCNT0": "GTXE2_CHANNEL_RXCLKCORCNT0", - "RXCLKCORCNT1": "GTXE2_CHANNEL_RXCLKCORCNT1", - "RXCOMINITDET": "GTXE2_CHANNEL_RXCOMINITDET", - "RXCOMMADET": "GTXE2_CHANNEL_RXCOMMADET", - "RXCOMMADETEN": "GTXE2_CHANNEL_RXCOMMADETEN", - "RXCOMSASDET": "GTXE2_CHANNEL_RXCOMSASDET", - "RXCOMWAKEDET": "GTXE2_CHANNEL_RXCOMWAKEDET", - "RXDATA0": "GTXE2_CHANNEL_RXDATA0", - "RXDATA1": "GTXE2_CHANNEL_RXDATA1", - "RXDATA10": "GTXE2_CHANNEL_RXDATA10", - "RXDATA11": "GTXE2_CHANNEL_RXDATA11", - "RXDATA12": "GTXE2_CHANNEL_RXDATA12", - "RXDATA13": "GTXE2_CHANNEL_RXDATA13", - "RXDATA14": "GTXE2_CHANNEL_RXDATA14", - "RXDATA15": "GTXE2_CHANNEL_RXDATA15", - "RXDATA16": "GTXE2_CHANNEL_RXDATA16", - "RXDATA17": "GTXE2_CHANNEL_RXDATA17", - "RXDATA18": "GTXE2_CHANNEL_RXDATA18", - "RXDATA19": "GTXE2_CHANNEL_RXDATA19", - "RXDATA2": "GTXE2_CHANNEL_RXDATA2", - "RXDATA20": "GTXE2_CHANNEL_RXDATA20", - "RXDATA21": "GTXE2_CHANNEL_RXDATA21", - "RXDATA22": "GTXE2_CHANNEL_RXDATA22", - "RXDATA23": "GTXE2_CHANNEL_RXDATA23", - "RXDATA24": "GTXE2_CHANNEL_RXDATA24", - "RXDATA25": "GTXE2_CHANNEL_RXDATA25", - "RXDATA26": "GTXE2_CHANNEL_RXDATA26", - "RXDATA27": "GTXE2_CHANNEL_RXDATA27", - "RXDATA28": "GTXE2_CHANNEL_RXDATA28", - "RXDATA29": "GTXE2_CHANNEL_RXDATA29", - "RXDATA3": "GTXE2_CHANNEL_RXDATA3", - "RXDATA30": "GTXE2_CHANNEL_RXDATA30", - "RXDATA31": "GTXE2_CHANNEL_RXDATA31", - "RXDATA32": "GTXE2_CHANNEL_RXDATA32", - "RXDATA33": "GTXE2_CHANNEL_RXDATA33", - "RXDATA34": "GTXE2_CHANNEL_RXDATA34", - "RXDATA35": "GTXE2_CHANNEL_RXDATA35", - "RXDATA36": "GTXE2_CHANNEL_RXDATA36", - "RXDATA37": "GTXE2_CHANNEL_RXDATA37", - "RXDATA38": "GTXE2_CHANNEL_RXDATA38", - "RXDATA39": "GTXE2_CHANNEL_RXDATA39", - "RXDATA4": "GTXE2_CHANNEL_RXDATA4", - "RXDATA40": "GTXE2_CHANNEL_RXDATA40", - "RXDATA41": "GTXE2_CHANNEL_RXDATA41", - "RXDATA42": "GTXE2_CHANNEL_RXDATA42", - "RXDATA43": "GTXE2_CHANNEL_RXDATA43", - "RXDATA44": "GTXE2_CHANNEL_RXDATA44", - "RXDATA45": "GTXE2_CHANNEL_RXDATA45", - "RXDATA46": "GTXE2_CHANNEL_RXDATA46", - "RXDATA47": "GTXE2_CHANNEL_RXDATA47", - "RXDATA48": "GTXE2_CHANNEL_RXDATA48", - "RXDATA49": "GTXE2_CHANNEL_RXDATA49", - "RXDATA5": "GTXE2_CHANNEL_RXDATA5", - "RXDATA50": "GTXE2_CHANNEL_RXDATA50", - "RXDATA51": "GTXE2_CHANNEL_RXDATA51", - "RXDATA52": "GTXE2_CHANNEL_RXDATA52", - "RXDATA53": "GTXE2_CHANNEL_RXDATA53", - "RXDATA54": "GTXE2_CHANNEL_RXDATA54", - "RXDATA55": "GTXE2_CHANNEL_RXDATA55", - "RXDATA56": "GTXE2_CHANNEL_RXDATA56", - "RXDATA57": "GTXE2_CHANNEL_RXDATA57", - "RXDATA58": "GTXE2_CHANNEL_RXDATA58", - "RXDATA59": "GTXE2_CHANNEL_RXDATA59", - "RXDATA6": "GTXE2_CHANNEL_RXDATA6", - "RXDATA60": "GTXE2_CHANNEL_RXDATA60", - "RXDATA61": "GTXE2_CHANNEL_RXDATA61", - "RXDATA62": "GTXE2_CHANNEL_RXDATA62", - "RXDATA63": "GTXE2_CHANNEL_RXDATA63", - "RXDATA7": "GTXE2_CHANNEL_RXDATA7", - "RXDATA8": "GTXE2_CHANNEL_RXDATA8", - "RXDATA9": "GTXE2_CHANNEL_RXDATA9", - "RXDATAVALID": "GTXE2_CHANNEL_RXDATAVALID", - "RXDDIEN": "GTXE2_CHANNEL_RXDDIEN", - "RXDEBUGPULSE": "GTXE2_CHANNEL_RXDEBUGPULSE", - "RXDFEAGCHOLD": "GTXE2_CHANNEL_RXDFEAGCHOLD", - "RXDFEAGCOVRDEN": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", - "RXDFECM1EN": "GTXE2_CHANNEL_RXDFECM1EN", - "RXDFELFHOLD": "GTXE2_CHANNEL_RXDFELFHOLD", - "RXDFELFOVRDEN": "GTXE2_CHANNEL_RXDFELFOVRDEN", - "RXDFELPMRESET": "GTXE2_CHANNEL_RXDFELPMRESET", - "RXDFETAP2HOLD": "GTXE2_CHANNEL_RXDFETAP2HOLD", - "RXDFETAP2OVRDEN": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", - "RXDFETAP3HOLD": "GTXE2_CHANNEL_RXDFETAP3HOLD", - "RXDFETAP3OVRDEN": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", - "RXDFETAP4HOLD": "GTXE2_CHANNEL_RXDFETAP4HOLD", - "RXDFETAP4OVRDEN": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", - "RXDFETAP5HOLD": "GTXE2_CHANNEL_RXDFETAP5HOLD", - "RXDFETAP5OVRDEN": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", - "RXDFEUTHOLD": "GTXE2_CHANNEL_RXDFEUTHOLD", - "RXDFEUTOVRDEN": "GTXE2_CHANNEL_RXDFEUTOVRDEN", - "RXDFEVPHOLD": "GTXE2_CHANNEL_RXDFEVPHOLD", - "RXDFEVPOVRDEN": "GTXE2_CHANNEL_RXDFEVPOVRDEN", - "RXDFEVSEN": "GTXE2_CHANNEL_RXDFEVSEN", - "RXDFEXYDEN": "GTXE2_CHANNEL_RXDFEXYDEN", - "RXDFEXYDHOLD": "GTXE2_CHANNEL_RXDFEXYDHOLD", - "RXDFEXYDOVRDEN": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", - "RXDISPERR0": "GTXE2_CHANNEL_RXDISPERR0", - "RXDISPERR1": "GTXE2_CHANNEL_RXDISPERR1", - "RXDISPERR2": "GTXE2_CHANNEL_RXDISPERR2", - "RXDISPERR3": "GTXE2_CHANNEL_RXDISPERR3", - "RXDISPERR4": "GTXE2_CHANNEL_RXDISPERR4", - "RXDISPERR5": "GTXE2_CHANNEL_RXDISPERR5", - "RXDISPERR6": "GTXE2_CHANNEL_RXDISPERR6", - "RXDISPERR7": "GTXE2_CHANNEL_RXDISPERR7", - "RXDLYBYPASS": "GTXE2_CHANNEL_RXDLYBYPASS", - "RXDLYEN": "GTXE2_CHANNEL_RXDLYEN", - "RXDLYOVRDEN": "GTXE2_CHANNEL_RXDLYOVRDEN", - "RXDLYSRESET": "GTXE2_CHANNEL_RXDLYSRESET", - "RXDLYSRESETDONE": "GTXE2_CHANNEL_RXDLYSRESETDONE", - "RXDLYTESTENB": "GTXE2_CHANNEL_RXDLYTESTENB", - "RXELECIDLE": "GTXE2_CHANNEL_RXELECIDLE", - "RXELECIDLEMODE0": "GTXE2_CHANNEL_RXELECIDLEMODE0", - "RXELECIDLEMODE1": "GTXE2_CHANNEL_RXELECIDLEMODE1", - "RXGEARBOXSLIP": "GTXE2_CHANNEL_RXGEARBOXSLIP", - "RXHEADER0": "GTXE2_CHANNEL_RXHEADER0", - "RXHEADER1": "GTXE2_CHANNEL_RXHEADER1", - "RXHEADER2": "GTXE2_CHANNEL_RXHEADER2", - "RXHEADERVALID": "GTXE2_CHANNEL_RXHEADERVALID", - "RXLPMEN": "GTXE2_CHANNEL_RXLPMEN", - "RXLPMHFHOLD": "GTXE2_CHANNEL_RXLPMHFHOLD", - "RXLPMHFOVRDEN": "GTXE2_CHANNEL_RXLPMHFOVRDEN", - "RXLPMLFHOLD": "GTXE2_CHANNEL_RXLPMLFHOLD", - "RXLPMLFKLOVRDEN": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", - "RXMCOMMAALIGNEN": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", - "RXMONITOROUT0": "GTXE2_CHANNEL_RXMONITOROUT0", - "RXMONITOROUT1": "GTXE2_CHANNEL_RXMONITOROUT1", - "RXMONITOROUT2": "GTXE2_CHANNEL_RXMONITOROUT2", - "RXMONITOROUT3": "GTXE2_CHANNEL_RXMONITOROUT3", - "RXMONITOROUT4": "GTXE2_CHANNEL_RXMONITOROUT4", - "RXMONITOROUT5": "GTXE2_CHANNEL_RXMONITOROUT5", - "RXMONITOROUT6": "GTXE2_CHANNEL_RXMONITOROUT6", - "RXMONITORSEL0": "GTXE2_CHANNEL_RXMONITORSEL0", - "RXMONITORSEL1": "GTXE2_CHANNEL_RXMONITORSEL1", - "RXNOTINTABLE0": "GTXE2_CHANNEL_RXNOTINTABLE0", - "RXNOTINTABLE1": "GTXE2_CHANNEL_RXNOTINTABLE1", - "RXNOTINTABLE2": "GTXE2_CHANNEL_RXNOTINTABLE2", - "RXNOTINTABLE3": "GTXE2_CHANNEL_RXNOTINTABLE3", - "RXNOTINTABLE4": "GTXE2_CHANNEL_RXNOTINTABLE4", - "RXNOTINTABLE5": "GTXE2_CHANNEL_RXNOTINTABLE5", - "RXNOTINTABLE6": "GTXE2_CHANNEL_RXNOTINTABLE6", - "RXNOTINTABLE7": "GTXE2_CHANNEL_RXNOTINTABLE7", - "RXOOBRESET": "GTXE2_CHANNEL_RXOOBRESET", - "RXOSHOLD": "GTXE2_CHANNEL_RXOSHOLD", - "RXOSOVRDEN": "GTXE2_CHANNEL_RXOSOVRDEN", - "RXOUTCLK": "GTXE2_CHANNEL_GTRXOUTCLK_2", - "RXOUTCLKFABRIC": "GTXE2_CHANNEL_RXOUTCLKFABRIC", - "RXOUTCLKPCS": "GTXE2_CHANNEL_RXOUTCLKPCS", - "RXOUTCLKSEL0": "GTXE2_CHANNEL_RXOUTCLKSEL0", - "RXOUTCLKSEL1": "GTXE2_CHANNEL_RXOUTCLKSEL1", - "RXOUTCLKSEL2": "GTXE2_CHANNEL_RXOUTCLKSEL2", - "RXPCD1DONE": "GTXE2_CHANNEL_RXPCD1DONE", - "RXPCOMMAALIGNEN": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", - "RXPCSRESET": "GTXE2_CHANNEL_RXPCSRESET", - "RXPD0": "GTXE2_CHANNEL_RXPD0", - "RXPD1": "GTXE2_CHANNEL_RXPD1", - "RXPHALIGN": "GTXE2_CHANNEL_RXPHALIGN", - "RXPHALIGNDONE": "GTXE2_CHANNEL_RXPHALIGNDONE", - "RXPHALIGNEN": "GTXE2_CHANNEL_RXPHALIGNEN", - "RXPHDLYPD": "GTXE2_CHANNEL_RXPHDLYPD", - "RXPHDLYRESET": "GTXE2_CHANNEL_RXPHDLYRESET", - "RXPHMONITOR0": "GTXE2_CHANNEL_RXPHMONITOR0", - "RXPHMONITOR1": "GTXE2_CHANNEL_RXPHMONITOR1", - "RXPHMONITOR2": "GTXE2_CHANNEL_RXPHMONITOR2", - "RXPHMONITOR3": "GTXE2_CHANNEL_RXPHMONITOR3", - "RXPHMONITOR4": "GTXE2_CHANNEL_RXPHMONITOR4", - "RXPHOVRDEN": "GTXE2_CHANNEL_RXPHOVRDEN", - "RXPHSLIPMONITOR0": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", - "RXPHSLIPMONITOR1": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", - "RXPHSLIPMONITOR2": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", - "RXPHSLIPMONITOR3": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", - "RXPHSLIPMONITOR4": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", - "RXPMARESET": "GTXE2_CHANNEL_RXPMARESET", - "RXPOLARITY": "GTXE2_CHANNEL_RXPOLARITY", - "RXPRBSCNTRESET": "GTXE2_CHANNEL_RXPRBSCNTRESET", - "RXPRBSERR": "GTXE2_CHANNEL_RXPRBSERR", - "RXPRBSSEL0": "GTXE2_CHANNEL_RXPRBSSEL0", - "RXPRBSSEL1": "GTXE2_CHANNEL_RXPRBSSEL1", - "RXPRBSSEL2": "GTXE2_CHANNEL_RXPRBSSEL2", - "RXQPIEN": "GTXE2_CHANNEL_RXQPIEN", - "RXQPISENN": "GTXE2_CHANNEL_RXQPISENN", - "RXQPISENP": "GTXE2_CHANNEL_RXQPISENP", - "RXRATE0": "GTXE2_CHANNEL_RXRATE0", - "RXRATE1": "GTXE2_CHANNEL_RXRATE1", - "RXRATE2": "GTXE2_CHANNEL_RXRATE2", - "RXRATEDONE": "GTXE2_CHANNEL_RXRATEDONE", - "RXRESETDONE": "GTXE2_CHANNEL_RXRESETDONE", - "RXSLIDE": "GTXE2_CHANNEL_RXSLIDE", - "RXSTARTOFSEQ": "GTXE2_CHANNEL_RXSTARTOFSEQ", - "RXSTATUS0": "GTXE2_CHANNEL_RXSTATUS0", - "RXSTATUS1": "GTXE2_CHANNEL_RXSTATUS1", - "RXSTATUS2": "GTXE2_CHANNEL_RXSTATUS2", - "RXSYSCLKSEL0": "GTXE2_CHANNEL_RXSYSCLKSEL0", - "RXSYSCLKSEL1": "GTXE2_CHANNEL_RXSYSCLKSEL1", - "RXUSERRDY": "GTXE2_CHANNEL_RXUSERRDY", - "RXUSRCLK": "GTXE2_CHANNEL_RXUSRCLK", - "RXUSRCLK2": "GTXE2_CHANNEL_RXUSRCLK2", - "RXVALID": "GTXE2_CHANNEL_RXVALID", - "SCANCLK": "GTXE2_CHANNEL_SCANCLK", - "SCANENB": "GTXE2_CHANNEL_SCANENB", - "SCANIN0": "GTXE2_CHANNEL_SCANIN0", - "SCANIN1": "GTXE2_CHANNEL_SCANIN1", - "SCANIN2": "GTXE2_CHANNEL_SCANIN2", - "SCANIN3": "GTXE2_CHANNEL_SCANIN3", - "SCANIN4": "GTXE2_CHANNEL_SCANIN4", - "SCANMODEB": "GTXE2_CHANNEL_SCANMODEB", - "SCANOUT0": "GTXE2_CHANNEL_SCANOUT0", - "SCANOUT1": "GTXE2_CHANNEL_SCANOUT1", - "SCANOUT2": "GTXE2_CHANNEL_SCANOUT2", - "SCANOUT3": "GTXE2_CHANNEL_SCANOUT3", - "SCANOUT4": "GTXE2_CHANNEL_SCANOUT4", - "SETERRSTATUS": "GTXE2_CHANNEL_SETERRSTATUS", - "TSTCLK0": "GTXE2_CHANNEL_TSTCLK0", - "TSTCLK1": "GTXE2_CHANNEL_TSTCLK1", - "TSTIN0": "GTXE2_CHANNEL_TSTIN0", - "TSTIN1": "GTXE2_CHANNEL_TSTIN1", - "TSTIN10": "GTXE2_CHANNEL_TSTIN10", - "TSTIN11": "GTXE2_CHANNEL_TSTIN11", - "TSTIN12": "GTXE2_CHANNEL_TSTIN12", - "TSTIN13": "GTXE2_CHANNEL_TSTIN13", - "TSTIN14": "GTXE2_CHANNEL_TSTIN14", - "TSTIN15": "GTXE2_CHANNEL_TSTIN15", - "TSTIN16": "GTXE2_CHANNEL_TSTIN16", - "TSTIN17": "GTXE2_CHANNEL_TSTIN17", - "TSTIN18": "GTXE2_CHANNEL_TSTIN18", - "TSTIN19": "GTXE2_CHANNEL_TSTIN19", - "TSTIN2": "GTXE2_CHANNEL_TSTIN2", - "TSTIN3": "GTXE2_CHANNEL_TSTIN3", - "TSTIN4": "GTXE2_CHANNEL_TSTIN4", - "TSTIN5": "GTXE2_CHANNEL_TSTIN5", - "TSTIN6": "GTXE2_CHANNEL_TSTIN6", - "TSTIN7": "GTXE2_CHANNEL_TSTIN7", - "TSTIN8": "GTXE2_CHANNEL_TSTIN8", - "TSTIN9": "GTXE2_CHANNEL_TSTIN9", - "TSTOUT0": "GTXE2_CHANNEL_TSTOUT0", - "TSTOUT1": "GTXE2_CHANNEL_TSTOUT1", - "TSTOUT2": "GTXE2_CHANNEL_TSTOUT2", - "TSTOUT3": "GTXE2_CHANNEL_TSTOUT3", - "TSTOUT4": "GTXE2_CHANNEL_TSTOUT4", - "TSTOUT5": "GTXE2_CHANNEL_TSTOUT5", - "TSTOUT6": "GTXE2_CHANNEL_TSTOUT6", - "TSTOUT7": "GTXE2_CHANNEL_TSTOUT7", - "TSTOUT8": "GTXE2_CHANNEL_TSTOUT8", - "TSTOUT9": "GTXE2_CHANNEL_TSTOUT9", - "TSTPD0": "GTXE2_CHANNEL_TSTPD0", - "TSTPD1": "GTXE2_CHANNEL_TSTPD1", - "TSTPD2": "GTXE2_CHANNEL_TSTPD2", - "TSTPD3": "GTXE2_CHANNEL_TSTPD3", - "TSTPD4": "GTXE2_CHANNEL_TSTPD4", - "TSTPDOVRDB": "GTXE2_CHANNEL_TSTPDOVRDB", - "TX8B10BBYPASS0": "GTXE2_CHANNEL_TX8B10BBYPASS0", - "TX8B10BBYPASS1": "GTXE2_CHANNEL_TX8B10BBYPASS1", - "TX8B10BBYPASS2": "GTXE2_CHANNEL_TX8B10BBYPASS2", - "TX8B10BBYPASS3": "GTXE2_CHANNEL_TX8B10BBYPASS3", - "TX8B10BBYPASS4": "GTXE2_CHANNEL_TX8B10BBYPASS4", - "TX8B10BBYPASS5": "GTXE2_CHANNEL_TX8B10BBYPASS5", - "TX8B10BBYPASS6": "GTXE2_CHANNEL_TX8B10BBYPASS6", - "TX8B10BBYPASS7": "GTXE2_CHANNEL_TX8B10BBYPASS7", - "TX8B10BEN": "GTXE2_CHANNEL_TX8B10BEN", - "TXBUFDIFFCTRL0": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", - "TXBUFDIFFCTRL1": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", - "TXBUFDIFFCTRL2": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", - "TXBUFSTATUS0": "GTXE2_CHANNEL_TXBUFSTATUS0", - "TXBUFSTATUS1": "GTXE2_CHANNEL_TXBUFSTATUS1", - "TXCHARDISPMODE0": "GTXE2_CHANNEL_TXCHARDISPMODE0", - "TXCHARDISPMODE1": "GTXE2_CHANNEL_TXCHARDISPMODE1", - "TXCHARDISPMODE2": "GTXE2_CHANNEL_TXCHARDISPMODE2", - "TXCHARDISPMODE3": "GTXE2_CHANNEL_TXCHARDISPMODE3", - "TXCHARDISPMODE4": "GTXE2_CHANNEL_TXCHARDISPMODE4", - "TXCHARDISPMODE5": "GTXE2_CHANNEL_TXCHARDISPMODE5", - "TXCHARDISPMODE6": "GTXE2_CHANNEL_TXCHARDISPMODE6", - "TXCHARDISPMODE7": "GTXE2_CHANNEL_TXCHARDISPMODE7", - "TXCHARDISPVAL0": "GTXE2_CHANNEL_TXCHARDISPVAL0", - "TXCHARDISPVAL1": "GTXE2_CHANNEL_TXCHARDISPVAL1", - "TXCHARDISPVAL2": "GTXE2_CHANNEL_TXCHARDISPVAL2", - "TXCHARDISPVAL3": "GTXE2_CHANNEL_TXCHARDISPVAL3", - "TXCHARDISPVAL4": "GTXE2_CHANNEL_TXCHARDISPVAL4", - "TXCHARDISPVAL5": "GTXE2_CHANNEL_TXCHARDISPVAL5", - "TXCHARDISPVAL6": "GTXE2_CHANNEL_TXCHARDISPVAL6", - "TXCHARDISPVAL7": "GTXE2_CHANNEL_TXCHARDISPVAL7", - "TXCHARISK0": "GTXE2_CHANNEL_TXCHARISK0", - "TXCHARISK1": "GTXE2_CHANNEL_TXCHARISK1", - "TXCHARISK2": "GTXE2_CHANNEL_TXCHARISK2", - "TXCHARISK3": "GTXE2_CHANNEL_TXCHARISK3", - "TXCHARISK4": "GTXE2_CHANNEL_TXCHARISK4", - "TXCHARISK5": "GTXE2_CHANNEL_TXCHARISK5", - "TXCHARISK6": "GTXE2_CHANNEL_TXCHARISK6", - "TXCHARISK7": "GTXE2_CHANNEL_TXCHARISK7", - "TXCOMFINISH": "GTXE2_CHANNEL_TXCOMFINISH", - "TXCOMINIT": "GTXE2_CHANNEL_TXCOMINIT", - "TXCOMSAS": "GTXE2_CHANNEL_TXCOMSAS", - "TXCOMWAKE": "GTXE2_CHANNEL_TXCOMWAKE", - "TXDATA0": "GTXE2_CHANNEL_TXDATA0", - "TXDATA1": "GTXE2_CHANNEL_TXDATA1", - "TXDATA10": "GTXE2_CHANNEL_TXDATA10", - "TXDATA11": "GTXE2_CHANNEL_TXDATA11", - "TXDATA12": "GTXE2_CHANNEL_TXDATA12", - "TXDATA13": "GTXE2_CHANNEL_TXDATA13", - "TXDATA14": "GTXE2_CHANNEL_TXDATA14", - "TXDATA15": "GTXE2_CHANNEL_TXDATA15", - "TXDATA16": "GTXE2_CHANNEL_TXDATA16", - "TXDATA17": "GTXE2_CHANNEL_TXDATA17", - "TXDATA18": "GTXE2_CHANNEL_TXDATA18", - "TXDATA19": "GTXE2_CHANNEL_TXDATA19", - "TXDATA2": "GTXE2_CHANNEL_TXDATA2", - "TXDATA20": "GTXE2_CHANNEL_TXDATA20", - "TXDATA21": "GTXE2_CHANNEL_TXDATA21", - "TXDATA22": "GTXE2_CHANNEL_TXDATA22", - "TXDATA23": "GTXE2_CHANNEL_TXDATA23", - "TXDATA24": "GTXE2_CHANNEL_TXDATA24", - "TXDATA25": "GTXE2_CHANNEL_TXDATA25", - "TXDATA26": "GTXE2_CHANNEL_TXDATA26", - "TXDATA27": "GTXE2_CHANNEL_TXDATA27", - "TXDATA28": "GTXE2_CHANNEL_TXDATA28", - "TXDATA29": "GTXE2_CHANNEL_TXDATA29", - "TXDATA3": "GTXE2_CHANNEL_TXDATA3", - "TXDATA30": "GTXE2_CHANNEL_TXDATA30", - "TXDATA31": "GTXE2_CHANNEL_TXDATA31", - "TXDATA32": "GTXE2_CHANNEL_TXDATA32", - "TXDATA33": "GTXE2_CHANNEL_TXDATA33", - "TXDATA34": "GTXE2_CHANNEL_TXDATA34", - "TXDATA35": "GTXE2_CHANNEL_TXDATA35", - "TXDATA36": "GTXE2_CHANNEL_TXDATA36", - "TXDATA37": "GTXE2_CHANNEL_TXDATA37", - "TXDATA38": "GTXE2_CHANNEL_TXDATA38", - "TXDATA39": "GTXE2_CHANNEL_TXDATA39", - "TXDATA4": "GTXE2_CHANNEL_TXDATA4", - "TXDATA40": "GTXE2_CHANNEL_TXDATA40", - "TXDATA41": "GTXE2_CHANNEL_TXDATA41", - "TXDATA42": "GTXE2_CHANNEL_TXDATA42", - "TXDATA43": "GTXE2_CHANNEL_TXDATA43", - "TXDATA44": "GTXE2_CHANNEL_TXDATA44", - "TXDATA45": "GTXE2_CHANNEL_TXDATA45", - "TXDATA46": "GTXE2_CHANNEL_TXDATA46", - "TXDATA47": "GTXE2_CHANNEL_TXDATA47", - "TXDATA48": "GTXE2_CHANNEL_TXDATA48", - "TXDATA49": "GTXE2_CHANNEL_TXDATA49", - "TXDATA5": "GTXE2_CHANNEL_TXDATA5", - "TXDATA50": "GTXE2_CHANNEL_TXDATA50", - "TXDATA51": "GTXE2_CHANNEL_TXDATA51", - "TXDATA52": "GTXE2_CHANNEL_TXDATA52", - "TXDATA53": "GTXE2_CHANNEL_TXDATA53", - "TXDATA54": "GTXE2_CHANNEL_TXDATA54", - "TXDATA55": "GTXE2_CHANNEL_TXDATA55", - "TXDATA56": "GTXE2_CHANNEL_TXDATA56", - "TXDATA57": "GTXE2_CHANNEL_TXDATA57", - "TXDATA58": "GTXE2_CHANNEL_TXDATA58", - "TXDATA59": "GTXE2_CHANNEL_TXDATA59", - "TXDATA6": "GTXE2_CHANNEL_TXDATA6", - "TXDATA60": "GTXE2_CHANNEL_TXDATA60", - "TXDATA61": "GTXE2_CHANNEL_TXDATA61", - "TXDATA62": "GTXE2_CHANNEL_TXDATA62", - "TXDATA63": "GTXE2_CHANNEL_TXDATA63", - "TXDATA7": "GTXE2_CHANNEL_TXDATA7", - "TXDATA8": "GTXE2_CHANNEL_TXDATA8", - "TXDATA9": "GTXE2_CHANNEL_TXDATA9", - "TXDEEMPH": "GTXE2_CHANNEL_TXDEEMPH", - "TXDETECTRX": "GTXE2_CHANNEL_TXDETECTRX", - "TXDIFFCTRL0": "GTXE2_CHANNEL_TXDIFFCTRL0", - "TXDIFFCTRL1": "GTXE2_CHANNEL_TXDIFFCTRL1", - "TXDIFFCTRL2": "GTXE2_CHANNEL_TXDIFFCTRL2", - "TXDIFFCTRL3": "GTXE2_CHANNEL_TXDIFFCTRL3", - "TXDIFFPD": "GTXE2_CHANNEL_TXDIFFPD", - "TXDLYBYPASS": "GTXE2_CHANNEL_TXDLYBYPASS", - "TXDLYEN": "GTXE2_CHANNEL_TXDLYEN", - "TXDLYHOLD": "GTXE2_CHANNEL_TXDLYHOLD", - "TXDLYOVRDEN": "GTXE2_CHANNEL_TXDLYOVRDEN", - "TXDLYSRESET": "GTXE2_CHANNEL_TXDLYSRESET", - "TXDLYSRESETDONE": "GTXE2_CHANNEL_TXDLYSRESETDONE", - "TXDLYTESTENB": "GTXE2_CHANNEL_TXDLYTESTENB", - "TXDLYUPDOWN": "GTXE2_CHANNEL_TXDLYUPDOWN", - "TXELECIDLE": "GTXE2_CHANNEL_TXELECIDLE", - "TXGEARBOXREADY": "GTXE2_CHANNEL_TXGEARBOXREADY", - "TXHEADER0": "GTXE2_CHANNEL_TXHEADER0", - "TXHEADER1": "GTXE2_CHANNEL_TXHEADER1", - "TXHEADER2": "GTXE2_CHANNEL_TXHEADER2", - "TXINHIBIT": "GTXE2_CHANNEL_TXINHIBIT", - "TXMAINCURSOR0": "GTXE2_CHANNEL_TXMAINCURSOR0", - "TXMAINCURSOR1": "GTXE2_CHANNEL_TXMAINCURSOR1", - "TXMAINCURSOR2": "GTXE2_CHANNEL_TXMAINCURSOR2", - "TXMAINCURSOR3": "GTXE2_CHANNEL_TXMAINCURSOR3", - "TXMAINCURSOR4": "GTXE2_CHANNEL_TXMAINCURSOR4", - "TXMAINCURSOR5": "GTXE2_CHANNEL_TXMAINCURSOR5", - "TXMAINCURSOR6": "GTXE2_CHANNEL_TXMAINCURSOR6", - "TXMARGIN0": "GTXE2_CHANNEL_TXMARGIN0", - "TXMARGIN1": "GTXE2_CHANNEL_TXMARGIN1", - "TXMARGIN2": "GTXE2_CHANNEL_TXMARGIN2", - "TXOUTCLK": "GTXE2_CHANNEL_GTTXOUTCLK_2", - "TXOUTCLKFABRIC": "GTXE2_CHANNEL_TXOUTCLKFABRIC", - "TXOUTCLKPCS": "GTXE2_CHANNEL_TXOUTCLKPCS", - "TXOUTCLKSEL0": "GTXE2_CHANNEL_TXOUTCLKSEL0", - "TXOUTCLKSEL1": "GTXE2_CHANNEL_TXOUTCLKSEL1", - "TXOUTCLKSEL2": "GTXE2_CHANNEL_TXOUTCLKSEL2", - "TXPCSRESET": "GTXE2_CHANNEL_TXPCSRESET", - "TXPD0": "GTXE2_CHANNEL_TXPD0", - "TXPD1": "GTXE2_CHANNEL_TXPD1", - "TXPDELECIDLEMODE": "GTXE2_CHANNEL_TXPDELECIDLEMODE", - "TXPHALIGN": "GTXE2_CHANNEL_TXPHALIGN", - "TXPHALIGNDONE": "GTXE2_CHANNEL_TXPHALIGNDONE", - "TXPHALIGNEN": "GTXE2_CHANNEL_TXPHALIGNEN", - "TXPHDLYPD": "GTXE2_CHANNEL_TXPHDLYPD", - "TXPHDLYRESET": "GTXE2_CHANNEL_TXPHDLYRESET", - "TXPHDLYTSTCLK": "GTXE2_CHANNEL_TXPHDLYTSTCLK", - "TXPHINIT": "GTXE2_CHANNEL_TXPHINIT", - "TXPHINITDONE": "GTXE2_CHANNEL_TXPHINITDONE", - "TXPHOVRDEN": "GTXE2_CHANNEL_TXPHOVRDEN", - "TXPISOPD": "GTXE2_CHANNEL_TXPISOPD", - "TXPMARESET": "GTXE2_CHANNEL_TXPMARESET", - "TXPOLARITY": "GTXE2_CHANNEL_TXPOLARITY", - "TXPOSTCURSOR0": "GTXE2_CHANNEL_TXPOSTCURSOR0", - "TXPOSTCURSOR1": "GTXE2_CHANNEL_TXPOSTCURSOR1", - "TXPOSTCURSOR2": "GTXE2_CHANNEL_TXPOSTCURSOR2", - "TXPOSTCURSOR3": "GTXE2_CHANNEL_TXPOSTCURSOR3", - "TXPOSTCURSOR4": "GTXE2_CHANNEL_TXPOSTCURSOR4", - "TXPOSTCURSORINV": "GTXE2_CHANNEL_TXPOSTCURSORINV", - "TXPRBSFORCEERR": "GTXE2_CHANNEL_TXPRBSFORCEERR", - "TXPRBSSEL0": "GTXE2_CHANNEL_TXPRBSSEL0", - "TXPRBSSEL1": "GTXE2_CHANNEL_TXPRBSSEL1", - "TXPRBSSEL2": "GTXE2_CHANNEL_TXPRBSSEL2", - "TXPRECURSOR0": "GTXE2_CHANNEL_TXPRECURSOR0", - "TXPRECURSOR1": "GTXE2_CHANNEL_TXPRECURSOR1", - "TXPRECURSOR2": "GTXE2_CHANNEL_TXPRECURSOR2", - "TXPRECURSOR3": "GTXE2_CHANNEL_TXPRECURSOR3", - "TXPRECURSOR4": "GTXE2_CHANNEL_TXPRECURSOR4", - "TXPRECURSORINV": "GTXE2_CHANNEL_TXPRECURSORINV", - "TXQPIBIASEN": "GTXE2_CHANNEL_TXQPIBIASEN", - "TXQPISENN": "GTXE2_CHANNEL_TXQPISENN", - "TXQPISENP": "GTXE2_CHANNEL_TXQPISENP", - "TXQPISTRONGPDOWN": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", - "TXQPIWEAKPUP": "GTXE2_CHANNEL_TXQPIWEAKPUP", - "TXRATE0": "GTXE2_CHANNEL_TXRATE0", - "TXRATE1": "GTXE2_CHANNEL_TXRATE1", - "TXRATE2": "GTXE2_CHANNEL_TXRATE2", - "TXRATEDONE": "GTXE2_CHANNEL_TXRATEDONE", - "TXRESETDONE": "GTXE2_CHANNEL_TXRESETDONE", - "TXRUNDISP0": "GTXE2_CHANNEL_TXRUNDISP0", - "TXRUNDISP1": "GTXE2_CHANNEL_TXRUNDISP1", - "TXRUNDISP2": "GTXE2_CHANNEL_TXRUNDISP2", - "TXRUNDISP3": "GTXE2_CHANNEL_TXRUNDISP3", - "TXRUNDISP4": "GTXE2_CHANNEL_TXRUNDISP4", - "TXRUNDISP5": "GTXE2_CHANNEL_TXRUNDISP5", - "TXRUNDISP6": "GTXE2_CHANNEL_TXRUNDISP6", - "TXRUNDISP7": "GTXE2_CHANNEL_TXRUNDISP7", - "TXSEQUENCE0": "GTXE2_CHANNEL_TXSEQUENCE0", - "TXSEQUENCE1": "GTXE2_CHANNEL_TXSEQUENCE1", - "TXSEQUENCE2": "GTXE2_CHANNEL_TXSEQUENCE2", - "TXSEQUENCE3": "GTXE2_CHANNEL_TXSEQUENCE3", - "TXSEQUENCE4": "GTXE2_CHANNEL_TXSEQUENCE4", - "TXSEQUENCE5": "GTXE2_CHANNEL_TXSEQUENCE5", - "TXSEQUENCE6": "GTXE2_CHANNEL_TXSEQUENCE6", - "TXSTARTSEQ": "GTXE2_CHANNEL_TXSTARTSEQ", - "TXSWING": "GTXE2_CHANNEL_TXSWING", - "TXSYSCLKSEL0": "GTXE2_CHANNEL_TXSYSCLKSEL0", - "TXSYSCLKSEL1": "GTXE2_CHANNEL_TXSYSCLKSEL1", - "TXUSERRDY": "GTXE2_CHANNEL_TXUSERRDY", - "TXUSRCLK": "GTXE2_CHANNEL_TXUSRCLK", - "TXUSRCLK2": "GTXE2_CHANNEL_TXUSRCLK2" + "CFGRESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CFGRESET" + }, + "CLKRSVD0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD0" + }, + "CLKRSVD1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD1" + }, + "CLKRSVD2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD2" + }, + "CLKRSVD3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + 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"wire": "GTXE2_CHANNEL_TXQPISENN" + }, + "TXQPISENP": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXQPISENP" + }, + "TXQPISTRONGPDOWN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN" + }, + "TXQPIWEAKPUP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXQPIWEAKPUP" + }, + "TXRATE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXRATE0" + }, + "TXRATE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXRATE1" + }, + "TXRATE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXRATE2" + }, + "TXRATEDONE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRATEDONE" + }, + "TXRESETDONE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRESETDONE" + }, + "TXRUNDISP0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP0" + }, + "TXRUNDISP1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP1" + }, + "TXRUNDISP2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP2" + }, + "TXRUNDISP3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP3" + }, + "TXRUNDISP4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP4" + }, + "TXRUNDISP5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP5" + }, + "TXRUNDISP6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP6" + }, + "TXRUNDISP7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP7" + }, + "TXSEQUENCE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE0" + }, + "TXSEQUENCE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE1" + }, + "TXSEQUENCE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE2" + }, + "TXSEQUENCE3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE3" + }, + "TXSEQUENCE4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE4" + }, + "TXSEQUENCE5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE5" + }, + "TXSEQUENCE6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE6" + }, + "TXSTARTSEQ": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSTARTSEQ" + }, + "TXSWING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSWING" + }, + "TXSYSCLKSEL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSYSCLKSEL0" + }, + "TXSYSCLKSEL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSYSCLKSEL1" + }, + "TXUSERRDY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSERRDY" + }, + "TXUSRCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSRCLK" + }, + "TXUSRCLK2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSRCLK2" + } }, "type": "GTXE2_CHANNEL", "x_coord": 0, @@ -5095,7 +18159,16 @@ "name": "X0Y0", "prefix": "IPAD", "site_pins": { - "O": "GTXE2_CHANNEL_RXN_PAD" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "GTXE2_CHANNEL_RXN_PAD" + } }, "type": "IPAD", "x_coord": 0, @@ -5105,7 +18178,16 @@ "name": "X0Y1", "prefix": "IPAD", "site_pins": { - "O": "GTXE2_CHANNEL_RXP_PAD" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "GTXE2_CHANNEL_RXP_PAD" + } }, "type": "IPAD", "x_coord": 0, @@ -5115,7 +18197,16 @@ "name": "X0Y0", "prefix": "OPAD", "site_pins": { - "I": "GTXE2_CHANNEL_TXN_PAD" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXN_PAD" + } }, "type": "OPAD", "x_coord": 0, @@ -5125,7 +18216,16 @@ "name": "X0Y1", "prefix": "OPAD", "site_pins": { - "I": "GTXE2_CHANNEL_TXP_PAD" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXP_PAD" + } }, "type": "OPAD", "x_coord": 0, @@ -5133,1722 +18233,5310 @@ } ], "tile_type": "GTX_CHANNEL_2", - "wires": [ - "GTXE2_BYP0_0", - "GTXE2_BYP0_1", - "GTXE2_BYP0_10", - "GTXE2_BYP0_2", - "GTXE2_BYP0_3", - "GTXE2_BYP0_4", - "GTXE2_BYP0_5", - "GTXE2_BYP0_6", - "GTXE2_BYP0_7", - "GTXE2_BYP0_8", - "GTXE2_BYP0_9", - "GTXE2_BYP1_0", - "GTXE2_BYP1_1", - "GTXE2_BYP1_10", - "GTXE2_BYP1_2", - "GTXE2_BYP1_3", - "GTXE2_BYP1_4", - "GTXE2_BYP1_5", - "GTXE2_BYP1_6", - "GTXE2_BYP1_7", - "GTXE2_BYP1_8", - "GTXE2_BYP1_9", - "GTXE2_BYP2_0", - "GTXE2_BYP2_1", - "GTXE2_BYP2_10", - "GTXE2_BYP2_2", - "GTXE2_BYP2_3", - "GTXE2_BYP2_4", - "GTXE2_BYP2_5", - "GTXE2_BYP2_6", - "GTXE2_BYP2_7", - "GTXE2_BYP2_8", - "GTXE2_BYP2_9", - "GTXE2_BYP3_0", - "GTXE2_BYP3_1", - "GTXE2_BYP3_10", - "GTXE2_BYP3_2", - "GTXE2_BYP3_3", - "GTXE2_BYP3_4", - "GTXE2_BYP3_5", - "GTXE2_BYP3_6", - "GTXE2_BYP3_7", - "GTXE2_BYP3_8", - "GTXE2_BYP3_9", - "GTXE2_BYP4_0", - "GTXE2_BYP4_1", - "GTXE2_BYP4_10", - "GTXE2_BYP4_2", - "GTXE2_BYP4_3", - "GTXE2_BYP4_4", - "GTXE2_BYP4_5", - "GTXE2_BYP4_6", - "GTXE2_BYP4_7", - "GTXE2_BYP4_8", - "GTXE2_BYP4_9", - "GTXE2_BYP5_0", - "GTXE2_BYP5_1", - "GTXE2_BYP5_10", - "GTXE2_BYP5_2", - "GTXE2_BYP5_3", - "GTXE2_BYP5_4", - "GTXE2_BYP5_5", - "GTXE2_BYP5_6", - "GTXE2_BYP5_7", - "GTXE2_BYP5_8", - "GTXE2_BYP5_9", - "GTXE2_BYP6_0", - "GTXE2_BYP6_1", - "GTXE2_BYP6_10", - "GTXE2_BYP6_2", - "GTXE2_BYP6_3", - "GTXE2_BYP6_4", - "GTXE2_BYP6_5", - "GTXE2_BYP6_6", - "GTXE2_BYP6_7", - "GTXE2_BYP6_8", - "GTXE2_BYP6_9", - "GTXE2_BYP7_0", - "GTXE2_BYP7_1", - "GTXE2_BYP7_10", - "GTXE2_BYP7_2", - "GTXE2_BYP7_3", - "GTXE2_BYP7_4", - "GTXE2_BYP7_5", - "GTXE2_BYP7_6", - "GTXE2_BYP7_7", - "GTXE2_BYP7_8", - "GTXE2_BYP7_9", - "GTXE2_CHANNEL_CFGRESET", - "GTXE2_CHANNEL_CLKRSVD0", - "GTXE2_CHANNEL_CLKRSVD1", - "GTXE2_CHANNEL_CLKRSVD2", - "GTXE2_CHANNEL_CLKRSVD3", - "GTXE2_CHANNEL_CPLLFBCLKLOST", - "GTXE2_CHANNEL_CPLLLOCK", - "GTXE2_CHANNEL_CPLLLOCKDETCLK", - "GTXE2_CHANNEL_CPLLLOCKEN", - "GTXE2_CHANNEL_CPLLPD", - "GTXE2_CHANNEL_CPLLREFCLKLOST", - "GTXE2_CHANNEL_CPLLREFCLKSEL0", - "GTXE2_CHANNEL_CPLLREFCLKSEL1", - "GTXE2_CHANNEL_CPLLREFCLKSEL2", - "GTXE2_CHANNEL_CPLLRESET", - "GTXE2_CHANNEL_DMONITOROUT0", - "GTXE2_CHANNEL_DMONITOROUT1", - "GTXE2_CHANNEL_DMONITOROUT2", - "GTXE2_CHANNEL_DMONITOROUT3", - "GTXE2_CHANNEL_DMONITOROUT4", - "GTXE2_CHANNEL_DMONITOROUT5", - "GTXE2_CHANNEL_DMONITOROUT6", - "GTXE2_CHANNEL_DMONITOROUT7", - "GTXE2_CHANNEL_DRPADDR0", - "GTXE2_CHANNEL_DRPADDR1", - "GTXE2_CHANNEL_DRPADDR2", - "GTXE2_CHANNEL_DRPADDR3", - "GTXE2_CHANNEL_DRPADDR4", - "GTXE2_CHANNEL_DRPADDR5", - "GTXE2_CHANNEL_DRPADDR6", - "GTXE2_CHANNEL_DRPADDR7", - "GTXE2_CHANNEL_DRPADDR8", - "GTXE2_CHANNEL_DRPCLK", - "GTXE2_CHANNEL_DRPDI0", - "GTXE2_CHANNEL_DRPDI1", - "GTXE2_CHANNEL_DRPDI10", - "GTXE2_CHANNEL_DRPDI11", - "GTXE2_CHANNEL_DRPDI12", - "GTXE2_CHANNEL_DRPDI13", - "GTXE2_CHANNEL_DRPDI14", - "GTXE2_CHANNEL_DRPDI15", - "GTXE2_CHANNEL_DRPDI2", - "GTXE2_CHANNEL_DRPDI3", - "GTXE2_CHANNEL_DRPDI4", - "GTXE2_CHANNEL_DRPDI5", - "GTXE2_CHANNEL_DRPDI6", - "GTXE2_CHANNEL_DRPDI7", - "GTXE2_CHANNEL_DRPDI8", - "GTXE2_CHANNEL_DRPDI9", - "GTXE2_CHANNEL_DRPDO0", - "GTXE2_CHANNEL_DRPDO1", - "GTXE2_CHANNEL_DRPDO10", - "GTXE2_CHANNEL_DRPDO11", - "GTXE2_CHANNEL_DRPDO12", - "GTXE2_CHANNEL_DRPDO13", - "GTXE2_CHANNEL_DRPDO14", - "GTXE2_CHANNEL_DRPDO15", - "GTXE2_CHANNEL_DRPDO2", - "GTXE2_CHANNEL_DRPDO3", - "GTXE2_CHANNEL_DRPDO4", - "GTXE2_CHANNEL_DRPDO5", - "GTXE2_CHANNEL_DRPDO6", - "GTXE2_CHANNEL_DRPDO7", - "GTXE2_CHANNEL_DRPDO8", - "GTXE2_CHANNEL_DRPDO9", - "GTXE2_CHANNEL_DRPEN", - "GTXE2_CHANNEL_DRPRDY", - "GTXE2_CHANNEL_DRPWE", - "GTXE2_CHANNEL_EDTBYPASS", - "GTXE2_CHANNEL_EDTCLOCK", - "GTXE2_CHANNEL_EDTCONFIGURATION", - "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", - "GTXE2_CHANNEL_EDTUPDATE", - "GTXE2_CHANNEL_EYESCANDATAERROR", - "GTXE2_CHANNEL_EYESCANMODE", - "GTXE2_CHANNEL_EYESCANRESET", - "GTXE2_CHANNEL_EYESCANTRIGGER", - "GTXE2_CHANNEL_GTGREFCLK", - "GTXE2_CHANNEL_GTNORTHREFCLK0", - "GTXE2_CHANNEL_GTNORTHREFCLK1", - "GTXE2_CHANNEL_GTQPLLCLK", - "GTXE2_CHANNEL_GTQPLLREFCLK", - "GTXE2_CHANNEL_GTREFCLK0", - "GTXE2_CHANNEL_GTREFCLK1", - "GTXE2_CHANNEL_GTREFCLKMONITOR", - "GTXE2_CHANNEL_GTRESETSEL", - "GTXE2_CHANNEL_GTRSVD0", - "GTXE2_CHANNEL_GTRSVD1", - "GTXE2_CHANNEL_GTRSVD10", - "GTXE2_CHANNEL_GTRSVD11", - "GTXE2_CHANNEL_GTRSVD12", - "GTXE2_CHANNEL_GTRSVD13", - "GTXE2_CHANNEL_GTRSVD14", - "GTXE2_CHANNEL_GTRSVD15", - "GTXE2_CHANNEL_GTRSVD2", - "GTXE2_CHANNEL_GTRSVD3", - "GTXE2_CHANNEL_GTRSVD4", - "GTXE2_CHANNEL_GTRSVD5", - "GTXE2_CHANNEL_GTRSVD6", - "GTXE2_CHANNEL_GTRSVD7", - "GTXE2_CHANNEL_GTRSVD8", - "GTXE2_CHANNEL_GTRSVD9", - "GTXE2_CHANNEL_GTRXOUTCLK_2", - "GTXE2_CHANNEL_GTRXRESET", - "GTXE2_CHANNEL_GTSOUTHREFCLK0", - "GTXE2_CHANNEL_GTSOUTHREFCLK1", - "GTXE2_CHANNEL_GTTXOUTCLK_2", - "GTXE2_CHANNEL_GTTXRESET", - "GTXE2_CHANNEL_LOOPBACK0", - "GTXE2_CHANNEL_LOOPBACK1", - "GTXE2_CHANNEL_LOOPBACK2", - "GTXE2_CHANNEL_NORTHREFCLK0", - "GTXE2_CHANNEL_NORTHREFCLK1", - "GTXE2_CHANNEL_PCSRSVDIN0", - "GTXE2_CHANNEL_PCSRSVDIN1", - "GTXE2_CHANNEL_PCSRSVDIN10", - "GTXE2_CHANNEL_PCSRSVDIN11", - "GTXE2_CHANNEL_PCSRSVDIN12", - "GTXE2_CHANNEL_PCSRSVDIN13", - "GTXE2_CHANNEL_PCSRSVDIN14", - "GTXE2_CHANNEL_PCSRSVDIN15", - "GTXE2_CHANNEL_PCSRSVDIN2", - "GTXE2_CHANNEL_PCSRSVDIN20", - "GTXE2_CHANNEL_PCSRSVDIN21", - "GTXE2_CHANNEL_PCSRSVDIN22", - "GTXE2_CHANNEL_PCSRSVDIN23", - "GTXE2_CHANNEL_PCSRSVDIN24", - "GTXE2_CHANNEL_PCSRSVDIN3", - "GTXE2_CHANNEL_PCSRSVDIN4", - "GTXE2_CHANNEL_PCSRSVDIN5", - "GTXE2_CHANNEL_PCSRSVDIN6", - "GTXE2_CHANNEL_PCSRSVDIN7", - "GTXE2_CHANNEL_PCSRSVDIN8", - "GTXE2_CHANNEL_PCSRSVDIN9", - "GTXE2_CHANNEL_PCSRSVDOUT0", - "GTXE2_CHANNEL_PCSRSVDOUT1", - "GTXE2_CHANNEL_PCSRSVDOUT10", - "GTXE2_CHANNEL_PCSRSVDOUT11", - "GTXE2_CHANNEL_PCSRSVDOUT12", - "GTXE2_CHANNEL_PCSRSVDOUT13", - "GTXE2_CHANNEL_PCSRSVDOUT14", - "GTXE2_CHANNEL_PCSRSVDOUT15", - "GTXE2_CHANNEL_PCSRSVDOUT2", - "GTXE2_CHANNEL_PCSRSVDOUT3", - "GTXE2_CHANNEL_PCSRSVDOUT4", - "GTXE2_CHANNEL_PCSRSVDOUT5", - "GTXE2_CHANNEL_PCSRSVDOUT6", - "GTXE2_CHANNEL_PCSRSVDOUT7", - "GTXE2_CHANNEL_PCSRSVDOUT8", - "GTXE2_CHANNEL_PCSRSVDOUT9", - "GTXE2_CHANNEL_PHYSTATUS", - "GTXE2_CHANNEL_PMARSVDIN0", - "GTXE2_CHANNEL_PMARSVDIN1", - "GTXE2_CHANNEL_PMARSVDIN2", - "GTXE2_CHANNEL_PMARSVDIN20", - "GTXE2_CHANNEL_PMARSVDIN21", - "GTXE2_CHANNEL_PMARSVDIN22", - "GTXE2_CHANNEL_PMARSVDIN23", - "GTXE2_CHANNEL_PMARSVDIN24", - "GTXE2_CHANNEL_PMARSVDIN3", - "GTXE2_CHANNEL_PMARSVDIN4", - "GTXE2_CHANNEL_PMASCANCLK0", - "GTXE2_CHANNEL_PMASCANCLK1", - "GTXE2_CHANNEL_PMASCANCLK2", - "GTXE2_CHANNEL_PMASCANCLK3", - "GTXE2_CHANNEL_PMASCANCLK4", - "GTXE2_CHANNEL_PMASCANENB", - "GTXE2_CHANNEL_PMASCANIN0", - "GTXE2_CHANNEL_PMASCANIN1", - "GTXE2_CHANNEL_PMASCANIN2", - "GTXE2_CHANNEL_PMASCANIN3", - "GTXE2_CHANNEL_PMASCANIN4", - "GTXE2_CHANNEL_PMASCANMODEB", - "GTXE2_CHANNEL_PMASCANOUT0", - "GTXE2_CHANNEL_PMASCANOUT1", - "GTXE2_CHANNEL_PMASCANOUT2", - "GTXE2_CHANNEL_PMASCANOUT3", - "GTXE2_CHANNEL_PMASCANOUT4", - "GTXE2_CHANNEL_PMASCANRSTEN", - "GTXE2_CHANNEL_QPLLCLK", - "GTXE2_CHANNEL_QPLLREFCLK", - "GTXE2_CHANNEL_REFCLK0", - "GTXE2_CHANNEL_REFCLK1", - "GTXE2_CHANNEL_RESETOVRD", - "GTXE2_CHANNEL_RX8B10BEN", - "GTXE2_CHANNEL_RXBUFRESET", - "GTXE2_CHANNEL_RXBUFSTATUS0", - "GTXE2_CHANNEL_RXBUFSTATUS1", - "GTXE2_CHANNEL_RXBUFSTATUS2", - "GTXE2_CHANNEL_RXBYTEISALIGNED", - "GTXE2_CHANNEL_RXBYTEREALIGN", - "GTXE2_CHANNEL_RXCDRFREQRESET", - "GTXE2_CHANNEL_RXCDRHOLD", - "GTXE2_CHANNEL_RXCDRLOCK", - "GTXE2_CHANNEL_RXCDROVRDEN", - "GTXE2_CHANNEL_RXCDRRESET", - "GTXE2_CHANNEL_RXCDRRESETRSV", - "GTXE2_CHANNEL_RXCHANBONDSEQ", - "GTXE2_CHANNEL_RXCHANISALIGNED", - "GTXE2_CHANNEL_RXCHANREALIGN", - "GTXE2_CHANNEL_RXCHARISCOMMA0", - "GTXE2_CHANNEL_RXCHARISCOMMA1", - "GTXE2_CHANNEL_RXCHARISCOMMA2", - "GTXE2_CHANNEL_RXCHARISCOMMA3", - "GTXE2_CHANNEL_RXCHARISCOMMA4", - "GTXE2_CHANNEL_RXCHARISCOMMA5", - "GTXE2_CHANNEL_RXCHARISCOMMA6", - "GTXE2_CHANNEL_RXCHARISCOMMA7", - "GTXE2_CHANNEL_RXCHARISK0", - "GTXE2_CHANNEL_RXCHARISK1", - "GTXE2_CHANNEL_RXCHARISK2", - "GTXE2_CHANNEL_RXCHARISK3", - "GTXE2_CHANNEL_RXCHARISK4", - "GTXE2_CHANNEL_RXCHARISK5", - "GTXE2_CHANNEL_RXCHARISK6", - "GTXE2_CHANNEL_RXCHARISK7", - "GTXE2_CHANNEL_RXCHBONDEN", - "GTXE2_CHANNEL_RXCHBONDI0", - "GTXE2_CHANNEL_RXCHBONDI1", - "GTXE2_CHANNEL_RXCHBONDI2", - "GTXE2_CHANNEL_RXCHBONDI3", - "GTXE2_CHANNEL_RXCHBONDI4", - "GTXE2_CHANNEL_RXCHBONDLEVEL0", - "GTXE2_CHANNEL_RXCHBONDLEVEL1", - "GTXE2_CHANNEL_RXCHBONDLEVEL2", - "GTXE2_CHANNEL_RXCHBONDMASTER", - "GTXE2_CHANNEL_RXCHBONDO0", - "GTXE2_CHANNEL_RXCHBONDO1", - "GTXE2_CHANNEL_RXCHBONDO2", - "GTXE2_CHANNEL_RXCHBONDO3", - "GTXE2_CHANNEL_RXCHBONDO4", - "GTXE2_CHANNEL_RXCHBONDSLAVE", - "GTXE2_CHANNEL_RXCLKCORCNT0", - "GTXE2_CHANNEL_RXCLKCORCNT1", - "GTXE2_CHANNEL_RXCOMINITDET", - "GTXE2_CHANNEL_RXCOMMADET", - "GTXE2_CHANNEL_RXCOMMADETEN", - "GTXE2_CHANNEL_RXCOMSASDET", - "GTXE2_CHANNEL_RXCOMWAKEDET", - "GTXE2_CHANNEL_RXDATA0", - "GTXE2_CHANNEL_RXDATA1", - "GTXE2_CHANNEL_RXDATA10", - "GTXE2_CHANNEL_RXDATA11", - "GTXE2_CHANNEL_RXDATA12", - "GTXE2_CHANNEL_RXDATA13", - "GTXE2_CHANNEL_RXDATA14", - "GTXE2_CHANNEL_RXDATA15", - "GTXE2_CHANNEL_RXDATA16", - "GTXE2_CHANNEL_RXDATA17", - "GTXE2_CHANNEL_RXDATA18", - "GTXE2_CHANNEL_RXDATA19", - "GTXE2_CHANNEL_RXDATA2", - "GTXE2_CHANNEL_RXDATA20", - "GTXE2_CHANNEL_RXDATA21", - "GTXE2_CHANNEL_RXDATA22", - "GTXE2_CHANNEL_RXDATA23", - "GTXE2_CHANNEL_RXDATA24", - "GTXE2_CHANNEL_RXDATA25", - "GTXE2_CHANNEL_RXDATA26", - "GTXE2_CHANNEL_RXDATA27", - "GTXE2_CHANNEL_RXDATA28", - "GTXE2_CHANNEL_RXDATA29", - "GTXE2_CHANNEL_RXDATA3", - "GTXE2_CHANNEL_RXDATA30", - "GTXE2_CHANNEL_RXDATA31", - "GTXE2_CHANNEL_RXDATA32", - "GTXE2_CHANNEL_RXDATA33", - "GTXE2_CHANNEL_RXDATA34", - "GTXE2_CHANNEL_RXDATA35", - "GTXE2_CHANNEL_RXDATA36", - "GTXE2_CHANNEL_RXDATA37", - "GTXE2_CHANNEL_RXDATA38", - "GTXE2_CHANNEL_RXDATA39", - "GTXE2_CHANNEL_RXDATA4", - "GTXE2_CHANNEL_RXDATA40", - "GTXE2_CHANNEL_RXDATA41", - "GTXE2_CHANNEL_RXDATA42", - "GTXE2_CHANNEL_RXDATA43", - "GTXE2_CHANNEL_RXDATA44", - "GTXE2_CHANNEL_RXDATA45", - "GTXE2_CHANNEL_RXDATA46", - "GTXE2_CHANNEL_RXDATA47", - "GTXE2_CHANNEL_RXDATA48", - "GTXE2_CHANNEL_RXDATA49", - "GTXE2_CHANNEL_RXDATA5", - "GTXE2_CHANNEL_RXDATA50", - "GTXE2_CHANNEL_RXDATA51", - "GTXE2_CHANNEL_RXDATA52", - "GTXE2_CHANNEL_RXDATA53", - "GTXE2_CHANNEL_RXDATA54", - "GTXE2_CHANNEL_RXDATA55", - "GTXE2_CHANNEL_RXDATA56", - "GTXE2_CHANNEL_RXDATA57", - "GTXE2_CHANNEL_RXDATA58", - "GTXE2_CHANNEL_RXDATA59", - "GTXE2_CHANNEL_RXDATA6", - "GTXE2_CHANNEL_RXDATA60", - "GTXE2_CHANNEL_RXDATA61", - "GTXE2_CHANNEL_RXDATA62", - "GTXE2_CHANNEL_RXDATA63", - "GTXE2_CHANNEL_RXDATA7", - "GTXE2_CHANNEL_RXDATA8", - "GTXE2_CHANNEL_RXDATA9", - "GTXE2_CHANNEL_RXDATAVALID", - "GTXE2_CHANNEL_RXDDIEN", - "GTXE2_CHANNEL_RXDEBUGPULSE", - "GTXE2_CHANNEL_RXDFEAGCHOLD", - "GTXE2_CHANNEL_RXDFEAGCOVRDEN", - "GTXE2_CHANNEL_RXDFECM1EN", - "GTXE2_CHANNEL_RXDFELFHOLD", - "GTXE2_CHANNEL_RXDFELFOVRDEN", - "GTXE2_CHANNEL_RXDFELPMRESET", - "GTXE2_CHANNEL_RXDFETAP2HOLD", - "GTXE2_CHANNEL_RXDFETAP2OVRDEN", - "GTXE2_CHANNEL_RXDFETAP3HOLD", - "GTXE2_CHANNEL_RXDFETAP3OVRDEN", - "GTXE2_CHANNEL_RXDFETAP4HOLD", - "GTXE2_CHANNEL_RXDFETAP4OVRDEN", - "GTXE2_CHANNEL_RXDFETAP5HOLD", - "GTXE2_CHANNEL_RXDFETAP5OVRDEN", - "GTXE2_CHANNEL_RXDFEUTHOLD", - "GTXE2_CHANNEL_RXDFEUTOVRDEN", - "GTXE2_CHANNEL_RXDFEVPHOLD", - "GTXE2_CHANNEL_RXDFEVPOVRDEN", - "GTXE2_CHANNEL_RXDFEVSEN", - "GTXE2_CHANNEL_RXDFEXYDEN", - "GTXE2_CHANNEL_RXDFEXYDHOLD", - "GTXE2_CHANNEL_RXDFEXYDOVRDEN", - "GTXE2_CHANNEL_RXDISPERR0", - "GTXE2_CHANNEL_RXDISPERR1", - "GTXE2_CHANNEL_RXDISPERR2", - "GTXE2_CHANNEL_RXDISPERR3", - "GTXE2_CHANNEL_RXDISPERR4", - "GTXE2_CHANNEL_RXDISPERR5", - "GTXE2_CHANNEL_RXDISPERR6", - "GTXE2_CHANNEL_RXDISPERR7", - "GTXE2_CHANNEL_RXDLYBYPASS", - "GTXE2_CHANNEL_RXDLYEN", - "GTXE2_CHANNEL_RXDLYOVRDEN", - "GTXE2_CHANNEL_RXDLYSRESET", - "GTXE2_CHANNEL_RXDLYSRESETDONE", - "GTXE2_CHANNEL_RXDLYTESTENB", - "GTXE2_CHANNEL_RXELECIDLE", - "GTXE2_CHANNEL_RXELECIDLEMODE0", - "GTXE2_CHANNEL_RXELECIDLEMODE1", - "GTXE2_CHANNEL_RXGEARBOXSLIP", - "GTXE2_CHANNEL_RXHEADER0", - "GTXE2_CHANNEL_RXHEADER1", - "GTXE2_CHANNEL_RXHEADER2", - "GTXE2_CHANNEL_RXHEADERVALID", - "GTXE2_CHANNEL_RXLPMEN", - "GTXE2_CHANNEL_RXLPMHFHOLD", - "GTXE2_CHANNEL_RXLPMHFOVRDEN", - "GTXE2_CHANNEL_RXLPMLFHOLD", - "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", - "GTXE2_CHANNEL_RXMCOMMAALIGNEN", - "GTXE2_CHANNEL_RXMONITOROUT0", - "GTXE2_CHANNEL_RXMONITOROUT1", - "GTXE2_CHANNEL_RXMONITOROUT2", - "GTXE2_CHANNEL_RXMONITOROUT3", - "GTXE2_CHANNEL_RXMONITOROUT4", - "GTXE2_CHANNEL_RXMONITOROUT5", - "GTXE2_CHANNEL_RXMONITOROUT6", - "GTXE2_CHANNEL_RXMONITORSEL0", - "GTXE2_CHANNEL_RXMONITORSEL1", - "GTXE2_CHANNEL_RXN", - "GTXE2_CHANNEL_RXNOTINTABLE0", - "GTXE2_CHANNEL_RXNOTINTABLE1", - "GTXE2_CHANNEL_RXNOTINTABLE2", - "GTXE2_CHANNEL_RXNOTINTABLE3", - "GTXE2_CHANNEL_RXNOTINTABLE4", - "GTXE2_CHANNEL_RXNOTINTABLE5", - "GTXE2_CHANNEL_RXNOTINTABLE6", - "GTXE2_CHANNEL_RXNOTINTABLE7", - "GTXE2_CHANNEL_RXN_PAD", - "GTXE2_CHANNEL_RXOOBRESET", - "GTXE2_CHANNEL_RXOSHOLD", - "GTXE2_CHANNEL_RXOSOVRDEN", - "GTXE2_CHANNEL_RXOUTCLKFABRIC", - "GTXE2_CHANNEL_RXOUTCLKPCS", - "GTXE2_CHANNEL_RXOUTCLKSEL0", - "GTXE2_CHANNEL_RXOUTCLKSEL1", - "GTXE2_CHANNEL_RXOUTCLKSEL2", - "GTXE2_CHANNEL_RXOUTCLK_0", - "GTXE2_CHANNEL_RXOUTCLK_1", - "GTXE2_CHANNEL_RXOUTCLK_2", - "GTXE2_CHANNEL_RXOUTCLK_3", - "GTXE2_CHANNEL_RXP", - "GTXE2_CHANNEL_RXPCD1DONE", - "GTXE2_CHANNEL_RXPCOMMAALIGNEN", - "GTXE2_CHANNEL_RXPCSRESET", - "GTXE2_CHANNEL_RXPD0", - "GTXE2_CHANNEL_RXPD1", - "GTXE2_CHANNEL_RXPHALIGN", - "GTXE2_CHANNEL_RXPHALIGNDONE", - "GTXE2_CHANNEL_RXPHALIGNEN", - "GTXE2_CHANNEL_RXPHDLYPD", - "GTXE2_CHANNEL_RXPHDLYRESET", - "GTXE2_CHANNEL_RXPHMONITOR0", - "GTXE2_CHANNEL_RXPHMONITOR1", - "GTXE2_CHANNEL_RXPHMONITOR2", - "GTXE2_CHANNEL_RXPHMONITOR3", - "GTXE2_CHANNEL_RXPHMONITOR4", - "GTXE2_CHANNEL_RXPHOVRDEN", - "GTXE2_CHANNEL_RXPHSLIPMONITOR0", - "GTXE2_CHANNEL_RXPHSLIPMONITOR1", - "GTXE2_CHANNEL_RXPHSLIPMONITOR2", - "GTXE2_CHANNEL_RXPHSLIPMONITOR3", - "GTXE2_CHANNEL_RXPHSLIPMONITOR4", - "GTXE2_CHANNEL_RXPMARESET", - "GTXE2_CHANNEL_RXPOLARITY", - "GTXE2_CHANNEL_RXPRBSCNTRESET", - "GTXE2_CHANNEL_RXPRBSERR", - "GTXE2_CHANNEL_RXPRBSSEL0", - "GTXE2_CHANNEL_RXPRBSSEL1", - "GTXE2_CHANNEL_RXPRBSSEL2", - "GTXE2_CHANNEL_RXP_PAD", - "GTXE2_CHANNEL_RXQPIEN", - "GTXE2_CHANNEL_RXQPISENN", - "GTXE2_CHANNEL_RXQPISENP", - "GTXE2_CHANNEL_RXRATE0", - "GTXE2_CHANNEL_RXRATE1", - "GTXE2_CHANNEL_RXRATE2", - "GTXE2_CHANNEL_RXRATEDONE", - "GTXE2_CHANNEL_RXRESETDONE", - "GTXE2_CHANNEL_RXSLIDE", - "GTXE2_CHANNEL_RXSTARTOFSEQ", - "GTXE2_CHANNEL_RXSTATUS0", - "GTXE2_CHANNEL_RXSTATUS1", - "GTXE2_CHANNEL_RXSTATUS2", - "GTXE2_CHANNEL_RXSYSCLKSEL0", - "GTXE2_CHANNEL_RXSYSCLKSEL1", - "GTXE2_CHANNEL_RXUSERRDY", - "GTXE2_CHANNEL_RXUSRCLK", - "GTXE2_CHANNEL_RXUSRCLK2", - "GTXE2_CHANNEL_RXVALID", - "GTXE2_CHANNEL_SCANCLK", - "GTXE2_CHANNEL_SCANENB", - "GTXE2_CHANNEL_SCANIN0", - "GTXE2_CHANNEL_SCANIN1", - "GTXE2_CHANNEL_SCANIN2", - "GTXE2_CHANNEL_SCANIN3", - "GTXE2_CHANNEL_SCANIN4", - "GTXE2_CHANNEL_SCANMODEB", - "GTXE2_CHANNEL_SCANOUT0", - "GTXE2_CHANNEL_SCANOUT1", - "GTXE2_CHANNEL_SCANOUT2", - "GTXE2_CHANNEL_SCANOUT3", - "GTXE2_CHANNEL_SCANOUT4", - "GTXE2_CHANNEL_SETERRSTATUS", - "GTXE2_CHANNEL_SOUTHREFCLK0", - "GTXE2_CHANNEL_SOUTHREFCLK1", - "GTXE2_CHANNEL_TSTCLK0", - "GTXE2_CHANNEL_TSTCLK1", - "GTXE2_CHANNEL_TSTIN0", - "GTXE2_CHANNEL_TSTIN1", - "GTXE2_CHANNEL_TSTIN10", - "GTXE2_CHANNEL_TSTIN11", - "GTXE2_CHANNEL_TSTIN12", - "GTXE2_CHANNEL_TSTIN13", - "GTXE2_CHANNEL_TSTIN14", - "GTXE2_CHANNEL_TSTIN15", - "GTXE2_CHANNEL_TSTIN16", - "GTXE2_CHANNEL_TSTIN17", - "GTXE2_CHANNEL_TSTIN18", - "GTXE2_CHANNEL_TSTIN19", - "GTXE2_CHANNEL_TSTIN2", - "GTXE2_CHANNEL_TSTIN3", - "GTXE2_CHANNEL_TSTIN4", - "GTXE2_CHANNEL_TSTIN5", - "GTXE2_CHANNEL_TSTIN6", - "GTXE2_CHANNEL_TSTIN7", - "GTXE2_CHANNEL_TSTIN8", - "GTXE2_CHANNEL_TSTIN9", - "GTXE2_CHANNEL_TSTOUT0", - "GTXE2_CHANNEL_TSTOUT1", - "GTXE2_CHANNEL_TSTOUT2", - "GTXE2_CHANNEL_TSTOUT3", - "GTXE2_CHANNEL_TSTOUT4", - "GTXE2_CHANNEL_TSTOUT5", - "GTXE2_CHANNEL_TSTOUT6", - "GTXE2_CHANNEL_TSTOUT7", - "GTXE2_CHANNEL_TSTOUT8", - "GTXE2_CHANNEL_TSTOUT9", - "GTXE2_CHANNEL_TSTPD0", - "GTXE2_CHANNEL_TSTPD1", - "GTXE2_CHANNEL_TSTPD2", - "GTXE2_CHANNEL_TSTPD3", - "GTXE2_CHANNEL_TSTPD4", - "GTXE2_CHANNEL_TSTPDOVRDB", - "GTXE2_CHANNEL_TX8B10BBYPASS0", - "GTXE2_CHANNEL_TX8B10BBYPASS1", - "GTXE2_CHANNEL_TX8B10BBYPASS2", - "GTXE2_CHANNEL_TX8B10BBYPASS3", - "GTXE2_CHANNEL_TX8B10BBYPASS4", - "GTXE2_CHANNEL_TX8B10BBYPASS5", - "GTXE2_CHANNEL_TX8B10BBYPASS6", - "GTXE2_CHANNEL_TX8B10BBYPASS7", - "GTXE2_CHANNEL_TX8B10BEN", - "GTXE2_CHANNEL_TXBUFDIFFCTRL0", - "GTXE2_CHANNEL_TXBUFDIFFCTRL1", - "GTXE2_CHANNEL_TXBUFDIFFCTRL2", - "GTXE2_CHANNEL_TXBUFSTATUS0", - "GTXE2_CHANNEL_TXBUFSTATUS1", - "GTXE2_CHANNEL_TXCHARDISPMODE0", - "GTXE2_CHANNEL_TXCHARDISPMODE1", - "GTXE2_CHANNEL_TXCHARDISPMODE2", - "GTXE2_CHANNEL_TXCHARDISPMODE3", - "GTXE2_CHANNEL_TXCHARDISPMODE4", - "GTXE2_CHANNEL_TXCHARDISPMODE5", - "GTXE2_CHANNEL_TXCHARDISPMODE6", - "GTXE2_CHANNEL_TXCHARDISPMODE7", - "GTXE2_CHANNEL_TXCHARDISPVAL0", - "GTXE2_CHANNEL_TXCHARDISPVAL1", - "GTXE2_CHANNEL_TXCHARDISPVAL2", - "GTXE2_CHANNEL_TXCHARDISPVAL3", - "GTXE2_CHANNEL_TXCHARDISPVAL4", - "GTXE2_CHANNEL_TXCHARDISPVAL5", - "GTXE2_CHANNEL_TXCHARDISPVAL6", - "GTXE2_CHANNEL_TXCHARDISPVAL7", - "GTXE2_CHANNEL_TXCHARISK0", - "GTXE2_CHANNEL_TXCHARISK1", - "GTXE2_CHANNEL_TXCHARISK2", - "GTXE2_CHANNEL_TXCHARISK3", - "GTXE2_CHANNEL_TXCHARISK4", - "GTXE2_CHANNEL_TXCHARISK5", - "GTXE2_CHANNEL_TXCHARISK6", - "GTXE2_CHANNEL_TXCHARISK7", - "GTXE2_CHANNEL_TXCOMFINISH", - "GTXE2_CHANNEL_TXCOMINIT", - "GTXE2_CHANNEL_TXCOMSAS", - "GTXE2_CHANNEL_TXCOMWAKE", - "GTXE2_CHANNEL_TXDATA0", - "GTXE2_CHANNEL_TXDATA1", - "GTXE2_CHANNEL_TXDATA10", - "GTXE2_CHANNEL_TXDATA11", - "GTXE2_CHANNEL_TXDATA12", - "GTXE2_CHANNEL_TXDATA13", - "GTXE2_CHANNEL_TXDATA14", - "GTXE2_CHANNEL_TXDATA15", - "GTXE2_CHANNEL_TXDATA16", - "GTXE2_CHANNEL_TXDATA17", - "GTXE2_CHANNEL_TXDATA18", - "GTXE2_CHANNEL_TXDATA19", - "GTXE2_CHANNEL_TXDATA2", - "GTXE2_CHANNEL_TXDATA20", - "GTXE2_CHANNEL_TXDATA21", - "GTXE2_CHANNEL_TXDATA22", - "GTXE2_CHANNEL_TXDATA23", - "GTXE2_CHANNEL_TXDATA24", - "GTXE2_CHANNEL_TXDATA25", - "GTXE2_CHANNEL_TXDATA26", - "GTXE2_CHANNEL_TXDATA27", - "GTXE2_CHANNEL_TXDATA28", - "GTXE2_CHANNEL_TXDATA29", - "GTXE2_CHANNEL_TXDATA3", - "GTXE2_CHANNEL_TXDATA30", - "GTXE2_CHANNEL_TXDATA31", - "GTXE2_CHANNEL_TXDATA32", - "GTXE2_CHANNEL_TXDATA33", - "GTXE2_CHANNEL_TXDATA34", - "GTXE2_CHANNEL_TXDATA35", - "GTXE2_CHANNEL_TXDATA36", - "GTXE2_CHANNEL_TXDATA37", - "GTXE2_CHANNEL_TXDATA38", - "GTXE2_CHANNEL_TXDATA39", - "GTXE2_CHANNEL_TXDATA4", - "GTXE2_CHANNEL_TXDATA40", - "GTXE2_CHANNEL_TXDATA41", - "GTXE2_CHANNEL_TXDATA42", - "GTXE2_CHANNEL_TXDATA43", - "GTXE2_CHANNEL_TXDATA44", - "GTXE2_CHANNEL_TXDATA45", - "GTXE2_CHANNEL_TXDATA46", - "GTXE2_CHANNEL_TXDATA47", - "GTXE2_CHANNEL_TXDATA48", - "GTXE2_CHANNEL_TXDATA49", - "GTXE2_CHANNEL_TXDATA5", - "GTXE2_CHANNEL_TXDATA50", - "GTXE2_CHANNEL_TXDATA51", - "GTXE2_CHANNEL_TXDATA52", - "GTXE2_CHANNEL_TXDATA53", - "GTXE2_CHANNEL_TXDATA54", - "GTXE2_CHANNEL_TXDATA55", - "GTXE2_CHANNEL_TXDATA56", - "GTXE2_CHANNEL_TXDATA57", - "GTXE2_CHANNEL_TXDATA58", - "GTXE2_CHANNEL_TXDATA59", - "GTXE2_CHANNEL_TXDATA6", - "GTXE2_CHANNEL_TXDATA60", - "GTXE2_CHANNEL_TXDATA61", - "GTXE2_CHANNEL_TXDATA62", - "GTXE2_CHANNEL_TXDATA63", - "GTXE2_CHANNEL_TXDATA7", - "GTXE2_CHANNEL_TXDATA8", - "GTXE2_CHANNEL_TXDATA9", - "GTXE2_CHANNEL_TXDEEMPH", - "GTXE2_CHANNEL_TXDETECTRX", - "GTXE2_CHANNEL_TXDIFFCTRL0", - "GTXE2_CHANNEL_TXDIFFCTRL1", - "GTXE2_CHANNEL_TXDIFFCTRL2", - "GTXE2_CHANNEL_TXDIFFCTRL3", - "GTXE2_CHANNEL_TXDIFFPD", - "GTXE2_CHANNEL_TXDLYBYPASS", - "GTXE2_CHANNEL_TXDLYEN", - "GTXE2_CHANNEL_TXDLYHOLD", - "GTXE2_CHANNEL_TXDLYOVRDEN", - "GTXE2_CHANNEL_TXDLYSRESET", - "GTXE2_CHANNEL_TXDLYSRESETDONE", - "GTXE2_CHANNEL_TXDLYTESTENB", - "GTXE2_CHANNEL_TXDLYUPDOWN", - "GTXE2_CHANNEL_TXELECIDLE", - "GTXE2_CHANNEL_TXGEARBOXREADY", - "GTXE2_CHANNEL_TXHEADER0", - "GTXE2_CHANNEL_TXHEADER1", - "GTXE2_CHANNEL_TXHEADER2", - "GTXE2_CHANNEL_TXINHIBIT", - "GTXE2_CHANNEL_TXMAINCURSOR0", - "GTXE2_CHANNEL_TXMAINCURSOR1", - "GTXE2_CHANNEL_TXMAINCURSOR2", - "GTXE2_CHANNEL_TXMAINCURSOR3", - "GTXE2_CHANNEL_TXMAINCURSOR4", - "GTXE2_CHANNEL_TXMAINCURSOR5", - "GTXE2_CHANNEL_TXMAINCURSOR6", - "GTXE2_CHANNEL_TXMARGIN0", - "GTXE2_CHANNEL_TXMARGIN1", - "GTXE2_CHANNEL_TXMARGIN2", - "GTXE2_CHANNEL_TXN", - "GTXE2_CHANNEL_TXN_PAD", - "GTXE2_CHANNEL_TXOUTCLKFABRIC", - "GTXE2_CHANNEL_TXOUTCLKPCS", - "GTXE2_CHANNEL_TXOUTCLKSEL0", - "GTXE2_CHANNEL_TXOUTCLKSEL1", - "GTXE2_CHANNEL_TXOUTCLKSEL2", - "GTXE2_CHANNEL_TXOUTCLK_0", - "GTXE2_CHANNEL_TXOUTCLK_1", - "GTXE2_CHANNEL_TXOUTCLK_2", - "GTXE2_CHANNEL_TXOUTCLK_3", - "GTXE2_CHANNEL_TXP", - "GTXE2_CHANNEL_TXPCSRESET", - "GTXE2_CHANNEL_TXPD0", - "GTXE2_CHANNEL_TXPD1", - "GTXE2_CHANNEL_TXPDELECIDLEMODE", - "GTXE2_CHANNEL_TXPHALIGN", - "GTXE2_CHANNEL_TXPHALIGNDONE", - "GTXE2_CHANNEL_TXPHALIGNEN", - "GTXE2_CHANNEL_TXPHDLYPD", - "GTXE2_CHANNEL_TXPHDLYRESET", - "GTXE2_CHANNEL_TXPHDLYTSTCLK", - "GTXE2_CHANNEL_TXPHINIT", - "GTXE2_CHANNEL_TXPHINITDONE", - "GTXE2_CHANNEL_TXPHOVRDEN", - "GTXE2_CHANNEL_TXPISOPD", - "GTXE2_CHANNEL_TXPMARESET", - "GTXE2_CHANNEL_TXPOLARITY", - "GTXE2_CHANNEL_TXPOSTCURSOR0", - "GTXE2_CHANNEL_TXPOSTCURSOR1", - "GTXE2_CHANNEL_TXPOSTCURSOR2", - "GTXE2_CHANNEL_TXPOSTCURSOR3", - "GTXE2_CHANNEL_TXPOSTCURSOR4", - "GTXE2_CHANNEL_TXPOSTCURSORINV", - "GTXE2_CHANNEL_TXPRBSFORCEERR", - "GTXE2_CHANNEL_TXPRBSSEL0", - "GTXE2_CHANNEL_TXPRBSSEL1", - "GTXE2_CHANNEL_TXPRBSSEL2", - "GTXE2_CHANNEL_TXPRECURSOR0", - "GTXE2_CHANNEL_TXPRECURSOR1", - "GTXE2_CHANNEL_TXPRECURSOR2", - "GTXE2_CHANNEL_TXPRECURSOR3", - "GTXE2_CHANNEL_TXPRECURSOR4", - "GTXE2_CHANNEL_TXPRECURSORINV", - "GTXE2_CHANNEL_TXP_PAD", - "GTXE2_CHANNEL_TXQPIBIASEN", - "GTXE2_CHANNEL_TXQPISENN", - "GTXE2_CHANNEL_TXQPISENP", - "GTXE2_CHANNEL_TXQPISTRONGPDOWN", - "GTXE2_CHANNEL_TXQPIWEAKPUP", - "GTXE2_CHANNEL_TXRATE0", - "GTXE2_CHANNEL_TXRATE1", - "GTXE2_CHANNEL_TXRATE2", - "GTXE2_CHANNEL_TXRATEDONE", - "GTXE2_CHANNEL_TXRESETDONE", - "GTXE2_CHANNEL_TXRUNDISP0", - "GTXE2_CHANNEL_TXRUNDISP1", - "GTXE2_CHANNEL_TXRUNDISP2", - "GTXE2_CHANNEL_TXRUNDISP3", - "GTXE2_CHANNEL_TXRUNDISP4", - "GTXE2_CHANNEL_TXRUNDISP5", - "GTXE2_CHANNEL_TXRUNDISP6", - "GTXE2_CHANNEL_TXRUNDISP7", - "GTXE2_CHANNEL_TXSEQUENCE0", - "GTXE2_CHANNEL_TXSEQUENCE1", - "GTXE2_CHANNEL_TXSEQUENCE2", - "GTXE2_CHANNEL_TXSEQUENCE3", - "GTXE2_CHANNEL_TXSEQUENCE4", - "GTXE2_CHANNEL_TXSEQUENCE5", - "GTXE2_CHANNEL_TXSEQUENCE6", - "GTXE2_CHANNEL_TXSTARTSEQ", - "GTXE2_CHANNEL_TXSWING", - "GTXE2_CHANNEL_TXSYSCLKSEL0", - "GTXE2_CHANNEL_TXSYSCLKSEL1", - "GTXE2_CHANNEL_TXUSERRDY", - "GTXE2_CHANNEL_TXUSRCLK", - "GTXE2_CHANNEL_TXUSRCLK2", - "GTXE2_CLK0_0", - "GTXE2_CLK0_1", - "GTXE2_CLK0_10", - "GTXE2_CLK0_2", - "GTXE2_CLK0_3", - "GTXE2_CLK0_4", - "GTXE2_CLK0_5", - "GTXE2_CLK0_6", - "GTXE2_CLK0_7", - "GTXE2_CLK0_8", - "GTXE2_CLK0_9", - "GTXE2_CLK1_0", - "GTXE2_CLK1_1", - "GTXE2_CLK1_10", - "GTXE2_CLK1_2", - "GTXE2_CLK1_3", - "GTXE2_CLK1_4", - "GTXE2_CLK1_5", - "GTXE2_CLK1_6", - "GTXE2_CLK1_7", - "GTXE2_CLK1_8", - "GTXE2_CLK1_9", - "GTXE2_CTRL0_0", - "GTXE2_CTRL0_1", - "GTXE2_CTRL0_10", - "GTXE2_CTRL0_2", - "GTXE2_CTRL0_3", - "GTXE2_CTRL0_4", - "GTXE2_CTRL0_5", - "GTXE2_CTRL0_6", - "GTXE2_CTRL0_7", - "GTXE2_CTRL0_8", - "GTXE2_CTRL0_9", - "GTXE2_CTRL1_0", - "GTXE2_CTRL1_1", - "GTXE2_CTRL1_10", - "GTXE2_CTRL1_2", - "GTXE2_CTRL1_3", - "GTXE2_CTRL1_4", - "GTXE2_CTRL1_5", - "GTXE2_CTRL1_6", - "GTXE2_CTRL1_7", - "GTXE2_CTRL1_8", - "GTXE2_CTRL1_9", - "GTXE2_FAN0_0", - "GTXE2_FAN0_1", - "GTXE2_FAN0_10", - "GTXE2_FAN0_2", - "GTXE2_FAN0_3", - "GTXE2_FAN0_4", - "GTXE2_FAN0_5", - "GTXE2_FAN0_6", - "GTXE2_FAN0_7", - "GTXE2_FAN0_8", - "GTXE2_FAN0_9", - "GTXE2_FAN1_0", - "GTXE2_FAN1_1", - "GTXE2_FAN1_10", - "GTXE2_FAN1_2", - "GTXE2_FAN1_3", - "GTXE2_FAN1_4", - "GTXE2_FAN1_5", - "GTXE2_FAN1_6", - "GTXE2_FAN1_7", - "GTXE2_FAN1_8", - "GTXE2_FAN1_9", - "GTXE2_FAN2_0", - "GTXE2_FAN2_1", - "GTXE2_FAN2_10", - "GTXE2_FAN2_2", - "GTXE2_FAN2_3", - "GTXE2_FAN2_4", - "GTXE2_FAN2_5", - "GTXE2_FAN2_6", - "GTXE2_FAN2_7", - "GTXE2_FAN2_8", - "GTXE2_FAN2_9", - "GTXE2_FAN3_0", - "GTXE2_FAN3_1", - "GTXE2_FAN3_10", - "GTXE2_FAN3_2", - "GTXE2_FAN3_3", - "GTXE2_FAN3_4", - "GTXE2_FAN3_5", - "GTXE2_FAN3_6", - "GTXE2_FAN3_7", - "GTXE2_FAN3_8", - "GTXE2_FAN3_9", - "GTXE2_FAN4_0", - "GTXE2_FAN4_1", - "GTXE2_FAN4_10", - "GTXE2_FAN4_2", - "GTXE2_FAN4_3", - "GTXE2_FAN4_4", - "GTXE2_FAN4_5", - "GTXE2_FAN4_6", - "GTXE2_FAN4_7", - "GTXE2_FAN4_8", - "GTXE2_FAN4_9", - "GTXE2_FAN5_0", - "GTXE2_FAN5_1", - "GTXE2_FAN5_10", - "GTXE2_FAN5_2", - "GTXE2_FAN5_3", - "GTXE2_FAN5_4", - "GTXE2_FAN5_5", - "GTXE2_FAN5_6", - "GTXE2_FAN5_7", - "GTXE2_FAN5_8", - "GTXE2_FAN5_9", - "GTXE2_FAN6_0", - "GTXE2_FAN6_1", - "GTXE2_FAN6_10", - "GTXE2_FAN6_2", - "GTXE2_FAN6_3", - "GTXE2_FAN6_4", - "GTXE2_FAN6_5", - "GTXE2_FAN6_6", - "GTXE2_FAN6_7", - "GTXE2_FAN6_8", - "GTXE2_FAN6_9", - "GTXE2_FAN7_0", - "GTXE2_FAN7_1", - "GTXE2_FAN7_10", - "GTXE2_FAN7_2", - "GTXE2_FAN7_3", - "GTXE2_FAN7_4", - "GTXE2_FAN7_5", - "GTXE2_FAN7_6", - "GTXE2_FAN7_7", - "GTXE2_FAN7_8", - "GTXE2_FAN7_9", - "GTXE2_IMUX0_0", - "GTXE2_IMUX0_1", - "GTXE2_IMUX0_10", - "GTXE2_IMUX0_2", - "GTXE2_IMUX0_3", - "GTXE2_IMUX0_4", - "GTXE2_IMUX0_5", - "GTXE2_IMUX0_6", - "GTXE2_IMUX0_7", - "GTXE2_IMUX0_8", - "GTXE2_IMUX0_9", - "GTXE2_IMUX10_0", - "GTXE2_IMUX10_1", - "GTXE2_IMUX10_10", - "GTXE2_IMUX10_2", - "GTXE2_IMUX10_3", - "GTXE2_IMUX10_4", - "GTXE2_IMUX10_5", - "GTXE2_IMUX10_6", - "GTXE2_IMUX10_7", - "GTXE2_IMUX10_8", - "GTXE2_IMUX10_9", - "GTXE2_IMUX11_0", - "GTXE2_IMUX11_1", - "GTXE2_IMUX11_10", - "GTXE2_IMUX11_2", - "GTXE2_IMUX11_3", - "GTXE2_IMUX11_4", - "GTXE2_IMUX11_5", - "GTXE2_IMUX11_6", - "GTXE2_IMUX11_7", - "GTXE2_IMUX11_8", - "GTXE2_IMUX11_9", - "GTXE2_IMUX12_0", - "GTXE2_IMUX12_1", - "GTXE2_IMUX12_10", - "GTXE2_IMUX12_2", - "GTXE2_IMUX12_3", - "GTXE2_IMUX12_4", - "GTXE2_IMUX12_5", - "GTXE2_IMUX12_6", - "GTXE2_IMUX12_7", - "GTXE2_IMUX12_8", - "GTXE2_IMUX12_9", - "GTXE2_IMUX13_0", - "GTXE2_IMUX13_1", - "GTXE2_IMUX13_10", - "GTXE2_IMUX13_2", - "GTXE2_IMUX13_3", - "GTXE2_IMUX13_4", - "GTXE2_IMUX13_5", - "GTXE2_IMUX13_6", - "GTXE2_IMUX13_7", - "GTXE2_IMUX13_8", - "GTXE2_IMUX13_9", - "GTXE2_IMUX14_0", - "GTXE2_IMUX14_1", - "GTXE2_IMUX14_10", - "GTXE2_IMUX14_2", - "GTXE2_IMUX14_3", - "GTXE2_IMUX14_4", - "GTXE2_IMUX14_5", - "GTXE2_IMUX14_6", - "GTXE2_IMUX14_7", - "GTXE2_IMUX14_8", - "GTXE2_IMUX14_9", - "GTXE2_IMUX15_0", - "GTXE2_IMUX15_1", - "GTXE2_IMUX15_10", - "GTXE2_IMUX15_2", - "GTXE2_IMUX15_3", - "GTXE2_IMUX15_4", - "GTXE2_IMUX15_5", - "GTXE2_IMUX15_6", - "GTXE2_IMUX15_7", - "GTXE2_IMUX15_8", - "GTXE2_IMUX15_9", - "GTXE2_IMUX16_0", - "GTXE2_IMUX16_1", - "GTXE2_IMUX16_10", - "GTXE2_IMUX16_2", - "GTXE2_IMUX16_3", - "GTXE2_IMUX16_4", - "GTXE2_IMUX16_5", - "GTXE2_IMUX16_6", - "GTXE2_IMUX16_7", - "GTXE2_IMUX16_8", - "GTXE2_IMUX16_9", - "GTXE2_IMUX17_0", - "GTXE2_IMUX17_1", - "GTXE2_IMUX17_10", - "GTXE2_IMUX17_2", - "GTXE2_IMUX17_3", - "GTXE2_IMUX17_4", - "GTXE2_IMUX17_5", - "GTXE2_IMUX17_6", - "GTXE2_IMUX17_7", - "GTXE2_IMUX17_8", - "GTXE2_IMUX17_9", - "GTXE2_IMUX18_0", - "GTXE2_IMUX18_1", - "GTXE2_IMUX18_10", - "GTXE2_IMUX18_2", - "GTXE2_IMUX18_3", - "GTXE2_IMUX18_4", - "GTXE2_IMUX18_5", - "GTXE2_IMUX18_6", - "GTXE2_IMUX18_7", - "GTXE2_IMUX18_8", - "GTXE2_IMUX18_9", - "GTXE2_IMUX19_0", - "GTXE2_IMUX19_1", - "GTXE2_IMUX19_10", - "GTXE2_IMUX19_2", - "GTXE2_IMUX19_3", - "GTXE2_IMUX19_4", - "GTXE2_IMUX19_5", - "GTXE2_IMUX19_6", - "GTXE2_IMUX19_7", - "GTXE2_IMUX19_8", - "GTXE2_IMUX19_9", - "GTXE2_IMUX1_0", - "GTXE2_IMUX1_1", - "GTXE2_IMUX1_10", - "GTXE2_IMUX1_2", - "GTXE2_IMUX1_3", - "GTXE2_IMUX1_4", - "GTXE2_IMUX1_5", - "GTXE2_IMUX1_6", - "GTXE2_IMUX1_7", - "GTXE2_IMUX1_8", - "GTXE2_IMUX1_9", - "GTXE2_IMUX20_0", - "GTXE2_IMUX20_1", - "GTXE2_IMUX20_10", - "GTXE2_IMUX20_2", - "GTXE2_IMUX20_3", - "GTXE2_IMUX20_4", - "GTXE2_IMUX20_5", - "GTXE2_IMUX20_6", - "GTXE2_IMUX20_7", - "GTXE2_IMUX20_8", - "GTXE2_IMUX20_9", - "GTXE2_IMUX21_0", - "GTXE2_IMUX21_1", - "GTXE2_IMUX21_10", - "GTXE2_IMUX21_2", - "GTXE2_IMUX21_3", - "GTXE2_IMUX21_4", - "GTXE2_IMUX21_5", - "GTXE2_IMUX21_6", - "GTXE2_IMUX21_7", - "GTXE2_IMUX21_8", - "GTXE2_IMUX21_9", - "GTXE2_IMUX22_0", - "GTXE2_IMUX22_1", - "GTXE2_IMUX22_10", - "GTXE2_IMUX22_2", - "GTXE2_IMUX22_3", - "GTXE2_IMUX22_4", - "GTXE2_IMUX22_5", - "GTXE2_IMUX22_6", - "GTXE2_IMUX22_7", - "GTXE2_IMUX22_8", - "GTXE2_IMUX22_9", - "GTXE2_IMUX23_0", - "GTXE2_IMUX23_1", - "GTXE2_IMUX23_10", - "GTXE2_IMUX23_2", - "GTXE2_IMUX23_3", - "GTXE2_IMUX23_4", - "GTXE2_IMUX23_5", - "GTXE2_IMUX23_6", - "GTXE2_IMUX23_7", - "GTXE2_IMUX23_8", - "GTXE2_IMUX23_9", - "GTXE2_IMUX24_0", - "GTXE2_IMUX24_1", - "GTXE2_IMUX24_10", - "GTXE2_IMUX24_2", - "GTXE2_IMUX24_3", - "GTXE2_IMUX24_4", - "GTXE2_IMUX24_5", - "GTXE2_IMUX24_6", - "GTXE2_IMUX24_7", - "GTXE2_IMUX24_8", - "GTXE2_IMUX24_9", - "GTXE2_IMUX25_0", - "GTXE2_IMUX25_1", - "GTXE2_IMUX25_10", - "GTXE2_IMUX25_2", - "GTXE2_IMUX25_3", - "GTXE2_IMUX25_4", - "GTXE2_IMUX25_5", - "GTXE2_IMUX25_6", - "GTXE2_IMUX25_7", - "GTXE2_IMUX25_8", - "GTXE2_IMUX25_9", - "GTXE2_IMUX26_0", - "GTXE2_IMUX26_1", - "GTXE2_IMUX26_10", - "GTXE2_IMUX26_2", - "GTXE2_IMUX26_3", - "GTXE2_IMUX26_4", - "GTXE2_IMUX26_5", - "GTXE2_IMUX26_6", - "GTXE2_IMUX26_7", - "GTXE2_IMUX26_8", - "GTXE2_IMUX26_9", - "GTXE2_IMUX27_0", - "GTXE2_IMUX27_1", - "GTXE2_IMUX27_10", - "GTXE2_IMUX27_2", - "GTXE2_IMUX27_3", - "GTXE2_IMUX27_4", - "GTXE2_IMUX27_5", - "GTXE2_IMUX27_6", - "GTXE2_IMUX27_7", - "GTXE2_IMUX27_8", - "GTXE2_IMUX27_9", - "GTXE2_IMUX28_0", - "GTXE2_IMUX28_1", - "GTXE2_IMUX28_10", - "GTXE2_IMUX28_2", - "GTXE2_IMUX28_3", - "GTXE2_IMUX28_4", - "GTXE2_IMUX28_5", - "GTXE2_IMUX28_6", - "GTXE2_IMUX28_7", - "GTXE2_IMUX28_8", - "GTXE2_IMUX28_9", - "GTXE2_IMUX29_0", - "GTXE2_IMUX29_1", - "GTXE2_IMUX29_10", - "GTXE2_IMUX29_2", - "GTXE2_IMUX29_3", - "GTXE2_IMUX29_4", - "GTXE2_IMUX29_5", - "GTXE2_IMUX29_6", - "GTXE2_IMUX29_7", - "GTXE2_IMUX29_8", - "GTXE2_IMUX29_9", - "GTXE2_IMUX2_0", - "GTXE2_IMUX2_1", - "GTXE2_IMUX2_10", - "GTXE2_IMUX2_2", - "GTXE2_IMUX2_3", - "GTXE2_IMUX2_4", - "GTXE2_IMUX2_5", - "GTXE2_IMUX2_6", - "GTXE2_IMUX2_7", - "GTXE2_IMUX2_8", - "GTXE2_IMUX2_9", - "GTXE2_IMUX30_0", - "GTXE2_IMUX30_1", - "GTXE2_IMUX30_10", - "GTXE2_IMUX30_2", - "GTXE2_IMUX30_3", - "GTXE2_IMUX30_4", - "GTXE2_IMUX30_5", - "GTXE2_IMUX30_6", - "GTXE2_IMUX30_7", - "GTXE2_IMUX30_8", - "GTXE2_IMUX30_9", - "GTXE2_IMUX31_0", - "GTXE2_IMUX31_1", - "GTXE2_IMUX31_10", - "GTXE2_IMUX31_2", - "GTXE2_IMUX31_3", - "GTXE2_IMUX31_4", - "GTXE2_IMUX31_5", - "GTXE2_IMUX31_6", - "GTXE2_IMUX31_7", - "GTXE2_IMUX31_8", - "GTXE2_IMUX31_9", - "GTXE2_IMUX32_0", - "GTXE2_IMUX32_1", - "GTXE2_IMUX32_10", - "GTXE2_IMUX32_2", - "GTXE2_IMUX32_3", - "GTXE2_IMUX32_4", - "GTXE2_IMUX32_5", - "GTXE2_IMUX32_6", - "GTXE2_IMUX32_7", - "GTXE2_IMUX32_8", - "GTXE2_IMUX32_9", - "GTXE2_IMUX33_0", - "GTXE2_IMUX33_1", - "GTXE2_IMUX33_10", - "GTXE2_IMUX33_2", - "GTXE2_IMUX33_3", - "GTXE2_IMUX33_4", - "GTXE2_IMUX33_5", - "GTXE2_IMUX33_6", - "GTXE2_IMUX33_7", - "GTXE2_IMUX33_8", - "GTXE2_IMUX33_9", - "GTXE2_IMUX34_0", - "GTXE2_IMUX34_1", - "GTXE2_IMUX34_10", - "GTXE2_IMUX34_2", - "GTXE2_IMUX34_3", - "GTXE2_IMUX34_4", - "GTXE2_IMUX34_5", - "GTXE2_IMUX34_6", - "GTXE2_IMUX34_7", - "GTXE2_IMUX34_8", - "GTXE2_IMUX34_9", - "GTXE2_IMUX35_0", - "GTXE2_IMUX35_1", - "GTXE2_IMUX35_10", - "GTXE2_IMUX35_2", - "GTXE2_IMUX35_3", - "GTXE2_IMUX35_4", - "GTXE2_IMUX35_5", - "GTXE2_IMUX35_6", - "GTXE2_IMUX35_7", - "GTXE2_IMUX35_8", - "GTXE2_IMUX35_9", - "GTXE2_IMUX36_0", - "GTXE2_IMUX36_1", - "GTXE2_IMUX36_10", - "GTXE2_IMUX36_2", - "GTXE2_IMUX36_3", - "GTXE2_IMUX36_4", - "GTXE2_IMUX36_5", - "GTXE2_IMUX36_6", - "GTXE2_IMUX36_7", - "GTXE2_IMUX36_8", - "GTXE2_IMUX36_9", - "GTXE2_IMUX37_0", - "GTXE2_IMUX37_1", - "GTXE2_IMUX37_10", - "GTXE2_IMUX37_2", - "GTXE2_IMUX37_3", - "GTXE2_IMUX37_4", - "GTXE2_IMUX37_5", - "GTXE2_IMUX37_6", - "GTXE2_IMUX37_7", - "GTXE2_IMUX37_8", - "GTXE2_IMUX37_9", - "GTXE2_IMUX38_0", - "GTXE2_IMUX38_1", - "GTXE2_IMUX38_10", - "GTXE2_IMUX38_2", - "GTXE2_IMUX38_3", - "GTXE2_IMUX38_4", - "GTXE2_IMUX38_5", - "GTXE2_IMUX38_6", - "GTXE2_IMUX38_7", - "GTXE2_IMUX38_8", - "GTXE2_IMUX38_9", - "GTXE2_IMUX39_0", - "GTXE2_IMUX39_1", - "GTXE2_IMUX39_10", - "GTXE2_IMUX39_2", - "GTXE2_IMUX39_3", - "GTXE2_IMUX39_4", - "GTXE2_IMUX39_5", - "GTXE2_IMUX39_6", - "GTXE2_IMUX39_7", - "GTXE2_IMUX39_8", - "GTXE2_IMUX39_9", - "GTXE2_IMUX3_0", - "GTXE2_IMUX3_1", - "GTXE2_IMUX3_10", - "GTXE2_IMUX3_2", - "GTXE2_IMUX3_3", - "GTXE2_IMUX3_4", - "GTXE2_IMUX3_5", - "GTXE2_IMUX3_6", - "GTXE2_IMUX3_7", - "GTXE2_IMUX3_8", - "GTXE2_IMUX3_9", - "GTXE2_IMUX40_0", - "GTXE2_IMUX40_1", - "GTXE2_IMUX40_10", - "GTXE2_IMUX40_2", - "GTXE2_IMUX40_3", - "GTXE2_IMUX40_4", - "GTXE2_IMUX40_5", - "GTXE2_IMUX40_6", - "GTXE2_IMUX40_7", - "GTXE2_IMUX40_8", - "GTXE2_IMUX40_9", - "GTXE2_IMUX41_0", - "GTXE2_IMUX41_1", - "GTXE2_IMUX41_10", - "GTXE2_IMUX41_2", - "GTXE2_IMUX41_3", - "GTXE2_IMUX41_4", - "GTXE2_IMUX41_5", - "GTXE2_IMUX41_6", - "GTXE2_IMUX41_7", - "GTXE2_IMUX41_8", - "GTXE2_IMUX41_9", - "GTXE2_IMUX42_0", - "GTXE2_IMUX42_1", - "GTXE2_IMUX42_10", - "GTXE2_IMUX42_2", - "GTXE2_IMUX42_3", - "GTXE2_IMUX42_4", - "GTXE2_IMUX42_5", - "GTXE2_IMUX42_6", - "GTXE2_IMUX42_7", - "GTXE2_IMUX42_8", - "GTXE2_IMUX42_9", - "GTXE2_IMUX43_0", - "GTXE2_IMUX43_1", - "GTXE2_IMUX43_10", - "GTXE2_IMUX43_2", - "GTXE2_IMUX43_3", - "GTXE2_IMUX43_4", - "GTXE2_IMUX43_5", - "GTXE2_IMUX43_6", - "GTXE2_IMUX43_7", - "GTXE2_IMUX43_8", - "GTXE2_IMUX43_9", - "GTXE2_IMUX44_0", - "GTXE2_IMUX44_1", - "GTXE2_IMUX44_10", - "GTXE2_IMUX44_2", - "GTXE2_IMUX44_3", - "GTXE2_IMUX44_4", - "GTXE2_IMUX44_5", - "GTXE2_IMUX44_6", - "GTXE2_IMUX44_7", - "GTXE2_IMUX44_8", - "GTXE2_IMUX44_9", - "GTXE2_IMUX45_0", - "GTXE2_IMUX45_1", - "GTXE2_IMUX45_10", - "GTXE2_IMUX45_2", - "GTXE2_IMUX45_3", - "GTXE2_IMUX45_4", - "GTXE2_IMUX45_5", - "GTXE2_IMUX45_6", - "GTXE2_IMUX45_7", - "GTXE2_IMUX45_8", - "GTXE2_IMUX45_9", - "GTXE2_IMUX46_0", - "GTXE2_IMUX46_1", - "GTXE2_IMUX46_10", - "GTXE2_IMUX46_2", - "GTXE2_IMUX46_3", - "GTXE2_IMUX46_4", - "GTXE2_IMUX46_5", - "GTXE2_IMUX46_6", - "GTXE2_IMUX46_7", - "GTXE2_IMUX46_8", - "GTXE2_IMUX46_9", - "GTXE2_IMUX47_0", - "GTXE2_IMUX47_1", - "GTXE2_IMUX47_10", - "GTXE2_IMUX47_2", - "GTXE2_IMUX47_3", - "GTXE2_IMUX47_4", - "GTXE2_IMUX47_5", - "GTXE2_IMUX47_6", - "GTXE2_IMUX47_7", - "GTXE2_IMUX47_8", - "GTXE2_IMUX47_9", - "GTXE2_IMUX4_0", - "GTXE2_IMUX4_1", - "GTXE2_IMUX4_10", - "GTXE2_IMUX4_2", - "GTXE2_IMUX4_3", - "GTXE2_IMUX4_4", - "GTXE2_IMUX4_5", - "GTXE2_IMUX4_6", - "GTXE2_IMUX4_7", - "GTXE2_IMUX4_8", - "GTXE2_IMUX4_9", - "GTXE2_IMUX5_0", - "GTXE2_IMUX5_1", - "GTXE2_IMUX5_10", - "GTXE2_IMUX5_2", - "GTXE2_IMUX5_3", - "GTXE2_IMUX5_4", - "GTXE2_IMUX5_5", - "GTXE2_IMUX5_6", - "GTXE2_IMUX5_7", - "GTXE2_IMUX5_8", - "GTXE2_IMUX5_9", - "GTXE2_IMUX6_0", - "GTXE2_IMUX6_1", - "GTXE2_IMUX6_10", - "GTXE2_IMUX6_2", - "GTXE2_IMUX6_3", - "GTXE2_IMUX6_4", - "GTXE2_IMUX6_5", - "GTXE2_IMUX6_6", - "GTXE2_IMUX6_7", - "GTXE2_IMUX6_8", - "GTXE2_IMUX6_9", - "GTXE2_IMUX7_0", - "GTXE2_IMUX7_1", - "GTXE2_IMUX7_10", - "GTXE2_IMUX7_2", - "GTXE2_IMUX7_3", - "GTXE2_IMUX7_4", - "GTXE2_IMUX7_5", - "GTXE2_IMUX7_6", - "GTXE2_IMUX7_7", - "GTXE2_IMUX7_8", - "GTXE2_IMUX7_9", - "GTXE2_IMUX8_0", - "GTXE2_IMUX8_1", - "GTXE2_IMUX8_10", - "GTXE2_IMUX8_2", - "GTXE2_IMUX8_3", - "GTXE2_IMUX8_4", - "GTXE2_IMUX8_5", - "GTXE2_IMUX8_6", - "GTXE2_IMUX8_7", - "GTXE2_IMUX8_8", - "GTXE2_IMUX8_9", - "GTXE2_IMUX9_0", - "GTXE2_IMUX9_1", - "GTXE2_IMUX9_10", - "GTXE2_IMUX9_2", - "GTXE2_IMUX9_3", - "GTXE2_IMUX9_4", - "GTXE2_IMUX9_5", - "GTXE2_IMUX9_6", - "GTXE2_IMUX9_7", - "GTXE2_IMUX9_8", - "GTXE2_IMUX9_9", - "GTXE2_LOGIC_OUTS_B0_0", - "GTXE2_LOGIC_OUTS_B0_1", - "GTXE2_LOGIC_OUTS_B0_10", - "GTXE2_LOGIC_OUTS_B0_2", - "GTXE2_LOGIC_OUTS_B0_3", - "GTXE2_LOGIC_OUTS_B0_4", - "GTXE2_LOGIC_OUTS_B0_5", - "GTXE2_LOGIC_OUTS_B0_6", - "GTXE2_LOGIC_OUTS_B0_7", - "GTXE2_LOGIC_OUTS_B0_8", - "GTXE2_LOGIC_OUTS_B0_9", - "GTXE2_LOGIC_OUTS_B10_0", - "GTXE2_LOGIC_OUTS_B10_1", - "GTXE2_LOGIC_OUTS_B10_10", - "GTXE2_LOGIC_OUTS_B10_2", - "GTXE2_LOGIC_OUTS_B10_3", - "GTXE2_LOGIC_OUTS_B10_4", - "GTXE2_LOGIC_OUTS_B10_5", - "GTXE2_LOGIC_OUTS_B10_6", - "GTXE2_LOGIC_OUTS_B10_7", - "GTXE2_LOGIC_OUTS_B10_8", - "GTXE2_LOGIC_OUTS_B10_9", - "GTXE2_LOGIC_OUTS_B11_0", - "GTXE2_LOGIC_OUTS_B11_1", - "GTXE2_LOGIC_OUTS_B11_10", - "GTXE2_LOGIC_OUTS_B11_2", - "GTXE2_LOGIC_OUTS_B11_3", - "GTXE2_LOGIC_OUTS_B11_4", - "GTXE2_LOGIC_OUTS_B11_5", - "GTXE2_LOGIC_OUTS_B11_6", - "GTXE2_LOGIC_OUTS_B11_7", - "GTXE2_LOGIC_OUTS_B11_8", - "GTXE2_LOGIC_OUTS_B11_9", - "GTXE2_LOGIC_OUTS_B12_0", - "GTXE2_LOGIC_OUTS_B12_1", - "GTXE2_LOGIC_OUTS_B12_10", - "GTXE2_LOGIC_OUTS_B12_2", - "GTXE2_LOGIC_OUTS_B12_3", - "GTXE2_LOGIC_OUTS_B12_4", - "GTXE2_LOGIC_OUTS_B12_5", - "GTXE2_LOGIC_OUTS_B12_6", - "GTXE2_LOGIC_OUTS_B12_7", - "GTXE2_LOGIC_OUTS_B12_8", - "GTXE2_LOGIC_OUTS_B12_9", - "GTXE2_LOGIC_OUTS_B13_0", - "GTXE2_LOGIC_OUTS_B13_1", - "GTXE2_LOGIC_OUTS_B13_10", - "GTXE2_LOGIC_OUTS_B13_2", - "GTXE2_LOGIC_OUTS_B13_3", - "GTXE2_LOGIC_OUTS_B13_4", - "GTXE2_LOGIC_OUTS_B13_5", - "GTXE2_LOGIC_OUTS_B13_6", - "GTXE2_LOGIC_OUTS_B13_7", - "GTXE2_LOGIC_OUTS_B13_8", - "GTXE2_LOGIC_OUTS_B13_9", - "GTXE2_LOGIC_OUTS_B14_0", - "GTXE2_LOGIC_OUTS_B14_1", - "GTXE2_LOGIC_OUTS_B14_10", - "GTXE2_LOGIC_OUTS_B14_2", - "GTXE2_LOGIC_OUTS_B14_3", - "GTXE2_LOGIC_OUTS_B14_4", - "GTXE2_LOGIC_OUTS_B14_5", - "GTXE2_LOGIC_OUTS_B14_6", - "GTXE2_LOGIC_OUTS_B14_7", - "GTXE2_LOGIC_OUTS_B14_8", - "GTXE2_LOGIC_OUTS_B14_9", - "GTXE2_LOGIC_OUTS_B15_0", - "GTXE2_LOGIC_OUTS_B15_1", - "GTXE2_LOGIC_OUTS_B15_10", - "GTXE2_LOGIC_OUTS_B15_2", - "GTXE2_LOGIC_OUTS_B15_3", - "GTXE2_LOGIC_OUTS_B15_4", - "GTXE2_LOGIC_OUTS_B15_5", - "GTXE2_LOGIC_OUTS_B15_6", - "GTXE2_LOGIC_OUTS_B15_7", - "GTXE2_LOGIC_OUTS_B15_8", - "GTXE2_LOGIC_OUTS_B15_9", - "GTXE2_LOGIC_OUTS_B16_0", - "GTXE2_LOGIC_OUTS_B16_1", - "GTXE2_LOGIC_OUTS_B16_10", - "GTXE2_LOGIC_OUTS_B16_2", - "GTXE2_LOGIC_OUTS_B16_3", - "GTXE2_LOGIC_OUTS_B16_4", - "GTXE2_LOGIC_OUTS_B16_5", - "GTXE2_LOGIC_OUTS_B16_6", - "GTXE2_LOGIC_OUTS_B16_7", - "GTXE2_LOGIC_OUTS_B16_8", - "GTXE2_LOGIC_OUTS_B16_9", - "GTXE2_LOGIC_OUTS_B17_0", - "GTXE2_LOGIC_OUTS_B17_1", - "GTXE2_LOGIC_OUTS_B17_10", - "GTXE2_LOGIC_OUTS_B17_2", - "GTXE2_LOGIC_OUTS_B17_3", - "GTXE2_LOGIC_OUTS_B17_4", - "GTXE2_LOGIC_OUTS_B17_5", - "GTXE2_LOGIC_OUTS_B17_6", - "GTXE2_LOGIC_OUTS_B17_7", - "GTXE2_LOGIC_OUTS_B17_8", - "GTXE2_LOGIC_OUTS_B17_9", - "GTXE2_LOGIC_OUTS_B18_0", - "GTXE2_LOGIC_OUTS_B18_1", - "GTXE2_LOGIC_OUTS_B18_10", - "GTXE2_LOGIC_OUTS_B18_2", - "GTXE2_LOGIC_OUTS_B18_3", - "GTXE2_LOGIC_OUTS_B18_4", - "GTXE2_LOGIC_OUTS_B18_5", - "GTXE2_LOGIC_OUTS_B18_6", - "GTXE2_LOGIC_OUTS_B18_7", - "GTXE2_LOGIC_OUTS_B18_8", - "GTXE2_LOGIC_OUTS_B18_9", - "GTXE2_LOGIC_OUTS_B19_0", - "GTXE2_LOGIC_OUTS_B19_1", - "GTXE2_LOGIC_OUTS_B19_10", - "GTXE2_LOGIC_OUTS_B19_2", - "GTXE2_LOGIC_OUTS_B19_3", - "GTXE2_LOGIC_OUTS_B19_4", - "GTXE2_LOGIC_OUTS_B19_5", - "GTXE2_LOGIC_OUTS_B19_6", - "GTXE2_LOGIC_OUTS_B19_7", - "GTXE2_LOGIC_OUTS_B19_8", - "GTXE2_LOGIC_OUTS_B19_9", - "GTXE2_LOGIC_OUTS_B1_0", - "GTXE2_LOGIC_OUTS_B1_1", - "GTXE2_LOGIC_OUTS_B1_10", - "GTXE2_LOGIC_OUTS_B1_2", - "GTXE2_LOGIC_OUTS_B1_3", - "GTXE2_LOGIC_OUTS_B1_4", - "GTXE2_LOGIC_OUTS_B1_5", - "GTXE2_LOGIC_OUTS_B1_6", - "GTXE2_LOGIC_OUTS_B1_7", - "GTXE2_LOGIC_OUTS_B1_8", - "GTXE2_LOGIC_OUTS_B1_9", - "GTXE2_LOGIC_OUTS_B20_0", - "GTXE2_LOGIC_OUTS_B20_1", - "GTXE2_LOGIC_OUTS_B20_10", - "GTXE2_LOGIC_OUTS_B20_2", - "GTXE2_LOGIC_OUTS_B20_3", - "GTXE2_LOGIC_OUTS_B20_4", - "GTXE2_LOGIC_OUTS_B20_5", - "GTXE2_LOGIC_OUTS_B20_6", - "GTXE2_LOGIC_OUTS_B20_7", - "GTXE2_LOGIC_OUTS_B20_8", - "GTXE2_LOGIC_OUTS_B20_9", - "GTXE2_LOGIC_OUTS_B21_0", - "GTXE2_LOGIC_OUTS_B21_1", - "GTXE2_LOGIC_OUTS_B21_10", - "GTXE2_LOGIC_OUTS_B21_2", - "GTXE2_LOGIC_OUTS_B21_3", - "GTXE2_LOGIC_OUTS_B21_4", - "GTXE2_LOGIC_OUTS_B21_5", - "GTXE2_LOGIC_OUTS_B21_6", - "GTXE2_LOGIC_OUTS_B21_7", - "GTXE2_LOGIC_OUTS_B21_8", - "GTXE2_LOGIC_OUTS_B21_9", - "GTXE2_LOGIC_OUTS_B22_0", - "GTXE2_LOGIC_OUTS_B22_1", - "GTXE2_LOGIC_OUTS_B22_10", - "GTXE2_LOGIC_OUTS_B22_2", - "GTXE2_LOGIC_OUTS_B22_3", - "GTXE2_LOGIC_OUTS_B22_4", - "GTXE2_LOGIC_OUTS_B22_5", - "GTXE2_LOGIC_OUTS_B22_6", - "GTXE2_LOGIC_OUTS_B22_7", - "GTXE2_LOGIC_OUTS_B22_8", - "GTXE2_LOGIC_OUTS_B22_9", - "GTXE2_LOGIC_OUTS_B23_0", - "GTXE2_LOGIC_OUTS_B23_1", - "GTXE2_LOGIC_OUTS_B23_10", - "GTXE2_LOGIC_OUTS_B23_2", - "GTXE2_LOGIC_OUTS_B23_3", - "GTXE2_LOGIC_OUTS_B23_4", - "GTXE2_LOGIC_OUTS_B23_5", - "GTXE2_LOGIC_OUTS_B23_6", - "GTXE2_LOGIC_OUTS_B23_7", - "GTXE2_LOGIC_OUTS_B23_8", - "GTXE2_LOGIC_OUTS_B23_9", - "GTXE2_LOGIC_OUTS_B2_0", - "GTXE2_LOGIC_OUTS_B2_1", - "GTXE2_LOGIC_OUTS_B2_10", - "GTXE2_LOGIC_OUTS_B2_2", - "GTXE2_LOGIC_OUTS_B2_3", - "GTXE2_LOGIC_OUTS_B2_4", - "GTXE2_LOGIC_OUTS_B2_5", - "GTXE2_LOGIC_OUTS_B2_6", - "GTXE2_LOGIC_OUTS_B2_7", - "GTXE2_LOGIC_OUTS_B2_8", - "GTXE2_LOGIC_OUTS_B2_9", - "GTXE2_LOGIC_OUTS_B3_0", - "GTXE2_LOGIC_OUTS_B3_1", - "GTXE2_LOGIC_OUTS_B3_10", - "GTXE2_LOGIC_OUTS_B3_2", - "GTXE2_LOGIC_OUTS_B3_3", - "GTXE2_LOGIC_OUTS_B3_4", - "GTXE2_LOGIC_OUTS_B3_5", - "GTXE2_LOGIC_OUTS_B3_6", - "GTXE2_LOGIC_OUTS_B3_7", - "GTXE2_LOGIC_OUTS_B3_8", - "GTXE2_LOGIC_OUTS_B3_9", - "GTXE2_LOGIC_OUTS_B4_0", - "GTXE2_LOGIC_OUTS_B4_1", - "GTXE2_LOGIC_OUTS_B4_10", - "GTXE2_LOGIC_OUTS_B4_2", - "GTXE2_LOGIC_OUTS_B4_3", - "GTXE2_LOGIC_OUTS_B4_4", - "GTXE2_LOGIC_OUTS_B4_5", - "GTXE2_LOGIC_OUTS_B4_6", - "GTXE2_LOGIC_OUTS_B4_7", - "GTXE2_LOGIC_OUTS_B4_8", - "GTXE2_LOGIC_OUTS_B4_9", - "GTXE2_LOGIC_OUTS_B5_0", - "GTXE2_LOGIC_OUTS_B5_1", - "GTXE2_LOGIC_OUTS_B5_10", - "GTXE2_LOGIC_OUTS_B5_2", - "GTXE2_LOGIC_OUTS_B5_3", - "GTXE2_LOGIC_OUTS_B5_4", - "GTXE2_LOGIC_OUTS_B5_5", - "GTXE2_LOGIC_OUTS_B5_6", - "GTXE2_LOGIC_OUTS_B5_7", - "GTXE2_LOGIC_OUTS_B5_8", - "GTXE2_LOGIC_OUTS_B5_9", - "GTXE2_LOGIC_OUTS_B6_0", - "GTXE2_LOGIC_OUTS_B6_1", - "GTXE2_LOGIC_OUTS_B6_10", - "GTXE2_LOGIC_OUTS_B6_2", - "GTXE2_LOGIC_OUTS_B6_3", - "GTXE2_LOGIC_OUTS_B6_4", - "GTXE2_LOGIC_OUTS_B6_5", - "GTXE2_LOGIC_OUTS_B6_6", - "GTXE2_LOGIC_OUTS_B6_7", - "GTXE2_LOGIC_OUTS_B6_8", - "GTXE2_LOGIC_OUTS_B6_9", - "GTXE2_LOGIC_OUTS_B7_0", - "GTXE2_LOGIC_OUTS_B7_1", - "GTXE2_LOGIC_OUTS_B7_10", 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"GTXE2_LOGIC_OUTS_B6_7": null, + "GTXE2_LOGIC_OUTS_B6_8": null, + "GTXE2_LOGIC_OUTS_B6_9": null, + "GTXE2_LOGIC_OUTS_B7_0": null, + "GTXE2_LOGIC_OUTS_B7_1": null, + "GTXE2_LOGIC_OUTS_B7_10": null, + "GTXE2_LOGIC_OUTS_B7_2": null, + "GTXE2_LOGIC_OUTS_B7_3": null, + "GTXE2_LOGIC_OUTS_B7_4": null, + "GTXE2_LOGIC_OUTS_B7_5": null, + "GTXE2_LOGIC_OUTS_B7_6": null, + "GTXE2_LOGIC_OUTS_B7_7": null, + "GTXE2_LOGIC_OUTS_B7_8": null, + "GTXE2_LOGIC_OUTS_B7_9": null, + "GTXE2_LOGIC_OUTS_B8_0": null, + "GTXE2_LOGIC_OUTS_B8_1": null, + "GTXE2_LOGIC_OUTS_B8_10": null, + "GTXE2_LOGIC_OUTS_B8_2": null, + "GTXE2_LOGIC_OUTS_B8_3": null, + "GTXE2_LOGIC_OUTS_B8_4": null, + "GTXE2_LOGIC_OUTS_B8_5": null, + "GTXE2_LOGIC_OUTS_B8_6": null, + "GTXE2_LOGIC_OUTS_B8_7": null, + "GTXE2_LOGIC_OUTS_B8_8": null, + "GTXE2_LOGIC_OUTS_B8_9": null, + "GTXE2_LOGIC_OUTS_B9_0": null, + "GTXE2_LOGIC_OUTS_B9_1": null, + "GTXE2_LOGIC_OUTS_B9_10": null, + "GTXE2_LOGIC_OUTS_B9_2": null, + "GTXE2_LOGIC_OUTS_B9_3": null, + "GTXE2_LOGIC_OUTS_B9_4": null, + "GTXE2_LOGIC_OUTS_B9_5": null, + "GTXE2_LOGIC_OUTS_B9_6": null, + "GTXE2_LOGIC_OUTS_B9_7": null, + "GTXE2_LOGIC_OUTS_B9_8": null, + "GTXE2_LOGIC_OUTS_B9_9": null + } } diff --git a/kintex7/tile_type_GTX_CHANNEL_3.json b/kintex7/tile_type_GTX_CHANNEL_3.json index cc75aec..01931ac 100644 --- a/kintex7/tile_type_GTX_CHANNEL_3.json +++ b/kintex7/tile_type_GTX_CHANNEL_3.json @@ -2,4398 +2,11306 @@ "pips": { "GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLFBCLKLOST" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLLOCK->GTXE2_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLLOCK" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_CPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_CPLLREFCLKLOST" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT0->GTXE2_LOGIC_OUTS_B9_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT1->GTXE2_LOGIC_OUTS_B9_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT2->GTXE2_LOGIC_OUTS_B9_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT3->GTXE2_LOGIC_OUTS_B9_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT4->GTXE2_LOGIC_OUTS_B9_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT5->GTXE2_LOGIC_OUTS_B9_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT6->GTXE2_LOGIC_OUTS_B9_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DMONITOROUT7->GTXE2_LOGIC_OUTS_B9_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DMONITOROUT7" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO0->GTXE2_LOGIC_OUTS_B0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO1->GTXE2_LOGIC_OUTS_B4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO10->GTXE2_LOGIC_OUTS_B2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO10" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO11->GTXE2_LOGIC_OUTS_B6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO11" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO12->GTXE2_LOGIC_OUTS_B5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO12" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO13->GTXE2_LOGIC_OUTS_B1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO13" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO14->GTXE2_LOGIC_OUTS_B7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO14" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO15->GTXE2_LOGIC_OUTS_B3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO15" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO2->GTXE2_LOGIC_OUTS_B2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO3->GTXE2_LOGIC_OUTS_B6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO4->GTXE2_LOGIC_OUTS_B5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO5->GTXE2_LOGIC_OUTS_B1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO6->GTXE2_LOGIC_OUTS_B7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO7->GTXE2_LOGIC_OUTS_B3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO7" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO8->GTXE2_LOGIC_OUTS_B0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO8" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPDO9->GTXE2_LOGIC_OUTS_B4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPDO9" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_DRPRDY->GTXE2_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_DRPRDY" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_EYESCANDATAERROR->GTXE2_LOGIC_OUTS_B20_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_EYESCANDATAERROR" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_GTREFCLKMONITOR->GTXE2_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTREFCLKMONITOR" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_GTRXOUTCLK_3->GTXE2_CHANNEL_RXOUTCLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLK_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTRXOUTCLK_3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_GTTXOUTCLK_3->GTXE2_CHANNEL_TXOUTCLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLK_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_GTTXOUTCLK_3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_NORTHREFCLK0->GTXE2_CHANNEL_GTNORTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_NORTHREFCLK0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_NORTHREFCLK1->GTXE2_CHANNEL_GTNORTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTNORTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_NORTHREFCLK1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT0->GTXE2_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT1->GTXE2_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT10->GTXE2_LOGIC_OUTS_B13_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT10" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT11->GTXE2_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT11" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT12->GTXE2_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT12" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT13->GTXE2_LOGIC_OUTS_B9_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT13" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT14->GTXE2_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT14" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT15->GTXE2_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT15" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT2->GTXE2_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT3->GTXE2_LOGIC_OUTS_B13_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT4->GTXE2_LOGIC_OUTS_B13_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT5->GTXE2_LOGIC_OUTS_B13_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT6->GTXE2_LOGIC_OUTS_B13_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT7->GTXE2_LOGIC_OUTS_B13_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT7" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT8->GTXE2_LOGIC_OUTS_B13_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT8" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PCSRSVDOUT9->GTXE2_LOGIC_OUTS_B13_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PCSRSVDOUT9" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_PHYSTATUS->GTXE2_LOGIC_OUTS_B10_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_PHYSTATUS" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_QPLLCLK->GTXE2_CHANNEL_GTQPLLCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTQPLLCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_QPLLCLK" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_QPLLREFCLK->GTXE2_CHANNEL_GTQPLLREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTQPLLREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_QPLLREFCLK" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_REFCLK0->GTXE2_CHANNEL_GTREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_REFCLK0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_REFCLK1->GTXE2_CHANNEL_GTREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_REFCLK1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBUFSTATUS0->GTXE2_LOGIC_OUTS_B23_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBUFSTATUS1->GTXE2_LOGIC_OUTS_B19_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBUFSTATUS2->GTXE2_LOGIC_OUTS_B17_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBUFSTATUS2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBYTEISALIGNED->GTXE2_LOGIC_OUTS_B18_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBYTEISALIGNED" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXBYTEREALIGN->GTXE2_LOGIC_OUTS_B10_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXBYTEREALIGN" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCDRLOCK->GTXE2_LOGIC_OUTS_B17_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCDRLOCK" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHANBONDSEQ->GTXE2_LOGIC_OUTS_B10_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANBONDSEQ" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHANISALIGNED->GTXE2_LOGIC_OUTS_B18_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANISALIGNED" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHANREALIGN->GTXE2_LOGIC_OUTS_B23_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHANREALIGN" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA0->GTXE2_LOGIC_OUTS_B15_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA1->GTXE2_LOGIC_OUTS_B15_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA2->GTXE2_LOGIC_OUTS_B15_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA3->GTXE2_LOGIC_OUTS_B15_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA4->GTXE2_LOGIC_OUTS_B15_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA5->GTXE2_LOGIC_OUTS_B15_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA6->GTXE2_LOGIC_OUTS_B15_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISCOMMA7->GTXE2_LOGIC_OUTS_B15_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISCOMMA7" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK0->GTXE2_LOGIC_OUTS_B12_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK1->GTXE2_LOGIC_OUTS_B12_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK2->GTXE2_LOGIC_OUTS_B12_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK3->GTXE2_LOGIC_OUTS_B12_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK4->GTXE2_LOGIC_OUTS_B12_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK5->GTXE2_LOGIC_OUTS_B12_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK6->GTXE2_LOGIC_OUTS_B12_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHARISK7->GTXE2_LOGIC_OUTS_B12_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHARISK7" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO0->GTXE2_LOGIC_OUTS_B16_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO1->GTXE2_LOGIC_OUTS_B16_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO2->GTXE2_LOGIC_OUTS_B16_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO3->GTXE2_LOGIC_OUTS_B16_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCHBONDO4->GTXE2_LOGIC_OUTS_B16_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCHBONDO4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCLKCORCNT0->GTXE2_LOGIC_OUTS_B18_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCLKCORCNT1->GTXE2_LOGIC_OUTS_B20_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCLKCORCNT1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCOMINITDET->GTXE2_LOGIC_OUTS_B20_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMINITDET" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCOMMADET->GTXE2_LOGIC_OUTS_B19_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMMADET" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCOMSASDET->GTXE2_LOGIC_OUTS_B18_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMSASDET" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXCOMWAKEDET->GTXE2_LOGIC_OUTS_B19_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXCOMWAKEDET" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA0->GTXE2_LOGIC_OUTS_B6_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA1->GTXE2_LOGIC_OUTS_B2_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA10->GTXE2_LOGIC_OUTS_B4_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA10" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA11->GTXE2_LOGIC_OUTS_B0_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA11" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA12->GTXE2_LOGIC_OUTS_B3_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA12" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA13->GTXE2_LOGIC_OUTS_B7_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA13" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA14->GTXE2_LOGIC_OUTS_B1_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA14" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA15->GTXE2_LOGIC_OUTS_B5_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA15" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA16->GTXE2_LOGIC_OUTS_B6_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA16" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA17->GTXE2_LOGIC_OUTS_B2_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA17" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA18->GTXE2_LOGIC_OUTS_B4_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA18" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA19->GTXE2_LOGIC_OUTS_B0_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA19" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA2->GTXE2_LOGIC_OUTS_B4_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA20->GTXE2_LOGIC_OUTS_B3_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA20" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA21->GTXE2_LOGIC_OUTS_B7_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA21" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA22->GTXE2_LOGIC_OUTS_B1_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA22" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA23->GTXE2_LOGIC_OUTS_B5_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA23" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA24->GTXE2_LOGIC_OUTS_B6_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA24" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA25->GTXE2_LOGIC_OUTS_B2_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA25" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA26->GTXE2_LOGIC_OUTS_B4_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA26" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA27->GTXE2_LOGIC_OUTS_B0_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA27" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA28->GTXE2_LOGIC_OUTS_B3_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA28" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA29->GTXE2_LOGIC_OUTS_B7_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA29" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA3->GTXE2_LOGIC_OUTS_B0_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA30->GTXE2_LOGIC_OUTS_B1_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA30" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA31->GTXE2_LOGIC_OUTS_B5_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA31" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA32->GTXE2_LOGIC_OUTS_B3_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA32" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA33->GTXE2_LOGIC_OUTS_B7_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA33" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA34->GTXE2_LOGIC_OUTS_B1_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA34" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA35->GTXE2_LOGIC_OUTS_B5_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA35" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA36->GTXE2_LOGIC_OUTS_B6_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA36" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA37->GTXE2_LOGIC_OUTS_B2_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA37" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA38->GTXE2_LOGIC_OUTS_B4_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA38" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA39->GTXE2_LOGIC_OUTS_B0_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA39" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA4->GTXE2_LOGIC_OUTS_B3_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA40->GTXE2_LOGIC_OUTS_B3_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA40" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA41->GTXE2_LOGIC_OUTS_B7_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA41" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA42->GTXE2_LOGIC_OUTS_B1_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA42" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA43->GTXE2_LOGIC_OUTS_B5_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA43" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA44->GTXE2_LOGIC_OUTS_B6_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA44" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA45->GTXE2_LOGIC_OUTS_B2_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA45" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA46->GTXE2_LOGIC_OUTS_B4_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA46" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA47->GTXE2_LOGIC_OUTS_B0_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA47" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA48->GTXE2_LOGIC_OUTS_B3_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA48" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA49->GTXE2_LOGIC_OUTS_B7_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA49" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA5->GTXE2_LOGIC_OUTS_B7_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA50->GTXE2_LOGIC_OUTS_B1_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA50" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA51->GTXE2_LOGIC_OUTS_B5_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA51" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA52->GTXE2_LOGIC_OUTS_B6_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA52" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA53->GTXE2_LOGIC_OUTS_B2_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA53" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA54->GTXE2_LOGIC_OUTS_B4_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA54" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA55->GTXE2_LOGIC_OUTS_B0_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA55" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA56->GTXE2_LOGIC_OUTS_B3_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA56" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA57->GTXE2_LOGIC_OUTS_B7_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA57" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA58->GTXE2_LOGIC_OUTS_B1_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA58" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA59->GTXE2_LOGIC_OUTS_B5_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA59" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA6->GTXE2_LOGIC_OUTS_B1_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA60->GTXE2_LOGIC_OUTS_B6_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA60" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA61->GTXE2_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA61" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA62->GTXE2_LOGIC_OUTS_B4_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA62" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA63->GTXE2_LOGIC_OUTS_B0_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA63" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA7->GTXE2_LOGIC_OUTS_B5_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA7" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA8->GTXE2_LOGIC_OUTS_B6_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA8" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATA9->GTXE2_LOGIC_OUTS_B2_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATA9" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDATAVALID->GTXE2_LOGIC_OUTS_B19_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDATAVALID" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR0->GTXE2_LOGIC_OUTS_B22_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR1->GTXE2_LOGIC_OUTS_B22_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR2->GTXE2_LOGIC_OUTS_B22_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR3->GTXE2_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR4->GTXE2_LOGIC_OUTS_B22_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR5->GTXE2_LOGIC_OUTS_B22_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR6->GTXE2_LOGIC_OUTS_B22_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDISPERR7->GTXE2_LOGIC_OUTS_B22_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDISPERR7" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXDLYSRESETDONE" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXELECIDLE->GTXE2_LOGIC_OUTS_B19_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXELECIDLE" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXHEADER0->GTXE2_LOGIC_OUTS_B19_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXHEADER1->GTXE2_LOGIC_OUTS_B23_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXHEADER2->GTXE2_LOGIC_OUTS_B17_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADER2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXHEADERVALID->GTXE2_LOGIC_OUTS_B23_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXHEADERVALID" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT0->GTXE2_LOGIC_OUTS_B8_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT1->GTXE2_LOGIC_OUTS_B8_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT2->GTXE2_LOGIC_OUTS_B8_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT3->GTXE2_LOGIC_OUTS_B8_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT4->GTXE2_LOGIC_OUTS_B8_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT5->GTXE2_LOGIC_OUTS_B8_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXMONITOROUT6->GTXE2_LOGIC_OUTS_B8_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXMONITOROUT6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE0->GTXE2_LOGIC_OUTS_B14_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE1->GTXE2_LOGIC_OUTS_B14_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE2->GTXE2_LOGIC_OUTS_B14_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE3->GTXE2_LOGIC_OUTS_B14_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE4->GTXE2_LOGIC_OUTS_B14_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE5->GTXE2_LOGIC_OUTS_B14_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE6->GTXE2_LOGIC_OUTS_B14_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXNOTINTABLE7->GTXE2_LOGIC_OUTS_B14_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXNOTINTABLE7" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXN_PAD->GTXE2_CHANNEL_RXN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXN_PAD" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B17_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXOUTCLKFABRIC" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXOUTCLKPCS->GTXE2_LOGIC_OUTS_B21_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXOUTCLKPCS" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHALIGNDONE" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR0->GTXE2_LOGIC_OUTS_B5_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B5_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR1->GTXE2_LOGIC_OUTS_B1_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B1_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR2->GTXE2_LOGIC_OUTS_B7_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B7_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR3->GTXE2_LOGIC_OUTS_B3_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B3_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHMONITOR4->GTXE2_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHMONITOR4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR0->GTXE2_LOGIC_OUTS_B0_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B0_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR1->GTXE2_LOGIC_OUTS_B4_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B4_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR2->GTXE2_LOGIC_OUTS_B2_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR3->GTXE2_LOGIC_OUTS_B6_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B6_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPHSLIPMONITOR4->GTXE2_LOGIC_OUTS_B16_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPHSLIPMONITOR4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXPRBSERR->GTXE2_LOGIC_OUTS_B20_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXPRBSERR" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXP_PAD->GTXE2_CHANNEL_RXP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXP_PAD" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXQPISENN->GTXE2_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXQPISENN" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXQPISENP->GTXE2_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXQPISENP" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXRATEDONE->GTXE2_LOGIC_OUTS_B23_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXRATEDONE" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXRESETDONE->GTXE2_LOGIC_OUTS_B20_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXRESETDONE" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXSTARTOFSEQ->GTXE2_LOGIC_OUTS_B18_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTARTOFSEQ" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXSTATUS0->GTXE2_LOGIC_OUTS_B21_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXSTATUS1->GTXE2_LOGIC_OUTS_B17_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXSTATUS2->GTXE2_LOGIC_OUTS_B23_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXSTATUS2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_RXVALID->GTXE2_LOGIC_OUTS_B20_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_RXVALID" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_SOUTHREFCLK0->GTXE2_CHANNEL_GTSOUTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_SOUTHREFCLK1->GTXE2_CHANNEL_GTSOUTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTSOUTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_SOUTHREFCLK1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT0->GTXE2_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT1->GTXE2_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT2->GTXE2_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT2" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT3->GTXE2_LOGIC_OUTS_B11_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT3" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT4->GTXE2_LOGIC_OUTS_B11_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT4" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT5->GTXE2_LOGIC_OUTS_B11_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT5" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT6->GTXE2_LOGIC_OUTS_B11_6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT6" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT7->GTXE2_LOGIC_OUTS_B11_7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT7" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT8->GTXE2_LOGIC_OUTS_B11_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT8" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TSTOUT9->GTXE2_LOGIC_OUTS_B11_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TSTOUT9" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXBUFSTATUS0->GTXE2_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS0" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXBUFSTATUS1->GTXE2_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXBUFSTATUS1" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXCOMFINISH->GTXE2_LOGIC_OUTS_B16_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXCOMFINISH" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXDLYSRESETDONE->GTXE2_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXDLYSRESETDONE" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXGEARBOXREADY->GTXE2_LOGIC_OUTS_B23_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXGEARBOXREADY" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXN->GTXE2_CHANNEL_TXN_PAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXN_PAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXN" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXOUTCLKFABRIC->GTXE2_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXOUTCLKFABRIC" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXOUTCLKPCS->GTXE2_LOGIC_OUTS_B17_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXOUTCLKPCS" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXP->GTXE2_CHANNEL_TXP_PAD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXP_PAD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXP" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHALIGNDONE->GTXE2_LOGIC_OUTS_B18_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXPHALIGNDONE" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXPHINITDONE->GTXE2_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXPHINITDONE" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXQPISENN->GTXE2_LOGIC_OUTS_B20_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXQPISENN" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXQPISENP->GTXE2_LOGIC_OUTS_B8_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXQPISENP" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXRATEDONE->GTXE2_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXRATEDONE" }, "GTX_CHANNEL_3.GTXE2_CHANNEL_TXRESETDONE->GTXE2_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CHANNEL_TXRESETDONE" }, "GTX_CHANNEL_3.GTXE2_CLK0_2->GTXE2_CHANNEL_CPLLLOCKDETCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLLOCKDETCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_2" }, "GTX_CHANNEL_3.GTXE2_CLK0_4->GTXE2_CHANNEL_TXUSRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_4" }, "GTX_CHANNEL_3.GTXE2_CLK0_5->GTXE2_CHANNEL_TXUSRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSRCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_5" }, "GTX_CHANNEL_3.GTXE2_CLK0_6->GTXE2_CHANNEL_RXUSRCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSRCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_6" }, "GTX_CHANNEL_3.GTXE2_CLK0_7->GTXE2_CHANNEL_RXUSRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSRCLK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_7" }, "GTX_CHANNEL_3.GTXE2_CLK1_1->GTXE2_CHANNEL_DRPCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_1" }, "GTX_CHANNEL_3.GTXE2_CLK1_2->GTXE2_CHANNEL_TXPHDLYTSTCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYTSTCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_2" }, "GTX_CHANNEL_3.GTXE2_CLK1_4->GTXE2_CHANNEL_CLKRSVD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_4" }, "GTX_CHANNEL_3.GTXE2_CLK1_5->GTXE2_CHANNEL_CLKRSVD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_5" }, "GTX_CHANNEL_3.GTXE2_CLK1_6->GTXE2_CHANNEL_GTGREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTGREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_6" }, "GTX_CHANNEL_3.GTXE2_CLK1_7->GTXE2_CHANNEL_CLKRSVD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_7" }, "GTX_CHANNEL_3.GTXE2_CLK1_8->GTXE2_CHANNEL_CLKRSVD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CLKRSVD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_8" }, "GTX_CHANNEL_3.GTXE2_CTRL0_10->GTXE2_CHANNEL_GTRESETSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRESETSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_10" }, "GTX_CHANNEL_3.GTXE2_CTRL0_3->GTXE2_CHANNEL_CPLLRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_3" }, "GTX_CHANNEL_3.GTXE2_CTRL0_5->GTXE2_CHANNEL_GTTXRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTTXRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_5" }, "GTX_CHANNEL_3.GTXE2_CTRL0_6->GTXE2_CHANNEL_RXDLYSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_6" }, "GTX_CHANNEL_3.GTXE2_CTRL0_7->GTXE2_CHANNEL_RXCDRFREQRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRFREQRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_7" }, "GTX_CHANNEL_3.GTXE2_CTRL0_8->GTXE2_CHANNEL_GTRXRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRXRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_8" }, "GTX_CHANNEL_3.GTXE2_CTRL0_9->GTXE2_CHANNEL_RXDFELPMRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELPMRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_9" }, "GTX_CHANNEL_3.GTXE2_CTRL1_1->GTXE2_CHANNEL_RXPHDLYRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHDLYRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_1" }, "GTX_CHANNEL_3.GTXE2_CTRL1_10->GTXE2_CHANNEL_RXOOBRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOOBRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_10" }, "GTX_CHANNEL_3.GTXE2_CTRL1_3->GTXE2_CHANNEL_TXPMARESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPMARESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_3" }, "GTX_CHANNEL_3.GTXE2_CTRL1_5->GTXE2_CHANNEL_CFGRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CFGRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_5" }, "GTX_CHANNEL_3.GTXE2_CTRL1_6->GTXE2_CHANNEL_RXBUFRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXBUFRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_6" }, "GTX_CHANNEL_3.GTXE2_CTRL1_7->GTXE2_CHANNEL_RXPMARESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPMARESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_7" }, "GTX_CHANNEL_3.GTXE2_CTRL1_8->GTXE2_CHANNEL_RXCDRRESETRSV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRRESETRSV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_8" }, "GTX_CHANNEL_3.GTXE2_CTRL1_9->GTXE2_CHANNEL_RXCDRRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_9" }, "GTX_CHANNEL_3.GTXE2_IMUX0_10->GTXE2_CHANNEL_RXELECIDLEMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_10" }, "GTX_CHANNEL_3.GTXE2_IMUX0_2->GTXE2_CHANNEL_TX8B10BEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_2" }, "GTX_CHANNEL_3.GTXE2_IMUX0_3->GTXE2_CHANNEL_TXMAINCURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_3" }, "GTX_CHANNEL_3.GTXE2_IMUX0_5->GTXE2_CHANNEL_TXSEQUENCE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_5" }, "GTX_CHANNEL_3.GTXE2_IMUX0_6->GTXE2_CHANNEL_PMARSVDIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_6" }, "GTX_CHANNEL_3.GTXE2_IMUX0_7->GTXE2_CHANNEL_PMARSVDIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_7" }, "GTX_CHANNEL_3.GTXE2_IMUX0_8->GTXE2_CHANNEL_PMARSVDIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_8" }, "GTX_CHANNEL_3.GTXE2_IMUX0_9->GTXE2_CHANNEL_PMARSVDIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX0_9" }, "GTX_CHANNEL_3.GTXE2_IMUX10_0->GTXE2_CHANNEL_TXCHARDISPVAL7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_0" }, "GTX_CHANNEL_3.GTXE2_IMUX10_1->GTXE2_CHANNEL_TXPDELECIDLEMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPDELECIDLEMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_1" }, "GTX_CHANNEL_3.GTXE2_IMUX10_2->GTXE2_CHANNEL_TXCHARDISPVAL6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_2" }, "GTX_CHANNEL_3.GTXE2_IMUX10_4->GTXE2_CHANNEL_TXCHARDISPVAL5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_4" }, "GTX_CHANNEL_3.GTXE2_IMUX10_5->GTXE2_CHANNEL_TXUSERRDY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXUSERRDY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_5" }, "GTX_CHANNEL_3.GTXE2_IMUX10_6->GTXE2_CHANNEL_TXCHARDISPVAL4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_6" }, "GTX_CHANNEL_3.GTXE2_IMUX10_7->GTXE2_CHANNEL_TXBUFDIFFCTRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_7" }, "GTX_CHANNEL_3.GTXE2_IMUX10_9->GTXE2_CHANNEL_RXQPIEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXQPIEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX10_9" }, "GTX_CHANNEL_3.GTXE2_IMUX11_10->GTXE2_CHANNEL_RXLPMLFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMLFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_10" }, "GTX_CHANNEL_3.GTXE2_IMUX11_2->GTXE2_CHANNEL_CPLLREFCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_2" }, "GTX_CHANNEL_3.GTXE2_IMUX11_5->GTXE2_CHANNEL_TXDLYHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_5" }, "GTX_CHANNEL_3.GTXE2_IMUX11_6->GTXE2_CHANNEL_RXRATE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_6" }, "GTX_CHANNEL_3.GTXE2_IMUX11_8->GTXE2_CHANNEL_RXDFEVSEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVSEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX11_8" }, "GTX_CHANNEL_3.GTXE2_IMUX12_1->GTXE2_CHANNEL_TXCOMWAKE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMWAKE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_1" }, "GTX_CHANNEL_3.GTXE2_IMUX12_10->GTXE2_CHANNEL_RXDFETAP3OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_10" }, "GTX_CHANNEL_3.GTXE2_IMUX12_2->GTXE2_CHANNEL_TXHEADER1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_2" }, "GTX_CHANNEL_3.GTXE2_IMUX12_4->GTXE2_CHANNEL_TXPHOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_4" }, "GTX_CHANNEL_3.GTXE2_IMUX12_5->GTXE2_CHANNEL_TXDLYOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_5" }, "GTX_CHANNEL_3.GTXE2_IMUX12_7->GTXE2_CHANNEL_TXBUFDIFFCTRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_7" }, "GTX_CHANNEL_3.GTXE2_IMUX12_8->GTXE2_CHANNEL_RXSLIDE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSLIDE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_8" }, "GTX_CHANNEL_3.GTXE2_IMUX12_9->GTXE2_CHANNEL_RX8B10BEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RX8B10BEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX12_9" }, "GTX_CHANNEL_3.GTXE2_IMUX13_1->GTXE2_CHANNEL_TXQPISTRONGPDOWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_1" }, "GTX_CHANNEL_3.GTXE2_IMUX13_10->GTXE2_CHANNEL_RXPRBSCNTRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSCNTRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_10" }, "GTX_CHANNEL_3.GTXE2_IMUX13_2->GTXE2_CHANNEL_TXHEADER0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_2" }, "GTX_CHANNEL_3.GTXE2_IMUX13_7->GTXE2_CHANNEL_TXBUFDIFFCTRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_7" }, "GTX_CHANNEL_3.GTXE2_IMUX13_8->GTXE2_CHANNEL_RXOSOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOSOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_8" }, "GTX_CHANNEL_3.GTXE2_IMUX13_9->GTXE2_CHANNEL_RXDFETAP5OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX13_9" }, "GTX_CHANNEL_3.GTXE2_IMUX14_10->GTXE2_CHANNEL_RXPHOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_10" }, "GTX_CHANNEL_3.GTXE2_IMUX14_2->GTXE2_CHANNEL_CPLLREFCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_2" }, "GTX_CHANNEL_3.GTXE2_IMUX14_5->GTXE2_CHANNEL_TXDLYEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_5" }, "GTX_CHANNEL_3.GTXE2_IMUX14_6->GTXE2_CHANNEL_RXRATE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_6" }, "GTX_CHANNEL_3.GTXE2_IMUX14_7->GTXE2_CHANNEL_RXPCSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPCSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_7" }, "GTX_CHANNEL_3.GTXE2_IMUX14_8->GTXE2_CHANNEL_RXCDROVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDROVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_8" }, "GTX_CHANNEL_3.GTXE2_IMUX14_9->GTXE2_CHANNEL_RXPHALIGN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHALIGN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX14_9" }, "GTX_CHANNEL_3.GTXE2_IMUX15_1->GTXE2_CHANNEL_TX8B10BBYPASS3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_1" }, "GTX_CHANNEL_3.GTXE2_IMUX15_2->GTXE2_CHANNEL_CPLLREFCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLREFCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_2" }, "GTX_CHANNEL_3.GTXE2_IMUX15_3->GTXE2_CHANNEL_TX8B10BBYPASS2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_3" }, "GTX_CHANNEL_3.GTXE2_IMUX15_4->GTXE2_CHANNEL_TXPRBSFORCEERR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSFORCEERR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_4" }, "GTX_CHANNEL_3.GTXE2_IMUX15_5->GTXE2_CHANNEL_TX8B10BBYPASS1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_5" }, "GTX_CHANNEL_3.GTXE2_IMUX15_6->GTXE2_CHANNEL_RXRATE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXRATE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_6" }, "GTX_CHANNEL_3.GTXE2_IMUX15_7->GTXE2_CHANNEL_TX8B10BBYPASS0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX15_7" }, "GTX_CHANNEL_3.GTXE2_IMUX16_0->GTXE2_CHANNEL_TXDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_0" }, "GTX_CHANNEL_3.GTXE2_IMUX16_1->GTXE2_CHANNEL_TXDATA56": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA56", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_1" }, "GTX_CHANNEL_3.GTXE2_IMUX16_10->GTXE2_CHANNEL_RXDFECM1EN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFECM1EN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_10" }, "GTX_CHANNEL_3.GTXE2_IMUX16_2->GTXE2_CHANNEL_TXDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_2" }, "GTX_CHANNEL_3.GTXE2_IMUX16_3->GTXE2_CHANNEL_TXDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_3" }, "GTX_CHANNEL_3.GTXE2_IMUX16_4->GTXE2_CHANNEL_TXDATA12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_4" }, "GTX_CHANNEL_3.GTXE2_IMUX16_5->GTXE2_CHANNEL_TXDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_5" }, "GTX_CHANNEL_3.GTXE2_IMUX16_6->GTXE2_CHANNEL_TXDATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_6" }, "GTX_CHANNEL_3.GTXE2_IMUX16_7->GTXE2_CHANNEL_TXDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_7" }, "GTX_CHANNEL_3.GTXE2_IMUX17_0->GTXE2_CHANNEL_TXDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_0" }, "GTX_CHANNEL_3.GTXE2_IMUX17_1->GTXE2_CHANNEL_TXDATA57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_1" }, "GTX_CHANNEL_3.GTXE2_IMUX17_2->GTXE2_CHANNEL_TXDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_2" }, "GTX_CHANNEL_3.GTXE2_IMUX17_3->GTXE2_CHANNEL_TXDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_3" }, "GTX_CHANNEL_3.GTXE2_IMUX17_4->GTXE2_CHANNEL_TXDATA13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_4" }, "GTX_CHANNEL_3.GTXE2_IMUX17_5->GTXE2_CHANNEL_TXDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_5" }, "GTX_CHANNEL_3.GTXE2_IMUX17_6->GTXE2_CHANNEL_TXDATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_6" }, "GTX_CHANNEL_3.GTXE2_IMUX17_7->GTXE2_CHANNEL_TXDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_7" }, "GTX_CHANNEL_3.GTXE2_IMUX17_9->GTXE2_CHANNEL_RXCHBONDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_9" }, "GTX_CHANNEL_3.GTXE2_IMUX18_0->GTXE2_CHANNEL_TXDATA60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_0" }, "GTX_CHANNEL_3.GTXE2_IMUX18_1->GTXE2_CHANNEL_TXDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_1" }, "GTX_CHANNEL_3.GTXE2_IMUX18_10->GTXE2_CHANNEL_RXCHBONDLEVEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_10" }, "GTX_CHANNEL_3.GTXE2_IMUX18_2->GTXE2_CHANNEL_TXDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_2" }, "GTX_CHANNEL_3.GTXE2_IMUX18_3->GTXE2_CHANNEL_TXDATA16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_3" }, "GTX_CHANNEL_3.GTXE2_IMUX18_4->GTXE2_CHANNEL_TXDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_4" }, "GTX_CHANNEL_3.GTXE2_IMUX18_5->GTXE2_CHANNEL_TXDATA8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_5" }, "GTX_CHANNEL_3.GTXE2_IMUX18_6->GTXE2_CHANNEL_TXDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_6" }, "GTX_CHANNEL_3.GTXE2_IMUX18_7->GTXE2_CHANNEL_TXDATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_7" }, "GTX_CHANNEL_3.GTXE2_IMUX18_9->GTXE2_CHANNEL_RXCHBONDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_9" }, "GTX_CHANNEL_3.GTXE2_IMUX19_0->GTXE2_CHANNEL_TXDATA61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_0" }, "GTX_CHANNEL_3.GTXE2_IMUX19_1->GTXE2_CHANNEL_TXDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_1" }, "GTX_CHANNEL_3.GTXE2_IMUX19_10->GTXE2_CHANNEL_RXCHBONDLEVEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_10" }, "GTX_CHANNEL_3.GTXE2_IMUX19_2->GTXE2_CHANNEL_TXDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_2" }, "GTX_CHANNEL_3.GTXE2_IMUX19_3->GTXE2_CHANNEL_TXDATA17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_3" }, "GTX_CHANNEL_3.GTXE2_IMUX19_4->GTXE2_CHANNEL_TXDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_4" }, "GTX_CHANNEL_3.GTXE2_IMUX19_5->GTXE2_CHANNEL_TXDATA9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_5" }, "GTX_CHANNEL_3.GTXE2_IMUX19_6->GTXE2_CHANNEL_TXDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_6" }, "GTX_CHANNEL_3.GTXE2_IMUX19_7->GTXE2_CHANNEL_TXDATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_7" }, "GTX_CHANNEL_3.GTXE2_IMUX19_8->GTXE2_CHANNEL_RXDFEVPHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVPHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_8" }, "GTX_CHANNEL_3.GTXE2_IMUX19_9->GTXE2_CHANNEL_RXCHBONDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_9" }, "GTX_CHANNEL_3.GTXE2_IMUX1_10->GTXE2_CHANNEL_RXELECIDLEMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXELECIDLEMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_10" }, "GTX_CHANNEL_3.GTXE2_IMUX1_2->GTXE2_CHANNEL_RXMONITORSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_2" }, "GTX_CHANNEL_3.GTXE2_IMUX1_3->GTXE2_CHANNEL_TXMAINCURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_3" }, "GTX_CHANNEL_3.GTXE2_IMUX1_4->GTXE2_CHANNEL_TXMAINCURSOR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_4" }, "GTX_CHANNEL_3.GTXE2_IMUX1_5->GTXE2_CHANNEL_TXSEQUENCE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_5" }, "GTX_CHANNEL_3.GTXE2_IMUX1_6->GTXE2_CHANNEL_TXSEQUENCE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_6" }, "GTX_CHANNEL_3.GTXE2_IMUX1_7->GTXE2_CHANNEL_PMARSVDIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_7" }, "GTX_CHANNEL_3.GTXE2_IMUX1_8->GTXE2_CHANNEL_TXOUTCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_8" }, "GTX_CHANNEL_3.GTXE2_IMUX1_9->GTXE2_CHANNEL_PMARSVDIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX1_9" }, "GTX_CHANNEL_3.GTXE2_IMUX20_0->GTXE2_CHANNEL_TXDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_0" }, "GTX_CHANNEL_3.GTXE2_IMUX20_1->GTXE2_CHANNEL_TXDATA58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_1" }, "GTX_CHANNEL_3.GTXE2_IMUX20_2->GTXE2_CHANNEL_TXDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_2" }, "GTX_CHANNEL_3.GTXE2_IMUX20_3->GTXE2_CHANNEL_TXDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_3" }, "GTX_CHANNEL_3.GTXE2_IMUX20_4->GTXE2_CHANNEL_TXDATA14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_4" }, "GTX_CHANNEL_3.GTXE2_IMUX20_5->GTXE2_CHANNEL_TXDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_5" }, "GTX_CHANNEL_3.GTXE2_IMUX20_6->GTXE2_CHANNEL_TXDATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_6" }, "GTX_CHANNEL_3.GTXE2_IMUX20_7->GTXE2_CHANNEL_TXDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_7" }, "GTX_CHANNEL_3.GTXE2_IMUX21_0->GTXE2_CHANNEL_TXDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_0" }, "GTX_CHANNEL_3.GTXE2_IMUX21_1->GTXE2_CHANNEL_TXDATA59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_1" }, "GTX_CHANNEL_3.GTXE2_IMUX21_10->GTXE2_CHANNEL_RXDFEAGCOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_10" }, "GTX_CHANNEL_3.GTXE2_IMUX21_2->GTXE2_CHANNEL_TXDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_2" }, "GTX_CHANNEL_3.GTXE2_IMUX21_3->GTXE2_CHANNEL_TXDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_3" }, "GTX_CHANNEL_3.GTXE2_IMUX21_4->GTXE2_CHANNEL_TXDATA15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_4" }, "GTX_CHANNEL_3.GTXE2_IMUX21_5->GTXE2_CHANNEL_TXDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_5" }, "GTX_CHANNEL_3.GTXE2_IMUX21_6->GTXE2_CHANNEL_TXDATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_6" }, "GTX_CHANNEL_3.GTXE2_IMUX21_7->GTXE2_CHANNEL_TXDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_7" }, "GTX_CHANNEL_3.GTXE2_IMUX21_8->GTXE2_CHANNEL_RXDFEXYDOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_8" }, "GTX_CHANNEL_3.GTXE2_IMUX21_9->GTXE2_CHANNEL_RXDFETAP4OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_9" }, "GTX_CHANNEL_3.GTXE2_IMUX22_0->GTXE2_CHANNEL_TXDATA62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_0" }, "GTX_CHANNEL_3.GTXE2_IMUX22_1->GTXE2_CHANNEL_TXDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_1" }, "GTX_CHANNEL_3.GTXE2_IMUX22_10->GTXE2_CHANNEL_RXCHBONDLEVEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDLEVEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_10" }, "GTX_CHANNEL_3.GTXE2_IMUX22_2->GTXE2_CHANNEL_TXDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_2" }, "GTX_CHANNEL_3.GTXE2_IMUX22_3->GTXE2_CHANNEL_TXDATA18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_3" }, "GTX_CHANNEL_3.GTXE2_IMUX22_4->GTXE2_CHANNEL_TXDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_4" }, "GTX_CHANNEL_3.GTXE2_IMUX22_5->GTXE2_CHANNEL_TXDATA10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_5" }, "GTX_CHANNEL_3.GTXE2_IMUX22_6->GTXE2_CHANNEL_TXDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_6" }, "GTX_CHANNEL_3.GTXE2_IMUX22_7->GTXE2_CHANNEL_TXDATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_7" }, "GTX_CHANNEL_3.GTXE2_IMUX22_8->GTXE2_CHANNEL_RXPRBSSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_8" }, "GTX_CHANNEL_3.GTXE2_IMUX22_9->GTXE2_CHANNEL_RXCHBONDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_9" }, "GTX_CHANNEL_3.GTXE2_IMUX23_0->GTXE2_CHANNEL_TXDATA63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_0" }, "GTX_CHANNEL_3.GTXE2_IMUX23_1->GTXE2_CHANNEL_TXDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_1" }, "GTX_CHANNEL_3.GTXE2_IMUX23_10->GTXE2_CHANNEL_RXCHBONDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_10" }, "GTX_CHANNEL_3.GTXE2_IMUX23_2->GTXE2_CHANNEL_TXDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_2" }, "GTX_CHANNEL_3.GTXE2_IMUX23_3->GTXE2_CHANNEL_TXDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_3" }, "GTX_CHANNEL_3.GTXE2_IMUX23_4->GTXE2_CHANNEL_TXDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_4" }, "GTX_CHANNEL_3.GTXE2_IMUX23_5->GTXE2_CHANNEL_TXDATA11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_5" }, "GTX_CHANNEL_3.GTXE2_IMUX23_6->GTXE2_CHANNEL_TXDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_6" }, "GTX_CHANNEL_3.GTXE2_IMUX23_7->GTXE2_CHANNEL_TXDATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_7" }, "GTX_CHANNEL_3.GTXE2_IMUX23_8->GTXE2_CHANNEL_RXPRBSSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_8" }, "GTX_CHANNEL_3.GTXE2_IMUX23_9->GTXE2_CHANNEL_RXCHBONDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_9" }, "GTX_CHANNEL_3.GTXE2_IMUX24_1->GTXE2_CHANNEL_TSTIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_1" }, "GTX_CHANNEL_3.GTXE2_IMUX24_10->GTXE2_CHANNEL_TSTIN19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_10" }, "GTX_CHANNEL_3.GTXE2_IMUX24_2->GTXE2_CHANNEL_TSTIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_2" }, "GTX_CHANNEL_3.GTXE2_IMUX24_3->GTXE2_CHANNEL_TSTIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_3" }, "GTX_CHANNEL_3.GTXE2_IMUX24_4->GTXE2_CHANNEL_TSTIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_4" }, "GTX_CHANNEL_3.GTXE2_IMUX24_5->GTXE2_CHANNEL_TSTIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_5" }, "GTX_CHANNEL_3.GTXE2_IMUX24_6->GTXE2_CHANNEL_TSTIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_6" }, "GTX_CHANNEL_3.GTXE2_IMUX24_7->GTXE2_CHANNEL_TSTIN16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_7" }, "GTX_CHANNEL_3.GTXE2_IMUX24_8->GTXE2_CHANNEL_TSTIN17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_8" }, "GTX_CHANNEL_3.GTXE2_IMUX24_9->GTXE2_CHANNEL_TSTIN18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_9" }, "GTX_CHANNEL_3.GTXE2_IMUX25_10->GTXE2_CHANNEL_PCSRSVDIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_10" }, "GTX_CHANNEL_3.GTXE2_IMUX25_2->GTXE2_CHANNEL_TXPHALIGN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHALIGN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_2" }, "GTX_CHANNEL_3.GTXE2_IMUX25_3->GTXE2_CHANNEL_PCSRSVDIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_3" }, "GTX_CHANNEL_3.GTXE2_IMUX25_4->GTXE2_CHANNEL_PCSRSVDIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_4" }, "GTX_CHANNEL_3.GTXE2_IMUX25_5->GTXE2_CHANNEL_PCSRSVDIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_5" }, "GTX_CHANNEL_3.GTXE2_IMUX25_6->GTXE2_CHANNEL_PCSRSVDIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_6" }, "GTX_CHANNEL_3.GTXE2_IMUX25_7->GTXE2_CHANNEL_PCSRSVDIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_7" }, "GTX_CHANNEL_3.GTXE2_IMUX25_8->GTXE2_CHANNEL_PCSRSVDIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_8" }, "GTX_CHANNEL_3.GTXE2_IMUX25_9->GTXE2_CHANNEL_PCSRSVDIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_9" }, "GTX_CHANNEL_3.GTXE2_IMUX26_10->GTXE2_CHANNEL_GTRSVD15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_10" }, "GTX_CHANNEL_3.GTXE2_IMUX26_3->GTXE2_CHANNEL_GTRSVD8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_3" }, "GTX_CHANNEL_3.GTXE2_IMUX26_4->GTXE2_CHANNEL_GTRSVD9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_4" }, "GTX_CHANNEL_3.GTXE2_IMUX26_5->GTXE2_CHANNEL_GTRSVD10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_5" }, "GTX_CHANNEL_3.GTXE2_IMUX26_6->GTXE2_CHANNEL_GTRSVD11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_6" }, "GTX_CHANNEL_3.GTXE2_IMUX26_7->GTXE2_CHANNEL_GTRSVD12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_7" }, "GTX_CHANNEL_3.GTXE2_IMUX26_8->GTXE2_CHANNEL_GTRSVD13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_8" }, "GTX_CHANNEL_3.GTXE2_IMUX26_9->GTXE2_CHANNEL_GTRSVD14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_9" }, "GTX_CHANNEL_3.GTXE2_IMUX27_10->GTXE2_CHANNEL_RXLPMHFOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMHFOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_10" }, "GTX_CHANNEL_3.GTXE2_IMUX27_5->GTXE2_CHANNEL_TXPHINIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHINIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_5" }, "GTX_CHANNEL_3.GTXE2_IMUX27_7->GTXE2_CHANNEL_RXPOLARITY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPOLARITY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_7" }, "GTX_CHANNEL_3.GTXE2_IMUX27_8->GTXE2_CHANNEL_RXDFEVPOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEVPOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_8" }, "GTX_CHANNEL_3.GTXE2_IMUX27_9->GTXE2_CHANNEL_RXDFELFOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELFOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_9" }, "GTX_CHANNEL_3.GTXE2_IMUX28_1->GTXE2_CHANNEL_TXCOMSAS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMSAS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_1" }, "GTX_CHANNEL_3.GTXE2_IMUX28_10->GTXE2_CHANNEL_RXDFETAP2OVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_10" }, "GTX_CHANNEL_3.GTXE2_IMUX28_2->GTXE2_CHANNEL_CPLLLOCKEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLLOCKEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_2" }, "GTX_CHANNEL_3.GTXE2_IMUX28_3->GTXE2_CHANNEL_DRPWE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPWE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_3" }, "GTX_CHANNEL_3.GTXE2_IMUX28_4->GTXE2_CHANNEL_TXSYSCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_4" }, "GTX_CHANNEL_3.GTXE2_IMUX28_5->GTXE2_CHANNEL_TXSYSCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSYSCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_5" }, "GTX_CHANNEL_3.GTXE2_IMUX28_6->GTXE2_CHANNEL_RXDLYEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_6" }, "GTX_CHANNEL_3.GTXE2_IMUX28_8->GTXE2_CHANNEL_RXPD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_8" }, "GTX_CHANNEL_3.GTXE2_IMUX29_0->GTXE2_CHANNEL_TXCHARDISPMODE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_0" }, "GTX_CHANNEL_3.GTXE2_IMUX29_1->GTXE2_CHANNEL_TXCHARISK7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_1" }, "GTX_CHANNEL_3.GTXE2_IMUX29_10->GTXE2_CHANNEL_RXDFEAGCHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEAGCHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_10" }, "GTX_CHANNEL_3.GTXE2_IMUX29_2->GTXE2_CHANNEL_TXCHARDISPMODE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_2" }, "GTX_CHANNEL_3.GTXE2_IMUX29_3->GTXE2_CHANNEL_TXCHARISK6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_3" }, "GTX_CHANNEL_3.GTXE2_IMUX29_4->GTXE2_CHANNEL_TXCHARDISPMODE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_4" }, "GTX_CHANNEL_3.GTXE2_IMUX29_5->GTXE2_CHANNEL_TXCHARISK5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_5" }, "GTX_CHANNEL_3.GTXE2_IMUX29_6->GTXE2_CHANNEL_TXCHARDISPMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_6" }, "GTX_CHANNEL_3.GTXE2_IMUX29_7->GTXE2_CHANNEL_TXCHARISK4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_7" }, "GTX_CHANNEL_3.GTXE2_IMUX29_8->GTXE2_CHANNEL_RXOSHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOSHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_8" }, "GTX_CHANNEL_3.GTXE2_IMUX29_9->GTXE2_CHANNEL_RXDFETAP5HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP5HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_9" }, "GTX_CHANNEL_3.GTXE2_IMUX2_10->GTXE2_CHANNEL_RXOUTCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_10" }, "GTX_CHANNEL_3.GTXE2_IMUX2_3->GTXE2_CHANNEL_DRPADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_3" }, "GTX_CHANNEL_3.GTXE2_IMUX2_4->GTXE2_CHANNEL_TXPOSTCURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_4" }, "GTX_CHANNEL_3.GTXE2_IMUX2_5->GTXE2_CHANNEL_TXDIFFCTRL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_5" }, "GTX_CHANNEL_3.GTXE2_IMUX2_6->GTXE2_CHANNEL_TXPRECURSOR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_6" }, "GTX_CHANNEL_3.GTXE2_IMUX2_8->GTXE2_CHANNEL_RXGEARBOXSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXGEARBOXSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_8" }, "GTX_CHANNEL_3.GTXE2_IMUX2_9->GTXE2_CHANNEL_RXMCOMMAALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX2_9" }, "GTX_CHANNEL_3.GTXE2_IMUX30_10->GTXE2_CHANNEL_RXCHBONDSLAVE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDSLAVE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_10" }, "GTX_CHANNEL_3.GTXE2_IMUX30_3->GTXE2_CHANNEL_TXPOLARITY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOLARITY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_3" }, "GTX_CHANNEL_3.GTXE2_IMUX30_7->GTXE2_CHANNEL_TXPCSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPCSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_7" }, "GTX_CHANNEL_3.GTXE2_IMUX30_8->GTXE2_CHANNEL_RXCDRHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCDRHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_8" }, "GTX_CHANNEL_3.GTXE2_IMUX30_9->GTXE2_CHANNEL_RXCHBONDMASTER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCHBONDMASTER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_9" }, "GTX_CHANNEL_3.GTXE2_IMUX31_0->GTXE2_CHANNEL_TXCHARDISPMODE7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_0" }, "GTX_CHANNEL_3.GTXE2_IMUX31_1->GTXE2_CHANNEL_TXCHARISK3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_1" }, "GTX_CHANNEL_3.GTXE2_IMUX31_2->GTXE2_CHANNEL_TXCHARDISPMODE6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_2" }, "GTX_CHANNEL_3.GTXE2_IMUX31_3->GTXE2_CHANNEL_TXCHARISK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_3" }, "GTX_CHANNEL_3.GTXE2_IMUX31_4->GTXE2_CHANNEL_TXCHARDISPMODE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_4" }, "GTX_CHANNEL_3.GTXE2_IMUX31_5->GTXE2_CHANNEL_TXCHARISK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_5" }, "GTX_CHANNEL_3.GTXE2_IMUX31_6->GTXE2_CHANNEL_TXCHARDISPMODE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPMODE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_6" }, "GTX_CHANNEL_3.GTXE2_IMUX31_7->GTXE2_CHANNEL_TXCHARISK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARISK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_7" }, "GTX_CHANNEL_3.GTXE2_IMUX31_8->GTXE2_CHANNEL_EYESCANTRIGGER": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANTRIGGER", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_8" }, "GTX_CHANNEL_3.GTXE2_IMUX32_0->GTXE2_CHANNEL_DRPDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_0" }, "GTX_CHANNEL_3.GTXE2_IMUX32_1->GTXE2_CHANNEL_DRPDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_1" }, "GTX_CHANNEL_3.GTXE2_IMUX32_2->GTXE2_CHANNEL_TXINHIBIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXINHIBIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_2" }, "GTX_CHANNEL_3.GTXE2_IMUX32_8->GTXE2_CHANNEL_RXDLYBYPASS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYBYPASS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX32_8" }, "GTX_CHANNEL_3.GTXE2_IMUX33_0->GTXE2_CHANNEL_DRPDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_0" }, "GTX_CHANNEL_3.GTXE2_IMUX33_1->GTXE2_CHANNEL_DRPDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_1" }, "GTX_CHANNEL_3.GTXE2_IMUX33_2->GTXE2_CHANNEL_TXPHALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX33_2" }, "GTX_CHANNEL_3.GTXE2_IMUX34_0->GTXE2_CHANNEL_DRPDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_0" }, "GTX_CHANNEL_3.GTXE2_IMUX34_1->GTXE2_CHANNEL_DRPDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_1" }, "GTX_CHANNEL_3.GTXE2_IMUX34_10->GTXE2_CHANNEL_PCSRSVDIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_10" }, "GTX_CHANNEL_3.GTXE2_IMUX34_2->GTXE2_CHANNEL_DRPADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_2" }, "GTX_CHANNEL_3.GTXE2_IMUX34_3->GTXE2_CHANNEL_DRPADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_3" }, "GTX_CHANNEL_3.GTXE2_IMUX34_4->GTXE2_CHANNEL_SETERRSTATUS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_SETERRSTATUS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_4" }, "GTX_CHANNEL_3.GTXE2_IMUX34_8->GTXE2_CHANNEL_RXLPMEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_8" }, "GTX_CHANNEL_3.GTXE2_IMUX34_9->GTXE2_CHANNEL_RXPCOMMAALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX34_9" }, "GTX_CHANNEL_3.GTXE2_IMUX35_0->GTXE2_CHANNEL_DRPDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_0" }, "GTX_CHANNEL_3.GTXE2_IMUX35_1->GTXE2_CHANNEL_DRPDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_1" }, "GTX_CHANNEL_3.GTXE2_IMUX35_10->GTXE2_CHANNEL_PCSRSVDIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_10" }, "GTX_CHANNEL_3.GTXE2_IMUX35_2->GTXE2_CHANNEL_DRPADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_2" }, "GTX_CHANNEL_3.GTXE2_IMUX35_3->GTXE2_CHANNEL_DRPADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_3" }, "GTX_CHANNEL_3.GTXE2_IMUX35_4->GTXE2_CHANNEL_TXMARGIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_4" }, "GTX_CHANNEL_3.GTXE2_IMUX35_5->GTXE2_CHANNEL_TXDEEMPH": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDEEMPH", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_5" }, "GTX_CHANNEL_3.GTXE2_IMUX35_6->GTXE2_CHANNEL_TXPD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_6" }, "GTX_CHANNEL_3.GTXE2_IMUX35_8->GTXE2_CHANNEL_RXDFEUTOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEUTOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_8" }, "GTX_CHANNEL_3.GTXE2_IMUX35_9->GTXE2_CHANNEL_RXDFELFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFELFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX35_9" }, "GTX_CHANNEL_3.GTXE2_IMUX36_0->GTXE2_CHANNEL_DRPDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_0" }, "GTX_CHANNEL_3.GTXE2_IMUX36_1->GTXE2_CHANNEL_DRPDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_1" }, "GTX_CHANNEL_3.GTXE2_IMUX36_10->GTXE2_CHANNEL_RXDFETAP3HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP3HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_10" }, "GTX_CHANNEL_3.GTXE2_IMUX36_2->GTXE2_CHANNEL_CPLLPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_CPLLPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_2" }, "GTX_CHANNEL_3.GTXE2_IMUX36_5->GTXE2_CHANNEL_TXPHDLYRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX36_5" }, "GTX_CHANNEL_3.GTXE2_IMUX37_0->GTXE2_CHANNEL_DRPDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_0" }, "GTX_CHANNEL_3.GTXE2_IMUX37_1->GTXE2_CHANNEL_DRPDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_1" }, "GTX_CHANNEL_3.GTXE2_IMUX37_3->GTXE2_CHANNEL_TXPHDLYPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPHDLYPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_3" }, "GTX_CHANNEL_3.GTXE2_IMUX37_4->GTXE2_CHANNEL_TXDIFFPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_4" }, "GTX_CHANNEL_3.GTXE2_IMUX37_8->GTXE2_CHANNEL_RXDFEXYDHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_8" }, "GTX_CHANNEL_3.GTXE2_IMUX37_9->GTXE2_CHANNEL_RXDFETAP4HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP4HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX37_9" }, "GTX_CHANNEL_3.GTXE2_IMUX38_0->GTXE2_CHANNEL_DRPDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_0" }, "GTX_CHANNEL_3.GTXE2_IMUX38_1->GTXE2_CHANNEL_DRPDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_1" }, "GTX_CHANNEL_3.GTXE2_IMUX38_10->GTXE2_CHANNEL_PCSRSVDIN22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_10" }, "GTX_CHANNEL_3.GTXE2_IMUX38_2->GTXE2_CHANNEL_DRPADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_2" }, "GTX_CHANNEL_3.GTXE2_IMUX38_3->GTXE2_CHANNEL_DRPADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_3" }, "GTX_CHANNEL_3.GTXE2_IMUX38_4->GTXE2_CHANNEL_TXMARGIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_4" }, "GTX_CHANNEL_3.GTXE2_IMUX38_5->GTXE2_CHANNEL_TXSWING": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSWING", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_5" }, "GTX_CHANNEL_3.GTXE2_IMUX38_6->GTXE2_CHANNEL_TXPD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_6" }, "GTX_CHANNEL_3.GTXE2_IMUX38_7->GTXE2_CHANNEL_RXDLYOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDLYOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_7" }, "GTX_CHANNEL_3.GTXE2_IMUX38_8->GTXE2_CHANNEL_RXPRBSSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPRBSSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX38_8" }, "GTX_CHANNEL_3.GTXE2_IMUX39_0->GTXE2_CHANNEL_DRPDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_0" }, "GTX_CHANNEL_3.GTXE2_IMUX39_1->GTXE2_CHANNEL_DRPDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_1" }, "GTX_CHANNEL_3.GTXE2_IMUX39_10->GTXE2_CHANNEL_PCSRSVDIN23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_10" }, "GTX_CHANNEL_3.GTXE2_IMUX39_2->GTXE2_CHANNEL_DRPADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_2" }, "GTX_CHANNEL_3.GTXE2_IMUX39_3->GTXE2_CHANNEL_DRPADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_3" }, "GTX_CHANNEL_3.GTXE2_IMUX39_4->GTXE2_CHANNEL_TXMARGIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMARGIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_4" }, "GTX_CHANNEL_3.GTXE2_IMUX39_5->GTXE2_CHANNEL_TXDETECTRX": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDETECTRX", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_5" }, "GTX_CHANNEL_3.GTXE2_IMUX39_6->GTXE2_CHANNEL_TXELECIDLE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXELECIDLE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_6" }, "GTX_CHANNEL_3.GTXE2_IMUX39_9->GTXE2_CHANNEL_PCSRSVDIN24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX39_9" }, "GTX_CHANNEL_3.GTXE2_IMUX3_10->GTXE2_CHANNEL_RXLPMLFKLOVRDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_10" }, "GTX_CHANNEL_3.GTXE2_IMUX3_3->GTXE2_CHANNEL_TXSTARTSEQ": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSTARTSEQ", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_3" }, "GTX_CHANNEL_3.GTXE2_IMUX3_4->GTXE2_CHANNEL_TXPOSTCURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_4" }, "GTX_CHANNEL_3.GTXE2_IMUX3_5->GTXE2_CHANNEL_TXDIFFCTRL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_5" }, "GTX_CHANNEL_3.GTXE2_IMUX3_6->GTXE2_CHANNEL_TXPRECURSOR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_6" }, "GTX_CHANNEL_3.GTXE2_IMUX3_7->GTXE2_CHANNEL_RXPD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_7" }, "GTX_CHANNEL_3.GTXE2_IMUX3_8->GTXE2_CHANNEL_TXPRBSSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_8" }, "GTX_CHANNEL_3.GTXE2_IMUX3_9->GTXE2_CHANNEL_RXDFEUTHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEUTHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX3_9" }, "GTX_CHANNEL_3.GTXE2_IMUX40_1->GTXE2_CHANNEL_TSTIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_1" }, "GTX_CHANNEL_3.GTXE2_IMUX40_10->GTXE2_CHANNEL_TSTIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_10" }, "GTX_CHANNEL_3.GTXE2_IMUX40_2->GTXE2_CHANNEL_TSTIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_2" }, "GTX_CHANNEL_3.GTXE2_IMUX40_3->GTXE2_CHANNEL_TSTIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_3" }, "GTX_CHANNEL_3.GTXE2_IMUX40_4->GTXE2_CHANNEL_TSTIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_4" }, "GTX_CHANNEL_3.GTXE2_IMUX40_5->GTXE2_CHANNEL_TSTIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_5" }, "GTX_CHANNEL_3.GTXE2_IMUX40_6->GTXE2_CHANNEL_TSTIN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_6" }, "GTX_CHANNEL_3.GTXE2_IMUX40_7->GTXE2_CHANNEL_TSTIN6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_7" }, "GTX_CHANNEL_3.GTXE2_IMUX40_8->GTXE2_CHANNEL_TSTIN7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_8" }, "GTX_CHANNEL_3.GTXE2_IMUX40_9->GTXE2_CHANNEL_TSTIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TSTIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX40_9" }, "GTX_CHANNEL_3.GTXE2_IMUX41_0->GTXE2_CHANNEL_EYESCANMODE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANMODE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_0" }, "GTX_CHANNEL_3.GTXE2_IMUX41_1->GTXE2_CHANNEL_TXPOSTCURSORINV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSORINV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_1" }, "GTX_CHANNEL_3.GTXE2_IMUX41_5->GTXE2_CHANNEL_RESETOVRD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RESETOVRD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_5" }, "GTX_CHANNEL_3.GTXE2_IMUX41_6->GTXE2_CHANNEL_RXPHALIGNEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHALIGNEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX41_6" }, "GTX_CHANNEL_3.GTXE2_IMUX42_10->GTXE2_CHANNEL_GTRSVD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_10" }, "GTX_CHANNEL_3.GTXE2_IMUX42_2->GTXE2_CHANNEL_RXSYSCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_2" }, "GTX_CHANNEL_3.GTXE2_IMUX42_3->GTXE2_CHANNEL_GTRSVD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_3" }, "GTX_CHANNEL_3.GTXE2_IMUX42_4->GTXE2_CHANNEL_GTRSVD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_4" }, "GTX_CHANNEL_3.GTXE2_IMUX42_5->GTXE2_CHANNEL_GTRSVD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_5" }, "GTX_CHANNEL_3.GTXE2_IMUX42_6->GTXE2_CHANNEL_GTRSVD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_6" }, "GTX_CHANNEL_3.GTXE2_IMUX42_7->GTXE2_CHANNEL_GTRSVD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_7" }, "GTX_CHANNEL_3.GTXE2_IMUX42_8->GTXE2_CHANNEL_GTRSVD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_8" }, "GTX_CHANNEL_3.GTXE2_IMUX42_9->GTXE2_CHANNEL_GTRSVD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_GTRSVD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX42_9" }, "GTX_CHANNEL_3.GTXE2_IMUX43_10->GTXE2_CHANNEL_RXLPMHFHOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXLPMHFHOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_10" }, "GTX_CHANNEL_3.GTXE2_IMUX43_5->GTXE2_CHANNEL_TXDLYUPDOWN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYUPDOWN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_5" }, "GTX_CHANNEL_3.GTXE2_IMUX43_6->GTXE2_CHANNEL_TXRATE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_6" }, "GTX_CHANNEL_3.GTXE2_IMUX43_9->GTXE2_CHANNEL_LOOPBACK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX43_9" }, "GTX_CHANNEL_3.GTXE2_IMUX44_1->GTXE2_CHANNEL_TXCOMINIT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCOMINIT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_1" }, "GTX_CHANNEL_3.GTXE2_IMUX44_10->GTXE2_CHANNEL_RXDFETAP2HOLD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFETAP2HOLD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_10" }, "GTX_CHANNEL_3.GTXE2_IMUX44_3->GTXE2_CHANNEL_DRPEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_DRPEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_3" }, "GTX_CHANNEL_3.GTXE2_IMUX44_5->GTXE2_CHANNEL_TXDLYBYPASS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYBYPASS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_5" }, "GTX_CHANNEL_3.GTXE2_IMUX44_8->GTXE2_CHANNEL_RXUSERRDY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXUSERRDY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_8" }, "GTX_CHANNEL_3.GTXE2_IMUX44_9->GTXE2_CHANNEL_RXCOMMADETEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXCOMMADETEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX44_9" }, "GTX_CHANNEL_3.GTXE2_IMUX45_1->GTXE2_CHANNEL_TXQPIWEAKPUP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPIWEAKPUP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_1" }, "GTX_CHANNEL_3.GTXE2_IMUX45_10->GTXE2_CHANNEL_RXMONITORSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXMONITORSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_10" }, "GTX_CHANNEL_3.GTXE2_IMUX45_2->GTXE2_CHANNEL_RXSYSCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXSYSCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_2" }, "GTX_CHANNEL_3.GTXE2_IMUX45_3->GTXE2_CHANNEL_TXDLYSRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDLYSRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_3" }, "GTX_CHANNEL_3.GTXE2_IMUX45_8->GTXE2_CHANNEL_EYESCANRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_EYESCANRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_8" }, "GTX_CHANNEL_3.GTXE2_IMUX45_9->GTXE2_CHANNEL_RXDFEXYDEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDFEXYDEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX45_9" }, "GTX_CHANNEL_3.GTXE2_IMUX46_6->GTXE2_CHANNEL_TXRATE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX46_6" }, "GTX_CHANNEL_3.GTXE2_IMUX46_9->GTXE2_CHANNEL_LOOPBACK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX46_9" }, "GTX_CHANNEL_3.GTXE2_IMUX47_6->GTXE2_CHANNEL_TXRATE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXRATE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX47_6" }, "GTX_CHANNEL_3.GTXE2_IMUX47_9->GTXE2_CHANNEL_LOOPBACK2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_LOOPBACK2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX47_9" }, "GTX_CHANNEL_3.GTXE2_IMUX4_1->GTXE2_CHANNEL_TXPRECURSORINV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSORINV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_1" }, "GTX_CHANNEL_3.GTXE2_IMUX4_10->GTXE2_CHANNEL_RXOUTCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_10" }, "GTX_CHANNEL_3.GTXE2_IMUX4_3->GTXE2_CHANNEL_TXMAINCURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_3" }, "GTX_CHANNEL_3.GTXE2_IMUX4_4->GTXE2_CHANNEL_TXMAINCURSOR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_4" }, "GTX_CHANNEL_3.GTXE2_IMUX4_5->GTXE2_CHANNEL_TXSEQUENCE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_5" }, "GTX_CHANNEL_3.GTXE2_IMUX4_6->GTXE2_CHANNEL_TXSEQUENCE5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_6" }, "GTX_CHANNEL_3.GTXE2_IMUX4_7->GTXE2_CHANNEL_PMARSVDIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_7" }, "GTX_CHANNEL_3.GTXE2_IMUX4_8->GTXE2_CHANNEL_TXOUTCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_8" }, "GTX_CHANNEL_3.GTXE2_IMUX4_9->GTXE2_CHANNEL_PMARSVDIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX4_9" }, "GTX_CHANNEL_3.GTXE2_IMUX5_1->GTXE2_CHANNEL_TXQPIBIASEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXQPIBIASEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_1" }, "GTX_CHANNEL_3.GTXE2_IMUX5_10->GTXE2_CHANNEL_RXOUTCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXOUTCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_10" }, "GTX_CHANNEL_3.GTXE2_IMUX5_3->GTXE2_CHANNEL_TXMAINCURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_3" }, "GTX_CHANNEL_3.GTXE2_IMUX5_4->GTXE2_CHANNEL_TXMAINCURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXMAINCURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_4" }, "GTX_CHANNEL_3.GTXE2_IMUX5_5->GTXE2_CHANNEL_TXSEQUENCE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_5" }, "GTX_CHANNEL_3.GTXE2_IMUX5_6->GTXE2_CHANNEL_TXSEQUENCE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXSEQUENCE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_6" }, "GTX_CHANNEL_3.GTXE2_IMUX5_7->GTXE2_CHANNEL_PMARSVDIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_7" }, "GTX_CHANNEL_3.GTXE2_IMUX5_8->GTXE2_CHANNEL_TXOUTCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXOUTCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_8" }, "GTX_CHANNEL_3.GTXE2_IMUX5_9->GTXE2_CHANNEL_PMARSVDIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PMARSVDIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX5_9" }, "GTX_CHANNEL_3.GTXE2_IMUX6_4->GTXE2_CHANNEL_TXPOSTCURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_4" }, "GTX_CHANNEL_3.GTXE2_IMUX6_5->GTXE2_CHANNEL_TXDIFFCTRL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_5" }, "GTX_CHANNEL_3.GTXE2_IMUX6_6->GTXE2_CHANNEL_TXPRECURSOR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_6" }, "GTX_CHANNEL_3.GTXE2_IMUX6_8->GTXE2_CHANNEL_TXPRBSSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX6_8" }, "GTX_CHANNEL_3.GTXE2_IMUX7_0->GTXE2_CHANNEL_TXPISOPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPISOPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_0" }, "GTX_CHANNEL_3.GTXE2_IMUX7_3->GTXE2_CHANNEL_TXPOSTCURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_3" }, "GTX_CHANNEL_3.GTXE2_IMUX7_4->GTXE2_CHANNEL_TXPOSTCURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPOSTCURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_4" }, "GTX_CHANNEL_3.GTXE2_IMUX7_5->GTXE2_CHANNEL_TXDIFFCTRL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXDIFFCTRL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_5" }, "GTX_CHANNEL_3.GTXE2_IMUX7_6->GTXE2_CHANNEL_TXPRECURSOR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_6" }, "GTX_CHANNEL_3.GTXE2_IMUX7_7->GTXE2_CHANNEL_TXPRECURSOR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRECURSOR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_7" }, "GTX_CHANNEL_3.GTXE2_IMUX7_8->GTXE2_CHANNEL_TXPRBSSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXPRBSSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX7_8" }, "GTX_CHANNEL_3.GTXE2_IMUX8_0->GTXE2_CHANNEL_TXCHARDISPVAL3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_0" }, "GTX_CHANNEL_3.GTXE2_IMUX8_1->GTXE2_CHANNEL_TX8B10BBYPASS7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_1" }, "GTX_CHANNEL_3.GTXE2_IMUX8_2->GTXE2_CHANNEL_TXCHARDISPVAL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_2" }, "GTX_CHANNEL_3.GTXE2_IMUX8_3->GTXE2_CHANNEL_TX8B10BBYPASS6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_3" }, "GTX_CHANNEL_3.GTXE2_IMUX8_4->GTXE2_CHANNEL_TXCHARDISPVAL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_4" }, "GTX_CHANNEL_3.GTXE2_IMUX8_5->GTXE2_CHANNEL_TX8B10BBYPASS5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_5" }, "GTX_CHANNEL_3.GTXE2_IMUX8_6->GTXE2_CHANNEL_TXCHARDISPVAL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXCHARDISPVAL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_6" }, "GTX_CHANNEL_3.GTXE2_IMUX8_7->GTXE2_CHANNEL_TX8B10BBYPASS4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TX8B10BBYPASS4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_7" }, "GTX_CHANNEL_3.GTXE2_IMUX8_8->GTXE2_CHANNEL_RXDDIEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXDDIEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX8_8" }, "GTX_CHANNEL_3.GTXE2_IMUX9_1->GTXE2_CHANNEL_RXPHDLYPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_RXPHDLYPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_1" }, "GTX_CHANNEL_3.GTXE2_IMUX9_10->GTXE2_CHANNEL_PCSRSVDIN15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_10" }, "GTX_CHANNEL_3.GTXE2_IMUX9_2->GTXE2_CHANNEL_TXHEADER2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_TXHEADER2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_2" }, "GTX_CHANNEL_3.GTXE2_IMUX9_3->GTXE2_CHANNEL_PCSRSVDIN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_3" }, "GTX_CHANNEL_3.GTXE2_IMUX9_4->GTXE2_CHANNEL_PCSRSVDIN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_4" }, "GTX_CHANNEL_3.GTXE2_IMUX9_5->GTXE2_CHANNEL_PCSRSVDIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_5" }, "GTX_CHANNEL_3.GTXE2_IMUX9_6->GTXE2_CHANNEL_PCSRSVDIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_6" }, "GTX_CHANNEL_3.GTXE2_IMUX9_7->GTXE2_CHANNEL_PCSRSVDIN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_7" }, "GTX_CHANNEL_3.GTXE2_IMUX9_8->GTXE2_CHANNEL_PCSRSVDIN13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_8" }, "GTX_CHANNEL_3.GTXE2_IMUX9_9->GTXE2_CHANNEL_PCSRSVDIN14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_CHANNEL_PCSRSVDIN14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX9_9" } }, @@ -4402,690 +11310,6846 @@ "name": "X0Y0", "prefix": "GTXE2_CHANNEL", "site_pins": { - "CFGRESET": "GTXE2_CHANNEL_CFGRESET", - "CLKRSVD0": "GTXE2_CHANNEL_CLKRSVD0", - "CLKRSVD1": "GTXE2_CHANNEL_CLKRSVD1", - "CLKRSVD2": "GTXE2_CHANNEL_CLKRSVD2", - "CLKRSVD3": "GTXE2_CHANNEL_CLKRSVD3", - "CPLLFBCLKLOST": "GTXE2_CHANNEL_CPLLFBCLKLOST", - "CPLLLOCK": "GTXE2_CHANNEL_CPLLLOCK", - "CPLLLOCKDETCLK": "GTXE2_CHANNEL_CPLLLOCKDETCLK", - "CPLLLOCKEN": "GTXE2_CHANNEL_CPLLLOCKEN", - "CPLLPD": "GTXE2_CHANNEL_CPLLPD", - "CPLLREFCLKLOST": "GTXE2_CHANNEL_CPLLREFCLKLOST", - "CPLLREFCLKSEL0": "GTXE2_CHANNEL_CPLLREFCLKSEL0", - "CPLLREFCLKSEL1": "GTXE2_CHANNEL_CPLLREFCLKSEL1", - "CPLLREFCLKSEL2": "GTXE2_CHANNEL_CPLLREFCLKSEL2", - "CPLLRESET": "GTXE2_CHANNEL_CPLLRESET", - "DMONITOROUT0": "GTXE2_CHANNEL_DMONITOROUT0", - "DMONITOROUT1": "GTXE2_CHANNEL_DMONITOROUT1", - "DMONITOROUT2": "GTXE2_CHANNEL_DMONITOROUT2", - "DMONITOROUT3": "GTXE2_CHANNEL_DMONITOROUT3", - "DMONITOROUT4": "GTXE2_CHANNEL_DMONITOROUT4", - "DMONITOROUT5": "GTXE2_CHANNEL_DMONITOROUT5", - "DMONITOROUT6": "GTXE2_CHANNEL_DMONITOROUT6", - "DMONITOROUT7": "GTXE2_CHANNEL_DMONITOROUT7", - "DRPADDR0": "GTXE2_CHANNEL_DRPADDR0", - "DRPADDR1": "GTXE2_CHANNEL_DRPADDR1", - "DRPADDR2": "GTXE2_CHANNEL_DRPADDR2", - "DRPADDR3": "GTXE2_CHANNEL_DRPADDR3", - "DRPADDR4": "GTXE2_CHANNEL_DRPADDR4", - "DRPADDR5": "GTXE2_CHANNEL_DRPADDR5", - "DRPADDR6": "GTXE2_CHANNEL_DRPADDR6", - "DRPADDR7": "GTXE2_CHANNEL_DRPADDR7", - "DRPADDR8": "GTXE2_CHANNEL_DRPADDR8", - "DRPCLK": "GTXE2_CHANNEL_DRPCLK", - "DRPDI0": "GTXE2_CHANNEL_DRPDI0", - "DRPDI1": "GTXE2_CHANNEL_DRPDI1", - "DRPDI10": "GTXE2_CHANNEL_DRPDI10", - "DRPDI11": "GTXE2_CHANNEL_DRPDI11", - "DRPDI12": "GTXE2_CHANNEL_DRPDI12", - "DRPDI13": "GTXE2_CHANNEL_DRPDI13", - "DRPDI14": "GTXE2_CHANNEL_DRPDI14", - "DRPDI15": "GTXE2_CHANNEL_DRPDI15", - "DRPDI2": "GTXE2_CHANNEL_DRPDI2", - "DRPDI3": "GTXE2_CHANNEL_DRPDI3", - "DRPDI4": "GTXE2_CHANNEL_DRPDI4", - "DRPDI5": "GTXE2_CHANNEL_DRPDI5", - "DRPDI6": "GTXE2_CHANNEL_DRPDI6", - "DRPDI7": "GTXE2_CHANNEL_DRPDI7", - "DRPDI8": "GTXE2_CHANNEL_DRPDI8", - "DRPDI9": "GTXE2_CHANNEL_DRPDI9", - "DRPDO0": "GTXE2_CHANNEL_DRPDO0", - "DRPDO1": "GTXE2_CHANNEL_DRPDO1", - "DRPDO10": "GTXE2_CHANNEL_DRPDO10", - "DRPDO11": "GTXE2_CHANNEL_DRPDO11", - "DRPDO12": "GTXE2_CHANNEL_DRPDO12", - "DRPDO13": "GTXE2_CHANNEL_DRPDO13", - "DRPDO14": "GTXE2_CHANNEL_DRPDO14", - "DRPDO15": "GTXE2_CHANNEL_DRPDO15", - "DRPDO2": "GTXE2_CHANNEL_DRPDO2", - "DRPDO3": "GTXE2_CHANNEL_DRPDO3", - "DRPDO4": "GTXE2_CHANNEL_DRPDO4", - "DRPDO5": "GTXE2_CHANNEL_DRPDO5", - "DRPDO6": "GTXE2_CHANNEL_DRPDO6", - "DRPDO7": "GTXE2_CHANNEL_DRPDO7", - "DRPDO8": "GTXE2_CHANNEL_DRPDO8", - "DRPDO9": "GTXE2_CHANNEL_DRPDO9", - "DRPEN": "GTXE2_CHANNEL_DRPEN", - "DRPRDY": "GTXE2_CHANNEL_DRPRDY", - "DRPWE": "GTXE2_CHANNEL_DRPWE", - "EDTBYPASS": "GTXE2_CHANNEL_EDTBYPASS", - "EDTCLOCK": "GTXE2_CHANNEL_EDTCLOCK", - "EDTCONFIGURATION": "GTXE2_CHANNEL_EDTCONFIGURATION", - "EDTSINGLEBYPASSCHAIN": "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", - "EDTUPDATE": "GTXE2_CHANNEL_EDTUPDATE", - "EYESCANDATAERROR": "GTXE2_CHANNEL_EYESCANDATAERROR", - "EYESCANMODE": "GTXE2_CHANNEL_EYESCANMODE", - "EYESCANRESET": "GTXE2_CHANNEL_EYESCANRESET", - "EYESCANTRIGGER": "GTXE2_CHANNEL_EYESCANTRIGGER", - "GTGREFCLK": "GTXE2_CHANNEL_GTGREFCLK", - "GTNORTHREFCLK0": "GTXE2_CHANNEL_GTNORTHREFCLK0", - "GTNORTHREFCLK1": "GTXE2_CHANNEL_GTNORTHREFCLK1", - "GTREFCLK0": "GTXE2_CHANNEL_GTREFCLK0", - "GTREFCLK1": "GTXE2_CHANNEL_GTREFCLK1", - "GTREFCLKMONITOR": "GTXE2_CHANNEL_GTREFCLKMONITOR", - "GTRESETSEL": "GTXE2_CHANNEL_GTRESETSEL", - "GTRSVD0": "GTXE2_CHANNEL_GTRSVD0", - "GTRSVD1": "GTXE2_CHANNEL_GTRSVD1", - "GTRSVD10": "GTXE2_CHANNEL_GTRSVD10", - "GTRSVD11": "GTXE2_CHANNEL_GTRSVD11", - "GTRSVD12": "GTXE2_CHANNEL_GTRSVD12", - "GTRSVD13": "GTXE2_CHANNEL_GTRSVD13", - "GTRSVD14": "GTXE2_CHANNEL_GTRSVD14", - "GTRSVD15": "GTXE2_CHANNEL_GTRSVD15", - "GTRSVD2": "GTXE2_CHANNEL_GTRSVD2", - "GTRSVD3": "GTXE2_CHANNEL_GTRSVD3", - "GTRSVD4": "GTXE2_CHANNEL_GTRSVD4", - "GTRSVD5": "GTXE2_CHANNEL_GTRSVD5", - "GTRSVD6": "GTXE2_CHANNEL_GTRSVD6", - "GTRSVD7": "GTXE2_CHANNEL_GTRSVD7", - "GTRSVD8": "GTXE2_CHANNEL_GTRSVD8", - "GTRSVD9": "GTXE2_CHANNEL_GTRSVD9", - "GTRXRESET": "GTXE2_CHANNEL_GTRXRESET", - "GTSOUTHREFCLK0": "GTXE2_CHANNEL_GTSOUTHREFCLK0", - "GTSOUTHREFCLK1": "GTXE2_CHANNEL_GTSOUTHREFCLK1", - "GTTXRESET": "GTXE2_CHANNEL_GTTXRESET", - "GTXRXN": "GTXE2_CHANNEL_RXN", - "GTXRXP": "GTXE2_CHANNEL_RXP", - "GTXTXN": "GTXE2_CHANNEL_TXN", - "GTXTXP": "GTXE2_CHANNEL_TXP", - "LOOPBACK0": "GTXE2_CHANNEL_LOOPBACK0", - "LOOPBACK1": "GTXE2_CHANNEL_LOOPBACK1", - "LOOPBACK2": "GTXE2_CHANNEL_LOOPBACK2", - "PCSRSVDIN0": "GTXE2_CHANNEL_PCSRSVDIN0", - "PCSRSVDIN1": "GTXE2_CHANNEL_PCSRSVDIN1", - "PCSRSVDIN10": "GTXE2_CHANNEL_PCSRSVDIN10", - "PCSRSVDIN11": "GTXE2_CHANNEL_PCSRSVDIN11", - "PCSRSVDIN12": "GTXE2_CHANNEL_PCSRSVDIN12", - "PCSRSVDIN13": "GTXE2_CHANNEL_PCSRSVDIN13", - "PCSRSVDIN14": "GTXE2_CHANNEL_PCSRSVDIN14", - "PCSRSVDIN15": "GTXE2_CHANNEL_PCSRSVDIN15", - "PCSRSVDIN2": "GTXE2_CHANNEL_PCSRSVDIN2", - "PCSRSVDIN20": "GTXE2_CHANNEL_PCSRSVDIN20", - "PCSRSVDIN21": "GTXE2_CHANNEL_PCSRSVDIN21", - "PCSRSVDIN22": "GTXE2_CHANNEL_PCSRSVDIN22", - "PCSRSVDIN23": "GTXE2_CHANNEL_PCSRSVDIN23", - "PCSRSVDIN24": "GTXE2_CHANNEL_PCSRSVDIN24", - "PCSRSVDIN3": "GTXE2_CHANNEL_PCSRSVDIN3", - "PCSRSVDIN4": "GTXE2_CHANNEL_PCSRSVDIN4", - "PCSRSVDIN5": "GTXE2_CHANNEL_PCSRSVDIN5", - "PCSRSVDIN6": "GTXE2_CHANNEL_PCSRSVDIN6", - "PCSRSVDIN7": "GTXE2_CHANNEL_PCSRSVDIN7", - "PCSRSVDIN8": "GTXE2_CHANNEL_PCSRSVDIN8", - "PCSRSVDIN9": "GTXE2_CHANNEL_PCSRSVDIN9", - "PCSRSVDOUT0": "GTXE2_CHANNEL_PCSRSVDOUT0", - "PCSRSVDOUT1": "GTXE2_CHANNEL_PCSRSVDOUT1", - "PCSRSVDOUT10": "GTXE2_CHANNEL_PCSRSVDOUT10", - "PCSRSVDOUT11": "GTXE2_CHANNEL_PCSRSVDOUT11", - "PCSRSVDOUT12": "GTXE2_CHANNEL_PCSRSVDOUT12", - "PCSRSVDOUT13": "GTXE2_CHANNEL_PCSRSVDOUT13", - "PCSRSVDOUT14": "GTXE2_CHANNEL_PCSRSVDOUT14", - "PCSRSVDOUT15": "GTXE2_CHANNEL_PCSRSVDOUT15", - "PCSRSVDOUT2": "GTXE2_CHANNEL_PCSRSVDOUT2", - "PCSRSVDOUT3": "GTXE2_CHANNEL_PCSRSVDOUT3", - "PCSRSVDOUT4": "GTXE2_CHANNEL_PCSRSVDOUT4", - "PCSRSVDOUT5": "GTXE2_CHANNEL_PCSRSVDOUT5", - "PCSRSVDOUT6": "GTXE2_CHANNEL_PCSRSVDOUT6", - "PCSRSVDOUT7": "GTXE2_CHANNEL_PCSRSVDOUT7", - "PCSRSVDOUT8": "GTXE2_CHANNEL_PCSRSVDOUT8", - "PCSRSVDOUT9": "GTXE2_CHANNEL_PCSRSVDOUT9", - "PHYSTATUS": "GTXE2_CHANNEL_PHYSTATUS", - "PMARSVDIN0": "GTXE2_CHANNEL_PMARSVDIN0", - "PMARSVDIN1": "GTXE2_CHANNEL_PMARSVDIN1", - "PMARSVDIN2": "GTXE2_CHANNEL_PMARSVDIN2", - "PMARSVDIN20": "GTXE2_CHANNEL_PMARSVDIN20", - "PMARSVDIN21": "GTXE2_CHANNEL_PMARSVDIN21", - "PMARSVDIN22": "GTXE2_CHANNEL_PMARSVDIN22", - "PMARSVDIN23": "GTXE2_CHANNEL_PMARSVDIN23", - "PMARSVDIN24": "GTXE2_CHANNEL_PMARSVDIN24", - "PMARSVDIN3": "GTXE2_CHANNEL_PMARSVDIN3", - "PMARSVDIN4": "GTXE2_CHANNEL_PMARSVDIN4", - "PMASCANCLK0": "GTXE2_CHANNEL_PMASCANCLK0", - "PMASCANCLK1": "GTXE2_CHANNEL_PMASCANCLK1", - "PMASCANCLK2": "GTXE2_CHANNEL_PMASCANCLK2", - "PMASCANCLK3": "GTXE2_CHANNEL_PMASCANCLK3", - "PMASCANCLK4": "GTXE2_CHANNEL_PMASCANCLK4", - "PMASCANENB": "GTXE2_CHANNEL_PMASCANENB", - "PMASCANIN0": "GTXE2_CHANNEL_PMASCANIN0", - "PMASCANIN1": "GTXE2_CHANNEL_PMASCANIN1", - "PMASCANIN2": "GTXE2_CHANNEL_PMASCANIN2", - "PMASCANIN3": "GTXE2_CHANNEL_PMASCANIN3", - "PMASCANIN4": "GTXE2_CHANNEL_PMASCANIN4", - "PMASCANMODEB": "GTXE2_CHANNEL_PMASCANMODEB", - "PMASCANOUT0": "GTXE2_CHANNEL_PMASCANOUT0", - "PMASCANOUT1": "GTXE2_CHANNEL_PMASCANOUT1", - "PMASCANOUT2": "GTXE2_CHANNEL_PMASCANOUT2", - "PMASCANOUT3": "GTXE2_CHANNEL_PMASCANOUT3", - "PMASCANOUT4": "GTXE2_CHANNEL_PMASCANOUT4", - "PMASCANRSTEN": "GTXE2_CHANNEL_PMASCANRSTEN", - "QPLLCLK": "GTXE2_CHANNEL_GTQPLLCLK", - "QPLLREFCLK": "GTXE2_CHANNEL_GTQPLLREFCLK", - "RESETOVRD": "GTXE2_CHANNEL_RESETOVRD", - "RX8B10BEN": "GTXE2_CHANNEL_RX8B10BEN", - "RXBUFRESET": "GTXE2_CHANNEL_RXBUFRESET", - "RXBUFSTATUS0": "GTXE2_CHANNEL_RXBUFSTATUS0", - "RXBUFSTATUS1": "GTXE2_CHANNEL_RXBUFSTATUS1", - "RXBUFSTATUS2": "GTXE2_CHANNEL_RXBUFSTATUS2", - "RXBYTEISALIGNED": "GTXE2_CHANNEL_RXBYTEISALIGNED", - "RXBYTEREALIGN": "GTXE2_CHANNEL_RXBYTEREALIGN", - "RXCDRFREQRESET": "GTXE2_CHANNEL_RXCDRFREQRESET", - "RXCDRHOLD": "GTXE2_CHANNEL_RXCDRHOLD", - "RXCDRLOCK": "GTXE2_CHANNEL_RXCDRLOCK", - "RXCDROVRDEN": "GTXE2_CHANNEL_RXCDROVRDEN", - "RXCDRRESET": "GTXE2_CHANNEL_RXCDRRESET", - "RXCDRRESETRSV": "GTXE2_CHANNEL_RXCDRRESETRSV", - "RXCHANBONDSEQ": "GTXE2_CHANNEL_RXCHANBONDSEQ", - "RXCHANISALIGNED": "GTXE2_CHANNEL_RXCHANISALIGNED", - "RXCHANREALIGN": "GTXE2_CHANNEL_RXCHANREALIGN", - "RXCHARISCOMMA0": "GTXE2_CHANNEL_RXCHARISCOMMA0", - "RXCHARISCOMMA1": "GTXE2_CHANNEL_RXCHARISCOMMA1", - "RXCHARISCOMMA2": "GTXE2_CHANNEL_RXCHARISCOMMA2", - "RXCHARISCOMMA3": "GTXE2_CHANNEL_RXCHARISCOMMA3", - "RXCHARISCOMMA4": "GTXE2_CHANNEL_RXCHARISCOMMA4", - "RXCHARISCOMMA5": "GTXE2_CHANNEL_RXCHARISCOMMA5", - "RXCHARISCOMMA6": "GTXE2_CHANNEL_RXCHARISCOMMA6", - "RXCHARISCOMMA7": "GTXE2_CHANNEL_RXCHARISCOMMA7", - "RXCHARISK0": "GTXE2_CHANNEL_RXCHARISK0", - "RXCHARISK1": "GTXE2_CHANNEL_RXCHARISK1", - "RXCHARISK2": "GTXE2_CHANNEL_RXCHARISK2", - "RXCHARISK3": "GTXE2_CHANNEL_RXCHARISK3", - "RXCHARISK4": "GTXE2_CHANNEL_RXCHARISK4", - "RXCHARISK5": "GTXE2_CHANNEL_RXCHARISK5", - "RXCHARISK6": "GTXE2_CHANNEL_RXCHARISK6", - "RXCHARISK7": "GTXE2_CHANNEL_RXCHARISK7", - "RXCHBONDEN": "GTXE2_CHANNEL_RXCHBONDEN", - "RXCHBONDI0": "GTXE2_CHANNEL_RXCHBONDI0", - "RXCHBONDI1": "GTXE2_CHANNEL_RXCHBONDI1", - "RXCHBONDI2": "GTXE2_CHANNEL_RXCHBONDI2", - "RXCHBONDI3": "GTXE2_CHANNEL_RXCHBONDI3", - "RXCHBONDI4": "GTXE2_CHANNEL_RXCHBONDI4", - "RXCHBONDLEVEL0": "GTXE2_CHANNEL_RXCHBONDLEVEL0", - "RXCHBONDLEVEL1": "GTXE2_CHANNEL_RXCHBONDLEVEL1", - "RXCHBONDLEVEL2": "GTXE2_CHANNEL_RXCHBONDLEVEL2", - "RXCHBONDMASTER": "GTXE2_CHANNEL_RXCHBONDMASTER", - "RXCHBONDO0": "GTXE2_CHANNEL_RXCHBONDO0", - "RXCHBONDO1": "GTXE2_CHANNEL_RXCHBONDO1", - "RXCHBONDO2": "GTXE2_CHANNEL_RXCHBONDO2", - "RXCHBONDO3": "GTXE2_CHANNEL_RXCHBONDO3", - "RXCHBONDO4": "GTXE2_CHANNEL_RXCHBONDO4", - "RXCHBONDSLAVE": "GTXE2_CHANNEL_RXCHBONDSLAVE", - "RXCLKCORCNT0": "GTXE2_CHANNEL_RXCLKCORCNT0", - "RXCLKCORCNT1": "GTXE2_CHANNEL_RXCLKCORCNT1", - "RXCOMINITDET": "GTXE2_CHANNEL_RXCOMINITDET", - "RXCOMMADET": "GTXE2_CHANNEL_RXCOMMADET", - "RXCOMMADETEN": "GTXE2_CHANNEL_RXCOMMADETEN", - "RXCOMSASDET": "GTXE2_CHANNEL_RXCOMSASDET", - "RXCOMWAKEDET": "GTXE2_CHANNEL_RXCOMWAKEDET", - "RXDATA0": "GTXE2_CHANNEL_RXDATA0", - "RXDATA1": "GTXE2_CHANNEL_RXDATA1", - "RXDATA10": "GTXE2_CHANNEL_RXDATA10", - "RXDATA11": "GTXE2_CHANNEL_RXDATA11", - "RXDATA12": "GTXE2_CHANNEL_RXDATA12", - "RXDATA13": "GTXE2_CHANNEL_RXDATA13", - "RXDATA14": "GTXE2_CHANNEL_RXDATA14", - "RXDATA15": "GTXE2_CHANNEL_RXDATA15", - "RXDATA16": "GTXE2_CHANNEL_RXDATA16", - "RXDATA17": "GTXE2_CHANNEL_RXDATA17", - "RXDATA18": "GTXE2_CHANNEL_RXDATA18", - "RXDATA19": "GTXE2_CHANNEL_RXDATA19", - "RXDATA2": "GTXE2_CHANNEL_RXDATA2", - "RXDATA20": "GTXE2_CHANNEL_RXDATA20", - "RXDATA21": "GTXE2_CHANNEL_RXDATA21", - "RXDATA22": "GTXE2_CHANNEL_RXDATA22", - "RXDATA23": "GTXE2_CHANNEL_RXDATA23", - "RXDATA24": "GTXE2_CHANNEL_RXDATA24", - "RXDATA25": "GTXE2_CHANNEL_RXDATA25", - "RXDATA26": "GTXE2_CHANNEL_RXDATA26", - "RXDATA27": "GTXE2_CHANNEL_RXDATA27", - "RXDATA28": "GTXE2_CHANNEL_RXDATA28", - "RXDATA29": "GTXE2_CHANNEL_RXDATA29", - "RXDATA3": "GTXE2_CHANNEL_RXDATA3", - "RXDATA30": "GTXE2_CHANNEL_RXDATA30", - "RXDATA31": "GTXE2_CHANNEL_RXDATA31", - "RXDATA32": "GTXE2_CHANNEL_RXDATA32", - "RXDATA33": "GTXE2_CHANNEL_RXDATA33", - "RXDATA34": "GTXE2_CHANNEL_RXDATA34", - "RXDATA35": "GTXE2_CHANNEL_RXDATA35", - "RXDATA36": "GTXE2_CHANNEL_RXDATA36", - "RXDATA37": "GTXE2_CHANNEL_RXDATA37", - "RXDATA38": "GTXE2_CHANNEL_RXDATA38", - "RXDATA39": "GTXE2_CHANNEL_RXDATA39", - "RXDATA4": "GTXE2_CHANNEL_RXDATA4", - "RXDATA40": "GTXE2_CHANNEL_RXDATA40", - "RXDATA41": "GTXE2_CHANNEL_RXDATA41", - "RXDATA42": "GTXE2_CHANNEL_RXDATA42", - "RXDATA43": "GTXE2_CHANNEL_RXDATA43", - "RXDATA44": "GTXE2_CHANNEL_RXDATA44", - "RXDATA45": "GTXE2_CHANNEL_RXDATA45", - "RXDATA46": "GTXE2_CHANNEL_RXDATA46", - "RXDATA47": "GTXE2_CHANNEL_RXDATA47", - "RXDATA48": "GTXE2_CHANNEL_RXDATA48", - "RXDATA49": "GTXE2_CHANNEL_RXDATA49", - "RXDATA5": "GTXE2_CHANNEL_RXDATA5", - "RXDATA50": "GTXE2_CHANNEL_RXDATA50", - "RXDATA51": "GTXE2_CHANNEL_RXDATA51", - "RXDATA52": "GTXE2_CHANNEL_RXDATA52", - "RXDATA53": "GTXE2_CHANNEL_RXDATA53", - "RXDATA54": "GTXE2_CHANNEL_RXDATA54", - "RXDATA55": "GTXE2_CHANNEL_RXDATA55", - "RXDATA56": "GTXE2_CHANNEL_RXDATA56", - "RXDATA57": "GTXE2_CHANNEL_RXDATA57", - "RXDATA58": "GTXE2_CHANNEL_RXDATA58", - "RXDATA59": "GTXE2_CHANNEL_RXDATA59", - "RXDATA6": "GTXE2_CHANNEL_RXDATA6", - "RXDATA60": "GTXE2_CHANNEL_RXDATA60", - "RXDATA61": "GTXE2_CHANNEL_RXDATA61", - "RXDATA62": "GTXE2_CHANNEL_RXDATA62", - "RXDATA63": "GTXE2_CHANNEL_RXDATA63", - "RXDATA7": "GTXE2_CHANNEL_RXDATA7", - "RXDATA8": "GTXE2_CHANNEL_RXDATA8", - "RXDATA9": "GTXE2_CHANNEL_RXDATA9", - "RXDATAVALID": "GTXE2_CHANNEL_RXDATAVALID", - "RXDDIEN": "GTXE2_CHANNEL_RXDDIEN", - "RXDEBUGPULSE": "GTXE2_CHANNEL_RXDEBUGPULSE", - "RXDFEAGCHOLD": "GTXE2_CHANNEL_RXDFEAGCHOLD", - "RXDFEAGCOVRDEN": "GTXE2_CHANNEL_RXDFEAGCOVRDEN", - "RXDFECM1EN": "GTXE2_CHANNEL_RXDFECM1EN", - "RXDFELFHOLD": "GTXE2_CHANNEL_RXDFELFHOLD", - "RXDFELFOVRDEN": "GTXE2_CHANNEL_RXDFELFOVRDEN", - "RXDFELPMRESET": "GTXE2_CHANNEL_RXDFELPMRESET", - "RXDFETAP2HOLD": "GTXE2_CHANNEL_RXDFETAP2HOLD", - "RXDFETAP2OVRDEN": "GTXE2_CHANNEL_RXDFETAP2OVRDEN", - "RXDFETAP3HOLD": "GTXE2_CHANNEL_RXDFETAP3HOLD", - "RXDFETAP3OVRDEN": "GTXE2_CHANNEL_RXDFETAP3OVRDEN", - "RXDFETAP4HOLD": "GTXE2_CHANNEL_RXDFETAP4HOLD", - "RXDFETAP4OVRDEN": "GTXE2_CHANNEL_RXDFETAP4OVRDEN", - "RXDFETAP5HOLD": "GTXE2_CHANNEL_RXDFETAP5HOLD", - "RXDFETAP5OVRDEN": "GTXE2_CHANNEL_RXDFETAP5OVRDEN", - "RXDFEUTHOLD": "GTXE2_CHANNEL_RXDFEUTHOLD", - "RXDFEUTOVRDEN": "GTXE2_CHANNEL_RXDFEUTOVRDEN", - "RXDFEVPHOLD": "GTXE2_CHANNEL_RXDFEVPHOLD", - "RXDFEVPOVRDEN": "GTXE2_CHANNEL_RXDFEVPOVRDEN", - "RXDFEVSEN": "GTXE2_CHANNEL_RXDFEVSEN", - "RXDFEXYDEN": "GTXE2_CHANNEL_RXDFEXYDEN", - "RXDFEXYDHOLD": "GTXE2_CHANNEL_RXDFEXYDHOLD", - "RXDFEXYDOVRDEN": "GTXE2_CHANNEL_RXDFEXYDOVRDEN", - "RXDISPERR0": "GTXE2_CHANNEL_RXDISPERR0", - "RXDISPERR1": "GTXE2_CHANNEL_RXDISPERR1", - "RXDISPERR2": "GTXE2_CHANNEL_RXDISPERR2", - "RXDISPERR3": "GTXE2_CHANNEL_RXDISPERR3", - "RXDISPERR4": "GTXE2_CHANNEL_RXDISPERR4", - "RXDISPERR5": "GTXE2_CHANNEL_RXDISPERR5", - "RXDISPERR6": "GTXE2_CHANNEL_RXDISPERR6", - "RXDISPERR7": "GTXE2_CHANNEL_RXDISPERR7", - "RXDLYBYPASS": "GTXE2_CHANNEL_RXDLYBYPASS", - "RXDLYEN": "GTXE2_CHANNEL_RXDLYEN", - "RXDLYOVRDEN": "GTXE2_CHANNEL_RXDLYOVRDEN", - "RXDLYSRESET": "GTXE2_CHANNEL_RXDLYSRESET", - "RXDLYSRESETDONE": "GTXE2_CHANNEL_RXDLYSRESETDONE", - "RXDLYTESTENB": "GTXE2_CHANNEL_RXDLYTESTENB", - "RXELECIDLE": "GTXE2_CHANNEL_RXELECIDLE", - "RXELECIDLEMODE0": "GTXE2_CHANNEL_RXELECIDLEMODE0", - "RXELECIDLEMODE1": "GTXE2_CHANNEL_RXELECIDLEMODE1", - "RXGEARBOXSLIP": "GTXE2_CHANNEL_RXGEARBOXSLIP", - "RXHEADER0": "GTXE2_CHANNEL_RXHEADER0", - "RXHEADER1": "GTXE2_CHANNEL_RXHEADER1", - "RXHEADER2": "GTXE2_CHANNEL_RXHEADER2", - "RXHEADERVALID": "GTXE2_CHANNEL_RXHEADERVALID", - "RXLPMEN": "GTXE2_CHANNEL_RXLPMEN", - "RXLPMHFHOLD": "GTXE2_CHANNEL_RXLPMHFHOLD", - "RXLPMHFOVRDEN": "GTXE2_CHANNEL_RXLPMHFOVRDEN", - "RXLPMLFHOLD": "GTXE2_CHANNEL_RXLPMLFHOLD", - "RXLPMLFKLOVRDEN": "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", - "RXMCOMMAALIGNEN": "GTXE2_CHANNEL_RXMCOMMAALIGNEN", - "RXMONITOROUT0": "GTXE2_CHANNEL_RXMONITOROUT0", - "RXMONITOROUT1": "GTXE2_CHANNEL_RXMONITOROUT1", - "RXMONITOROUT2": "GTXE2_CHANNEL_RXMONITOROUT2", - "RXMONITOROUT3": "GTXE2_CHANNEL_RXMONITOROUT3", - "RXMONITOROUT4": "GTXE2_CHANNEL_RXMONITOROUT4", - "RXMONITOROUT5": "GTXE2_CHANNEL_RXMONITOROUT5", - "RXMONITOROUT6": "GTXE2_CHANNEL_RXMONITOROUT6", - "RXMONITORSEL0": "GTXE2_CHANNEL_RXMONITORSEL0", - "RXMONITORSEL1": "GTXE2_CHANNEL_RXMONITORSEL1", - "RXNOTINTABLE0": "GTXE2_CHANNEL_RXNOTINTABLE0", - "RXNOTINTABLE1": "GTXE2_CHANNEL_RXNOTINTABLE1", - "RXNOTINTABLE2": "GTXE2_CHANNEL_RXNOTINTABLE2", - "RXNOTINTABLE3": "GTXE2_CHANNEL_RXNOTINTABLE3", - "RXNOTINTABLE4": "GTXE2_CHANNEL_RXNOTINTABLE4", - "RXNOTINTABLE5": "GTXE2_CHANNEL_RXNOTINTABLE5", - "RXNOTINTABLE6": "GTXE2_CHANNEL_RXNOTINTABLE6", - "RXNOTINTABLE7": "GTXE2_CHANNEL_RXNOTINTABLE7", - "RXOOBRESET": "GTXE2_CHANNEL_RXOOBRESET", - "RXOSHOLD": "GTXE2_CHANNEL_RXOSHOLD", - "RXOSOVRDEN": "GTXE2_CHANNEL_RXOSOVRDEN", - "RXOUTCLK": "GTXE2_CHANNEL_GTRXOUTCLK_3", - "RXOUTCLKFABRIC": "GTXE2_CHANNEL_RXOUTCLKFABRIC", - "RXOUTCLKPCS": "GTXE2_CHANNEL_RXOUTCLKPCS", - "RXOUTCLKSEL0": "GTXE2_CHANNEL_RXOUTCLKSEL0", - "RXOUTCLKSEL1": "GTXE2_CHANNEL_RXOUTCLKSEL1", - "RXOUTCLKSEL2": "GTXE2_CHANNEL_RXOUTCLKSEL2", - "RXPCD1DONE": "GTXE2_CHANNEL_RXPCD1DONE", - "RXPCOMMAALIGNEN": "GTXE2_CHANNEL_RXPCOMMAALIGNEN", - "RXPCSRESET": "GTXE2_CHANNEL_RXPCSRESET", - "RXPD0": "GTXE2_CHANNEL_RXPD0", - "RXPD1": "GTXE2_CHANNEL_RXPD1", - "RXPHALIGN": "GTXE2_CHANNEL_RXPHALIGN", - "RXPHALIGNDONE": "GTXE2_CHANNEL_RXPHALIGNDONE", - "RXPHALIGNEN": "GTXE2_CHANNEL_RXPHALIGNEN", - "RXPHDLYPD": "GTXE2_CHANNEL_RXPHDLYPD", - "RXPHDLYRESET": "GTXE2_CHANNEL_RXPHDLYRESET", - "RXPHMONITOR0": "GTXE2_CHANNEL_RXPHMONITOR0", - "RXPHMONITOR1": "GTXE2_CHANNEL_RXPHMONITOR1", - "RXPHMONITOR2": "GTXE2_CHANNEL_RXPHMONITOR2", - "RXPHMONITOR3": "GTXE2_CHANNEL_RXPHMONITOR3", - "RXPHMONITOR4": "GTXE2_CHANNEL_RXPHMONITOR4", - "RXPHOVRDEN": "GTXE2_CHANNEL_RXPHOVRDEN", - "RXPHSLIPMONITOR0": "GTXE2_CHANNEL_RXPHSLIPMONITOR0", - "RXPHSLIPMONITOR1": "GTXE2_CHANNEL_RXPHSLIPMONITOR1", - "RXPHSLIPMONITOR2": "GTXE2_CHANNEL_RXPHSLIPMONITOR2", - "RXPHSLIPMONITOR3": "GTXE2_CHANNEL_RXPHSLIPMONITOR3", - "RXPHSLIPMONITOR4": "GTXE2_CHANNEL_RXPHSLIPMONITOR4", - "RXPMARESET": "GTXE2_CHANNEL_RXPMARESET", - "RXPOLARITY": "GTXE2_CHANNEL_RXPOLARITY", - "RXPRBSCNTRESET": "GTXE2_CHANNEL_RXPRBSCNTRESET", - "RXPRBSERR": "GTXE2_CHANNEL_RXPRBSERR", - "RXPRBSSEL0": "GTXE2_CHANNEL_RXPRBSSEL0", - "RXPRBSSEL1": "GTXE2_CHANNEL_RXPRBSSEL1", - "RXPRBSSEL2": "GTXE2_CHANNEL_RXPRBSSEL2", - "RXQPIEN": "GTXE2_CHANNEL_RXQPIEN", - "RXQPISENN": "GTXE2_CHANNEL_RXQPISENN", - "RXQPISENP": "GTXE2_CHANNEL_RXQPISENP", - "RXRATE0": "GTXE2_CHANNEL_RXRATE0", - "RXRATE1": "GTXE2_CHANNEL_RXRATE1", - "RXRATE2": "GTXE2_CHANNEL_RXRATE2", - "RXRATEDONE": "GTXE2_CHANNEL_RXRATEDONE", - "RXRESETDONE": "GTXE2_CHANNEL_RXRESETDONE", - "RXSLIDE": "GTXE2_CHANNEL_RXSLIDE", - "RXSTARTOFSEQ": "GTXE2_CHANNEL_RXSTARTOFSEQ", - "RXSTATUS0": "GTXE2_CHANNEL_RXSTATUS0", - "RXSTATUS1": "GTXE2_CHANNEL_RXSTATUS1", - "RXSTATUS2": "GTXE2_CHANNEL_RXSTATUS2", - "RXSYSCLKSEL0": "GTXE2_CHANNEL_RXSYSCLKSEL0", - "RXSYSCLKSEL1": "GTXE2_CHANNEL_RXSYSCLKSEL1", - "RXUSERRDY": "GTXE2_CHANNEL_RXUSERRDY", - "RXUSRCLK": "GTXE2_CHANNEL_RXUSRCLK", - "RXUSRCLK2": "GTXE2_CHANNEL_RXUSRCLK2", - "RXVALID": "GTXE2_CHANNEL_RXVALID", - "SCANCLK": "GTXE2_CHANNEL_SCANCLK", - "SCANENB": "GTXE2_CHANNEL_SCANENB", - "SCANIN0": "GTXE2_CHANNEL_SCANIN0", - "SCANIN1": "GTXE2_CHANNEL_SCANIN1", - "SCANIN2": "GTXE2_CHANNEL_SCANIN2", - "SCANIN3": "GTXE2_CHANNEL_SCANIN3", - "SCANIN4": "GTXE2_CHANNEL_SCANIN4", - "SCANMODEB": "GTXE2_CHANNEL_SCANMODEB", - "SCANOUT0": "GTXE2_CHANNEL_SCANOUT0", - "SCANOUT1": "GTXE2_CHANNEL_SCANOUT1", - "SCANOUT2": "GTXE2_CHANNEL_SCANOUT2", - "SCANOUT3": "GTXE2_CHANNEL_SCANOUT3", - "SCANOUT4": "GTXE2_CHANNEL_SCANOUT4", - "SETERRSTATUS": "GTXE2_CHANNEL_SETERRSTATUS", - "TSTCLK0": "GTXE2_CHANNEL_TSTCLK0", - "TSTCLK1": "GTXE2_CHANNEL_TSTCLK1", - "TSTIN0": "GTXE2_CHANNEL_TSTIN0", - "TSTIN1": "GTXE2_CHANNEL_TSTIN1", - "TSTIN10": "GTXE2_CHANNEL_TSTIN10", - "TSTIN11": "GTXE2_CHANNEL_TSTIN11", - "TSTIN12": "GTXE2_CHANNEL_TSTIN12", - "TSTIN13": "GTXE2_CHANNEL_TSTIN13", - "TSTIN14": "GTXE2_CHANNEL_TSTIN14", - "TSTIN15": "GTXE2_CHANNEL_TSTIN15", - "TSTIN16": "GTXE2_CHANNEL_TSTIN16", - "TSTIN17": "GTXE2_CHANNEL_TSTIN17", - "TSTIN18": "GTXE2_CHANNEL_TSTIN18", - "TSTIN19": "GTXE2_CHANNEL_TSTIN19", - "TSTIN2": "GTXE2_CHANNEL_TSTIN2", - "TSTIN3": "GTXE2_CHANNEL_TSTIN3", - "TSTIN4": "GTXE2_CHANNEL_TSTIN4", - "TSTIN5": "GTXE2_CHANNEL_TSTIN5", - "TSTIN6": "GTXE2_CHANNEL_TSTIN6", - "TSTIN7": "GTXE2_CHANNEL_TSTIN7", - "TSTIN8": "GTXE2_CHANNEL_TSTIN8", - "TSTIN9": "GTXE2_CHANNEL_TSTIN9", - "TSTOUT0": "GTXE2_CHANNEL_TSTOUT0", - "TSTOUT1": "GTXE2_CHANNEL_TSTOUT1", - "TSTOUT2": "GTXE2_CHANNEL_TSTOUT2", - "TSTOUT3": "GTXE2_CHANNEL_TSTOUT3", - "TSTOUT4": "GTXE2_CHANNEL_TSTOUT4", - "TSTOUT5": "GTXE2_CHANNEL_TSTOUT5", - "TSTOUT6": "GTXE2_CHANNEL_TSTOUT6", - "TSTOUT7": "GTXE2_CHANNEL_TSTOUT7", - "TSTOUT8": "GTXE2_CHANNEL_TSTOUT8", - "TSTOUT9": "GTXE2_CHANNEL_TSTOUT9", - "TSTPD0": "GTXE2_CHANNEL_TSTPD0", - "TSTPD1": "GTXE2_CHANNEL_TSTPD1", - "TSTPD2": "GTXE2_CHANNEL_TSTPD2", - "TSTPD3": "GTXE2_CHANNEL_TSTPD3", - "TSTPD4": "GTXE2_CHANNEL_TSTPD4", - "TSTPDOVRDB": "GTXE2_CHANNEL_TSTPDOVRDB", - "TX8B10BBYPASS0": "GTXE2_CHANNEL_TX8B10BBYPASS0", - "TX8B10BBYPASS1": "GTXE2_CHANNEL_TX8B10BBYPASS1", - "TX8B10BBYPASS2": "GTXE2_CHANNEL_TX8B10BBYPASS2", - "TX8B10BBYPASS3": "GTXE2_CHANNEL_TX8B10BBYPASS3", - "TX8B10BBYPASS4": "GTXE2_CHANNEL_TX8B10BBYPASS4", - "TX8B10BBYPASS5": "GTXE2_CHANNEL_TX8B10BBYPASS5", - "TX8B10BBYPASS6": "GTXE2_CHANNEL_TX8B10BBYPASS6", - "TX8B10BBYPASS7": "GTXE2_CHANNEL_TX8B10BBYPASS7", - "TX8B10BEN": "GTXE2_CHANNEL_TX8B10BEN", - "TXBUFDIFFCTRL0": "GTXE2_CHANNEL_TXBUFDIFFCTRL0", - "TXBUFDIFFCTRL1": "GTXE2_CHANNEL_TXBUFDIFFCTRL1", - "TXBUFDIFFCTRL2": "GTXE2_CHANNEL_TXBUFDIFFCTRL2", - "TXBUFSTATUS0": "GTXE2_CHANNEL_TXBUFSTATUS0", - "TXBUFSTATUS1": "GTXE2_CHANNEL_TXBUFSTATUS1", - "TXCHARDISPMODE0": "GTXE2_CHANNEL_TXCHARDISPMODE0", - "TXCHARDISPMODE1": "GTXE2_CHANNEL_TXCHARDISPMODE1", - "TXCHARDISPMODE2": "GTXE2_CHANNEL_TXCHARDISPMODE2", - "TXCHARDISPMODE3": "GTXE2_CHANNEL_TXCHARDISPMODE3", - "TXCHARDISPMODE4": "GTXE2_CHANNEL_TXCHARDISPMODE4", - "TXCHARDISPMODE5": "GTXE2_CHANNEL_TXCHARDISPMODE5", - "TXCHARDISPMODE6": "GTXE2_CHANNEL_TXCHARDISPMODE6", - "TXCHARDISPMODE7": "GTXE2_CHANNEL_TXCHARDISPMODE7", - "TXCHARDISPVAL0": "GTXE2_CHANNEL_TXCHARDISPVAL0", - "TXCHARDISPVAL1": "GTXE2_CHANNEL_TXCHARDISPVAL1", - "TXCHARDISPVAL2": "GTXE2_CHANNEL_TXCHARDISPVAL2", - "TXCHARDISPVAL3": "GTXE2_CHANNEL_TXCHARDISPVAL3", - "TXCHARDISPVAL4": "GTXE2_CHANNEL_TXCHARDISPVAL4", - "TXCHARDISPVAL5": "GTXE2_CHANNEL_TXCHARDISPVAL5", - "TXCHARDISPVAL6": "GTXE2_CHANNEL_TXCHARDISPVAL6", - "TXCHARDISPVAL7": "GTXE2_CHANNEL_TXCHARDISPVAL7", - "TXCHARISK0": "GTXE2_CHANNEL_TXCHARISK0", - "TXCHARISK1": "GTXE2_CHANNEL_TXCHARISK1", - "TXCHARISK2": "GTXE2_CHANNEL_TXCHARISK2", - "TXCHARISK3": "GTXE2_CHANNEL_TXCHARISK3", - "TXCHARISK4": "GTXE2_CHANNEL_TXCHARISK4", - "TXCHARISK5": "GTXE2_CHANNEL_TXCHARISK5", - "TXCHARISK6": "GTXE2_CHANNEL_TXCHARISK6", - "TXCHARISK7": "GTXE2_CHANNEL_TXCHARISK7", - "TXCOMFINISH": "GTXE2_CHANNEL_TXCOMFINISH", - "TXCOMINIT": "GTXE2_CHANNEL_TXCOMINIT", - "TXCOMSAS": "GTXE2_CHANNEL_TXCOMSAS", - "TXCOMWAKE": "GTXE2_CHANNEL_TXCOMWAKE", - "TXDATA0": "GTXE2_CHANNEL_TXDATA0", - "TXDATA1": "GTXE2_CHANNEL_TXDATA1", - "TXDATA10": "GTXE2_CHANNEL_TXDATA10", - "TXDATA11": "GTXE2_CHANNEL_TXDATA11", - "TXDATA12": "GTXE2_CHANNEL_TXDATA12", - "TXDATA13": "GTXE2_CHANNEL_TXDATA13", - "TXDATA14": "GTXE2_CHANNEL_TXDATA14", - "TXDATA15": "GTXE2_CHANNEL_TXDATA15", - "TXDATA16": "GTXE2_CHANNEL_TXDATA16", - "TXDATA17": "GTXE2_CHANNEL_TXDATA17", - "TXDATA18": "GTXE2_CHANNEL_TXDATA18", - "TXDATA19": "GTXE2_CHANNEL_TXDATA19", - "TXDATA2": "GTXE2_CHANNEL_TXDATA2", - "TXDATA20": "GTXE2_CHANNEL_TXDATA20", - "TXDATA21": "GTXE2_CHANNEL_TXDATA21", - "TXDATA22": "GTXE2_CHANNEL_TXDATA22", - "TXDATA23": "GTXE2_CHANNEL_TXDATA23", - "TXDATA24": "GTXE2_CHANNEL_TXDATA24", - "TXDATA25": "GTXE2_CHANNEL_TXDATA25", - "TXDATA26": "GTXE2_CHANNEL_TXDATA26", - "TXDATA27": "GTXE2_CHANNEL_TXDATA27", - "TXDATA28": "GTXE2_CHANNEL_TXDATA28", - "TXDATA29": "GTXE2_CHANNEL_TXDATA29", - "TXDATA3": "GTXE2_CHANNEL_TXDATA3", - "TXDATA30": "GTXE2_CHANNEL_TXDATA30", - "TXDATA31": "GTXE2_CHANNEL_TXDATA31", - "TXDATA32": "GTXE2_CHANNEL_TXDATA32", - "TXDATA33": "GTXE2_CHANNEL_TXDATA33", - "TXDATA34": "GTXE2_CHANNEL_TXDATA34", - "TXDATA35": "GTXE2_CHANNEL_TXDATA35", - "TXDATA36": "GTXE2_CHANNEL_TXDATA36", - "TXDATA37": "GTXE2_CHANNEL_TXDATA37", - "TXDATA38": "GTXE2_CHANNEL_TXDATA38", - "TXDATA39": "GTXE2_CHANNEL_TXDATA39", - "TXDATA4": "GTXE2_CHANNEL_TXDATA4", - "TXDATA40": "GTXE2_CHANNEL_TXDATA40", - "TXDATA41": "GTXE2_CHANNEL_TXDATA41", - "TXDATA42": "GTXE2_CHANNEL_TXDATA42", - "TXDATA43": "GTXE2_CHANNEL_TXDATA43", - "TXDATA44": "GTXE2_CHANNEL_TXDATA44", - "TXDATA45": "GTXE2_CHANNEL_TXDATA45", - "TXDATA46": "GTXE2_CHANNEL_TXDATA46", - "TXDATA47": "GTXE2_CHANNEL_TXDATA47", - "TXDATA48": "GTXE2_CHANNEL_TXDATA48", - "TXDATA49": "GTXE2_CHANNEL_TXDATA49", - "TXDATA5": "GTXE2_CHANNEL_TXDATA5", - "TXDATA50": "GTXE2_CHANNEL_TXDATA50", - "TXDATA51": "GTXE2_CHANNEL_TXDATA51", - "TXDATA52": "GTXE2_CHANNEL_TXDATA52", - "TXDATA53": "GTXE2_CHANNEL_TXDATA53", - "TXDATA54": "GTXE2_CHANNEL_TXDATA54", - "TXDATA55": "GTXE2_CHANNEL_TXDATA55", - "TXDATA56": "GTXE2_CHANNEL_TXDATA56", - "TXDATA57": "GTXE2_CHANNEL_TXDATA57", - "TXDATA58": "GTXE2_CHANNEL_TXDATA58", - "TXDATA59": "GTXE2_CHANNEL_TXDATA59", - "TXDATA6": "GTXE2_CHANNEL_TXDATA6", - "TXDATA60": "GTXE2_CHANNEL_TXDATA60", - "TXDATA61": "GTXE2_CHANNEL_TXDATA61", - "TXDATA62": "GTXE2_CHANNEL_TXDATA62", - "TXDATA63": "GTXE2_CHANNEL_TXDATA63", - "TXDATA7": "GTXE2_CHANNEL_TXDATA7", - "TXDATA8": "GTXE2_CHANNEL_TXDATA8", - "TXDATA9": "GTXE2_CHANNEL_TXDATA9", - "TXDEEMPH": "GTXE2_CHANNEL_TXDEEMPH", - "TXDETECTRX": "GTXE2_CHANNEL_TXDETECTRX", - "TXDIFFCTRL0": "GTXE2_CHANNEL_TXDIFFCTRL0", - "TXDIFFCTRL1": "GTXE2_CHANNEL_TXDIFFCTRL1", - "TXDIFFCTRL2": "GTXE2_CHANNEL_TXDIFFCTRL2", - "TXDIFFCTRL3": "GTXE2_CHANNEL_TXDIFFCTRL3", - "TXDIFFPD": "GTXE2_CHANNEL_TXDIFFPD", - "TXDLYBYPASS": "GTXE2_CHANNEL_TXDLYBYPASS", - "TXDLYEN": "GTXE2_CHANNEL_TXDLYEN", - "TXDLYHOLD": "GTXE2_CHANNEL_TXDLYHOLD", - "TXDLYOVRDEN": "GTXE2_CHANNEL_TXDLYOVRDEN", - "TXDLYSRESET": "GTXE2_CHANNEL_TXDLYSRESET", - "TXDLYSRESETDONE": "GTXE2_CHANNEL_TXDLYSRESETDONE", - "TXDLYTESTENB": "GTXE2_CHANNEL_TXDLYTESTENB", - "TXDLYUPDOWN": "GTXE2_CHANNEL_TXDLYUPDOWN", - "TXELECIDLE": "GTXE2_CHANNEL_TXELECIDLE", - "TXGEARBOXREADY": "GTXE2_CHANNEL_TXGEARBOXREADY", - "TXHEADER0": "GTXE2_CHANNEL_TXHEADER0", - "TXHEADER1": "GTXE2_CHANNEL_TXHEADER1", - "TXHEADER2": "GTXE2_CHANNEL_TXHEADER2", - "TXINHIBIT": "GTXE2_CHANNEL_TXINHIBIT", - "TXMAINCURSOR0": "GTXE2_CHANNEL_TXMAINCURSOR0", - "TXMAINCURSOR1": "GTXE2_CHANNEL_TXMAINCURSOR1", - "TXMAINCURSOR2": "GTXE2_CHANNEL_TXMAINCURSOR2", - "TXMAINCURSOR3": "GTXE2_CHANNEL_TXMAINCURSOR3", - "TXMAINCURSOR4": "GTXE2_CHANNEL_TXMAINCURSOR4", - "TXMAINCURSOR5": "GTXE2_CHANNEL_TXMAINCURSOR5", - "TXMAINCURSOR6": "GTXE2_CHANNEL_TXMAINCURSOR6", - "TXMARGIN0": "GTXE2_CHANNEL_TXMARGIN0", - "TXMARGIN1": "GTXE2_CHANNEL_TXMARGIN1", - "TXMARGIN2": "GTXE2_CHANNEL_TXMARGIN2", - "TXOUTCLK": "GTXE2_CHANNEL_GTTXOUTCLK_3", - "TXOUTCLKFABRIC": "GTXE2_CHANNEL_TXOUTCLKFABRIC", - "TXOUTCLKPCS": "GTXE2_CHANNEL_TXOUTCLKPCS", - "TXOUTCLKSEL0": "GTXE2_CHANNEL_TXOUTCLKSEL0", - "TXOUTCLKSEL1": "GTXE2_CHANNEL_TXOUTCLKSEL1", - "TXOUTCLKSEL2": "GTXE2_CHANNEL_TXOUTCLKSEL2", - "TXPCSRESET": "GTXE2_CHANNEL_TXPCSRESET", - "TXPD0": "GTXE2_CHANNEL_TXPD0", - "TXPD1": "GTXE2_CHANNEL_TXPD1", - "TXPDELECIDLEMODE": "GTXE2_CHANNEL_TXPDELECIDLEMODE", - "TXPHALIGN": "GTXE2_CHANNEL_TXPHALIGN", - "TXPHALIGNDONE": "GTXE2_CHANNEL_TXPHALIGNDONE", - "TXPHALIGNEN": "GTXE2_CHANNEL_TXPHALIGNEN", - "TXPHDLYPD": "GTXE2_CHANNEL_TXPHDLYPD", - "TXPHDLYRESET": "GTXE2_CHANNEL_TXPHDLYRESET", - "TXPHDLYTSTCLK": "GTXE2_CHANNEL_TXPHDLYTSTCLK", - "TXPHINIT": "GTXE2_CHANNEL_TXPHINIT", - "TXPHINITDONE": "GTXE2_CHANNEL_TXPHINITDONE", - "TXPHOVRDEN": "GTXE2_CHANNEL_TXPHOVRDEN", - "TXPISOPD": "GTXE2_CHANNEL_TXPISOPD", - "TXPMARESET": "GTXE2_CHANNEL_TXPMARESET", - "TXPOLARITY": "GTXE2_CHANNEL_TXPOLARITY", - "TXPOSTCURSOR0": "GTXE2_CHANNEL_TXPOSTCURSOR0", - "TXPOSTCURSOR1": "GTXE2_CHANNEL_TXPOSTCURSOR1", - "TXPOSTCURSOR2": "GTXE2_CHANNEL_TXPOSTCURSOR2", - "TXPOSTCURSOR3": "GTXE2_CHANNEL_TXPOSTCURSOR3", - "TXPOSTCURSOR4": "GTXE2_CHANNEL_TXPOSTCURSOR4", - "TXPOSTCURSORINV": "GTXE2_CHANNEL_TXPOSTCURSORINV", - "TXPRBSFORCEERR": "GTXE2_CHANNEL_TXPRBSFORCEERR", - "TXPRBSSEL0": "GTXE2_CHANNEL_TXPRBSSEL0", - "TXPRBSSEL1": "GTXE2_CHANNEL_TXPRBSSEL1", - "TXPRBSSEL2": "GTXE2_CHANNEL_TXPRBSSEL2", - "TXPRECURSOR0": "GTXE2_CHANNEL_TXPRECURSOR0", - "TXPRECURSOR1": "GTXE2_CHANNEL_TXPRECURSOR1", - "TXPRECURSOR2": "GTXE2_CHANNEL_TXPRECURSOR2", - "TXPRECURSOR3": "GTXE2_CHANNEL_TXPRECURSOR3", - "TXPRECURSOR4": "GTXE2_CHANNEL_TXPRECURSOR4", - "TXPRECURSORINV": "GTXE2_CHANNEL_TXPRECURSORINV", - "TXQPIBIASEN": "GTXE2_CHANNEL_TXQPIBIASEN", - "TXQPISENN": "GTXE2_CHANNEL_TXQPISENN", - "TXQPISENP": "GTXE2_CHANNEL_TXQPISENP", - "TXQPISTRONGPDOWN": "GTXE2_CHANNEL_TXQPISTRONGPDOWN", - "TXQPIWEAKPUP": "GTXE2_CHANNEL_TXQPIWEAKPUP", - "TXRATE0": "GTXE2_CHANNEL_TXRATE0", - "TXRATE1": "GTXE2_CHANNEL_TXRATE1", - "TXRATE2": "GTXE2_CHANNEL_TXRATE2", - "TXRATEDONE": "GTXE2_CHANNEL_TXRATEDONE", - "TXRESETDONE": "GTXE2_CHANNEL_TXRESETDONE", - "TXRUNDISP0": "GTXE2_CHANNEL_TXRUNDISP0", - "TXRUNDISP1": "GTXE2_CHANNEL_TXRUNDISP1", - "TXRUNDISP2": "GTXE2_CHANNEL_TXRUNDISP2", - "TXRUNDISP3": "GTXE2_CHANNEL_TXRUNDISP3", - "TXRUNDISP4": "GTXE2_CHANNEL_TXRUNDISP4", - "TXRUNDISP5": "GTXE2_CHANNEL_TXRUNDISP5", - "TXRUNDISP6": "GTXE2_CHANNEL_TXRUNDISP6", - "TXRUNDISP7": "GTXE2_CHANNEL_TXRUNDISP7", - "TXSEQUENCE0": "GTXE2_CHANNEL_TXSEQUENCE0", - "TXSEQUENCE1": "GTXE2_CHANNEL_TXSEQUENCE1", - "TXSEQUENCE2": "GTXE2_CHANNEL_TXSEQUENCE2", - "TXSEQUENCE3": "GTXE2_CHANNEL_TXSEQUENCE3", - "TXSEQUENCE4": "GTXE2_CHANNEL_TXSEQUENCE4", - "TXSEQUENCE5": "GTXE2_CHANNEL_TXSEQUENCE5", - "TXSEQUENCE6": "GTXE2_CHANNEL_TXSEQUENCE6", - "TXSTARTSEQ": "GTXE2_CHANNEL_TXSTARTSEQ", - "TXSWING": "GTXE2_CHANNEL_TXSWING", - "TXSYSCLKSEL0": "GTXE2_CHANNEL_TXSYSCLKSEL0", - "TXSYSCLKSEL1": "GTXE2_CHANNEL_TXSYSCLKSEL1", - "TXUSERRDY": "GTXE2_CHANNEL_TXUSERRDY", - "TXUSRCLK": "GTXE2_CHANNEL_TXUSRCLK", - "TXUSRCLK2": "GTXE2_CHANNEL_TXUSRCLK2" + "CFGRESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CFGRESET" + }, + "CLKRSVD0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD0" + }, + "CLKRSVD1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD1" + }, + "CLKRSVD2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_CLKRSVD2" + }, + "CLKRSVD3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + 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"wire": "GTXE2_CHANNEL_TXQPISENN" + }, + "TXQPISENP": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXQPISENP" + }, + "TXQPISTRONGPDOWN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXQPISTRONGPDOWN" + }, + "TXQPIWEAKPUP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXQPIWEAKPUP" + }, + "TXRATE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXRATE0" + }, + "TXRATE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXRATE1" + }, + "TXRATE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXRATE2" + }, + "TXRATEDONE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRATEDONE" + }, + "TXRESETDONE": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRESETDONE" + }, + "TXRUNDISP0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP0" + }, + "TXRUNDISP1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP1" + }, + "TXRUNDISP2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP2" + }, + "TXRUNDISP3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP3" + }, + "TXRUNDISP4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP4" + }, + "TXRUNDISP5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP5" + }, + "TXRUNDISP6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP6" + }, + "TXRUNDISP7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_CHANNEL_TXRUNDISP7" + }, + "TXSEQUENCE0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE0" + }, + "TXSEQUENCE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE1" + }, + "TXSEQUENCE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE2" + }, + "TXSEQUENCE3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE3" + }, + "TXSEQUENCE4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE4" + }, + "TXSEQUENCE5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE5" + }, + "TXSEQUENCE6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSEQUENCE6" + }, + "TXSTARTSEQ": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSTARTSEQ" + }, + "TXSWING": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSWING" + }, + "TXSYSCLKSEL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSYSCLKSEL0" + }, + "TXSYSCLKSEL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXSYSCLKSEL1" + }, + "TXUSERRDY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSERRDY" + }, + "TXUSRCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSRCLK" + }, + "TXUSRCLK2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXUSRCLK2" + } }, "type": "GTXE2_CHANNEL", "x_coord": 0, @@ -5095,7 +18159,16 @@ "name": "X0Y0", "prefix": "IPAD", "site_pins": { - "O": "GTXE2_CHANNEL_RXN_PAD" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "GTXE2_CHANNEL_RXN_PAD" + } }, "type": "IPAD", "x_coord": 0, @@ -5105,7 +18178,16 @@ "name": "X0Y1", "prefix": "IPAD", "site_pins": { - "O": "GTXE2_CHANNEL_RXP_PAD" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "GTXE2_CHANNEL_RXP_PAD" + } }, "type": "IPAD", "x_coord": 0, @@ -5115,7 +18197,16 @@ "name": "X0Y0", "prefix": "OPAD", "site_pins": { - "I": "GTXE2_CHANNEL_TXN_PAD" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXN_PAD" + } }, "type": "OPAD", "x_coord": 0, @@ -5125,7 +18216,16 @@ "name": "X0Y1", "prefix": "OPAD", "site_pins": { - "I": "GTXE2_CHANNEL_TXP_PAD" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_CHANNEL_TXP_PAD" + } }, "type": "OPAD", "x_coord": 0, @@ -5133,1722 +18233,5310 @@ } ], "tile_type": "GTX_CHANNEL_3", - "wires": [ - "GTXE2_BYP0_0", - "GTXE2_BYP0_1", - "GTXE2_BYP0_10", - "GTXE2_BYP0_2", - "GTXE2_BYP0_3", - "GTXE2_BYP0_4", - "GTXE2_BYP0_5", - "GTXE2_BYP0_6", - "GTXE2_BYP0_7", - "GTXE2_BYP0_8", - "GTXE2_BYP0_9", - "GTXE2_BYP1_0", - "GTXE2_BYP1_1", - "GTXE2_BYP1_10", - "GTXE2_BYP1_2", - "GTXE2_BYP1_3", - "GTXE2_BYP1_4", - "GTXE2_BYP1_5", - "GTXE2_BYP1_6", - "GTXE2_BYP1_7", - "GTXE2_BYP1_8", - "GTXE2_BYP1_9", - "GTXE2_BYP2_0", - "GTXE2_BYP2_1", - "GTXE2_BYP2_10", - "GTXE2_BYP2_2", - "GTXE2_BYP2_3", - "GTXE2_BYP2_4", - "GTXE2_BYP2_5", - "GTXE2_BYP2_6", - "GTXE2_BYP2_7", - "GTXE2_BYP2_8", - "GTXE2_BYP2_9", - "GTXE2_BYP3_0", - "GTXE2_BYP3_1", - "GTXE2_BYP3_10", - "GTXE2_BYP3_2", - "GTXE2_BYP3_3", - "GTXE2_BYP3_4", - "GTXE2_BYP3_5", - "GTXE2_BYP3_6", - "GTXE2_BYP3_7", - "GTXE2_BYP3_8", - "GTXE2_BYP3_9", - "GTXE2_BYP4_0", - "GTXE2_BYP4_1", - "GTXE2_BYP4_10", - "GTXE2_BYP4_2", - "GTXE2_BYP4_3", - "GTXE2_BYP4_4", - "GTXE2_BYP4_5", - "GTXE2_BYP4_6", - "GTXE2_BYP4_7", - "GTXE2_BYP4_8", - "GTXE2_BYP4_9", - "GTXE2_BYP5_0", - "GTXE2_BYP5_1", - "GTXE2_BYP5_10", - "GTXE2_BYP5_2", - "GTXE2_BYP5_3", - "GTXE2_BYP5_4", - "GTXE2_BYP5_5", - "GTXE2_BYP5_6", - "GTXE2_BYP5_7", - "GTXE2_BYP5_8", - "GTXE2_BYP5_9", - "GTXE2_BYP6_0", - "GTXE2_BYP6_1", - "GTXE2_BYP6_10", - "GTXE2_BYP6_2", - "GTXE2_BYP6_3", - "GTXE2_BYP6_4", - "GTXE2_BYP6_5", - "GTXE2_BYP6_6", - "GTXE2_BYP6_7", - "GTXE2_BYP6_8", - "GTXE2_BYP6_9", - "GTXE2_BYP7_0", - "GTXE2_BYP7_1", - "GTXE2_BYP7_10", - "GTXE2_BYP7_2", - "GTXE2_BYP7_3", - "GTXE2_BYP7_4", - "GTXE2_BYP7_5", - "GTXE2_BYP7_6", - "GTXE2_BYP7_7", - "GTXE2_BYP7_8", - "GTXE2_BYP7_9", - "GTXE2_CHANNEL_CFGRESET", - "GTXE2_CHANNEL_CLKRSVD0", - "GTXE2_CHANNEL_CLKRSVD1", - "GTXE2_CHANNEL_CLKRSVD2", - "GTXE2_CHANNEL_CLKRSVD3", - "GTXE2_CHANNEL_CPLLFBCLKLOST", - "GTXE2_CHANNEL_CPLLLOCK", - "GTXE2_CHANNEL_CPLLLOCKDETCLK", - "GTXE2_CHANNEL_CPLLLOCKEN", - "GTXE2_CHANNEL_CPLLPD", - "GTXE2_CHANNEL_CPLLREFCLKLOST", - "GTXE2_CHANNEL_CPLLREFCLKSEL0", - "GTXE2_CHANNEL_CPLLREFCLKSEL1", - "GTXE2_CHANNEL_CPLLREFCLKSEL2", - "GTXE2_CHANNEL_CPLLRESET", - "GTXE2_CHANNEL_DMONITOROUT0", - "GTXE2_CHANNEL_DMONITOROUT1", - "GTXE2_CHANNEL_DMONITOROUT2", - "GTXE2_CHANNEL_DMONITOROUT3", - "GTXE2_CHANNEL_DMONITOROUT4", - "GTXE2_CHANNEL_DMONITOROUT5", - "GTXE2_CHANNEL_DMONITOROUT6", - "GTXE2_CHANNEL_DMONITOROUT7", - "GTXE2_CHANNEL_DRPADDR0", - "GTXE2_CHANNEL_DRPADDR1", - "GTXE2_CHANNEL_DRPADDR2", - "GTXE2_CHANNEL_DRPADDR3", - "GTXE2_CHANNEL_DRPADDR4", - "GTXE2_CHANNEL_DRPADDR5", - "GTXE2_CHANNEL_DRPADDR6", - "GTXE2_CHANNEL_DRPADDR7", - "GTXE2_CHANNEL_DRPADDR8", - "GTXE2_CHANNEL_DRPCLK", - "GTXE2_CHANNEL_DRPDI0", - "GTXE2_CHANNEL_DRPDI1", - "GTXE2_CHANNEL_DRPDI10", - "GTXE2_CHANNEL_DRPDI11", - "GTXE2_CHANNEL_DRPDI12", - "GTXE2_CHANNEL_DRPDI13", - "GTXE2_CHANNEL_DRPDI14", - "GTXE2_CHANNEL_DRPDI15", - "GTXE2_CHANNEL_DRPDI2", - "GTXE2_CHANNEL_DRPDI3", - "GTXE2_CHANNEL_DRPDI4", - "GTXE2_CHANNEL_DRPDI5", - "GTXE2_CHANNEL_DRPDI6", - "GTXE2_CHANNEL_DRPDI7", - "GTXE2_CHANNEL_DRPDI8", - "GTXE2_CHANNEL_DRPDI9", - "GTXE2_CHANNEL_DRPDO0", - "GTXE2_CHANNEL_DRPDO1", - "GTXE2_CHANNEL_DRPDO10", - "GTXE2_CHANNEL_DRPDO11", - "GTXE2_CHANNEL_DRPDO12", - "GTXE2_CHANNEL_DRPDO13", - "GTXE2_CHANNEL_DRPDO14", - "GTXE2_CHANNEL_DRPDO15", - "GTXE2_CHANNEL_DRPDO2", - "GTXE2_CHANNEL_DRPDO3", - "GTXE2_CHANNEL_DRPDO4", - "GTXE2_CHANNEL_DRPDO5", - "GTXE2_CHANNEL_DRPDO6", - "GTXE2_CHANNEL_DRPDO7", - "GTXE2_CHANNEL_DRPDO8", - "GTXE2_CHANNEL_DRPDO9", - "GTXE2_CHANNEL_DRPEN", - "GTXE2_CHANNEL_DRPRDY", - "GTXE2_CHANNEL_DRPWE", - "GTXE2_CHANNEL_EDTBYPASS", - "GTXE2_CHANNEL_EDTCLOCK", - "GTXE2_CHANNEL_EDTCONFIGURATION", - "GTXE2_CHANNEL_EDTSINGLEBYPASSCHAIN", - "GTXE2_CHANNEL_EDTUPDATE", - "GTXE2_CHANNEL_EYESCANDATAERROR", - "GTXE2_CHANNEL_EYESCANMODE", - "GTXE2_CHANNEL_EYESCANRESET", - "GTXE2_CHANNEL_EYESCANTRIGGER", - "GTXE2_CHANNEL_GTGREFCLK", - "GTXE2_CHANNEL_GTNORTHREFCLK0", - "GTXE2_CHANNEL_GTNORTHREFCLK1", - "GTXE2_CHANNEL_GTQPLLCLK", - "GTXE2_CHANNEL_GTQPLLREFCLK", - "GTXE2_CHANNEL_GTREFCLK0", - "GTXE2_CHANNEL_GTREFCLK1", - "GTXE2_CHANNEL_GTREFCLKMONITOR", - "GTXE2_CHANNEL_GTRESETSEL", - "GTXE2_CHANNEL_GTRSVD0", - "GTXE2_CHANNEL_GTRSVD1", - "GTXE2_CHANNEL_GTRSVD10", - "GTXE2_CHANNEL_GTRSVD11", - "GTXE2_CHANNEL_GTRSVD12", - "GTXE2_CHANNEL_GTRSVD13", - "GTXE2_CHANNEL_GTRSVD14", - "GTXE2_CHANNEL_GTRSVD15", - "GTXE2_CHANNEL_GTRSVD2", - "GTXE2_CHANNEL_GTRSVD3", - "GTXE2_CHANNEL_GTRSVD4", - "GTXE2_CHANNEL_GTRSVD5", - "GTXE2_CHANNEL_GTRSVD6", - "GTXE2_CHANNEL_GTRSVD7", - "GTXE2_CHANNEL_GTRSVD8", - "GTXE2_CHANNEL_GTRSVD9", - "GTXE2_CHANNEL_GTRXOUTCLK_3", - "GTXE2_CHANNEL_GTRXRESET", - "GTXE2_CHANNEL_GTSOUTHREFCLK0", - "GTXE2_CHANNEL_GTSOUTHREFCLK1", - "GTXE2_CHANNEL_GTTXOUTCLK_3", - "GTXE2_CHANNEL_GTTXRESET", - "GTXE2_CHANNEL_LOOPBACK0", - "GTXE2_CHANNEL_LOOPBACK1", - "GTXE2_CHANNEL_LOOPBACK2", - "GTXE2_CHANNEL_NORTHREFCLK0", - "GTXE2_CHANNEL_NORTHREFCLK1", - "GTXE2_CHANNEL_PCSRSVDIN0", - "GTXE2_CHANNEL_PCSRSVDIN1", - "GTXE2_CHANNEL_PCSRSVDIN10", - "GTXE2_CHANNEL_PCSRSVDIN11", - "GTXE2_CHANNEL_PCSRSVDIN12", - "GTXE2_CHANNEL_PCSRSVDIN13", - "GTXE2_CHANNEL_PCSRSVDIN14", - "GTXE2_CHANNEL_PCSRSVDIN15", - "GTXE2_CHANNEL_PCSRSVDIN2", - "GTXE2_CHANNEL_PCSRSVDIN20", - "GTXE2_CHANNEL_PCSRSVDIN21", - "GTXE2_CHANNEL_PCSRSVDIN22", - "GTXE2_CHANNEL_PCSRSVDIN23", - "GTXE2_CHANNEL_PCSRSVDIN24", - "GTXE2_CHANNEL_PCSRSVDIN3", - "GTXE2_CHANNEL_PCSRSVDIN4", - "GTXE2_CHANNEL_PCSRSVDIN5", - "GTXE2_CHANNEL_PCSRSVDIN6", - "GTXE2_CHANNEL_PCSRSVDIN7", - "GTXE2_CHANNEL_PCSRSVDIN8", - "GTXE2_CHANNEL_PCSRSVDIN9", - "GTXE2_CHANNEL_PCSRSVDOUT0", - "GTXE2_CHANNEL_PCSRSVDOUT1", - "GTXE2_CHANNEL_PCSRSVDOUT10", - "GTXE2_CHANNEL_PCSRSVDOUT11", - "GTXE2_CHANNEL_PCSRSVDOUT12", - "GTXE2_CHANNEL_PCSRSVDOUT13", - "GTXE2_CHANNEL_PCSRSVDOUT14", - "GTXE2_CHANNEL_PCSRSVDOUT15", - "GTXE2_CHANNEL_PCSRSVDOUT2", - "GTXE2_CHANNEL_PCSRSVDOUT3", - "GTXE2_CHANNEL_PCSRSVDOUT4", - "GTXE2_CHANNEL_PCSRSVDOUT5", - "GTXE2_CHANNEL_PCSRSVDOUT6", - "GTXE2_CHANNEL_PCSRSVDOUT7", - "GTXE2_CHANNEL_PCSRSVDOUT8", - "GTXE2_CHANNEL_PCSRSVDOUT9", - "GTXE2_CHANNEL_PHYSTATUS", - "GTXE2_CHANNEL_PMARSVDIN0", - "GTXE2_CHANNEL_PMARSVDIN1", - "GTXE2_CHANNEL_PMARSVDIN2", - "GTXE2_CHANNEL_PMARSVDIN20", - "GTXE2_CHANNEL_PMARSVDIN21", - "GTXE2_CHANNEL_PMARSVDIN22", - "GTXE2_CHANNEL_PMARSVDIN23", - "GTXE2_CHANNEL_PMARSVDIN24", - "GTXE2_CHANNEL_PMARSVDIN3", - "GTXE2_CHANNEL_PMARSVDIN4", - "GTXE2_CHANNEL_PMASCANCLK0", - "GTXE2_CHANNEL_PMASCANCLK1", - "GTXE2_CHANNEL_PMASCANCLK2", - "GTXE2_CHANNEL_PMASCANCLK3", - "GTXE2_CHANNEL_PMASCANCLK4", - "GTXE2_CHANNEL_PMASCANENB", - "GTXE2_CHANNEL_PMASCANIN0", - "GTXE2_CHANNEL_PMASCANIN1", - "GTXE2_CHANNEL_PMASCANIN2", - "GTXE2_CHANNEL_PMASCANIN3", - "GTXE2_CHANNEL_PMASCANIN4", - "GTXE2_CHANNEL_PMASCANMODEB", - "GTXE2_CHANNEL_PMASCANOUT0", - "GTXE2_CHANNEL_PMASCANOUT1", - "GTXE2_CHANNEL_PMASCANOUT2", - "GTXE2_CHANNEL_PMASCANOUT3", - "GTXE2_CHANNEL_PMASCANOUT4", - "GTXE2_CHANNEL_PMASCANRSTEN", - "GTXE2_CHANNEL_QPLLCLK", - "GTXE2_CHANNEL_QPLLREFCLK", - "GTXE2_CHANNEL_REFCLK0", - "GTXE2_CHANNEL_REFCLK1", - "GTXE2_CHANNEL_RESETOVRD", - "GTXE2_CHANNEL_RX8B10BEN", - "GTXE2_CHANNEL_RXBUFRESET", - "GTXE2_CHANNEL_RXBUFSTATUS0", - "GTXE2_CHANNEL_RXBUFSTATUS1", - "GTXE2_CHANNEL_RXBUFSTATUS2", - "GTXE2_CHANNEL_RXBYTEISALIGNED", - "GTXE2_CHANNEL_RXBYTEREALIGN", - "GTXE2_CHANNEL_RXCDRFREQRESET", - "GTXE2_CHANNEL_RXCDRHOLD", - "GTXE2_CHANNEL_RXCDRLOCK", - "GTXE2_CHANNEL_RXCDROVRDEN", - "GTXE2_CHANNEL_RXCDRRESET", - "GTXE2_CHANNEL_RXCDRRESETRSV", - "GTXE2_CHANNEL_RXCHANBONDSEQ", - "GTXE2_CHANNEL_RXCHANISALIGNED", - "GTXE2_CHANNEL_RXCHANREALIGN", - "GTXE2_CHANNEL_RXCHARISCOMMA0", - "GTXE2_CHANNEL_RXCHARISCOMMA1", - "GTXE2_CHANNEL_RXCHARISCOMMA2", - "GTXE2_CHANNEL_RXCHARISCOMMA3", - "GTXE2_CHANNEL_RXCHARISCOMMA4", - "GTXE2_CHANNEL_RXCHARISCOMMA5", - "GTXE2_CHANNEL_RXCHARISCOMMA6", - "GTXE2_CHANNEL_RXCHARISCOMMA7", - "GTXE2_CHANNEL_RXCHARISK0", - "GTXE2_CHANNEL_RXCHARISK1", - "GTXE2_CHANNEL_RXCHARISK2", - "GTXE2_CHANNEL_RXCHARISK3", - "GTXE2_CHANNEL_RXCHARISK4", - "GTXE2_CHANNEL_RXCHARISK5", - "GTXE2_CHANNEL_RXCHARISK6", - "GTXE2_CHANNEL_RXCHARISK7", - "GTXE2_CHANNEL_RXCHBONDEN", - "GTXE2_CHANNEL_RXCHBONDI0", - "GTXE2_CHANNEL_RXCHBONDI1", - "GTXE2_CHANNEL_RXCHBONDI2", - "GTXE2_CHANNEL_RXCHBONDI3", - "GTXE2_CHANNEL_RXCHBONDI4", - "GTXE2_CHANNEL_RXCHBONDLEVEL0", - "GTXE2_CHANNEL_RXCHBONDLEVEL1", - "GTXE2_CHANNEL_RXCHBONDLEVEL2", - "GTXE2_CHANNEL_RXCHBONDMASTER", - "GTXE2_CHANNEL_RXCHBONDO0", - "GTXE2_CHANNEL_RXCHBONDO1", - "GTXE2_CHANNEL_RXCHBONDO2", - "GTXE2_CHANNEL_RXCHBONDO3", - "GTXE2_CHANNEL_RXCHBONDO4", - "GTXE2_CHANNEL_RXCHBONDSLAVE", - "GTXE2_CHANNEL_RXCLKCORCNT0", - "GTXE2_CHANNEL_RXCLKCORCNT1", - "GTXE2_CHANNEL_RXCOMINITDET", - "GTXE2_CHANNEL_RXCOMMADET", - "GTXE2_CHANNEL_RXCOMMADETEN", - "GTXE2_CHANNEL_RXCOMSASDET", - "GTXE2_CHANNEL_RXCOMWAKEDET", - "GTXE2_CHANNEL_RXDATA0", - "GTXE2_CHANNEL_RXDATA1", - "GTXE2_CHANNEL_RXDATA10", - "GTXE2_CHANNEL_RXDATA11", - "GTXE2_CHANNEL_RXDATA12", - "GTXE2_CHANNEL_RXDATA13", - "GTXE2_CHANNEL_RXDATA14", - "GTXE2_CHANNEL_RXDATA15", - "GTXE2_CHANNEL_RXDATA16", - "GTXE2_CHANNEL_RXDATA17", - "GTXE2_CHANNEL_RXDATA18", - "GTXE2_CHANNEL_RXDATA19", - "GTXE2_CHANNEL_RXDATA2", - "GTXE2_CHANNEL_RXDATA20", - "GTXE2_CHANNEL_RXDATA21", - "GTXE2_CHANNEL_RXDATA22", - "GTXE2_CHANNEL_RXDATA23", - "GTXE2_CHANNEL_RXDATA24", - "GTXE2_CHANNEL_RXDATA25", - "GTXE2_CHANNEL_RXDATA26", - "GTXE2_CHANNEL_RXDATA27", - "GTXE2_CHANNEL_RXDATA28", - "GTXE2_CHANNEL_RXDATA29", - "GTXE2_CHANNEL_RXDATA3", - "GTXE2_CHANNEL_RXDATA30", - "GTXE2_CHANNEL_RXDATA31", - "GTXE2_CHANNEL_RXDATA32", - "GTXE2_CHANNEL_RXDATA33", - "GTXE2_CHANNEL_RXDATA34", - "GTXE2_CHANNEL_RXDATA35", - "GTXE2_CHANNEL_RXDATA36", - "GTXE2_CHANNEL_RXDATA37", - "GTXE2_CHANNEL_RXDATA38", - "GTXE2_CHANNEL_RXDATA39", - "GTXE2_CHANNEL_RXDATA4", - "GTXE2_CHANNEL_RXDATA40", - "GTXE2_CHANNEL_RXDATA41", - "GTXE2_CHANNEL_RXDATA42", - "GTXE2_CHANNEL_RXDATA43", - "GTXE2_CHANNEL_RXDATA44", - "GTXE2_CHANNEL_RXDATA45", - "GTXE2_CHANNEL_RXDATA46", - "GTXE2_CHANNEL_RXDATA47", - "GTXE2_CHANNEL_RXDATA48", - "GTXE2_CHANNEL_RXDATA49", - "GTXE2_CHANNEL_RXDATA5", - "GTXE2_CHANNEL_RXDATA50", - "GTXE2_CHANNEL_RXDATA51", - "GTXE2_CHANNEL_RXDATA52", - "GTXE2_CHANNEL_RXDATA53", - "GTXE2_CHANNEL_RXDATA54", - "GTXE2_CHANNEL_RXDATA55", - "GTXE2_CHANNEL_RXDATA56", - "GTXE2_CHANNEL_RXDATA57", - "GTXE2_CHANNEL_RXDATA58", - "GTXE2_CHANNEL_RXDATA59", - "GTXE2_CHANNEL_RXDATA6", - "GTXE2_CHANNEL_RXDATA60", - "GTXE2_CHANNEL_RXDATA61", - "GTXE2_CHANNEL_RXDATA62", - "GTXE2_CHANNEL_RXDATA63", - "GTXE2_CHANNEL_RXDATA7", - "GTXE2_CHANNEL_RXDATA8", - "GTXE2_CHANNEL_RXDATA9", - "GTXE2_CHANNEL_RXDATAVALID", - "GTXE2_CHANNEL_RXDDIEN", - "GTXE2_CHANNEL_RXDEBUGPULSE", - "GTXE2_CHANNEL_RXDFEAGCHOLD", - "GTXE2_CHANNEL_RXDFEAGCOVRDEN", - "GTXE2_CHANNEL_RXDFECM1EN", - "GTXE2_CHANNEL_RXDFELFHOLD", - "GTXE2_CHANNEL_RXDFELFOVRDEN", - "GTXE2_CHANNEL_RXDFELPMRESET", - "GTXE2_CHANNEL_RXDFETAP2HOLD", - "GTXE2_CHANNEL_RXDFETAP2OVRDEN", - "GTXE2_CHANNEL_RXDFETAP3HOLD", - "GTXE2_CHANNEL_RXDFETAP3OVRDEN", - "GTXE2_CHANNEL_RXDFETAP4HOLD", - "GTXE2_CHANNEL_RXDFETAP4OVRDEN", - "GTXE2_CHANNEL_RXDFETAP5HOLD", - "GTXE2_CHANNEL_RXDFETAP5OVRDEN", - "GTXE2_CHANNEL_RXDFEUTHOLD", - "GTXE2_CHANNEL_RXDFEUTOVRDEN", - "GTXE2_CHANNEL_RXDFEVPHOLD", - "GTXE2_CHANNEL_RXDFEVPOVRDEN", - "GTXE2_CHANNEL_RXDFEVSEN", - "GTXE2_CHANNEL_RXDFEXYDEN", - "GTXE2_CHANNEL_RXDFEXYDHOLD", - "GTXE2_CHANNEL_RXDFEXYDOVRDEN", - "GTXE2_CHANNEL_RXDISPERR0", - "GTXE2_CHANNEL_RXDISPERR1", - "GTXE2_CHANNEL_RXDISPERR2", - "GTXE2_CHANNEL_RXDISPERR3", - "GTXE2_CHANNEL_RXDISPERR4", - "GTXE2_CHANNEL_RXDISPERR5", - "GTXE2_CHANNEL_RXDISPERR6", - "GTXE2_CHANNEL_RXDISPERR7", - "GTXE2_CHANNEL_RXDLYBYPASS", - "GTXE2_CHANNEL_RXDLYEN", - "GTXE2_CHANNEL_RXDLYOVRDEN", - "GTXE2_CHANNEL_RXDLYSRESET", - "GTXE2_CHANNEL_RXDLYSRESETDONE", - "GTXE2_CHANNEL_RXDLYTESTENB", - "GTXE2_CHANNEL_RXELECIDLE", - "GTXE2_CHANNEL_RXELECIDLEMODE0", - "GTXE2_CHANNEL_RXELECIDLEMODE1", - "GTXE2_CHANNEL_RXGEARBOXSLIP", - "GTXE2_CHANNEL_RXHEADER0", - "GTXE2_CHANNEL_RXHEADER1", - "GTXE2_CHANNEL_RXHEADER2", - "GTXE2_CHANNEL_RXHEADERVALID", - "GTXE2_CHANNEL_RXLPMEN", - "GTXE2_CHANNEL_RXLPMHFHOLD", - "GTXE2_CHANNEL_RXLPMHFOVRDEN", - "GTXE2_CHANNEL_RXLPMLFHOLD", - "GTXE2_CHANNEL_RXLPMLFKLOVRDEN", - "GTXE2_CHANNEL_RXMCOMMAALIGNEN", - "GTXE2_CHANNEL_RXMONITOROUT0", - "GTXE2_CHANNEL_RXMONITOROUT1", - "GTXE2_CHANNEL_RXMONITOROUT2", - "GTXE2_CHANNEL_RXMONITOROUT3", - "GTXE2_CHANNEL_RXMONITOROUT4", - "GTXE2_CHANNEL_RXMONITOROUT5", - "GTXE2_CHANNEL_RXMONITOROUT6", - "GTXE2_CHANNEL_RXMONITORSEL0", - "GTXE2_CHANNEL_RXMONITORSEL1", - "GTXE2_CHANNEL_RXN", - "GTXE2_CHANNEL_RXNOTINTABLE0", - "GTXE2_CHANNEL_RXNOTINTABLE1", - "GTXE2_CHANNEL_RXNOTINTABLE2", - "GTXE2_CHANNEL_RXNOTINTABLE3", - "GTXE2_CHANNEL_RXNOTINTABLE4", - "GTXE2_CHANNEL_RXNOTINTABLE5", - "GTXE2_CHANNEL_RXNOTINTABLE6", - "GTXE2_CHANNEL_RXNOTINTABLE7", - "GTXE2_CHANNEL_RXN_PAD", - "GTXE2_CHANNEL_RXOOBRESET", - "GTXE2_CHANNEL_RXOSHOLD", - "GTXE2_CHANNEL_RXOSOVRDEN", - "GTXE2_CHANNEL_RXOUTCLKFABRIC", - "GTXE2_CHANNEL_RXOUTCLKPCS", - "GTXE2_CHANNEL_RXOUTCLKSEL0", - "GTXE2_CHANNEL_RXOUTCLKSEL1", - "GTXE2_CHANNEL_RXOUTCLKSEL2", - "GTXE2_CHANNEL_RXOUTCLK_0", - "GTXE2_CHANNEL_RXOUTCLK_1", - "GTXE2_CHANNEL_RXOUTCLK_2", - "GTXE2_CHANNEL_RXOUTCLK_3", - "GTXE2_CHANNEL_RXP", - "GTXE2_CHANNEL_RXPCD1DONE", - "GTXE2_CHANNEL_RXPCOMMAALIGNEN", - "GTXE2_CHANNEL_RXPCSRESET", - "GTXE2_CHANNEL_RXPD0", - "GTXE2_CHANNEL_RXPD1", - "GTXE2_CHANNEL_RXPHALIGN", - "GTXE2_CHANNEL_RXPHALIGNDONE", - "GTXE2_CHANNEL_RXPHALIGNEN", - "GTXE2_CHANNEL_RXPHDLYPD", - "GTXE2_CHANNEL_RXPHDLYRESET", - "GTXE2_CHANNEL_RXPHMONITOR0", - "GTXE2_CHANNEL_RXPHMONITOR1", - "GTXE2_CHANNEL_RXPHMONITOR2", - "GTXE2_CHANNEL_RXPHMONITOR3", - "GTXE2_CHANNEL_RXPHMONITOR4", - "GTXE2_CHANNEL_RXPHOVRDEN", - "GTXE2_CHANNEL_RXPHSLIPMONITOR0", - "GTXE2_CHANNEL_RXPHSLIPMONITOR1", - "GTXE2_CHANNEL_RXPHSLIPMONITOR2", - "GTXE2_CHANNEL_RXPHSLIPMONITOR3", - "GTXE2_CHANNEL_RXPHSLIPMONITOR4", - "GTXE2_CHANNEL_RXPMARESET", - "GTXE2_CHANNEL_RXPOLARITY", - "GTXE2_CHANNEL_RXPRBSCNTRESET", - "GTXE2_CHANNEL_RXPRBSERR", - "GTXE2_CHANNEL_RXPRBSSEL0", - "GTXE2_CHANNEL_RXPRBSSEL1", - "GTXE2_CHANNEL_RXPRBSSEL2", - "GTXE2_CHANNEL_RXP_PAD", - "GTXE2_CHANNEL_RXQPIEN", - "GTXE2_CHANNEL_RXQPISENN", - "GTXE2_CHANNEL_RXQPISENP", - "GTXE2_CHANNEL_RXRATE0", - "GTXE2_CHANNEL_RXRATE1", - "GTXE2_CHANNEL_RXRATE2", - "GTXE2_CHANNEL_RXRATEDONE", - "GTXE2_CHANNEL_RXRESETDONE", - "GTXE2_CHANNEL_RXSLIDE", - "GTXE2_CHANNEL_RXSTARTOFSEQ", - "GTXE2_CHANNEL_RXSTATUS0", - "GTXE2_CHANNEL_RXSTATUS1", - "GTXE2_CHANNEL_RXSTATUS2", - "GTXE2_CHANNEL_RXSYSCLKSEL0", - "GTXE2_CHANNEL_RXSYSCLKSEL1", - "GTXE2_CHANNEL_RXUSERRDY", - "GTXE2_CHANNEL_RXUSRCLK", - "GTXE2_CHANNEL_RXUSRCLK2", - "GTXE2_CHANNEL_RXVALID", - "GTXE2_CHANNEL_SCANCLK", - "GTXE2_CHANNEL_SCANENB", - "GTXE2_CHANNEL_SCANIN0", - "GTXE2_CHANNEL_SCANIN1", - "GTXE2_CHANNEL_SCANIN2", - "GTXE2_CHANNEL_SCANIN3", - "GTXE2_CHANNEL_SCANIN4", - "GTXE2_CHANNEL_SCANMODEB", - "GTXE2_CHANNEL_SCANOUT0", - "GTXE2_CHANNEL_SCANOUT1", - "GTXE2_CHANNEL_SCANOUT2", - "GTXE2_CHANNEL_SCANOUT3", - "GTXE2_CHANNEL_SCANOUT4", - "GTXE2_CHANNEL_SETERRSTATUS", - "GTXE2_CHANNEL_SOUTHREFCLK0", - "GTXE2_CHANNEL_SOUTHREFCLK1", - "GTXE2_CHANNEL_TSTCLK0", - "GTXE2_CHANNEL_TSTCLK1", - "GTXE2_CHANNEL_TSTIN0", - "GTXE2_CHANNEL_TSTIN1", - "GTXE2_CHANNEL_TSTIN10", - "GTXE2_CHANNEL_TSTIN11", - "GTXE2_CHANNEL_TSTIN12", - "GTXE2_CHANNEL_TSTIN13", - "GTXE2_CHANNEL_TSTIN14", - "GTXE2_CHANNEL_TSTIN15", - "GTXE2_CHANNEL_TSTIN16", - "GTXE2_CHANNEL_TSTIN17", - "GTXE2_CHANNEL_TSTIN18", - "GTXE2_CHANNEL_TSTIN19", - "GTXE2_CHANNEL_TSTIN2", - "GTXE2_CHANNEL_TSTIN3", - "GTXE2_CHANNEL_TSTIN4", - "GTXE2_CHANNEL_TSTIN5", - "GTXE2_CHANNEL_TSTIN6", - "GTXE2_CHANNEL_TSTIN7", - "GTXE2_CHANNEL_TSTIN8", - "GTXE2_CHANNEL_TSTIN9", - "GTXE2_CHANNEL_TSTOUT0", - "GTXE2_CHANNEL_TSTOUT1", - "GTXE2_CHANNEL_TSTOUT2", - "GTXE2_CHANNEL_TSTOUT3", - "GTXE2_CHANNEL_TSTOUT4", - "GTXE2_CHANNEL_TSTOUT5", - "GTXE2_CHANNEL_TSTOUT6", - "GTXE2_CHANNEL_TSTOUT7", - "GTXE2_CHANNEL_TSTOUT8", - "GTXE2_CHANNEL_TSTOUT9", - "GTXE2_CHANNEL_TSTPD0", - "GTXE2_CHANNEL_TSTPD1", - "GTXE2_CHANNEL_TSTPD2", - "GTXE2_CHANNEL_TSTPD3", - "GTXE2_CHANNEL_TSTPD4", - "GTXE2_CHANNEL_TSTPDOVRDB", - "GTXE2_CHANNEL_TX8B10BBYPASS0", - "GTXE2_CHANNEL_TX8B10BBYPASS1", - "GTXE2_CHANNEL_TX8B10BBYPASS2", - "GTXE2_CHANNEL_TX8B10BBYPASS3", - "GTXE2_CHANNEL_TX8B10BBYPASS4", - "GTXE2_CHANNEL_TX8B10BBYPASS5", - "GTXE2_CHANNEL_TX8B10BBYPASS6", - "GTXE2_CHANNEL_TX8B10BBYPASS7", - "GTXE2_CHANNEL_TX8B10BEN", - "GTXE2_CHANNEL_TXBUFDIFFCTRL0", - "GTXE2_CHANNEL_TXBUFDIFFCTRL1", - "GTXE2_CHANNEL_TXBUFDIFFCTRL2", - "GTXE2_CHANNEL_TXBUFSTATUS0", - "GTXE2_CHANNEL_TXBUFSTATUS1", - "GTXE2_CHANNEL_TXCHARDISPMODE0", - "GTXE2_CHANNEL_TXCHARDISPMODE1", - "GTXE2_CHANNEL_TXCHARDISPMODE2", - "GTXE2_CHANNEL_TXCHARDISPMODE3", - "GTXE2_CHANNEL_TXCHARDISPMODE4", - "GTXE2_CHANNEL_TXCHARDISPMODE5", - "GTXE2_CHANNEL_TXCHARDISPMODE6", - "GTXE2_CHANNEL_TXCHARDISPMODE7", - "GTXE2_CHANNEL_TXCHARDISPVAL0", - "GTXE2_CHANNEL_TXCHARDISPVAL1", - "GTXE2_CHANNEL_TXCHARDISPVAL2", - "GTXE2_CHANNEL_TXCHARDISPVAL3", - "GTXE2_CHANNEL_TXCHARDISPVAL4", - "GTXE2_CHANNEL_TXCHARDISPVAL5", - "GTXE2_CHANNEL_TXCHARDISPVAL6", - "GTXE2_CHANNEL_TXCHARDISPVAL7", - "GTXE2_CHANNEL_TXCHARISK0", - "GTXE2_CHANNEL_TXCHARISK1", - "GTXE2_CHANNEL_TXCHARISK2", - "GTXE2_CHANNEL_TXCHARISK3", - "GTXE2_CHANNEL_TXCHARISK4", - "GTXE2_CHANNEL_TXCHARISK5", - "GTXE2_CHANNEL_TXCHARISK6", - "GTXE2_CHANNEL_TXCHARISK7", - "GTXE2_CHANNEL_TXCOMFINISH", - "GTXE2_CHANNEL_TXCOMINIT", - "GTXE2_CHANNEL_TXCOMSAS", - "GTXE2_CHANNEL_TXCOMWAKE", - "GTXE2_CHANNEL_TXDATA0", - "GTXE2_CHANNEL_TXDATA1", - "GTXE2_CHANNEL_TXDATA10", - "GTXE2_CHANNEL_TXDATA11", - "GTXE2_CHANNEL_TXDATA12", - "GTXE2_CHANNEL_TXDATA13", - "GTXE2_CHANNEL_TXDATA14", - "GTXE2_CHANNEL_TXDATA15", - "GTXE2_CHANNEL_TXDATA16", - "GTXE2_CHANNEL_TXDATA17", - "GTXE2_CHANNEL_TXDATA18", - "GTXE2_CHANNEL_TXDATA19", - "GTXE2_CHANNEL_TXDATA2", - "GTXE2_CHANNEL_TXDATA20", - "GTXE2_CHANNEL_TXDATA21", - "GTXE2_CHANNEL_TXDATA22", - "GTXE2_CHANNEL_TXDATA23", - "GTXE2_CHANNEL_TXDATA24", - "GTXE2_CHANNEL_TXDATA25", - "GTXE2_CHANNEL_TXDATA26", - "GTXE2_CHANNEL_TXDATA27", - "GTXE2_CHANNEL_TXDATA28", - "GTXE2_CHANNEL_TXDATA29", - "GTXE2_CHANNEL_TXDATA3", - "GTXE2_CHANNEL_TXDATA30", - "GTXE2_CHANNEL_TXDATA31", - "GTXE2_CHANNEL_TXDATA32", - "GTXE2_CHANNEL_TXDATA33", - "GTXE2_CHANNEL_TXDATA34", - "GTXE2_CHANNEL_TXDATA35", - "GTXE2_CHANNEL_TXDATA36", - "GTXE2_CHANNEL_TXDATA37", - "GTXE2_CHANNEL_TXDATA38", - "GTXE2_CHANNEL_TXDATA39", - "GTXE2_CHANNEL_TXDATA4", - "GTXE2_CHANNEL_TXDATA40", - "GTXE2_CHANNEL_TXDATA41", - "GTXE2_CHANNEL_TXDATA42", - "GTXE2_CHANNEL_TXDATA43", - "GTXE2_CHANNEL_TXDATA44", - "GTXE2_CHANNEL_TXDATA45", - "GTXE2_CHANNEL_TXDATA46", - "GTXE2_CHANNEL_TXDATA47", - "GTXE2_CHANNEL_TXDATA48", - "GTXE2_CHANNEL_TXDATA49", - "GTXE2_CHANNEL_TXDATA5", - "GTXE2_CHANNEL_TXDATA50", - "GTXE2_CHANNEL_TXDATA51", - "GTXE2_CHANNEL_TXDATA52", - "GTXE2_CHANNEL_TXDATA53", - "GTXE2_CHANNEL_TXDATA54", - "GTXE2_CHANNEL_TXDATA55", - "GTXE2_CHANNEL_TXDATA56", - "GTXE2_CHANNEL_TXDATA57", - "GTXE2_CHANNEL_TXDATA58", - "GTXE2_CHANNEL_TXDATA59", - "GTXE2_CHANNEL_TXDATA6", - "GTXE2_CHANNEL_TXDATA60", - "GTXE2_CHANNEL_TXDATA61", - "GTXE2_CHANNEL_TXDATA62", - "GTXE2_CHANNEL_TXDATA63", - "GTXE2_CHANNEL_TXDATA7", - "GTXE2_CHANNEL_TXDATA8", - "GTXE2_CHANNEL_TXDATA9", - "GTXE2_CHANNEL_TXDEEMPH", - "GTXE2_CHANNEL_TXDETECTRX", - "GTXE2_CHANNEL_TXDIFFCTRL0", - "GTXE2_CHANNEL_TXDIFFCTRL1", - "GTXE2_CHANNEL_TXDIFFCTRL2", - "GTXE2_CHANNEL_TXDIFFCTRL3", - "GTXE2_CHANNEL_TXDIFFPD", - "GTXE2_CHANNEL_TXDLYBYPASS", - "GTXE2_CHANNEL_TXDLYEN", - "GTXE2_CHANNEL_TXDLYHOLD", - "GTXE2_CHANNEL_TXDLYOVRDEN", - "GTXE2_CHANNEL_TXDLYSRESET", - "GTXE2_CHANNEL_TXDLYSRESETDONE", - "GTXE2_CHANNEL_TXDLYTESTENB", - "GTXE2_CHANNEL_TXDLYUPDOWN", - "GTXE2_CHANNEL_TXELECIDLE", - "GTXE2_CHANNEL_TXGEARBOXREADY", - "GTXE2_CHANNEL_TXHEADER0", - "GTXE2_CHANNEL_TXHEADER1", - "GTXE2_CHANNEL_TXHEADER2", - "GTXE2_CHANNEL_TXINHIBIT", - "GTXE2_CHANNEL_TXMAINCURSOR0", - "GTXE2_CHANNEL_TXMAINCURSOR1", - "GTXE2_CHANNEL_TXMAINCURSOR2", - "GTXE2_CHANNEL_TXMAINCURSOR3", - "GTXE2_CHANNEL_TXMAINCURSOR4", - "GTXE2_CHANNEL_TXMAINCURSOR5", - "GTXE2_CHANNEL_TXMAINCURSOR6", - "GTXE2_CHANNEL_TXMARGIN0", - "GTXE2_CHANNEL_TXMARGIN1", - "GTXE2_CHANNEL_TXMARGIN2", - "GTXE2_CHANNEL_TXN", - "GTXE2_CHANNEL_TXN_PAD", - "GTXE2_CHANNEL_TXOUTCLKFABRIC", - "GTXE2_CHANNEL_TXOUTCLKPCS", - "GTXE2_CHANNEL_TXOUTCLKSEL0", - "GTXE2_CHANNEL_TXOUTCLKSEL1", - "GTXE2_CHANNEL_TXOUTCLKSEL2", - "GTXE2_CHANNEL_TXOUTCLK_0", - "GTXE2_CHANNEL_TXOUTCLK_1", - "GTXE2_CHANNEL_TXOUTCLK_2", - "GTXE2_CHANNEL_TXOUTCLK_3", - "GTXE2_CHANNEL_TXP", - "GTXE2_CHANNEL_TXPCSRESET", - "GTXE2_CHANNEL_TXPD0", - "GTXE2_CHANNEL_TXPD1", - "GTXE2_CHANNEL_TXPDELECIDLEMODE", - "GTXE2_CHANNEL_TXPHALIGN", - "GTXE2_CHANNEL_TXPHALIGNDONE", - "GTXE2_CHANNEL_TXPHALIGNEN", - "GTXE2_CHANNEL_TXPHDLYPD", - "GTXE2_CHANNEL_TXPHDLYRESET", - "GTXE2_CHANNEL_TXPHDLYTSTCLK", - "GTXE2_CHANNEL_TXPHINIT", - "GTXE2_CHANNEL_TXPHINITDONE", - "GTXE2_CHANNEL_TXPHOVRDEN", - "GTXE2_CHANNEL_TXPISOPD", - "GTXE2_CHANNEL_TXPMARESET", - "GTXE2_CHANNEL_TXPOLARITY", - "GTXE2_CHANNEL_TXPOSTCURSOR0", - "GTXE2_CHANNEL_TXPOSTCURSOR1", - "GTXE2_CHANNEL_TXPOSTCURSOR2", - "GTXE2_CHANNEL_TXPOSTCURSOR3", - "GTXE2_CHANNEL_TXPOSTCURSOR4", - "GTXE2_CHANNEL_TXPOSTCURSORINV", - "GTXE2_CHANNEL_TXPRBSFORCEERR", - "GTXE2_CHANNEL_TXPRBSSEL0", - "GTXE2_CHANNEL_TXPRBSSEL1", - "GTXE2_CHANNEL_TXPRBSSEL2", - "GTXE2_CHANNEL_TXPRECURSOR0", - "GTXE2_CHANNEL_TXPRECURSOR1", - "GTXE2_CHANNEL_TXPRECURSOR2", - "GTXE2_CHANNEL_TXPRECURSOR3", - "GTXE2_CHANNEL_TXPRECURSOR4", - "GTXE2_CHANNEL_TXPRECURSORINV", - "GTXE2_CHANNEL_TXP_PAD", - "GTXE2_CHANNEL_TXQPIBIASEN", - "GTXE2_CHANNEL_TXQPISENN", - "GTXE2_CHANNEL_TXQPISENP", - "GTXE2_CHANNEL_TXQPISTRONGPDOWN", - "GTXE2_CHANNEL_TXQPIWEAKPUP", - "GTXE2_CHANNEL_TXRATE0", - "GTXE2_CHANNEL_TXRATE1", - "GTXE2_CHANNEL_TXRATE2", - "GTXE2_CHANNEL_TXRATEDONE", - "GTXE2_CHANNEL_TXRESETDONE", - "GTXE2_CHANNEL_TXRUNDISP0", - "GTXE2_CHANNEL_TXRUNDISP1", - "GTXE2_CHANNEL_TXRUNDISP2", - "GTXE2_CHANNEL_TXRUNDISP3", - "GTXE2_CHANNEL_TXRUNDISP4", - "GTXE2_CHANNEL_TXRUNDISP5", - "GTXE2_CHANNEL_TXRUNDISP6", - "GTXE2_CHANNEL_TXRUNDISP7", - "GTXE2_CHANNEL_TXSEQUENCE0", - "GTXE2_CHANNEL_TXSEQUENCE1", - "GTXE2_CHANNEL_TXSEQUENCE2", - "GTXE2_CHANNEL_TXSEQUENCE3", - "GTXE2_CHANNEL_TXSEQUENCE4", - "GTXE2_CHANNEL_TXSEQUENCE5", - "GTXE2_CHANNEL_TXSEQUENCE6", - "GTXE2_CHANNEL_TXSTARTSEQ", - "GTXE2_CHANNEL_TXSWING", - "GTXE2_CHANNEL_TXSYSCLKSEL0", - "GTXE2_CHANNEL_TXSYSCLKSEL1", - "GTXE2_CHANNEL_TXUSERRDY", - "GTXE2_CHANNEL_TXUSRCLK", - "GTXE2_CHANNEL_TXUSRCLK2", - "GTXE2_CLK0_0", - "GTXE2_CLK0_1", - "GTXE2_CLK0_10", - "GTXE2_CLK0_2", - "GTXE2_CLK0_3", - "GTXE2_CLK0_4", - "GTXE2_CLK0_5", - "GTXE2_CLK0_6", - "GTXE2_CLK0_7", - "GTXE2_CLK0_8", - "GTXE2_CLK0_9", - "GTXE2_CLK1_0", - "GTXE2_CLK1_1", - "GTXE2_CLK1_10", - "GTXE2_CLK1_2", - "GTXE2_CLK1_3", - "GTXE2_CLK1_4", - "GTXE2_CLK1_5", - "GTXE2_CLK1_6", - "GTXE2_CLK1_7", - "GTXE2_CLK1_8", - "GTXE2_CLK1_9", - "GTXE2_CTRL0_0", - "GTXE2_CTRL0_1", - "GTXE2_CTRL0_10", - "GTXE2_CTRL0_2", - "GTXE2_CTRL0_3", - "GTXE2_CTRL0_4", - "GTXE2_CTRL0_5", - "GTXE2_CTRL0_6", - "GTXE2_CTRL0_7", - "GTXE2_CTRL0_8", - "GTXE2_CTRL0_9", - "GTXE2_CTRL1_0", - "GTXE2_CTRL1_1", - "GTXE2_CTRL1_10", - "GTXE2_CTRL1_2", - "GTXE2_CTRL1_3", - "GTXE2_CTRL1_4", - "GTXE2_CTRL1_5", - "GTXE2_CTRL1_6", - "GTXE2_CTRL1_7", - "GTXE2_CTRL1_8", - "GTXE2_CTRL1_9", - "GTXE2_FAN0_0", - "GTXE2_FAN0_1", - "GTXE2_FAN0_10", - "GTXE2_FAN0_2", - "GTXE2_FAN0_3", - "GTXE2_FAN0_4", - "GTXE2_FAN0_5", - "GTXE2_FAN0_6", - "GTXE2_FAN0_7", - "GTXE2_FAN0_8", - "GTXE2_FAN0_9", - "GTXE2_FAN1_0", - "GTXE2_FAN1_1", - "GTXE2_FAN1_10", - "GTXE2_FAN1_2", - "GTXE2_FAN1_3", - "GTXE2_FAN1_4", - "GTXE2_FAN1_5", - "GTXE2_FAN1_6", - "GTXE2_FAN1_7", - "GTXE2_FAN1_8", - "GTXE2_FAN1_9", - "GTXE2_FAN2_0", - "GTXE2_FAN2_1", - "GTXE2_FAN2_10", - "GTXE2_FAN2_2", - "GTXE2_FAN2_3", - "GTXE2_FAN2_4", - "GTXE2_FAN2_5", - "GTXE2_FAN2_6", - "GTXE2_FAN2_7", - "GTXE2_FAN2_8", - "GTXE2_FAN2_9", - "GTXE2_FAN3_0", - "GTXE2_FAN3_1", - "GTXE2_FAN3_10", - "GTXE2_FAN3_2", - "GTXE2_FAN3_3", - "GTXE2_FAN3_4", - "GTXE2_FAN3_5", - "GTXE2_FAN3_6", - "GTXE2_FAN3_7", - "GTXE2_FAN3_8", - "GTXE2_FAN3_9", - "GTXE2_FAN4_0", - "GTXE2_FAN4_1", - "GTXE2_FAN4_10", - "GTXE2_FAN4_2", - "GTXE2_FAN4_3", - "GTXE2_FAN4_4", - "GTXE2_FAN4_5", - "GTXE2_FAN4_6", - "GTXE2_FAN4_7", - "GTXE2_FAN4_8", - "GTXE2_FAN4_9", - "GTXE2_FAN5_0", - "GTXE2_FAN5_1", - "GTXE2_FAN5_10", - "GTXE2_FAN5_2", - "GTXE2_FAN5_3", - "GTXE2_FAN5_4", - "GTXE2_FAN5_5", - "GTXE2_FAN5_6", - "GTXE2_FAN5_7", - "GTXE2_FAN5_8", - "GTXE2_FAN5_9", - "GTXE2_FAN6_0", - "GTXE2_FAN6_1", - "GTXE2_FAN6_10", - "GTXE2_FAN6_2", - "GTXE2_FAN6_3", - "GTXE2_FAN6_4", - "GTXE2_FAN6_5", - "GTXE2_FAN6_6", - "GTXE2_FAN6_7", - "GTXE2_FAN6_8", - "GTXE2_FAN6_9", - "GTXE2_FAN7_0", - "GTXE2_FAN7_1", - "GTXE2_FAN7_10", - "GTXE2_FAN7_2", - "GTXE2_FAN7_3", - "GTXE2_FAN7_4", - "GTXE2_FAN7_5", - "GTXE2_FAN7_6", - "GTXE2_FAN7_7", - "GTXE2_FAN7_8", - "GTXE2_FAN7_9", - "GTXE2_IMUX0_0", - "GTXE2_IMUX0_1", - "GTXE2_IMUX0_10", - "GTXE2_IMUX0_2", - "GTXE2_IMUX0_3", - "GTXE2_IMUX0_4", - "GTXE2_IMUX0_5", - "GTXE2_IMUX0_6", - "GTXE2_IMUX0_7", - "GTXE2_IMUX0_8", - "GTXE2_IMUX0_9", - "GTXE2_IMUX10_0", - "GTXE2_IMUX10_1", - "GTXE2_IMUX10_10", - "GTXE2_IMUX10_2", - "GTXE2_IMUX10_3", - "GTXE2_IMUX10_4", - "GTXE2_IMUX10_5", - "GTXE2_IMUX10_6", - "GTXE2_IMUX10_7", - "GTXE2_IMUX10_8", - "GTXE2_IMUX10_9", - "GTXE2_IMUX11_0", - "GTXE2_IMUX11_1", - "GTXE2_IMUX11_10", - "GTXE2_IMUX11_2", - "GTXE2_IMUX11_3", - "GTXE2_IMUX11_4", - "GTXE2_IMUX11_5", - "GTXE2_IMUX11_6", - "GTXE2_IMUX11_7", - "GTXE2_IMUX11_8", - "GTXE2_IMUX11_9", - "GTXE2_IMUX12_0", - "GTXE2_IMUX12_1", - "GTXE2_IMUX12_10", - "GTXE2_IMUX12_2", - "GTXE2_IMUX12_3", - "GTXE2_IMUX12_4", - "GTXE2_IMUX12_5", - "GTXE2_IMUX12_6", - "GTXE2_IMUX12_7", - "GTXE2_IMUX12_8", - "GTXE2_IMUX12_9", - "GTXE2_IMUX13_0", - "GTXE2_IMUX13_1", - "GTXE2_IMUX13_10", - "GTXE2_IMUX13_2", - "GTXE2_IMUX13_3", - "GTXE2_IMUX13_4", - "GTXE2_IMUX13_5", - "GTXE2_IMUX13_6", - "GTXE2_IMUX13_7", - "GTXE2_IMUX13_8", - "GTXE2_IMUX13_9", - "GTXE2_IMUX14_0", - "GTXE2_IMUX14_1", - "GTXE2_IMUX14_10", - "GTXE2_IMUX14_2", - "GTXE2_IMUX14_3", - "GTXE2_IMUX14_4", - "GTXE2_IMUX14_5", - "GTXE2_IMUX14_6", - "GTXE2_IMUX14_7", - "GTXE2_IMUX14_8", - "GTXE2_IMUX14_9", - "GTXE2_IMUX15_0", - "GTXE2_IMUX15_1", - "GTXE2_IMUX15_10", - "GTXE2_IMUX15_2", - "GTXE2_IMUX15_3", - "GTXE2_IMUX15_4", - "GTXE2_IMUX15_5", - "GTXE2_IMUX15_6", - "GTXE2_IMUX15_7", - "GTXE2_IMUX15_8", - "GTXE2_IMUX15_9", - "GTXE2_IMUX16_0", - "GTXE2_IMUX16_1", - "GTXE2_IMUX16_10", - "GTXE2_IMUX16_2", - "GTXE2_IMUX16_3", - "GTXE2_IMUX16_4", - "GTXE2_IMUX16_5", - "GTXE2_IMUX16_6", - "GTXE2_IMUX16_7", - "GTXE2_IMUX16_8", - "GTXE2_IMUX16_9", - "GTXE2_IMUX17_0", - "GTXE2_IMUX17_1", - "GTXE2_IMUX17_10", - "GTXE2_IMUX17_2", - "GTXE2_IMUX17_3", - "GTXE2_IMUX17_4", - "GTXE2_IMUX17_5", - "GTXE2_IMUX17_6", - "GTXE2_IMUX17_7", - "GTXE2_IMUX17_8", - "GTXE2_IMUX17_9", - "GTXE2_IMUX18_0", - "GTXE2_IMUX18_1", - "GTXE2_IMUX18_10", - "GTXE2_IMUX18_2", - "GTXE2_IMUX18_3", - "GTXE2_IMUX18_4", - "GTXE2_IMUX18_5", - "GTXE2_IMUX18_6", - "GTXE2_IMUX18_7", - "GTXE2_IMUX18_8", - "GTXE2_IMUX18_9", - "GTXE2_IMUX19_0", - "GTXE2_IMUX19_1", - "GTXE2_IMUX19_10", - "GTXE2_IMUX19_2", - "GTXE2_IMUX19_3", - "GTXE2_IMUX19_4", - "GTXE2_IMUX19_5", - "GTXE2_IMUX19_6", - "GTXE2_IMUX19_7", - "GTXE2_IMUX19_8", - "GTXE2_IMUX19_9", - "GTXE2_IMUX1_0", - "GTXE2_IMUX1_1", - "GTXE2_IMUX1_10", - "GTXE2_IMUX1_2", - "GTXE2_IMUX1_3", - "GTXE2_IMUX1_4", - "GTXE2_IMUX1_5", - "GTXE2_IMUX1_6", - "GTXE2_IMUX1_7", - "GTXE2_IMUX1_8", - "GTXE2_IMUX1_9", - "GTXE2_IMUX20_0", - "GTXE2_IMUX20_1", - "GTXE2_IMUX20_10", - "GTXE2_IMUX20_2", - "GTXE2_IMUX20_3", - "GTXE2_IMUX20_4", - "GTXE2_IMUX20_5", - "GTXE2_IMUX20_6", - "GTXE2_IMUX20_7", - "GTXE2_IMUX20_8", - "GTXE2_IMUX20_9", - "GTXE2_IMUX21_0", - "GTXE2_IMUX21_1", - "GTXE2_IMUX21_10", - "GTXE2_IMUX21_2", - "GTXE2_IMUX21_3", - "GTXE2_IMUX21_4", - "GTXE2_IMUX21_5", - "GTXE2_IMUX21_6", - "GTXE2_IMUX21_7", - "GTXE2_IMUX21_8", - "GTXE2_IMUX21_9", - "GTXE2_IMUX22_0", - "GTXE2_IMUX22_1", - "GTXE2_IMUX22_10", - "GTXE2_IMUX22_2", - "GTXE2_IMUX22_3", - "GTXE2_IMUX22_4", - "GTXE2_IMUX22_5", - "GTXE2_IMUX22_6", - "GTXE2_IMUX22_7", - "GTXE2_IMUX22_8", - "GTXE2_IMUX22_9", - "GTXE2_IMUX23_0", - "GTXE2_IMUX23_1", - "GTXE2_IMUX23_10", - "GTXE2_IMUX23_2", - "GTXE2_IMUX23_3", - "GTXE2_IMUX23_4", - "GTXE2_IMUX23_5", - "GTXE2_IMUX23_6", - "GTXE2_IMUX23_7", - "GTXE2_IMUX23_8", - "GTXE2_IMUX23_9", - "GTXE2_IMUX24_0", - "GTXE2_IMUX24_1", - "GTXE2_IMUX24_10", - "GTXE2_IMUX24_2", - "GTXE2_IMUX24_3", - "GTXE2_IMUX24_4", - "GTXE2_IMUX24_5", - "GTXE2_IMUX24_6", - "GTXE2_IMUX24_7", - "GTXE2_IMUX24_8", - "GTXE2_IMUX24_9", - "GTXE2_IMUX25_0", - "GTXE2_IMUX25_1", - "GTXE2_IMUX25_10", - "GTXE2_IMUX25_2", - "GTXE2_IMUX25_3", - "GTXE2_IMUX25_4", - "GTXE2_IMUX25_5", - "GTXE2_IMUX25_6", - "GTXE2_IMUX25_7", - "GTXE2_IMUX25_8", - "GTXE2_IMUX25_9", - "GTXE2_IMUX26_0", - "GTXE2_IMUX26_1", - "GTXE2_IMUX26_10", - "GTXE2_IMUX26_2", - "GTXE2_IMUX26_3", - "GTXE2_IMUX26_4", - "GTXE2_IMUX26_5", - "GTXE2_IMUX26_6", - "GTXE2_IMUX26_7", - "GTXE2_IMUX26_8", - "GTXE2_IMUX26_9", - "GTXE2_IMUX27_0", - "GTXE2_IMUX27_1", - "GTXE2_IMUX27_10", - "GTXE2_IMUX27_2", - "GTXE2_IMUX27_3", - "GTXE2_IMUX27_4", - "GTXE2_IMUX27_5", - "GTXE2_IMUX27_6", - "GTXE2_IMUX27_7", - "GTXE2_IMUX27_8", - "GTXE2_IMUX27_9", - "GTXE2_IMUX28_0", - "GTXE2_IMUX28_1", - "GTXE2_IMUX28_10", - "GTXE2_IMUX28_2", - "GTXE2_IMUX28_3", - "GTXE2_IMUX28_4", - "GTXE2_IMUX28_5", - "GTXE2_IMUX28_6", - "GTXE2_IMUX28_7", - "GTXE2_IMUX28_8", - "GTXE2_IMUX28_9", - "GTXE2_IMUX29_0", - "GTXE2_IMUX29_1", - "GTXE2_IMUX29_10", - "GTXE2_IMUX29_2", - "GTXE2_IMUX29_3", - "GTXE2_IMUX29_4", - "GTXE2_IMUX29_5", - "GTXE2_IMUX29_6", - "GTXE2_IMUX29_7", - "GTXE2_IMUX29_8", - "GTXE2_IMUX29_9", - "GTXE2_IMUX2_0", - "GTXE2_IMUX2_1", - "GTXE2_IMUX2_10", - "GTXE2_IMUX2_2", - "GTXE2_IMUX2_3", - "GTXE2_IMUX2_4", - "GTXE2_IMUX2_5", - "GTXE2_IMUX2_6", - "GTXE2_IMUX2_7", - "GTXE2_IMUX2_8", - "GTXE2_IMUX2_9", - "GTXE2_IMUX30_0", - "GTXE2_IMUX30_1", - "GTXE2_IMUX30_10", - "GTXE2_IMUX30_2", - "GTXE2_IMUX30_3", - "GTXE2_IMUX30_4", - "GTXE2_IMUX30_5", - "GTXE2_IMUX30_6", - "GTXE2_IMUX30_7", - "GTXE2_IMUX30_8", - "GTXE2_IMUX30_9", - "GTXE2_IMUX31_0", - "GTXE2_IMUX31_1", - "GTXE2_IMUX31_10", - "GTXE2_IMUX31_2", - "GTXE2_IMUX31_3", - "GTXE2_IMUX31_4", - "GTXE2_IMUX31_5", - "GTXE2_IMUX31_6", - "GTXE2_IMUX31_7", - "GTXE2_IMUX31_8", - "GTXE2_IMUX31_9", - "GTXE2_IMUX32_0", - "GTXE2_IMUX32_1", - "GTXE2_IMUX32_10", - "GTXE2_IMUX32_2", - "GTXE2_IMUX32_3", - "GTXE2_IMUX32_4", - "GTXE2_IMUX32_5", - "GTXE2_IMUX32_6", - "GTXE2_IMUX32_7", - "GTXE2_IMUX32_8", - "GTXE2_IMUX32_9", - "GTXE2_IMUX33_0", - "GTXE2_IMUX33_1", - "GTXE2_IMUX33_10", - "GTXE2_IMUX33_2", - "GTXE2_IMUX33_3", - "GTXE2_IMUX33_4", - "GTXE2_IMUX33_5", - "GTXE2_IMUX33_6", - "GTXE2_IMUX33_7", - "GTXE2_IMUX33_8", - "GTXE2_IMUX33_9", - "GTXE2_IMUX34_0", - "GTXE2_IMUX34_1", - "GTXE2_IMUX34_10", - "GTXE2_IMUX34_2", - "GTXE2_IMUX34_3", - "GTXE2_IMUX34_4", - "GTXE2_IMUX34_5", - "GTXE2_IMUX34_6", - "GTXE2_IMUX34_7", - "GTXE2_IMUX34_8", - "GTXE2_IMUX34_9", - "GTXE2_IMUX35_0", - "GTXE2_IMUX35_1", - "GTXE2_IMUX35_10", - "GTXE2_IMUX35_2", - "GTXE2_IMUX35_3", - "GTXE2_IMUX35_4", - "GTXE2_IMUX35_5", - "GTXE2_IMUX35_6", - "GTXE2_IMUX35_7", - "GTXE2_IMUX35_8", - "GTXE2_IMUX35_9", - "GTXE2_IMUX36_0", - "GTXE2_IMUX36_1", - "GTXE2_IMUX36_10", - "GTXE2_IMUX36_2", - "GTXE2_IMUX36_3", - "GTXE2_IMUX36_4", - "GTXE2_IMUX36_5", - "GTXE2_IMUX36_6", - "GTXE2_IMUX36_7", - "GTXE2_IMUX36_8", - "GTXE2_IMUX36_9", - "GTXE2_IMUX37_0", - "GTXE2_IMUX37_1", - "GTXE2_IMUX37_10", - "GTXE2_IMUX37_2", - "GTXE2_IMUX37_3", - "GTXE2_IMUX37_4", - "GTXE2_IMUX37_5", - "GTXE2_IMUX37_6", - "GTXE2_IMUX37_7", - "GTXE2_IMUX37_8", - "GTXE2_IMUX37_9", - "GTXE2_IMUX38_0", - "GTXE2_IMUX38_1", - "GTXE2_IMUX38_10", - "GTXE2_IMUX38_2", - "GTXE2_IMUX38_3", - "GTXE2_IMUX38_4", - "GTXE2_IMUX38_5", - "GTXE2_IMUX38_6", - "GTXE2_IMUX38_7", - "GTXE2_IMUX38_8", - "GTXE2_IMUX38_9", - "GTXE2_IMUX39_0", - "GTXE2_IMUX39_1", - "GTXE2_IMUX39_10", - "GTXE2_IMUX39_2", - "GTXE2_IMUX39_3", - "GTXE2_IMUX39_4", - "GTXE2_IMUX39_5", - "GTXE2_IMUX39_6", - "GTXE2_IMUX39_7", - "GTXE2_IMUX39_8", - "GTXE2_IMUX39_9", - "GTXE2_IMUX3_0", - "GTXE2_IMUX3_1", - "GTXE2_IMUX3_10", - "GTXE2_IMUX3_2", - "GTXE2_IMUX3_3", - "GTXE2_IMUX3_4", - "GTXE2_IMUX3_5", - "GTXE2_IMUX3_6", - "GTXE2_IMUX3_7", - "GTXE2_IMUX3_8", - "GTXE2_IMUX3_9", - "GTXE2_IMUX40_0", - "GTXE2_IMUX40_1", - "GTXE2_IMUX40_10", - "GTXE2_IMUX40_2", - "GTXE2_IMUX40_3", - "GTXE2_IMUX40_4", - "GTXE2_IMUX40_5", - "GTXE2_IMUX40_6", - "GTXE2_IMUX40_7", - "GTXE2_IMUX40_8", - "GTXE2_IMUX40_9", - "GTXE2_IMUX41_0", - "GTXE2_IMUX41_1", - "GTXE2_IMUX41_10", - "GTXE2_IMUX41_2", - "GTXE2_IMUX41_3", - "GTXE2_IMUX41_4", - "GTXE2_IMUX41_5", - "GTXE2_IMUX41_6", - "GTXE2_IMUX41_7", - "GTXE2_IMUX41_8", - "GTXE2_IMUX41_9", - "GTXE2_IMUX42_0", - "GTXE2_IMUX42_1", - "GTXE2_IMUX42_10", - "GTXE2_IMUX42_2", - "GTXE2_IMUX42_3", - "GTXE2_IMUX42_4", - "GTXE2_IMUX42_5", - "GTXE2_IMUX42_6", - "GTXE2_IMUX42_7", - "GTXE2_IMUX42_8", - "GTXE2_IMUX42_9", - "GTXE2_IMUX43_0", - "GTXE2_IMUX43_1", - "GTXE2_IMUX43_10", - "GTXE2_IMUX43_2", - "GTXE2_IMUX43_3", - "GTXE2_IMUX43_4", - "GTXE2_IMUX43_5", - "GTXE2_IMUX43_6", - "GTXE2_IMUX43_7", - "GTXE2_IMUX43_8", - "GTXE2_IMUX43_9", - "GTXE2_IMUX44_0", - "GTXE2_IMUX44_1", - "GTXE2_IMUX44_10", - "GTXE2_IMUX44_2", - "GTXE2_IMUX44_3", - "GTXE2_IMUX44_4", - "GTXE2_IMUX44_5", - "GTXE2_IMUX44_6", - "GTXE2_IMUX44_7", - "GTXE2_IMUX44_8", - "GTXE2_IMUX44_9", - "GTXE2_IMUX45_0", - "GTXE2_IMUX45_1", - "GTXE2_IMUX45_10", - "GTXE2_IMUX45_2", - "GTXE2_IMUX45_3", - "GTXE2_IMUX45_4", - "GTXE2_IMUX45_5", - "GTXE2_IMUX45_6", - "GTXE2_IMUX45_7", - "GTXE2_IMUX45_8", - "GTXE2_IMUX45_9", - "GTXE2_IMUX46_0", - "GTXE2_IMUX46_1", - "GTXE2_IMUX46_10", - "GTXE2_IMUX46_2", - "GTXE2_IMUX46_3", - "GTXE2_IMUX46_4", - "GTXE2_IMUX46_5", - "GTXE2_IMUX46_6", - "GTXE2_IMUX46_7", - "GTXE2_IMUX46_8", - "GTXE2_IMUX46_9", - "GTXE2_IMUX47_0", - "GTXE2_IMUX47_1", - "GTXE2_IMUX47_10", - "GTXE2_IMUX47_2", - "GTXE2_IMUX47_3", - "GTXE2_IMUX47_4", - "GTXE2_IMUX47_5", - "GTXE2_IMUX47_6", - "GTXE2_IMUX47_7", - "GTXE2_IMUX47_8", - "GTXE2_IMUX47_9", - "GTXE2_IMUX4_0", - "GTXE2_IMUX4_1", - "GTXE2_IMUX4_10", - "GTXE2_IMUX4_2", - "GTXE2_IMUX4_3", - "GTXE2_IMUX4_4", - "GTXE2_IMUX4_5", - "GTXE2_IMUX4_6", - "GTXE2_IMUX4_7", - "GTXE2_IMUX4_8", - "GTXE2_IMUX4_9", - "GTXE2_IMUX5_0", - "GTXE2_IMUX5_1", - "GTXE2_IMUX5_10", - "GTXE2_IMUX5_2", - "GTXE2_IMUX5_3", - "GTXE2_IMUX5_4", - "GTXE2_IMUX5_5", - "GTXE2_IMUX5_6", - "GTXE2_IMUX5_7", - "GTXE2_IMUX5_8", - "GTXE2_IMUX5_9", - "GTXE2_IMUX6_0", - "GTXE2_IMUX6_1", - "GTXE2_IMUX6_10", - "GTXE2_IMUX6_2", - "GTXE2_IMUX6_3", - "GTXE2_IMUX6_4", - "GTXE2_IMUX6_5", - "GTXE2_IMUX6_6", - "GTXE2_IMUX6_7", - "GTXE2_IMUX6_8", - "GTXE2_IMUX6_9", - "GTXE2_IMUX7_0", - "GTXE2_IMUX7_1", - "GTXE2_IMUX7_10", - "GTXE2_IMUX7_2", - "GTXE2_IMUX7_3", - "GTXE2_IMUX7_4", - "GTXE2_IMUX7_5", - "GTXE2_IMUX7_6", - "GTXE2_IMUX7_7", - "GTXE2_IMUX7_8", - "GTXE2_IMUX7_9", - "GTXE2_IMUX8_0", - "GTXE2_IMUX8_1", - "GTXE2_IMUX8_10", - "GTXE2_IMUX8_2", - "GTXE2_IMUX8_3", - "GTXE2_IMUX8_4", - "GTXE2_IMUX8_5", - "GTXE2_IMUX8_6", - "GTXE2_IMUX8_7", - "GTXE2_IMUX8_8", - "GTXE2_IMUX8_9", - "GTXE2_IMUX9_0", - "GTXE2_IMUX9_1", - "GTXE2_IMUX9_10", - "GTXE2_IMUX9_2", - "GTXE2_IMUX9_3", - "GTXE2_IMUX9_4", - "GTXE2_IMUX9_5", - "GTXE2_IMUX9_6", - "GTXE2_IMUX9_7", - "GTXE2_IMUX9_8", - "GTXE2_IMUX9_9", - "GTXE2_LOGIC_OUTS_B0_0", - "GTXE2_LOGIC_OUTS_B0_1", - "GTXE2_LOGIC_OUTS_B0_10", - "GTXE2_LOGIC_OUTS_B0_2", - "GTXE2_LOGIC_OUTS_B0_3", - "GTXE2_LOGIC_OUTS_B0_4", - "GTXE2_LOGIC_OUTS_B0_5", - "GTXE2_LOGIC_OUTS_B0_6", - "GTXE2_LOGIC_OUTS_B0_7", - "GTXE2_LOGIC_OUTS_B0_8", - "GTXE2_LOGIC_OUTS_B0_9", - "GTXE2_LOGIC_OUTS_B10_0", - "GTXE2_LOGIC_OUTS_B10_1", - "GTXE2_LOGIC_OUTS_B10_10", - "GTXE2_LOGIC_OUTS_B10_2", - "GTXE2_LOGIC_OUTS_B10_3", - "GTXE2_LOGIC_OUTS_B10_4", - "GTXE2_LOGIC_OUTS_B10_5", - "GTXE2_LOGIC_OUTS_B10_6", - "GTXE2_LOGIC_OUTS_B10_7", - "GTXE2_LOGIC_OUTS_B10_8", - "GTXE2_LOGIC_OUTS_B10_9", - "GTXE2_LOGIC_OUTS_B11_0", - "GTXE2_LOGIC_OUTS_B11_1", - "GTXE2_LOGIC_OUTS_B11_10", - "GTXE2_LOGIC_OUTS_B11_2", - "GTXE2_LOGIC_OUTS_B11_3", - "GTXE2_LOGIC_OUTS_B11_4", - "GTXE2_LOGIC_OUTS_B11_5", - "GTXE2_LOGIC_OUTS_B11_6", - "GTXE2_LOGIC_OUTS_B11_7", - "GTXE2_LOGIC_OUTS_B11_8", - "GTXE2_LOGIC_OUTS_B11_9", - "GTXE2_LOGIC_OUTS_B12_0", - "GTXE2_LOGIC_OUTS_B12_1", - "GTXE2_LOGIC_OUTS_B12_10", - "GTXE2_LOGIC_OUTS_B12_2", - "GTXE2_LOGIC_OUTS_B12_3", - "GTXE2_LOGIC_OUTS_B12_4", - "GTXE2_LOGIC_OUTS_B12_5", - "GTXE2_LOGIC_OUTS_B12_6", - "GTXE2_LOGIC_OUTS_B12_7", - "GTXE2_LOGIC_OUTS_B12_8", - "GTXE2_LOGIC_OUTS_B12_9", - "GTXE2_LOGIC_OUTS_B13_0", - "GTXE2_LOGIC_OUTS_B13_1", - "GTXE2_LOGIC_OUTS_B13_10", - "GTXE2_LOGIC_OUTS_B13_2", - "GTXE2_LOGIC_OUTS_B13_3", - "GTXE2_LOGIC_OUTS_B13_4", - "GTXE2_LOGIC_OUTS_B13_5", - "GTXE2_LOGIC_OUTS_B13_6", - "GTXE2_LOGIC_OUTS_B13_7", - "GTXE2_LOGIC_OUTS_B13_8", - "GTXE2_LOGIC_OUTS_B13_9", - "GTXE2_LOGIC_OUTS_B14_0", - "GTXE2_LOGIC_OUTS_B14_1", - "GTXE2_LOGIC_OUTS_B14_10", - "GTXE2_LOGIC_OUTS_B14_2", - "GTXE2_LOGIC_OUTS_B14_3", - "GTXE2_LOGIC_OUTS_B14_4", - "GTXE2_LOGIC_OUTS_B14_5", - "GTXE2_LOGIC_OUTS_B14_6", - "GTXE2_LOGIC_OUTS_B14_7", - "GTXE2_LOGIC_OUTS_B14_8", - "GTXE2_LOGIC_OUTS_B14_9", - "GTXE2_LOGIC_OUTS_B15_0", - "GTXE2_LOGIC_OUTS_B15_1", - "GTXE2_LOGIC_OUTS_B15_10", - "GTXE2_LOGIC_OUTS_B15_2", - "GTXE2_LOGIC_OUTS_B15_3", - "GTXE2_LOGIC_OUTS_B15_4", - "GTXE2_LOGIC_OUTS_B15_5", - "GTXE2_LOGIC_OUTS_B15_6", - "GTXE2_LOGIC_OUTS_B15_7", - "GTXE2_LOGIC_OUTS_B15_8", - "GTXE2_LOGIC_OUTS_B15_9", - "GTXE2_LOGIC_OUTS_B16_0", - "GTXE2_LOGIC_OUTS_B16_1", - "GTXE2_LOGIC_OUTS_B16_10", - "GTXE2_LOGIC_OUTS_B16_2", - "GTXE2_LOGIC_OUTS_B16_3", - "GTXE2_LOGIC_OUTS_B16_4", - "GTXE2_LOGIC_OUTS_B16_5", - "GTXE2_LOGIC_OUTS_B16_6", - "GTXE2_LOGIC_OUTS_B16_7", - "GTXE2_LOGIC_OUTS_B16_8", - "GTXE2_LOGIC_OUTS_B16_9", - "GTXE2_LOGIC_OUTS_B17_0", - "GTXE2_LOGIC_OUTS_B17_1", - "GTXE2_LOGIC_OUTS_B17_10", - "GTXE2_LOGIC_OUTS_B17_2", - "GTXE2_LOGIC_OUTS_B17_3", - "GTXE2_LOGIC_OUTS_B17_4", - "GTXE2_LOGIC_OUTS_B17_5", - "GTXE2_LOGIC_OUTS_B17_6", - "GTXE2_LOGIC_OUTS_B17_7", - "GTXE2_LOGIC_OUTS_B17_8", - "GTXE2_LOGIC_OUTS_B17_9", - "GTXE2_LOGIC_OUTS_B18_0", - "GTXE2_LOGIC_OUTS_B18_1", - "GTXE2_LOGIC_OUTS_B18_10", - "GTXE2_LOGIC_OUTS_B18_2", - "GTXE2_LOGIC_OUTS_B18_3", - "GTXE2_LOGIC_OUTS_B18_4", - "GTXE2_LOGIC_OUTS_B18_5", - "GTXE2_LOGIC_OUTS_B18_6", - "GTXE2_LOGIC_OUTS_B18_7", - "GTXE2_LOGIC_OUTS_B18_8", - "GTXE2_LOGIC_OUTS_B18_9", - "GTXE2_LOGIC_OUTS_B19_0", - "GTXE2_LOGIC_OUTS_B19_1", - "GTXE2_LOGIC_OUTS_B19_10", - "GTXE2_LOGIC_OUTS_B19_2", - "GTXE2_LOGIC_OUTS_B19_3", - "GTXE2_LOGIC_OUTS_B19_4", - "GTXE2_LOGIC_OUTS_B19_5", - "GTXE2_LOGIC_OUTS_B19_6", - "GTXE2_LOGIC_OUTS_B19_7", - "GTXE2_LOGIC_OUTS_B19_8", - "GTXE2_LOGIC_OUTS_B19_9", - "GTXE2_LOGIC_OUTS_B1_0", - "GTXE2_LOGIC_OUTS_B1_1", - "GTXE2_LOGIC_OUTS_B1_10", - "GTXE2_LOGIC_OUTS_B1_2", - "GTXE2_LOGIC_OUTS_B1_3", - "GTXE2_LOGIC_OUTS_B1_4", - "GTXE2_LOGIC_OUTS_B1_5", - "GTXE2_LOGIC_OUTS_B1_6", - "GTXE2_LOGIC_OUTS_B1_7", - "GTXE2_LOGIC_OUTS_B1_8", - "GTXE2_LOGIC_OUTS_B1_9", - "GTXE2_LOGIC_OUTS_B20_0", - "GTXE2_LOGIC_OUTS_B20_1", - "GTXE2_LOGIC_OUTS_B20_10", - "GTXE2_LOGIC_OUTS_B20_2", - "GTXE2_LOGIC_OUTS_B20_3", - "GTXE2_LOGIC_OUTS_B20_4", - "GTXE2_LOGIC_OUTS_B20_5", - "GTXE2_LOGIC_OUTS_B20_6", - "GTXE2_LOGIC_OUTS_B20_7", - "GTXE2_LOGIC_OUTS_B20_8", - "GTXE2_LOGIC_OUTS_B20_9", - "GTXE2_LOGIC_OUTS_B21_0", - "GTXE2_LOGIC_OUTS_B21_1", - "GTXE2_LOGIC_OUTS_B21_10", - "GTXE2_LOGIC_OUTS_B21_2", - "GTXE2_LOGIC_OUTS_B21_3", - "GTXE2_LOGIC_OUTS_B21_4", - "GTXE2_LOGIC_OUTS_B21_5", - "GTXE2_LOGIC_OUTS_B21_6", - "GTXE2_LOGIC_OUTS_B21_7", - "GTXE2_LOGIC_OUTS_B21_8", - "GTXE2_LOGIC_OUTS_B21_9", - "GTXE2_LOGIC_OUTS_B22_0", - "GTXE2_LOGIC_OUTS_B22_1", - "GTXE2_LOGIC_OUTS_B22_10", - "GTXE2_LOGIC_OUTS_B22_2", - "GTXE2_LOGIC_OUTS_B22_3", - "GTXE2_LOGIC_OUTS_B22_4", - "GTXE2_LOGIC_OUTS_B22_5", - "GTXE2_LOGIC_OUTS_B22_6", - "GTXE2_LOGIC_OUTS_B22_7", - "GTXE2_LOGIC_OUTS_B22_8", - "GTXE2_LOGIC_OUTS_B22_9", - "GTXE2_LOGIC_OUTS_B23_0", - "GTXE2_LOGIC_OUTS_B23_1", - "GTXE2_LOGIC_OUTS_B23_10", - "GTXE2_LOGIC_OUTS_B23_2", - "GTXE2_LOGIC_OUTS_B23_3", - "GTXE2_LOGIC_OUTS_B23_4", - "GTXE2_LOGIC_OUTS_B23_5", - "GTXE2_LOGIC_OUTS_B23_6", - "GTXE2_LOGIC_OUTS_B23_7", - "GTXE2_LOGIC_OUTS_B23_8", - "GTXE2_LOGIC_OUTS_B23_9", - "GTXE2_LOGIC_OUTS_B2_0", - "GTXE2_LOGIC_OUTS_B2_1", - "GTXE2_LOGIC_OUTS_B2_10", - "GTXE2_LOGIC_OUTS_B2_2", - "GTXE2_LOGIC_OUTS_B2_3", - "GTXE2_LOGIC_OUTS_B2_4", - "GTXE2_LOGIC_OUTS_B2_5", - "GTXE2_LOGIC_OUTS_B2_6", - "GTXE2_LOGIC_OUTS_B2_7", - "GTXE2_LOGIC_OUTS_B2_8", - "GTXE2_LOGIC_OUTS_B2_9", - "GTXE2_LOGIC_OUTS_B3_0", - "GTXE2_LOGIC_OUTS_B3_1", - "GTXE2_LOGIC_OUTS_B3_10", - "GTXE2_LOGIC_OUTS_B3_2", - "GTXE2_LOGIC_OUTS_B3_3", - "GTXE2_LOGIC_OUTS_B3_4", - "GTXE2_LOGIC_OUTS_B3_5", - "GTXE2_LOGIC_OUTS_B3_6", - "GTXE2_LOGIC_OUTS_B3_7", - "GTXE2_LOGIC_OUTS_B3_8", - "GTXE2_LOGIC_OUTS_B3_9", - "GTXE2_LOGIC_OUTS_B4_0", - "GTXE2_LOGIC_OUTS_B4_1", - "GTXE2_LOGIC_OUTS_B4_10", - "GTXE2_LOGIC_OUTS_B4_2", - "GTXE2_LOGIC_OUTS_B4_3", - "GTXE2_LOGIC_OUTS_B4_4", - "GTXE2_LOGIC_OUTS_B4_5", - "GTXE2_LOGIC_OUTS_B4_6", - "GTXE2_LOGIC_OUTS_B4_7", - "GTXE2_LOGIC_OUTS_B4_8", - "GTXE2_LOGIC_OUTS_B4_9", - "GTXE2_LOGIC_OUTS_B5_0", - "GTXE2_LOGIC_OUTS_B5_1", - "GTXE2_LOGIC_OUTS_B5_10", - "GTXE2_LOGIC_OUTS_B5_2", - "GTXE2_LOGIC_OUTS_B5_3", - "GTXE2_LOGIC_OUTS_B5_4", - "GTXE2_LOGIC_OUTS_B5_5", - "GTXE2_LOGIC_OUTS_B5_6", - "GTXE2_LOGIC_OUTS_B5_7", - "GTXE2_LOGIC_OUTS_B5_8", - "GTXE2_LOGIC_OUTS_B5_9", - "GTXE2_LOGIC_OUTS_B6_0", - "GTXE2_LOGIC_OUTS_B6_1", - "GTXE2_LOGIC_OUTS_B6_10", - "GTXE2_LOGIC_OUTS_B6_2", - "GTXE2_LOGIC_OUTS_B6_3", - "GTXE2_LOGIC_OUTS_B6_4", - "GTXE2_LOGIC_OUTS_B6_5", - "GTXE2_LOGIC_OUTS_B6_6", - "GTXE2_LOGIC_OUTS_B6_7", - "GTXE2_LOGIC_OUTS_B6_8", - "GTXE2_LOGIC_OUTS_B6_9", - "GTXE2_LOGIC_OUTS_B7_0", - "GTXE2_LOGIC_OUTS_B7_1", - "GTXE2_LOGIC_OUTS_B7_10", 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"GTXE2_LOGIC_OUTS_B6_7": null, + "GTXE2_LOGIC_OUTS_B6_8": null, + "GTXE2_LOGIC_OUTS_B6_9": null, + "GTXE2_LOGIC_OUTS_B7_0": null, + "GTXE2_LOGIC_OUTS_B7_1": null, + "GTXE2_LOGIC_OUTS_B7_10": null, + "GTXE2_LOGIC_OUTS_B7_2": null, + "GTXE2_LOGIC_OUTS_B7_3": null, + "GTXE2_LOGIC_OUTS_B7_4": null, + "GTXE2_LOGIC_OUTS_B7_5": null, + "GTXE2_LOGIC_OUTS_B7_6": null, + "GTXE2_LOGIC_OUTS_B7_7": null, + "GTXE2_LOGIC_OUTS_B7_8": null, + "GTXE2_LOGIC_OUTS_B7_9": null, + "GTXE2_LOGIC_OUTS_B8_0": null, + "GTXE2_LOGIC_OUTS_B8_1": null, + "GTXE2_LOGIC_OUTS_B8_10": null, + "GTXE2_LOGIC_OUTS_B8_2": null, + "GTXE2_LOGIC_OUTS_B8_3": null, + "GTXE2_LOGIC_OUTS_B8_4": null, + "GTXE2_LOGIC_OUTS_B8_5": null, + "GTXE2_LOGIC_OUTS_B8_6": null, + "GTXE2_LOGIC_OUTS_B8_7": null, + "GTXE2_LOGIC_OUTS_B8_8": null, + "GTXE2_LOGIC_OUTS_B8_9": null, + "GTXE2_LOGIC_OUTS_B9_0": null, + "GTXE2_LOGIC_OUTS_B9_1": null, + "GTXE2_LOGIC_OUTS_B9_10": null, + "GTXE2_LOGIC_OUTS_B9_2": null, + "GTXE2_LOGIC_OUTS_B9_3": null, + "GTXE2_LOGIC_OUTS_B9_4": null, + "GTXE2_LOGIC_OUTS_B9_5": null, + "GTXE2_LOGIC_OUTS_B9_6": null, + "GTXE2_LOGIC_OUTS_B9_7": null, + "GTXE2_LOGIC_OUTS_B9_8": null, + "GTXE2_LOGIC_OUTS_B9_9": null + } } diff --git a/kintex7/tile_type_GTX_COMMON.json b/kintex7/tile_type_GTX_COMMON.json index 6820fe0..d8775e4 100644 --- a/kintex7/tile_type_GTX_COMMON.json +++ b/kintex7/tile_type_GTX_COMMON.json @@ -2,933 +2,2556 @@ "pips": { "GTX_COMMON.GTXE2_CLK0_2->GTXE2_COMMON_GTGREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_GTGREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK0_2" }, "GTX_COMMON.GTXE2_CLK1_1->GTXE2_COMMON_DRPCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_1" }, "GTX_COMMON.GTXE2_CLK1_3->GTXE2_COMMON_QPLLLOCKDETCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLLOCKDETCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CLK1_3" }, "GTX_COMMON.GTXE2_COMMON_DRPDO0->GTXE2_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO0" }, "GTX_COMMON.GTXE2_COMMON_DRPDO1->GTXE2_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO1" }, "GTX_COMMON.GTXE2_COMMON_DRPDO10->GTXE2_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO10" }, "GTX_COMMON.GTXE2_COMMON_DRPDO11->GTXE2_LOGIC_OUTS_B9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO11" }, "GTX_COMMON.GTXE2_COMMON_DRPDO12->GTXE2_LOGIC_OUTS_B10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO12" }, "GTX_COMMON.GTXE2_COMMON_DRPDO13->GTXE2_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO13" }, "GTX_COMMON.GTXE2_COMMON_DRPDO14->GTXE2_LOGIC_OUTS_B8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO14" }, "GTX_COMMON.GTXE2_COMMON_DRPDO15->GTXE2_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO15" }, "GTX_COMMON.GTXE2_COMMON_DRPDO2->GTXE2_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO2" }, "GTX_COMMON.GTXE2_COMMON_DRPDO3->GTXE2_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO3" }, "GTX_COMMON.GTXE2_COMMON_DRPDO4->GTXE2_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO4" }, "GTX_COMMON.GTXE2_COMMON_DRPDO5->GTXE2_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO5" }, "GTX_COMMON.GTXE2_COMMON_DRPDO6->GTXE2_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO6" }, "GTX_COMMON.GTXE2_COMMON_DRPDO7->GTXE2_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO7" }, "GTX_COMMON.GTXE2_COMMON_DRPDO8->GTXE2_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO8" }, "GTX_COMMON.GTXE2_COMMON_DRPDO9->GTXE2_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPDO9" }, "GTX_COMMON.GTXE2_COMMON_DRPRDY->GTXE2_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_DRPRDY" }, "GTX_COMMON.GTXE2_COMMON_GTQPLLOUTCLK->GTXE2_COMMON_QPLLOUTCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLOUTCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_GTQPLLOUTCLK" }, "GTX_COMMON.GTXE2_COMMON_GTQPLLOUTREFCLK->GTXE2_COMMON_QPLLOUTREFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLOUTREFCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_GTQPLLOUTREFCLK" }, "GTX_COMMON.GTXE2_COMMON_NORTHREFCLK0->>GTXE2_COMMON_GTNORTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_GTNORTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_NORTHREFCLK0" }, "GTX_COMMON.GTXE2_COMMON_NORTHREFCLK1->>GTXE2_COMMON_GTNORTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_GTNORTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_NORTHREFCLK1" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR0->GTXE2_LOGIC_OUTS_B19_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR0" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR1->GTXE2_LOGIC_OUTS_B23_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B23_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR1" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR2->GTXE2_LOGIC_OUTS_B17_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B17_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR2" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR3->GTXE2_LOGIC_OUTS_B21_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B21_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR3" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR4->GTXE2_LOGIC_OUTS_B22_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B22_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR4" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR5->GTXE2_LOGIC_OUTS_B18_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B18_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR5" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR6->GTXE2_LOGIC_OUTS_B20_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B20_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR6" }, "GTX_COMMON.GTXE2_COMMON_QPLLDMONITOR7->GTXE2_LOGIC_OUTS_B16_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B16_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLDMONITOR7" }, "GTX_COMMON.GTXE2_COMMON_QPLLFBCLKLOST->GTXE2_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLFBCLKLOST" }, "GTX_COMMON.GTXE2_COMMON_QPLLLOCK->GTXE2_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLLOCK" }, "GTX_COMMON.GTXE2_COMMON_QPLLREFCLKLOST->GTXE2_LOGIC_OUTS_B10_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B10_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_QPLLREFCLKLOST" }, "GTX_COMMON.GTXE2_COMMON_REFCLK0->>GTXE2_COMMON_GTREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_GTREFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_REFCLK0" }, "GTX_COMMON.GTXE2_COMMON_REFCLK1->>GTXE2_COMMON_GTREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_GTREFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_REFCLK1" }, "GTX_COMMON.GTXE2_COMMON_REFCLKOUTMONITOR->GTXE2_LOGIC_OUTS_B2_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_LOGIC_OUTS_B2_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_COMMON_REFCLKOUTMONITOR" }, "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_0->>GTXE2_COMMON_MGT_CLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_RXOUTCLK_0" }, "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_1->>GTXE2_COMMON_MGT_CLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_RXOUTCLK_1" }, "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_2->>GTXE2_COMMON_MGT_CLK6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_RXOUTCLK_2" }, "GTX_COMMON.GTXE2_COMMON_RXOUTCLK_3->>GTXE2_COMMON_MGT_CLK7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_RXOUTCLK_3" }, "GTX_COMMON.GTXE2_COMMON_SOUTHREFCLK0->>GTXE2_COMMON_GTSOUTHREFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_GTSOUTHREFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_SOUTHREFCLK0" }, "GTX_COMMON.GTXE2_COMMON_SOUTHREFCLK1->>GTXE2_COMMON_GTSOUTHREFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_GTSOUTHREFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_SOUTHREFCLK1" }, "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_0->>GTXE2_COMMON_MGT_CLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_TXOUTCLK_0" }, "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_1->>GTXE2_COMMON_MGT_CLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_TXOUTCLK_1" }, "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_2->>GTXE2_COMMON_MGT_CLK8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_TXOUTCLK_2" }, "GTX_COMMON.GTXE2_COMMON_TXOUTCLK_3->>GTXE2_COMMON_MGT_CLK9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "GTXE2_COMMON_TXOUTCLK_3" }, "GTX_COMMON.GTXE2_CTRL0_3->GTXE2_COMMON_QPLLRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL0_3" }, "GTX_COMMON.GTXE2_CTRL1_2->GTXE2_COMMON_QPLLOUTRESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLOUTRESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_CTRL1_2" }, "GTX_COMMON.GTXE2_IMUX16_0->GTXE2_COMMON_DRPDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_0" }, "GTX_COMMON.GTXE2_IMUX16_1->GTXE2_COMMON_DRPDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_1" }, "GTX_COMMON.GTXE2_IMUX16_2->GTXE2_COMMON_QPLLRSVD20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_2" }, "GTX_COMMON.GTXE2_IMUX16_3->GTXE2_COMMON_QPLLRSVD21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_3" }, "GTX_COMMON.GTXE2_IMUX16_4->GTXE2_COMMON_QPLLRSVD22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_4" }, "GTX_COMMON.GTXE2_IMUX16_5->GTXE2_COMMON_QPLLRSVD23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX16_5" }, "GTX_COMMON.GTXE2_IMUX17_0->GTXE2_COMMON_DRPDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_0" }, "GTX_COMMON.GTXE2_IMUX17_1->GTXE2_COMMON_DRPDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_1" }, "GTX_COMMON.GTXE2_IMUX17_5->GTXE2_COMMON_QPLLRSVD24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX17_5" }, "GTX_COMMON.GTXE2_IMUX18_0->GTXE2_COMMON_DRPDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_0" }, "GTX_COMMON.GTXE2_IMUX18_1->GTXE2_COMMON_DRPDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_1" }, "GTX_COMMON.GTXE2_IMUX18_2->GTXE2_COMMON_QPLLRSVD13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_2" }, "GTX_COMMON.GTXE2_IMUX18_3->GTXE2_COMMON_QPLLRSVD17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_3" }, "GTX_COMMON.GTXE2_IMUX18_4->GTXE2_COMMON_QPLLRSVD111": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD111", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_4" }, "GTX_COMMON.GTXE2_IMUX18_5->GTXE2_COMMON_QPLLRSVD115": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD115", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX18_5" }, "GTX_COMMON.GTXE2_IMUX19_0->GTXE2_COMMON_DRPDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_0" }, "GTX_COMMON.GTXE2_IMUX19_1->GTXE2_COMMON_DRPDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_1" }, "GTX_COMMON.GTXE2_IMUX19_2->GTXE2_COMMON_QPLLRSVD12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_2" }, "GTX_COMMON.GTXE2_IMUX19_3->GTXE2_COMMON_QPLLRSVD16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_3" }, "GTX_COMMON.GTXE2_IMUX19_4->GTXE2_COMMON_QPLLRSVD110": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD110", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_4" }, "GTX_COMMON.GTXE2_IMUX19_5->GTXE2_COMMON_QPLLRSVD114": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD114", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX19_5" }, "GTX_COMMON.GTXE2_IMUX20_0->GTXE2_COMMON_DRPDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_0" }, "GTX_COMMON.GTXE2_IMUX20_1->GTXE2_COMMON_DRPDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_1" }, "GTX_COMMON.GTXE2_IMUX20_2->GTXE2_COMMON_PMARSVD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_PMARSVD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_2" }, "GTX_COMMON.GTXE2_IMUX20_3->GTXE2_COMMON_PMARSVD5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_PMARSVD5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_3" }, "GTX_COMMON.GTXE2_IMUX20_4->GTXE2_COMMON_PMARSVD6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_PMARSVD6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_4" }, "GTX_COMMON.GTXE2_IMUX20_5->GTXE2_COMMON_PMARSVD7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_PMARSVD7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX20_5" }, "GTX_COMMON.GTXE2_IMUX21_0->GTXE2_COMMON_DRPDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_0" }, "GTX_COMMON.GTXE2_IMUX21_1->GTXE2_COMMON_DRPDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_1" }, "GTX_COMMON.GTXE2_IMUX21_2->GTXE2_COMMON_PMARSVD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_PMARSVD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_2" }, "GTX_COMMON.GTXE2_IMUX21_3->GTXE2_COMMON_PMARSVD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_PMARSVD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_3" }, "GTX_COMMON.GTXE2_IMUX21_4->GTXE2_COMMON_PMARSVD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_PMARSVD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_4" }, "GTX_COMMON.GTXE2_IMUX21_5->GTXE2_COMMON_PMARSVD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_PMARSVD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX21_5" }, "GTX_COMMON.GTXE2_IMUX22_0->GTXE2_COMMON_DRPDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_0" }, "GTX_COMMON.GTXE2_IMUX22_1->GTXE2_COMMON_DRPDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_1" }, "GTX_COMMON.GTXE2_IMUX22_2->GTXE2_COMMON_QPLLRSVD11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_2" }, "GTX_COMMON.GTXE2_IMUX22_3->GTXE2_COMMON_QPLLRSVD15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_3" }, "GTX_COMMON.GTXE2_IMUX22_4->GTXE2_COMMON_QPLLRSVD19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_4" }, "GTX_COMMON.GTXE2_IMUX22_5->GTXE2_COMMON_QPLLRSVD113": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD113", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX22_5" }, "GTX_COMMON.GTXE2_IMUX23_0->GTXE2_COMMON_DRPDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_0" }, "GTX_COMMON.GTXE2_IMUX23_1->GTXE2_COMMON_DRPDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_1" }, "GTX_COMMON.GTXE2_IMUX23_2->GTXE2_COMMON_QPLLRSVD10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_2" }, "GTX_COMMON.GTXE2_IMUX23_3->GTXE2_COMMON_QPLLRSVD14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_3" }, "GTX_COMMON.GTXE2_IMUX23_4->GTXE2_COMMON_QPLLRSVD18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_4" }, "GTX_COMMON.GTXE2_IMUX23_5->GTXE2_COMMON_QPLLRSVD112": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLRSVD112", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX23_5" }, "GTX_COMMON.GTXE2_IMUX24_2->GTXE2_COMMON_DRPADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_2" }, "GTX_COMMON.GTXE2_IMUX24_3->GTXE2_COMMON_QPLLLOCKEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLLOCKEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX24_3" }, "GTX_COMMON.GTXE2_IMUX25_2->GTXE2_COMMON_DRPADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX25_2" }, "GTX_COMMON.GTXE2_IMUX26_2->GTXE2_COMMON_DRPADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_2" }, "GTX_COMMON.GTXE2_IMUX26_3->IBUFDS_GTE2_0_CEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_0_CEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_3" }, "GTX_COMMON.GTXE2_IMUX26_4->GTXE2_COMMON_BGRCALOVRD3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_4" }, "GTX_COMMON.GTXE2_IMUX26_5->GTXE2_COMMON_BGPDB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_BGPDB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX26_5" }, "GTX_COMMON.GTXE2_IMUX27_2->GTXE2_COMMON_DRPADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_2" }, "GTX_COMMON.GTXE2_IMUX27_3->GTXE2_COMMON_QPLLREFCLKSEL2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLREFCLKSEL2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_3" }, "GTX_COMMON.GTXE2_IMUX27_4->GTXE2_COMMON_BGRCALOVRD2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_4" }, "GTX_COMMON.GTXE2_IMUX27_5->GTXE2_COMMON_BGMONITORENB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_BGMONITORENB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX27_5" }, "GTX_COMMON.GTXE2_IMUX28_2->GTXE2_COMMON_DRPADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_2" }, "GTX_COMMON.GTXE2_IMUX28_3->GTXE2_COMMON_QPLLPD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLPD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_3" }, "GTX_COMMON.GTXE2_IMUX28_4->GTXE2_COMMON_RCALENB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_RCALENB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX28_4" }, "GTX_COMMON.GTXE2_IMUX29_0->GTXE2_COMMON_DRPWE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPWE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_0" }, "GTX_COMMON.GTXE2_IMUX29_1->GTXE2_COMMON_DRPEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_1" }, "GTX_COMMON.GTXE2_IMUX29_2->GTXE2_COMMON_DRPADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_2" }, "GTX_COMMON.GTXE2_IMUX29_3->IBUFDS_GTE2_1_CEB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_1_CEB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_3" }, "GTX_COMMON.GTXE2_IMUX29_4->GTXE2_COMMON_BGRCALOVRD4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX29_4" }, "GTX_COMMON.GTXE2_IMUX30_2->GTXE2_COMMON_DRPADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_2" }, "GTX_COMMON.GTXE2_IMUX30_3->GTXE2_COMMON_QPLLREFCLKSEL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLREFCLKSEL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_3" }, "GTX_COMMON.GTXE2_IMUX30_4->GTXE2_COMMON_BGRCALOVRD1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_4" }, "GTX_COMMON.GTXE2_IMUX30_5->GTXE2_COMMON_BGBYPASSB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_BGBYPASSB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX30_5" }, "GTX_COMMON.GTXE2_IMUX31_2->GTXE2_COMMON_DRPADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_DRPADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_2" }, "GTX_COMMON.GTXE2_IMUX31_3->GTXE2_COMMON_QPLLREFCLKSEL0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_QPLLREFCLKSEL0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_3" }, "GTX_COMMON.GTXE2_IMUX31_4->GTXE2_COMMON_BGRCALOVRD0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_BGRCALOVRD0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "GTXE2_IMUX31_4" }, "GTX_COMMON.IBUFDS_GTE2_0_I->IBUFDS_GTE2_0_I_SEG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_0_I_SEG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_0_I" }, "GTX_COMMON.IBUFDS_GTE2_0_IB->IBUFDS_GTE2_0_IB_SEG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_0_IB_SEG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_0_IB" }, "GTX_COMMON.IBUFDS_GTE2_0_MGTCLKOUT->>GTXE2_COMMON_MGT_CLK4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "IBUFDS_GTE2_0_MGTCLKOUT" }, "GTX_COMMON.IBUFDS_GTE2_0_O->GTXE2_COMMON_REFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_REFCLK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_0_O" }, "GTX_COMMON.IBUFDS_GTE2_0_O->IBUFDS_GTE2_0_MGTCLKOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_0_MGTCLKOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_0_O" }, "GTX_COMMON.IBUFDS_GTE2_0_ODIV2->IBUFDS_GTE2_0_MGTCLKOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_0_MGTCLKOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_0_ODIV2" }, "GTX_COMMON.IBUFDS_GTE2_1_I->IBUFDS_GTE2_1_I_SEG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_1_I_SEG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_1_I" }, "GTX_COMMON.IBUFDS_GTE2_1_IB->IBUFDS_GTE2_1_IB_SEG": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_1_IB_SEG", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_1_IB" }, "GTX_COMMON.IBUFDS_GTE2_1_MGTCLKOUT->>GTXE2_COMMON_MGT_CLK5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "GTXE2_COMMON_MGT_CLK5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "IBUFDS_GTE2_1_MGTCLKOUT" }, "GTX_COMMON.IBUFDS_GTE2_1_O->GTXE2_COMMON_REFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "GTXE2_COMMON_REFCLK1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_1_O" }, "GTX_COMMON.IBUFDS_GTE2_1_O->IBUFDS_GTE2_1_MGTCLKOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_1_MGTCLKOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_1_O" }, "GTX_COMMON.IBUFDS_GTE2_1_ODIV2->IBUFDS_GTE2_1_MGTCLKOUT": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IBUFDS_GTE2_1_MGTCLKOUT", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IBUFDS_GTE2_1_ODIV2" } }, @@ -937,134 +2560,1286 @@ "name": "X0Y0", "prefix": "GTXE2_COMMON", "site_pins": { - "BGBYPASSB": "GTXE2_COMMON_BGBYPASSB", - "BGMONITORENB": "GTXE2_COMMON_BGMONITORENB", - "BGPDB": "GTXE2_COMMON_BGPDB", - "BGRCALOVRD0": "GTXE2_COMMON_BGRCALOVRD0", - "BGRCALOVRD1": "GTXE2_COMMON_BGRCALOVRD1", - "BGRCALOVRD2": "GTXE2_COMMON_BGRCALOVRD2", - "BGRCALOVRD3": "GTXE2_COMMON_BGRCALOVRD3", - "BGRCALOVRD4": "GTXE2_COMMON_BGRCALOVRD4", - "DRPADDR0": "GTXE2_COMMON_DRPADDR0", - "DRPADDR1": "GTXE2_COMMON_DRPADDR1", - "DRPADDR2": "GTXE2_COMMON_DRPADDR2", - "DRPADDR3": "GTXE2_COMMON_DRPADDR3", - "DRPADDR4": "GTXE2_COMMON_DRPADDR4", - "DRPADDR5": "GTXE2_COMMON_DRPADDR5", - "DRPADDR6": "GTXE2_COMMON_DRPADDR6", - "DRPADDR7": "GTXE2_COMMON_DRPADDR7", - "DRPCLK": "GTXE2_COMMON_DRPCLK", - "DRPDI0": "GTXE2_COMMON_DRPDI0", - "DRPDI1": "GTXE2_COMMON_DRPDI1", - "DRPDI10": "GTXE2_COMMON_DRPDI10", - "DRPDI11": "GTXE2_COMMON_DRPDI11", - "DRPDI12": "GTXE2_COMMON_DRPDI12", - "DRPDI13": "GTXE2_COMMON_DRPDI13", - "DRPDI14": "GTXE2_COMMON_DRPDI14", - "DRPDI15": "GTXE2_COMMON_DRPDI15", - "DRPDI2": "GTXE2_COMMON_DRPDI2", - "DRPDI3": "GTXE2_COMMON_DRPDI3", - "DRPDI4": "GTXE2_COMMON_DRPDI4", - "DRPDI5": "GTXE2_COMMON_DRPDI5", - "DRPDI6": "GTXE2_COMMON_DRPDI6", - "DRPDI7": "GTXE2_COMMON_DRPDI7", - "DRPDI8": "GTXE2_COMMON_DRPDI8", - "DRPDI9": "GTXE2_COMMON_DRPDI9", - "DRPDO0": "GTXE2_COMMON_DRPDO0", - "DRPDO1": "GTXE2_COMMON_DRPDO1", - "DRPDO10": "GTXE2_COMMON_DRPDO10", - "DRPDO11": "GTXE2_COMMON_DRPDO11", - "DRPDO12": "GTXE2_COMMON_DRPDO12", - "DRPDO13": "GTXE2_COMMON_DRPDO13", - "DRPDO14": "GTXE2_COMMON_DRPDO14", - "DRPDO15": "GTXE2_COMMON_DRPDO15", - "DRPDO2": "GTXE2_COMMON_DRPDO2", - "DRPDO3": "GTXE2_COMMON_DRPDO3", - "DRPDO4": "GTXE2_COMMON_DRPDO4", - "DRPDO5": "GTXE2_COMMON_DRPDO5", - "DRPDO6": "GTXE2_COMMON_DRPDO6", - "DRPDO7": "GTXE2_COMMON_DRPDO7", - "DRPDO8": "GTXE2_COMMON_DRPDO8", - "DRPDO9": "GTXE2_COMMON_DRPDO9", - "DRPEN": "GTXE2_COMMON_DRPEN", - "DRPRDY": "GTXE2_COMMON_DRPRDY", - "DRPWE": "GTXE2_COMMON_DRPWE", - "GTGREFCLK": "GTXE2_COMMON_GTGREFCLK", - "GTNORTHREFCLK0": "GTXE2_COMMON_GTNORTHREFCLK0", - "GTNORTHREFCLK1": "GTXE2_COMMON_GTNORTHREFCLK1", - "GTREFCLK0": "GTXE2_COMMON_GTREFCLK0", - "GTREFCLK1": "GTXE2_COMMON_GTREFCLK1", - "GTSOUTHREFCLK0": "GTXE2_COMMON_GTSOUTHREFCLK0", - "GTSOUTHREFCLK1": "GTXE2_COMMON_GTSOUTHREFCLK1", - "PMARSVD0": "GTXE2_COMMON_PMARSVD0", - "PMARSVD1": "GTXE2_COMMON_PMARSVD1", - "PMARSVD2": "GTXE2_COMMON_PMARSVD2", - "PMARSVD3": "GTXE2_COMMON_PMARSVD3", - "PMARSVD4": "GTXE2_COMMON_PMARSVD4", - "PMARSVD5": "GTXE2_COMMON_PMARSVD5", - "PMARSVD6": "GTXE2_COMMON_PMARSVD6", - "PMARSVD7": "GTXE2_COMMON_PMARSVD7", - "PMASCANCLK0": "GTXE2_COMMON_PMASCANCLK0", - "PMASCANCLK1": "GTXE2_COMMON_PMASCANCLK1", - "PMASCANENB": "GTXE2_COMMON_PMASCANENB", - "PMASCANIN0": "GTXE2_COMMON_PMASCANIN0", - "PMASCANIN1": "GTXE2_COMMON_PMASCANIN1", - "PMASCANIN2": "GTXE2_COMMON_PMASCANIN2", - "PMASCANIN3": "GTXE2_COMMON_PMASCANIN3", - "PMASCANIN4": "GTXE2_COMMON_PMASCANIN4", - "PMASCANOUT0": "GTXE2_COMMON_PMASCANOUT0", - "PMASCANOUT1": "GTXE2_COMMON_PMASCANOUT1", - "PMASCANOUT2": "GTXE2_COMMON_PMASCANOUT2", - "PMASCANOUT3": "GTXE2_COMMON_PMASCANOUT3", - "PMASCANOUT4": "GTXE2_COMMON_PMASCANOUT4", - "QDPMASCANMODEB": "GTXE2_COMMON_QDPMASCANMODEB", - "QDPMASCANRSTEN": "GTXE2_COMMON_QDPMASCANRSTEN", - "QPLLCLKSPARE0": "GTXE2_COMMON_QPLLCLKSPARE0", - "QPLLCLKSPARE1": "GTXE2_COMMON_QPLLCLKSPARE1", - "QPLLDMONITOR0": "GTXE2_COMMON_QPLLDMONITOR0", - "QPLLDMONITOR1": "GTXE2_COMMON_QPLLDMONITOR1", - "QPLLDMONITOR2": "GTXE2_COMMON_QPLLDMONITOR2", - "QPLLDMONITOR3": "GTXE2_COMMON_QPLLDMONITOR3", - "QPLLDMONITOR4": "GTXE2_COMMON_QPLLDMONITOR4", - "QPLLDMONITOR5": "GTXE2_COMMON_QPLLDMONITOR5", - "QPLLDMONITOR6": "GTXE2_COMMON_QPLLDMONITOR6", - "QPLLDMONITOR7": "GTXE2_COMMON_QPLLDMONITOR7", - "QPLLFBCLKLOST": "GTXE2_COMMON_QPLLFBCLKLOST", - "QPLLLOCK": "GTXE2_COMMON_QPLLLOCK", - "QPLLLOCKDETCLK": "GTXE2_COMMON_QPLLLOCKDETCLK", - "QPLLLOCKEN": "GTXE2_COMMON_QPLLLOCKEN", - "QPLLOUTCLK": "GTXE2_COMMON_GTQPLLOUTCLK", - "QPLLOUTREFCLK": "GTXE2_COMMON_GTQPLLOUTREFCLK", - "QPLLOUTRESET": "GTXE2_COMMON_QPLLOUTRESET", - "QPLLPD": "GTXE2_COMMON_QPLLPD", - "QPLLREFCLKLOST": "GTXE2_COMMON_QPLLREFCLKLOST", - "QPLLREFCLKSEL0": "GTXE2_COMMON_QPLLREFCLKSEL0", - "QPLLREFCLKSEL1": "GTXE2_COMMON_QPLLREFCLKSEL1", - "QPLLREFCLKSEL2": "GTXE2_COMMON_QPLLREFCLKSEL2", - "QPLLRESET": "GTXE2_COMMON_QPLLRESET", - "QPLLRSVD10": "GTXE2_COMMON_QPLLRSVD10", - "QPLLRSVD11": "GTXE2_COMMON_QPLLRSVD11", - "QPLLRSVD110": "GTXE2_COMMON_QPLLRSVD110", - "QPLLRSVD111": "GTXE2_COMMON_QPLLRSVD111", - "QPLLRSVD112": "GTXE2_COMMON_QPLLRSVD112", - "QPLLRSVD113": "GTXE2_COMMON_QPLLRSVD113", - "QPLLRSVD114": "GTXE2_COMMON_QPLLRSVD114", - "QPLLRSVD115": "GTXE2_COMMON_QPLLRSVD115", - "QPLLRSVD12": "GTXE2_COMMON_QPLLRSVD12", - "QPLLRSVD13": "GTXE2_COMMON_QPLLRSVD13", - "QPLLRSVD14": "GTXE2_COMMON_QPLLRSVD14", - "QPLLRSVD15": "GTXE2_COMMON_QPLLRSVD15", - "QPLLRSVD16": "GTXE2_COMMON_QPLLRSVD16", - "QPLLRSVD17": "GTXE2_COMMON_QPLLRSVD17", - "QPLLRSVD18": "GTXE2_COMMON_QPLLRSVD18", - "QPLLRSVD19": "GTXE2_COMMON_QPLLRSVD19", - "QPLLRSVD20": "GTXE2_COMMON_QPLLRSVD20", - "QPLLRSVD21": "GTXE2_COMMON_QPLLRSVD21", - "QPLLRSVD22": "GTXE2_COMMON_QPLLRSVD22", - "QPLLRSVD23": "GTXE2_COMMON_QPLLRSVD23", - "QPLLRSVD24": "GTXE2_COMMON_QPLLRSVD24", - "RCALENB": "GTXE2_COMMON_RCALENB", - "REFCLKOUTMONITOR": "GTXE2_COMMON_REFCLKOUTMONITOR" + "BGBYPASSB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_BGBYPASSB" + }, + "BGMONITORENB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_BGMONITORENB" + }, + "BGPDB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_BGPDB" + }, + "BGRCALOVRD0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + 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"QPLLDMONITOR1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLDMONITOR1" + }, + "QPLLDMONITOR2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLDMONITOR2" + }, + "QPLLDMONITOR3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLDMONITOR3" + }, + "QPLLDMONITOR4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLDMONITOR4" + }, + "QPLLDMONITOR5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLDMONITOR5" + }, + "QPLLDMONITOR6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLDMONITOR6" + }, + "QPLLDMONITOR7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLDMONITOR7" + }, + "QPLLFBCLKLOST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLFBCLKLOST" + }, + "QPLLLOCK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLLOCK" + }, + "QPLLLOCKDETCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLLOCKDETCLK" + }, + "QPLLLOCKEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLLOCKEN" + }, + "QPLLOUTCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_GTQPLLOUTCLK" + }, + "QPLLOUTREFCLK": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_GTQPLLOUTREFCLK" + }, + "QPLLOUTRESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLOUTRESET" + }, + "QPLLPD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLPD" + }, + "QPLLREFCLKLOST": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_QPLLREFCLKLOST" + }, + "QPLLREFCLKSEL0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLREFCLKSEL0" + }, + "QPLLREFCLKSEL1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLREFCLKSEL1" + }, + "QPLLREFCLKSEL2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLREFCLKSEL2" + }, + "QPLLRESET": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRESET" + }, + "QPLLRSVD10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD10" + }, + "QPLLRSVD11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD11" + }, + "QPLLRSVD110": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD110" + }, + "QPLLRSVD111": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD111" + }, + "QPLLRSVD112": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD112" + }, + "QPLLRSVD113": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD113" + }, + "QPLLRSVD114": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD114" + }, + "QPLLRSVD115": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD115" + }, + "QPLLRSVD12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD12" + }, + "QPLLRSVD13": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD13" + }, + "QPLLRSVD14": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD14" + }, + "QPLLRSVD15": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD15" + }, + "QPLLRSVD16": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD16" + }, + "QPLLRSVD17": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD17" + }, + "QPLLRSVD18": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD18" + }, + "QPLLRSVD19": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD19" + }, + "QPLLRSVD20": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD20" + }, + "QPLLRSVD21": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD21" + }, + "QPLLRSVD22": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD22" + }, + "QPLLRSVD23": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD23" + }, + "QPLLRSVD24": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_QPLLRSVD24" + }, + "RCALENB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "GTXE2_COMMON_RCALENB" + }, + "REFCLKOUTMONITOR": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GTXE2_COMMON_REFCLKOUTMONITOR" + } }, "type": "GTXE2_COMMON", "x_coord": 0, @@ -1074,7 +3849,16 @@ "name": "X0Y1", "prefix": "IPAD", "site_pins": { - "O": "IBUFDS_GTE2_0_IB" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IBUFDS_GTE2_0_IB" + } }, "type": "IPAD", "x_coord": 0, @@ -1084,7 +3868,16 @@ "name": "X0Y0", "prefix": "IPAD", "site_pins": { - "O": "IBUFDS_GTE2_0_I" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IBUFDS_GTE2_0_I" + } }, "type": "IPAD", "x_coord": 0, @@ -1094,7 +3887,16 @@ "name": "X0Y3", "prefix": "IPAD", "site_pins": { - "O": "IBUFDS_GTE2_1_IB" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IBUFDS_GTE2_1_IB" + } }, "type": "IPAD", "x_coord": 0, @@ -1104,7 +3906,16 @@ "name": "X0Y2", "prefix": "IPAD", "site_pins": { - "O": "IBUFDS_GTE2_1_I" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IBUFDS_GTE2_1_I" + } }, "type": "IPAD", "x_coord": 0, @@ -1114,12 +3925,66 @@ "name": "X0Y0", "prefix": "IBUFDS_GTE2", "site_pins": { - "CEB": "IBUFDS_GTE2_0_CEB", - "CLKTESTSIG": "IBUFDS_GTE2_0_CLKTESTSIG", - "I": "IBUFDS_GTE2_0_I_SEG", - "IB": "IBUFDS_GTE2_0_IB_SEG", - "O": "IBUFDS_GTE2_0_O", - "ODIV2": "IBUFDS_GTE2_0_ODIV2" + "CEB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IBUFDS_GTE2_0_CEB" + }, + "CLKTESTSIG": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IBUFDS_GTE2_0_CLKTESTSIG" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IBUFDS_GTE2_0_I_SEG" + }, + "IB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IBUFDS_GTE2_0_IB_SEG" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IBUFDS_GTE2_0_O" + }, + "ODIV2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IBUFDS_GTE2_0_ODIV2" + } }, "type": "IBUFDS_GTE2", "x_coord": 0, @@ -1129,12 +3994,66 @@ "name": "X0Y1", "prefix": "IBUFDS_GTE2", "site_pins": { - "CEB": "IBUFDS_GTE2_1_CEB", - "CLKTESTSIG": "IBUFDS_GTE2_1_CLKTESTSIG", - "I": "IBUFDS_GTE2_1_I_SEG", - "IB": "IBUFDS_GTE2_1_IB_SEG", - "O": "IBUFDS_GTE2_1_O", - "ODIV2": "IBUFDS_GTE2_1_ODIV2" + "CEB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IBUFDS_GTE2_1_CEB" + }, + "CLKTESTSIG": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IBUFDS_GTE2_1_CLKTESTSIG" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IBUFDS_GTE2_1_I_SEG" + }, + "IB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IBUFDS_GTE2_1_IB_SEG" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IBUFDS_GTE2_1_O" + }, + "ODIV2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IBUFDS_GTE2_1_ODIV2" + } }, "type": "IBUFDS_GTE2", "x_coord": 0, @@ -1142,732 +4061,2286 @@ } ], "tile_type": "GTX_COMMON", - "wires": [ - "GTXE2_BYP0_0", - "GTXE2_BYP0_1", - "GTXE2_BYP0_2", - "GTXE2_BYP0_3", - "GTXE2_BYP0_4", - "GTXE2_BYP0_5", - "GTXE2_BYP1_0", - "GTXE2_BYP1_1", - "GTXE2_BYP1_2", - "GTXE2_BYP1_3", - "GTXE2_BYP1_4", - "GTXE2_BYP1_5", - "GTXE2_BYP2_0", - "GTXE2_BYP2_1", - "GTXE2_BYP2_2", - "GTXE2_BYP2_3", - "GTXE2_BYP2_4", - "GTXE2_BYP2_5", - "GTXE2_BYP3_0", - "GTXE2_BYP3_1", - "GTXE2_BYP3_2", - "GTXE2_BYP3_3", - "GTXE2_BYP3_4", - "GTXE2_BYP3_5", - "GTXE2_BYP4_0", - "GTXE2_BYP4_1", - "GTXE2_BYP4_2", - "GTXE2_BYP4_3", - "GTXE2_BYP4_4", - "GTXE2_BYP4_5", - "GTXE2_BYP5_0", - "GTXE2_BYP5_1", - "GTXE2_BYP5_2", - "GTXE2_BYP5_3", - "GTXE2_BYP5_4", - "GTXE2_BYP5_5", - "GTXE2_BYP6_0", - "GTXE2_BYP6_1", - "GTXE2_BYP6_2", - "GTXE2_BYP6_3", - "GTXE2_BYP6_4", - "GTXE2_BYP6_5", - "GTXE2_BYP7_0", - "GTXE2_BYP7_1", - "GTXE2_BYP7_2", - "GTXE2_BYP7_3", - "GTXE2_BYP7_4", - "GTXE2_BYP7_5", - "GTXE2_CLK0_0", - "GTXE2_CLK0_1", - "GTXE2_CLK0_2", - "GTXE2_CLK0_3", - "GTXE2_CLK0_4", - "GTXE2_CLK0_5", - "GTXE2_CLK1_0", - "GTXE2_CLK1_1", - "GTXE2_CLK1_2", - "GTXE2_CLK1_3", - "GTXE2_CLK1_4", - "GTXE2_CLK1_5", - "GTXE2_COMMON_BGBYPASSB", - "GTXE2_COMMON_BGMONITORENB", - "GTXE2_COMMON_BGPDB", - "GTXE2_COMMON_BGRCALOVRD0", - "GTXE2_COMMON_BGRCALOVRD1", - "GTXE2_COMMON_BGRCALOVRD2", - "GTXE2_COMMON_BGRCALOVRD3", - "GTXE2_COMMON_BGRCALOVRD4", - "GTXE2_COMMON_DRPADDR0", - "GTXE2_COMMON_DRPADDR1", - "GTXE2_COMMON_DRPADDR2", - "GTXE2_COMMON_DRPADDR3", - "GTXE2_COMMON_DRPADDR4", - "GTXE2_COMMON_DRPADDR5", - "GTXE2_COMMON_DRPADDR6", - "GTXE2_COMMON_DRPADDR7", - "GTXE2_COMMON_DRPCLK", - "GTXE2_COMMON_DRPDI0", - "GTXE2_COMMON_DRPDI1", - "GTXE2_COMMON_DRPDI10", - "GTXE2_COMMON_DRPDI11", - "GTXE2_COMMON_DRPDI12", - "GTXE2_COMMON_DRPDI13", - "GTXE2_COMMON_DRPDI14", - "GTXE2_COMMON_DRPDI15", - "GTXE2_COMMON_DRPDI2", - "GTXE2_COMMON_DRPDI3", - "GTXE2_COMMON_DRPDI4", - "GTXE2_COMMON_DRPDI5", - "GTXE2_COMMON_DRPDI6", - "GTXE2_COMMON_DRPDI7", - "GTXE2_COMMON_DRPDI8", - "GTXE2_COMMON_DRPDI9", - "GTXE2_COMMON_DRPDO0", - "GTXE2_COMMON_DRPDO1", - "GTXE2_COMMON_DRPDO10", - "GTXE2_COMMON_DRPDO11", - "GTXE2_COMMON_DRPDO12", - "GTXE2_COMMON_DRPDO13", - "GTXE2_COMMON_DRPDO14", - "GTXE2_COMMON_DRPDO15", - "GTXE2_COMMON_DRPDO2", - "GTXE2_COMMON_DRPDO3", - "GTXE2_COMMON_DRPDO4", - "GTXE2_COMMON_DRPDO5", - "GTXE2_COMMON_DRPDO6", - "GTXE2_COMMON_DRPDO7", - "GTXE2_COMMON_DRPDO8", - "GTXE2_COMMON_DRPDO9", - "GTXE2_COMMON_DRPEN", - "GTXE2_COMMON_DRPRDY", - "GTXE2_COMMON_DRPWE", - "GTXE2_COMMON_GTGREFCLK", - "GTXE2_COMMON_GTNORTHREFCLK0", - "GTXE2_COMMON_GTNORTHREFCLK1", - "GTXE2_COMMON_GTQPLLOUTCLK", - "GTXE2_COMMON_GTQPLLOUTREFCLK", - "GTXE2_COMMON_GTREFCLK0", - "GTXE2_COMMON_GTREFCLK1", - "GTXE2_COMMON_GTSOUTHREFCLK0", - "GTXE2_COMMON_GTSOUTHREFCLK1", - "GTXE2_COMMON_MGT_CLK0", - "GTXE2_COMMON_MGT_CLK1", - "GTXE2_COMMON_MGT_CLK2", - "GTXE2_COMMON_MGT_CLK3", - "GTXE2_COMMON_MGT_CLK4", - "GTXE2_COMMON_MGT_CLK5", - "GTXE2_COMMON_MGT_CLK6", - "GTXE2_COMMON_MGT_CLK7", - "GTXE2_COMMON_MGT_CLK8", - "GTXE2_COMMON_MGT_CLK9", - "GTXE2_COMMON_NORTHREFCLK0", - "GTXE2_COMMON_NORTHREFCLK1", - "GTXE2_COMMON_PMARSVD0", - "GTXE2_COMMON_PMARSVD1", - "GTXE2_COMMON_PMARSVD2", - "GTXE2_COMMON_PMARSVD3", - "GTXE2_COMMON_PMARSVD4", - "GTXE2_COMMON_PMARSVD5", - "GTXE2_COMMON_PMARSVD6", - "GTXE2_COMMON_PMARSVD7", - "GTXE2_COMMON_PMASCANCLK0", - "GTXE2_COMMON_PMASCANCLK1", - "GTXE2_COMMON_PMASCANENB", - "GTXE2_COMMON_PMASCANIN0", - "GTXE2_COMMON_PMASCANIN1", - "GTXE2_COMMON_PMASCANIN2", - "GTXE2_COMMON_PMASCANIN3", - "GTXE2_COMMON_PMASCANIN4", - "GTXE2_COMMON_PMASCANOUT0", - "GTXE2_COMMON_PMASCANOUT1", - "GTXE2_COMMON_PMASCANOUT2", - "GTXE2_COMMON_PMASCANOUT3", - "GTXE2_COMMON_PMASCANOUT4", - "GTXE2_COMMON_QDPMASCANMODEB", - "GTXE2_COMMON_QDPMASCANRSTEN", - "GTXE2_COMMON_QPLLCLKSPARE0", - "GTXE2_COMMON_QPLLCLKSPARE1", - "GTXE2_COMMON_QPLLDMONITOR0", - "GTXE2_COMMON_QPLLDMONITOR1", - "GTXE2_COMMON_QPLLDMONITOR2", - "GTXE2_COMMON_QPLLDMONITOR3", - "GTXE2_COMMON_QPLLDMONITOR4", - "GTXE2_COMMON_QPLLDMONITOR5", - "GTXE2_COMMON_QPLLDMONITOR6", - "GTXE2_COMMON_QPLLDMONITOR7", - "GTXE2_COMMON_QPLLFBCLKLOST", - "GTXE2_COMMON_QPLLLOCK", - "GTXE2_COMMON_QPLLLOCKDETCLK", - "GTXE2_COMMON_QPLLLOCKEN", - "GTXE2_COMMON_QPLLOUTCLK", - "GTXE2_COMMON_QPLLOUTREFCLK", - "GTXE2_COMMON_QPLLOUTRESET", - "GTXE2_COMMON_QPLLPD", - "GTXE2_COMMON_QPLLREFCLKLOST", - "GTXE2_COMMON_QPLLREFCLKSEL0", - "GTXE2_COMMON_QPLLREFCLKSEL1", - "GTXE2_COMMON_QPLLREFCLKSEL2", - "GTXE2_COMMON_QPLLRESET", - "GTXE2_COMMON_QPLLRSVD10", - "GTXE2_COMMON_QPLLRSVD11", - "GTXE2_COMMON_QPLLRSVD110", - "GTXE2_COMMON_QPLLRSVD111", - "GTXE2_COMMON_QPLLRSVD112", - "GTXE2_COMMON_QPLLRSVD113", - "GTXE2_COMMON_QPLLRSVD114", - "GTXE2_COMMON_QPLLRSVD115", - "GTXE2_COMMON_QPLLRSVD12", - "GTXE2_COMMON_QPLLRSVD13", - "GTXE2_COMMON_QPLLRSVD14", - "GTXE2_COMMON_QPLLRSVD15", - "GTXE2_COMMON_QPLLRSVD16", - "GTXE2_COMMON_QPLLRSVD17", - "GTXE2_COMMON_QPLLRSVD18", - "GTXE2_COMMON_QPLLRSVD19", - "GTXE2_COMMON_QPLLRSVD20", - "GTXE2_COMMON_QPLLRSVD21", - "GTXE2_COMMON_QPLLRSVD22", - "GTXE2_COMMON_QPLLRSVD23", - "GTXE2_COMMON_QPLLRSVD24", - "GTXE2_COMMON_RCALENB", - "GTXE2_COMMON_REFCLK0", - "GTXE2_COMMON_REFCLK1", - "GTXE2_COMMON_REFCLKOUTMONITOR", - "GTXE2_COMMON_RXOUTCLK_0", - "GTXE2_COMMON_RXOUTCLK_1", - "GTXE2_COMMON_RXOUTCLK_2", - "GTXE2_COMMON_RXOUTCLK_3", - "GTXE2_COMMON_SOUTHREFCLK0", - "GTXE2_COMMON_SOUTHREFCLK1", - "GTXE2_COMMON_TXOUTCLK_0", - "GTXE2_COMMON_TXOUTCLK_1", - "GTXE2_COMMON_TXOUTCLK_2", - "GTXE2_COMMON_TXOUTCLK_3", - "GTXE2_CTRL0_0", - "GTXE2_CTRL0_1", - "GTXE2_CTRL0_2", - "GTXE2_CTRL0_3", - "GTXE2_CTRL0_4", - "GTXE2_CTRL0_5", - "GTXE2_CTRL1_0", - "GTXE2_CTRL1_1", - "GTXE2_CTRL1_2", - "GTXE2_CTRL1_3", - "GTXE2_CTRL1_4", - "GTXE2_CTRL1_5", - "GTXE2_FAN0_0", - "GTXE2_FAN0_1", - "GTXE2_FAN0_2", - "GTXE2_FAN0_3", - "GTXE2_FAN0_4", - "GTXE2_FAN0_5", - "GTXE2_FAN1_0", - "GTXE2_FAN1_1", - "GTXE2_FAN1_2", - "GTXE2_FAN1_3", - "GTXE2_FAN1_4", - "GTXE2_FAN1_5", - "GTXE2_FAN2_0", - "GTXE2_FAN2_1", - "GTXE2_FAN2_2", - "GTXE2_FAN2_3", - "GTXE2_FAN2_4", - "GTXE2_FAN2_5", - "GTXE2_FAN3_0", - "GTXE2_FAN3_1", - "GTXE2_FAN3_2", - "GTXE2_FAN3_3", - "GTXE2_FAN3_4", - "GTXE2_FAN3_5", - "GTXE2_FAN4_0", - "GTXE2_FAN4_1", - "GTXE2_FAN4_2", - "GTXE2_FAN4_3", - "GTXE2_FAN4_4", - "GTXE2_FAN4_5", - "GTXE2_FAN5_0", - "GTXE2_FAN5_1", - "GTXE2_FAN5_2", - "GTXE2_FAN5_3", - "GTXE2_FAN5_4", - "GTXE2_FAN5_5", - "GTXE2_FAN6_0", - "GTXE2_FAN6_1", - "GTXE2_FAN6_2", - "GTXE2_FAN6_3", - "GTXE2_FAN6_4", - "GTXE2_FAN6_5", - "GTXE2_FAN7_0", - "GTXE2_FAN7_1", - "GTXE2_FAN7_2", - "GTXE2_FAN7_3", - "GTXE2_FAN7_4", - "GTXE2_FAN7_5", - "GTXE2_IMUX0_0", - "GTXE2_IMUX0_1", - "GTXE2_IMUX0_2", - "GTXE2_IMUX0_3", - "GTXE2_IMUX0_4", - "GTXE2_IMUX0_5", - "GTXE2_IMUX10_0", - "GTXE2_IMUX10_1", - "GTXE2_IMUX10_2", - "GTXE2_IMUX10_3", - "GTXE2_IMUX10_4", - "GTXE2_IMUX10_5", - "GTXE2_IMUX11_0", - "GTXE2_IMUX11_1", - "GTXE2_IMUX11_2", - "GTXE2_IMUX11_3", - "GTXE2_IMUX11_4", - "GTXE2_IMUX11_5", - "GTXE2_IMUX12_0", - "GTXE2_IMUX12_1", - "GTXE2_IMUX12_2", - "GTXE2_IMUX12_3", - "GTXE2_IMUX12_4", - "GTXE2_IMUX12_5", - "GTXE2_IMUX13_0", - "GTXE2_IMUX13_1", - "GTXE2_IMUX13_2", - "GTXE2_IMUX13_3", - "GTXE2_IMUX13_4", - "GTXE2_IMUX13_5", - "GTXE2_IMUX14_0", - "GTXE2_IMUX14_1", - "GTXE2_IMUX14_2", - "GTXE2_IMUX14_3", - "GTXE2_IMUX14_4", - "GTXE2_IMUX14_5", - "GTXE2_IMUX15_0", - "GTXE2_IMUX15_1", - "GTXE2_IMUX15_2", - "GTXE2_IMUX15_3", - "GTXE2_IMUX15_4", - "GTXE2_IMUX15_5", - "GTXE2_IMUX16_0", - "GTXE2_IMUX16_1", - "GTXE2_IMUX16_2", - "GTXE2_IMUX16_3", - "GTXE2_IMUX16_4", - "GTXE2_IMUX16_5", - "GTXE2_IMUX17_0", - "GTXE2_IMUX17_1", - "GTXE2_IMUX17_2", - "GTXE2_IMUX17_3", - "GTXE2_IMUX17_4", - "GTXE2_IMUX17_5", - "GTXE2_IMUX18_0", - "GTXE2_IMUX18_1", - "GTXE2_IMUX18_2", - "GTXE2_IMUX18_3", - "GTXE2_IMUX18_4", - "GTXE2_IMUX18_5", - "GTXE2_IMUX19_0", - "GTXE2_IMUX19_1", - "GTXE2_IMUX19_2", - "GTXE2_IMUX19_3", - "GTXE2_IMUX19_4", - "GTXE2_IMUX19_5", - "GTXE2_IMUX1_0", - "GTXE2_IMUX1_1", - "GTXE2_IMUX1_2", - "GTXE2_IMUX1_3", - "GTXE2_IMUX1_4", - "GTXE2_IMUX1_5", - "GTXE2_IMUX20_0", - "GTXE2_IMUX20_1", - "GTXE2_IMUX20_2", - "GTXE2_IMUX20_3", - "GTXE2_IMUX20_4", - "GTXE2_IMUX20_5", - "GTXE2_IMUX21_0", - "GTXE2_IMUX21_1", - "GTXE2_IMUX21_2", - "GTXE2_IMUX21_3", - "GTXE2_IMUX21_4", - "GTXE2_IMUX21_5", - "GTXE2_IMUX22_0", - "GTXE2_IMUX22_1", - "GTXE2_IMUX22_2", - "GTXE2_IMUX22_3", - "GTXE2_IMUX22_4", - "GTXE2_IMUX22_5", - "GTXE2_IMUX23_0", - "GTXE2_IMUX23_1", - "GTXE2_IMUX23_2", - "GTXE2_IMUX23_3", - "GTXE2_IMUX23_4", - "GTXE2_IMUX23_5", - "GTXE2_IMUX24_0", - "GTXE2_IMUX24_1", - "GTXE2_IMUX24_2", - "GTXE2_IMUX24_3", - "GTXE2_IMUX24_4", - "GTXE2_IMUX24_5", - "GTXE2_IMUX25_0", - "GTXE2_IMUX25_1", - "GTXE2_IMUX25_2", - "GTXE2_IMUX25_3", - "GTXE2_IMUX25_4", - "GTXE2_IMUX25_5", - "GTXE2_IMUX26_0", - "GTXE2_IMUX26_1", - "GTXE2_IMUX26_2", - "GTXE2_IMUX26_3", - "GTXE2_IMUX26_4", - "GTXE2_IMUX26_5", - "GTXE2_IMUX27_0", - "GTXE2_IMUX27_1", - "GTXE2_IMUX27_2", - "GTXE2_IMUX27_3", - "GTXE2_IMUX27_4", - "GTXE2_IMUX27_5", - "GTXE2_IMUX28_0", - "GTXE2_IMUX28_1", - "GTXE2_IMUX28_2", - "GTXE2_IMUX28_3", - "GTXE2_IMUX28_4", - "GTXE2_IMUX28_5", - "GTXE2_IMUX29_0", - "GTXE2_IMUX29_1", - "GTXE2_IMUX29_2", - "GTXE2_IMUX29_3", - "GTXE2_IMUX29_4", - "GTXE2_IMUX29_5", - "GTXE2_IMUX2_0", - "GTXE2_IMUX2_1", - "GTXE2_IMUX2_2", - "GTXE2_IMUX2_3", - "GTXE2_IMUX2_4", - "GTXE2_IMUX2_5", - "GTXE2_IMUX30_0", - "GTXE2_IMUX30_1", - "GTXE2_IMUX30_2", - "GTXE2_IMUX30_3", - "GTXE2_IMUX30_4", - "GTXE2_IMUX30_5", - "GTXE2_IMUX31_0", - "GTXE2_IMUX31_1", - "GTXE2_IMUX31_2", - "GTXE2_IMUX31_3", - "GTXE2_IMUX31_4", - "GTXE2_IMUX31_5", - "GTXE2_IMUX32_0", - "GTXE2_IMUX32_1", - "GTXE2_IMUX32_2", - "GTXE2_IMUX32_3", - "GTXE2_IMUX32_4", - "GTXE2_IMUX32_5", - "GTXE2_IMUX33_0", - "GTXE2_IMUX33_1", - "GTXE2_IMUX33_2", - "GTXE2_IMUX33_3", - "GTXE2_IMUX33_4", - "GTXE2_IMUX33_5", - "GTXE2_IMUX34_0", - "GTXE2_IMUX34_1", - "GTXE2_IMUX34_2", - "GTXE2_IMUX34_3", - "GTXE2_IMUX34_4", - "GTXE2_IMUX34_5", - "GTXE2_IMUX35_0", - "GTXE2_IMUX35_1", - "GTXE2_IMUX35_2", - "GTXE2_IMUX35_3", - "GTXE2_IMUX35_4", - "GTXE2_IMUX35_5", - "GTXE2_IMUX36_0", - "GTXE2_IMUX36_1", - "GTXE2_IMUX36_2", - "GTXE2_IMUX36_3", - "GTXE2_IMUX36_4", - "GTXE2_IMUX36_5", - "GTXE2_IMUX37_0", - "GTXE2_IMUX37_1", - "GTXE2_IMUX37_2", - "GTXE2_IMUX37_3", - "GTXE2_IMUX37_4", - "GTXE2_IMUX37_5", - "GTXE2_IMUX38_0", - "GTXE2_IMUX38_1", - "GTXE2_IMUX38_2", - "GTXE2_IMUX38_3", - "GTXE2_IMUX38_4", - "GTXE2_IMUX38_5", - "GTXE2_IMUX39_0", - "GTXE2_IMUX39_1", - "GTXE2_IMUX39_2", - "GTXE2_IMUX39_3", - "GTXE2_IMUX39_4", - "GTXE2_IMUX39_5", - "GTXE2_IMUX3_0", - "GTXE2_IMUX3_1", - "GTXE2_IMUX3_2", - "GTXE2_IMUX3_3", - "GTXE2_IMUX3_4", - "GTXE2_IMUX3_5", - "GTXE2_IMUX40_0", - "GTXE2_IMUX40_1", - "GTXE2_IMUX40_2", - "GTXE2_IMUX40_3", - "GTXE2_IMUX40_4", - "GTXE2_IMUX40_5", - "GTXE2_IMUX41_0", - "GTXE2_IMUX41_1", - "GTXE2_IMUX41_2", - "GTXE2_IMUX41_3", - "GTXE2_IMUX41_4", - "GTXE2_IMUX41_5", - "GTXE2_IMUX42_0", - "GTXE2_IMUX42_1", - "GTXE2_IMUX42_2", - "GTXE2_IMUX42_3", - "GTXE2_IMUX42_4", - "GTXE2_IMUX42_5", - "GTXE2_IMUX43_0", - "GTXE2_IMUX43_1", - "GTXE2_IMUX43_2", - "GTXE2_IMUX43_3", - "GTXE2_IMUX43_4", - "GTXE2_IMUX43_5", - "GTXE2_IMUX44_0", - "GTXE2_IMUX44_1", - "GTXE2_IMUX44_2", - "GTXE2_IMUX44_3", - "GTXE2_IMUX44_4", - "GTXE2_IMUX44_5", - "GTXE2_IMUX45_0", - "GTXE2_IMUX45_1", - "GTXE2_IMUX45_2", - "GTXE2_IMUX45_3", - "GTXE2_IMUX45_4", - "GTXE2_IMUX45_5", - "GTXE2_IMUX46_0", - "GTXE2_IMUX46_1", - "GTXE2_IMUX46_2", - "GTXE2_IMUX46_3", - "GTXE2_IMUX46_4", - "GTXE2_IMUX46_5", - "GTXE2_IMUX47_0", - "GTXE2_IMUX47_1", - "GTXE2_IMUX47_2", - "GTXE2_IMUX47_3", - "GTXE2_IMUX47_4", - "GTXE2_IMUX47_5", - "GTXE2_IMUX4_0", - "GTXE2_IMUX4_1", - "GTXE2_IMUX4_2", - "GTXE2_IMUX4_3", - "GTXE2_IMUX4_4", - "GTXE2_IMUX4_5", - "GTXE2_IMUX5_0", - "GTXE2_IMUX5_1", - "GTXE2_IMUX5_2", - "GTXE2_IMUX5_3", - "GTXE2_IMUX5_4", - "GTXE2_IMUX5_5", - "GTXE2_IMUX6_0", - "GTXE2_IMUX6_1", - "GTXE2_IMUX6_2", - "GTXE2_IMUX6_3", - "GTXE2_IMUX6_4", - "GTXE2_IMUX6_5", - "GTXE2_IMUX7_0", - "GTXE2_IMUX7_1", - "GTXE2_IMUX7_2", - "GTXE2_IMUX7_3", - "GTXE2_IMUX7_4", - "GTXE2_IMUX7_5", - "GTXE2_IMUX8_0", - "GTXE2_IMUX8_1", - "GTXE2_IMUX8_2", - "GTXE2_IMUX8_3", - "GTXE2_IMUX8_4", - "GTXE2_IMUX8_5", - "GTXE2_IMUX9_0", - "GTXE2_IMUX9_1", - "GTXE2_IMUX9_2", - "GTXE2_IMUX9_3", - "GTXE2_IMUX9_4", - "GTXE2_IMUX9_5", - "GTXE2_LOGIC_OUTS_B0_0", - "GTXE2_LOGIC_OUTS_B0_1", - "GTXE2_LOGIC_OUTS_B0_2", - "GTXE2_LOGIC_OUTS_B0_3", - "GTXE2_LOGIC_OUTS_B0_4", - "GTXE2_LOGIC_OUTS_B0_5", - "GTXE2_LOGIC_OUTS_B10_0", - "GTXE2_LOGIC_OUTS_B10_1", - "GTXE2_LOGIC_OUTS_B10_2", - "GTXE2_LOGIC_OUTS_B10_3", - "GTXE2_LOGIC_OUTS_B10_4", - "GTXE2_LOGIC_OUTS_B10_5", - "GTXE2_LOGIC_OUTS_B11_0", - "GTXE2_LOGIC_OUTS_B11_1", - "GTXE2_LOGIC_OUTS_B11_2", - "GTXE2_LOGIC_OUTS_B11_3", - "GTXE2_LOGIC_OUTS_B11_4", - "GTXE2_LOGIC_OUTS_B11_5", - "GTXE2_LOGIC_OUTS_B12_0", - "GTXE2_LOGIC_OUTS_B12_1", - "GTXE2_LOGIC_OUTS_B12_2", - "GTXE2_LOGIC_OUTS_B12_3", - "GTXE2_LOGIC_OUTS_B12_4", - "GTXE2_LOGIC_OUTS_B12_5", - "GTXE2_LOGIC_OUTS_B13_0", - "GTXE2_LOGIC_OUTS_B13_1", - "GTXE2_LOGIC_OUTS_B13_2", - "GTXE2_LOGIC_OUTS_B13_3", - "GTXE2_LOGIC_OUTS_B13_4", - "GTXE2_LOGIC_OUTS_B13_5", - "GTXE2_LOGIC_OUTS_B14_0", - "GTXE2_LOGIC_OUTS_B14_1", - "GTXE2_LOGIC_OUTS_B14_2", - "GTXE2_LOGIC_OUTS_B14_3", - "GTXE2_LOGIC_OUTS_B14_4", - "GTXE2_LOGIC_OUTS_B14_5", - "GTXE2_LOGIC_OUTS_B15_0", - "GTXE2_LOGIC_OUTS_B15_1", - "GTXE2_LOGIC_OUTS_B15_2", - "GTXE2_LOGIC_OUTS_B15_3", - "GTXE2_LOGIC_OUTS_B15_4", - "GTXE2_LOGIC_OUTS_B15_5", - "GTXE2_LOGIC_OUTS_B16_0", - "GTXE2_LOGIC_OUTS_B16_1", - "GTXE2_LOGIC_OUTS_B16_2", - "GTXE2_LOGIC_OUTS_B16_3", - "GTXE2_LOGIC_OUTS_B16_4", - "GTXE2_LOGIC_OUTS_B16_5", - "GTXE2_LOGIC_OUTS_B17_0", - "GTXE2_LOGIC_OUTS_B17_1", - "GTXE2_LOGIC_OUTS_B17_2", - "GTXE2_LOGIC_OUTS_B17_3", - "GTXE2_LOGIC_OUTS_B17_4", - "GTXE2_LOGIC_OUTS_B17_5", - "GTXE2_LOGIC_OUTS_B18_0", - "GTXE2_LOGIC_OUTS_B18_1", - "GTXE2_LOGIC_OUTS_B18_2", - "GTXE2_LOGIC_OUTS_B18_3", - "GTXE2_LOGIC_OUTS_B18_4", - "GTXE2_LOGIC_OUTS_B18_5", - "GTXE2_LOGIC_OUTS_B19_0", - "GTXE2_LOGIC_OUTS_B19_1", - "GTXE2_LOGIC_OUTS_B19_2", - "GTXE2_LOGIC_OUTS_B19_3", - "GTXE2_LOGIC_OUTS_B19_4", - "GTXE2_LOGIC_OUTS_B19_5", - "GTXE2_LOGIC_OUTS_B1_0", - "GTXE2_LOGIC_OUTS_B1_1", - "GTXE2_LOGIC_OUTS_B1_2", - "GTXE2_LOGIC_OUTS_B1_3", - "GTXE2_LOGIC_OUTS_B1_4", - "GTXE2_LOGIC_OUTS_B1_5", - "GTXE2_LOGIC_OUTS_B20_0", - "GTXE2_LOGIC_OUTS_B20_1", - "GTXE2_LOGIC_OUTS_B20_2", - "GTXE2_LOGIC_OUTS_B20_3", - "GTXE2_LOGIC_OUTS_B20_4", - "GTXE2_LOGIC_OUTS_B20_5", - "GTXE2_LOGIC_OUTS_B21_0", - "GTXE2_LOGIC_OUTS_B21_1", - "GTXE2_LOGIC_OUTS_B21_2", - "GTXE2_LOGIC_OUTS_B21_3", - "GTXE2_LOGIC_OUTS_B21_4", - "GTXE2_LOGIC_OUTS_B21_5", - "GTXE2_LOGIC_OUTS_B22_0", - "GTXE2_LOGIC_OUTS_B22_1", - "GTXE2_LOGIC_OUTS_B22_2", - "GTXE2_LOGIC_OUTS_B22_3", - "GTXE2_LOGIC_OUTS_B22_4", - "GTXE2_LOGIC_OUTS_B22_5", - "GTXE2_LOGIC_OUTS_B23_0", - "GTXE2_LOGIC_OUTS_B23_1", - "GTXE2_LOGIC_OUTS_B23_2", - "GTXE2_LOGIC_OUTS_B23_3", - "GTXE2_LOGIC_OUTS_B23_4", - "GTXE2_LOGIC_OUTS_B23_5", - "GTXE2_LOGIC_OUTS_B2_0", - "GTXE2_LOGIC_OUTS_B2_1", - "GTXE2_LOGIC_OUTS_B2_2", - "GTXE2_LOGIC_OUTS_B2_3", - "GTXE2_LOGIC_OUTS_B2_4", - "GTXE2_LOGIC_OUTS_B2_5", - "GTXE2_LOGIC_OUTS_B3_0", - "GTXE2_LOGIC_OUTS_B3_1", - "GTXE2_LOGIC_OUTS_B3_2", - "GTXE2_LOGIC_OUTS_B3_3", - "GTXE2_LOGIC_OUTS_B3_4", - "GTXE2_LOGIC_OUTS_B3_5", - "GTXE2_LOGIC_OUTS_B4_0", - "GTXE2_LOGIC_OUTS_B4_1", - "GTXE2_LOGIC_OUTS_B4_2", - "GTXE2_LOGIC_OUTS_B4_3", - "GTXE2_LOGIC_OUTS_B4_4", - "GTXE2_LOGIC_OUTS_B4_5", - "GTXE2_LOGIC_OUTS_B5_0", - "GTXE2_LOGIC_OUTS_B5_1", - "GTXE2_LOGIC_OUTS_B5_2", - "GTXE2_LOGIC_OUTS_B5_3", - "GTXE2_LOGIC_OUTS_B5_4", - "GTXE2_LOGIC_OUTS_B5_5", - "GTXE2_LOGIC_OUTS_B6_0", - "GTXE2_LOGIC_OUTS_B6_1", - "GTXE2_LOGIC_OUTS_B6_2", - "GTXE2_LOGIC_OUTS_B6_3", - "GTXE2_LOGIC_OUTS_B6_4", - "GTXE2_LOGIC_OUTS_B6_5", - "GTXE2_LOGIC_OUTS_B7_0", - "GTXE2_LOGIC_OUTS_B7_1", - "GTXE2_LOGIC_OUTS_B7_2", - "GTXE2_LOGIC_OUTS_B7_3", - "GTXE2_LOGIC_OUTS_B7_4", - "GTXE2_LOGIC_OUTS_B7_5", - "GTXE2_LOGIC_OUTS_B8_0", - "GTXE2_LOGIC_OUTS_B8_1", - "GTXE2_LOGIC_OUTS_B8_2", - "GTXE2_LOGIC_OUTS_B8_3", - "GTXE2_LOGIC_OUTS_B8_4", - "GTXE2_LOGIC_OUTS_B8_5", - "GTXE2_LOGIC_OUTS_B9_0", - "GTXE2_LOGIC_OUTS_B9_1", - "GTXE2_LOGIC_OUTS_B9_2", - "GTXE2_LOGIC_OUTS_B9_3", - "GTXE2_LOGIC_OUTS_B9_4", - "GTXE2_LOGIC_OUTS_B9_5", - "IBUFDS_GTE2_0_CEB", - "IBUFDS_GTE2_0_CLKTESTSIG", - "IBUFDS_GTE2_0_CLKTESTSIG_SEG", - "IBUFDS_GTE2_0_I", - "IBUFDS_GTE2_0_IB", - "IBUFDS_GTE2_0_IB_SEG", - "IBUFDS_GTE2_0_I_SEG", - "IBUFDS_GTE2_0_MGTCLKOUT", - "IBUFDS_GTE2_0_O", - "IBUFDS_GTE2_0_ODIV2", - "IBUFDS_GTE2_1_CEB", - "IBUFDS_GTE2_1_CLKTESTSIG", - "IBUFDS_GTE2_1_CLKTESTSIG_SEG", - "IBUFDS_GTE2_1_I", - "IBUFDS_GTE2_1_IB", - "IBUFDS_GTE2_1_IB_SEG", - "IBUFDS_GTE2_1_I_SEG", - "IBUFDS_GTE2_1_MGTCLKOUT", - "IBUFDS_GTE2_1_O", - "IBUFDS_GTE2_1_ODIV2" - ] + "wires": { + "GTXE2_BYP0_0": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP0_1": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP0_2": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP0_3": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP0_4": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP0_5": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP1_0": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP1_1": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP1_2": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP1_3": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP1_4": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP1_5": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP2_0": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP2_1": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP2_2": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP2_3": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP2_4": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP2_5": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP3_0": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP3_1": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP3_2": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP3_3": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP3_4": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP3_5": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP4_0": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP4_1": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP4_2": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP4_3": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP4_4": { + "cap": "127.500", + "res": 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+ }, + "GTXE2_BYP7_3": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP7_4": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_BYP7_5": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK0_0": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK0_1": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK0_2": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK0_3": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK0_4": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK0_5": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK1_0": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK1_1": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK1_2": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK1_3": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK1_4": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_CLK1_5": { + "cap": "127.500", + "res": "0.000" + }, + "GTXE2_COMMON_BGBYPASSB": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_BGMONITORENB": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_BGPDB": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_BGRCALOVRD0": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_BGRCALOVRD1": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_BGRCALOVRD2": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_BGRCALOVRD3": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_BGRCALOVRD4": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_DRPADDR0": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_DRPADDR1": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_DRPADDR2": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_DRPADDR3": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_DRPADDR4": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_DRPADDR5": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_COMMON_DRPADDR6": { + "cap": "0.100", + "res": "0.000" + }, + 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a/kintex7/tile_type_GTX_INT_INTERFACE.json b/kintex7/tile_type_GTX_INT_INTERFACE.json index 4d6c564..f981929 100644 --- a/kintex7/tile_type_GTX_INT_INTERFACE.json +++ b/kintex7/tile_type_GTX_INT_INTERFACE.json @@ -2,1525 +2,4717 @@ "pips": { "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX0->>GTXE2_INT_INTERFACE_IMUX_DELAY0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.291", + "0.356", + "0.481", + "0.644" + ], + "in_cap": "0.000", + "res": "878.41875" + }, "dst_wire": "GTXE2_INT_INTERFACE_IMUX_DELAY0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.291", + "0.356", + "0.481", + "0.644" + ], + "in_cap": "0.000", + "res": "878.41875" + }, "src_wire": "GTXE2_INT_INTERFACE_IMUX0" }, "GTX_INT_INTERFACE.GTXE2_INT_INTERFACE_IMUX0->>GTXE2_INT_INTERFACE_IMUX_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.025", + "0.030", + "0.045", + "0.054" + ], + "in_cap": "0.000", + "res": "878.41875" + }, "dst_wire": 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"0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX40": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX41": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX42": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX43": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX44": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX45": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX46": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX47": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX5": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX6": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX7": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX8": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX9": { + "cap": "0.100", + "res": "0.000" + }, + "GTXE2_INT_INTERFACE_IMUX_DELAY0": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY1": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY10": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY11": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY12": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY13": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY14": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY15": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY16": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY17": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY18": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY19": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY2": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY20": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY21": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY22": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY23": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY24": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY25": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY26": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY27": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY28": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY29": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY3": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY30": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY31": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY32": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY33": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY34": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY35": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY36": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY37": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY38": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY39": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY4": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY40": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY41": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY42": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY43": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY44": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY45": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY46": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY47": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY5": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY6": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY7": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY8": null, + "GTXE2_INT_INTERFACE_IMUX_DELAY9": null, + "GTXE2_INT_INTERFACE_IMUX_OUT0": null, + "GTXE2_INT_INTERFACE_IMUX_OUT1": null, + "GTXE2_INT_INTERFACE_IMUX_OUT10": null, + "GTXE2_INT_INTERFACE_IMUX_OUT11": null, + "GTXE2_INT_INTERFACE_IMUX_OUT12": null, + "GTXE2_INT_INTERFACE_IMUX_OUT13": null, + "GTXE2_INT_INTERFACE_IMUX_OUT14": null, + "GTXE2_INT_INTERFACE_IMUX_OUT15": null, + "GTXE2_INT_INTERFACE_IMUX_OUT16": null, + "GTXE2_INT_INTERFACE_IMUX_OUT17": null, + "GTXE2_INT_INTERFACE_IMUX_OUT18": null, + "GTXE2_INT_INTERFACE_IMUX_OUT19": null, + "GTXE2_INT_INTERFACE_IMUX_OUT2": null, + "GTXE2_INT_INTERFACE_IMUX_OUT20": null, + "GTXE2_INT_INTERFACE_IMUX_OUT21": null, + "GTXE2_INT_INTERFACE_IMUX_OUT22": null, + "GTXE2_INT_INTERFACE_IMUX_OUT23": null, + "GTXE2_INT_INTERFACE_IMUX_OUT24": null, + "GTXE2_INT_INTERFACE_IMUX_OUT25": null, + "GTXE2_INT_INTERFACE_IMUX_OUT26": null, + "GTXE2_INT_INTERFACE_IMUX_OUT27": null, + "GTXE2_INT_INTERFACE_IMUX_OUT28": null, + "GTXE2_INT_INTERFACE_IMUX_OUT29": null, + "GTXE2_INT_INTERFACE_IMUX_OUT3": null, + "GTXE2_INT_INTERFACE_IMUX_OUT30": null, + "GTXE2_INT_INTERFACE_IMUX_OUT31": null, + "GTXE2_INT_INTERFACE_IMUX_OUT32": null, + "GTXE2_INT_INTERFACE_IMUX_OUT33": null, + "GTXE2_INT_INTERFACE_IMUX_OUT34": null, + "GTXE2_INT_INTERFACE_IMUX_OUT35": null, + "GTXE2_INT_INTERFACE_IMUX_OUT36": null, + "GTXE2_INT_INTERFACE_IMUX_OUT37": null, + "GTXE2_INT_INTERFACE_IMUX_OUT38": null, + "GTXE2_INT_INTERFACE_IMUX_OUT39": null, + "GTXE2_INT_INTERFACE_IMUX_OUT4": null, + "GTXE2_INT_INTERFACE_IMUX_OUT40": null, + "GTXE2_INT_INTERFACE_IMUX_OUT41": null, + "GTXE2_INT_INTERFACE_IMUX_OUT42": null, + "GTXE2_INT_INTERFACE_IMUX_OUT43": null, + "GTXE2_INT_INTERFACE_IMUX_OUT44": null, + "GTXE2_INT_INTERFACE_IMUX_OUT45": null, + "GTXE2_INT_INTERFACE_IMUX_OUT46": null, + "GTXE2_INT_INTERFACE_IMUX_OUT47": null, + "GTXE2_INT_INTERFACE_IMUX_OUT5": null, + "GTXE2_INT_INTERFACE_IMUX_OUT6": null, + "GTXE2_INT_INTERFACE_IMUX_OUT7": null, + "GTXE2_INT_INTERFACE_IMUX_OUT8": null, + "GTXE2_INT_INTERFACE_IMUX_OUT9": null, + "INT_INTERFACE_BLOCK_OUTS_B0": null, + "INT_INTERFACE_BLOCK_OUTS_B1": null, + "INT_INTERFACE_BLOCK_OUTS_B2": null, + "INT_INTERFACE_BLOCK_OUTS_B3": null, + "INT_INTERFACE_BYP0": null, + "INT_INTERFACE_BYP1": null, + "INT_INTERFACE_BYP2": null, + "INT_INTERFACE_BYP3": null, + "INT_INTERFACE_BYP4": null, + "INT_INTERFACE_BYP5": null, + "INT_INTERFACE_BYP6": null, + "INT_INTERFACE_BYP7": null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS0": null, + "INT_INTERFACE_LOGIC_OUTS1": null, + "INT_INTERFACE_LOGIC_OUTS10": null, + "INT_INTERFACE_LOGIC_OUTS11": null, + "INT_INTERFACE_LOGIC_OUTS12": null, + "INT_INTERFACE_LOGIC_OUTS13": null, + "INT_INTERFACE_LOGIC_OUTS14": null, + "INT_INTERFACE_LOGIC_OUTS15": null, + "INT_INTERFACE_LOGIC_OUTS16": null, + "INT_INTERFACE_LOGIC_OUTS17": null, + "INT_INTERFACE_LOGIC_OUTS18": null, + "INT_INTERFACE_LOGIC_OUTS19": null, + "INT_INTERFACE_LOGIC_OUTS2": null, + "INT_INTERFACE_LOGIC_OUTS20": null, + "INT_INTERFACE_LOGIC_OUTS21": null, + "INT_INTERFACE_LOGIC_OUTS22": null, + "INT_INTERFACE_LOGIC_OUTS23": null, + "INT_INTERFACE_LOGIC_OUTS3": null, + "INT_INTERFACE_LOGIC_OUTS4": null, + "INT_INTERFACE_LOGIC_OUTS5": null, + "INT_INTERFACE_LOGIC_OUTS6": null, + "INT_INTERFACE_LOGIC_OUTS7": null, + "INT_INTERFACE_LOGIC_OUTS8": null, + "INT_INTERFACE_LOGIC_OUTS9": null, + "INT_INTERFACE_LOGIC_OUTS_B0": null, + "INT_INTERFACE_LOGIC_OUTS_B1": null, + "INT_INTERFACE_LOGIC_OUTS_B10": null, + "INT_INTERFACE_LOGIC_OUTS_B11": null, + "INT_INTERFACE_LOGIC_OUTS_B12": null, + "INT_INTERFACE_LOGIC_OUTS_B13": null, + "INT_INTERFACE_LOGIC_OUTS_B14": null, + "INT_INTERFACE_LOGIC_OUTS_B15": null, + "INT_INTERFACE_LOGIC_OUTS_B16": null, + "INT_INTERFACE_LOGIC_OUTS_B17": null, + "INT_INTERFACE_LOGIC_OUTS_B18": null, + "INT_INTERFACE_LOGIC_OUTS_B19": null, + "INT_INTERFACE_LOGIC_OUTS_B2": null, + "INT_INTERFACE_LOGIC_OUTS_B20": null, + "INT_INTERFACE_LOGIC_OUTS_B21": null, + "INT_INTERFACE_LOGIC_OUTS_B22": null, + "INT_INTERFACE_LOGIC_OUTS_B23": null, + "INT_INTERFACE_LOGIC_OUTS_B3": null, + "INT_INTERFACE_LOGIC_OUTS_B4": null, + "INT_INTERFACE_LOGIC_OUTS_B5": null, + "INT_INTERFACE_LOGIC_OUTS_B6": null, + "INT_INTERFACE_LOGIC_OUTS_B7": null, + "INT_INTERFACE_LOGIC_OUTS_B8": null, + "INT_INTERFACE_LOGIC_OUTS_B9": null, + "INT_INTERFACE_MONITOR_N": null, + "INT_INTERFACE_MONITOR_P": null, + "INT_INTERFACE_NE2A0": null, + "INT_INTERFACE_NE2A1": null, + "INT_INTERFACE_NE2A2": null, + "INT_INTERFACE_NE2A3": null, + "INT_INTERFACE_NE4BEG0": null, + "INT_INTERFACE_NE4BEG1": null, + "INT_INTERFACE_NE4BEG2": null, + "INT_INTERFACE_NE4BEG3": null, + "INT_INTERFACE_NE4C0": null, + "INT_INTERFACE_NE4C1": null, + "INT_INTERFACE_NE4C2": null, + "INT_INTERFACE_NE4C3": null, + "INT_INTERFACE_NW2A0": null, + "INT_INTERFACE_NW2A1": null, + "INT_INTERFACE_NW2A2": null, + "INT_INTERFACE_NW2A3": null, + "INT_INTERFACE_NW4A0": null, + "INT_INTERFACE_NW4A1": null, + "INT_INTERFACE_NW4A2": null, + "INT_INTERFACE_NW4A3": null, + "INT_INTERFACE_NW4END0": null, + "INT_INTERFACE_NW4END1": null, + "INT_INTERFACE_NW4END2": null, + "INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + "INT_INTERFACE_SW4END3": null, + "INT_INTERFACE_WL1END0": null, + "INT_INTERFACE_WL1END1": null, + "INT_INTERFACE_WL1END2": null, + "INT_INTERFACE_WL1END3": null, + "INT_INTERFACE_WR1END0": null, + "INT_INTERFACE_WR1END1": null, + "INT_INTERFACE_WR1END2": null, + "INT_INTERFACE_WR1END3": null, + "INT_INTERFACE_WW2A0": null, + "INT_INTERFACE_WW2A1": null, + "INT_INTERFACE_WW2A2": null, + "INT_INTERFACE_WW2A3": null, + "INT_INTERFACE_WW2END0": null, + "INT_INTERFACE_WW2END1": null, + "INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null + } } diff --git a/kintex7/tile_type_HCLK_BRAM.json b/kintex7/tile_type_HCLK_BRAM.json index 5e5a40f..edbe22c 100644 --- a/kintex7/tile_type_HCLK_BRAM.json +++ b/kintex7/tile_type_HCLK_BRAM.json @@ -2,107 +2,107 @@ "pips": {}, "sites": [], "tile_type": "HCLK_BRAM", - "wires": [ - "HCLK_BRAM_CASCADEA_L", - "HCLK_BRAM_CASCADEA_R", - "HCLK_BRAM_CASCADEB_L", - "HCLK_BRAM_CASCADEB_R", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8", - "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8", - "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9", - "HCLK_BRAM_CK_BUFHCLK0", - "HCLK_BRAM_CK_BUFHCLK1", - "HCLK_BRAM_CK_BUFHCLK10", - "HCLK_BRAM_CK_BUFHCLK11", - "HCLK_BRAM_CK_BUFHCLK2", - "HCLK_BRAM_CK_BUFHCLK3", - "HCLK_BRAM_CK_BUFHCLK4", - "HCLK_BRAM_CK_BUFHCLK5", - "HCLK_BRAM_CK_BUFHCLK6", - "HCLK_BRAM_CK_BUFHCLK7", - "HCLK_BRAM_CK_BUFHCLK8", - "HCLK_BRAM_CK_BUFHCLK9", - "HCLK_BRAM_CK_BUFRCLK0", - "HCLK_BRAM_CK_BUFRCLK1", - "HCLK_BRAM_CK_BUFRCLK2", - "HCLK_BRAM_CK_BUFRCLK3", - "HCLK_BRAM_CK_IN0", - "HCLK_BRAM_CK_IN1", - "HCLK_BRAM_CK_IN10", - "HCLK_BRAM_CK_IN11", - "HCLK_BRAM_CK_IN12", - "HCLK_BRAM_CK_IN13", - "HCLK_BRAM_CK_IN2", - "HCLK_BRAM_CK_IN3", - "HCLK_BRAM_CK_IN4", - "HCLK_BRAM_CK_IN5", - "HCLK_BRAM_CK_IN6", - "HCLK_BRAM_CK_IN7", - "HCLK_BRAM_CK_IN8", - "HCLK_BRAM_CK_IN9", - "HCLK_BRAM_PMVBRAM_O", - "HCLK_BRAM_PMVBRAM_ODIV2", - "HCLK_BRAM_PMVBRAM_ODIV4", - "HCLK_BRAM_PMVBRAM_SELECT1", - "HCLK_BRAM_PMVBRAM_SELECT2", - "HCLK_BRAM_PMVBRAM_SELECT3", - "HCLK_BRAM_PMVBRAM_SELECT4" - ] + "wires": { + "HCLK_BRAM_CASCADEA_L": null, + "HCLK_BRAM_CASCADEA_R": null, + "HCLK_BRAM_CASCADEB_L": null, + "HCLK_BRAM_CASCADEB_R": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU0": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU1": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU10": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU11": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU12": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU13": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU14": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU2": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU3": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU4": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU5": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU6": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU7": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU8": null, + "HCLK_BRAM_CASCIN_L_ADDRARDADDRU9": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU0": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU1": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU10": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU11": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU12": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU13": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU14": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU2": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU3": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU4": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU5": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU6": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU7": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU8": null, + "HCLK_BRAM_CASCIN_L_ADDRBWRADDRU9": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU0": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU1": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU10": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU11": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU12": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU13": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU14": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU2": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU3": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU4": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU5": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU6": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU7": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU8": null, + "HCLK_BRAM_CASCOUT_L_ADDRARDADDRU9": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU0": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU1": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU10": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU11": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU12": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU13": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU14": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU2": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU3": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU4": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU5": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU6": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU7": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU8": null, + "HCLK_BRAM_CASCOUT_L_ADDRBWRADDRU9": null, + "HCLK_BRAM_CK_BUFHCLK0": null, + "HCLK_BRAM_CK_BUFHCLK1": null, + "HCLK_BRAM_CK_BUFHCLK10": null, + "HCLK_BRAM_CK_BUFHCLK11": null, + "HCLK_BRAM_CK_BUFHCLK2": null, + "HCLK_BRAM_CK_BUFHCLK3": null, + "HCLK_BRAM_CK_BUFHCLK4": null, + "HCLK_BRAM_CK_BUFHCLK5": null, + "HCLK_BRAM_CK_BUFHCLK6": null, + "HCLK_BRAM_CK_BUFHCLK7": null, + "HCLK_BRAM_CK_BUFHCLK8": null, + "HCLK_BRAM_CK_BUFHCLK9": null, + "HCLK_BRAM_CK_BUFRCLK0": null, + "HCLK_BRAM_CK_BUFRCLK1": null, + "HCLK_BRAM_CK_BUFRCLK2": null, + "HCLK_BRAM_CK_BUFRCLK3": null, + "HCLK_BRAM_CK_IN0": null, + "HCLK_BRAM_CK_IN1": null, + "HCLK_BRAM_CK_IN10": null, + "HCLK_BRAM_CK_IN11": null, + "HCLK_BRAM_CK_IN12": null, + "HCLK_BRAM_CK_IN13": null, + "HCLK_BRAM_CK_IN2": null, + "HCLK_BRAM_CK_IN3": null, + "HCLK_BRAM_CK_IN4": null, + "HCLK_BRAM_CK_IN5": null, + "HCLK_BRAM_CK_IN6": null, + "HCLK_BRAM_CK_IN7": null, + "HCLK_BRAM_CK_IN8": null, + "HCLK_BRAM_CK_IN9": null, + "HCLK_BRAM_PMVBRAM_O": null, + "HCLK_BRAM_PMVBRAM_ODIV2": null, + "HCLK_BRAM_PMVBRAM_ODIV4": null, + "HCLK_BRAM_PMVBRAM_SELECT1": null, + "HCLK_BRAM_PMVBRAM_SELECT2": null, + "HCLK_BRAM_PMVBRAM_SELECT3": null, + "HCLK_BRAM_PMVBRAM_SELECT4": null + } } diff --git a/kintex7/tile_type_HCLK_CLB.json b/kintex7/tile_type_HCLK_CLB.json index d435e59..8bca17d 100644 --- a/kintex7/tile_type_HCLK_CLB.json +++ b/kintex7/tile_type_HCLK_CLB.json @@ -2,48 +2,60 @@ "pips": {}, "sites": [], "tile_type": "HCLK_CLB", - "wires": [ - "HCLK_CLB_CK_BUFHCLK0", - "HCLK_CLB_CK_BUFHCLK1", - "HCLK_CLB_CK_BUFHCLK10", - "HCLK_CLB_CK_BUFHCLK11", - "HCLK_CLB_CK_BUFHCLK2", - "HCLK_CLB_CK_BUFHCLK3", - "HCLK_CLB_CK_BUFHCLK4", - "HCLK_CLB_CK_BUFHCLK5", - "HCLK_CLB_CK_BUFHCLK6", - "HCLK_CLB_CK_BUFHCLK7", - "HCLK_CLB_CK_BUFHCLK8", - "HCLK_CLB_CK_BUFHCLK9", - "HCLK_CLB_CK_BUFRCLK0", - "HCLK_CLB_CK_BUFRCLK1", - "HCLK_CLB_CK_BUFRCLK2", - "HCLK_CLB_CK_BUFRCLK3", - "HCLK_CLB_CK_IN0", - "HCLK_CLB_CK_IN1", - "HCLK_CLB_CK_IN10", - "HCLK_CLB_CK_IN11", - "HCLK_CLB_CK_IN12", - "HCLK_CLB_CK_IN13", - "HCLK_CLB_CK_IN2", - "HCLK_CLB_CK_IN3", - "HCLK_CLB_CK_IN4", - "HCLK_CLB_CK_IN5", - "HCLK_CLB_CK_IN6", - "HCLK_CLB_CK_IN7", - "HCLK_CLB_CK_IN8", - "HCLK_CLB_CK_IN9", - "HCLK_CLB_COUT0_L", - "HCLK_CLB_COUT0_R", - "HCLK_CLB_COUT1_L", - "HCLK_CLB_COUT1_R", - "HCLK_CLB_PERFCLK0", - "HCLK_CLB_PERFCLK1", - "HCLK_CLB_PERFCLK2", - "HCLK_CLB_PERFCLK3", - "HCLK_CLB_REFCK_EASTCLK0", - "HCLK_CLB_REFCK_EASTCLK1", - "HCLK_CLB_REFCK_WESTCLK0", - "HCLK_CLB_REFCK_WESTCLK1" - ] + "wires": { + "HCLK_CLB_CK_BUFHCLK0": null, + "HCLK_CLB_CK_BUFHCLK1": null, + "HCLK_CLB_CK_BUFHCLK10": null, + "HCLK_CLB_CK_BUFHCLK11": null, + "HCLK_CLB_CK_BUFHCLK2": null, + "HCLK_CLB_CK_BUFHCLK3": null, + "HCLK_CLB_CK_BUFHCLK4": null, + "HCLK_CLB_CK_BUFHCLK5": null, + "HCLK_CLB_CK_BUFHCLK6": null, + "HCLK_CLB_CK_BUFHCLK7": null, + "HCLK_CLB_CK_BUFHCLK8": null, + "HCLK_CLB_CK_BUFHCLK9": null, + "HCLK_CLB_CK_BUFRCLK0": null, + "HCLK_CLB_CK_BUFRCLK1": null, + "HCLK_CLB_CK_BUFRCLK2": null, + "HCLK_CLB_CK_BUFRCLK3": null, + "HCLK_CLB_CK_IN0": null, + "HCLK_CLB_CK_IN1": null, + "HCLK_CLB_CK_IN10": null, + "HCLK_CLB_CK_IN11": null, + "HCLK_CLB_CK_IN12": null, + "HCLK_CLB_CK_IN13": null, + "HCLK_CLB_CK_IN2": null, + "HCLK_CLB_CK_IN3": null, + "HCLK_CLB_CK_IN4": null, + "HCLK_CLB_CK_IN5": null, + "HCLK_CLB_CK_IN6": null, + "HCLK_CLB_CK_IN7": null, + "HCLK_CLB_CK_IN8": null, + "HCLK_CLB_CK_IN9": null, + "HCLK_CLB_COUT0_L": { + "cap": "10.383", + "res": "0.000" + }, + "HCLK_CLB_COUT0_R": { + "cap": "10.383", + "res": "0.000" + }, + "HCLK_CLB_COUT1_L": { + "cap": "10.383", + "res": "0.000" + }, + "HCLK_CLB_COUT1_R": { + "cap": "10.383", + "res": "0.000" + }, + "HCLK_CLB_PERFCLK0": null, + "HCLK_CLB_PERFCLK1": null, + "HCLK_CLB_PERFCLK2": null, + "HCLK_CLB_PERFCLK3": null, + "HCLK_CLB_REFCK_EASTCLK0": null, + "HCLK_CLB_REFCK_EASTCLK1": null, + "HCLK_CLB_REFCK_WESTCLK0": null, + "HCLK_CLB_REFCK_WESTCLK1": null + } } diff --git a/kintex7/tile_type_HCLK_CMT.json b/kintex7/tile_type_HCLK_CMT.json index d71515f..e5d92fb 100644 --- a/kintex7/tile_type_HCLK_CMT.json +++ b/kintex7/tile_type_HCLK_CMT.json @@ -2,6876 +2,27478 @@ "pips": { "HCLK_CMT.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_BUFMRCE_O0" }, "HCLK_CMT.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_BUFMRCE_O1" }, "HCLK_CMT.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_CMT_BUFMR_CE0" }, "HCLK_CMT.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_CMT_BUFMR_CE1" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.178", + "0.205", + "0.443", + "0.511" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.178", + "0.205", + "0.443", + "0.511" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT.HCLK_CMT_CCIO0->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + 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"src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK1" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK1->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.199", + 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"res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK10->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK10" }, 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"0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, 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"HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK11->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK11" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_0": { 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"in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK2->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": 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"HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ 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"src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_7": { 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": 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"res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, 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"in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ 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"0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", 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"0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": 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"0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK5" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_10": { 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"in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + 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"0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK6" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_10": { 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"in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK7->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", 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}, "src_wire": "HCLK_CMT_CK_BUFHCLK7" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_10": { 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"in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ 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"HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ 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"0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK9" }, "HCLK_CMT.HCLK_CMT_CK_BUFHCLK9->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP1", 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"0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM11->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM11" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM12" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM12->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + 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}, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM13->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM13" }, 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"in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, 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"in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM3->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM3" }, 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null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, 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null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM4->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { 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"in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM7->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM7" }, 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null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, 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"in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM8->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM8" }, 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}, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, 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"in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_MMCM9->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, 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"delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM9" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": 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null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL0->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL0" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL1->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", 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"res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL1" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", 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"res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_MUX_CLK_9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_MUX_CLK_9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0" }, "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0" }, "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1" }, "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1" }, "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2" }, "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2" }, "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3" }, "HCLK_CMT.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3" }, "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0" }, "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1" }, "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2" }, "HCLK_CMT.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" } }, @@ -6880,9 +27482,36 @@ "name": "X0Y1", "prefix": "BUFMRCE", "site_pins": { - "CE": "HCLK_CMT_BUFMRCE_CEINP1", - "I": "HCLK_CMT_BUFMR_INP1", - "O": "HCLK_CMT_BUFMRCE_O1" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_CMT_BUFMRCE_CEINP1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_CMT_BUFMR_INP1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_CMT_BUFMRCE_O1" + } }, "type": "BUFMRCE", "x_coord": 0, @@ -6892,9 +27521,36 @@ "name": "X0Y0", "prefix": "BUFMRCE", "site_pins": { - "CE": "HCLK_CMT_BUFMRCE_CEINP0", - "I": "HCLK_CMT_BUFMR_INP0", - "O": "HCLK_CMT_BUFMRCE_O0" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_CMT_BUFMRCE_CEINP0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_CMT_BUFMR_INP0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_CMT_BUFMRCE_O0" + } }, "type": "BUFMRCE", "x_coord": 0, @@ -6902,166 +27558,166 @@ } ], "tile_type": "HCLK_CMT", - "wires": [ - "HCLK_CMT_BUFMRCE_CEINP0", - "HCLK_CMT_BUFMRCE_CEINP1", - "HCLK_CMT_BUFMRCE_O0", - "HCLK_CMT_BUFMRCE_O1", - "HCLK_CMT_BUFMR_CE0", - "HCLK_CMT_BUFMR_CE1", - "HCLK_CMT_BUFMR_INP0", - "HCLK_CMT_BUFMR_INP1", - "HCLK_CMT_BUFMR_PHASEREF0", - "HCLK_CMT_BUFMR_PHASEREF1", - "HCLK_CMT_CCIO0", - "HCLK_CMT_CCIO1", - "HCLK_CMT_CCIO2", - "HCLK_CMT_CCIO3", - "HCLK_CMT_CK_BUFHCLK0", - "HCLK_CMT_CK_BUFHCLK1", - "HCLK_CMT_CK_BUFHCLK10", - "HCLK_CMT_CK_BUFHCLK11", - "HCLK_CMT_CK_BUFHCLK2", - "HCLK_CMT_CK_BUFHCLK3", - "HCLK_CMT_CK_BUFHCLK4", - "HCLK_CMT_CK_BUFHCLK5", - "HCLK_CMT_CK_BUFHCLK6", - "HCLK_CMT_CK_BUFHCLK7", - "HCLK_CMT_CK_BUFHCLK8", - "HCLK_CMT_CK_BUFHCLK9", - "HCLK_CMT_CK_BUFRCLK0", - "HCLK_CMT_CK_BUFRCLK1", - "HCLK_CMT_CK_BUFRCLK2", - "HCLK_CMT_CK_BUFRCLK3", - "HCLK_CMT_CK_IN0", - "HCLK_CMT_CK_IN1", - "HCLK_CMT_CK_IN10", - "HCLK_CMT_CK_IN11", - "HCLK_CMT_CK_IN12", - "HCLK_CMT_CK_IN13", - "HCLK_CMT_CK_IN2", - "HCLK_CMT_CK_IN3", - "HCLK_CMT_CK_IN4", - "HCLK_CMT_CK_IN5", - "HCLK_CMT_CK_IN6", - "HCLK_CMT_CK_IN7", - "HCLK_CMT_CK_IN8", - "HCLK_CMT_CK_IN9", - "HCLK_CMT_ECALIB0", - "HCLK_CMT_ECALIB1", - "HCLK_CMT_FREQ_PHASER_REFMUX_0", - "HCLK_CMT_FREQ_PHASER_REFMUX_1", - "HCLK_CMT_FREQ_PHASER_REFMUX_2", - "HCLK_CMT_FREQ_REF_NS0", - "HCLK_CMT_FREQ_REF_NS1", - "HCLK_CMT_FREQ_REF_NS2", - "HCLK_CMT_FREQ_REF_NS3", - "HCLK_CMT_IBURST0", - "HCLK_CMT_IBURST1", - "HCLK_CMT_IBURSTPENDING0", - "HCLK_CMT_IBURSTPENDING1", - "HCLK_CMT_MUX_CLKINT_0", - "HCLK_CMT_MUX_CLKINT_1", - "HCLK_CMT_MUX_CLKINT_2", - "HCLK_CMT_MUX_CLKINT_3", - "HCLK_CMT_MUX_CLK_0", - "HCLK_CMT_MUX_CLK_1", - "HCLK_CMT_MUX_CLK_10", - "HCLK_CMT_MUX_CLK_11", - "HCLK_CMT_MUX_CLK_12", - "HCLK_CMT_MUX_CLK_13", - "HCLK_CMT_MUX_CLK_2", - "HCLK_CMT_MUX_CLK_3", - "HCLK_CMT_MUX_CLK_4", - "HCLK_CMT_MUX_CLK_5", - "HCLK_CMT_MUX_CLK_6", - "HCLK_CMT_MUX_CLK_7", - "HCLK_CMT_MUX_CLK_8", - "HCLK_CMT_MUX_CLK_9", - "HCLK_CMT_MUX_CLK_LEAF_DN0", - "HCLK_CMT_MUX_CLK_LEAF_DN1", - "HCLK_CMT_MUX_CLK_LEAF_UP0", - "HCLK_CMT_MUX_CLK_LEAF_UP1", - "HCLK_CMT_MUX_CLK_MMCM0", - "HCLK_CMT_MUX_CLK_MMCM1", - "HCLK_CMT_MUX_CLK_MMCM10", - "HCLK_CMT_MUX_CLK_MMCM11", - "HCLK_CMT_MUX_CLK_MMCM12", - "HCLK_CMT_MUX_CLK_MMCM13", - "HCLK_CMT_MUX_CLK_MMCM2", - "HCLK_CMT_MUX_CLK_MMCM3", - "HCLK_CMT_MUX_CLK_MMCM4", - "HCLK_CMT_MUX_CLK_MMCM5", - "HCLK_CMT_MUX_CLK_MMCM6", - "HCLK_CMT_MUX_CLK_MMCM7", - "HCLK_CMT_MUX_CLK_MMCM8", - "HCLK_CMT_MUX_CLK_MMCM9", - "HCLK_CMT_MUX_CLK_PLL0", - "HCLK_CMT_MUX_CLK_PLL1", - "HCLK_CMT_MUX_CLK_PLL2", - "HCLK_CMT_MUX_CLK_PLL3", - "HCLK_CMT_MUX_CLK_PLL4", - "HCLK_CMT_MUX_CLK_PLL5", - "HCLK_CMT_MUX_CLK_PLL6", - "HCLK_CMT_MUX_CLK_PLL7", - "HCLK_CMT_MUX_MMCM_CLKFBIN", - "HCLK_CMT_MUX_MMCM_CLKIN1", - "HCLK_CMT_MUX_MMCM_CLKIN2", - "HCLK_CMT_MUX_MMCM_MUXED0", - "HCLK_CMT_MUX_MMCM_MUXED1", - "HCLK_CMT_MUX_MMCM_MUXED2", - "HCLK_CMT_MUX_MMCM_MUXED3", - "HCLK_CMT_MUX_OUT_FREQ_REF0", - "HCLK_CMT_MUX_OUT_FREQ_REF1", - "HCLK_CMT_MUX_OUT_FREQ_REF2", - "HCLK_CMT_MUX_OUT_FREQ_REF3", - "HCLK_CMT_MUX_PHSR_PERFCLK0", - "HCLK_CMT_MUX_PHSR_PERFCLK1", - "HCLK_CMT_MUX_PHSR_PERFCLK2", - "HCLK_CMT_MUX_PHSR_PERFCLK3", - "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "HCLK_CMT_MUX_PLLE2_CLKIN1", - "HCLK_CMT_MUX_PLLE2_CLKIN2", - "HCLK_CMT_OBURSTPENDING0", - "HCLK_CMT_OBURSTPENDING1", - "HCLK_CMT_PHASEREF_ABOVE0", - "HCLK_CMT_PHASEREF_ABOVE1", - "HCLK_CMT_PHASEREF_BELOW0", - "HCLK_CMT_PHASEREF_BELOW1", - "HCLK_CMT_PHASERINA_ICLK", - "HCLK_CMT_PHASERINA_ICLKDIV", - "HCLK_CMT_PHASERINB_ICLK", - "HCLK_CMT_PHASERINB_ICLKDIV", - "HCLK_CMT_PHASERINC_ICLK", - "HCLK_CMT_PHASERINC_ICLKDIV", - "HCLK_CMT_PHASERIND_ICLK", - "HCLK_CMT_PHASERIND_ICLKDIV", - "HCLK_CMT_PHASERIN_RCLK0", - "HCLK_CMT_PHASERIN_RCLK1", - "HCLK_CMT_PHASERIN_RCLK2", - "HCLK_CMT_PHASERIN_RCLK3", - "HCLK_CMT_PHASEROUTA_OCLK", - "HCLK_CMT_PHASEROUTA_OCLK1X_90", - "HCLK_CMT_PHASEROUTA_OCLKDIV", - "HCLK_CMT_PHASEROUTB_OCLK", - "HCLK_CMT_PHASEROUTB_OCLK1X_90", - "HCLK_CMT_PHASEROUTB_OCLKDIV", - "HCLK_CMT_PHASEROUTC_OCLK", - "HCLK_CMT_PHASEROUTC_OCLK1X_90", - "HCLK_CMT_PHASEROUTC_OCLKDIV", - "HCLK_CMT_PHASEROUTD_OCLK", - "HCLK_CMT_PHASEROUTD_OCLK1X_90", - "HCLK_CMT_PHASEROUTD_OCLKDIV", - "HCLK_CMT_PHY_CONTROL_IRANKA0", - "HCLK_CMT_PHY_CONTROL_IRANKA1", - "HCLK_CMT_PHY_CONTROL_IRANKB0", - "HCLK_CMT_PHY_CONTROL_IRANKB1", - "HCLK_CMT_PHY_SYNC_BB", - "HCLK_CMT_PREF_BOUNCE0", - "HCLK_CMT_PREF_BOUNCE1", - "HCLK_CMT_PREF_BOUNCE2", - "HCLK_CMT_PREF_BOUNCE3", - "HCLK_CMT_PREF_CLKOUT", - "HCLK_CMT_PREF_TMUXOUT" - ] + "wires": { + "HCLK_CMT_BUFMRCE_CEINP0": null, + "HCLK_CMT_BUFMRCE_CEINP1": null, + "HCLK_CMT_BUFMRCE_O0": null, + "HCLK_CMT_BUFMRCE_O1": null, + "HCLK_CMT_BUFMR_CE0": null, + "HCLK_CMT_BUFMR_CE1": null, + "HCLK_CMT_BUFMR_INP0": null, + "HCLK_CMT_BUFMR_INP1": null, + "HCLK_CMT_BUFMR_PHASEREF0": null, + "HCLK_CMT_BUFMR_PHASEREF1": null, + "HCLK_CMT_CCIO0": null, + "HCLK_CMT_CCIO1": null, + "HCLK_CMT_CCIO2": null, + "HCLK_CMT_CCIO3": null, + "HCLK_CMT_CK_BUFHCLK0": null, + "HCLK_CMT_CK_BUFHCLK1": null, + "HCLK_CMT_CK_BUFHCLK10": null, + "HCLK_CMT_CK_BUFHCLK11": null, + "HCLK_CMT_CK_BUFHCLK2": null, + "HCLK_CMT_CK_BUFHCLK3": null, + "HCLK_CMT_CK_BUFHCLK4": null, + "HCLK_CMT_CK_BUFHCLK5": null, + "HCLK_CMT_CK_BUFHCLK6": null, + "HCLK_CMT_CK_BUFHCLK7": null, + "HCLK_CMT_CK_BUFHCLK8": null, + "HCLK_CMT_CK_BUFHCLK9": null, + "HCLK_CMT_CK_BUFRCLK0": null, + "HCLK_CMT_CK_BUFRCLK1": null, + "HCLK_CMT_CK_BUFRCLK2": null, + "HCLK_CMT_CK_BUFRCLK3": null, + "HCLK_CMT_CK_IN0": null, + "HCLK_CMT_CK_IN1": null, + "HCLK_CMT_CK_IN10": null, + "HCLK_CMT_CK_IN11": null, + "HCLK_CMT_CK_IN12": null, + "HCLK_CMT_CK_IN13": null, + "HCLK_CMT_CK_IN2": null, + "HCLK_CMT_CK_IN3": null, + "HCLK_CMT_CK_IN4": null, + "HCLK_CMT_CK_IN5": null, + "HCLK_CMT_CK_IN6": null, + "HCLK_CMT_CK_IN7": null, + "HCLK_CMT_CK_IN8": null, + "HCLK_CMT_CK_IN9": null, + "HCLK_CMT_ECALIB0": null, + "HCLK_CMT_ECALIB1": null, + "HCLK_CMT_FREQ_PHASER_REFMUX_0": null, + "HCLK_CMT_FREQ_PHASER_REFMUX_1": null, + "HCLK_CMT_FREQ_PHASER_REFMUX_2": null, + "HCLK_CMT_FREQ_REF_NS0": null, + "HCLK_CMT_FREQ_REF_NS1": null, + "HCLK_CMT_FREQ_REF_NS2": null, + "HCLK_CMT_FREQ_REF_NS3": null, + "HCLK_CMT_IBURST0": null, + "HCLK_CMT_IBURST1": null, + "HCLK_CMT_IBURSTPENDING0": null, + "HCLK_CMT_IBURSTPENDING1": null, + "HCLK_CMT_MUX_CLKINT_0": null, + "HCLK_CMT_MUX_CLKINT_1": null, + "HCLK_CMT_MUX_CLKINT_2": null, + "HCLK_CMT_MUX_CLKINT_3": null, + "HCLK_CMT_MUX_CLK_0": null, + "HCLK_CMT_MUX_CLK_1": null, + "HCLK_CMT_MUX_CLK_10": null, + "HCLK_CMT_MUX_CLK_11": null, + "HCLK_CMT_MUX_CLK_12": null, + "HCLK_CMT_MUX_CLK_13": null, + "HCLK_CMT_MUX_CLK_2": null, + "HCLK_CMT_MUX_CLK_3": null, + "HCLK_CMT_MUX_CLK_4": null, + "HCLK_CMT_MUX_CLK_5": null, + "HCLK_CMT_MUX_CLK_6": null, + "HCLK_CMT_MUX_CLK_7": null, + "HCLK_CMT_MUX_CLK_8": null, + "HCLK_CMT_MUX_CLK_9": null, + "HCLK_CMT_MUX_CLK_LEAF_DN0": null, + "HCLK_CMT_MUX_CLK_LEAF_DN1": null, + "HCLK_CMT_MUX_CLK_LEAF_UP0": null, + "HCLK_CMT_MUX_CLK_LEAF_UP1": null, + "HCLK_CMT_MUX_CLK_MMCM0": null, + "HCLK_CMT_MUX_CLK_MMCM1": null, + "HCLK_CMT_MUX_CLK_MMCM10": null, + "HCLK_CMT_MUX_CLK_MMCM11": null, + "HCLK_CMT_MUX_CLK_MMCM12": null, + "HCLK_CMT_MUX_CLK_MMCM13": null, + "HCLK_CMT_MUX_CLK_MMCM2": null, + "HCLK_CMT_MUX_CLK_MMCM3": null, + "HCLK_CMT_MUX_CLK_MMCM4": null, + "HCLK_CMT_MUX_CLK_MMCM5": null, + "HCLK_CMT_MUX_CLK_MMCM6": null, + "HCLK_CMT_MUX_CLK_MMCM7": null, + "HCLK_CMT_MUX_CLK_MMCM8": null, + "HCLK_CMT_MUX_CLK_MMCM9": null, + "HCLK_CMT_MUX_CLK_PLL0": null, + "HCLK_CMT_MUX_CLK_PLL1": null, + "HCLK_CMT_MUX_CLK_PLL2": null, + "HCLK_CMT_MUX_CLK_PLL3": null, + "HCLK_CMT_MUX_CLK_PLL4": null, + "HCLK_CMT_MUX_CLK_PLL5": null, + "HCLK_CMT_MUX_CLK_PLL6": null, + "HCLK_CMT_MUX_CLK_PLL7": null, + "HCLK_CMT_MUX_MMCM_CLKFBIN": null, + "HCLK_CMT_MUX_MMCM_CLKIN1": null, + "HCLK_CMT_MUX_MMCM_CLKIN2": null, + "HCLK_CMT_MUX_MMCM_MUXED0": null, + "HCLK_CMT_MUX_MMCM_MUXED1": null, + "HCLK_CMT_MUX_MMCM_MUXED2": null, + "HCLK_CMT_MUX_MMCM_MUXED3": null, + "HCLK_CMT_MUX_OUT_FREQ_REF0": null, + "HCLK_CMT_MUX_OUT_FREQ_REF1": null, + "HCLK_CMT_MUX_OUT_FREQ_REF2": null, + "HCLK_CMT_MUX_OUT_FREQ_REF3": null, + "HCLK_CMT_MUX_PHSR_PERFCLK0": null, + "HCLK_CMT_MUX_PHSR_PERFCLK1": null, + "HCLK_CMT_MUX_PHSR_PERFCLK2": null, + "HCLK_CMT_MUX_PHSR_PERFCLK3": null, + "HCLK_CMT_MUX_PLLE2_CLKFBIN": null, + "HCLK_CMT_MUX_PLLE2_CLKIN1": null, + "HCLK_CMT_MUX_PLLE2_CLKIN2": null, + "HCLK_CMT_OBURSTPENDING0": null, + "HCLK_CMT_OBURSTPENDING1": null, + "HCLK_CMT_PHASEREF_ABOVE0": null, + "HCLK_CMT_PHASEREF_ABOVE1": null, + "HCLK_CMT_PHASEREF_BELOW0": null, + "HCLK_CMT_PHASEREF_BELOW1": null, + "HCLK_CMT_PHASERINA_ICLK": null, + "HCLK_CMT_PHASERINA_ICLKDIV": null, + "HCLK_CMT_PHASERINB_ICLK": null, + "HCLK_CMT_PHASERINB_ICLKDIV": null, + "HCLK_CMT_PHASERINC_ICLK": null, + "HCLK_CMT_PHASERINC_ICLKDIV": null, + "HCLK_CMT_PHASERIND_ICLK": null, + "HCLK_CMT_PHASERIND_ICLKDIV": null, + "HCLK_CMT_PHASERIN_RCLK0": null, + "HCLK_CMT_PHASERIN_RCLK1": null, + "HCLK_CMT_PHASERIN_RCLK2": null, + "HCLK_CMT_PHASERIN_RCLK3": null, + "HCLK_CMT_PHASEROUTA_OCLK": null, + "HCLK_CMT_PHASEROUTA_OCLK1X_90": null, + "HCLK_CMT_PHASEROUTA_OCLKDIV": null, + "HCLK_CMT_PHASEROUTB_OCLK": null, + "HCLK_CMT_PHASEROUTB_OCLK1X_90": null, + "HCLK_CMT_PHASEROUTB_OCLKDIV": null, + "HCLK_CMT_PHASEROUTC_OCLK": null, + "HCLK_CMT_PHASEROUTC_OCLK1X_90": null, + "HCLK_CMT_PHASEROUTC_OCLKDIV": null, + "HCLK_CMT_PHASEROUTD_OCLK": null, + "HCLK_CMT_PHASEROUTD_OCLK1X_90": null, + "HCLK_CMT_PHASEROUTD_OCLKDIV": null, + "HCLK_CMT_PHY_CONTROL_IRANKA0": null, + "HCLK_CMT_PHY_CONTROL_IRANKA1": null, + "HCLK_CMT_PHY_CONTROL_IRANKB0": null, + "HCLK_CMT_PHY_CONTROL_IRANKB1": null, + "HCLK_CMT_PHY_SYNC_BB": null, + "HCLK_CMT_PREF_BOUNCE0": null, + "HCLK_CMT_PREF_BOUNCE1": null, + "HCLK_CMT_PREF_BOUNCE2": null, + "HCLK_CMT_PREF_BOUNCE3": null, + "HCLK_CMT_PREF_CLKOUT": null, + "HCLK_CMT_PREF_TMUXOUT": null + } } diff --git a/kintex7/tile_type_HCLK_CMT_L.json b/kintex7/tile_type_HCLK_CMT_L.json index 59a5956..d351c8b 100644 --- a/kintex7/tile_type_HCLK_CMT_L.json +++ b/kintex7/tile_type_HCLK_CMT_L.json @@ -2,6876 +2,27478 @@ "pips": { "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O0->>HCLK_CMT_BUFMR_PHASEREF0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_PHASEREF0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_BUFMRCE_O0" }, "HCLK_CMT_L.HCLK_CMT_BUFMRCE_O1->>HCLK_CMT_BUFMR_PHASEREF1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_PHASEREF1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_BUFMRCE_O1" }, "HCLK_CMT_L.HCLK_CMT_BUFMR_CE0->HCLK_CMT_BUFMRCE_CEINP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_CMT_BUFMRCE_CEINP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_CMT_BUFMR_CE0" }, "HCLK_CMT_L.HCLK_CMT_BUFMR_CE1->HCLK_CMT_BUFMRCE_CEINP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_CMT_BUFMRCE_CEINP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_CMT_BUFMR_CE1" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.178", + "0.205", + "0.443", + "0.511" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.178", + "0.205", + "0.443", + "0.511" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.327", + "0.353", + "0.625", + "0.676" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CCIO0" }, "HCLK_CMT_L.HCLK_CMT_CCIO0->>HCLK_CMT_CK_IN4": { "can_invert": "0", + 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"src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK0" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK0->>HCLK_CMT_CK_IN9": { "can_invert": "0", + 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"0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK2" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK3" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK3->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], 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"0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": 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"dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.199", + "0.225", + "0.443", + "0.493" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK4" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.205", + "0.232", + "0.463", + "0.516" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": 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"HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.104", + "0.117", + "0.238", + "0.266" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_DN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_DN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_CLK_LEAF_UP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_CK_BUFHCLK8" }, "HCLK_CMT_L.HCLK_CMT_CK_BUFHCLK8->>HCLK_CMT_MUX_CLK_LEAF_UP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"0.184", + "0.406", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.163", + "0.184", + "0.406", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.201", + "0.228", + "0.391", + "0.440" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.201", + "0.228", + "0.391", + "0.440" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_1" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_1->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.201", + "0.228", + "0.391", + "0.440" + ], + "in_cap": "0.000", + "res": "0.0" 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"is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.163", + "0.184", + "0.406", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLKINT_3->>HCLK_CMT_MUX_OUT_FREQ_REF3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.163", + "0.184", + "0.406", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.163", + "0.184", + "0.406", + "0.452" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLKINT_3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN11": { 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null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, 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"res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_10" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_10->>HCLK_CMT_CK_IN8": { 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}, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_11" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_11->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + 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"0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_12" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_12->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { 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"HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_13" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_13->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { 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"0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_4->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_5->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, 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"0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_MMCM_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_MMCM_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_6->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_BUFMR_INP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_BUFMR_INP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.152", + "0.172", + "0.356", + "0.397" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_7->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + 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"is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, 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"0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_8" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_8->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.099", + "0.112", + "0.230", + "0.257" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_MMCM_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.192", + "0.217", + "0.432", + "0.482" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKFBIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKFBIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_9->>HCLK_CMT_MUX_PLLE2_CLKIN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PLLE2_CLKIN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.203", + "0.230", + "0.460", + "0.513" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_CLK_9" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM0->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM0" }, 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null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM2->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM2" }, 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null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM5->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.229", + "0.259", + "0.530", + "0.591" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_MMCM5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_MMCM6->>HCLK_CMT_CK_IN0": { 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}, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL2->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL2" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN0": { 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null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, 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null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, 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"0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL3->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL3" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + 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null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL4->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL4" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, 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"0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": 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"delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL5->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL5" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN3": { 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null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL6->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL6" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN12": { "can_invert": "0", + "dst_to_src": { + "delay": [ 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"HCLK_CMT_CK_IN2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_CLK_PLL7->>HCLK_CMT_CK_IN9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_CK_IN9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.247", + "0.279", + "0.528", + "0.589" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_CLK_PLL7" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED0" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED1" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED2" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3" }, "HCLK_CMT_L.HCLK_CMT_MUX_MMCM_MUXED3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.365", + "0.412", + "0.744", + "0.830" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_MUX_MMCM_MUXED3" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF0->>HCLK_CMT_FREQ_REF_NS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF0" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF1->>HCLK_CMT_FREQ_REF_NS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF1" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF2->>HCLK_CMT_FREQ_REF_NS2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF2" }, "HCLK_CMT_L.HCLK_CMT_MUX_OUT_FREQ_REF3->>HCLK_CMT_FREQ_REF_NS3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_CMT_FREQ_REF_NS3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CMT_MUX_OUT_FREQ_REF3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK0->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK0" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK1->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK1" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK2->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK2" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" }, "HCLK_CMT_L.HCLK_CMT_PHASERIN_RCLK3->>HCLK_CMT_MUX_PHSR_PERFCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CMT_MUX_PHSR_PERFCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.180", + "0.203", + "0.383", + "0.427" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CMT_PHASERIN_RCLK3" } }, @@ -6880,9 +27482,36 @@ "name": "X0Y1", "prefix": "BUFMRCE", "site_pins": { - "CE": "HCLK_CMT_BUFMRCE_CEINP1", - "I": "HCLK_CMT_BUFMR_INP1", - "O": "HCLK_CMT_BUFMRCE_O1" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_CMT_BUFMRCE_CEINP1" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_CMT_BUFMR_INP1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_CMT_BUFMRCE_O1" + } }, "type": "BUFMRCE", "x_coord": 0, @@ -6892,9 +27521,36 @@ "name": "X0Y0", "prefix": "BUFMRCE", "site_pins": { - "CE": "HCLK_CMT_BUFMRCE_CEINP0", - "I": "HCLK_CMT_BUFMR_INP0", - "O": "HCLK_CMT_BUFMRCE_O0" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_CMT_BUFMRCE_CEINP0" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_CMT_BUFMR_INP0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_CMT_BUFMRCE_O0" + } }, "type": "BUFMRCE", "x_coord": 0, @@ -6902,146 +27558,146 @@ } ], "tile_type": "HCLK_CMT_L", - "wires": [ - "HCLK_CMT_BUFMRCE_CEINP0", - "HCLK_CMT_BUFMRCE_CEINP1", - "HCLK_CMT_BUFMRCE_O0", - "HCLK_CMT_BUFMRCE_O1", - "HCLK_CMT_BUFMR_CE0", - "HCLK_CMT_BUFMR_CE1", - "HCLK_CMT_BUFMR_INP0", - "HCLK_CMT_BUFMR_INP1", - "HCLK_CMT_BUFMR_PHASEREF0", - "HCLK_CMT_BUFMR_PHASEREF1", - "HCLK_CMT_CCIO0", - "HCLK_CMT_CCIO1", - "HCLK_CMT_CCIO2", - "HCLK_CMT_CCIO3", - "HCLK_CMT_CK_BUFHCLK0", - "HCLK_CMT_CK_BUFHCLK1", - "HCLK_CMT_CK_BUFHCLK10", - "HCLK_CMT_CK_BUFHCLK11", - "HCLK_CMT_CK_BUFHCLK2", - "HCLK_CMT_CK_BUFHCLK3", - "HCLK_CMT_CK_BUFHCLK4", - "HCLK_CMT_CK_BUFHCLK5", - "HCLK_CMT_CK_BUFHCLK6", - "HCLK_CMT_CK_BUFHCLK7", - "HCLK_CMT_CK_BUFHCLK8", - "HCLK_CMT_CK_BUFHCLK9", - "HCLK_CMT_CK_BUFRCLK0", - "HCLK_CMT_CK_BUFRCLK1", - "HCLK_CMT_CK_BUFRCLK2", - "HCLK_CMT_CK_BUFRCLK3", - "HCLK_CMT_CK_IN0", - "HCLK_CMT_CK_IN1", - "HCLK_CMT_CK_IN10", - "HCLK_CMT_CK_IN11", - "HCLK_CMT_CK_IN12", - "HCLK_CMT_CK_IN13", - "HCLK_CMT_CK_IN2", - "HCLK_CMT_CK_IN3", - "HCLK_CMT_CK_IN4", - "HCLK_CMT_CK_IN5", - "HCLK_CMT_CK_IN6", - "HCLK_CMT_CK_IN7", - "HCLK_CMT_CK_IN8", - "HCLK_CMT_CK_IN9", - "HCLK_CMT_ECALIB0", - "HCLK_CMT_ECALIB1", - "HCLK_CMT_FREQ_PHASER_REFMUX_0", - "HCLK_CMT_FREQ_PHASER_REFMUX_1", - "HCLK_CMT_FREQ_PHASER_REFMUX_2", - "HCLK_CMT_FREQ_REF_NS0", - "HCLK_CMT_FREQ_REF_NS1", - "HCLK_CMT_FREQ_REF_NS2", - "HCLK_CMT_FREQ_REF_NS3", - "HCLK_CMT_IBURST0", - "HCLK_CMT_IBURST1", - "HCLK_CMT_IBURSTPENDING0", - "HCLK_CMT_IBURSTPENDING1", - "HCLK_CMT_MUX_CLKINT_0", - "HCLK_CMT_MUX_CLKINT_1", - "HCLK_CMT_MUX_CLKINT_2", - "HCLK_CMT_MUX_CLKINT_3", - "HCLK_CMT_MUX_CLK_0", - "HCLK_CMT_MUX_CLK_1", - "HCLK_CMT_MUX_CLK_10", - "HCLK_CMT_MUX_CLK_11", - "HCLK_CMT_MUX_CLK_12", - "HCLK_CMT_MUX_CLK_13", - "HCLK_CMT_MUX_CLK_2", - "HCLK_CMT_MUX_CLK_3", - "HCLK_CMT_MUX_CLK_4", - "HCLK_CMT_MUX_CLK_5", - "HCLK_CMT_MUX_CLK_6", - "HCLK_CMT_MUX_CLK_7", - "HCLK_CMT_MUX_CLK_8", - "HCLK_CMT_MUX_CLK_9", - "HCLK_CMT_MUX_CLK_LEAF_DN0", - "HCLK_CMT_MUX_CLK_LEAF_DN1", - "HCLK_CMT_MUX_CLK_LEAF_UP0", - "HCLK_CMT_MUX_CLK_LEAF_UP1", - "HCLK_CMT_MUX_CLK_MMCM0", - "HCLK_CMT_MUX_CLK_MMCM1", - "HCLK_CMT_MUX_CLK_MMCM10", - "HCLK_CMT_MUX_CLK_MMCM11", - "HCLK_CMT_MUX_CLK_MMCM12", - "HCLK_CMT_MUX_CLK_MMCM13", - "HCLK_CMT_MUX_CLK_MMCM2", - "HCLK_CMT_MUX_CLK_MMCM3", - "HCLK_CMT_MUX_CLK_MMCM4", - "HCLK_CMT_MUX_CLK_MMCM5", - "HCLK_CMT_MUX_CLK_MMCM6", - "HCLK_CMT_MUX_CLK_MMCM7", - "HCLK_CMT_MUX_CLK_MMCM8", - "HCLK_CMT_MUX_CLK_MMCM9", - "HCLK_CMT_MUX_CLK_PLL0", - "HCLK_CMT_MUX_CLK_PLL1", - "HCLK_CMT_MUX_CLK_PLL2", - "HCLK_CMT_MUX_CLK_PLL3", - "HCLK_CMT_MUX_CLK_PLL4", - "HCLK_CMT_MUX_CLK_PLL5", - "HCLK_CMT_MUX_CLK_PLL6", - "HCLK_CMT_MUX_CLK_PLL7", - "HCLK_CMT_MUX_MMCM_CLKFBIN", - "HCLK_CMT_MUX_MMCM_CLKIN1", - "HCLK_CMT_MUX_MMCM_CLKIN2", - "HCLK_CMT_MUX_MMCM_MUXED0", - "HCLK_CMT_MUX_MMCM_MUXED1", - "HCLK_CMT_MUX_MMCM_MUXED2", - "HCLK_CMT_MUX_MMCM_MUXED3", - "HCLK_CMT_MUX_OUT_FREQ_REF0", - "HCLK_CMT_MUX_OUT_FREQ_REF1", - "HCLK_CMT_MUX_OUT_FREQ_REF2", - "HCLK_CMT_MUX_OUT_FREQ_REF3", - "HCLK_CMT_MUX_PHSR_PERFCLK0", - "HCLK_CMT_MUX_PHSR_PERFCLK1", - "HCLK_CMT_MUX_PHSR_PERFCLK2", - "HCLK_CMT_MUX_PHSR_PERFCLK3", - "HCLK_CMT_MUX_PLLE2_CLKFBIN", - "HCLK_CMT_MUX_PLLE2_CLKIN1", - "HCLK_CMT_MUX_PLLE2_CLKIN2", - "HCLK_CMT_OBURSTPENDING0", - "HCLK_CMT_OBURSTPENDING1", - "HCLK_CMT_PHASEREF_ABOVE0", - "HCLK_CMT_PHASEREF_ABOVE1", - "HCLK_CMT_PHASEREF_BELOW0", - "HCLK_CMT_PHASEREF_BELOW1", - "HCLK_CMT_PHASERIN_RCLK0", - "HCLK_CMT_PHASERIN_RCLK1", - "HCLK_CMT_PHASERIN_RCLK2", - "HCLK_CMT_PHASERIN_RCLK3", - "HCLK_CMT_PHY_CONTROL_IRANKA0", - "HCLK_CMT_PHY_CONTROL_IRANKA1", - "HCLK_CMT_PHY_CONTROL_IRANKB0", - "HCLK_CMT_PHY_CONTROL_IRANKB1", - "HCLK_CMT_PHY_SYNC_BB", - "HCLK_CMT_PREF_BOUNCE0", - "HCLK_CMT_PREF_BOUNCE1", - "HCLK_CMT_PREF_BOUNCE2", - "HCLK_CMT_PREF_BOUNCE3", - "HCLK_CMT_PREF_CLKOUT", - "HCLK_CMT_PREF_TMUXOUT" - ] + "wires": { + "HCLK_CMT_BUFMRCE_CEINP0": null, + "HCLK_CMT_BUFMRCE_CEINP1": null, + "HCLK_CMT_BUFMRCE_O0": null, + "HCLK_CMT_BUFMRCE_O1": null, + "HCLK_CMT_BUFMR_CE0": null, + "HCLK_CMT_BUFMR_CE1": null, + "HCLK_CMT_BUFMR_INP0": null, + "HCLK_CMT_BUFMR_INP1": null, + "HCLK_CMT_BUFMR_PHASEREF0": null, + "HCLK_CMT_BUFMR_PHASEREF1": null, + "HCLK_CMT_CCIO0": null, + "HCLK_CMT_CCIO1": null, + "HCLK_CMT_CCIO2": null, + "HCLK_CMT_CCIO3": null, + "HCLK_CMT_CK_BUFHCLK0": null, + "HCLK_CMT_CK_BUFHCLK1": null, + "HCLK_CMT_CK_BUFHCLK10": null, + "HCLK_CMT_CK_BUFHCLK11": null, + "HCLK_CMT_CK_BUFHCLK2": null, + "HCLK_CMT_CK_BUFHCLK3": null, + "HCLK_CMT_CK_BUFHCLK4": null, + "HCLK_CMT_CK_BUFHCLK5": null, + "HCLK_CMT_CK_BUFHCLK6": null, + "HCLK_CMT_CK_BUFHCLK7": null, + "HCLK_CMT_CK_BUFHCLK8": null, + "HCLK_CMT_CK_BUFHCLK9": null, + "HCLK_CMT_CK_BUFRCLK0": null, + "HCLK_CMT_CK_BUFRCLK1": null, + "HCLK_CMT_CK_BUFRCLK2": null, + "HCLK_CMT_CK_BUFRCLK3": null, + "HCLK_CMT_CK_IN0": null, + "HCLK_CMT_CK_IN1": null, + "HCLK_CMT_CK_IN10": null, + "HCLK_CMT_CK_IN11": null, + "HCLK_CMT_CK_IN12": null, + "HCLK_CMT_CK_IN13": null, + "HCLK_CMT_CK_IN2": null, + "HCLK_CMT_CK_IN3": null, + "HCLK_CMT_CK_IN4": null, + "HCLK_CMT_CK_IN5": null, + "HCLK_CMT_CK_IN6": null, + "HCLK_CMT_CK_IN7": null, + "HCLK_CMT_CK_IN8": null, + "HCLK_CMT_CK_IN9": null, + "HCLK_CMT_ECALIB0": null, + "HCLK_CMT_ECALIB1": null, + "HCLK_CMT_FREQ_PHASER_REFMUX_0": null, + "HCLK_CMT_FREQ_PHASER_REFMUX_1": null, + "HCLK_CMT_FREQ_PHASER_REFMUX_2": null, + "HCLK_CMT_FREQ_REF_NS0": null, + "HCLK_CMT_FREQ_REF_NS1": null, + "HCLK_CMT_FREQ_REF_NS2": null, + "HCLK_CMT_FREQ_REF_NS3": null, + "HCLK_CMT_IBURST0": null, + "HCLK_CMT_IBURST1": null, + "HCLK_CMT_IBURSTPENDING0": null, + "HCLK_CMT_IBURSTPENDING1": null, + "HCLK_CMT_MUX_CLKINT_0": null, + "HCLK_CMT_MUX_CLKINT_1": null, + "HCLK_CMT_MUX_CLKINT_2": null, + "HCLK_CMT_MUX_CLKINT_3": null, + "HCLK_CMT_MUX_CLK_0": null, + "HCLK_CMT_MUX_CLK_1": null, + "HCLK_CMT_MUX_CLK_10": null, + "HCLK_CMT_MUX_CLK_11": null, + "HCLK_CMT_MUX_CLK_12": null, + "HCLK_CMT_MUX_CLK_13": null, + "HCLK_CMT_MUX_CLK_2": null, + "HCLK_CMT_MUX_CLK_3": null, + "HCLK_CMT_MUX_CLK_4": null, + "HCLK_CMT_MUX_CLK_5": null, + "HCLK_CMT_MUX_CLK_6": null, + "HCLK_CMT_MUX_CLK_7": null, + "HCLK_CMT_MUX_CLK_8": null, + "HCLK_CMT_MUX_CLK_9": null, + "HCLK_CMT_MUX_CLK_LEAF_DN0": null, + "HCLK_CMT_MUX_CLK_LEAF_DN1": null, + "HCLK_CMT_MUX_CLK_LEAF_UP0": null, + "HCLK_CMT_MUX_CLK_LEAF_UP1": null, + "HCLK_CMT_MUX_CLK_MMCM0": null, + "HCLK_CMT_MUX_CLK_MMCM1": null, + "HCLK_CMT_MUX_CLK_MMCM10": null, + "HCLK_CMT_MUX_CLK_MMCM11": null, + "HCLK_CMT_MUX_CLK_MMCM12": null, + "HCLK_CMT_MUX_CLK_MMCM13": null, + "HCLK_CMT_MUX_CLK_MMCM2": null, + "HCLK_CMT_MUX_CLK_MMCM3": null, + "HCLK_CMT_MUX_CLK_MMCM4": null, + "HCLK_CMT_MUX_CLK_MMCM5": null, + "HCLK_CMT_MUX_CLK_MMCM6": null, + "HCLK_CMT_MUX_CLK_MMCM7": null, + "HCLK_CMT_MUX_CLK_MMCM8": null, + "HCLK_CMT_MUX_CLK_MMCM9": null, + "HCLK_CMT_MUX_CLK_PLL0": null, + "HCLK_CMT_MUX_CLK_PLL1": null, + "HCLK_CMT_MUX_CLK_PLL2": null, + "HCLK_CMT_MUX_CLK_PLL3": null, + "HCLK_CMT_MUX_CLK_PLL4": null, + "HCLK_CMT_MUX_CLK_PLL5": null, + "HCLK_CMT_MUX_CLK_PLL6": null, + "HCLK_CMT_MUX_CLK_PLL7": null, + "HCLK_CMT_MUX_MMCM_CLKFBIN": null, + "HCLK_CMT_MUX_MMCM_CLKIN1": null, + "HCLK_CMT_MUX_MMCM_CLKIN2": null, + "HCLK_CMT_MUX_MMCM_MUXED0": null, + "HCLK_CMT_MUX_MMCM_MUXED1": null, + "HCLK_CMT_MUX_MMCM_MUXED2": null, + "HCLK_CMT_MUX_MMCM_MUXED3": null, + "HCLK_CMT_MUX_OUT_FREQ_REF0": null, + "HCLK_CMT_MUX_OUT_FREQ_REF1": null, + "HCLK_CMT_MUX_OUT_FREQ_REF2": null, + "HCLK_CMT_MUX_OUT_FREQ_REF3": null, + "HCLK_CMT_MUX_PHSR_PERFCLK0": null, + "HCLK_CMT_MUX_PHSR_PERFCLK1": null, + "HCLK_CMT_MUX_PHSR_PERFCLK2": null, + "HCLK_CMT_MUX_PHSR_PERFCLK3": null, + "HCLK_CMT_MUX_PLLE2_CLKFBIN": null, + "HCLK_CMT_MUX_PLLE2_CLKIN1": null, + "HCLK_CMT_MUX_PLLE2_CLKIN2": null, + "HCLK_CMT_OBURSTPENDING0": null, + "HCLK_CMT_OBURSTPENDING1": null, + "HCLK_CMT_PHASEREF_ABOVE0": null, + "HCLK_CMT_PHASEREF_ABOVE1": null, + "HCLK_CMT_PHASEREF_BELOW0": null, + "HCLK_CMT_PHASEREF_BELOW1": null, + "HCLK_CMT_PHASERIN_RCLK0": null, + "HCLK_CMT_PHASERIN_RCLK1": null, + "HCLK_CMT_PHASERIN_RCLK2": null, + "HCLK_CMT_PHASERIN_RCLK3": null, + "HCLK_CMT_PHY_CONTROL_IRANKA0": null, + "HCLK_CMT_PHY_CONTROL_IRANKA1": null, + "HCLK_CMT_PHY_CONTROL_IRANKB0": null, + "HCLK_CMT_PHY_CONTROL_IRANKB1": null, + "HCLK_CMT_PHY_SYNC_BB": null, + "HCLK_CMT_PREF_BOUNCE0": null, + "HCLK_CMT_PREF_BOUNCE1": null, + "HCLK_CMT_PREF_BOUNCE2": null, + "HCLK_CMT_PREF_BOUNCE3": null, + "HCLK_CMT_PREF_CLKOUT": null, + "HCLK_CMT_PREF_TMUXOUT": null + } } diff --git a/kintex7/tile_type_HCLK_DSP_L.json b/kintex7/tile_type_HCLK_DSP_L.json index 0750914..be1e20f 100644 --- a/kintex7/tile_type_HCLK_DSP_L.json +++ b/kintex7/tile_type_HCLK_DSP_L.json @@ -2,134 +2,428 @@ "pips": {}, "sites": [], "tile_type": "HCLK_DSP_L", - "wires": [ - "HCLK_DSP_ACIN0", - "HCLK_DSP_ACIN1", - "HCLK_DSP_ACIN10", - "HCLK_DSP_ACIN11", - "HCLK_DSP_ACIN12", - "HCLK_DSP_ACIN13", - "HCLK_DSP_ACIN14", - "HCLK_DSP_ACIN15", - "HCLK_DSP_ACIN16", - "HCLK_DSP_ACIN17", - "HCLK_DSP_ACIN18", - "HCLK_DSP_ACIN19", - "HCLK_DSP_ACIN2", - "HCLK_DSP_ACIN20", - "HCLK_DSP_ACIN21", - "HCLK_DSP_ACIN22", - "HCLK_DSP_ACIN23", - "HCLK_DSP_ACIN24", - "HCLK_DSP_ACIN25", - "HCLK_DSP_ACIN26", - "HCLK_DSP_ACIN27", - "HCLK_DSP_ACIN28", - "HCLK_DSP_ACIN29", - "HCLK_DSP_ACIN3", - "HCLK_DSP_ACIN4", - "HCLK_DSP_ACIN5", - "HCLK_DSP_ACIN6", - "HCLK_DSP_ACIN7", - "HCLK_DSP_ACIN8", - "HCLK_DSP_ACIN9", - "HCLK_DSP_BCIN0", - "HCLK_DSP_BCIN1", - "HCLK_DSP_BCIN10", - "HCLK_DSP_BCIN11", - "HCLK_DSP_BCIN12", - "HCLK_DSP_BCIN13", - "HCLK_DSP_BCIN14", - "HCLK_DSP_BCIN15", - "HCLK_DSP_BCIN16", - "HCLK_DSP_BCIN17", - "HCLK_DSP_BCIN2", - "HCLK_DSP_BCIN3", - "HCLK_DSP_BCIN4", - "HCLK_DSP_BCIN5", - "HCLK_DSP_BCIN6", - "HCLK_DSP_BCIN7", - "HCLK_DSP_BCIN8", - "HCLK_DSP_BCIN9", - "HCLK_DSP_CARRYCASCIN", - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_DSP_CK_IN0", - "HCLK_DSP_CK_IN1", - "HCLK_DSP_CK_IN10", - "HCLK_DSP_CK_IN11", - "HCLK_DSP_CK_IN12", - "HCLK_DSP_CK_IN13", - "HCLK_DSP_CK_IN2", - "HCLK_DSP_CK_IN3", - "HCLK_DSP_CK_IN4", - "HCLK_DSP_CK_IN5", - "HCLK_DSP_CK_IN6", - "HCLK_DSP_CK_IN7", - "HCLK_DSP_CK_IN8", - "HCLK_DSP_CK_IN9", - "HCLK_DSP_MULTSIGNIN", - "HCLK_DSP_PCIN0", - "HCLK_DSP_PCIN1", - "HCLK_DSP_PCIN10", - "HCLK_DSP_PCIN11", - "HCLK_DSP_PCIN12", - "HCLK_DSP_PCIN13", - "HCLK_DSP_PCIN14", - "HCLK_DSP_PCIN15", - "HCLK_DSP_PCIN16", - "HCLK_DSP_PCIN17", - "HCLK_DSP_PCIN18", - "HCLK_DSP_PCIN19", - "HCLK_DSP_PCIN2", - "HCLK_DSP_PCIN20", - "HCLK_DSP_PCIN21", - "HCLK_DSP_PCIN22", - "HCLK_DSP_PCIN23", - "HCLK_DSP_PCIN24", - "HCLK_DSP_PCIN25", - "HCLK_DSP_PCIN26", - "HCLK_DSP_PCIN27", - "HCLK_DSP_PCIN28", - "HCLK_DSP_PCIN29", - "HCLK_DSP_PCIN3", - "HCLK_DSP_PCIN30", - "HCLK_DSP_PCIN31", - "HCLK_DSP_PCIN32", - "HCLK_DSP_PCIN33", - "HCLK_DSP_PCIN34", - "HCLK_DSP_PCIN35", - "HCLK_DSP_PCIN36", - "HCLK_DSP_PCIN37", - "HCLK_DSP_PCIN38", - "HCLK_DSP_PCIN39", - "HCLK_DSP_PCIN4", - "HCLK_DSP_PCIN40", - "HCLK_DSP_PCIN41", - "HCLK_DSP_PCIN42", - "HCLK_DSP_PCIN43", - "HCLK_DSP_PCIN44", - "HCLK_DSP_PCIN45", - "HCLK_DSP_PCIN46", - "HCLK_DSP_PCIN47", - "HCLK_DSP_PCIN5", - "HCLK_DSP_PCIN6", - "HCLK_DSP_PCIN7", - "HCLK_DSP_PCIN8", - "HCLK_DSP_PCIN9" - ] + "wires": { + "HCLK_DSP_ACIN0": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN1": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN10": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN11": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN12": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN13": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN14": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN15": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN16": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN17": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN18": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN19": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN2": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN20": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN21": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN22": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN23": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN24": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN25": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN26": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN27": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN28": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN29": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN3": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN4": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN5": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN6": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN7": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN8": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN9": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN0": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN1": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN10": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN11": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN12": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN13": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN14": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN15": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN16": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN17": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN2": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN3": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN4": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN5": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN6": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN7": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN8": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN9": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_CARRYCASCIN": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_CK_BUFHCLK0": null, + "HCLK_DSP_CK_BUFHCLK1": null, + "HCLK_DSP_CK_BUFHCLK10": null, + "HCLK_DSP_CK_BUFHCLK11": null, + "HCLK_DSP_CK_BUFHCLK2": null, + "HCLK_DSP_CK_BUFHCLK3": null, + "HCLK_DSP_CK_BUFHCLK4": null, + "HCLK_DSP_CK_BUFHCLK5": null, + "HCLK_DSP_CK_BUFHCLK6": null, + "HCLK_DSP_CK_BUFHCLK7": null, + "HCLK_DSP_CK_BUFHCLK8": null, + "HCLK_DSP_CK_BUFHCLK9": null, + "HCLK_DSP_CK_BUFRCLK0": null, + "HCLK_DSP_CK_BUFRCLK1": null, + "HCLK_DSP_CK_BUFRCLK2": null, + "HCLK_DSP_CK_BUFRCLK3": null, + "HCLK_DSP_CK_IN0": null, + "HCLK_DSP_CK_IN1": null, + "HCLK_DSP_CK_IN10": null, + "HCLK_DSP_CK_IN11": null, + "HCLK_DSP_CK_IN12": null, + "HCLK_DSP_CK_IN13": null, + "HCLK_DSP_CK_IN2": null, + "HCLK_DSP_CK_IN3": null, + "HCLK_DSP_CK_IN4": null, + "HCLK_DSP_CK_IN5": null, + "HCLK_DSP_CK_IN6": null, + "HCLK_DSP_CK_IN7": null, + "HCLK_DSP_CK_IN8": null, + "HCLK_DSP_CK_IN9": null, + "HCLK_DSP_MULTSIGNIN": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN0": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN1": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN10": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN11": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN12": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN13": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN14": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN15": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN16": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN17": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN18": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN19": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN2": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN20": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN21": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN22": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN23": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN24": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN25": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN26": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN27": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN28": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN29": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN3": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN30": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN31": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN32": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN33": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN34": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN35": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN36": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN37": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN38": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN39": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN4": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN40": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN41": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN42": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN43": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN44": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN45": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN46": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN47": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN5": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN6": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN7": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN8": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN9": { + "cap": "28.698", + "res": "0.000" + } + } } diff --git a/kintex7/tile_type_HCLK_DSP_R.json b/kintex7/tile_type_HCLK_DSP_R.json index 909e88d..f56b792 100644 --- a/kintex7/tile_type_HCLK_DSP_R.json +++ b/kintex7/tile_type_HCLK_DSP_R.json @@ -2,134 +2,428 @@ "pips": {}, "sites": [], "tile_type": "HCLK_DSP_R", - "wires": [ - "HCLK_DSP_ACIN0", - "HCLK_DSP_ACIN1", - "HCLK_DSP_ACIN10", - "HCLK_DSP_ACIN11", - "HCLK_DSP_ACIN12", - "HCLK_DSP_ACIN13", - "HCLK_DSP_ACIN14", - "HCLK_DSP_ACIN15", - "HCLK_DSP_ACIN16", - "HCLK_DSP_ACIN17", - "HCLK_DSP_ACIN18", - "HCLK_DSP_ACIN19", - "HCLK_DSP_ACIN2", - "HCLK_DSP_ACIN20", - "HCLK_DSP_ACIN21", - "HCLK_DSP_ACIN22", - "HCLK_DSP_ACIN23", - "HCLK_DSP_ACIN24", - "HCLK_DSP_ACIN25", - "HCLK_DSP_ACIN26", - "HCLK_DSP_ACIN27", - "HCLK_DSP_ACIN28", - "HCLK_DSP_ACIN29", - "HCLK_DSP_ACIN3", - "HCLK_DSP_ACIN4", - "HCLK_DSP_ACIN5", - "HCLK_DSP_ACIN6", - "HCLK_DSP_ACIN7", - "HCLK_DSP_ACIN8", - "HCLK_DSP_ACIN9", - "HCLK_DSP_BCIN0", - "HCLK_DSP_BCIN1", - "HCLK_DSP_BCIN10", - "HCLK_DSP_BCIN11", - "HCLK_DSP_BCIN12", - "HCLK_DSP_BCIN13", - "HCLK_DSP_BCIN14", - "HCLK_DSP_BCIN15", - "HCLK_DSP_BCIN16", - "HCLK_DSP_BCIN17", - "HCLK_DSP_BCIN2", - "HCLK_DSP_BCIN3", - "HCLK_DSP_BCIN4", - "HCLK_DSP_BCIN5", - "HCLK_DSP_BCIN6", - "HCLK_DSP_BCIN7", - "HCLK_DSP_BCIN8", - "HCLK_DSP_BCIN9", - "HCLK_DSP_CARRYCASCIN", - "HCLK_DSP_CK_BUFHCLK0", - "HCLK_DSP_CK_BUFHCLK1", - "HCLK_DSP_CK_BUFHCLK10", - "HCLK_DSP_CK_BUFHCLK11", - "HCLK_DSP_CK_BUFHCLK2", - "HCLK_DSP_CK_BUFHCLK3", - "HCLK_DSP_CK_BUFHCLK4", - "HCLK_DSP_CK_BUFHCLK5", - "HCLK_DSP_CK_BUFHCLK6", - "HCLK_DSP_CK_BUFHCLK7", - "HCLK_DSP_CK_BUFHCLK8", - "HCLK_DSP_CK_BUFHCLK9", - "HCLK_DSP_CK_BUFRCLK0", - "HCLK_DSP_CK_BUFRCLK1", - "HCLK_DSP_CK_BUFRCLK2", - "HCLK_DSP_CK_BUFRCLK3", - "HCLK_DSP_CK_IN0", - "HCLK_DSP_CK_IN1", - "HCLK_DSP_CK_IN10", - "HCLK_DSP_CK_IN11", - "HCLK_DSP_CK_IN12", - "HCLK_DSP_CK_IN13", - "HCLK_DSP_CK_IN2", - "HCLK_DSP_CK_IN3", - "HCLK_DSP_CK_IN4", - "HCLK_DSP_CK_IN5", - "HCLK_DSP_CK_IN6", - "HCLK_DSP_CK_IN7", - "HCLK_DSP_CK_IN8", - "HCLK_DSP_CK_IN9", - "HCLK_DSP_MULTSIGNIN", - "HCLK_DSP_PCIN0", - "HCLK_DSP_PCIN1", - "HCLK_DSP_PCIN10", - "HCLK_DSP_PCIN11", - "HCLK_DSP_PCIN12", - "HCLK_DSP_PCIN13", - "HCLK_DSP_PCIN14", - "HCLK_DSP_PCIN15", - "HCLK_DSP_PCIN16", - "HCLK_DSP_PCIN17", - "HCLK_DSP_PCIN18", - "HCLK_DSP_PCIN19", - "HCLK_DSP_PCIN2", - "HCLK_DSP_PCIN20", - "HCLK_DSP_PCIN21", - "HCLK_DSP_PCIN22", - "HCLK_DSP_PCIN23", - "HCLK_DSP_PCIN24", - "HCLK_DSP_PCIN25", - "HCLK_DSP_PCIN26", - "HCLK_DSP_PCIN27", - "HCLK_DSP_PCIN28", - "HCLK_DSP_PCIN29", - "HCLK_DSP_PCIN3", - "HCLK_DSP_PCIN30", - "HCLK_DSP_PCIN31", - "HCLK_DSP_PCIN32", - "HCLK_DSP_PCIN33", - "HCLK_DSP_PCIN34", - "HCLK_DSP_PCIN35", - "HCLK_DSP_PCIN36", - "HCLK_DSP_PCIN37", - "HCLK_DSP_PCIN38", - "HCLK_DSP_PCIN39", - "HCLK_DSP_PCIN4", - "HCLK_DSP_PCIN40", - "HCLK_DSP_PCIN41", - "HCLK_DSP_PCIN42", - "HCLK_DSP_PCIN43", - "HCLK_DSP_PCIN44", - "HCLK_DSP_PCIN45", - "HCLK_DSP_PCIN46", - "HCLK_DSP_PCIN47", - "HCLK_DSP_PCIN5", - "HCLK_DSP_PCIN6", - "HCLK_DSP_PCIN7", - "HCLK_DSP_PCIN8", - "HCLK_DSP_PCIN9" - ] + "wires": { + "HCLK_DSP_ACIN0": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN1": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN10": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN11": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN12": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN13": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN14": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN15": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN16": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN17": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN18": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN19": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN2": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN20": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN21": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN22": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN23": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN24": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN25": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN26": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN27": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN28": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN29": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN3": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN4": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN5": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN6": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN7": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN8": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_ACIN9": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN0": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN1": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN10": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN11": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN12": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN13": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN14": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN15": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN16": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN17": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN2": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN3": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN4": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN5": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN6": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN7": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN8": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_BCIN9": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_CARRYCASCIN": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_CK_BUFHCLK0": null, + "HCLK_DSP_CK_BUFHCLK1": null, + "HCLK_DSP_CK_BUFHCLK10": null, + "HCLK_DSP_CK_BUFHCLK11": null, + "HCLK_DSP_CK_BUFHCLK2": null, + "HCLK_DSP_CK_BUFHCLK3": null, + "HCLK_DSP_CK_BUFHCLK4": null, + "HCLK_DSP_CK_BUFHCLK5": null, + "HCLK_DSP_CK_BUFHCLK6": null, + "HCLK_DSP_CK_BUFHCLK7": null, + "HCLK_DSP_CK_BUFHCLK8": null, + "HCLK_DSP_CK_BUFHCLK9": null, + "HCLK_DSP_CK_BUFRCLK0": null, + "HCLK_DSP_CK_BUFRCLK1": null, + "HCLK_DSP_CK_BUFRCLK2": null, + "HCLK_DSP_CK_BUFRCLK3": null, + "HCLK_DSP_CK_IN0": null, + "HCLK_DSP_CK_IN1": null, + "HCLK_DSP_CK_IN10": null, + "HCLK_DSP_CK_IN11": null, + "HCLK_DSP_CK_IN12": null, + "HCLK_DSP_CK_IN13": null, + "HCLK_DSP_CK_IN2": null, + "HCLK_DSP_CK_IN3": null, + "HCLK_DSP_CK_IN4": null, + "HCLK_DSP_CK_IN5": null, + "HCLK_DSP_CK_IN6": null, + "HCLK_DSP_CK_IN7": null, + "HCLK_DSP_CK_IN8": null, + "HCLK_DSP_CK_IN9": null, + "HCLK_DSP_MULTSIGNIN": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN0": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN1": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN10": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN11": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN12": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN13": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN14": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN15": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN16": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN17": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN18": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN19": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN2": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN20": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN21": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN22": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN23": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN24": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN25": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN26": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN27": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN28": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN29": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN3": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN30": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN31": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN32": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN33": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN34": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN35": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN36": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN37": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN38": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN39": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN4": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN40": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN41": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN42": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN43": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN44": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN45": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN46": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN47": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN5": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN6": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN7": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN8": { + "cap": "28.698", + "res": "0.000" + }, + "HCLK_DSP_PCIN9": { + "cap": "28.698", + "res": "0.000" + } + } } diff --git a/kintex7/tile_type_HCLK_FEEDTHRU_1.json b/kintex7/tile_type_HCLK_FEEDTHRU_1.json index 58cd290..7eb6ca1 100644 --- a/kintex7/tile_type_HCLK_FEEDTHRU_1.json +++ b/kintex7/tile_type_HCLK_FEEDTHRU_1.json @@ -2,36 +2,36 @@ "pips": {}, "sites": [], "tile_type": "HCLK_FEEDTHRU_1", - "wires": [ - "HCLK_FEEDTHRU_1_CK_BUFHCLK0", - "HCLK_FEEDTHRU_1_CK_BUFHCLK1", - "HCLK_FEEDTHRU_1_CK_BUFHCLK10", - "HCLK_FEEDTHRU_1_CK_BUFHCLK11", - "HCLK_FEEDTHRU_1_CK_BUFHCLK2", - "HCLK_FEEDTHRU_1_CK_BUFHCLK3", - "HCLK_FEEDTHRU_1_CK_BUFHCLK4", - "HCLK_FEEDTHRU_1_CK_BUFHCLK5", - "HCLK_FEEDTHRU_1_CK_BUFHCLK6", - "HCLK_FEEDTHRU_1_CK_BUFHCLK7", - "HCLK_FEEDTHRU_1_CK_BUFHCLK8", - "HCLK_FEEDTHRU_1_CK_BUFHCLK9", - "HCLK_FEEDTHRU_1_CK_BUFRCLK0", - "HCLK_FEEDTHRU_1_CK_BUFRCLK1", - "HCLK_FEEDTHRU_1_CK_BUFRCLK2", - "HCLK_FEEDTHRU_1_CK_BUFRCLK3", - "HCLK_FEEDTHRU_1_CK_IN0", - "HCLK_FEEDTHRU_1_CK_IN1", - "HCLK_FEEDTHRU_1_CK_IN10", - "HCLK_FEEDTHRU_1_CK_IN11", - "HCLK_FEEDTHRU_1_CK_IN12", - "HCLK_FEEDTHRU_1_CK_IN13", - "HCLK_FEEDTHRU_1_CK_IN2", - "HCLK_FEEDTHRU_1_CK_IN3", - "HCLK_FEEDTHRU_1_CK_IN4", - "HCLK_FEEDTHRU_1_CK_IN5", - "HCLK_FEEDTHRU_1_CK_IN6", - "HCLK_FEEDTHRU_1_CK_IN7", - "HCLK_FEEDTHRU_1_CK_IN8", - "HCLK_FEEDTHRU_1_CK_IN9" - ] + "wires": { + "HCLK_FEEDTHRU_1_CK_BUFHCLK0": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK1": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK10": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK11": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK2": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK3": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK4": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK5": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK6": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK7": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK8": null, + "HCLK_FEEDTHRU_1_CK_BUFHCLK9": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK0": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK1": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK2": null, + "HCLK_FEEDTHRU_1_CK_BUFRCLK3": null, + "HCLK_FEEDTHRU_1_CK_IN0": null, + "HCLK_FEEDTHRU_1_CK_IN1": null, + "HCLK_FEEDTHRU_1_CK_IN10": null, + "HCLK_FEEDTHRU_1_CK_IN11": null, + "HCLK_FEEDTHRU_1_CK_IN12": null, + "HCLK_FEEDTHRU_1_CK_IN13": null, + "HCLK_FEEDTHRU_1_CK_IN2": null, + "HCLK_FEEDTHRU_1_CK_IN3": null, + "HCLK_FEEDTHRU_1_CK_IN4": null, + "HCLK_FEEDTHRU_1_CK_IN5": null, + "HCLK_FEEDTHRU_1_CK_IN6": null, + "HCLK_FEEDTHRU_1_CK_IN7": null, + "HCLK_FEEDTHRU_1_CK_IN8": null, + "HCLK_FEEDTHRU_1_CK_IN9": null + } } diff --git a/kintex7/tile_type_HCLK_FEEDTHRU_2.json b/kintex7/tile_type_HCLK_FEEDTHRU_2.json index df05939..076baf9 100644 --- a/kintex7/tile_type_HCLK_FEEDTHRU_2.json +++ b/kintex7/tile_type_HCLK_FEEDTHRU_2.json @@ -2,36 +2,36 @@ "pips": {}, "sites": [], "tile_type": "HCLK_FEEDTHRU_2", - "wires": [ - "HCLK_FEEDTHRU_2_CK_BUFHCLK0", - "HCLK_FEEDTHRU_2_CK_BUFHCLK1", - "HCLK_FEEDTHRU_2_CK_BUFHCLK10", - "HCLK_FEEDTHRU_2_CK_BUFHCLK11", - "HCLK_FEEDTHRU_2_CK_BUFHCLK2", - "HCLK_FEEDTHRU_2_CK_BUFHCLK3", - "HCLK_FEEDTHRU_2_CK_BUFHCLK4", - "HCLK_FEEDTHRU_2_CK_BUFHCLK5", - "HCLK_FEEDTHRU_2_CK_BUFHCLK6", - "HCLK_FEEDTHRU_2_CK_BUFHCLK7", - "HCLK_FEEDTHRU_2_CK_BUFHCLK8", - "HCLK_FEEDTHRU_2_CK_BUFHCLK9", - "HCLK_FEEDTHRU_2_CK_BUFRCLK0", - "HCLK_FEEDTHRU_2_CK_BUFRCLK1", - "HCLK_FEEDTHRU_2_CK_BUFRCLK2", - "HCLK_FEEDTHRU_2_CK_BUFRCLK3", - "HCLK_FEEDTHRU_2_CK_IN0", - "HCLK_FEEDTHRU_2_CK_IN1", - "HCLK_FEEDTHRU_2_CK_IN10", - "HCLK_FEEDTHRU_2_CK_IN11", - "HCLK_FEEDTHRU_2_CK_IN12", - "HCLK_FEEDTHRU_2_CK_IN13", - "HCLK_FEEDTHRU_2_CK_IN2", - "HCLK_FEEDTHRU_2_CK_IN3", - "HCLK_FEEDTHRU_2_CK_IN4", - "HCLK_FEEDTHRU_2_CK_IN5", - "HCLK_FEEDTHRU_2_CK_IN6", - "HCLK_FEEDTHRU_2_CK_IN7", - "HCLK_FEEDTHRU_2_CK_IN8", - "HCLK_FEEDTHRU_2_CK_IN9" - ] + "wires": { + "HCLK_FEEDTHRU_2_CK_BUFHCLK0": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK1": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK10": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK11": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK2": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK3": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK4": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK5": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK6": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK7": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK8": null, + "HCLK_FEEDTHRU_2_CK_BUFHCLK9": null, + "HCLK_FEEDTHRU_2_CK_BUFRCLK0": null, + "HCLK_FEEDTHRU_2_CK_BUFRCLK1": null, + "HCLK_FEEDTHRU_2_CK_BUFRCLK2": null, + "HCLK_FEEDTHRU_2_CK_BUFRCLK3": null, + "HCLK_FEEDTHRU_2_CK_IN0": null, + "HCLK_FEEDTHRU_2_CK_IN1": null, + "HCLK_FEEDTHRU_2_CK_IN10": null, + "HCLK_FEEDTHRU_2_CK_IN11": null, + "HCLK_FEEDTHRU_2_CK_IN12": null, + "HCLK_FEEDTHRU_2_CK_IN13": null, + "HCLK_FEEDTHRU_2_CK_IN2": null, + "HCLK_FEEDTHRU_2_CK_IN3": null, + "HCLK_FEEDTHRU_2_CK_IN4": null, + "HCLK_FEEDTHRU_2_CK_IN5": null, + "HCLK_FEEDTHRU_2_CK_IN6": null, + "HCLK_FEEDTHRU_2_CK_IN7": null, + "HCLK_FEEDTHRU_2_CK_IN8": null, + "HCLK_FEEDTHRU_2_CK_IN9": null + } } diff --git a/kintex7/tile_type_HCLK_FIFO_L.json b/kintex7/tile_type_HCLK_FIFO_L.json index 258356f..5b11755 100644 --- a/kintex7/tile_type_HCLK_FIFO_L.json +++ b/kintex7/tile_type_HCLK_FIFO_L.json @@ -2,44 +2,44 @@ "pips": {}, "sites": [], "tile_type": "HCLK_FIFO_L", - "wires": [ - "HCLK_FIFO_CCIO0", - "HCLK_FIFO_CCIO1", - "HCLK_FIFO_CCIO2", - "HCLK_FIFO_CCIO3", - "HCLK_FIFO_CK_BUFHCLK0", - "HCLK_FIFO_CK_BUFHCLK1", - "HCLK_FIFO_CK_BUFHCLK10", - "HCLK_FIFO_CK_BUFHCLK11", - "HCLK_FIFO_CK_BUFHCLK2", - "HCLK_FIFO_CK_BUFHCLK3", - "HCLK_FIFO_CK_BUFHCLK4", - "HCLK_FIFO_CK_BUFHCLK5", - "HCLK_FIFO_CK_BUFHCLK6", - "HCLK_FIFO_CK_BUFHCLK7", - "HCLK_FIFO_CK_BUFHCLK8", - "HCLK_FIFO_CK_BUFHCLK9", - "HCLK_FIFO_CK_BUFRCLK0", - "HCLK_FIFO_CK_BUFRCLK1", - "HCLK_FIFO_CK_BUFRCLK2", - "HCLK_FIFO_CK_BUFRCLK3", - "HCLK_FIFO_CK_IN0", - "HCLK_FIFO_CK_IN1", - "HCLK_FIFO_CK_IN10", - "HCLK_FIFO_CK_IN11", - "HCLK_FIFO_CK_IN12", - "HCLK_FIFO_CK_IN13", - "HCLK_FIFO_CK_IN2", - "HCLK_FIFO_CK_IN3", - "HCLK_FIFO_CK_IN4", - "HCLK_FIFO_CK_IN5", - "HCLK_FIFO_CK_IN6", - "HCLK_FIFO_CK_IN7", - "HCLK_FIFO_CK_IN8", - "HCLK_FIFO_CK_IN9", - "HCLK_FIFO_PERFCLK0", - "HCLK_FIFO_PERFCLK1", - "HCLK_FIFO_PERFCLK2", - "HCLK_FIFO_PERFCLK3" - ] + "wires": { + "HCLK_FIFO_CCIO0": null, + "HCLK_FIFO_CCIO1": null, + "HCLK_FIFO_CCIO2": null, + "HCLK_FIFO_CCIO3": null, + "HCLK_FIFO_CK_BUFHCLK0": null, + "HCLK_FIFO_CK_BUFHCLK1": null, + "HCLK_FIFO_CK_BUFHCLK10": null, + "HCLK_FIFO_CK_BUFHCLK11": null, + "HCLK_FIFO_CK_BUFHCLK2": null, + "HCLK_FIFO_CK_BUFHCLK3": null, + "HCLK_FIFO_CK_BUFHCLK4": null, + "HCLK_FIFO_CK_BUFHCLK5": null, + "HCLK_FIFO_CK_BUFHCLK6": null, + "HCLK_FIFO_CK_BUFHCLK7": null, + "HCLK_FIFO_CK_BUFHCLK8": null, + "HCLK_FIFO_CK_BUFHCLK9": null, + "HCLK_FIFO_CK_BUFRCLK0": null, + "HCLK_FIFO_CK_BUFRCLK1": null, + "HCLK_FIFO_CK_BUFRCLK2": null, + "HCLK_FIFO_CK_BUFRCLK3": null, + "HCLK_FIFO_CK_IN0": null, + "HCLK_FIFO_CK_IN1": null, + "HCLK_FIFO_CK_IN10": null, + "HCLK_FIFO_CK_IN11": null, + "HCLK_FIFO_CK_IN12": null, + "HCLK_FIFO_CK_IN13": null, + "HCLK_FIFO_CK_IN2": null, + "HCLK_FIFO_CK_IN3": null, + "HCLK_FIFO_CK_IN4": null, + "HCLK_FIFO_CK_IN5": null, + "HCLK_FIFO_CK_IN6": null, + "HCLK_FIFO_CK_IN7": null, + "HCLK_FIFO_CK_IN8": null, + "HCLK_FIFO_CK_IN9": null, + "HCLK_FIFO_PERFCLK0": null, + "HCLK_FIFO_PERFCLK1": null, + "HCLK_FIFO_PERFCLK2": null, + "HCLK_FIFO_PERFCLK3": null + } } diff --git a/kintex7/tile_type_HCLK_GTX.json b/kintex7/tile_type_HCLK_GTX.json index 9370a76..d8dbfbb 100644 --- a/kintex7/tile_type_HCLK_GTX.json +++ b/kintex7/tile_type_HCLK_GTX.json @@ -2,20 +2,20 @@ "pips": {}, "sites": [], "tile_type": "HCLK_GTX", - "wires": [ - "HCLK_GTX_CK_IN0", - "HCLK_GTX_CK_IN1", - "HCLK_GTX_CK_IN10", - "HCLK_GTX_CK_IN11", - "HCLK_GTX_CK_IN12", - "HCLK_GTX_CK_IN13", - "HCLK_GTX_CK_IN2", - "HCLK_GTX_CK_IN3", - "HCLK_GTX_CK_IN4", - "HCLK_GTX_CK_IN5", - "HCLK_GTX_CK_IN6", - "HCLK_GTX_CK_IN7", - "HCLK_GTX_CK_IN8", - "HCLK_GTX_CK_IN9" - ] + "wires": { + "HCLK_GTX_CK_IN0": null, + "HCLK_GTX_CK_IN1": null, + "HCLK_GTX_CK_IN10": null, + "HCLK_GTX_CK_IN11": null, + "HCLK_GTX_CK_IN12": null, + "HCLK_GTX_CK_IN13": null, + "HCLK_GTX_CK_IN2": null, + "HCLK_GTX_CK_IN3": null, + "HCLK_GTX_CK_IN4": null, + "HCLK_GTX_CK_IN5": null, + "HCLK_GTX_CK_IN6": null, + "HCLK_GTX_CK_IN7": null, + "HCLK_GTX_CK_IN8": null, + "HCLK_GTX_CK_IN9": null + } } diff --git a/kintex7/tile_type_HCLK_INT_INTERFACE.json b/kintex7/tile_type_HCLK_INT_INTERFACE.json index 93e55e2..df45c5e 100644 --- a/kintex7/tile_type_HCLK_INT_INTERFACE.json +++ b/kintex7/tile_type_HCLK_INT_INTERFACE.json @@ -2,48 +2,48 @@ "pips": {}, "sites": [], "tile_type": "HCLK_INT_INTERFACE", - "wires": [ - "HCLK_INT_INTERFACE_CCIO0", - "HCLK_INT_INTERFACE_CCIO1", - "HCLK_INT_INTERFACE_CCIO2", - "HCLK_INT_INTERFACE_CCIO3", - "HCLK_INT_INTERFACE_CK_BUFHCLK0", - "HCLK_INT_INTERFACE_CK_BUFHCLK1", - "HCLK_INT_INTERFACE_CK_BUFHCLK10", - "HCLK_INT_INTERFACE_CK_BUFHCLK11", - "HCLK_INT_INTERFACE_CK_BUFHCLK2", - "HCLK_INT_INTERFACE_CK_BUFHCLK3", - "HCLK_INT_INTERFACE_CK_BUFHCLK4", - "HCLK_INT_INTERFACE_CK_BUFHCLK5", - "HCLK_INT_INTERFACE_CK_BUFHCLK6", - "HCLK_INT_INTERFACE_CK_BUFHCLK7", - "HCLK_INT_INTERFACE_CK_BUFHCLK8", - "HCLK_INT_INTERFACE_CK_BUFHCLK9", - "HCLK_INT_INTERFACE_CK_BUFRCLK0", - "HCLK_INT_INTERFACE_CK_BUFRCLK1", - "HCLK_INT_INTERFACE_CK_BUFRCLK2", - "HCLK_INT_INTERFACE_CK_BUFRCLK3", - "HCLK_INT_INTERFACE_CK_IN0", - "HCLK_INT_INTERFACE_CK_IN1", - "HCLK_INT_INTERFACE_CK_IN10", - "HCLK_INT_INTERFACE_CK_IN11", - "HCLK_INT_INTERFACE_CK_IN12", - "HCLK_INT_INTERFACE_CK_IN13", - "HCLK_INT_INTERFACE_CK_IN2", - "HCLK_INT_INTERFACE_CK_IN3", - "HCLK_INT_INTERFACE_CK_IN4", - "HCLK_INT_INTERFACE_CK_IN5", - "HCLK_INT_INTERFACE_CK_IN6", - "HCLK_INT_INTERFACE_CK_IN7", - "HCLK_INT_INTERFACE_CK_IN8", - "HCLK_INT_INTERFACE_CK_IN9", - "HCLK_INT_INTERFACE_PERFCLK0", - "HCLK_INT_INTERFACE_PERFCLK1", - "HCLK_INT_INTERFACE_PERFCLK2", - "HCLK_INT_INTERFACE_PERFCLK3", - "HCLK_INT_INTERFACE_REFCK_EASTCLK0", - "HCLK_INT_INTERFACE_REFCK_EASTCLK1", - "HCLK_INT_INTERFACE_REFCK_WESTCLK0", - "HCLK_INT_INTERFACE_REFCK_WESTCLK1" - ] + "wires": { + "HCLK_INT_INTERFACE_CCIO0": null, + "HCLK_INT_INTERFACE_CCIO1": null, + "HCLK_INT_INTERFACE_CCIO2": null, + "HCLK_INT_INTERFACE_CCIO3": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK0": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK1": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK10": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK11": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK2": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK3": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK4": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK5": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK6": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK7": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK8": null, + "HCLK_INT_INTERFACE_CK_BUFHCLK9": null, + "HCLK_INT_INTERFACE_CK_BUFRCLK0": null, + "HCLK_INT_INTERFACE_CK_BUFRCLK1": null, + "HCLK_INT_INTERFACE_CK_BUFRCLK2": null, + "HCLK_INT_INTERFACE_CK_BUFRCLK3": null, + "HCLK_INT_INTERFACE_CK_IN0": null, + "HCLK_INT_INTERFACE_CK_IN1": null, + "HCLK_INT_INTERFACE_CK_IN10": null, + "HCLK_INT_INTERFACE_CK_IN11": null, + "HCLK_INT_INTERFACE_CK_IN12": null, + "HCLK_INT_INTERFACE_CK_IN13": null, + "HCLK_INT_INTERFACE_CK_IN2": null, + "HCLK_INT_INTERFACE_CK_IN3": null, + "HCLK_INT_INTERFACE_CK_IN4": null, + "HCLK_INT_INTERFACE_CK_IN5": null, + "HCLK_INT_INTERFACE_CK_IN6": null, + "HCLK_INT_INTERFACE_CK_IN7": null, + "HCLK_INT_INTERFACE_CK_IN8": null, + "HCLK_INT_INTERFACE_CK_IN9": null, + "HCLK_INT_INTERFACE_PERFCLK0": null, + "HCLK_INT_INTERFACE_PERFCLK1": null, + "HCLK_INT_INTERFACE_PERFCLK2": null, + "HCLK_INT_INTERFACE_PERFCLK3": null, + "HCLK_INT_INTERFACE_REFCK_EASTCLK0": null, + "HCLK_INT_INTERFACE_REFCK_EASTCLK1": null, + "HCLK_INT_INTERFACE_REFCK_WESTCLK0": null, + "HCLK_INT_INTERFACE_REFCK_WESTCLK1": null + } } diff --git a/kintex7/tile_type_HCLK_IOB.json b/kintex7/tile_type_HCLK_IOB.json index bf06214..d85709f 100644 --- a/kintex7/tile_type_HCLK_IOB.json +++ b/kintex7/tile_type_HCLK_IOB.json @@ -2,40 +2,40 @@ "pips": {}, "sites": [], "tile_type": "HCLK_IOB", - "wires": [ - "HCLK_IOB_CK_BUFHCLK0", - "HCLK_IOB_CK_BUFHCLK1", - "HCLK_IOB_CK_BUFHCLK10", - "HCLK_IOB_CK_BUFHCLK11", - "HCLK_IOB_CK_BUFHCLK2", - "HCLK_IOB_CK_BUFHCLK3", - "HCLK_IOB_CK_BUFHCLK4", - "HCLK_IOB_CK_BUFHCLK5", - "HCLK_IOB_CK_BUFHCLK6", - "HCLK_IOB_CK_BUFHCLK7", - "HCLK_IOB_CK_BUFHCLK8", - "HCLK_IOB_CK_BUFHCLK9", - "HCLK_IOB_CK_BUFRCLK0", - "HCLK_IOB_CK_BUFRCLK1", - "HCLK_IOB_CK_BUFRCLK2", - "HCLK_IOB_CK_BUFRCLK3", - "HCLK_IOB_CK_IN0", - "HCLK_IOB_CK_IN1", - "HCLK_IOB_CK_IN10", - "HCLK_IOB_CK_IN11", - "HCLK_IOB_CK_IN12", - "HCLK_IOB_CK_IN13", - "HCLK_IOB_CK_IN2", - "HCLK_IOB_CK_IN3", - "HCLK_IOB_CK_IN4", - "HCLK_IOB_CK_IN5", - "HCLK_IOB_CK_IN6", - "HCLK_IOB_CK_IN7", - "HCLK_IOB_CK_IN8", - "HCLK_IOB_CK_IN9", - "HCLK_IOB_PERFCLK0", - "HCLK_IOB_PERFCLK1", - "HCLK_IOB_PERFCLK2", - "HCLK_IOB_PERFCLK3" - ] + "wires": { + "HCLK_IOB_CK_BUFHCLK0": null, + "HCLK_IOB_CK_BUFHCLK1": null, + "HCLK_IOB_CK_BUFHCLK10": null, + "HCLK_IOB_CK_BUFHCLK11": null, + "HCLK_IOB_CK_BUFHCLK2": null, + "HCLK_IOB_CK_BUFHCLK3": null, + "HCLK_IOB_CK_BUFHCLK4": null, + "HCLK_IOB_CK_BUFHCLK5": null, + "HCLK_IOB_CK_BUFHCLK6": null, + "HCLK_IOB_CK_BUFHCLK7": null, + "HCLK_IOB_CK_BUFHCLK8": null, + "HCLK_IOB_CK_BUFHCLK9": null, + "HCLK_IOB_CK_BUFRCLK0": null, + "HCLK_IOB_CK_BUFRCLK1": null, + "HCLK_IOB_CK_BUFRCLK2": null, + "HCLK_IOB_CK_BUFRCLK3": null, + "HCLK_IOB_CK_IN0": null, + "HCLK_IOB_CK_IN1": null, + "HCLK_IOB_CK_IN10": null, + "HCLK_IOB_CK_IN11": null, + "HCLK_IOB_CK_IN12": null, + "HCLK_IOB_CK_IN13": null, + "HCLK_IOB_CK_IN2": null, + "HCLK_IOB_CK_IN3": null, + "HCLK_IOB_CK_IN4": null, + "HCLK_IOB_CK_IN5": null, + "HCLK_IOB_CK_IN6": null, + "HCLK_IOB_CK_IN7": null, + "HCLK_IOB_CK_IN8": null, + "HCLK_IOB_CK_IN9": null, + "HCLK_IOB_PERFCLK0": null, + "HCLK_IOB_PERFCLK1": null, + "HCLK_IOB_PERFCLK2": null, + "HCLK_IOB_PERFCLK3": null + } } diff --git a/kintex7/tile_type_HCLK_IOI.json b/kintex7/tile_type_HCLK_IOI.json index f5beb11..ed3b033 100644 --- a/kintex7/tile_type_HCLK_IOI.json +++ b/kintex7/tile_type_HCLK_IOI.json @@ -2,1710 +2,6754 @@ "pips": { "HCLK_IOI.HCLK_IOI_BUFIO_O0->>HCLK_IOI_IOCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O0" }, "HCLK_IOI.HCLK_IOI_BUFIO_O1->>HCLK_IOI_IOCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O1" }, "HCLK_IOI.HCLK_IOI_BUFIO_O2->>HCLK_IOI_IOCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O2" }, "HCLK_IOI.HCLK_IOI_BUFIO_O3->>HCLK_IOI_IOCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O3" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK0->>HCLK_IOI_CK_IGCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK0" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK1->>HCLK_IOI_CK_IGCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK1" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK10->>HCLK_IOI_CK_IGCLK10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK10" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK11->>HCLK_IOI_CK_IGCLK11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK11" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK2->>HCLK_IOI_CK_IGCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK2" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK3->>HCLK_IOI_CK_IGCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK3" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK4->>HCLK_IOI_CK_IGCLK4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK4" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK5->>HCLK_IOI_CK_IGCLK5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK5" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK6->>HCLK_IOI_CK_IGCLK6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK6" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK7->>HCLK_IOI_CK_IGCLK7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK7" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK8->>HCLK_IOI_CK_IGCLK8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK8" }, "HCLK_IOI.HCLK_IOI_CK_BUFHCLK9->>HCLK_IOI_CK_IGCLK9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK9" }, "HCLK_IOI.HCLK_IOI_CK_BUFRCLK0->>HCLK_IOI_RCLK2IO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK0" }, "HCLK_IOI.HCLK_IOI_CK_BUFRCLK1->>HCLK_IOI_RCLK2IO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK1" }, "HCLK_IOI.HCLK_IOI_CK_BUFRCLK2->>HCLK_IOI_RCLK2IO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK2" }, "HCLK_IOI.HCLK_IOI_CK_BUFRCLK3->>HCLK_IOI_RCLK2IO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null 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], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null 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], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK6->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK6" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI.HCLK_IOI_I2IOCLK_BOT0->>HCLK_IOI_IO_PLL_CLK2_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_BOT0" }, "HCLK_IOI.HCLK_IOI_I2IOCLK_BOT1->>HCLK_IOI_IO_PLL_CLK3_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_BOT1" }, "HCLK_IOI.HCLK_IOI_I2IOCLK_TOP0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_TOP0" }, "HCLK_IOI.HCLK_IOI_I2IOCLK_TOP1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_TOP1" }, "HCLK_IOI.HCLK_IOI_IOCLK_PLL0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL0" }, "HCLK_IOI.HCLK_IOI_IOCLK_PLL1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL1" }, "HCLK_IOI.HCLK_IOI_IOCLK_PLL2->>HCLK_IOI_IO_PLL_CLK2_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL2" }, "HCLK_IOI.HCLK_IOI_IOCLK_PLL3->>HCLK_IOI_IO_PLL_CLK3_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL3" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_IO_PLL_CLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_RCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_IO_PLL_CLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_RCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_IO_PLL_CLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_RCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_IO_PLL_CLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" }, "HCLK_IOI.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_RCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT0->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT0" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT1->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT1" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT2->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT2" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT3->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT3" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT4->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT4" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_BOT5->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT5" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP0->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP0" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP1->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP1" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP2->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP2" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP3->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP3" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP4->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP4" }, "HCLK_IOI.HCLK_IOI_LEAF_GCLK_TOP5->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP5" }, "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2RCLK0->>HCLK_IOI_CK_BUFRCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_CK_BUFRCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_RCLK2RCLK0" }, "HCLK_IOI.HCLK_IOI_RCLK2RCLK1->>HCLK_IOI_CK_BUFRCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_CK_BUFRCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_RCLK2RCLK1" }, "HCLK_IOI.HCLK_IOI_RCLK2RCLK2->>HCLK_IOI_CK_BUFRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_CK_BUFRCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_RCLK2RCLK2" }, "HCLK_IOI.HCLK_IOI_RCLK2RCLK3->>HCLK_IOI_CK_BUFRCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_CK_BUFRCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_RCLK2RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV0->>HCLK_IOI_RCLK_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.090", + "0.093", + "0.289", + "0.314" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.090", + "0.093", + "0.289", + "0.314" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV0" }, "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV1->>HCLK_IOI_RCLK_OUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.090", + "0.093", + "0.289", + "0.314" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_OUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.090", + "0.093", + "0.289", + "0.314" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV1" }, "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV2->>HCLK_IOI_RCLK_OUT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.090", + "0.093", + "0.289", + "0.314" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_OUT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.090", + "0.093", + "0.289", + "0.314" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV2" }, "HCLK_IOI.HCLK_IOI_RCLK_BEFORE_DIV3->>HCLK_IOI_RCLK_OUT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.090", + "0.093", + "0.289", + "0.314" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_OUT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.090", + "0.093", + "0.289", + "0.314" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_BEFORE_DIV3" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX0" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX0" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX0" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX0" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX1" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX1" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX1" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX1" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX2" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX2" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX2" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX2" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI.HCLK_IOI_RCLK_OUT0->>HCLK_IOI_RCLK2RCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT0" }, "HCLK_IOI.HCLK_IOI_RCLK_OUT1->>HCLK_IOI_RCLK2RCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT1" }, "HCLK_IOI.HCLK_IOI_RCLK_OUT2->>HCLK_IOI_RCLK2RCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT2" }, "HCLK_IOI.HCLK_IOI_RCLK_OUT3->>HCLK_IOI_RCLK2RCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT3" }, "HCLK_IOI.HCLK_RCLK_DIV_CE0->HCLK_IOI_BUFR0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE0" }, "HCLK_IOI.HCLK_RCLK_DIV_CE1->HCLK_IOI_BUFR1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE1" }, "HCLK_IOI.HCLK_RCLK_DIV_CE2->HCLK_IOI_BUFR2_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR2_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE2" }, "HCLK_IOI.HCLK_RCLK_DIV_CE3->HCLK_IOI_BUFR3_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR3_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE3" }, "HCLK_IOI.HCLK_RCLK_DIV_CLR0->HCLK_IOI_BUFR0_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR0_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR0" }, "HCLK_IOI.HCLK_RCLK_DIV_CLR1->HCLK_IOI_BUFR1_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR1_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR1" }, "HCLK_IOI.HCLK_RCLK_DIV_CLR2->HCLK_IOI_BUFR2_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR2_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR2" }, "HCLK_IOI.HCLK_RCLK_DIV_CLR3->HCLK_IOI_BUFR3_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR3_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR3" } }, @@ -1714,8 +6758,26 @@ "name": "X0Y1", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK3", - "O": "HCLK_IOI_BUFIO_O3" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O3" + } }, "type": "BUFIO", "x_coord": 0, @@ -1725,8 +6787,26 @@ "name": "X0Y0", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK2", - "O": "HCLK_IOI_BUFIO_O2" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O2" + } }, "type": "BUFIO", "x_coord": 0, @@ -1736,8 +6816,26 @@ "name": "X0Y3", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK1", - "O": "HCLK_IOI_BUFIO_O1" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O1" + } }, "type": "BUFIO", "x_coord": 0, @@ -1747,8 +6845,26 @@ "name": "X0Y2", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK0", - "O": "HCLK_IOI_BUFIO_O0" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O0" + } }, "type": "BUFIO", "x_coord": 0, @@ -1758,10 +6874,46 @@ "name": "X0Y1", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR3_CE", - "CLR": "HCLK_IOI_BUFR3_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV3", - "O": "HCLK_IOI_RCLK_OUT3" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR3_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR3_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT3" + } }, "type": "BUFR", "x_coord": 0, @@ -1771,10 +6923,46 @@ "name": "X0Y0", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR2_CE", - "CLR": "HCLK_IOI_BUFR2_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV2", - "O": "HCLK_IOI_RCLK_OUT2" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR2_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR2_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT2" + } }, "type": "BUFR", "x_coord": 0, @@ -1784,10 +6972,46 @@ "name": "X0Y3", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR1_CE", - "CLR": "HCLK_IOI_BUFR1_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV1", - "O": "HCLK_IOI_RCLK_OUT1" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR1_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR1_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT1" + } }, "type": "BUFR", "x_coord": 0, @@ -1797,10 +7021,46 @@ "name": "X0Y2", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR0_CE", - "CLR": "HCLK_IOI_BUFR0_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV0", - "O": "HCLK_IOI_RCLK_OUT0" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR0_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR0_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT0" + } }, "type": "BUFR", "x_coord": 0, @@ -1810,13 +7070,76 @@ "name": "X0Y0", "prefix": "IDELAYCTRL", "site_pins": { - "DNPULSEOUT": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", - "OUTN1": "HCLK_IOI_IDELAYCTRL_OUTN1", - "OUTN65": "HCLK_IOI_IDELAYCTRL_OUTN65", - "RDY": "HCLK_IOI_IDELAYCTRL_RDY", - "REFCLK": "HCLK_IOI_IDELAYCTRL_REFCLK", - "RST": "HCLK_IOI_IDELAYCTRL_RST", - "UPPULSEOUT": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT" + "DNPULSEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT" + }, + "OUTN1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_OUTN1" + }, + "OUTN65": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_OUTN65" + }, + "RDY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_IDELAYCTRL_RDY" + }, + "REFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IDELAYCTRL_RST" + }, + "UPPULSEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT" + } }, "type": "IDELAYCTRL", "x_coord": 0, @@ -1824,144 +7147,144 @@ } ], "tile_type": "HCLK_IOI", - "wires": [ - "HCLK_DCI_DCIADDRESS0", - "HCLK_DCI_DCIADDRESS1", - "HCLK_DCI_DCIADDRESS2", - "HCLK_DCI_DCIDATA", - "HCLK_DCI_DCIIOUPDATE", - "HCLK_DCI_DCIREFIOUPDATE", - "HCLK_DCI_DCISCLK", - "HCLK_IOI_BUFIO_O0", - "HCLK_IOI_BUFIO_O1", - "HCLK_IOI_BUFIO_O2", - "HCLK_IOI_BUFIO_O3", - "HCLK_IOI_BUFR0_CE", - "HCLK_IOI_BUFR0_CLR", - "HCLK_IOI_BUFR1_CE", - "HCLK_IOI_BUFR1_CLR", - "HCLK_IOI_BUFR2_CE", - "HCLK_IOI_BUFR2_CLR", - "HCLK_IOI_BUFR3_CE", - "HCLK_IOI_BUFR3_CLR", - "HCLK_IOI_CK_BUFHCLK0", - "HCLK_IOI_CK_BUFHCLK1", - "HCLK_IOI_CK_BUFHCLK10", - "HCLK_IOI_CK_BUFHCLK11", - "HCLK_IOI_CK_BUFHCLK2", - "HCLK_IOI_CK_BUFHCLK3", - "HCLK_IOI_CK_BUFHCLK4", - "HCLK_IOI_CK_BUFHCLK5", - "HCLK_IOI_CK_BUFHCLK6", - "HCLK_IOI_CK_BUFHCLK7", - "HCLK_IOI_CK_BUFHCLK8", - "HCLK_IOI_CK_BUFHCLK9", - "HCLK_IOI_CK_BUFRCLK0", - "HCLK_IOI_CK_BUFRCLK1", - "HCLK_IOI_CK_BUFRCLK2", - "HCLK_IOI_CK_BUFRCLK3", - "HCLK_IOI_CK_IGCLK0", - "HCLK_IOI_CK_IGCLK1", - "HCLK_IOI_CK_IGCLK10", - "HCLK_IOI_CK_IGCLK11", - "HCLK_IOI_CK_IGCLK2", - "HCLK_IOI_CK_IGCLK3", - "HCLK_IOI_CK_IGCLK4", - "HCLK_IOI_CK_IGCLK5", - "HCLK_IOI_CK_IGCLK6", - "HCLK_IOI_CK_IGCLK7", - "HCLK_IOI_CK_IGCLK8", - "HCLK_IOI_CK_IGCLK9", - "HCLK_IOI_CK_IN0", - "HCLK_IOI_CK_IN1", - "HCLK_IOI_CK_IN10", - "HCLK_IOI_CK_IN11", - "HCLK_IOI_CK_IN12", - "HCLK_IOI_CK_IN13", - "HCLK_IOI_CK_IN2", - "HCLK_IOI_CK_IN3", - "HCLK_IOI_CK_IN4", - "HCLK_IOI_CK_IN5", - "HCLK_IOI_CK_IN6", - "HCLK_IOI_CK_IN7", - "HCLK_IOI_CK_IN8", - "HCLK_IOI_CK_IN9", - "HCLK_IOI_DCI_DCIDONE", - "HCLK_IOI_DCI_TSTCLK", - "HCLK_IOI_DCI_TSTHLN", - "HCLK_IOI_DCI_TSTHLP", - "HCLK_IOI_DCI_TSTRST", - "HCLK_IOI_I2IOCLK_BOT0", - "HCLK_IOI_I2IOCLK_BOT1", - "HCLK_IOI_I2IOCLK_TOP0", - "HCLK_IOI_I2IOCLK_TOP1", - "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", - "HCLK_IOI_IDELAYCTRL_OUTN1", - "HCLK_IOI_IDELAYCTRL_OUTN65", - "HCLK_IOI_IDELAYCTRL_RDY", - "HCLK_IOI_IDELAYCTRL_REFCLK", - "HCLK_IOI_IDELAYCTRL_RST", - "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", - "HCLK_IOI_INT_DCI_EN", - "HCLK_IOI_IOCLK0", - "HCLK_IOI_IOCLK1", - "HCLK_IOI_IOCLK2", - "HCLK_IOI_IOCLK3", - "HCLK_IOI_IOCLK_PLL0", - "HCLK_IOI_IOCLK_PLL1", - "HCLK_IOI_IOCLK_PLL2", - "HCLK_IOI_IOCLK_PLL3", - "HCLK_IOI_IO_PLL_CLK0", - "HCLK_IOI_IO_PLL_CLK0_DMUX", - "HCLK_IOI_IO_PLL_CLK1", - "HCLK_IOI_IO_PLL_CLK1_DMUX", - "HCLK_IOI_IO_PLL_CLK2", - "HCLK_IOI_IO_PLL_CLK2_DMUX", - "HCLK_IOI_IO_PLL_CLK3", - "HCLK_IOI_IO_PLL_CLK3_DMUX", - "HCLK_IOI_LEAF_GCLK_BOT0", - "HCLK_IOI_LEAF_GCLK_BOT1", - "HCLK_IOI_LEAF_GCLK_BOT2", - "HCLK_IOI_LEAF_GCLK_BOT3", - "HCLK_IOI_LEAF_GCLK_BOT4", - "HCLK_IOI_LEAF_GCLK_BOT5", - "HCLK_IOI_LEAF_GCLK_TOP0", - "HCLK_IOI_LEAF_GCLK_TOP1", - "HCLK_IOI_LEAF_GCLK_TOP2", - "HCLK_IOI_LEAF_GCLK_TOP3", - "HCLK_IOI_LEAF_GCLK_TOP4", - "HCLK_IOI_LEAF_GCLK_TOP5", - "HCLK_IOI_RCLK0", - "HCLK_IOI_RCLK1", - "HCLK_IOI_RCLK2", - "HCLK_IOI_RCLK2IO0", - "HCLK_IOI_RCLK2IO1", - "HCLK_IOI_RCLK2IO2", - "HCLK_IOI_RCLK2IO3", - "HCLK_IOI_RCLK2RCLK0", - "HCLK_IOI_RCLK2RCLK1", - "HCLK_IOI_RCLK2RCLK2", - "HCLK_IOI_RCLK2RCLK3", - "HCLK_IOI_RCLK3", - "HCLK_IOI_RCLK_BEFORE_DIV0", - "HCLK_IOI_RCLK_BEFORE_DIV1", - "HCLK_IOI_RCLK_BEFORE_DIV2", - "HCLK_IOI_RCLK_BEFORE_DIV3", - "HCLK_IOI_RCLK_IMUX0", - "HCLK_IOI_RCLK_IMUX1", - "HCLK_IOI_RCLK_IMUX2", - "HCLK_IOI_RCLK_IMUX3", - "HCLK_IOI_RCLK_OUT0", - "HCLK_IOI_RCLK_OUT1", - "HCLK_IOI_RCLK_OUT2", - "HCLK_IOI_RCLK_OUT3", - "HCLK_RCLK_DIV_CE0", - "HCLK_RCLK_DIV_CE1", - "HCLK_RCLK_DIV_CE2", - "HCLK_RCLK_DIV_CE3", - "HCLK_RCLK_DIV_CLR0", - "HCLK_RCLK_DIV_CLR1", - "HCLK_RCLK_DIV_CLR2", - "HCLK_RCLK_DIV_CLR3" - ] + "wires": { + "HCLK_DCI_DCIADDRESS0": null, + "HCLK_DCI_DCIADDRESS1": null, + "HCLK_DCI_DCIADDRESS2": null, + "HCLK_DCI_DCIDATA": null, + "HCLK_DCI_DCIIOUPDATE": null, + "HCLK_DCI_DCIREFIOUPDATE": null, + "HCLK_DCI_DCISCLK": null, + "HCLK_IOI_BUFIO_O0": null, + "HCLK_IOI_BUFIO_O1": null, + "HCLK_IOI_BUFIO_O2": null, + "HCLK_IOI_BUFIO_O3": null, + "HCLK_IOI_BUFR0_CE": null, + "HCLK_IOI_BUFR0_CLR": null, + "HCLK_IOI_BUFR1_CE": null, + "HCLK_IOI_BUFR1_CLR": null, + "HCLK_IOI_BUFR2_CE": null, + "HCLK_IOI_BUFR2_CLR": null, + "HCLK_IOI_BUFR3_CE": null, + "HCLK_IOI_BUFR3_CLR": null, + "HCLK_IOI_CK_BUFHCLK0": null, + "HCLK_IOI_CK_BUFHCLK1": null, + "HCLK_IOI_CK_BUFHCLK10": null, + "HCLK_IOI_CK_BUFHCLK11": null, + "HCLK_IOI_CK_BUFHCLK2": null, + "HCLK_IOI_CK_BUFHCLK3": null, + "HCLK_IOI_CK_BUFHCLK4": null, + "HCLK_IOI_CK_BUFHCLK5": null, + "HCLK_IOI_CK_BUFHCLK6": null, + "HCLK_IOI_CK_BUFHCLK7": null, + "HCLK_IOI_CK_BUFHCLK8": null, + "HCLK_IOI_CK_BUFHCLK9": null, + "HCLK_IOI_CK_BUFRCLK0": null, + "HCLK_IOI_CK_BUFRCLK1": null, + "HCLK_IOI_CK_BUFRCLK2": null, + "HCLK_IOI_CK_BUFRCLK3": null, + "HCLK_IOI_CK_IGCLK0": null, + "HCLK_IOI_CK_IGCLK1": null, + "HCLK_IOI_CK_IGCLK10": null, + "HCLK_IOI_CK_IGCLK11": null, + "HCLK_IOI_CK_IGCLK2": null, + "HCLK_IOI_CK_IGCLK3": null, + "HCLK_IOI_CK_IGCLK4": null, + "HCLK_IOI_CK_IGCLK5": null, + "HCLK_IOI_CK_IGCLK6": null, + "HCLK_IOI_CK_IGCLK7": null, + "HCLK_IOI_CK_IGCLK8": null, + "HCLK_IOI_CK_IGCLK9": null, + "HCLK_IOI_CK_IN0": null, + "HCLK_IOI_CK_IN1": null, + "HCLK_IOI_CK_IN10": null, + "HCLK_IOI_CK_IN11": null, + "HCLK_IOI_CK_IN12": null, + "HCLK_IOI_CK_IN13": null, + "HCLK_IOI_CK_IN2": null, + "HCLK_IOI_CK_IN3": null, + "HCLK_IOI_CK_IN4": null, + "HCLK_IOI_CK_IN5": null, + "HCLK_IOI_CK_IN6": null, + "HCLK_IOI_CK_IN7": null, + "HCLK_IOI_CK_IN8": null, + "HCLK_IOI_CK_IN9": null, + "HCLK_IOI_DCI_DCIDONE": null, + "HCLK_IOI_DCI_TSTCLK": null, + "HCLK_IOI_DCI_TSTHLN": null, + "HCLK_IOI_DCI_TSTHLP": null, + "HCLK_IOI_DCI_TSTRST": null, + "HCLK_IOI_I2IOCLK_BOT0": null, + "HCLK_IOI_I2IOCLK_BOT1": null, + "HCLK_IOI_I2IOCLK_TOP0": null, + "HCLK_IOI_I2IOCLK_TOP1": null, + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT": null, + "HCLK_IOI_IDELAYCTRL_OUTN1": null, + "HCLK_IOI_IDELAYCTRL_OUTN65": null, + "HCLK_IOI_IDELAYCTRL_RDY": null, + "HCLK_IOI_IDELAYCTRL_REFCLK": null, + "HCLK_IOI_IDELAYCTRL_RST": null, + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT": null, + "HCLK_IOI_INT_DCI_EN": null, + "HCLK_IOI_IOCLK0": null, + "HCLK_IOI_IOCLK1": null, + "HCLK_IOI_IOCLK2": null, + "HCLK_IOI_IOCLK3": null, + "HCLK_IOI_IOCLK_PLL0": null, + "HCLK_IOI_IOCLK_PLL1": null, + "HCLK_IOI_IOCLK_PLL2": null, + "HCLK_IOI_IOCLK_PLL3": null, + "HCLK_IOI_IO_PLL_CLK0": null, + "HCLK_IOI_IO_PLL_CLK0_DMUX": null, + "HCLK_IOI_IO_PLL_CLK1": null, + "HCLK_IOI_IO_PLL_CLK1_DMUX": null, + "HCLK_IOI_IO_PLL_CLK2": null, + "HCLK_IOI_IO_PLL_CLK2_DMUX": null, + "HCLK_IOI_IO_PLL_CLK3": null, + "HCLK_IOI_IO_PLL_CLK3_DMUX": null, + "HCLK_IOI_LEAF_GCLK_BOT0": null, + "HCLK_IOI_LEAF_GCLK_BOT1": null, + "HCLK_IOI_LEAF_GCLK_BOT2": null, + "HCLK_IOI_LEAF_GCLK_BOT3": null, + "HCLK_IOI_LEAF_GCLK_BOT4": null, + "HCLK_IOI_LEAF_GCLK_BOT5": null, + "HCLK_IOI_LEAF_GCLK_TOP0": null, + "HCLK_IOI_LEAF_GCLK_TOP1": null, + "HCLK_IOI_LEAF_GCLK_TOP2": null, + "HCLK_IOI_LEAF_GCLK_TOP3": null, + "HCLK_IOI_LEAF_GCLK_TOP4": null, + "HCLK_IOI_LEAF_GCLK_TOP5": null, + "HCLK_IOI_RCLK0": null, + "HCLK_IOI_RCLK1": null, + "HCLK_IOI_RCLK2": null, + "HCLK_IOI_RCLK2IO0": null, + "HCLK_IOI_RCLK2IO1": null, + "HCLK_IOI_RCLK2IO2": null, + "HCLK_IOI_RCLK2IO3": null, + "HCLK_IOI_RCLK2RCLK0": null, + "HCLK_IOI_RCLK2RCLK1": null, + "HCLK_IOI_RCLK2RCLK2": null, + "HCLK_IOI_RCLK2RCLK3": null, + "HCLK_IOI_RCLK3": null, + "HCLK_IOI_RCLK_BEFORE_DIV0": null, + "HCLK_IOI_RCLK_BEFORE_DIV1": null, + "HCLK_IOI_RCLK_BEFORE_DIV2": null, + "HCLK_IOI_RCLK_BEFORE_DIV3": null, + "HCLK_IOI_RCLK_IMUX0": null, + "HCLK_IOI_RCLK_IMUX1": null, + "HCLK_IOI_RCLK_IMUX2": null, + "HCLK_IOI_RCLK_IMUX3": null, + "HCLK_IOI_RCLK_OUT0": null, + "HCLK_IOI_RCLK_OUT1": null, + "HCLK_IOI_RCLK_OUT2": null, + "HCLK_IOI_RCLK_OUT3": null, + "HCLK_RCLK_DIV_CE0": null, + "HCLK_RCLK_DIV_CE1": null, + "HCLK_RCLK_DIV_CE2": null, + "HCLK_RCLK_DIV_CE3": null, + "HCLK_RCLK_DIV_CLR0": null, + "HCLK_RCLK_DIV_CLR1": null, + "HCLK_RCLK_DIV_CLR2": null, + "HCLK_RCLK_DIV_CLR3": null + } } diff --git a/kintex7/tile_type_HCLK_IOI3.json b/kintex7/tile_type_HCLK_IOI3.json index 422034a..bbc5ca1 100644 --- a/kintex7/tile_type_HCLK_IOI3.json +++ b/kintex7/tile_type_HCLK_IOI3.json @@ -2,1710 +2,6754 @@ "pips": { "HCLK_IOI3.HCLK_IOI_BUFIO_O0->>HCLK_IOI_IOCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O0" }, "HCLK_IOI3.HCLK_IOI_BUFIO_O1->>HCLK_IOI_IOCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O1" }, "HCLK_IOI3.HCLK_IOI_BUFIO_O2->>HCLK_IOI_IOCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O2" }, "HCLK_IOI3.HCLK_IOI_BUFIO_O3->>HCLK_IOI_IOCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_IOCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_BUFIO_O3" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK0->>HCLK_IOI_CK_IGCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK1->>HCLK_IOI_CK_IGCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK10->>HCLK_IOI_CK_IGCLK10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK10" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK11->>HCLK_IOI_CK_IGCLK11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK11" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK2->>HCLK_IOI_CK_IGCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK3->>HCLK_IOI_CK_IGCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK3" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK4->>HCLK_IOI_CK_IGCLK4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK4" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK5->>HCLK_IOI_CK_IGCLK5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK5" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK6->>HCLK_IOI_CK_IGCLK6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK6" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK7->>HCLK_IOI_CK_IGCLK7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK7", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK8->>HCLK_IOI_CK_IGCLK8": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK8", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_BUFHCLK9->>HCLK_IOI_CK_IGCLK9": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_CK_IGCLK9", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.141", + "0.151", + "0.230", + "0.258" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_CK_BUFHCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK0->>HCLK_IOI_RCLK2IO0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK1->>HCLK_IOI_RCLK2IO1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK2->>HCLK_IOI_RCLK2IO2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_BUFRCLK3->>HCLK_IOI_RCLK2IO3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_RCLK2IO3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.161", + "0.185", + "0.294", + "0.318" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_BUFRCLK3" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK0" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK0->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" 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"dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK1" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK1->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": 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"delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK10" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK10->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": 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"dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK11" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK11->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": 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"0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", 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"delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK2->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK2" }, 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"dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK3" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK3->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": 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}, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK4->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK4" }, 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"dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK5" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK5->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": 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"dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + 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"0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK7" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK7->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": 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"delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK8->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK8" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_CK_IGCLK9->>HCLK_IOI_LEAF_GCLK_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_LEAF_GCLK_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_CK_IGCLK9" }, "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT0->>HCLK_IOI_IO_PLL_CLK2_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_BOT0" }, "HCLK_IOI3.HCLK_IOI_I2IOCLK_BOT1->>HCLK_IOI_IO_PLL_CLK3_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_BOT1" }, "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_TOP0" }, "HCLK_IOI3.HCLK_IOI_I2IOCLK_TOP1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.103", + "0.119", + "0.155", + "0.203" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_I2IOCLK_TOP1" }, "HCLK_IOI3.HCLK_IOI_IOCLK_PLL0->>HCLK_IOI_IO_PLL_CLK0_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL0" }, "HCLK_IOI3.HCLK_IOI_IOCLK_PLL1->>HCLK_IOI_IO_PLL_CLK1_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL1" }, "HCLK_IOI3.HCLK_IOI_IOCLK_PLL2->>HCLK_IOI_IO_PLL_CLK2_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL2" }, "HCLK_IOI3.HCLK_IOI_IOCLK_PLL3->>HCLK_IOI_IO_PLL_CLK3_DMUX": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_IOCLK_PLL3" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_IO_PLL_CLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK0_DMUX->>HCLK_IOI_RCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK0_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_IO_PLL_CLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK1_DMUX->>HCLK_IOI_RCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK1_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_IO_PLL_CLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK2_DMUX->>HCLK_IOI_RCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK2_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_IO_PLL_CLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IO_PLL_CLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.034", + "0.040", + "0.047", + "0.055" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" }, "HCLK_IOI3.HCLK_IOI_IO_PLL_CLK3_DMUX->>HCLK_IOI_RCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.063", + "0.073", + "0.112", + "0.129" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "HCLK_IOI_IO_PLL_CLK3_DMUX" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT0->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT0" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT1->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT1" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT2->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT2" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT3->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT3" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT4->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT4" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_BOT5->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_BOT5" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP0->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP0" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP1->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP1" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP2->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP2" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP3->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP3" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP4->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP4" }, "HCLK_IOI3.HCLK_IOI_LEAF_GCLK_TOP5->>HCLK_IOI_IDELAYCTRL_REFCLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_IDELAYCTRL_REFCLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_LEAF_GCLK_TOP5" }, "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI3.HCLK_IOI_RCLK0->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK0" }, "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI3.HCLK_IOI_RCLK1->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK1" }, "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI3.HCLK_IOI_RCLK2->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK2" }, "HCLK_IOI3.HCLK_IOI_RCLK2RCLK0->>HCLK_IOI_CK_BUFRCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_CK_BUFRCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_RCLK2RCLK0" }, "HCLK_IOI3.HCLK_IOI_RCLK2RCLK1->>HCLK_IOI_CK_BUFRCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_CK_BUFRCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_RCLK2RCLK1" }, "HCLK_IOI3.HCLK_IOI_RCLK2RCLK2->>HCLK_IOI_CK_BUFRCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_CK_BUFRCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_RCLK2RCLK2" }, "HCLK_IOI3.HCLK_IOI_RCLK2RCLK3->>HCLK_IOI_CK_BUFRCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_IOI_CK_BUFRCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_IOI_RCLK2RCLK3" }, "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK3" }, "HCLK_IOI3.HCLK_IOI_RCLK3->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + 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"0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX0" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX0" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX0->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": 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"HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX1" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX1" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX1->>HCLK_IOI_RCLK_BEFORE_DIV3": { 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"0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX2" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX2" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX2->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX2" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI3.HCLK_IOI_RCLK_IMUX3->>HCLK_IOI_RCLK_BEFORE_DIV3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK_BEFORE_DIV3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_IMUX3" }, "HCLK_IOI3.HCLK_IOI_RCLK_OUT0->>HCLK_IOI_RCLK2RCLK0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT0" }, "HCLK_IOI3.HCLK_IOI_RCLK_OUT1->>HCLK_IOI_RCLK2RCLK1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT1" }, "HCLK_IOI3.HCLK_IOI_RCLK_OUT2->>HCLK_IOI_RCLK2RCLK2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT2" }, "HCLK_IOI3.HCLK_IOI_RCLK_OUT3->>HCLK_IOI_RCLK2RCLK3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_IOI_RCLK2RCLK3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_IOI_RCLK_OUT3" }, "HCLK_IOI3.HCLK_RCLK_DIV_CE0->HCLK_IOI_BUFR0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE0" }, "HCLK_IOI3.HCLK_RCLK_DIV_CE1->HCLK_IOI_BUFR1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE1" }, "HCLK_IOI3.HCLK_RCLK_DIV_CE2->HCLK_IOI_BUFR2_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR2_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE2" }, "HCLK_IOI3.HCLK_RCLK_DIV_CE3->HCLK_IOI_BUFR3_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR3_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CE3" }, "HCLK_IOI3.HCLK_RCLK_DIV_CLR0->HCLK_IOI_BUFR0_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR0_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR0" }, "HCLK_IOI3.HCLK_RCLK_DIV_CLR1->HCLK_IOI_BUFR1_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR1_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR1" }, "HCLK_IOI3.HCLK_RCLK_DIV_CLR2->HCLK_IOI_BUFR2_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR2_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR2" }, "HCLK_IOI3.HCLK_RCLK_DIV_CLR3->HCLK_IOI_BUFR3_CLR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "HCLK_IOI_BUFR3_CLR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "HCLK_RCLK_DIV_CLR3" } }, @@ -1714,8 +6758,26 @@ "name": "X0Y1", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK3", - "O": "HCLK_IOI_BUFIO_O3" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O3" + } }, "type": "BUFIO", "x_coord": 0, @@ -1725,8 +6787,26 @@ "name": "X0Y0", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK2", - "O": "HCLK_IOI_BUFIO_O2" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O2" + } }, "type": "BUFIO", "x_coord": 0, @@ -1736,8 +6816,26 @@ "name": "X0Y3", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK1", - "O": "HCLK_IOI_BUFIO_O1" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O1" + } }, "type": "BUFIO", "x_coord": 0, @@ -1747,8 +6845,26 @@ "name": "X0Y2", "prefix": "BUFIO", "site_pins": { - "I": "HCLK_IOI_IO_PLL_CLK0", - "O": "HCLK_IOI_BUFIO_O0" + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IO_PLL_CLK0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_BUFIO_O0" + } }, "type": "BUFIO", "x_coord": 0, @@ -1758,10 +6874,46 @@ "name": "X0Y1", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR3_CE", - "CLR": "HCLK_IOI_BUFR3_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV3", - "O": "HCLK_IOI_RCLK_OUT3" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR3_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR3_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV3" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT3" + } }, "type": "BUFR", "x_coord": 0, @@ -1771,10 +6923,46 @@ "name": "X0Y0", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR2_CE", - "CLR": "HCLK_IOI_BUFR2_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV2", - "O": "HCLK_IOI_RCLK_OUT2" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR2_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR2_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV2" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT2" + } }, "type": "BUFR", "x_coord": 0, @@ -1784,10 +6972,46 @@ "name": "X0Y3", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR1_CE", - "CLR": "HCLK_IOI_BUFR1_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV1", - "O": "HCLK_IOI_RCLK_OUT1" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR1_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR1_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV1" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT1" + } }, "type": "BUFR", "x_coord": 0, @@ -1797,10 +7021,46 @@ "name": "X0Y2", "prefix": "BUFR", "site_pins": { - "CE": "HCLK_IOI_BUFR0_CE", - "CLR": "HCLK_IOI_BUFR0_CLR", - "I": "HCLK_IOI_RCLK_BEFORE_DIV0", - "O": "HCLK_IOI_RCLK_OUT0" + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR0_CE" + }, + "CLR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_BUFR0_CLR" + }, + "I": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_RCLK_BEFORE_DIV0" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_RCLK_OUT0" + } }, "type": "BUFR", "x_coord": 0, @@ -1810,13 +7070,76 @@ "name": "X0Y0", "prefix": "IDELAYCTRL", "site_pins": { - "DNPULSEOUT": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", - "OUTN1": "HCLK_IOI_IDELAYCTRL_OUTN1", - "OUTN65": "HCLK_IOI_IDELAYCTRL_OUTN65", - "RDY": "HCLK_IOI_IDELAYCTRL_RDY", - "REFCLK": "HCLK_IOI_IDELAYCTRL_REFCLK", - "RST": "HCLK_IOI_IDELAYCTRL_RST", - "UPPULSEOUT": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT" + "DNPULSEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_DNPULSEOUT" + }, + "OUTN1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_OUTN1" + }, + "OUTN65": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_OUTN65" + }, + "RDY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "HCLK_IOI_IDELAYCTRL_RDY" + }, + "REFCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IDELAYCTRL_REFCLK" + }, + "RST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "HCLK_IOI_IDELAYCTRL_RST" + }, + "UPPULSEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "HCLK_IOI_IDELAYCTRL_UPPULSEOUT" + } }, "type": "IDELAYCTRL", "x_coord": 0, @@ -1824,131 +7147,131 @@ } ], "tile_type": "HCLK_IOI3", - "wires": [ - "HCLK_IOI_BUFIO_O0", - "HCLK_IOI_BUFIO_O1", - "HCLK_IOI_BUFIO_O2", - "HCLK_IOI_BUFIO_O3", - "HCLK_IOI_BUFR0_CE", - "HCLK_IOI_BUFR0_CLR", - "HCLK_IOI_BUFR1_CE", - "HCLK_IOI_BUFR1_CLR", - "HCLK_IOI_BUFR2_CE", - "HCLK_IOI_BUFR2_CLR", - "HCLK_IOI_BUFR3_CE", - "HCLK_IOI_BUFR3_CLR", - "HCLK_IOI_CK_BUFHCLK0", - "HCLK_IOI_CK_BUFHCLK1", - "HCLK_IOI_CK_BUFHCLK10", - "HCLK_IOI_CK_BUFHCLK11", - "HCLK_IOI_CK_BUFHCLK2", - "HCLK_IOI_CK_BUFHCLK3", - "HCLK_IOI_CK_BUFHCLK4", - "HCLK_IOI_CK_BUFHCLK5", - "HCLK_IOI_CK_BUFHCLK6", - "HCLK_IOI_CK_BUFHCLK7", - "HCLK_IOI_CK_BUFHCLK8", - "HCLK_IOI_CK_BUFHCLK9", - "HCLK_IOI_CK_BUFRCLK0", - "HCLK_IOI_CK_BUFRCLK1", - "HCLK_IOI_CK_BUFRCLK2", - "HCLK_IOI_CK_BUFRCLK3", - "HCLK_IOI_CK_IGCLK0", - "HCLK_IOI_CK_IGCLK1", - "HCLK_IOI_CK_IGCLK10", - "HCLK_IOI_CK_IGCLK11", - "HCLK_IOI_CK_IGCLK2", - "HCLK_IOI_CK_IGCLK3", - "HCLK_IOI_CK_IGCLK4", - "HCLK_IOI_CK_IGCLK5", - "HCLK_IOI_CK_IGCLK6", - "HCLK_IOI_CK_IGCLK7", - "HCLK_IOI_CK_IGCLK8", - "HCLK_IOI_CK_IGCLK9", - "HCLK_IOI_CK_IN0", - "HCLK_IOI_CK_IN1", - "HCLK_IOI_CK_IN10", - "HCLK_IOI_CK_IN11", - "HCLK_IOI_CK_IN12", - "HCLK_IOI_CK_IN13", - "HCLK_IOI_CK_IN2", - "HCLK_IOI_CK_IN3", - "HCLK_IOI_CK_IN4", - "HCLK_IOI_CK_IN5", - "HCLK_IOI_CK_IN6", - "HCLK_IOI_CK_IN7", - "HCLK_IOI_CK_IN8", - "HCLK_IOI_CK_IN9", - "HCLK_IOI_I2IOCLK_BOT0", - "HCLK_IOI_I2IOCLK_BOT1", - "HCLK_IOI_I2IOCLK_TOP0", - "HCLK_IOI_I2IOCLK_TOP1", - "HCLK_IOI_IDELAYCTRL_DNPULSEOUT", - "HCLK_IOI_IDELAYCTRL_OUTN1", - "HCLK_IOI_IDELAYCTRL_OUTN65", - "HCLK_IOI_IDELAYCTRL_RDY", - "HCLK_IOI_IDELAYCTRL_REFCLK", - "HCLK_IOI_IDELAYCTRL_RST", - "HCLK_IOI_IDELAYCTRL_UPPULSEOUT", - "HCLK_IOI_IOCLK0", - "HCLK_IOI_IOCLK1", - "HCLK_IOI_IOCLK2", - "HCLK_IOI_IOCLK3", - "HCLK_IOI_IOCLK_PLL0", - "HCLK_IOI_IOCLK_PLL1", - "HCLK_IOI_IOCLK_PLL2", - "HCLK_IOI_IOCLK_PLL3", - "HCLK_IOI_IO_PLL_CLK0", - "HCLK_IOI_IO_PLL_CLK0_DMUX", - "HCLK_IOI_IO_PLL_CLK1", - "HCLK_IOI_IO_PLL_CLK1_DMUX", - "HCLK_IOI_IO_PLL_CLK2", - "HCLK_IOI_IO_PLL_CLK2_DMUX", - "HCLK_IOI_IO_PLL_CLK3", - "HCLK_IOI_IO_PLL_CLK3_DMUX", - "HCLK_IOI_LEAF_GCLK_BOT0", - "HCLK_IOI_LEAF_GCLK_BOT1", - "HCLK_IOI_LEAF_GCLK_BOT2", - "HCLK_IOI_LEAF_GCLK_BOT3", - "HCLK_IOI_LEAF_GCLK_BOT4", - "HCLK_IOI_LEAF_GCLK_BOT5", - "HCLK_IOI_LEAF_GCLK_TOP0", - "HCLK_IOI_LEAF_GCLK_TOP1", - "HCLK_IOI_LEAF_GCLK_TOP2", - "HCLK_IOI_LEAF_GCLK_TOP3", - "HCLK_IOI_LEAF_GCLK_TOP4", - "HCLK_IOI_LEAF_GCLK_TOP5", - "HCLK_IOI_RCLK0", - "HCLK_IOI_RCLK1", - "HCLK_IOI_RCLK2", - "HCLK_IOI_RCLK2IO0", - "HCLK_IOI_RCLK2IO1", - "HCLK_IOI_RCLK2IO2", - "HCLK_IOI_RCLK2IO3", - "HCLK_IOI_RCLK2RCLK0", - "HCLK_IOI_RCLK2RCLK1", - "HCLK_IOI_RCLK2RCLK2", - "HCLK_IOI_RCLK2RCLK3", - "HCLK_IOI_RCLK3", - "HCLK_IOI_RCLK_BEFORE_DIV0", - "HCLK_IOI_RCLK_BEFORE_DIV1", - "HCLK_IOI_RCLK_BEFORE_DIV2", - "HCLK_IOI_RCLK_BEFORE_DIV3", - "HCLK_IOI_RCLK_IMUX0", - "HCLK_IOI_RCLK_IMUX1", - "HCLK_IOI_RCLK_IMUX2", - "HCLK_IOI_RCLK_IMUX3", - "HCLK_IOI_RCLK_OUT0", - "HCLK_IOI_RCLK_OUT1", - "HCLK_IOI_RCLK_OUT2", - "HCLK_IOI_RCLK_OUT3", - "HCLK_RCLK_DIV_CE0", - "HCLK_RCLK_DIV_CE1", - "HCLK_RCLK_DIV_CE2", - "HCLK_RCLK_DIV_CE3", - "HCLK_RCLK_DIV_CLR0", - "HCLK_RCLK_DIV_CLR1", - "HCLK_RCLK_DIV_CLR2", - "HCLK_RCLK_DIV_CLR3" - ] + "wires": { + "HCLK_IOI_BUFIO_O0": null, + "HCLK_IOI_BUFIO_O1": null, + "HCLK_IOI_BUFIO_O2": null, + "HCLK_IOI_BUFIO_O3": null, + "HCLK_IOI_BUFR0_CE": null, + "HCLK_IOI_BUFR0_CLR": null, + "HCLK_IOI_BUFR1_CE": null, + "HCLK_IOI_BUFR1_CLR": null, + "HCLK_IOI_BUFR2_CE": null, + "HCLK_IOI_BUFR2_CLR": null, + "HCLK_IOI_BUFR3_CE": null, + "HCLK_IOI_BUFR3_CLR": null, + "HCLK_IOI_CK_BUFHCLK0": null, + "HCLK_IOI_CK_BUFHCLK1": null, + "HCLK_IOI_CK_BUFHCLK10": null, + "HCLK_IOI_CK_BUFHCLK11": null, + "HCLK_IOI_CK_BUFHCLK2": null, + "HCLK_IOI_CK_BUFHCLK3": null, + "HCLK_IOI_CK_BUFHCLK4": null, + "HCLK_IOI_CK_BUFHCLK5": null, + "HCLK_IOI_CK_BUFHCLK6": null, + "HCLK_IOI_CK_BUFHCLK7": null, + "HCLK_IOI_CK_BUFHCLK8": null, + "HCLK_IOI_CK_BUFHCLK9": null, + "HCLK_IOI_CK_BUFRCLK0": null, + "HCLK_IOI_CK_BUFRCLK1": null, + "HCLK_IOI_CK_BUFRCLK2": null, + "HCLK_IOI_CK_BUFRCLK3": null, + "HCLK_IOI_CK_IGCLK0": null, + "HCLK_IOI_CK_IGCLK1": null, + "HCLK_IOI_CK_IGCLK10": null, + "HCLK_IOI_CK_IGCLK11": null, + "HCLK_IOI_CK_IGCLK2": null, + "HCLK_IOI_CK_IGCLK3": null, + "HCLK_IOI_CK_IGCLK4": null, + "HCLK_IOI_CK_IGCLK5": null, + "HCLK_IOI_CK_IGCLK6": null, + "HCLK_IOI_CK_IGCLK7": null, + "HCLK_IOI_CK_IGCLK8": null, + "HCLK_IOI_CK_IGCLK9": null, + "HCLK_IOI_CK_IN0": null, + "HCLK_IOI_CK_IN1": null, + "HCLK_IOI_CK_IN10": null, + "HCLK_IOI_CK_IN11": null, + "HCLK_IOI_CK_IN12": null, + "HCLK_IOI_CK_IN13": null, + "HCLK_IOI_CK_IN2": null, + "HCLK_IOI_CK_IN3": null, + "HCLK_IOI_CK_IN4": null, + "HCLK_IOI_CK_IN5": null, + "HCLK_IOI_CK_IN6": null, + "HCLK_IOI_CK_IN7": null, + "HCLK_IOI_CK_IN8": null, + "HCLK_IOI_CK_IN9": null, + "HCLK_IOI_I2IOCLK_BOT0": null, + "HCLK_IOI_I2IOCLK_BOT1": null, + "HCLK_IOI_I2IOCLK_TOP0": null, + "HCLK_IOI_I2IOCLK_TOP1": null, + "HCLK_IOI_IDELAYCTRL_DNPULSEOUT": null, + "HCLK_IOI_IDELAYCTRL_OUTN1": null, + "HCLK_IOI_IDELAYCTRL_OUTN65": null, + "HCLK_IOI_IDELAYCTRL_RDY": null, + "HCLK_IOI_IDELAYCTRL_REFCLK": null, + "HCLK_IOI_IDELAYCTRL_RST": null, + "HCLK_IOI_IDELAYCTRL_UPPULSEOUT": null, + "HCLK_IOI_IOCLK0": null, + "HCLK_IOI_IOCLK1": null, + "HCLK_IOI_IOCLK2": null, + "HCLK_IOI_IOCLK3": null, + "HCLK_IOI_IOCLK_PLL0": null, + "HCLK_IOI_IOCLK_PLL1": null, + "HCLK_IOI_IOCLK_PLL2": null, + "HCLK_IOI_IOCLK_PLL3": null, + "HCLK_IOI_IO_PLL_CLK0": null, + "HCLK_IOI_IO_PLL_CLK0_DMUX": null, + "HCLK_IOI_IO_PLL_CLK1": null, + "HCLK_IOI_IO_PLL_CLK1_DMUX": null, + "HCLK_IOI_IO_PLL_CLK2": null, + "HCLK_IOI_IO_PLL_CLK2_DMUX": null, + "HCLK_IOI_IO_PLL_CLK3": null, + "HCLK_IOI_IO_PLL_CLK3_DMUX": null, + "HCLK_IOI_LEAF_GCLK_BOT0": null, + "HCLK_IOI_LEAF_GCLK_BOT1": null, + "HCLK_IOI_LEAF_GCLK_BOT2": null, + "HCLK_IOI_LEAF_GCLK_BOT3": null, + "HCLK_IOI_LEAF_GCLK_BOT4": null, + "HCLK_IOI_LEAF_GCLK_BOT5": null, + "HCLK_IOI_LEAF_GCLK_TOP0": null, + "HCLK_IOI_LEAF_GCLK_TOP1": null, + "HCLK_IOI_LEAF_GCLK_TOP2": null, + "HCLK_IOI_LEAF_GCLK_TOP3": null, + "HCLK_IOI_LEAF_GCLK_TOP4": null, + "HCLK_IOI_LEAF_GCLK_TOP5": null, + "HCLK_IOI_RCLK0": null, + "HCLK_IOI_RCLK1": null, + "HCLK_IOI_RCLK2": null, + "HCLK_IOI_RCLK2IO0": null, + "HCLK_IOI_RCLK2IO1": null, + "HCLK_IOI_RCLK2IO2": null, + "HCLK_IOI_RCLK2IO3": null, + "HCLK_IOI_RCLK2RCLK0": null, + "HCLK_IOI_RCLK2RCLK1": null, + "HCLK_IOI_RCLK2RCLK2": null, + "HCLK_IOI_RCLK2RCLK3": null, + "HCLK_IOI_RCLK3": null, + "HCLK_IOI_RCLK_BEFORE_DIV0": null, + "HCLK_IOI_RCLK_BEFORE_DIV1": null, + "HCLK_IOI_RCLK_BEFORE_DIV2": null, + "HCLK_IOI_RCLK_BEFORE_DIV3": null, + "HCLK_IOI_RCLK_IMUX0": null, + "HCLK_IOI_RCLK_IMUX1": null, + "HCLK_IOI_RCLK_IMUX2": null, + "HCLK_IOI_RCLK_IMUX3": null, + "HCLK_IOI_RCLK_OUT0": null, + "HCLK_IOI_RCLK_OUT1": null, + "HCLK_IOI_RCLK_OUT2": null, + "HCLK_IOI_RCLK_OUT3": null, + "HCLK_RCLK_DIV_CE0": null, + "HCLK_RCLK_DIV_CE1": null, + "HCLK_RCLK_DIV_CE2": null, + "HCLK_RCLK_DIV_CE3": null, + "HCLK_RCLK_DIV_CLR0": null, + "HCLK_RCLK_DIV_CLR1": null, + "HCLK_RCLK_DIV_CLR2": null, + "HCLK_RCLK_DIV_CLR3": null + } } diff --git a/kintex7/tile_type_HCLK_L.json b/kintex7/tile_type_HCLK_L.json index 7fe9cbe..55b7e5b 100644 --- a/kintex7/tile_type_HCLK_L.json +++ b/kintex7/tile_type_HCLK_L.json @@ -2,1694 +2,6545 @@ "pips": { "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_CK_INOUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_CK_INOUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_CK_INOUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_CK_INOUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_CK_INOUT_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK0" }, "HCLK_L.HCLK_CK_BUFRCLK0->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, 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"src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK1->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK1" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_CK_INOUT_L6": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L6", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK2->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK2" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_CK_INOUT_L7": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, 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"src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_BUFRCLK3->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFRCLK3" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L0->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L0" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L1" }, "HCLK_L.HCLK_CK_OUTIN_L1->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, 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"src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L2" }, "HCLK_L.HCLK_CK_OUTIN_L2->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + 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"src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L3->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L3" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L4->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L4" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L5->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L5" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L6->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L6" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_BOTL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOTL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" }, "HCLK_L.HCLK_CK_OUTIN_L7->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_L7" } }, "sites": [], "tile_type": "HCLK_L", - "wires": [ - "HCLK_BYP_BOUNCE2", - "HCLK_BYP_BOUNCE3", - "HCLK_BYP_BOUNCE6", - "HCLK_BYP_BOUNCE7", - "HCLK_CCIO0", - "HCLK_CCIO1", - "HCLK_CCIO2", - "HCLK_CCIO3", - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK3", - "HCLK_CK_IN0", - "HCLK_CK_IN1", - "HCLK_CK_IN10", - "HCLK_CK_IN11", - "HCLK_CK_IN12", - "HCLK_CK_IN13", - "HCLK_CK_IN2", - "HCLK_CK_IN3", - "HCLK_CK_IN4", - "HCLK_CK_IN5", - "HCLK_CK_IN6", - "HCLK_CK_IN7", - "HCLK_CK_IN8", - "HCLK_CK_IN9", - "HCLK_CK_INOUT_L0", - "HCLK_CK_INOUT_L1", - "HCLK_CK_INOUT_L2", - "HCLK_CK_INOUT_L3", - "HCLK_CK_INOUT_L4", - "HCLK_CK_INOUT_L5", - "HCLK_CK_INOUT_L6", - "HCLK_CK_INOUT_L7", - "HCLK_CK_OUTIN_L0", - "HCLK_CK_OUTIN_L1", - "HCLK_CK_OUTIN_L2", - "HCLK_CK_OUTIN_L3", - "HCLK_CK_OUTIN_L4", - "HCLK_CK_OUTIN_L5", - "HCLK_CK_OUTIN_L6", - "HCLK_CK_OUTIN_L7", - "HCLK_EL1BEG3", - "HCLK_EL1END_S3_0", - "HCLK_ER1BEG_S0", - "HCLK_ER1END3", - "HCLK_FAN_BOUNCE_S3_0", - "HCLK_FAN_BOUNCE_S3_2", - "HCLK_FAN_BOUNCE_S3_4", - "HCLK_FAN_BOUNCE_S3_6", - "HCLK_INT_PERFCLK0", - "HCLK_INT_PERFCLK1", - "HCLK_INT_PERFCLK2", - "HCLK_INT_PERFCLK3", - "HCLK_LEAF_CLK_B_BOTL0", - "HCLK_LEAF_CLK_B_BOTL1", - "HCLK_LEAF_CLK_B_BOTL2", - "HCLK_LEAF_CLK_B_BOTL3", - "HCLK_LEAF_CLK_B_BOTL4", - "HCLK_LEAF_CLK_B_BOTL5", - "HCLK_LEAF_CLK_B_TOPL0", - "HCLK_LEAF_CLK_B_TOPL1", - "HCLK_LEAF_CLK_B_TOPL2", - "HCLK_LEAF_CLK_B_TOPL3", - "HCLK_LEAF_CLK_B_TOPL4", - "HCLK_LEAF_CLK_B_TOPL5", - "HCLK_LV0", - "HCLK_LV1", - "HCLK_LV10", - "HCLK_LV11", - "HCLK_LV12", - "HCLK_LV13", - "HCLK_LV14", - "HCLK_LV15", - "HCLK_LV16", - "HCLK_LV17", - "HCLK_LV2", - "HCLK_LV3", - "HCLK_LV4", - "HCLK_LV5", - "HCLK_LV6", - "HCLK_LV7", - "HCLK_LV8", - "HCLK_LV9", - "HCLK_LVB1", - "HCLK_LVB10", - "HCLK_LVB11", - "HCLK_LVB12", - "HCLK_LVB2", - "HCLK_LVB3", - "HCLK_LVB4", - "HCLK_LVB5", - "HCLK_LVB6", - "HCLK_LVB7", - "HCLK_LVB8", - "HCLK_LVB9", - "HCLK_NE2BEG0", - "HCLK_NE2BEG1", - "HCLK_NE2BEG2", - "HCLK_NE2BEG3", - "HCLK_NE2END_S3_0", - "HCLK_NE6A0", - "HCLK_NE6A1", - "HCLK_NE6A2", - "HCLK_NE6A3", - "HCLK_NE6B0", - "HCLK_NE6B1", - "HCLK_NE6B2", - "HCLK_NE6B3", - "HCLK_NE6C0", - "HCLK_NE6C1", - "HCLK_NE6C2", - "HCLK_NE6C3", - "HCLK_NE6D0", - "HCLK_NE6D1", - "HCLK_NE6D2", - "HCLK_NE6D3", - "HCLK_NL1BEG0", - "HCLK_NL1BEG1", - "HCLK_NL1BEG2", - "HCLK_NL1END_S3_0", - "HCLK_NN2A0", - "HCLK_NN2A1", - "HCLK_NN2A2", - "HCLK_NN2A3", - "HCLK_NN2BEG0", - "HCLK_NN2BEG1", - "HCLK_NN2BEG2", - "HCLK_NN2BEG3", - "HCLK_NN2END_S2_0", - "HCLK_NN6A0", - "HCLK_NN6A1", - "HCLK_NN6A2", - "HCLK_NN6A3", - "HCLK_NN6B0", - "HCLK_NN6B1", - "HCLK_NN6B2", - "HCLK_NN6B3", - "HCLK_NN6BEG0", - "HCLK_NN6BEG1", - "HCLK_NN6BEG2", - "HCLK_NN6BEG3", - "HCLK_NN6C0", - "HCLK_NN6C1", - "HCLK_NN6C2", - "HCLK_NN6C3", - "HCLK_NN6D0", - "HCLK_NN6D1", - "HCLK_NN6D2", - "HCLK_NN6D3", - "HCLK_NN6E0", - "HCLK_NN6E1", - "HCLK_NN6E2", - "HCLK_NN6E3", - "HCLK_NN6END_S1_0", - "HCLK_NR1BEG0", - "HCLK_NR1BEG1", - "HCLK_NR1BEG2", - "HCLK_NR1BEG3", - "HCLK_NW2A0", - "HCLK_NW2A1", - "HCLK_NW2A2", - "HCLK_NW2A3", - "HCLK_NW2END_S0_0", - "HCLK_NW6A0", - "HCLK_NW6A1", - "HCLK_NW6A2", - "HCLK_NW6A3", - "HCLK_NW6B0", - "HCLK_NW6B1", - "HCLK_NW6B2", - "HCLK_NW6B3", - "HCLK_NW6C0", - "HCLK_NW6C1", - "HCLK_NW6C2", - "HCLK_NW6C3", - "HCLK_NW6D0", - "HCLK_NW6D1", - "HCLK_NW6D2", - "HCLK_NW6D3", - "HCLK_NW6END_S0_0", - "HCLK_REFCK_EASTCLK0", - "HCLK_REFCK_EASTCLK1", - "HCLK_REFCK_WESTCLK0", - "HCLK_REFCK_WESTCLK1", - "HCLK_SE2A0", - "HCLK_SE2A1", - "HCLK_SE2A2", - "HCLK_SE2A3", - "HCLK_SE6B0", - "HCLK_SE6B1", - "HCLK_SE6B2", - "HCLK_SE6B3", - "HCLK_SE6C0", - "HCLK_SE6C1", - "HCLK_SE6C2", - "HCLK_SE6C3", - "HCLK_SE6D0", - "HCLK_SE6D1", - "HCLK_SE6D2", - "HCLK_SE6D3", - "HCLK_SE6E0", - "HCLK_SE6E1", - "HCLK_SE6E2", - "HCLK_SE6E3", - "HCLK_SL1END0", - "HCLK_SL1END1", - "HCLK_SL1END2", - "HCLK_SL1END3", - "HCLK_SR1BEG3", - "HCLK_SR1END1", - "HCLK_SR1END2", - "HCLK_SR1END_N3_3", - "HCLK_SS2A0", - "HCLK_SS2A1", - "HCLK_SS2A2", - "HCLK_SS2A3", - "HCLK_SS2BEG3", - "HCLK_SS2END0", - "HCLK_SS2END1", - "HCLK_SS2END2", - "HCLK_SS2END_N0_3", - "HCLK_SS6A0", - "HCLK_SS6A1", - "HCLK_SS6A2", - "HCLK_SS6A3", - "HCLK_SS6B0", - "HCLK_SS6B1", - "HCLK_SS6B2", - "HCLK_SS6B3", - "HCLK_SS6C0", - "HCLK_SS6C1", - "HCLK_SS6C2", - "HCLK_SS6C3", - "HCLK_SS6D0", - "HCLK_SS6D1", - "HCLK_SS6D2", - "HCLK_SS6D3", - "HCLK_SS6E0", - "HCLK_SS6E1", - "HCLK_SS6E2", - "HCLK_SS6E3", - "HCLK_SS6END0", - "HCLK_SS6END1", - "HCLK_SS6END2", - "HCLK_SS6END3", - "HCLK_SS6END_N0_3", - "HCLK_SW2A3", - "HCLK_SW2END0", - "HCLK_SW2END1", - "HCLK_SW2END2", - "HCLK_SW2END_N0_3", - "HCLK_SW6B0", - "HCLK_SW6B1", - "HCLK_SW6B2", - "HCLK_SW6B3", - "HCLK_SW6C0", - "HCLK_SW6C1", - "HCLK_SW6C2", - "HCLK_SW6C3", - "HCLK_SW6D0", - "HCLK_SW6D1", - "HCLK_SW6D2", - "HCLK_SW6D3", - "HCLK_SW6E0", - "HCLK_SW6E1", - "HCLK_SW6E2", - "HCLK_SW6E3", - "HCLK_SW6END3", - "HCLK_WL1BEG3", - "HCLK_WL1END3", - "HCLK_WR1BEG_S0", - "HCLK_WR1END_S1_0", - "HCLK_WW2END3", - "HCLK_WW4END_S0_0" - ] + "wires": { + "HCLK_BYP_BOUNCE2": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE3": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE6": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE7": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_CCIO0": null, + "HCLK_CCIO1": null, + "HCLK_CCIO2": null, + "HCLK_CCIO3": null, + "HCLK_CK_BUFHCLK0": null, + "HCLK_CK_BUFHCLK1": null, + "HCLK_CK_BUFHCLK10": null, + "HCLK_CK_BUFHCLK11": null, + "HCLK_CK_BUFHCLK2": null, + "HCLK_CK_BUFHCLK3": null, + "HCLK_CK_BUFHCLK4": null, + "HCLK_CK_BUFHCLK5": null, + "HCLK_CK_BUFHCLK6": null, + "HCLK_CK_BUFHCLK7": null, + "HCLK_CK_BUFHCLK8": null, + "HCLK_CK_BUFHCLK9": null, + "HCLK_CK_BUFRCLK0": null, + "HCLK_CK_BUFRCLK1": null, + "HCLK_CK_BUFRCLK2": null, + "HCLK_CK_BUFRCLK3": null, + "HCLK_CK_IN0": null, + "HCLK_CK_IN1": null, + "HCLK_CK_IN10": null, + "HCLK_CK_IN11": null, + "HCLK_CK_IN12": null, + "HCLK_CK_IN13": null, + "HCLK_CK_IN2": null, + "HCLK_CK_IN3": null, + "HCLK_CK_IN4": null, + "HCLK_CK_IN5": null, + "HCLK_CK_IN6": null, + "HCLK_CK_IN7": null, + "HCLK_CK_IN8": null, + "HCLK_CK_IN9": null, + "HCLK_CK_INOUT_L0": null, + "HCLK_CK_INOUT_L1": null, + "HCLK_CK_INOUT_L2": null, + "HCLK_CK_INOUT_L3": null, + "HCLK_CK_INOUT_L4": null, + "HCLK_CK_INOUT_L5": null, + "HCLK_CK_INOUT_L6": null, + "HCLK_CK_INOUT_L7": null, + "HCLK_CK_OUTIN_L0": null, + "HCLK_CK_OUTIN_L1": null, + "HCLK_CK_OUTIN_L2": null, + "HCLK_CK_OUTIN_L3": null, + "HCLK_CK_OUTIN_L4": null, + "HCLK_CK_OUTIN_L5": null, + "HCLK_CK_OUTIN_L6": null, + "HCLK_CK_OUTIN_L7": null, + "HCLK_EL1BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_EL1END_S3_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_ER1BEG_S0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_ER1END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_FAN_BOUNCE_S3_0": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_2": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_4": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_6": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_INT_PERFCLK0": null, + "HCLK_INT_PERFCLK1": null, + "HCLK_INT_PERFCLK2": null, + "HCLK_INT_PERFCLK3": null, + "HCLK_LEAF_CLK_B_BOTL0": null, + "HCLK_LEAF_CLK_B_BOTL1": null, + "HCLK_LEAF_CLK_B_BOTL2": null, + "HCLK_LEAF_CLK_B_BOTL3": null, + "HCLK_LEAF_CLK_B_BOTL4": null, + "HCLK_LEAF_CLK_B_BOTL5": null, + "HCLK_LEAF_CLK_B_TOPL0": null, + "HCLK_LEAF_CLK_B_TOPL1": null, + "HCLK_LEAF_CLK_B_TOPL2": null, + "HCLK_LEAF_CLK_B_TOPL3": null, + "HCLK_LEAF_CLK_B_TOPL4": null, + "HCLK_LEAF_CLK_B_TOPL5": null, + "HCLK_LV0": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV1": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV10": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV11": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV12": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV13": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV14": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV15": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV16": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV17": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB10": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB11": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB12": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB6": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB7": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB8": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB9": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_NE2BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE2BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE2BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE2BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE2END_S3_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1END_S3_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2END_S2_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6END_S1_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2END_S0_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6END_S0_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_REFCK_EASTCLK0": null, + "HCLK_REFCK_EASTCLK1": null, + "HCLK_REFCK_WESTCLK0": null, + "HCLK_REFCK_WESTCLK1": null, + "HCLK_SE2A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE2A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE2A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SR1BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SR1END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SR1END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SR1END_N3_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2END_N0_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END_N0_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2END_N0_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WL1BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WL1END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WR1BEG_S0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WR1END_S1_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WW2END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WW4END_S0_0": { + "cap": "16.660", + "res": "154.960" + } + } } diff --git a/kintex7/tile_type_HCLK_L_BOT_UTURN.json b/kintex7/tile_type_HCLK_L_BOT_UTURN.json index e8f03d3..d5fb852 100644 --- a/kintex7/tile_type_HCLK_L_BOT_UTURN.json +++ b/kintex7/tile_type_HCLK_L_BOT_UTURN.json @@ -2,907 +2,3163 @@ "pips": { "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_CK_INOUT_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK10->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK10" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_CK_INOUT_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK11->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK11" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_CK_INOUT_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK8->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK8" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_CK_INOUT_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK9" }, "HCLK_L_BOT_UTURN.HCLK_CK_BUFHCLK9->>HCLK_LEAF_CLK_B_TOPL5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOPL5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": 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"HCLK_LEAF_CLK_B_TOPL0", - "HCLK_LEAF_CLK_B_TOPL1", - "HCLK_LEAF_CLK_B_TOPL2", - "HCLK_LEAF_CLK_B_TOPL3", - "HCLK_LEAF_CLK_B_TOPL4", - "HCLK_LEAF_CLK_B_TOPL5" - ] + "wires": { + "B_TERM_UTURN_INT_ER1BEG0": null, + "B_TERM_UTURN_INT_ER1END_N3_3": null, + "B_TERM_UTURN_INT_FAN_BOUNCE0": null, + "B_TERM_UTURN_INT_FAN_BOUNCE2": null, + "B_TERM_UTURN_INT_FAN_BOUNCE4": null, + "B_TERM_UTURN_INT_FAN_BOUNCE6": null, + "B_TERM_UTURN_INT_LV18": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L0": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L1": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB_L5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L18": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L6": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L7": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L8": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L9": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_SE2BEG0": null, + "B_TERM_UTURN_INT_SE2BEG1": null, + "B_TERM_UTURN_INT_SE2BEG2": null, + "B_TERM_UTURN_INT_SE2BEG3": null, + "B_TERM_UTURN_INT_SE6A0": null, + "B_TERM_UTURN_INT_SE6A1": null, + "B_TERM_UTURN_INT_SE6A2": null, + "B_TERM_UTURN_INT_SE6A3": null, + "B_TERM_UTURN_INT_SE6B0": null, + "B_TERM_UTURN_INT_SE6B1": null, + "B_TERM_UTURN_INT_SE6B2": null, + "B_TERM_UTURN_INT_SE6B3": null, + "B_TERM_UTURN_INT_SE6C0": null, + "B_TERM_UTURN_INT_SE6C1": null, + "B_TERM_UTURN_INT_SE6C2": null, + "B_TERM_UTURN_INT_SE6C3": null, + "B_TERM_UTURN_INT_SE6D0": null, + "B_TERM_UTURN_INT_SE6D1": null, + "B_TERM_UTURN_INT_SE6D2": null, + "B_TERM_UTURN_INT_SE6D3": null, + "B_TERM_UTURN_INT_SL1BEG0": null, + "B_TERM_UTURN_INT_SL1BEG1": null, + "B_TERM_UTURN_INT_SL1BEG2": null, + "B_TERM_UTURN_INT_SL1BEG3": null, + "B_TERM_UTURN_INT_SR1BEG1": null, + "B_TERM_UTURN_INT_SR1BEG2": null, + "B_TERM_UTURN_INT_SR1BEG3": null, + "B_TERM_UTURN_INT_SS2A0": null, + "B_TERM_UTURN_INT_SS2A1": null, + "B_TERM_UTURN_INT_SS2A2": null, + "B_TERM_UTURN_INT_SS2A3": null, + "B_TERM_UTURN_INT_SS2BEG0": null, + "B_TERM_UTURN_INT_SS2BEG1": null, + "B_TERM_UTURN_INT_SS2BEG2": null, + "B_TERM_UTURN_INT_SS2BEG3": null, + "B_TERM_UTURN_INT_SS6A0": null, + "B_TERM_UTURN_INT_SS6A1": null, + "B_TERM_UTURN_INT_SS6A2": null, + "B_TERM_UTURN_INT_SS6A3": null, + "B_TERM_UTURN_INT_SS6B0": null, + "B_TERM_UTURN_INT_SS6B1": null, + "B_TERM_UTURN_INT_SS6B2": null, + "B_TERM_UTURN_INT_SS6B3": null, + "B_TERM_UTURN_INT_SS6BEG0": null, + "B_TERM_UTURN_INT_SS6BEG1": null, + "B_TERM_UTURN_INT_SS6BEG2": null, + "B_TERM_UTURN_INT_SS6BEG3": null, + "B_TERM_UTURN_INT_SS6C0": null, + "B_TERM_UTURN_INT_SS6C1": null, + "B_TERM_UTURN_INT_SS6C2": null, + "B_TERM_UTURN_INT_SS6C3": null, + "B_TERM_UTURN_INT_SS6D0": null, + "B_TERM_UTURN_INT_SS6D1": null, + "B_TERM_UTURN_INT_SS6D2": null, + "B_TERM_UTURN_INT_SS6D3": null, + "B_TERM_UTURN_INT_SS6E0": null, + "B_TERM_UTURN_INT_SS6E1": null, + "B_TERM_UTURN_INT_SS6E2": null, + "B_TERM_UTURN_INT_SS6E3": null, + "B_TERM_UTURN_INT_SW2BEG0": null, + "B_TERM_UTURN_INT_SW2BEG1": null, + "B_TERM_UTURN_INT_SW2BEG2": null, + "B_TERM_UTURN_INT_SW2BEG3": null, + "B_TERM_UTURN_INT_SW6A0": null, + "B_TERM_UTURN_INT_SW6A1": null, + "B_TERM_UTURN_INT_SW6A2": null, + "B_TERM_UTURN_INT_SW6A3": null, + "B_TERM_UTURN_INT_SW6B0": null, + "B_TERM_UTURN_INT_SW6B1": null, + "B_TERM_UTURN_INT_SW6B2": null, + "B_TERM_UTURN_INT_SW6B3": null, + "B_TERM_UTURN_INT_SW6C0": null, + "B_TERM_UTURN_INT_SW6C1": null, + "B_TERM_UTURN_INT_SW6C2": null, + "B_TERM_UTURN_INT_SW6C3": null, + "B_TERM_UTURN_INT_SW6D0": null, + "B_TERM_UTURN_INT_SW6D1": null, + "B_TERM_UTURN_INT_SW6D2": null, + "B_TERM_UTURN_INT_SW6D3": null, + "B_TERM_UTURN_INT_SW6END_N0_3": null, + "B_TERM_UTURN_INT_WR1BEG0": null, + "B_TERM_UTURN_INT_WR1END0": null, + "HCLK_CCIO0": null, + "HCLK_CCIO1": null, + "HCLK_CCIO2": null, + "HCLK_CCIO3": null, + "HCLK_CK_BUFHCLK0": null, + "HCLK_CK_BUFHCLK1": null, + "HCLK_CK_BUFHCLK10": null, + "HCLK_CK_BUFHCLK11": null, + "HCLK_CK_BUFHCLK2": null, + "HCLK_CK_BUFHCLK3": null, + "HCLK_CK_BUFHCLK4": null, + "HCLK_CK_BUFHCLK5": null, + "HCLK_CK_BUFHCLK6": null, + "HCLK_CK_BUFHCLK7": null, + "HCLK_CK_BUFHCLK8": null, + "HCLK_CK_BUFHCLK9": null, + "HCLK_CK_BUFRCLK0": null, + "HCLK_CK_BUFRCLK1": null, + "HCLK_CK_BUFRCLK2": null, + "HCLK_CK_BUFRCLK3": null, + "HCLK_CK_IN0": null, + "HCLK_CK_IN1": null, + "HCLK_CK_IN10": null, + "HCLK_CK_IN11": null, + "HCLK_CK_IN12": null, + "HCLK_CK_IN13": null, + "HCLK_CK_IN2": null, + "HCLK_CK_IN3": null, + "HCLK_CK_IN4": null, + "HCLK_CK_IN5": null, + "HCLK_CK_IN6": null, + "HCLK_CK_IN7": null, + "HCLK_CK_IN8": null, + "HCLK_CK_IN9": null, + "HCLK_CK_INOUT_L0": null, + "HCLK_CK_INOUT_L1": null, + "HCLK_CK_INOUT_L2": null, + "HCLK_CK_INOUT_L3": null, + "HCLK_CK_INOUT_L4": null, + "HCLK_CK_INOUT_L5": null, + "HCLK_CK_INOUT_L6": null, + "HCLK_CK_INOUT_L7": null, + "HCLK_CK_OUTIN_L0": null, + "HCLK_CK_OUTIN_L1": null, + "HCLK_CK_OUTIN_L2": null, + "HCLK_CK_OUTIN_L3": null, + "HCLK_CK_OUTIN_L4": null, + "HCLK_CK_OUTIN_L5": null, + "HCLK_CK_OUTIN_L6": null, + "HCLK_CK_OUTIN_L7": null, + "HCLK_INT_PERFCLK0": null, + "HCLK_INT_PERFCLK1": null, + "HCLK_INT_PERFCLK2": null, + "HCLK_INT_PERFCLK3": null, + "HCLK_LEAF_CLK_B_TOPL0": null, + "HCLK_LEAF_CLK_B_TOPL1": null, + "HCLK_LEAF_CLK_B_TOPL2": null, + "HCLK_LEAF_CLK_B_TOPL3": null, + "HCLK_LEAF_CLK_B_TOPL4": null, + "HCLK_LEAF_CLK_B_TOPL5": null + } } diff --git a/kintex7/tile_type_HCLK_R.json b/kintex7/tile_type_HCLK_R.json index 7ef8574..1837837 100644 --- a/kintex7/tile_type_HCLK_R.json +++ b/kintex7/tile_type_HCLK_R.json @@ -2,1694 +2,6545 @@ "pips": { "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_CK_INOUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_CK_INOUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + 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"src_wire": "HCLK_CK_BUFHCLK3" }, "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK3" }, "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK3" }, "HCLK_R.HCLK_CK_BUFHCLK3->>HCLK_LEAF_CLK_B_BOT3": { "can_invert": "0", + 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"delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK4" }, "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK4" }, "HCLK_R.HCLK_CK_BUFHCLK4->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": 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"delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK5" }, "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK5" }, "HCLK_R.HCLK_CK_BUFHCLK5->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": 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"delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R6->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R6" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_BOT5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_BOT5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" }, "HCLK_R.HCLK_CK_OUTIN_R7->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_OUTIN_R7" } }, "sites": [], "tile_type": "HCLK_R", - "wires": [ - "HCLK_BYP_BOUNCE2", - "HCLK_BYP_BOUNCE3", - "HCLK_BYP_BOUNCE6", - "HCLK_BYP_BOUNCE7", - "HCLK_CCIO0", - "HCLK_CCIO1", - "HCLK_CCIO2", - "HCLK_CCIO3", - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK3", - "HCLK_CK_IN0", - "HCLK_CK_IN1", - "HCLK_CK_IN10", - "HCLK_CK_IN11", - "HCLK_CK_IN12", - "HCLK_CK_IN13", - "HCLK_CK_IN2", - "HCLK_CK_IN3", - "HCLK_CK_IN4", - "HCLK_CK_IN5", - "HCLK_CK_IN6", - "HCLK_CK_IN7", - "HCLK_CK_IN8", - "HCLK_CK_IN9", - "HCLK_CK_INOUT_R0", - "HCLK_CK_INOUT_R1", - "HCLK_CK_INOUT_R2", - "HCLK_CK_INOUT_R3", - "HCLK_CK_INOUT_R4", - "HCLK_CK_INOUT_R5", - "HCLK_CK_INOUT_R6", - "HCLK_CK_INOUT_R7", - "HCLK_CK_OUTIN_R0", - "HCLK_CK_OUTIN_R1", - "HCLK_CK_OUTIN_R2", - "HCLK_CK_OUTIN_R3", - "HCLK_CK_OUTIN_R4", - "HCLK_CK_OUTIN_R5", - "HCLK_CK_OUTIN_R6", - "HCLK_CK_OUTIN_R7", - "HCLK_EL1BEG3", - "HCLK_EL1END_S3_0", - "HCLK_ER1BEG_S0", - "HCLK_ER1END3", - "HCLK_FAN_BOUNCE_S3_0", - "HCLK_FAN_BOUNCE_S3_2", - "HCLK_FAN_BOUNCE_S3_4", - "HCLK_FAN_BOUNCE_S3_6", - "HCLK_INT_PERFCLK0", - "HCLK_INT_PERFCLK1", - "HCLK_INT_PERFCLK2", - "HCLK_INT_PERFCLK3", - "HCLK_LEAF_CLK_B_BOT0", - "HCLK_LEAF_CLK_B_BOT1", - "HCLK_LEAF_CLK_B_BOT2", - "HCLK_LEAF_CLK_B_BOT3", - "HCLK_LEAF_CLK_B_BOT4", - "HCLK_LEAF_CLK_B_BOT5", - "HCLK_LEAF_CLK_B_TOP0", - "HCLK_LEAF_CLK_B_TOP1", - "HCLK_LEAF_CLK_B_TOP2", - "HCLK_LEAF_CLK_B_TOP3", - "HCLK_LEAF_CLK_B_TOP4", - "HCLK_LEAF_CLK_B_TOP5", - "HCLK_LV0", - "HCLK_LV1", - "HCLK_LV10", - "HCLK_LV11", - "HCLK_LV12", - "HCLK_LV13", - "HCLK_LV14", - "HCLK_LV15", - "HCLK_LV16", - "HCLK_LV17", - "HCLK_LV2", - "HCLK_LV3", - "HCLK_LV4", - "HCLK_LV5", - "HCLK_LV6", - "HCLK_LV7", - "HCLK_LV8", - "HCLK_LV9", - "HCLK_LVB1", - "HCLK_LVB10", - "HCLK_LVB11", - "HCLK_LVB12", - "HCLK_LVB2", - "HCLK_LVB3", - "HCLK_LVB4", - "HCLK_LVB5", - "HCLK_LVB6", - "HCLK_LVB7", - "HCLK_LVB8", - "HCLK_LVB9", - "HCLK_NE2BEG0", - "HCLK_NE2BEG1", - "HCLK_NE2BEG2", - "HCLK_NE2BEG3", - "HCLK_NE2END_S3_0", - "HCLK_NE6A0", - "HCLK_NE6A1", - "HCLK_NE6A2", - "HCLK_NE6A3", - "HCLK_NE6B0", - "HCLK_NE6B1", - "HCLK_NE6B2", - "HCLK_NE6B3", - "HCLK_NE6C0", - "HCLK_NE6C1", - "HCLK_NE6C2", - "HCLK_NE6C3", - "HCLK_NE6D0", - "HCLK_NE6D1", - "HCLK_NE6D2", - "HCLK_NE6D3", - "HCLK_NL1BEG0", - "HCLK_NL1BEG1", - "HCLK_NL1BEG2", - "HCLK_NL1END_S3_0", - "HCLK_NN2A0", - "HCLK_NN2A1", - "HCLK_NN2A2", - "HCLK_NN2A3", - "HCLK_NN2BEG0", - "HCLK_NN2BEG1", - "HCLK_NN2BEG2", - "HCLK_NN2BEG3", - "HCLK_NN2END_S2_0", - "HCLK_NN6A0", - "HCLK_NN6A1", - "HCLK_NN6A2", - "HCLK_NN6A3", - "HCLK_NN6B0", - "HCLK_NN6B1", - "HCLK_NN6B2", - "HCLK_NN6B3", - "HCLK_NN6BEG0", - "HCLK_NN6BEG1", - "HCLK_NN6BEG2", - "HCLK_NN6BEG3", - "HCLK_NN6C0", - "HCLK_NN6C1", - "HCLK_NN6C2", - "HCLK_NN6C3", - "HCLK_NN6D0", - "HCLK_NN6D1", - "HCLK_NN6D2", - "HCLK_NN6D3", - "HCLK_NN6E0", - "HCLK_NN6E1", - "HCLK_NN6E2", - "HCLK_NN6E3", - "HCLK_NN6END_S1_0", - "HCLK_NR1BEG0", - "HCLK_NR1BEG1", - "HCLK_NR1BEG2", - "HCLK_NR1BEG3", - "HCLK_NW2A0", - "HCLK_NW2A1", - "HCLK_NW2A2", - "HCLK_NW2A3", - "HCLK_NW2END_S0_0", - "HCLK_NW6A0", - "HCLK_NW6A1", - "HCLK_NW6A2", - "HCLK_NW6A3", - "HCLK_NW6B0", - "HCLK_NW6B1", - "HCLK_NW6B2", - "HCLK_NW6B3", - "HCLK_NW6C0", - "HCLK_NW6C1", - "HCLK_NW6C2", - "HCLK_NW6C3", - "HCLK_NW6D0", - "HCLK_NW6D1", - "HCLK_NW6D2", - "HCLK_NW6D3", - "HCLK_NW6END_S0_0", - "HCLK_REFCK_EASTCLK0", - "HCLK_REFCK_EASTCLK1", - "HCLK_REFCK_WESTCLK0", - "HCLK_REFCK_WESTCLK1", - "HCLK_SE2A0", - "HCLK_SE2A1", - "HCLK_SE2A2", - "HCLK_SE2A3", - "HCLK_SE6B0", - "HCLK_SE6B1", - "HCLK_SE6B2", - "HCLK_SE6B3", - "HCLK_SE6C0", - "HCLK_SE6C1", - "HCLK_SE6C2", - "HCLK_SE6C3", - "HCLK_SE6D0", - "HCLK_SE6D1", - "HCLK_SE6D2", - "HCLK_SE6D3", - "HCLK_SE6E0", - "HCLK_SE6E1", - "HCLK_SE6E2", - "HCLK_SE6E3", - "HCLK_SL1END0", - "HCLK_SL1END1", - "HCLK_SL1END2", - "HCLK_SL1END3", - "HCLK_SR1BEG3", - "HCLK_SR1END1", - "HCLK_SR1END2", - "HCLK_SR1END_N3_3", - "HCLK_SS2A0", - "HCLK_SS2A1", - "HCLK_SS2A2", - "HCLK_SS2A3", - "HCLK_SS2BEG3", - "HCLK_SS2END0", - "HCLK_SS2END1", - "HCLK_SS2END2", - "HCLK_SS2END_N0_3", - "HCLK_SS6A0", - "HCLK_SS6A1", - "HCLK_SS6A2", - "HCLK_SS6A3", - "HCLK_SS6B0", - "HCLK_SS6B1", - "HCLK_SS6B2", - "HCLK_SS6B3", - "HCLK_SS6C0", - "HCLK_SS6C1", - "HCLK_SS6C2", - "HCLK_SS6C3", - "HCLK_SS6D0", - "HCLK_SS6D1", - "HCLK_SS6D2", - "HCLK_SS6D3", - "HCLK_SS6E0", - "HCLK_SS6E1", - "HCLK_SS6E2", - "HCLK_SS6E3", - "HCLK_SS6END0", - "HCLK_SS6END1", - "HCLK_SS6END2", - "HCLK_SS6END3", - "HCLK_SS6END_N0_3", - "HCLK_SW2A3", - "HCLK_SW2END0", - "HCLK_SW2END1", - "HCLK_SW2END2", - "HCLK_SW2END_N0_3", - "HCLK_SW6B0", - "HCLK_SW6B1", - "HCLK_SW6B2", - "HCLK_SW6B3", - "HCLK_SW6C0", - "HCLK_SW6C1", - "HCLK_SW6C2", - "HCLK_SW6C3", - "HCLK_SW6D0", - "HCLK_SW6D1", - "HCLK_SW6D2", - "HCLK_SW6D3", - "HCLK_SW6E0", - "HCLK_SW6E1", - "HCLK_SW6E2", - "HCLK_SW6E3", - "HCLK_SW6END3", - "HCLK_WL1BEG3", - "HCLK_WL1END3", - "HCLK_WR1BEG_S0", - "HCLK_WR1END_S1_0", - "HCLK_WW2END3", - "HCLK_WW4END_S0_0" - ] + "wires": { + "HCLK_BYP_BOUNCE2": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE3": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE6": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_BYP_BOUNCE7": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_CCIO0": null, + "HCLK_CCIO1": null, + "HCLK_CCIO2": null, + "HCLK_CCIO3": null, + "HCLK_CK_BUFHCLK0": null, + "HCLK_CK_BUFHCLK1": null, + "HCLK_CK_BUFHCLK10": null, + "HCLK_CK_BUFHCLK11": null, + "HCLK_CK_BUFHCLK2": null, + "HCLK_CK_BUFHCLK3": null, + "HCLK_CK_BUFHCLK4": null, + "HCLK_CK_BUFHCLK5": null, + "HCLK_CK_BUFHCLK6": null, + "HCLK_CK_BUFHCLK7": null, + "HCLK_CK_BUFHCLK8": null, + "HCLK_CK_BUFHCLK9": null, + "HCLK_CK_BUFRCLK0": null, + "HCLK_CK_BUFRCLK1": null, + "HCLK_CK_BUFRCLK2": null, + "HCLK_CK_BUFRCLK3": null, + "HCLK_CK_IN0": null, + "HCLK_CK_IN1": null, + "HCLK_CK_IN10": null, + "HCLK_CK_IN11": null, + "HCLK_CK_IN12": null, + "HCLK_CK_IN13": null, + "HCLK_CK_IN2": null, + "HCLK_CK_IN3": null, + "HCLK_CK_IN4": null, + "HCLK_CK_IN5": null, + "HCLK_CK_IN6": null, + "HCLK_CK_IN7": null, + "HCLK_CK_IN8": null, + "HCLK_CK_IN9": null, + "HCLK_CK_INOUT_R0": null, + "HCLK_CK_INOUT_R1": null, + "HCLK_CK_INOUT_R2": null, + "HCLK_CK_INOUT_R3": null, + "HCLK_CK_INOUT_R4": null, + "HCLK_CK_INOUT_R5": null, + "HCLK_CK_INOUT_R6": null, + "HCLK_CK_INOUT_R7": null, + "HCLK_CK_OUTIN_R0": null, + "HCLK_CK_OUTIN_R1": null, + "HCLK_CK_OUTIN_R2": null, + "HCLK_CK_OUTIN_R3": null, + "HCLK_CK_OUTIN_R4": null, + "HCLK_CK_OUTIN_R5": null, + "HCLK_CK_OUTIN_R6": null, + "HCLK_CK_OUTIN_R7": null, + "HCLK_EL1BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_EL1END_S3_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_ER1BEG_S0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_ER1END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_FAN_BOUNCE_S3_0": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_2": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_4": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_FAN_BOUNCE_S3_6": { + "cap": "29.530", + "res": "0.000" + }, + "HCLK_INT_PERFCLK0": null, + "HCLK_INT_PERFCLK1": null, + "HCLK_INT_PERFCLK2": null, + "HCLK_INT_PERFCLK3": null, + "HCLK_LEAF_CLK_B_BOT0": null, + "HCLK_LEAF_CLK_B_BOT1": null, + "HCLK_LEAF_CLK_B_BOT2": null, + "HCLK_LEAF_CLK_B_BOT3": null, + "HCLK_LEAF_CLK_B_BOT4": null, + "HCLK_LEAF_CLK_B_BOT5": null, + "HCLK_LEAF_CLK_B_TOP0": null, + "HCLK_LEAF_CLK_B_TOP1": null, + "HCLK_LEAF_CLK_B_TOP2": null, + "HCLK_LEAF_CLK_B_TOP3": null, + "HCLK_LEAF_CLK_B_TOP4": null, + "HCLK_LEAF_CLK_B_TOP5": null, + "HCLK_LV0": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV1": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV10": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV11": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV12": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV13": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV14": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV15": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV16": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV17": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB10": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB11": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB12": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB6": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB7": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB8": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_LVB9": { + "cap": "13.000", + "res": "2.800" + }, + "HCLK_NE2BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE2BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE2BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE2BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE2END_S3_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NE6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NL1END_S3_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN2END_S2_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NN6END_S1_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NR1BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW2END_S0_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_NW6END_S0_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_REFCK_EASTCLK0": null, + "HCLK_REFCK_EASTCLK1": null, + "HCLK_REFCK_WESTCLK0": null, + "HCLK_REFCK_WESTCLK1": null, + "HCLK_SE2A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE2A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE2A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SE6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SL1END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SR1BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SR1END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SR1END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SR1END_N3_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS2END_N0_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SS6END_N0_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2A3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2END0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2END1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2END2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW2END_N0_3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6B3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6C3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6D3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E1": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E2": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6E3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_SW6END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WL1BEG3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WL1END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WR1BEG_S0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WR1END_S1_0": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WW2END3": { + "cap": "16.660", + "res": "154.960" + }, + "HCLK_WW4END_S0_0": { + "cap": "16.660", + "res": "154.960" + } + } } diff --git a/kintex7/tile_type_HCLK_R_BOT_UTURN.json b/kintex7/tile_type_HCLK_R_BOT_UTURN.json index 398fc90..90cfc26 100644 --- a/kintex7/tile_type_HCLK_R_BOT_UTURN.json +++ b/kintex7/tile_type_HCLK_R_BOT_UTURN.json @@ -2,907 +2,3163 @@ "pips": { "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_CK_INOUT_R0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_R0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK0->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK0" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_CK_INOUT_R1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_R1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK1->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK1" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_CK_INOUT_R2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "HCLK_CK_INOUT_R2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "HCLK_CK_BUFHCLK2" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK2" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK2" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK2" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK2" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "src_wire": "HCLK_CK_BUFHCLK2" }, "HCLK_R_BOT_UTURN.HCLK_CK_BUFHCLK2->>HCLK_LEAF_CLK_B_TOP5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.082", + "0.084", + "0.153", + "0.155" + ], + "in_cap": null, + "res": null + }, "dst_wire": "HCLK_LEAF_CLK_B_TOP5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.082", + "0.084", + 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"B_TERM_UTURN_INT_SW6D3", - "B_TERM_UTURN_INT_SW6END_N0_3", - "B_TERM_UTURN_INT_WR1BEG0", - "B_TERM_UTURN_INT_WR1END0", - "HCLK_CCIO0", - "HCLK_CCIO1", - "HCLK_CCIO2", - "HCLK_CCIO3", - "HCLK_CK_BUFHCLK0", - "HCLK_CK_BUFHCLK1", - "HCLK_CK_BUFHCLK10", - "HCLK_CK_BUFHCLK11", - "HCLK_CK_BUFHCLK2", - "HCLK_CK_BUFHCLK3", - "HCLK_CK_BUFHCLK4", - "HCLK_CK_BUFHCLK5", - "HCLK_CK_BUFHCLK6", - "HCLK_CK_BUFHCLK7", - "HCLK_CK_BUFHCLK8", - "HCLK_CK_BUFHCLK9", - "HCLK_CK_BUFRCLK0", - "HCLK_CK_BUFRCLK1", - "HCLK_CK_BUFRCLK2", - "HCLK_CK_BUFRCLK3", - "HCLK_CK_IN0", - "HCLK_CK_IN1", - "HCLK_CK_IN10", - "HCLK_CK_IN11", - "HCLK_CK_IN12", - "HCLK_CK_IN13", - "HCLK_CK_IN2", - "HCLK_CK_IN3", - "HCLK_CK_IN4", - "HCLK_CK_IN5", - "HCLK_CK_IN6", - "HCLK_CK_IN7", - "HCLK_CK_IN8", - "HCLK_CK_IN9", - "HCLK_CK_INOUT_R0", - "HCLK_CK_INOUT_R1", - "HCLK_CK_INOUT_R2", - "HCLK_CK_INOUT_R3", - "HCLK_CK_INOUT_R4", - "HCLK_CK_INOUT_R5", - "HCLK_CK_INOUT_R6", - "HCLK_CK_INOUT_R7", - "HCLK_CK_OUTIN_R0", - "HCLK_CK_OUTIN_R1", - "HCLK_CK_OUTIN_R2", - "HCLK_CK_OUTIN_R3", - "HCLK_CK_OUTIN_R4", - "HCLK_CK_OUTIN_R5", - "HCLK_CK_OUTIN_R6", - "HCLK_CK_OUTIN_R7", - "HCLK_INT_PERFCLK0", - "HCLK_INT_PERFCLK1", - "HCLK_INT_PERFCLK2", - "HCLK_INT_PERFCLK3", - "HCLK_LEAF_CLK_B_TOP0", - "HCLK_LEAF_CLK_B_TOP1", - "HCLK_LEAF_CLK_B_TOP2", - "HCLK_LEAF_CLK_B_TOP3", - "HCLK_LEAF_CLK_B_TOP4", - "HCLK_LEAF_CLK_B_TOP5" - ] + "wires": { + "B_TERM_UTURN_INT_ER1BEG0": null, + "B_TERM_UTURN_INT_ER1END_N3_3": null, + "B_TERM_UTURN_INT_FAN_BOUNCE0": null, + "B_TERM_UTURN_INT_FAN_BOUNCE2": null, + "B_TERM_UTURN_INT_FAN_BOUNCE4": null, + "B_TERM_UTURN_INT_FAN_BOUNCE6": null, + "B_TERM_UTURN_INT_LV18": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV6": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV7": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV8": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV9": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB0": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB1": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LVB5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L18": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L2": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L3": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L4": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L5": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L6": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L7": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L8": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_LV_L9": { + "cap": "13.000", + "res": "2.800" + }, + "B_TERM_UTURN_INT_SE2BEG0": null, + "B_TERM_UTURN_INT_SE2BEG1": null, + "B_TERM_UTURN_INT_SE2BEG2": null, + "B_TERM_UTURN_INT_SE2BEG3": null, + "B_TERM_UTURN_INT_SE6A0": null, + "B_TERM_UTURN_INT_SE6A1": null, + "B_TERM_UTURN_INT_SE6A2": null, + "B_TERM_UTURN_INT_SE6A3": null, + "B_TERM_UTURN_INT_SE6B0": null, + "B_TERM_UTURN_INT_SE6B1": null, + "B_TERM_UTURN_INT_SE6B2": null, + "B_TERM_UTURN_INT_SE6B3": null, + "B_TERM_UTURN_INT_SE6C0": null, + "B_TERM_UTURN_INT_SE6C1": null, + "B_TERM_UTURN_INT_SE6C2": null, + "B_TERM_UTURN_INT_SE6C3": null, + "B_TERM_UTURN_INT_SE6D0": null, + "B_TERM_UTURN_INT_SE6D1": null, + "B_TERM_UTURN_INT_SE6D2": null, + "B_TERM_UTURN_INT_SE6D3": null, + "B_TERM_UTURN_INT_SL1BEG0": null, + "B_TERM_UTURN_INT_SL1BEG1": null, + "B_TERM_UTURN_INT_SL1BEG2": null, + "B_TERM_UTURN_INT_SL1BEG3": null, + "B_TERM_UTURN_INT_SR1BEG1": null, + "B_TERM_UTURN_INT_SR1BEG2": null, + "B_TERM_UTURN_INT_SR1BEG3": null, + "B_TERM_UTURN_INT_SS2A0": null, + "B_TERM_UTURN_INT_SS2A1": null, + "B_TERM_UTURN_INT_SS2A2": null, + "B_TERM_UTURN_INT_SS2A3": null, + "B_TERM_UTURN_INT_SS2BEG0": null, + "B_TERM_UTURN_INT_SS2BEG1": null, + "B_TERM_UTURN_INT_SS2BEG2": null, + "B_TERM_UTURN_INT_SS2BEG3": null, + "B_TERM_UTURN_INT_SS6A0": null, + "B_TERM_UTURN_INT_SS6A1": null, + "B_TERM_UTURN_INT_SS6A2": null, + "B_TERM_UTURN_INT_SS6A3": null, + "B_TERM_UTURN_INT_SS6B0": null, + "B_TERM_UTURN_INT_SS6B1": null, + "B_TERM_UTURN_INT_SS6B2": null, + "B_TERM_UTURN_INT_SS6B3": null, + "B_TERM_UTURN_INT_SS6BEG0": null, + "B_TERM_UTURN_INT_SS6BEG1": null, + "B_TERM_UTURN_INT_SS6BEG2": null, + "B_TERM_UTURN_INT_SS6BEG3": null, + "B_TERM_UTURN_INT_SS6C0": null, + "B_TERM_UTURN_INT_SS6C1": null, + "B_TERM_UTURN_INT_SS6C2": null, + "B_TERM_UTURN_INT_SS6C3": null, + "B_TERM_UTURN_INT_SS6D0": null, + "B_TERM_UTURN_INT_SS6D1": null, + "B_TERM_UTURN_INT_SS6D2": null, + "B_TERM_UTURN_INT_SS6D3": null, + "B_TERM_UTURN_INT_SS6E0": null, + "B_TERM_UTURN_INT_SS6E1": null, + "B_TERM_UTURN_INT_SS6E2": null, + "B_TERM_UTURN_INT_SS6E3": null, + "B_TERM_UTURN_INT_SW2BEG0": null, + "B_TERM_UTURN_INT_SW2BEG1": null, + "B_TERM_UTURN_INT_SW2BEG2": null, + "B_TERM_UTURN_INT_SW2BEG3": null, + "B_TERM_UTURN_INT_SW6A0": null, + "B_TERM_UTURN_INT_SW6A1": null, + "B_TERM_UTURN_INT_SW6A2": null, + "B_TERM_UTURN_INT_SW6A3": null, + "B_TERM_UTURN_INT_SW6B0": null, + "B_TERM_UTURN_INT_SW6B1": null, + "B_TERM_UTURN_INT_SW6B2": null, + "B_TERM_UTURN_INT_SW6B3": null, + "B_TERM_UTURN_INT_SW6C0": null, + "B_TERM_UTURN_INT_SW6C1": null, + "B_TERM_UTURN_INT_SW6C2": null, + "B_TERM_UTURN_INT_SW6C3": null, + "B_TERM_UTURN_INT_SW6D0": null, + "B_TERM_UTURN_INT_SW6D1": null, + "B_TERM_UTURN_INT_SW6D2": null, + "B_TERM_UTURN_INT_SW6D3": null, + "B_TERM_UTURN_INT_SW6END_N0_3": null, + "B_TERM_UTURN_INT_WR1BEG0": null, + "B_TERM_UTURN_INT_WR1END0": null, + "HCLK_CCIO0": null, + "HCLK_CCIO1": null, + "HCLK_CCIO2": null, + "HCLK_CCIO3": null, + "HCLK_CK_BUFHCLK0": null, + "HCLK_CK_BUFHCLK1": null, + "HCLK_CK_BUFHCLK10": null, + "HCLK_CK_BUFHCLK11": null, + "HCLK_CK_BUFHCLK2": null, + "HCLK_CK_BUFHCLK3": null, + "HCLK_CK_BUFHCLK4": null, + "HCLK_CK_BUFHCLK5": null, + "HCLK_CK_BUFHCLK6": null, + "HCLK_CK_BUFHCLK7": null, + "HCLK_CK_BUFHCLK8": null, + "HCLK_CK_BUFHCLK9": null, + "HCLK_CK_BUFRCLK0": null, + "HCLK_CK_BUFRCLK1": null, + "HCLK_CK_BUFRCLK2": null, + "HCLK_CK_BUFRCLK3": null, + "HCLK_CK_IN0": null, + "HCLK_CK_IN1": null, + "HCLK_CK_IN10": null, + "HCLK_CK_IN11": null, + "HCLK_CK_IN12": null, + "HCLK_CK_IN13": null, + "HCLK_CK_IN2": null, + "HCLK_CK_IN3": null, + "HCLK_CK_IN4": null, + "HCLK_CK_IN5": null, + "HCLK_CK_IN6": null, + "HCLK_CK_IN7": null, + "HCLK_CK_IN8": null, + "HCLK_CK_IN9": null, + "HCLK_CK_INOUT_R0": null, + "HCLK_CK_INOUT_R1": null, + "HCLK_CK_INOUT_R2": null, + "HCLK_CK_INOUT_R3": null, + "HCLK_CK_INOUT_R4": null, + "HCLK_CK_INOUT_R5": null, + "HCLK_CK_INOUT_R6": null, + "HCLK_CK_INOUT_R7": null, + "HCLK_CK_OUTIN_R0": null, + "HCLK_CK_OUTIN_R1": null, + "HCLK_CK_OUTIN_R2": null, + "HCLK_CK_OUTIN_R3": null, + "HCLK_CK_OUTIN_R4": null, + "HCLK_CK_OUTIN_R5": null, + "HCLK_CK_OUTIN_R6": null, + "HCLK_CK_OUTIN_R7": null, + "HCLK_INT_PERFCLK0": null, + "HCLK_INT_PERFCLK1": null, + "HCLK_INT_PERFCLK2": null, + "HCLK_INT_PERFCLK3": null, + "HCLK_LEAF_CLK_B_TOP0": null, + "HCLK_LEAF_CLK_B_TOP1": null, + "HCLK_LEAF_CLK_B_TOP2": null, + "HCLK_LEAF_CLK_B_TOP3": null, + "HCLK_LEAF_CLK_B_TOP4": null, + "HCLK_LEAF_CLK_B_TOP5": null + } } diff --git a/kintex7/tile_type_HCLK_TERM.json b/kintex7/tile_type_HCLK_TERM.json index 0138939..bb3a3bf 100644 --- a/kintex7/tile_type_HCLK_TERM.json +++ b/kintex7/tile_type_HCLK_TERM.json @@ -2,44 +2,44 @@ "pips": {}, "sites": [], "tile_type": "HCLK_TERM", - "wires": [ - "HCLK_TERM_CCIO0", - "HCLK_TERM_CCIO1", - "HCLK_TERM_CCIO2", - "HCLK_TERM_CCIO3", - "HCLK_TERM_CK_BUFHCLK0", - "HCLK_TERM_CK_BUFHCLK1", - "HCLK_TERM_CK_BUFHCLK10", - "HCLK_TERM_CK_BUFHCLK11", - "HCLK_TERM_CK_BUFHCLK2", - "HCLK_TERM_CK_BUFHCLK3", - "HCLK_TERM_CK_BUFHCLK4", - "HCLK_TERM_CK_BUFHCLK5", - "HCLK_TERM_CK_BUFHCLK6", - "HCLK_TERM_CK_BUFHCLK7", - "HCLK_TERM_CK_BUFHCLK8", - "HCLK_TERM_CK_BUFHCLK9", - "HCLK_TERM_CK_BUFRCLK0", - "HCLK_TERM_CK_BUFRCLK1", - "HCLK_TERM_CK_BUFRCLK2", - "HCLK_TERM_CK_BUFRCLK3", - "HCLK_TERM_CK_IN0", - "HCLK_TERM_CK_IN1", - "HCLK_TERM_CK_IN10", - "HCLK_TERM_CK_IN11", - "HCLK_TERM_CK_IN12", - "HCLK_TERM_CK_IN13", - "HCLK_TERM_CK_IN2", - "HCLK_TERM_CK_IN3", - "HCLK_TERM_CK_IN4", - "HCLK_TERM_CK_IN5", - "HCLK_TERM_CK_IN6", - "HCLK_TERM_CK_IN7", - "HCLK_TERM_CK_IN8", - "HCLK_TERM_CK_IN9", - "HCLK_TERM_PERFCLK0", - "HCLK_TERM_PERFCLK1", - "HCLK_TERM_PERFCLK2", - "HCLK_TERM_PERFCLK3" - ] + "wires": { + "HCLK_TERM_CCIO0": null, + "HCLK_TERM_CCIO1": null, + "HCLK_TERM_CCIO2": null, + "HCLK_TERM_CCIO3": null, + "HCLK_TERM_CK_BUFHCLK0": null, + "HCLK_TERM_CK_BUFHCLK1": null, + "HCLK_TERM_CK_BUFHCLK10": null, + "HCLK_TERM_CK_BUFHCLK11": null, + "HCLK_TERM_CK_BUFHCLK2": null, + "HCLK_TERM_CK_BUFHCLK3": null, + "HCLK_TERM_CK_BUFHCLK4": null, + "HCLK_TERM_CK_BUFHCLK5": null, + "HCLK_TERM_CK_BUFHCLK6": null, + "HCLK_TERM_CK_BUFHCLK7": null, + "HCLK_TERM_CK_BUFHCLK8": null, + "HCLK_TERM_CK_BUFHCLK9": null, + "HCLK_TERM_CK_BUFRCLK0": null, + "HCLK_TERM_CK_BUFRCLK1": null, + "HCLK_TERM_CK_BUFRCLK2": null, + "HCLK_TERM_CK_BUFRCLK3": null, + "HCLK_TERM_CK_IN0": null, + "HCLK_TERM_CK_IN1": null, + "HCLK_TERM_CK_IN10": null, + "HCLK_TERM_CK_IN11": null, + "HCLK_TERM_CK_IN12": null, + "HCLK_TERM_CK_IN13": null, + "HCLK_TERM_CK_IN2": null, + "HCLK_TERM_CK_IN3": null, + "HCLK_TERM_CK_IN4": null, + "HCLK_TERM_CK_IN5": null, + "HCLK_TERM_CK_IN6": null, + "HCLK_TERM_CK_IN7": null, + "HCLK_TERM_CK_IN8": null, + "HCLK_TERM_CK_IN9": null, + "HCLK_TERM_PERFCLK0": null, + "HCLK_TERM_PERFCLK1": null, + "HCLK_TERM_PERFCLK2": null, + "HCLK_TERM_PERFCLK3": null + } } diff --git a/kintex7/tile_type_HCLK_TERM_GTX.json b/kintex7/tile_type_HCLK_TERM_GTX.json index ec192db..cdb842e 100644 --- a/kintex7/tile_type_HCLK_TERM_GTX.json +++ b/kintex7/tile_type_HCLK_TERM_GTX.json @@ -2,20 +2,20 @@ "pips": {}, "sites": [], "tile_type": "HCLK_TERM_GTX", - "wires": [ - "HCLK_TERM_GTX_CK_IN0", - "HCLK_TERM_GTX_CK_IN1", - "HCLK_TERM_GTX_CK_IN10", - "HCLK_TERM_GTX_CK_IN11", - "HCLK_TERM_GTX_CK_IN12", - "HCLK_TERM_GTX_CK_IN13", - "HCLK_TERM_GTX_CK_IN2", - "HCLK_TERM_GTX_CK_IN3", - "HCLK_TERM_GTX_CK_IN4", - "HCLK_TERM_GTX_CK_IN5", - "HCLK_TERM_GTX_CK_IN6", - "HCLK_TERM_GTX_CK_IN7", - "HCLK_TERM_GTX_CK_IN8", - "HCLK_TERM_GTX_CK_IN9" - ] + "wires": { + "HCLK_TERM_GTX_CK_IN0": null, + "HCLK_TERM_GTX_CK_IN1": null, + "HCLK_TERM_GTX_CK_IN10": null, + "HCLK_TERM_GTX_CK_IN11": null, + "HCLK_TERM_GTX_CK_IN12": null, + "HCLK_TERM_GTX_CK_IN13": null, + "HCLK_TERM_GTX_CK_IN2": null, + "HCLK_TERM_GTX_CK_IN3": null, + "HCLK_TERM_GTX_CK_IN4": null, + "HCLK_TERM_GTX_CK_IN5": null, + "HCLK_TERM_GTX_CK_IN6": null, + "HCLK_TERM_GTX_CK_IN7": null, + "HCLK_TERM_GTX_CK_IN8": null, + "HCLK_TERM_GTX_CK_IN9": null + } } diff --git a/kintex7/tile_type_HCLK_VBRK.json b/kintex7/tile_type_HCLK_VBRK.json index 2525d57..628c7e8 100644 --- a/kintex7/tile_type_HCLK_VBRK.json +++ b/kintex7/tile_type_HCLK_VBRK.json @@ -2,44 +2,44 @@ "pips": {}, "sites": [], "tile_type": "HCLK_VBRK", - "wires": [ - "HCLK_VBRK_CK_BUFHCLK0", - "HCLK_VBRK_CK_BUFHCLK1", - "HCLK_VBRK_CK_BUFHCLK10", - "HCLK_VBRK_CK_BUFHCLK11", - "HCLK_VBRK_CK_BUFHCLK2", - "HCLK_VBRK_CK_BUFHCLK3", - "HCLK_VBRK_CK_BUFHCLK4", - "HCLK_VBRK_CK_BUFHCLK5", - "HCLK_VBRK_CK_BUFHCLK6", - "HCLK_VBRK_CK_BUFHCLK7", - "HCLK_VBRK_CK_BUFHCLK8", - "HCLK_VBRK_CK_BUFHCLK9", - "HCLK_VBRK_CK_BUFRCLK0", - "HCLK_VBRK_CK_BUFRCLK1", - "HCLK_VBRK_CK_BUFRCLK2", - "HCLK_VBRK_CK_BUFRCLK3", - "HCLK_VBRK_MUX_CLK0", - "HCLK_VBRK_MUX_CLK1", - "HCLK_VBRK_MUX_CLK10", - "HCLK_VBRK_MUX_CLK11", - "HCLK_VBRK_MUX_CLK12", - "HCLK_VBRK_MUX_CLK13", - "HCLK_VBRK_MUX_CLK2", - "HCLK_VBRK_MUX_CLK3", - "HCLK_VBRK_MUX_CLK4", - "HCLK_VBRK_MUX_CLK5", - "HCLK_VBRK_MUX_CLK6", - "HCLK_VBRK_MUX_CLK7", - "HCLK_VBRK_MUX_CLK8", - "HCLK_VBRK_MUX_CLK9", - "HCLK_VBRK_PHSR_PERFCLK0", - "HCLK_VBRK_PHSR_PERFCLK1", - "HCLK_VBRK_PHSR_PERFCLK2", - "HCLK_VBRK_PHSR_PERFCLK3", - "HCLK_VBRK_REFCK_EASTCLK0", - "HCLK_VBRK_REFCK_EASTCLK1", - "HCLK_VBRK_REFCK_WESTCLK0", - "HCLK_VBRK_REFCK_WESTCLK1" - ] + "wires": { + "HCLK_VBRK_CK_BUFHCLK0": null, + "HCLK_VBRK_CK_BUFHCLK1": null, + "HCLK_VBRK_CK_BUFHCLK10": null, + "HCLK_VBRK_CK_BUFHCLK11": null, + "HCLK_VBRK_CK_BUFHCLK2": null, + "HCLK_VBRK_CK_BUFHCLK3": null, + "HCLK_VBRK_CK_BUFHCLK4": null, + "HCLK_VBRK_CK_BUFHCLK5": null, + "HCLK_VBRK_CK_BUFHCLK6": null, + "HCLK_VBRK_CK_BUFHCLK7": null, + "HCLK_VBRK_CK_BUFHCLK8": null, + "HCLK_VBRK_CK_BUFHCLK9": null, + "HCLK_VBRK_CK_BUFRCLK0": null, + "HCLK_VBRK_CK_BUFRCLK1": null, + "HCLK_VBRK_CK_BUFRCLK2": null, + "HCLK_VBRK_CK_BUFRCLK3": null, + "HCLK_VBRK_MUX_CLK0": null, + "HCLK_VBRK_MUX_CLK1": null, + "HCLK_VBRK_MUX_CLK10": null, + "HCLK_VBRK_MUX_CLK11": null, + "HCLK_VBRK_MUX_CLK12": null, + "HCLK_VBRK_MUX_CLK13": null, + "HCLK_VBRK_MUX_CLK2": null, + "HCLK_VBRK_MUX_CLK3": null, + "HCLK_VBRK_MUX_CLK4": null, + "HCLK_VBRK_MUX_CLK5": null, + "HCLK_VBRK_MUX_CLK6": null, + "HCLK_VBRK_MUX_CLK7": null, + "HCLK_VBRK_MUX_CLK8": null, + "HCLK_VBRK_MUX_CLK9": null, + "HCLK_VBRK_PHSR_PERFCLK0": null, + "HCLK_VBRK_PHSR_PERFCLK1": null, + "HCLK_VBRK_PHSR_PERFCLK2": null, + "HCLK_VBRK_PHSR_PERFCLK3": null, + "HCLK_VBRK_REFCK_EASTCLK0": null, + "HCLK_VBRK_REFCK_EASTCLK1": null, + "HCLK_VBRK_REFCK_WESTCLK0": null, + "HCLK_VBRK_REFCK_WESTCLK1": null + } } diff --git a/kintex7/tile_type_HCLK_VFRAME.json b/kintex7/tile_type_HCLK_VFRAME.json index ca01e96..5f5152a 100644 --- a/kintex7/tile_type_HCLK_VFRAME.json +++ b/kintex7/tile_type_HCLK_VFRAME.json @@ -2,36 +2,36 @@ "pips": {}, "sites": [], "tile_type": "HCLK_VFRAME", - "wires": [ - "HCLK_VFRAME_CK_BUFHCLK0", - "HCLK_VFRAME_CK_BUFHCLK1", - "HCLK_VFRAME_CK_BUFHCLK10", - "HCLK_VFRAME_CK_BUFHCLK11", - "HCLK_VFRAME_CK_BUFHCLK2", - "HCLK_VFRAME_CK_BUFHCLK3", - "HCLK_VFRAME_CK_BUFHCLK4", - "HCLK_VFRAME_CK_BUFHCLK5", - "HCLK_VFRAME_CK_BUFHCLK6", - "HCLK_VFRAME_CK_BUFHCLK7", - "HCLK_VFRAME_CK_BUFHCLK8", - "HCLK_VFRAME_CK_BUFHCLK9", - "HCLK_VFRAME_CK_BUFRCLK0", - "HCLK_VFRAME_CK_BUFRCLK1", - "HCLK_VFRAME_CK_BUFRCLK2", - "HCLK_VFRAME_CK_BUFRCLK3", - "HCLK_VFRAME_CK_IN0", - "HCLK_VFRAME_CK_IN1", - "HCLK_VFRAME_CK_IN10", - "HCLK_VFRAME_CK_IN11", - "HCLK_VFRAME_CK_IN12", - "HCLK_VFRAME_CK_IN13", - "HCLK_VFRAME_CK_IN2", - "HCLK_VFRAME_CK_IN3", - "HCLK_VFRAME_CK_IN4", - "HCLK_VFRAME_CK_IN5", - "HCLK_VFRAME_CK_IN6", - "HCLK_VFRAME_CK_IN7", - "HCLK_VFRAME_CK_IN8", - "HCLK_VFRAME_CK_IN9" - ] + "wires": { + "HCLK_VFRAME_CK_BUFHCLK0": null, + "HCLK_VFRAME_CK_BUFHCLK1": null, + "HCLK_VFRAME_CK_BUFHCLK10": null, + "HCLK_VFRAME_CK_BUFHCLK11": null, + "HCLK_VFRAME_CK_BUFHCLK2": null, + "HCLK_VFRAME_CK_BUFHCLK3": null, + "HCLK_VFRAME_CK_BUFHCLK4": null, + "HCLK_VFRAME_CK_BUFHCLK5": null, + "HCLK_VFRAME_CK_BUFHCLK6": null, + "HCLK_VFRAME_CK_BUFHCLK7": null, + "HCLK_VFRAME_CK_BUFHCLK8": null, + "HCLK_VFRAME_CK_BUFHCLK9": null, + "HCLK_VFRAME_CK_BUFRCLK0": null, + "HCLK_VFRAME_CK_BUFRCLK1": null, + "HCLK_VFRAME_CK_BUFRCLK2": null, + "HCLK_VFRAME_CK_BUFRCLK3": null, + "HCLK_VFRAME_CK_IN0": null, + "HCLK_VFRAME_CK_IN1": null, + "HCLK_VFRAME_CK_IN10": null, + "HCLK_VFRAME_CK_IN11": null, + "HCLK_VFRAME_CK_IN12": null, + "HCLK_VFRAME_CK_IN13": null, + "HCLK_VFRAME_CK_IN2": null, + "HCLK_VFRAME_CK_IN3": null, + "HCLK_VFRAME_CK_IN4": null, + "HCLK_VFRAME_CK_IN5": null, + "HCLK_VFRAME_CK_IN6": null, + "HCLK_VFRAME_CK_IN7": null, + "HCLK_VFRAME_CK_IN8": null, + "HCLK_VFRAME_CK_IN9": null + } } diff --git a/kintex7/tile_type_INT_FEEDTHRU_1.json b/kintex7/tile_type_INT_FEEDTHRU_1.json index eecff34..8504c78 100644 --- a/kintex7/tile_type_INT_FEEDTHRU_1.json +++ b/kintex7/tile_type_INT_FEEDTHRU_1.json @@ -2,132 +2,132 @@ "pips": {}, "sites": [], "tile_type": "INT_FEEDTHRU_1", - "wires": [ - "INT_FEEDTHRU_1_EE2A0", - "INT_FEEDTHRU_1_EE2A1", - "INT_FEEDTHRU_1_EE2A2", - "INT_FEEDTHRU_1_EE2A3", - "INT_FEEDTHRU_1_EE2BEG0", - "INT_FEEDTHRU_1_EE2BEG1", - "INT_FEEDTHRU_1_EE2BEG2", - "INT_FEEDTHRU_1_EE2BEG3", - "INT_FEEDTHRU_1_EE4A0", - "INT_FEEDTHRU_1_EE4A1", - "INT_FEEDTHRU_1_EE4A2", - "INT_FEEDTHRU_1_EE4A3", - "INT_FEEDTHRU_1_EE4B0", - "INT_FEEDTHRU_1_EE4B1", - "INT_FEEDTHRU_1_EE4B2", - "INT_FEEDTHRU_1_EE4B3", - "INT_FEEDTHRU_1_EE4BEG0", - "INT_FEEDTHRU_1_EE4BEG1", - "INT_FEEDTHRU_1_EE4BEG2", - "INT_FEEDTHRU_1_EE4BEG3", - "INT_FEEDTHRU_1_EE4C0", - "INT_FEEDTHRU_1_EE4C1", - "INT_FEEDTHRU_1_EE4C2", - "INT_FEEDTHRU_1_EE4C3", - "INT_FEEDTHRU_1_EL1BEG0", - "INT_FEEDTHRU_1_EL1BEG1", - "INT_FEEDTHRU_1_EL1BEG2", - "INT_FEEDTHRU_1_EL1BEG3", - "INT_FEEDTHRU_1_ER1BEG0", - "INT_FEEDTHRU_1_ER1BEG1", - "INT_FEEDTHRU_1_ER1BEG2", - "INT_FEEDTHRU_1_ER1BEG3", - "INT_FEEDTHRU_1_LH1", - "INT_FEEDTHRU_1_LH10", - "INT_FEEDTHRU_1_LH11", - "INT_FEEDTHRU_1_LH12", - "INT_FEEDTHRU_1_LH2", - "INT_FEEDTHRU_1_LH3", - "INT_FEEDTHRU_1_LH4", - "INT_FEEDTHRU_1_LH5", - "INT_FEEDTHRU_1_LH6", - "INT_FEEDTHRU_1_LH7", - "INT_FEEDTHRU_1_LH8", - "INT_FEEDTHRU_1_LH9", - "INT_FEEDTHRU_1_MONITOR_N", - "INT_FEEDTHRU_1_MONITOR_P", - "INT_FEEDTHRU_1_NE2A0", - "INT_FEEDTHRU_1_NE2A1", - "INT_FEEDTHRU_1_NE2A2", - "INT_FEEDTHRU_1_NE2A3", - "INT_FEEDTHRU_1_NE4BEG0", - "INT_FEEDTHRU_1_NE4BEG1", - "INT_FEEDTHRU_1_NE4BEG2", - "INT_FEEDTHRU_1_NE4BEG3", - "INT_FEEDTHRU_1_NE4C0", - "INT_FEEDTHRU_1_NE4C1", - "INT_FEEDTHRU_1_NE4C2", - "INT_FEEDTHRU_1_NE4C3", - "INT_FEEDTHRU_1_NW2A0", - "INT_FEEDTHRU_1_NW2A1", - "INT_FEEDTHRU_1_NW2A2", - "INT_FEEDTHRU_1_NW2A3", - "INT_FEEDTHRU_1_NW4A0", - "INT_FEEDTHRU_1_NW4A1", - "INT_FEEDTHRU_1_NW4A2", - "INT_FEEDTHRU_1_NW4A3", - "INT_FEEDTHRU_1_NW4END0", - "INT_FEEDTHRU_1_NW4END1", - "INT_FEEDTHRU_1_NW4END2", - "INT_FEEDTHRU_1_NW4END3", - "INT_FEEDTHRU_1_SE2A0", - "INT_FEEDTHRU_1_SE2A1", - "INT_FEEDTHRU_1_SE2A2", - "INT_FEEDTHRU_1_SE2A3", - "INT_FEEDTHRU_1_SE4BEG0", - "INT_FEEDTHRU_1_SE4BEG1", - "INT_FEEDTHRU_1_SE4BEG2", - "INT_FEEDTHRU_1_SE4BEG3", - "INT_FEEDTHRU_1_SE4C0", - "INT_FEEDTHRU_1_SE4C1", - "INT_FEEDTHRU_1_SE4C2", - "INT_FEEDTHRU_1_SE4C3", - "INT_FEEDTHRU_1_SW2A0", - "INT_FEEDTHRU_1_SW2A1", - "INT_FEEDTHRU_1_SW2A2", - "INT_FEEDTHRU_1_SW2A3", - "INT_FEEDTHRU_1_SW4A0", - "INT_FEEDTHRU_1_SW4A1", - "INT_FEEDTHRU_1_SW4A2", - "INT_FEEDTHRU_1_SW4A3", - "INT_FEEDTHRU_1_SW4END0", - "INT_FEEDTHRU_1_SW4END1", - "INT_FEEDTHRU_1_SW4END2", - "INT_FEEDTHRU_1_SW4END3", - "INT_FEEDTHRU_1_WL1END0", - "INT_FEEDTHRU_1_WL1END1", - "INT_FEEDTHRU_1_WL1END2", - "INT_FEEDTHRU_1_WL1END3", - "INT_FEEDTHRU_1_WR1END0", - "INT_FEEDTHRU_1_WR1END1", - "INT_FEEDTHRU_1_WR1END2", - "INT_FEEDTHRU_1_WR1END3", - "INT_FEEDTHRU_1_WW2A0", - "INT_FEEDTHRU_1_WW2A1", - "INT_FEEDTHRU_1_WW2A2", - "INT_FEEDTHRU_1_WW2A3", - "INT_FEEDTHRU_1_WW2END0", - "INT_FEEDTHRU_1_WW2END1", - "INT_FEEDTHRU_1_WW2END2", - "INT_FEEDTHRU_1_WW2END3", - "INT_FEEDTHRU_1_WW4A0", - "INT_FEEDTHRU_1_WW4A1", - "INT_FEEDTHRU_1_WW4A2", - "INT_FEEDTHRU_1_WW4A3", - "INT_FEEDTHRU_1_WW4B0", - "INT_FEEDTHRU_1_WW4B1", - "INT_FEEDTHRU_1_WW4B2", - "INT_FEEDTHRU_1_WW4B3", - "INT_FEEDTHRU_1_WW4C0", - "INT_FEEDTHRU_1_WW4C1", - "INT_FEEDTHRU_1_WW4C2", - "INT_FEEDTHRU_1_WW4C3", - "INT_FEEDTHRU_1_WW4END0", - "INT_FEEDTHRU_1_WW4END1", - "INT_FEEDTHRU_1_WW4END2", - "INT_FEEDTHRU_1_WW4END3" - ] + "wires": { + "INT_FEEDTHRU_1_EE2A0": null, + "INT_FEEDTHRU_1_EE2A1": null, + "INT_FEEDTHRU_1_EE2A2": null, + "INT_FEEDTHRU_1_EE2A3": null, + "INT_FEEDTHRU_1_EE2BEG0": null, + "INT_FEEDTHRU_1_EE2BEG1": null, + "INT_FEEDTHRU_1_EE2BEG2": null, + "INT_FEEDTHRU_1_EE2BEG3": null, + "INT_FEEDTHRU_1_EE4A0": null, + "INT_FEEDTHRU_1_EE4A1": null, + "INT_FEEDTHRU_1_EE4A2": null, + "INT_FEEDTHRU_1_EE4A3": null, + "INT_FEEDTHRU_1_EE4B0": null, + "INT_FEEDTHRU_1_EE4B1": null, + "INT_FEEDTHRU_1_EE4B2": null, + "INT_FEEDTHRU_1_EE4B3": null, + "INT_FEEDTHRU_1_EE4BEG0": null, + "INT_FEEDTHRU_1_EE4BEG1": null, + "INT_FEEDTHRU_1_EE4BEG2": null, + "INT_FEEDTHRU_1_EE4BEG3": null, + "INT_FEEDTHRU_1_EE4C0": null, + "INT_FEEDTHRU_1_EE4C1": null, + "INT_FEEDTHRU_1_EE4C2": null, + "INT_FEEDTHRU_1_EE4C3": null, + "INT_FEEDTHRU_1_EL1BEG0": null, + "INT_FEEDTHRU_1_EL1BEG1": null, + "INT_FEEDTHRU_1_EL1BEG2": null, + "INT_FEEDTHRU_1_EL1BEG3": null, + "INT_FEEDTHRU_1_ER1BEG0": null, + "INT_FEEDTHRU_1_ER1BEG1": null, + "INT_FEEDTHRU_1_ER1BEG2": null, + "INT_FEEDTHRU_1_ER1BEG3": null, + "INT_FEEDTHRU_1_LH1": null, + "INT_FEEDTHRU_1_LH10": null, + "INT_FEEDTHRU_1_LH11": null, + "INT_FEEDTHRU_1_LH12": null, + "INT_FEEDTHRU_1_LH2": null, + "INT_FEEDTHRU_1_LH3": null, + "INT_FEEDTHRU_1_LH4": null, + "INT_FEEDTHRU_1_LH5": null, + "INT_FEEDTHRU_1_LH6": null, + "INT_FEEDTHRU_1_LH7": null, + "INT_FEEDTHRU_1_LH8": null, + "INT_FEEDTHRU_1_LH9": null, + "INT_FEEDTHRU_1_MONITOR_N": null, + "INT_FEEDTHRU_1_MONITOR_P": null, + "INT_FEEDTHRU_1_NE2A0": null, + "INT_FEEDTHRU_1_NE2A1": null, + "INT_FEEDTHRU_1_NE2A2": null, + "INT_FEEDTHRU_1_NE2A3": null, + "INT_FEEDTHRU_1_NE4BEG0": null, + "INT_FEEDTHRU_1_NE4BEG1": null, + "INT_FEEDTHRU_1_NE4BEG2": null, + "INT_FEEDTHRU_1_NE4BEG3": null, + "INT_FEEDTHRU_1_NE4C0": null, + "INT_FEEDTHRU_1_NE4C1": null, + "INT_FEEDTHRU_1_NE4C2": null, + "INT_FEEDTHRU_1_NE4C3": null, + "INT_FEEDTHRU_1_NW2A0": null, + "INT_FEEDTHRU_1_NW2A1": null, + "INT_FEEDTHRU_1_NW2A2": null, + "INT_FEEDTHRU_1_NW2A3": null, + "INT_FEEDTHRU_1_NW4A0": null, + "INT_FEEDTHRU_1_NW4A1": null, + "INT_FEEDTHRU_1_NW4A2": null, + "INT_FEEDTHRU_1_NW4A3": null, + "INT_FEEDTHRU_1_NW4END0": null, + "INT_FEEDTHRU_1_NW4END1": null, + "INT_FEEDTHRU_1_NW4END2": null, + "INT_FEEDTHRU_1_NW4END3": null, + "INT_FEEDTHRU_1_SE2A0": null, + "INT_FEEDTHRU_1_SE2A1": null, + "INT_FEEDTHRU_1_SE2A2": null, + "INT_FEEDTHRU_1_SE2A3": null, + "INT_FEEDTHRU_1_SE4BEG0": null, + "INT_FEEDTHRU_1_SE4BEG1": null, + "INT_FEEDTHRU_1_SE4BEG2": null, + "INT_FEEDTHRU_1_SE4BEG3": null, + "INT_FEEDTHRU_1_SE4C0": null, + "INT_FEEDTHRU_1_SE4C1": null, + "INT_FEEDTHRU_1_SE4C2": null, + "INT_FEEDTHRU_1_SE4C3": null, + "INT_FEEDTHRU_1_SW2A0": null, + "INT_FEEDTHRU_1_SW2A1": null, + "INT_FEEDTHRU_1_SW2A2": null, + "INT_FEEDTHRU_1_SW2A3": null, + "INT_FEEDTHRU_1_SW4A0": null, + "INT_FEEDTHRU_1_SW4A1": null, + "INT_FEEDTHRU_1_SW4A2": null, + "INT_FEEDTHRU_1_SW4A3": null, + "INT_FEEDTHRU_1_SW4END0": null, + "INT_FEEDTHRU_1_SW4END1": null, + "INT_FEEDTHRU_1_SW4END2": null, + "INT_FEEDTHRU_1_SW4END3": null, + "INT_FEEDTHRU_1_WL1END0": null, + "INT_FEEDTHRU_1_WL1END1": null, + "INT_FEEDTHRU_1_WL1END2": null, + "INT_FEEDTHRU_1_WL1END3": null, + "INT_FEEDTHRU_1_WR1END0": null, + "INT_FEEDTHRU_1_WR1END1": null, + "INT_FEEDTHRU_1_WR1END2": null, + "INT_FEEDTHRU_1_WR1END3": null, + "INT_FEEDTHRU_1_WW2A0": null, + "INT_FEEDTHRU_1_WW2A1": null, + "INT_FEEDTHRU_1_WW2A2": null, + "INT_FEEDTHRU_1_WW2A3": null, + "INT_FEEDTHRU_1_WW2END0": null, + "INT_FEEDTHRU_1_WW2END1": null, + "INT_FEEDTHRU_1_WW2END2": null, + "INT_FEEDTHRU_1_WW2END3": null, + "INT_FEEDTHRU_1_WW4A0": null, + "INT_FEEDTHRU_1_WW4A1": null, + "INT_FEEDTHRU_1_WW4A2": null, + "INT_FEEDTHRU_1_WW4A3": null, + "INT_FEEDTHRU_1_WW4B0": null, + "INT_FEEDTHRU_1_WW4B1": null, + "INT_FEEDTHRU_1_WW4B2": null, + "INT_FEEDTHRU_1_WW4B3": null, + "INT_FEEDTHRU_1_WW4C0": null, + "INT_FEEDTHRU_1_WW4C1": null, + "INT_FEEDTHRU_1_WW4C2": null, + "INT_FEEDTHRU_1_WW4C3": null, + "INT_FEEDTHRU_1_WW4END0": null, + "INT_FEEDTHRU_1_WW4END1": null, + "INT_FEEDTHRU_1_WW4END2": null, + "INT_FEEDTHRU_1_WW4END3": null + } } diff --git a/kintex7/tile_type_INT_FEEDTHRU_2.json b/kintex7/tile_type_INT_FEEDTHRU_2.json index ea9fb16..5820f86 100644 --- a/kintex7/tile_type_INT_FEEDTHRU_2.json +++ b/kintex7/tile_type_INT_FEEDTHRU_2.json @@ -2,132 +2,132 @@ "pips": {}, "sites": [], "tile_type": "INT_FEEDTHRU_2", - "wires": [ - "INT_FEEDTHRU_2_EE2A0", - "INT_FEEDTHRU_2_EE2A1", - "INT_FEEDTHRU_2_EE2A2", - "INT_FEEDTHRU_2_EE2A3", - "INT_FEEDTHRU_2_EE2BEG0", - "INT_FEEDTHRU_2_EE2BEG1", - "INT_FEEDTHRU_2_EE2BEG2", - "INT_FEEDTHRU_2_EE2BEG3", - "INT_FEEDTHRU_2_EE4A0", - "INT_FEEDTHRU_2_EE4A1", - "INT_FEEDTHRU_2_EE4A2", - "INT_FEEDTHRU_2_EE4A3", - "INT_FEEDTHRU_2_EE4B0", - "INT_FEEDTHRU_2_EE4B1", - "INT_FEEDTHRU_2_EE4B2", - "INT_FEEDTHRU_2_EE4B3", - "INT_FEEDTHRU_2_EE4BEG0", - "INT_FEEDTHRU_2_EE4BEG1", - "INT_FEEDTHRU_2_EE4BEG2", - "INT_FEEDTHRU_2_EE4BEG3", - "INT_FEEDTHRU_2_EE4C0", - "INT_FEEDTHRU_2_EE4C1", - "INT_FEEDTHRU_2_EE4C2", - "INT_FEEDTHRU_2_EE4C3", - "INT_FEEDTHRU_2_EL1BEG0", - "INT_FEEDTHRU_2_EL1BEG1", - "INT_FEEDTHRU_2_EL1BEG2", - "INT_FEEDTHRU_2_EL1BEG3", - "INT_FEEDTHRU_2_ER1BEG0", - "INT_FEEDTHRU_2_ER1BEG1", - "INT_FEEDTHRU_2_ER1BEG2", - "INT_FEEDTHRU_2_ER1BEG3", - "INT_FEEDTHRU_2_LH1", - "INT_FEEDTHRU_2_LH10", - "INT_FEEDTHRU_2_LH11", - "INT_FEEDTHRU_2_LH12", - "INT_FEEDTHRU_2_LH2", - "INT_FEEDTHRU_2_LH3", - "INT_FEEDTHRU_2_LH4", - "INT_FEEDTHRU_2_LH5", - "INT_FEEDTHRU_2_LH6", - "INT_FEEDTHRU_2_LH7", - "INT_FEEDTHRU_2_LH8", - "INT_FEEDTHRU_2_LH9", - "INT_FEEDTHRU_2_MONITOR_N", - "INT_FEEDTHRU_2_MONITOR_P", - "INT_FEEDTHRU_2_NE2A0", - "INT_FEEDTHRU_2_NE2A1", - "INT_FEEDTHRU_2_NE2A2", - "INT_FEEDTHRU_2_NE2A3", - "INT_FEEDTHRU_2_NE4BEG0", - "INT_FEEDTHRU_2_NE4BEG1", - "INT_FEEDTHRU_2_NE4BEG2", - "INT_FEEDTHRU_2_NE4BEG3", - "INT_FEEDTHRU_2_NE4C0", - "INT_FEEDTHRU_2_NE4C1", - "INT_FEEDTHRU_2_NE4C2", - "INT_FEEDTHRU_2_NE4C3", - "INT_FEEDTHRU_2_NW2A0", - "INT_FEEDTHRU_2_NW2A1", - "INT_FEEDTHRU_2_NW2A2", - "INT_FEEDTHRU_2_NW2A3", - "INT_FEEDTHRU_2_NW4A0", - "INT_FEEDTHRU_2_NW4A1", - "INT_FEEDTHRU_2_NW4A2", - "INT_FEEDTHRU_2_NW4A3", - "INT_FEEDTHRU_2_NW4END0", - "INT_FEEDTHRU_2_NW4END1", - "INT_FEEDTHRU_2_NW4END2", - "INT_FEEDTHRU_2_NW4END3", - "INT_FEEDTHRU_2_SE2A0", - "INT_FEEDTHRU_2_SE2A1", - "INT_FEEDTHRU_2_SE2A2", - "INT_FEEDTHRU_2_SE2A3", - "INT_FEEDTHRU_2_SE4BEG0", - "INT_FEEDTHRU_2_SE4BEG1", - "INT_FEEDTHRU_2_SE4BEG2", - "INT_FEEDTHRU_2_SE4BEG3", - "INT_FEEDTHRU_2_SE4C0", - "INT_FEEDTHRU_2_SE4C1", - "INT_FEEDTHRU_2_SE4C2", - "INT_FEEDTHRU_2_SE4C3", - "INT_FEEDTHRU_2_SW2A0", - "INT_FEEDTHRU_2_SW2A1", - "INT_FEEDTHRU_2_SW2A2", - "INT_FEEDTHRU_2_SW2A3", - "INT_FEEDTHRU_2_SW4A0", - "INT_FEEDTHRU_2_SW4A1", - "INT_FEEDTHRU_2_SW4A2", - "INT_FEEDTHRU_2_SW4A3", - "INT_FEEDTHRU_2_SW4END0", - "INT_FEEDTHRU_2_SW4END1", - "INT_FEEDTHRU_2_SW4END2", - "INT_FEEDTHRU_2_SW4END3", - "INT_FEEDTHRU_2_WL1END0", - "INT_FEEDTHRU_2_WL1END1", - "INT_FEEDTHRU_2_WL1END2", - "INT_FEEDTHRU_2_WL1END3", - "INT_FEEDTHRU_2_WR1END0", - "INT_FEEDTHRU_2_WR1END1", - "INT_FEEDTHRU_2_WR1END2", - "INT_FEEDTHRU_2_WR1END3", - "INT_FEEDTHRU_2_WW2A0", - "INT_FEEDTHRU_2_WW2A1", - "INT_FEEDTHRU_2_WW2A2", - "INT_FEEDTHRU_2_WW2A3", - "INT_FEEDTHRU_2_WW2END0", - "INT_FEEDTHRU_2_WW2END1", - "INT_FEEDTHRU_2_WW2END2", - "INT_FEEDTHRU_2_WW2END3", - "INT_FEEDTHRU_2_WW4A0", - "INT_FEEDTHRU_2_WW4A1", - "INT_FEEDTHRU_2_WW4A2", - "INT_FEEDTHRU_2_WW4A3", - "INT_FEEDTHRU_2_WW4B0", - "INT_FEEDTHRU_2_WW4B1", - "INT_FEEDTHRU_2_WW4B2", - "INT_FEEDTHRU_2_WW4B3", - "INT_FEEDTHRU_2_WW4C0", - "INT_FEEDTHRU_2_WW4C1", - "INT_FEEDTHRU_2_WW4C2", - "INT_FEEDTHRU_2_WW4C3", - "INT_FEEDTHRU_2_WW4END0", - "INT_FEEDTHRU_2_WW4END1", - "INT_FEEDTHRU_2_WW4END2", - "INT_FEEDTHRU_2_WW4END3" - ] + "wires": { + "INT_FEEDTHRU_2_EE2A0": null, + "INT_FEEDTHRU_2_EE2A1": null, + "INT_FEEDTHRU_2_EE2A2": null, + "INT_FEEDTHRU_2_EE2A3": null, + "INT_FEEDTHRU_2_EE2BEG0": null, + "INT_FEEDTHRU_2_EE2BEG1": null, + "INT_FEEDTHRU_2_EE2BEG2": null, + "INT_FEEDTHRU_2_EE2BEG3": null, + "INT_FEEDTHRU_2_EE4A0": null, + "INT_FEEDTHRU_2_EE4A1": null, + "INT_FEEDTHRU_2_EE4A2": null, + "INT_FEEDTHRU_2_EE4A3": null, + "INT_FEEDTHRU_2_EE4B0": null, + "INT_FEEDTHRU_2_EE4B1": null, + "INT_FEEDTHRU_2_EE4B2": null, + "INT_FEEDTHRU_2_EE4B3": null, + "INT_FEEDTHRU_2_EE4BEG0": null, + "INT_FEEDTHRU_2_EE4BEG1": null, + "INT_FEEDTHRU_2_EE4BEG2": null, + "INT_FEEDTHRU_2_EE4BEG3": null, + "INT_FEEDTHRU_2_EE4C0": null, + "INT_FEEDTHRU_2_EE4C1": null, + "INT_FEEDTHRU_2_EE4C2": null, + "INT_FEEDTHRU_2_EE4C3": null, + "INT_FEEDTHRU_2_EL1BEG0": null, + "INT_FEEDTHRU_2_EL1BEG1": null, + "INT_FEEDTHRU_2_EL1BEG2": null, + "INT_FEEDTHRU_2_EL1BEG3": null, + "INT_FEEDTHRU_2_ER1BEG0": null, + "INT_FEEDTHRU_2_ER1BEG1": null, + "INT_FEEDTHRU_2_ER1BEG2": null, + "INT_FEEDTHRU_2_ER1BEG3": null, + "INT_FEEDTHRU_2_LH1": null, + "INT_FEEDTHRU_2_LH10": null, + "INT_FEEDTHRU_2_LH11": null, + "INT_FEEDTHRU_2_LH12": null, + "INT_FEEDTHRU_2_LH2": null, + "INT_FEEDTHRU_2_LH3": null, + "INT_FEEDTHRU_2_LH4": null, + "INT_FEEDTHRU_2_LH5": null, + "INT_FEEDTHRU_2_LH6": null, + "INT_FEEDTHRU_2_LH7": null, + "INT_FEEDTHRU_2_LH8": null, + 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"INT_FEEDTHRU_2_WW2A1": null, + "INT_FEEDTHRU_2_WW2A2": null, + "INT_FEEDTHRU_2_WW2A3": null, + "INT_FEEDTHRU_2_WW2END0": null, + "INT_FEEDTHRU_2_WW2END1": null, + "INT_FEEDTHRU_2_WW2END2": null, + "INT_FEEDTHRU_2_WW2END3": null, + "INT_FEEDTHRU_2_WW4A0": null, + "INT_FEEDTHRU_2_WW4A1": null, + "INT_FEEDTHRU_2_WW4A2": null, + "INT_FEEDTHRU_2_WW4A3": null, + "INT_FEEDTHRU_2_WW4B0": null, + "INT_FEEDTHRU_2_WW4B1": null, + "INT_FEEDTHRU_2_WW4B2": null, + "INT_FEEDTHRU_2_WW4B3": null, + "INT_FEEDTHRU_2_WW4C0": null, + "INT_FEEDTHRU_2_WW4C1": null, + "INT_FEEDTHRU_2_WW4C2": null, + "INT_FEEDTHRU_2_WW4C3": null, + "INT_FEEDTHRU_2_WW4END0": null, + "INT_FEEDTHRU_2_WW4END1": null, + "INT_FEEDTHRU_2_WW4END2": null, + "INT_FEEDTHRU_2_WW4END3": null + } } diff --git a/kintex7/tile_type_INT_INTERFACE_L.json b/kintex7/tile_type_INT_INTERFACE_L.json index f401da4..81679d7 100644 --- a/kintex7/tile_type_INT_INTERFACE_L.json +++ b/kintex7/tile_type_INT_INTERFACE_L.json @@ -2,427 +2,931 @@ "pips": { "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B0->>INT_INTERFACE_LOGIC_OUTS_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B0" }, "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B1->>INT_INTERFACE_LOGIC_OUTS_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B1" }, "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B10->>INT_INTERFACE_LOGIC_OUTS_L10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B10" }, "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B11->>INT_INTERFACE_LOGIC_OUTS_L11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B11" }, "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B12->>INT_INTERFACE_LOGIC_OUTS_L12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_L_B12" }, "INT_INTERFACE_L.INT_INTERFACE_LOGIC_OUTS_L_B13->>INT_INTERFACE_LOGIC_OUTS_L13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS_L13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + 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"INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW4END3", - "L_INT_INTER_DQS_IOTOPHASER" - ] + "wires": { + "INT_INTERFACE_BLOCK_OUTS_L_B0": null, + "INT_INTERFACE_BLOCK_OUTS_L_B1": null, + "INT_INTERFACE_BLOCK_OUTS_L_B2": null, + "INT_INTERFACE_BLOCK_OUTS_L_B3": null, + "INT_INTERFACE_BYP0": null, + "INT_INTERFACE_BYP1": null, + "INT_INTERFACE_BYP2": null, + "INT_INTERFACE_BYP3": null, + "INT_INTERFACE_BYP4": null, + "INT_INTERFACE_BYP5": null, + "INT_INTERFACE_BYP6": null, + "INT_INTERFACE_BYP7": null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_IMUX0": null, + "INT_INTERFACE_IMUX1": null, + "INT_INTERFACE_IMUX10": null, + "INT_INTERFACE_IMUX11": null, + "INT_INTERFACE_IMUX12": null, + "INT_INTERFACE_IMUX13": null, + "INT_INTERFACE_IMUX14": null, + "INT_INTERFACE_IMUX15": null, + "INT_INTERFACE_IMUX16": null, + "INT_INTERFACE_IMUX17": null, + "INT_INTERFACE_IMUX18": null, + "INT_INTERFACE_IMUX19": null, + "INT_INTERFACE_IMUX2": null, + "INT_INTERFACE_IMUX20": null, + "INT_INTERFACE_IMUX21": null, + "INT_INTERFACE_IMUX22": null, + "INT_INTERFACE_IMUX23": null, + "INT_INTERFACE_IMUX24": null, + "INT_INTERFACE_IMUX25": null, + "INT_INTERFACE_IMUX26": null, + "INT_INTERFACE_IMUX27": null, + "INT_INTERFACE_IMUX28": null, + "INT_INTERFACE_IMUX29": null, + "INT_INTERFACE_IMUX3": null, + "INT_INTERFACE_IMUX30": null, + "INT_INTERFACE_IMUX31": null, + "INT_INTERFACE_IMUX32": null, + "INT_INTERFACE_IMUX33": null, + "INT_INTERFACE_IMUX34": null, + "INT_INTERFACE_IMUX35": null, + "INT_INTERFACE_IMUX36": null, + "INT_INTERFACE_IMUX37": null, + "INT_INTERFACE_IMUX38": null, + "INT_INTERFACE_IMUX39": null, + "INT_INTERFACE_IMUX4": null, + "INT_INTERFACE_IMUX40": null, + "INT_INTERFACE_IMUX41": null, + "INT_INTERFACE_IMUX42": null, + "INT_INTERFACE_IMUX43": null, + "INT_INTERFACE_IMUX44": null, + "INT_INTERFACE_IMUX45": null, + "INT_INTERFACE_IMUX46": null, + "INT_INTERFACE_IMUX47": null, + "INT_INTERFACE_IMUX5": null, + "INT_INTERFACE_IMUX6": null, + "INT_INTERFACE_IMUX7": null, + "INT_INTERFACE_IMUX8": null, + "INT_INTERFACE_IMUX9": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS_L0": null, + "INT_INTERFACE_LOGIC_OUTS_L1": null, + "INT_INTERFACE_LOGIC_OUTS_L10": null, + "INT_INTERFACE_LOGIC_OUTS_L11": null, + "INT_INTERFACE_LOGIC_OUTS_L12": null, + "INT_INTERFACE_LOGIC_OUTS_L13": null, + "INT_INTERFACE_LOGIC_OUTS_L14": null, + "INT_INTERFACE_LOGIC_OUTS_L15": null, + "INT_INTERFACE_LOGIC_OUTS_L16": null, + "INT_INTERFACE_LOGIC_OUTS_L17": null, + "INT_INTERFACE_LOGIC_OUTS_L18": null, + "INT_INTERFACE_LOGIC_OUTS_L19": null, + "INT_INTERFACE_LOGIC_OUTS_L2": null, + "INT_INTERFACE_LOGIC_OUTS_L20": null, + "INT_INTERFACE_LOGIC_OUTS_L21": null, + "INT_INTERFACE_LOGIC_OUTS_L22": null, + "INT_INTERFACE_LOGIC_OUTS_L23": null, + "INT_INTERFACE_LOGIC_OUTS_L3": null, + "INT_INTERFACE_LOGIC_OUTS_L4": null, + "INT_INTERFACE_LOGIC_OUTS_L5": null, + "INT_INTERFACE_LOGIC_OUTS_L6": null, + "INT_INTERFACE_LOGIC_OUTS_L7": null, + "INT_INTERFACE_LOGIC_OUTS_L8": null, + "INT_INTERFACE_LOGIC_OUTS_L9": null, + "INT_INTERFACE_LOGIC_OUTS_L_B0": null, + "INT_INTERFACE_LOGIC_OUTS_L_B1": null, + "INT_INTERFACE_LOGIC_OUTS_L_B10": null, + "INT_INTERFACE_LOGIC_OUTS_L_B11": null, + "INT_INTERFACE_LOGIC_OUTS_L_B12": null, + "INT_INTERFACE_LOGIC_OUTS_L_B13": null, + "INT_INTERFACE_LOGIC_OUTS_L_B14": null, + "INT_INTERFACE_LOGIC_OUTS_L_B15": null, + "INT_INTERFACE_LOGIC_OUTS_L_B16": null, + "INT_INTERFACE_LOGIC_OUTS_L_B17": null, + "INT_INTERFACE_LOGIC_OUTS_L_B18": null, + "INT_INTERFACE_LOGIC_OUTS_L_B19": null, + "INT_INTERFACE_LOGIC_OUTS_L_B2": null, + "INT_INTERFACE_LOGIC_OUTS_L_B20": null, + "INT_INTERFACE_LOGIC_OUTS_L_B21": null, + "INT_INTERFACE_LOGIC_OUTS_L_B22": null, + "INT_INTERFACE_LOGIC_OUTS_L_B23": null, + "INT_INTERFACE_LOGIC_OUTS_L_B3": null, + "INT_INTERFACE_LOGIC_OUTS_L_B4": null, + "INT_INTERFACE_LOGIC_OUTS_L_B5": null, + "INT_INTERFACE_LOGIC_OUTS_L_B6": null, + "INT_INTERFACE_LOGIC_OUTS_L_B7": null, + "INT_INTERFACE_LOGIC_OUTS_L_B8": null, + "INT_INTERFACE_LOGIC_OUTS_L_B9": null, + "INT_INTERFACE_MONITOR_N": null, + "INT_INTERFACE_MONITOR_P": null, + "INT_INTERFACE_NE2A0": null, + "INT_INTERFACE_NE2A1": null, + "INT_INTERFACE_NE2A2": null, + "INT_INTERFACE_NE2A3": null, + "INT_INTERFACE_NE4BEG0": null, + "INT_INTERFACE_NE4BEG1": null, + "INT_INTERFACE_NE4BEG2": null, + "INT_INTERFACE_NE4BEG3": null, + "INT_INTERFACE_NE4C0": null, + "INT_INTERFACE_NE4C1": null, + "INT_INTERFACE_NE4C2": null, + "INT_INTERFACE_NE4C3": null, + "INT_INTERFACE_NW2A0": null, + "INT_INTERFACE_NW2A1": null, + "INT_INTERFACE_NW2A2": null, + "INT_INTERFACE_NW2A3": null, + "INT_INTERFACE_NW4A0": null, + "INT_INTERFACE_NW4A1": null, + "INT_INTERFACE_NW4A2": null, + "INT_INTERFACE_NW4A3": null, + "INT_INTERFACE_NW4END0": null, + "INT_INTERFACE_NW4END1": null, + "INT_INTERFACE_NW4END2": null, + "INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_PHASER_TO_IO_ICLK": null, + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90": null, + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + "INT_INTERFACE_SW4END3": null, + "INT_INTERFACE_WL1END0": null, + "INT_INTERFACE_WL1END1": null, + "INT_INTERFACE_WL1END2": null, + "INT_INTERFACE_WL1END3": null, + "INT_INTERFACE_WR1END0": null, + "INT_INTERFACE_WR1END1": null, + "INT_INTERFACE_WR1END2": null, + "INT_INTERFACE_WR1END3": null, + "INT_INTERFACE_WW2A0": null, + "INT_INTERFACE_WW2A1": null, + "INT_INTERFACE_WW2A2": null, + "INT_INTERFACE_WW2A3": null, + "INT_INTERFACE_WW2END0": null, + "INT_INTERFACE_WW2END1": null, + "INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/kintex7/tile_type_INT_INTERFACE_R.json b/kintex7/tile_type_INT_INTERFACE_R.json index 0ff8f31..35ea5ce 100644 --- a/kintex7/tile_type_INT_INTERFACE_R.json +++ b/kintex7/tile_type_INT_INTERFACE_R.json @@ -2,427 +2,931 @@ "pips": { "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0" }, "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B1" }, "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B10->>INT_INTERFACE_LOGIC_OUTS10": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS10", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B10" }, "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B11->>INT_INTERFACE_LOGIC_OUTS11": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS11", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B11" }, "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B12->>INT_INTERFACE_LOGIC_OUTS12": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS12", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B12" }, "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B13->>INT_INTERFACE_LOGIC_OUTS13": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS13", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B13" }, "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B14->>INT_INTERFACE_LOGIC_OUTS14": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS14", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B14" }, "INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B15->>INT_INTERFACE_LOGIC_OUTS15": { "can_invert": "0", + "dst_to_src": { + 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"INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_PHASER_TO_IO_ICLK": null, + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90": null, + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + 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"INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/kintex7/tile_type_INT_L.json b/kintex7/tile_type_INT_L.json index 0323024..9d9a40a 100644 --- a/kintex7/tile_type_INT_L.json +++ b/kintex7/tile_type_INT_L.json @@ -2,26161 +2,104638 @@ "pips": { "INT_L.BYP_ALT0->>BYP_BOUNCE0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "dst_wire": "BYP_BOUNCE0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "src_wire": "BYP_ALT0" }, "INT_L.BYP_ALT0->>BYP_L0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "dst_wire": "BYP_L0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "src_wire": "BYP_ALT0" }, "INT_L.BYP_ALT1->>BYP_BOUNCE1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "dst_wire": "BYP_BOUNCE1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "src_wire": "BYP_ALT1" }, "INT_L.BYP_ALT1->>BYP_L1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "dst_wire": "BYP_L1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "src_wire": "BYP_ALT1" }, "INT_L.BYP_ALT2->>BYP_BOUNCE2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "dst_wire": "BYP_BOUNCE2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "src_wire": "BYP_ALT2" }, "INT_L.BYP_ALT2->>BYP_L2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "dst_wire": "BYP_L2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "src_wire": "BYP_ALT2" }, "INT_L.BYP_ALT3->>BYP_BOUNCE3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "dst_wire": "BYP_BOUNCE3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "src_wire": "BYP_ALT3" }, "INT_L.BYP_ALT3->>BYP_L3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "dst_wire": "BYP_L3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "src_wire": "BYP_ALT3" }, "INT_L.BYP_ALT4->>BYP_BOUNCE4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "dst_wire": "BYP_BOUNCE4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "src_wire": "BYP_ALT4" }, "INT_L.BYP_ALT4->>BYP_L4": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "dst_wire": "BYP_L4", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.083", + "0.101" + ], + "in_cap": "0.000", + "res": "1874.8963749999998" + }, "src_wire": "BYP_ALT4" }, "INT_L.BYP_ALT5->>BYP_BOUNCE5": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.044", + "0.054", + "0.083", + "0.102" + ], + "in_cap": "0.000", + "res": "830.8705625" + }, "dst_wire": "BYP_BOUNCE5", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.044", + "0.054", + "0.083", + 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"X0Y0", "prefix": "TIEOFF", "site_pins": { - "HARD0": "GND_WIRE", - "HARD1": "VCC_WIRE" + "HARD0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GND_WIRE" + }, + "HARD1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "VCC_WIRE" + } }, "type": "TIEOFF", "x_coord": 0, @@ -26174,606 +104669,702 @@ } ], "tile_type": "INT_L", - "wires": [ - "BYP_ALT0", - "BYP_ALT1", - "BYP_ALT2", - "BYP_ALT3", - "BYP_ALT4", - "BYP_ALT5", - "BYP_ALT6", - "BYP_ALT7", - "BYP_BOUNCE0", - "BYP_BOUNCE1", - "BYP_BOUNCE2", - "BYP_BOUNCE3", - "BYP_BOUNCE4", - "BYP_BOUNCE5", - "BYP_BOUNCE6", - "BYP_BOUNCE7", - "BYP_BOUNCE_N3_2", - "BYP_BOUNCE_N3_3", - "BYP_BOUNCE_N3_6", - "BYP_BOUNCE_N3_7", - "BYP_L0", - "BYP_L1", - "BYP_L2", - "BYP_L3", - "BYP_L4", - "BYP_L5", - "BYP_L6", - "BYP_L7", - "CLK_L0", - "CLK_L1", - "CTRL_L0", - "CTRL_L1", - "EE2A0", - "EE2A1", - "EE2A2", - "EE2A3", - "EE2BEG0", - "EE2BEG1", - "EE2BEG2", - "EE2BEG3", - "EE2END0", - "EE2END1", - "EE2END2", - "EE2END3", - "EE4A0", - "EE4A1", - "EE4A2", - "EE4A3", - "EE4B0", - "EE4B1", - "EE4B2", - "EE4B3", - "EE4BEG0", - "EE4BEG1", - "EE4BEG2", - "EE4BEG3", - "EE4C0", - "EE4C1", - "EE4C2", - "EE4C3", - "EE4END0", - "EE4END1", - "EE4END2", - "EE4END3", - "EL1BEG0", - "EL1BEG1", - "EL1BEG2", - "EL1BEG3", - "EL1BEG_N3", - "EL1END0", - "EL1END1", - "EL1END2", - "EL1END3", - "EL1END_S3_0", - "ER1BEG0", - "ER1BEG1", - "ER1BEG2", - "ER1BEG3", - "ER1BEG_S0", - "ER1END0", - "ER1END1", - "ER1END2", - "ER1END3", - "ER1END_N3_3", - "FAN_ALT0", - "FAN_ALT1", - "FAN_ALT2", - "FAN_ALT3", - "FAN_ALT4", - "FAN_ALT5", - "FAN_ALT6", - "FAN_ALT7", - "FAN_BOUNCE0", - "FAN_BOUNCE1", - "FAN_BOUNCE2", - "FAN_BOUNCE3", - "FAN_BOUNCE4", - "FAN_BOUNCE5", - "FAN_BOUNCE6", - "FAN_BOUNCE7", - "FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_6", - "FAN_L0", - "FAN_L1", - "FAN_L2", - "FAN_L3", - "FAN_L4", - "FAN_L5", - "FAN_L6", - "FAN_L7", - "GCLK_L_B0", - "GCLK_L_B1", - "GCLK_L_B10", - "GCLK_L_B10_EAST", - "GCLK_L_B10_WEST", - "GCLK_L_B11", - "GCLK_L_B11_EAST", - "GCLK_L_B11_WEST", - "GCLK_L_B2", - "GCLK_L_B3", - "GCLK_L_B4", - "GCLK_L_B5", - "GCLK_L_B6", - "GCLK_L_B6_EAST", - "GCLK_L_B6_WEST", - "GCLK_L_B7", - "GCLK_L_B7_EAST", - "GCLK_L_B7_WEST", - "GCLK_L_B8", - "GCLK_L_B8_EAST", - "GCLK_L_B8_WEST", - "GCLK_L_B9", - "GCLK_L_B9_EAST", - "GCLK_L_B9_WEST", - "GFAN0", - "GFAN1", - "GND_WIRE", - "IMUX_L0", - "IMUX_L1", - "IMUX_L10", - "IMUX_L11", - "IMUX_L12", - "IMUX_L13", - "IMUX_L14", - "IMUX_L15", - "IMUX_L16", - "IMUX_L17", - "IMUX_L18", - "IMUX_L19", - "IMUX_L2", - "IMUX_L20", - "IMUX_L21", - "IMUX_L22", - "IMUX_L23", - "IMUX_L24", - "IMUX_L25", - "IMUX_L26", - "IMUX_L27", - "IMUX_L28", - "IMUX_L29", - "IMUX_L3", - "IMUX_L30", - "IMUX_L31", - "IMUX_L32", - "IMUX_L33", - "IMUX_L34", - "IMUX_L35", - "IMUX_L36", - "IMUX_L37", - "IMUX_L38", - "IMUX_L39", - "IMUX_L4", - "IMUX_L40", - "IMUX_L41", - "IMUX_L42", - "IMUX_L43", - "IMUX_L44", - "IMUX_L45", - "IMUX_L46", - "IMUX_L47", - "IMUX_L5", - "IMUX_L6", - "IMUX_L7", - "IMUX_L8", - "IMUX_L9", - "INT_DQS_IOTOPHASER", - "INT_PHASER_TO_IO_ICLK", - "INT_PHASER_TO_IO_ICLKDIV", - "INT_PHASER_TO_IO_OCLK", - "INT_PHASER_TO_IO_OCLK1X_90", - "INT_PHASER_TO_IO_OCLKDIV", - "LH0", - "LH1", - "LH10", - "LH11", - "LH12", - "LH2", - "LH3", - "LH4", - "LH5", - "LH6", - "LH7", - "LH8", - "LH9", - "LOGIC_OUTS_L0", - "LOGIC_OUTS_L1", - "LOGIC_OUTS_L10", - "LOGIC_OUTS_L11", - "LOGIC_OUTS_L12", - "LOGIC_OUTS_L13", - "LOGIC_OUTS_L14", - "LOGIC_OUTS_L15", - "LOGIC_OUTS_L16", - "LOGIC_OUTS_L17", - "LOGIC_OUTS_L18", - "LOGIC_OUTS_L19", - "LOGIC_OUTS_L2", - "LOGIC_OUTS_L20", - "LOGIC_OUTS_L21", - "LOGIC_OUTS_L22", - "LOGIC_OUTS_L23", - "LOGIC_OUTS_L3", - "LOGIC_OUTS_L4", - "LOGIC_OUTS_L5", - "LOGIC_OUTS_L6", - "LOGIC_OUTS_L7", - "LOGIC_OUTS_L8", - "LOGIC_OUTS_L9", - "LVB_L0", - "LVB_L1", - "LVB_L10", - "LVB_L11", - "LVB_L12", - "LVB_L2", - "LVB_L3", - "LVB_L4", - "LVB_L5", - "LVB_L6", - "LVB_L7", - "LVB_L8", - "LVB_L9", - "LV_L0", - "LV_L1", - "LV_L10", - "LV_L11", - "LV_L12", - "LV_L13", - "LV_L14", - "LV_L15", - "LV_L16", - "LV_L17", - "LV_L18", - "LV_L2", - "LV_L3", - "LV_L4", - "LV_L5", - "LV_L6", - "LV_L7", - "LV_L8", - "LV_L9", - "MONITOR_N", - "MONITOR_P", - "NE2A0", - "NE2A1", - "NE2A2", - "NE2A3", - "NE2BEG0", - "NE2BEG1", - "NE2BEG2", - "NE2BEG3", - "NE2END0", - "NE2END1", - "NE2END2", - "NE2END3", - "NE2END_S3_0", - "NE6A0", - "NE6A1", - "NE6A2", - "NE6A3", - "NE6B0", - "NE6B1", - "NE6B2", - "NE6B3", - "NE6BEG0", - "NE6BEG1", - "NE6BEG2", - "NE6BEG3", - "NE6C0", - "NE6C1", - "NE6C2", - "NE6C3", - "NE6D0", - "NE6D1", - "NE6D2", - "NE6D3", - "NE6E0", - "NE6E1", - "NE6E2", - "NE6E3", - "NE6END0", - "NE6END1", - "NE6END2", - "NE6END3", - "NL1BEG0", - "NL1BEG1", - "NL1BEG2", - "NL1BEG_N3", - "NL1END0", - "NL1END1", - "NL1END2", - "NL1END_S3_0", - "NN2A0", - "NN2A1", - "NN2A2", - "NN2A3", - "NN2BEG0", - "NN2BEG1", - "NN2BEG2", - "NN2BEG3", - "NN2END0", - "NN2END1", - "NN2END2", - "NN2END3", - "NN2END_S2_0", - "NN6A0", - "NN6A1", - "NN6A2", - "NN6A3", - "NN6B0", - "NN6B1", - "NN6B2", - "NN6B3", - "NN6BEG0", - "NN6BEG1", - "NN6BEG2", - "NN6BEG3", - "NN6C0", - "NN6C1", - "NN6C2", - "NN6C3", - "NN6D0", - "NN6D1", - "NN6D2", - "NN6D3", - "NN6E0", - "NN6E1", - "NN6E2", - "NN6E3", - "NN6END0", - "NN6END1", - "NN6END2", - "NN6END3", - "NN6END_S1_0", - "NR1BEG0", - "NR1BEG1", - "NR1BEG2", - "NR1BEG3", - "NR1END0", - "NR1END1", - "NR1END2", - "NR1END3", - "NW2A0", - "NW2A1", - "NW2A2", - "NW2A3", - "NW2BEG0", - "NW2BEG1", - "NW2BEG2", - "NW2BEG3", - "NW2END0", - "NW2END1", - "NW2END2", - "NW2END3", - "NW2END_S0_0", - "NW6A0", - "NW6A1", - "NW6A2", - "NW6A3", - "NW6B0", - "NW6B1", - "NW6B2", - "NW6B3", - "NW6BEG0", - "NW6BEG1", - "NW6BEG2", - "NW6BEG3", - "NW6C0", - "NW6C1", - "NW6C2", - "NW6C3", - "NW6D0", - "NW6D1", - "NW6D2", - "NW6D3", - "NW6E0", - "NW6E1", - "NW6E2", - "NW6E3", - "NW6END0", - "NW6END1", - "NW6END2", - "NW6END3", - "NW6END_S0_0", - "SE2A0", - "SE2A1", - "SE2A2", - "SE2A3", - "SE2BEG0", - "SE2BEG1", - "SE2BEG2", - "SE2BEG3", - "SE2END0", - "SE2END1", - "SE2END2", - "SE2END3", - "SE6A0", - "SE6A1", - "SE6A2", - "SE6A3", - "SE6B0", - "SE6B1", - "SE6B2", - "SE6B3", - "SE6BEG0", - "SE6BEG1", - "SE6BEG2", - "SE6BEG3", - "SE6C0", - "SE6C1", - "SE6C2", - "SE6C3", - "SE6D0", - "SE6D1", - "SE6D2", - "SE6D3", - "SE6E0", - "SE6E1", - "SE6E2", - "SE6E3", - "SE6END0", - "SE6END1", - "SE6END2", - "SE6END3", - "SL1BEG0", - "SL1BEG1", - "SL1BEG2", - "SL1BEG3", - "SL1END0", - "SL1END1", - "SL1END2", - "SL1END3", - "SR1BEG1", - "SR1BEG2", - "SR1BEG3", - "SR1BEG_S0", - "SR1END1", - "SR1END2", - "SR1END3", - "SR1END_N3_3", - "SS2A0", - "SS2A1", - "SS2A2", - "SS2A3", - "SS2BEG0", - "SS2BEG1", - "SS2BEG2", - "SS2BEG3", - "SS2END0", - "SS2END1", - "SS2END2", - "SS2END3", - "SS2END_N0_3", - "SS6A0", - "SS6A1", - "SS6A2", - "SS6A3", - "SS6B0", - "SS6B1", - "SS6B2", - "SS6B3", - "SS6BEG0", - "SS6BEG1", - "SS6BEG2", - "SS6BEG3", - "SS6C0", - "SS6C1", - "SS6C2", - "SS6C3", - "SS6D0", - "SS6D1", - "SS6D2", - "SS6D3", - "SS6E0", - "SS6E1", - "SS6E2", - "SS6E3", - "SS6END0", - "SS6END1", - "SS6END2", - "SS6END3", - "SS6END_N0_3", - "SW2A0", - "SW2A1", - "SW2A2", - "SW2A3", - "SW2BEG0", - "SW2BEG1", - "SW2BEG2", - "SW2BEG3", - "SW2END0", - "SW2END1", - "SW2END2", - "SW2END3", - "SW2END_N0_3", - "SW6A0", - "SW6A1", - "SW6A2", - "SW6A3", - "SW6B0", - "SW6B1", - "SW6B2", - "SW6B3", - "SW6BEG0", - "SW6BEG1", - "SW6BEG2", - "SW6BEG3", - "SW6C0", - "SW6C1", - "SW6C2", - "SW6C3", - "SW6D0", - "SW6D1", - "SW6D2", - "SW6D3", - "SW6E0", - "SW6E1", - "SW6E2", - "SW6E3", - "SW6END0", - "SW6END1", - "SW6END2", - "SW6END3", - "SW6END_N0_3", - "VCC_WIRE", - "WL1BEG0", - "WL1BEG1", - "WL1BEG2", - "WL1BEG3", - "WL1BEG_N3", - "WL1END0", - "WL1END1", - "WL1END2", - "WL1END3", - "WL1END_N1_3", - "WR1BEG0", - "WR1BEG1", - "WR1BEG2", - "WR1BEG3", - "WR1BEG_S0", - "WR1END0", - "WR1END1", - "WR1END2", - "WR1END3", - "WR1END_S1_0", - "WW2A0", - "WW2A1", - "WW2A2", - "WW2A3", - "WW2BEG0", - "WW2BEG1", - "WW2BEG2", - "WW2BEG3", - "WW2END0", - "WW2END1", - "WW2END2", - "WW2END3", - "WW2END_N0_3", - "WW4A0", - "WW4A1", - "WW4A2", - "WW4A3", - "WW4B0", - "WW4B1", - "WW4B2", - "WW4B3", - "WW4BEG0", - "WW4BEG1", - "WW4BEG2", - "WW4BEG3", - "WW4C0", - "WW4C1", - "WW4C2", - "WW4C3", - "WW4END0", - "WW4END1", - "WW4END2", - "WW4END3", - "WW4END_S0_0" - ] + "wires": { + "BYP_ALT0": null, + "BYP_ALT1": null, + "BYP_ALT2": null, + "BYP_ALT3": null, + "BYP_ALT4": null, + "BYP_ALT5": null, + "BYP_ALT6": null, + "BYP_ALT7": null, + "BYP_BOUNCE0": null, + "BYP_BOUNCE1": null, + "BYP_BOUNCE2": null, + "BYP_BOUNCE3": null, + "BYP_BOUNCE4": null, + "BYP_BOUNCE5": null, + "BYP_BOUNCE6": null, + "BYP_BOUNCE7": null, + "BYP_BOUNCE_N3_2": null, + "BYP_BOUNCE_N3_3": null, + "BYP_BOUNCE_N3_6": null, + "BYP_BOUNCE_N3_7": null, + "BYP_L0": null, + "BYP_L1": null, + "BYP_L2": null, + "BYP_L3": null, + "BYP_L4": null, + "BYP_L5": null, + "BYP_L6": null, + "BYP_L7": null, + "CLK_L0": null, + "CLK_L1": null, + "CTRL_L0": null, + "CTRL_L1": null, + "EE2A0": null, + "EE2A1": null, + "EE2A2": null, + "EE2A3": null, + "EE2BEG0": null, + "EE2BEG1": null, + "EE2BEG2": null, + "EE2BEG3": null, + "EE2END0": null, + "EE2END1": null, + "EE2END2": null, + "EE2END3": null, + "EE4A0": null, + "EE4A1": null, + "EE4A2": null, + "EE4A3": null, + "EE4B0": null, + "EE4B1": null, + "EE4B2": null, + "EE4B3": null, + "EE4BEG0": null, + "EE4BEG1": null, + "EE4BEG2": null, + "EE4BEG3": null, + "EE4C0": null, + "EE4C1": null, + "EE4C2": null, + "EE4C3": null, + "EE4END0": null, + "EE4END1": null, + "EE4END2": null, + "EE4END3": null, + "EL1BEG0": null, + "EL1BEG1": null, + "EL1BEG2": null, + "EL1BEG3": null, + "EL1BEG_N3": null, + "EL1END0": null, + "EL1END1": null, + "EL1END2": null, + "EL1END3": null, + "EL1END_S3_0": null, + "ER1BEG0": null, + "ER1BEG1": null, + "ER1BEG2": null, + "ER1BEG3": null, + "ER1BEG_S0": null, + "ER1END0": null, + "ER1END1": null, + "ER1END2": null, + "ER1END3": null, + "ER1END_N3_3": null, + "FAN_ALT0": null, + "FAN_ALT1": null, + "FAN_ALT2": null, + "FAN_ALT3": null, + "FAN_ALT4": null, + "FAN_ALT5": null, + "FAN_ALT6": null, + "FAN_ALT7": null, + "FAN_BOUNCE0": null, + "FAN_BOUNCE1": null, + "FAN_BOUNCE2": null, + "FAN_BOUNCE3": null, + "FAN_BOUNCE4": null, + "FAN_BOUNCE5": null, + "FAN_BOUNCE6": null, + "FAN_BOUNCE7": null, + "FAN_BOUNCE_S3_0": null, + "FAN_BOUNCE_S3_2": null, + "FAN_BOUNCE_S3_4": null, + "FAN_BOUNCE_S3_6": null, + "FAN_L0": null, + "FAN_L1": null, + "FAN_L2": null, + "FAN_L3": null, + "FAN_L4": null, + "FAN_L5": null, + "FAN_L6": null, + "FAN_L7": null, + "GCLK_L_B0": null, + "GCLK_L_B1": null, + "GCLK_L_B10": null, + "GCLK_L_B10_EAST": null, + "GCLK_L_B10_WEST": null, + "GCLK_L_B11": null, + "GCLK_L_B11_EAST": null, + "GCLK_L_B11_WEST": null, + "GCLK_L_B2": null, + "GCLK_L_B3": null, + "GCLK_L_B4": null, + "GCLK_L_B5": null, + "GCLK_L_B6": null, + "GCLK_L_B6_EAST": null, + "GCLK_L_B6_WEST": null, + "GCLK_L_B7": null, + "GCLK_L_B7_EAST": null, + "GCLK_L_B7_WEST": null, + "GCLK_L_B8": null, + "GCLK_L_B8_EAST": null, + "GCLK_L_B8_WEST": null, + "GCLK_L_B9": null, + "GCLK_L_B9_EAST": null, + "GCLK_L_B9_WEST": null, + "GFAN0": null, + "GFAN1": null, + "GND_WIRE": null, + "IMUX_L0": null, + "IMUX_L1": null, + "IMUX_L10": null, + "IMUX_L11": null, + "IMUX_L12": null, + "IMUX_L13": null, + "IMUX_L14": null, + "IMUX_L15": null, + "IMUX_L16": null, + "IMUX_L17": null, + "IMUX_L18": null, + "IMUX_L19": null, + "IMUX_L2": null, + "IMUX_L20": null, + "IMUX_L21": null, + "IMUX_L22": null, + "IMUX_L23": null, + "IMUX_L24": null, + "IMUX_L25": null, + "IMUX_L26": null, + "IMUX_L27": null, + "IMUX_L28": null, + "IMUX_L29": null, + "IMUX_L3": null, + "IMUX_L30": null, + "IMUX_L31": null, + "IMUX_L32": null, + "IMUX_L33": null, + "IMUX_L34": null, + "IMUX_L35": null, + "IMUX_L36": null, + "IMUX_L37": null, + "IMUX_L38": null, + "IMUX_L39": null, + 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"INT_R.WW4END3->>WR1BEG_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.036", + "0.047", + "0.066", + "0.080" + ], + "in_cap": "7.673", + "res": "524.1005" + }, "dst_wire": "WR1BEG_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.036", + "0.047", + "0.066", + "0.080" + ], + "in_cap": "7.673", + "res": "524.1005" + }, "src_wire": "WW4END3" }, "INT_R.WW4END3->>WW2BEG2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.074", + "0.089" + ], + "in_cap": "7.365", + "res": "515.3919374999999" + }, "dst_wire": "WW2BEG2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.074", + "0.089" + ], + "in_cap": "7.365", + "res": "515.3919374999999" + }, "src_wire": "WW4END3" }, "INT_R.WW4END3->>WW4BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.054", + "0.066", + "0.089", + "0.107" + ], + "in_cap": "7.586", + "res": "548.194625" + }, "dst_wire": "WW4BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.054", + "0.066", + "0.089", + "0.107" + ], + "in_cap": "7.586", + "res": "548.194625" + }, "src_wire": "WW4END3" }, "INT_R.WW4END_S0_0->>ER1BEG_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.036", + "0.047", + "0.066", + "0.080" + ], + "in_cap": "7.673", + "res": "524.1005" + }, "dst_wire": "ER1BEG_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.036", + "0.047", + "0.066", + "0.080" + ], + "in_cap": "7.673", + "res": "524.1005" + }, "src_wire": "WW4END_S0_0" }, "INT_R.WW4END_S0_0->>SR1BEG_S0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.047", + "0.066", + "0.080" + ], + "in_cap": "7.673", + "res": "524.1005" + }, "dst_wire": "SR1BEG_S0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.047", + "0.066", + "0.080" + ], + "in_cap": "7.673", + "res": "524.1005" + }, "src_wire": "WW4END_S0_0" }, "INT_R.WW4END_S0_0->>SS2BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.044", + "0.053", + "0.073", + "0.089" + ], + "in_cap": "7.365", + "res": "515.3919374999999" + }, "dst_wire": "SS2BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.044", + "0.053", + "0.073", + "0.089" + ], + "in_cap": "7.365", + "res": "515.3919374999999" + }, "src_wire": "WW4END_S0_0" }, "INT_R.WW4END_S0_0->>SS6BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.067", + "0.082", + "0.109", + "0.133" + ], + "in_cap": "8.242", + "res": "768.6401249999999" + }, "dst_wire": "SS6BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.067", + "0.082", + "0.109", + "0.133" + ], + "in_cap": "8.242", + "res": "768.6401249999999" + }, "src_wire": "WW4END_S0_0" }, "INT_R.WW4END_S0_0->>SW2BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.038", + "0.051", + "0.069", + "0.085" + ], + "in_cap": "7.487", + "res": "505.863875" + }, "dst_wire": "SW2BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.038", + "0.051", + "0.069", + "0.085" + ], + "in_cap": "7.487", + "res": "505.863875" + }, "src_wire": "WW4END_S0_0" }, "INT_R.WW4END_S0_0->>SW6BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.062", + "0.075", + "0.100", + "0.121" + ], + "in_cap": "8.242", + "res": "768.6401249999999" + }, "dst_wire": "SW6BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.062", + "0.075", + "0.100", + "0.121" + ], + "in_cap": "8.242", + "res": "768.6401249999999" + }, "src_wire": "WW4END_S0_0" }, "INT_R.WW4END_S0_0->>WL1BEG2": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.035", + "0.045", + "0.064", + "0.077" + ], + "in_cap": "7.673", + "res": "524.1005" + }, "dst_wire": "WL1BEG2", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.035", + "0.045", + "0.064", + "0.077" + ], + "in_cap": "7.673", + "res": "524.1005" + }, "src_wire": "WW4END_S0_0" }, "INT_R.WW4END_S0_0->>WW2BEG3": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.045", + "0.055", + "0.074", + "0.089" + ], + "in_cap": "7.365", + "res": "515.3919374999999" + }, "dst_wire": "WW2BEG3", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.045", + "0.055", + "0.074", + "0.089" + ], + "in_cap": "7.365", + "res": "515.3919374999999" + }, "src_wire": "WW4END_S0_0" } }, @@ -26165,8 +104642,26 @@ "name": "X0Y0", "prefix": "TIEOFF", "site_pins": { - "HARD0": "GND_WIRE", - "HARD1": "VCC_WIRE" + "HARD0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "GND_WIRE" + }, + "HARD1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "VCC_WIRE" + } }, "type": "TIEOFF", "x_coord": 0, @@ -26174,606 +104669,702 @@ } ], "tile_type": "INT_R", - "wires": [ - "BYP0", - "BYP1", - "BYP2", - "BYP3", - "BYP4", - "BYP5", - "BYP6", - "BYP7", - "BYP_ALT0", - "BYP_ALT1", - "BYP_ALT2", - "BYP_ALT3", - "BYP_ALT4", - "BYP_ALT5", - "BYP_ALT6", - "BYP_ALT7", - "BYP_BOUNCE0", - "BYP_BOUNCE1", - "BYP_BOUNCE2", - "BYP_BOUNCE3", - "BYP_BOUNCE4", - "BYP_BOUNCE5", - "BYP_BOUNCE6", - "BYP_BOUNCE7", - "BYP_BOUNCE_N3_2", - "BYP_BOUNCE_N3_3", - "BYP_BOUNCE_N3_6", - "BYP_BOUNCE_N3_7", - "CLK0", - "CLK1", - "CTRL0", - "CTRL1", - "EE2A0", - "EE2A1", - "EE2A2", - "EE2A3", - "EE2BEG0", - "EE2BEG1", - "EE2BEG2", - "EE2BEG3", - "EE2END0", - "EE2END1", - "EE2END2", - "EE2END3", - "EE4A0", - "EE4A1", - "EE4A2", - "EE4A3", - "EE4B0", - "EE4B1", - "EE4B2", - "EE4B3", - "EE4BEG0", - "EE4BEG1", - "EE4BEG2", - "EE4BEG3", - "EE4C0", - "EE4C1", - "EE4C2", - "EE4C3", - "EE4END0", - "EE4END1", - "EE4END2", - "EE4END3", - "EL1BEG0", - "EL1BEG1", - "EL1BEG2", - "EL1BEG3", - "EL1BEG_N3", - "EL1END0", - "EL1END1", - "EL1END2", - "EL1END3", - "EL1END_S3_0", - "ER1BEG0", - "ER1BEG1", - "ER1BEG2", - "ER1BEG3", - "ER1BEG_S0", - "ER1END0", - "ER1END1", - "ER1END2", - "ER1END3", - "ER1END_N3_3", - "FAN0", - "FAN1", - "FAN2", - "FAN3", - "FAN4", - "FAN5", - "FAN6", - "FAN7", - "FAN_ALT0", - "FAN_ALT1", - "FAN_ALT2", - "FAN_ALT3", - "FAN_ALT4", - "FAN_ALT5", - "FAN_ALT6", - "FAN_ALT7", - "FAN_BOUNCE0", - "FAN_BOUNCE1", - "FAN_BOUNCE2", - "FAN_BOUNCE3", - "FAN_BOUNCE4", - "FAN_BOUNCE5", - "FAN_BOUNCE6", - "FAN_BOUNCE7", - "FAN_BOUNCE_S3_0", - "FAN_BOUNCE_S3_2", - "FAN_BOUNCE_S3_4", - "FAN_BOUNCE_S3_6", - "GCLK_B0", - "GCLK_B0_EAST", - "GCLK_B0_WEST", - "GCLK_B1", - "GCLK_B10", - "GCLK_B11", - "GCLK_B1_EAST", - "GCLK_B1_WEST", - "GCLK_B2", - "GCLK_B2_EAST", - "GCLK_B2_WEST", - "GCLK_B3", - "GCLK_B3_EAST", - "GCLK_B3_WEST", - "GCLK_B4", - "GCLK_B4_EAST", - "GCLK_B4_WEST", - "GCLK_B5", - "GCLK_B5_EAST", - "GCLK_B5_WEST", - "GCLK_B6", - "GCLK_B7", - "GCLK_B8", - "GCLK_B9", - "GFAN0", - "GFAN1", - "GND_WIRE", - "IMUX0", - "IMUX1", - "IMUX10", - "IMUX11", - "IMUX12", - "IMUX13", - "IMUX14", - "IMUX15", - "IMUX16", - "IMUX17", - "IMUX18", - "IMUX19", - "IMUX2", - "IMUX20", - "IMUX21", - "IMUX22", - "IMUX23", - "IMUX24", - "IMUX25", - "IMUX26", - "IMUX27", - "IMUX28", - "IMUX29", - "IMUX3", - "IMUX30", - "IMUX31", - "IMUX32", - "IMUX33", - "IMUX34", - "IMUX35", - "IMUX36", - "IMUX37", - "IMUX38", - "IMUX39", - "IMUX4", - "IMUX40", - "IMUX41", - "IMUX42", - "IMUX43", - "IMUX44", - "IMUX45", - "IMUX46", - "IMUX47", - "IMUX5", - "IMUX6", - "IMUX7", - "IMUX8", - "IMUX9", - "INT_DQS_IOTOPHASER", - "INT_PHASER_TO_IO_ICLK", - "INT_PHASER_TO_IO_ICLKDIV", - "INT_PHASER_TO_IO_OCLK", - "INT_PHASER_TO_IO_OCLK1X_90", - "INT_PHASER_TO_IO_OCLKDIV", - "LH0", - "LH1", - "LH10", - "LH11", - "LH12", - "LH2", - "LH3", - "LH4", - "LH5", - "LH6", - "LH7", - "LH8", - "LH9", - "LOGIC_OUTS0", - "LOGIC_OUTS1", - "LOGIC_OUTS10", - "LOGIC_OUTS11", - "LOGIC_OUTS12", - "LOGIC_OUTS13", - "LOGIC_OUTS14", - "LOGIC_OUTS15", - "LOGIC_OUTS16", - "LOGIC_OUTS17", - "LOGIC_OUTS18", - "LOGIC_OUTS19", - "LOGIC_OUTS2", - "LOGIC_OUTS20", - "LOGIC_OUTS21", - "LOGIC_OUTS22", - "LOGIC_OUTS23", - "LOGIC_OUTS3", - "LOGIC_OUTS4", - "LOGIC_OUTS5", - "LOGIC_OUTS6", - "LOGIC_OUTS7", - "LOGIC_OUTS8", - "LOGIC_OUTS9", - "LV0", - "LV1", - "LV10", - "LV11", - "LV12", - "LV13", - "LV14", - "LV15", - "LV16", - "LV17", - "LV18", - "LV2", - "LV3", - "LV4", - "LV5", - "LV6", - "LV7", - "LV8", - "LV9", - "LVB0", - "LVB1", - "LVB10", - "LVB11", - "LVB12", - "LVB2", - "LVB3", - "LVB4", - "LVB5", - "LVB6", - "LVB7", - "LVB8", - "LVB9", - "MONITOR_N", - "MONITOR_P", - "NE2A0", - "NE2A1", - "NE2A2", - "NE2A3", - "NE2BEG0", - "NE2BEG1", - "NE2BEG2", - "NE2BEG3", - "NE2END0", - "NE2END1", - "NE2END2", - "NE2END3", - "NE2END_S3_0", - "NE6A0", - "NE6A1", - "NE6A2", - "NE6A3", - "NE6B0", - "NE6B1", - "NE6B2", - "NE6B3", - "NE6BEG0", - "NE6BEG1", - "NE6BEG2", - "NE6BEG3", - "NE6C0", - "NE6C1", - "NE6C2", - "NE6C3", - "NE6D0", - "NE6D1", - "NE6D2", - "NE6D3", - "NE6E0", - "NE6E1", - "NE6E2", - "NE6E3", - "NE6END0", - "NE6END1", - "NE6END2", - "NE6END3", - "NL1BEG0", - "NL1BEG1", - "NL1BEG2", - "NL1BEG_N3", - "NL1END0", - "NL1END1", - "NL1END2", - "NL1END_S3_0", - "NN2A0", - "NN2A1", - "NN2A2", - "NN2A3", - "NN2BEG0", - "NN2BEG1", - "NN2BEG2", - "NN2BEG3", - "NN2END0", - "NN2END1", - "NN2END2", - "NN2END3", - "NN2END_S2_0", - "NN6A0", - "NN6A1", - "NN6A2", - "NN6A3", - "NN6B0", - "NN6B1", - "NN6B2", - "NN6B3", - "NN6BEG0", - "NN6BEG1", - "NN6BEG2", - "NN6BEG3", - "NN6C0", - "NN6C1", - "NN6C2", - "NN6C3", - "NN6D0", - "NN6D1", - "NN6D2", - "NN6D3", - "NN6E0", - "NN6E1", - "NN6E2", - "NN6E3", - "NN6END0", - "NN6END1", - "NN6END2", - "NN6END3", - "NN6END_S1_0", - "NR1BEG0", - "NR1BEG1", - "NR1BEG2", - "NR1BEG3", - "NR1END0", - "NR1END1", - "NR1END2", - "NR1END3", - "NW2A0", - "NW2A1", - "NW2A2", - "NW2A3", - "NW2BEG0", - "NW2BEG1", - "NW2BEG2", - "NW2BEG3", - "NW2END0", - "NW2END1", - "NW2END2", - "NW2END3", - "NW2END_S0_0", - "NW6A0", - "NW6A1", - "NW6A2", - "NW6A3", - "NW6B0", - "NW6B1", - "NW6B2", - "NW6B3", - "NW6BEG0", - "NW6BEG1", - "NW6BEG2", - "NW6BEG3", - "NW6C0", - "NW6C1", - "NW6C2", - "NW6C3", - "NW6D0", - "NW6D1", - "NW6D2", - "NW6D3", - "NW6E0", - "NW6E1", - "NW6E2", - "NW6E3", - "NW6END0", - "NW6END1", - "NW6END2", - "NW6END3", - "NW6END_S0_0", - "SE2A0", - "SE2A1", - "SE2A2", - "SE2A3", - "SE2BEG0", - "SE2BEG1", - "SE2BEG2", - "SE2BEG3", - "SE2END0", - "SE2END1", - "SE2END2", - "SE2END3", - "SE6A0", - "SE6A1", - "SE6A2", - "SE6A3", - "SE6B0", - "SE6B1", - "SE6B2", - "SE6B3", - "SE6BEG0", - "SE6BEG1", - "SE6BEG2", - "SE6BEG3", - "SE6C0", - "SE6C1", - "SE6C2", - "SE6C3", - "SE6D0", - "SE6D1", - "SE6D2", - "SE6D3", - "SE6E0", - "SE6E1", - "SE6E2", - "SE6E3", - "SE6END0", - "SE6END1", - "SE6END2", - "SE6END3", - "SL1BEG0", - "SL1BEG1", - "SL1BEG2", - "SL1BEG3", - "SL1END0", - "SL1END1", - "SL1END2", - "SL1END3", - "SR1BEG1", - "SR1BEG2", - "SR1BEG3", - "SR1BEG_S0", - "SR1END1", - "SR1END2", - "SR1END3", - "SR1END_N3_3", - "SS2A0", - "SS2A1", - "SS2A2", - "SS2A3", - "SS2BEG0", - "SS2BEG1", - "SS2BEG2", - "SS2BEG3", - "SS2END0", - "SS2END1", - "SS2END2", - "SS2END3", - "SS2END_N0_3", - "SS6A0", - "SS6A1", - "SS6A2", - "SS6A3", - "SS6B0", - "SS6B1", - "SS6B2", - "SS6B3", - "SS6BEG0", - "SS6BEG1", - "SS6BEG2", - "SS6BEG3", - "SS6C0", - "SS6C1", - "SS6C2", - "SS6C3", - "SS6D0", - "SS6D1", - "SS6D2", - "SS6D3", - "SS6E0", - "SS6E1", - "SS6E2", - "SS6E3", - "SS6END0", - "SS6END1", - "SS6END2", - "SS6END3", - "SS6END_N0_3", - "SW2A0", - "SW2A1", - "SW2A2", - "SW2A3", - "SW2BEG0", - "SW2BEG1", - "SW2BEG2", - "SW2BEG3", - "SW2END0", - "SW2END1", - "SW2END2", - "SW2END3", - "SW2END_N0_3", - "SW6A0", - "SW6A1", - "SW6A2", - "SW6A3", - "SW6B0", - "SW6B1", - "SW6B2", - "SW6B3", - "SW6BEG0", - "SW6BEG1", - "SW6BEG2", - "SW6BEG3", - "SW6C0", - "SW6C1", - "SW6C2", - "SW6C3", - "SW6D0", - "SW6D1", - "SW6D2", - "SW6D3", - "SW6E0", - "SW6E1", - "SW6E2", - "SW6E3", - "SW6END0", - "SW6END1", - "SW6END2", - "SW6END3", - "SW6END_N0_3", - "VCC_WIRE", - "WL1BEG0", - "WL1BEG1", - "WL1BEG2", - "WL1BEG3", - "WL1BEG_N3", - "WL1END0", - "WL1END1", - "WL1END2", - "WL1END3", - "WL1END_N1_3", - "WR1BEG0", - "WR1BEG1", - "WR1BEG2", - "WR1BEG3", - "WR1BEG_S0", - "WR1END0", - "WR1END1", - "WR1END2", - "WR1END3", - "WR1END_S1_0", - "WW2A0", - "WW2A1", - "WW2A2", - "WW2A3", - "WW2BEG0", - "WW2BEG1", - "WW2BEG2", - "WW2BEG3", - "WW2END0", - "WW2END1", - "WW2END2", - "WW2END3", - "WW2END_N0_3", - "WW4A0", - "WW4A1", - "WW4A2", - "WW4A3", - "WW4B0", - "WW4B1", - "WW4B2", - "WW4B3", - "WW4BEG0", - "WW4BEG1", - "WW4BEG2", - "WW4BEG3", - "WW4C0", - "WW4C1", - "WW4C2", - "WW4C3", - "WW4END0", - "WW4END1", - "WW4END2", - "WW4END3", - "WW4END_S0_0" - ] + "wires": { + "BYP0": null, + "BYP1": null, + "BYP2": null, + "BYP3": null, + "BYP4": null, + "BYP5": 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"INT_INTERFACE_LH12", - "INT_INTERFACE_LH2", - "INT_INTERFACE_LH3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_LH5", - "INT_INTERFACE_LH6", - "INT_INTERFACE_LH7", - "INT_INTERFACE_LH8", - "INT_INTERFACE_LH9", - "INT_INTERFACE_LOGIC_OUTS_L0", - "INT_INTERFACE_LOGIC_OUTS_L1", - "INT_INTERFACE_LOGIC_OUTS_L10", - "INT_INTERFACE_LOGIC_OUTS_L11", - "INT_INTERFACE_LOGIC_OUTS_L12", - "INT_INTERFACE_LOGIC_OUTS_L13", - "INT_INTERFACE_LOGIC_OUTS_L14", - "INT_INTERFACE_LOGIC_OUTS_L15", - "INT_INTERFACE_LOGIC_OUTS_L16", - "INT_INTERFACE_LOGIC_OUTS_L17", - "INT_INTERFACE_LOGIC_OUTS_L18", - "INT_INTERFACE_LOGIC_OUTS_L19", - "INT_INTERFACE_LOGIC_OUTS_L2", - "INT_INTERFACE_LOGIC_OUTS_L20", - "INT_INTERFACE_LOGIC_OUTS_L21", - "INT_INTERFACE_LOGIC_OUTS_L22", - "INT_INTERFACE_LOGIC_OUTS_L23", - "INT_INTERFACE_LOGIC_OUTS_L3", - "INT_INTERFACE_LOGIC_OUTS_L4", - "INT_INTERFACE_LOGIC_OUTS_L5", - "INT_INTERFACE_LOGIC_OUTS_L6", - "INT_INTERFACE_LOGIC_OUTS_L7", - "INT_INTERFACE_LOGIC_OUTS_L8", - "INT_INTERFACE_LOGIC_OUTS_L9", - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "INT_INTERFACE_LOGIC_OUTS_L_B14", - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_PHASER_TO_IO_ICLK", - "INT_INTERFACE_PHASER_TO_IO_ICLKDIV", - "INT_INTERFACE_PHASER_TO_IO_OCLK", - "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90", - "INT_INTERFACE_PHASER_TO_IO_OCLKDIV", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW4END3", - "L_INT_INTER_DQS_IOTOPHASER" - ] + "wires": { + "INT_INTERFACE_BLOCK_OUTS_L_B0": null, + "INT_INTERFACE_BLOCK_OUTS_L_B1": null, + "INT_INTERFACE_BLOCK_OUTS_L_B2": null, + "INT_INTERFACE_BLOCK_OUTS_L_B3": null, + "INT_INTERFACE_BYP0": null, + "INT_INTERFACE_BYP1": null, + "INT_INTERFACE_BYP2": null, + "INT_INTERFACE_BYP3": null, + "INT_INTERFACE_BYP4": null, + "INT_INTERFACE_BYP5": null, + "INT_INTERFACE_BYP6": null, + "INT_INTERFACE_BYP7": null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_IMUX0": null, + "INT_INTERFACE_IMUX1": null, + "INT_INTERFACE_IMUX10": null, + "INT_INTERFACE_IMUX11": null, + "INT_INTERFACE_IMUX12": null, + "INT_INTERFACE_IMUX13": null, + "INT_INTERFACE_IMUX14": null, + "INT_INTERFACE_IMUX15": null, + "INT_INTERFACE_IMUX16": null, + "INT_INTERFACE_IMUX17": null, + "INT_INTERFACE_IMUX18": null, + "INT_INTERFACE_IMUX19": null, + "INT_INTERFACE_IMUX2": null, + "INT_INTERFACE_IMUX20": null, + "INT_INTERFACE_IMUX21": null, + "INT_INTERFACE_IMUX22": null, + "INT_INTERFACE_IMUX23": null, + "INT_INTERFACE_IMUX24": null, + "INT_INTERFACE_IMUX25": null, + "INT_INTERFACE_IMUX26": null, + "INT_INTERFACE_IMUX27": null, + "INT_INTERFACE_IMUX28": null, + "INT_INTERFACE_IMUX29": null, + "INT_INTERFACE_IMUX3": null, + "INT_INTERFACE_IMUX30": null, + "INT_INTERFACE_IMUX31": null, + "INT_INTERFACE_IMUX32": null, + "INT_INTERFACE_IMUX33": null, + "INT_INTERFACE_IMUX34": null, + "INT_INTERFACE_IMUX35": null, + "INT_INTERFACE_IMUX36": null, + "INT_INTERFACE_IMUX37": null, + "INT_INTERFACE_IMUX38": null, + "INT_INTERFACE_IMUX39": null, + "INT_INTERFACE_IMUX4": null, + "INT_INTERFACE_IMUX40": null, + "INT_INTERFACE_IMUX41": null, + "INT_INTERFACE_IMUX42": null, + "INT_INTERFACE_IMUX43": null, + "INT_INTERFACE_IMUX44": null, + "INT_INTERFACE_IMUX45": null, + "INT_INTERFACE_IMUX46": null, + "INT_INTERFACE_IMUX47": null, + "INT_INTERFACE_IMUX5": null, + "INT_INTERFACE_IMUX6": null, + "INT_INTERFACE_IMUX7": null, + "INT_INTERFACE_IMUX8": null, + "INT_INTERFACE_IMUX9": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS_L0": null, + "INT_INTERFACE_LOGIC_OUTS_L1": null, + "INT_INTERFACE_LOGIC_OUTS_L10": null, + "INT_INTERFACE_LOGIC_OUTS_L11": null, + "INT_INTERFACE_LOGIC_OUTS_L12": null, + "INT_INTERFACE_LOGIC_OUTS_L13": null, + "INT_INTERFACE_LOGIC_OUTS_L14": null, + "INT_INTERFACE_LOGIC_OUTS_L15": null, + "INT_INTERFACE_LOGIC_OUTS_L16": null, + "INT_INTERFACE_LOGIC_OUTS_L17": null, + "INT_INTERFACE_LOGIC_OUTS_L18": null, + "INT_INTERFACE_LOGIC_OUTS_L19": null, + "INT_INTERFACE_LOGIC_OUTS_L2": null, + "INT_INTERFACE_LOGIC_OUTS_L20": null, + "INT_INTERFACE_LOGIC_OUTS_L21": null, + "INT_INTERFACE_LOGIC_OUTS_L22": null, + "INT_INTERFACE_LOGIC_OUTS_L23": null, + "INT_INTERFACE_LOGIC_OUTS_L3": null, + "INT_INTERFACE_LOGIC_OUTS_L4": null, + "INT_INTERFACE_LOGIC_OUTS_L5": null, + "INT_INTERFACE_LOGIC_OUTS_L6": null, + "INT_INTERFACE_LOGIC_OUTS_L7": null, + "INT_INTERFACE_LOGIC_OUTS_L8": null, + "INT_INTERFACE_LOGIC_OUTS_L9": null, + "INT_INTERFACE_LOGIC_OUTS_L_B0": null, + "INT_INTERFACE_LOGIC_OUTS_L_B1": null, + "INT_INTERFACE_LOGIC_OUTS_L_B10": null, + "INT_INTERFACE_LOGIC_OUTS_L_B11": null, + "INT_INTERFACE_LOGIC_OUTS_L_B12": null, + "INT_INTERFACE_LOGIC_OUTS_L_B13": null, + "INT_INTERFACE_LOGIC_OUTS_L_B14": null, + "INT_INTERFACE_LOGIC_OUTS_L_B15": null, + "INT_INTERFACE_LOGIC_OUTS_L_B16": null, + "INT_INTERFACE_LOGIC_OUTS_L_B17": null, + "INT_INTERFACE_LOGIC_OUTS_L_B18": null, + "INT_INTERFACE_LOGIC_OUTS_L_B19": null, + "INT_INTERFACE_LOGIC_OUTS_L_B2": null, + "INT_INTERFACE_LOGIC_OUTS_L_B20": null, + "INT_INTERFACE_LOGIC_OUTS_L_B21": null, + "INT_INTERFACE_LOGIC_OUTS_L_B22": null, + "INT_INTERFACE_LOGIC_OUTS_L_B23": null, + "INT_INTERFACE_LOGIC_OUTS_L_B3": null, + "INT_INTERFACE_LOGIC_OUTS_L_B4": null, + "INT_INTERFACE_LOGIC_OUTS_L_B5": null, + "INT_INTERFACE_LOGIC_OUTS_L_B6": null, + "INT_INTERFACE_LOGIC_OUTS_L_B7": null, + "INT_INTERFACE_LOGIC_OUTS_L_B8": null, + "INT_INTERFACE_LOGIC_OUTS_L_B9": null, + "INT_INTERFACE_MONITOR_N": null, + "INT_INTERFACE_MONITOR_P": null, + "INT_INTERFACE_NE2A0": null, + "INT_INTERFACE_NE2A1": null, + "INT_INTERFACE_NE2A2": null, + "INT_INTERFACE_NE2A3": null, + "INT_INTERFACE_NE4BEG0": null, + "INT_INTERFACE_NE4BEG1": null, + "INT_INTERFACE_NE4BEG2": null, + "INT_INTERFACE_NE4BEG3": null, + "INT_INTERFACE_NE4C0": null, + "INT_INTERFACE_NE4C1": null, + "INT_INTERFACE_NE4C2": null, + "INT_INTERFACE_NE4C3": null, + "INT_INTERFACE_NW2A0": null, + "INT_INTERFACE_NW2A1": null, + "INT_INTERFACE_NW2A2": null, + "INT_INTERFACE_NW2A3": null, + "INT_INTERFACE_NW4A0": null, + "INT_INTERFACE_NW4A1": null, + "INT_INTERFACE_NW4A2": null, + "INT_INTERFACE_NW4A3": null, + "INT_INTERFACE_NW4END0": null, + "INT_INTERFACE_NW4END1": null, + "INT_INTERFACE_NW4END2": null, + "INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_PHASER_TO_IO_ICLK": null, + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90": null, + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + "INT_INTERFACE_SW4END3": null, + "INT_INTERFACE_WL1END0": null, + "INT_INTERFACE_WL1END1": null, + "INT_INTERFACE_WL1END2": null, + "INT_INTERFACE_WL1END3": null, + "INT_INTERFACE_WR1END0": null, + "INT_INTERFACE_WR1END1": null, + "INT_INTERFACE_WR1END2": null, + "INT_INTERFACE_WR1END3": null, + "INT_INTERFACE_WW2A0": null, + "INT_INTERFACE_WW2A1": null, + "INT_INTERFACE_WW2A2": null, + "INT_INTERFACE_WW2A3": null, + "INT_INTERFACE_WW2END0": null, + "INT_INTERFACE_WW2END1": null, + "INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/kintex7/tile_type_IO_INT_INTERFACE_R.json b/kintex7/tile_type_IO_INT_INTERFACE_R.json index f2c39bd..172ac41 100644 --- a/kintex7/tile_type_IO_INT_INTERFACE_R.json +++ b/kintex7/tile_type_IO_INT_INTERFACE_R.json @@ -2,427 +2,931 @@ "pips": { "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B0->>INT_INTERFACE_LOGIC_OUTS0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "src_wire": "INT_INTERFACE_LOGIC_OUTS_B0" }, "IO_INT_INTERFACE_R.INT_INTERFACE_LOGIC_OUTS_B1->>INT_INTERFACE_LOGIC_OUTS1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.047", + "0.057", + "0.085", + "0.104" + ], + "in_cap": "5.296", + "res": "922.18775" + }, "dst_wire": "INT_INTERFACE_LOGIC_OUTS1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": 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"INT_INTERFACE_LOGIC_OUTS4", - "INT_INTERFACE_LOGIC_OUTS5", - "INT_INTERFACE_LOGIC_OUTS6", - "INT_INTERFACE_LOGIC_OUTS7", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS9", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_LOGIC_OUTS_B1", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS_B11", - "INT_INTERFACE_LOGIC_OUTS_B12", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_LOGIC_OUTS_B14", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_LOGIC_OUTS_B18", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_LOGIC_OUTS_B2", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_LOGIC_OUTS_B21", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_LOGIC_OUTS_B23", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_LOGIC_OUTS_B4", - "INT_INTERFACE_LOGIC_OUTS_B5", - "INT_INTERFACE_LOGIC_OUTS_B6", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_LOGIC_OUTS_B9", - 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"INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW4END3", - "L_INT_INTER_DQS_IOTOPHASER" - ] + "wires": { + "INT_INTERFACE_BLOCK_OUTS_B0": null, + "INT_INTERFACE_BLOCK_OUTS_B1": null, + "INT_INTERFACE_BLOCK_OUTS_B2": null, + "INT_INTERFACE_BLOCK_OUTS_B3": null, + "INT_INTERFACE_BYP0": null, + "INT_INTERFACE_BYP1": null, + "INT_INTERFACE_BYP2": null, + "INT_INTERFACE_BYP3": null, + "INT_INTERFACE_BYP4": null, + "INT_INTERFACE_BYP5": null, + "INT_INTERFACE_BYP6": null, + "INT_INTERFACE_BYP7": null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_IMUX0": null, + "INT_INTERFACE_IMUX1": null, + "INT_INTERFACE_IMUX10": null, + "INT_INTERFACE_IMUX11": null, + "INT_INTERFACE_IMUX12": null, + "INT_INTERFACE_IMUX13": null, + "INT_INTERFACE_IMUX14": null, + "INT_INTERFACE_IMUX15": null, + "INT_INTERFACE_IMUX16": null, + "INT_INTERFACE_IMUX17": null, + "INT_INTERFACE_IMUX18": null, + "INT_INTERFACE_IMUX19": null, + "INT_INTERFACE_IMUX2": null, + "INT_INTERFACE_IMUX20": null, + "INT_INTERFACE_IMUX21": null, + "INT_INTERFACE_IMUX22": null, + "INT_INTERFACE_IMUX23": null, + "INT_INTERFACE_IMUX24": null, + "INT_INTERFACE_IMUX25": null, + "INT_INTERFACE_IMUX26": null, + "INT_INTERFACE_IMUX27": null, + "INT_INTERFACE_IMUX28": null, + "INT_INTERFACE_IMUX29": null, + "INT_INTERFACE_IMUX3": null, + "INT_INTERFACE_IMUX30": null, + "INT_INTERFACE_IMUX31": null, + "INT_INTERFACE_IMUX32": null, + "INT_INTERFACE_IMUX33": null, + "INT_INTERFACE_IMUX34": null, + "INT_INTERFACE_IMUX35": null, + "INT_INTERFACE_IMUX36": null, + "INT_INTERFACE_IMUX37": null, + "INT_INTERFACE_IMUX38": null, + "INT_INTERFACE_IMUX39": null, + "INT_INTERFACE_IMUX4": null, + "INT_INTERFACE_IMUX40": null, + "INT_INTERFACE_IMUX41": null, + "INT_INTERFACE_IMUX42": null, + "INT_INTERFACE_IMUX43": null, + "INT_INTERFACE_IMUX44": null, + "INT_INTERFACE_IMUX45": null, + "INT_INTERFACE_IMUX46": null, + "INT_INTERFACE_IMUX47": null, + "INT_INTERFACE_IMUX5": null, + "INT_INTERFACE_IMUX6": null, + "INT_INTERFACE_IMUX7": null, + "INT_INTERFACE_IMUX8": null, + "INT_INTERFACE_IMUX9": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS0": null, + "INT_INTERFACE_LOGIC_OUTS1": null, + "INT_INTERFACE_LOGIC_OUTS10": null, + "INT_INTERFACE_LOGIC_OUTS11": null, + "INT_INTERFACE_LOGIC_OUTS12": null, + "INT_INTERFACE_LOGIC_OUTS13": null, + "INT_INTERFACE_LOGIC_OUTS14": null, + "INT_INTERFACE_LOGIC_OUTS15": null, + "INT_INTERFACE_LOGIC_OUTS16": null, + "INT_INTERFACE_LOGIC_OUTS17": null, + "INT_INTERFACE_LOGIC_OUTS18": null, + "INT_INTERFACE_LOGIC_OUTS19": null, + "INT_INTERFACE_LOGIC_OUTS2": null, + "INT_INTERFACE_LOGIC_OUTS20": null, + "INT_INTERFACE_LOGIC_OUTS21": null, + "INT_INTERFACE_LOGIC_OUTS22": null, + "INT_INTERFACE_LOGIC_OUTS23": null, + "INT_INTERFACE_LOGIC_OUTS3": null, + "INT_INTERFACE_LOGIC_OUTS4": null, + "INT_INTERFACE_LOGIC_OUTS5": null, + "INT_INTERFACE_LOGIC_OUTS6": null, + "INT_INTERFACE_LOGIC_OUTS7": null, + "INT_INTERFACE_LOGIC_OUTS8": null, + "INT_INTERFACE_LOGIC_OUTS9": null, + "INT_INTERFACE_LOGIC_OUTS_B0": null, + "INT_INTERFACE_LOGIC_OUTS_B1": null, + "INT_INTERFACE_LOGIC_OUTS_B10": null, + "INT_INTERFACE_LOGIC_OUTS_B11": null, + "INT_INTERFACE_LOGIC_OUTS_B12": null, + "INT_INTERFACE_LOGIC_OUTS_B13": null, + "INT_INTERFACE_LOGIC_OUTS_B14": null, + "INT_INTERFACE_LOGIC_OUTS_B15": null, + "INT_INTERFACE_LOGIC_OUTS_B16": null, + "INT_INTERFACE_LOGIC_OUTS_B17": null, + "INT_INTERFACE_LOGIC_OUTS_B18": null, + "INT_INTERFACE_LOGIC_OUTS_B19": null, + "INT_INTERFACE_LOGIC_OUTS_B2": null, + "INT_INTERFACE_LOGIC_OUTS_B20": null, + "INT_INTERFACE_LOGIC_OUTS_B21": null, + "INT_INTERFACE_LOGIC_OUTS_B22": null, + "INT_INTERFACE_LOGIC_OUTS_B23": null, + "INT_INTERFACE_LOGIC_OUTS_B3": null, + "INT_INTERFACE_LOGIC_OUTS_B4": null, + "INT_INTERFACE_LOGIC_OUTS_B5": null, + "INT_INTERFACE_LOGIC_OUTS_B6": null, + "INT_INTERFACE_LOGIC_OUTS_B7": null, + "INT_INTERFACE_LOGIC_OUTS_B8": null, + "INT_INTERFACE_LOGIC_OUTS_B9": null, + "INT_INTERFACE_MONITOR_N": null, + "INT_INTERFACE_MONITOR_P": null, + "INT_INTERFACE_NE2A0": null, + "INT_INTERFACE_NE2A1": null, + "INT_INTERFACE_NE2A2": null, + "INT_INTERFACE_NE2A3": null, + "INT_INTERFACE_NE4BEG0": null, + "INT_INTERFACE_NE4BEG1": null, + "INT_INTERFACE_NE4BEG2": null, + "INT_INTERFACE_NE4BEG3": null, + "INT_INTERFACE_NE4C0": null, + "INT_INTERFACE_NE4C1": null, + "INT_INTERFACE_NE4C2": null, + "INT_INTERFACE_NE4C3": null, + "INT_INTERFACE_NW2A0": null, + "INT_INTERFACE_NW2A1": null, + "INT_INTERFACE_NW2A2": null, + "INT_INTERFACE_NW2A3": null, + "INT_INTERFACE_NW4A0": null, + "INT_INTERFACE_NW4A1": null, + "INT_INTERFACE_NW4A2": null, + "INT_INTERFACE_NW4A3": null, + "INT_INTERFACE_NW4END0": null, + "INT_INTERFACE_NW4END1": null, + "INT_INTERFACE_NW4END2": null, + "INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_PHASER_TO_IO_ICLK": null, + "INT_INTERFACE_PHASER_TO_IO_ICLKDIV": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK": null, + "INT_INTERFACE_PHASER_TO_IO_OCLK1X_90": null, + "INT_INTERFACE_PHASER_TO_IO_OCLKDIV": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + "INT_INTERFACE_SW4END3": null, + "INT_INTERFACE_WL1END0": null, + "INT_INTERFACE_WL1END1": null, + "INT_INTERFACE_WL1END2": null, + "INT_INTERFACE_WL1END3": null, + "INT_INTERFACE_WR1END0": null, + "INT_INTERFACE_WR1END1": null, + "INT_INTERFACE_WR1END2": null, + "INT_INTERFACE_WR1END3": null, + "INT_INTERFACE_WW2A0": null, + "INT_INTERFACE_WW2A1": null, + "INT_INTERFACE_WW2A2": null, + "INT_INTERFACE_WW2A3": null, + "INT_INTERFACE_WW2END0": null, + "INT_INTERFACE_WW2END1": null, + "INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "L_INT_INTER_DQS_IOTOPHASER": null + } } diff --git a/kintex7/tile_type_LIOB33.json b/kintex7/tile_type_LIOB33.json index a0960b5..98d5117 100644 --- a/kintex7/tile_type_LIOB33.json +++ b/kintex7/tile_type_LIOB33.json @@ -2,72 +2,212 @@ "pips": { "LIOB33.IOB_DIFFO_IN1->>IOB_PADOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOB_PADOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOB_DIFFO_IN1" }, "LIOB33.IOB_DIFFO_OUT0->IOB_DIFFO_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_DIFFO_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_DIFFO_OUT0" }, "LIOB33.IOB_O0->>IOB_O_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOB_O_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOB_O0" }, "LIOB33.IOB_O_OUT0->IOB_O_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_O_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_O_OUT0" }, "LIOB33.IOB_PADOUT0->IOB_DIFFI_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_DIFFI_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT0" }, "LIOB33.IOB_PADOUT0->LIOB_MONITOR_P": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOB_MONITOR_P", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT0" }, "LIOB33.IOB_PADOUT1->IOB_DIFFI_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_DIFFI_IN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT1" }, "LIOB33.IOB_PADOUT1->LIOB_MONITOR_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOB_MONITOR_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT1" }, "LIOB33.IOB_T0->>IOB_T_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOB_T_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOB_T0" }, "LIOB33.IOB_T_OUT0->IOB_T_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_T_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_T_OUT0" } }, @@ -76,23 +216,176 @@ "name": "X0Y0", "prefix": "IOB", "site_pins": { - "DIFFI_IN": "IOB_DIFFI_IN1", - "DIFFO_IN": "IOB_DIFFO_IN1", - "DIFFO_OUT": "IOB_DIFFO_OUT1", - "DIFF_TERM_INT_EN": "IOB_DIFF_TERM_INT_EN", - "I": "IOB_IBUF1", - "IBUFDISABLE": "IOB_IBUF_DISABLE1", - "INTERMDISABLE": "LIOB_IN_TERM1", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_0", - "O": "IOB_O1", - "O_IN": "IOB_O_IN1", - "O_OUT": "IOB_O_OUT1", - "PADOUT": "IOB_PADOUT1", - "PD_INT_EN": "IOB_PD_INT_EN_0", - "PU_INT_EN": "IOB_PU_INT_EN_0", - "T": "IOB_T1", - "T_IN": "IOB_T_IN1", - "T_OUT": "IOB_T_OUT1" + "DIFFI_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFFI_IN1" + }, + "DIFFO_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFFO_IN1" + }, + "DIFFO_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_DIFFO_OUT1" + }, + "DIFF_TERM_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFF_TERM_INT_EN" + }, + "I": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_IBUF1" + }, + "IBUFDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_IBUF_DISABLE1" + }, + "INTERMDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOB_IN_TERM1" + }, + "KEEPER_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_KEEPER_INT_EN_0" + }, + "O": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_O1" + }, + "O_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_O_IN1" + }, + "O_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_O_OUT1" + }, + "PADOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_PADOUT1" + }, + "PD_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PD_INT_EN_0" + }, + "PU_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PU_INT_EN_0" + }, + "T": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_T1" + }, + "T_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_T_IN1" + }, + "T_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_T_OUT1" + } }, "type": "IOB33S", "x_coord": 0, @@ -102,23 +395,140 @@ "name": "X0Y1", "prefix": "IOB", "site_pins": { - "DIFFI_IN": "IOB_DIFFI_IN0", + "DIFFI_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFFI_IN0" + }, "DIFFO_IN": null, - "DIFFO_OUT": "IOB_DIFFO_OUT0", + "DIFFO_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_DIFFO_OUT0" + }, "DIFF_TERM_INT_EN": null, - "I": "IOB_IBUF0", - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "INTERMDISABLE": "LIOB_IN_TERM0", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "O": "IOB_O0", + "I": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_IBUF0" + }, + "IBUFDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_IBUF_DISABLE0" + }, + "INTERMDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOB_IN_TERM0" + }, + "KEEPER_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_KEEPER_INT_EN_1" + }, + "O": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_O0" + }, "O_IN": null, - "O_OUT": "IOB_O_OUT0", - "PADOUT": "IOB_PADOUT0", - "PD_INT_EN": "IOB_PD_INT_EN_1", - "PU_INT_EN": "IOB_PU_INT_EN_1", - "T": "IOB_T0", + "O_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_O_OUT0" + }, + "PADOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_PADOUT0" + }, + "PD_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PD_INT_EN_1" + }, + "PU_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PU_INT_EN_1" + }, + "T": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_T0" + }, "T_IN": null, - "T_OUT": "IOB_T_OUT0" + "T_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_T_OUT0" + } }, "type": "IOB33M", "x_coord": 0, @@ -126,290 +536,1034 @@ } ], "tile_type": "LIOB33", - "wires": [ - "IOB_DIFFI_IN0", - "IOB_DIFFI_IN1", - "IOB_DIFFO_IN0", - "IOB_DIFFO_IN1", - "IOB_DIFFO_OUT0", - "IOB_DIFFO_OUT1", - "IOB_DIFF_TERM_INT_EN", - "IOB_DIFF_TERM_INT_EN_STUB", - "IOB_IBUF0", - "IOB_IBUF1", - "IOB_IBUF_DISABLE0", - "IOB_IBUF_DISABLE1", - "IOB_KEEPER_INT_EN_0", - "IOB_KEEPER_INT_EN_1", - "IOB_O0", - "IOB_O1", - "IOB_O_IN0", - "IOB_O_IN1", - "IOB_O_OUT0", - "IOB_O_OUT1", - "IOB_PADOUT0", - "IOB_PADOUT1", - "IOB_PD_INT_EN_0", - "IOB_PD_INT_EN_1", - "IOB_PU_INT_EN_0", - "IOB_PU_INT_EN_1", - "IOB_T0", - "IOB_T1", - "IOB_T_IN0", - "IOB_T_IN1", - "IOB_T_OUT0", - "IOB_T_OUT1", - "LIOB_EE2A0_0", - "LIOB_EE2A0_1", - "LIOB_EE2A1_0", - "LIOB_EE2A1_1", - "LIOB_EE2A2_0", - "LIOB_EE2A2_1", - "LIOB_EE2A3_0", - "LIOB_EE2A3_1", - "LIOB_EE2BEG0_0", - "LIOB_EE2BEG0_1", - "LIOB_EE2BEG1_0", - "LIOB_EE2BEG1_1", - "LIOB_EE2BEG2_0", - "LIOB_EE2BEG2_1", - "LIOB_EE2BEG3_0", - "LIOB_EE2BEG3_1", - "LIOB_EE4A0_0", - "LIOB_EE4A0_1", - "LIOB_EE4A1_0", - "LIOB_EE4A1_1", - "LIOB_EE4A2_0", - "LIOB_EE4A2_1", - "LIOB_EE4A3_0", - "LIOB_EE4A3_1", - "LIOB_EE4B0_0", - "LIOB_EE4B0_1", - "LIOB_EE4B1_0", - "LIOB_EE4B1_1", - "LIOB_EE4B2_0", - "LIOB_EE4B2_1", - "LIOB_EE4B3_0", - "LIOB_EE4B3_1", - "LIOB_EE4BEG0_0", - "LIOB_EE4BEG0_1", - "LIOB_EE4BEG1_0", - "LIOB_EE4BEG1_1", - "LIOB_EE4BEG2_0", - "LIOB_EE4BEG2_1", - "LIOB_EE4BEG3_0", - "LIOB_EE4BEG3_1", - "LIOB_EE4C0_0", - "LIOB_EE4C0_1", - "LIOB_EE4C1_0", - "LIOB_EE4C1_1", - "LIOB_EE4C2_0", - "LIOB_EE4C2_1", - "LIOB_EE4C3_0", - "LIOB_EE4C3_1", - "LIOB_EL1BEG0_0", - "LIOB_EL1BEG0_1", - "LIOB_EL1BEG1_0", - "LIOB_EL1BEG1_1", - "LIOB_EL1BEG2_0", - "LIOB_EL1BEG2_1", - "LIOB_EL1BEG3_0", - "LIOB_EL1BEG3_1", - "LIOB_ER1BEG0_0", - "LIOB_ER1BEG0_1", - "LIOB_ER1BEG1_0", - "LIOB_ER1BEG1_1", - "LIOB_ER1BEG2_0", - "LIOB_ER1BEG2_1", - "LIOB_ER1BEG3_0", - "LIOB_ER1BEG3_1", - "LIOB_IN_TERM0", - "LIOB_IN_TERM1", - "LIOB_LH10_0", - "LIOB_LH10_1", - "LIOB_LH11_0", - "LIOB_LH11_1", - "LIOB_LH12_0", - "LIOB_LH12_1", - "LIOB_LH1_0", - "LIOB_LH1_1", - "LIOB_LH2_0", - "LIOB_LH2_1", - "LIOB_LH3_0", - "LIOB_LH3_1", - "LIOB_LH4_0", - "LIOB_LH4_1", - "LIOB_LH5_0", - "LIOB_LH5_1", - "LIOB_LH6_0", - "LIOB_LH6_1", - "LIOB_LH7_0", - "LIOB_LH7_1", - "LIOB_LH8_0", - "LIOB_LH8_1", - "LIOB_LH9_0", - "LIOB_LH9_1", - "LIOB_MONITOR_N", - "LIOB_MONITOR_P", - "LIOB_NE2A0_0", - "LIOB_NE2A0_1", - "LIOB_NE2A1_0", - "LIOB_NE2A1_1", - "LIOB_NE2A2_0", - "LIOB_NE2A2_1", - "LIOB_NE2A3_0", - "LIOB_NE2A3_1", - "LIOB_NE4BEG0_0", - "LIOB_NE4BEG0_1", - "LIOB_NE4BEG1_0", - "LIOB_NE4BEG1_1", - "LIOB_NE4BEG2_0", - "LIOB_NE4BEG2_1", - "LIOB_NE4BEG3_0", - "LIOB_NE4BEG3_1", - "LIOB_NE4C0_0", - "LIOB_NE4C0_1", - "LIOB_NE4C1_0", - "LIOB_NE4C1_1", - "LIOB_NE4C2_0", - "LIOB_NE4C2_1", - "LIOB_NE4C3_0", - "LIOB_NE4C3_1", - "LIOB_NW2A0_0", - "LIOB_NW2A0_1", - "LIOB_NW2A1_0", - "LIOB_NW2A1_1", - "LIOB_NW2A2_0", - "LIOB_NW2A2_1", - "LIOB_NW2A3_0", - "LIOB_NW2A3_1", - "LIOB_NW4A0_0", - "LIOB_NW4A0_1", - "LIOB_NW4A1_0", - "LIOB_NW4A1_1", - "LIOB_NW4A2_0", - "LIOB_NW4A2_1", - "LIOB_NW4A3_0", - "LIOB_NW4A3_1", - "LIOB_NW4END0_0", - "LIOB_NW4END0_1", - "LIOB_NW4END1_0", - "LIOB_NW4END1_1", - "LIOB_NW4END2_0", - "LIOB_NW4END2_1", - "LIOB_NW4END3_0", - "LIOB_NW4END3_1", - "LIOB_SE2A0_0", - "LIOB_SE2A0_1", - "LIOB_SE2A1_0", - "LIOB_SE2A1_1", - "LIOB_SE2A2_0", - "LIOB_SE2A2_1", - "LIOB_SE2A3_0", - "LIOB_SE2A3_1", - "LIOB_SE4BEG0_0", - "LIOB_SE4BEG0_1", - "LIOB_SE4BEG1_0", - "LIOB_SE4BEG1_1", - "LIOB_SE4BEG2_0", - "LIOB_SE4BEG2_1", - "LIOB_SE4BEG3_0", - "LIOB_SE4BEG3_1", - "LIOB_SE4C0_0", - "LIOB_SE4C0_1", - "LIOB_SE4C1_0", - "LIOB_SE4C1_1", - "LIOB_SE4C2_0", - "LIOB_SE4C2_1", - "LIOB_SE4C3_0", - "LIOB_SE4C3_1", - "LIOB_SW2A0_0", - "LIOB_SW2A0_1", - "LIOB_SW2A1_0", - "LIOB_SW2A1_1", - "LIOB_SW2A2_0", - "LIOB_SW2A2_1", - "LIOB_SW2A3_0", - "LIOB_SW2A3_1", - "LIOB_SW4A0_0", - "LIOB_SW4A0_1", - "LIOB_SW4A1_0", - "LIOB_SW4A1_1", - "LIOB_SW4A2_0", - "LIOB_SW4A2_1", - "LIOB_SW4A3_0", - "LIOB_SW4A3_1", - "LIOB_SW4END0_0", - "LIOB_SW4END0_1", - "LIOB_SW4END1_0", - "LIOB_SW4END1_1", - "LIOB_SW4END2_0", - "LIOB_SW4END2_1", - "LIOB_SW4END3_0", - "LIOB_SW4END3_1", - "LIOB_WL1END0_0", - "LIOB_WL1END0_1", - "LIOB_WL1END1_0", - "LIOB_WL1END1_1", - "LIOB_WL1END2_0", - "LIOB_WL1END2_1", - "LIOB_WL1END3_0", - "LIOB_WL1END3_1", - "LIOB_WR1END0_0", - "LIOB_WR1END0_1", - "LIOB_WR1END1_0", - "LIOB_WR1END1_1", - "LIOB_WR1END2_0", - "LIOB_WR1END2_1", - "LIOB_WR1END3_0", - "LIOB_WR1END3_1", - "LIOB_WW2A0_0", - "LIOB_WW2A0_1", - "LIOB_WW2A1_0", - "LIOB_WW2A1_1", - "LIOB_WW2A2_0", - "LIOB_WW2A2_1", - "LIOB_WW2A3_0", - "LIOB_WW2A3_1", - "LIOB_WW2END0_0", - "LIOB_WW2END0_1", - "LIOB_WW2END1_0", - "LIOB_WW2END1_1", - "LIOB_WW2END2_0", - "LIOB_WW2END2_1", - "LIOB_WW2END3_0", - "LIOB_WW2END3_1", - "LIOB_WW4A0_0", - "LIOB_WW4A0_1", - "LIOB_WW4A1_0", - "LIOB_WW4A1_1", - "LIOB_WW4A2_0", - "LIOB_WW4A2_1", - "LIOB_WW4A3_0", - "LIOB_WW4A3_1", - "LIOB_WW4B0_0", - "LIOB_WW4B0_1", - "LIOB_WW4B1_0", - "LIOB_WW4B1_1", - "LIOB_WW4B2_0", - "LIOB_WW4B2_1", - "LIOB_WW4B3_0", - "LIOB_WW4B3_1", - "LIOB_WW4C0_0", - "LIOB_WW4C0_1", - "LIOB_WW4C1_0", - "LIOB_WW4C1_1", - "LIOB_WW4C2_0", - "LIOB_WW4C2_1", - "LIOB_WW4C3_0", - "LIOB_WW4C3_1", - "LIOB_WW4END0_0", - "LIOB_WW4END0_1", - "LIOB_WW4END1_0", - "LIOB_WW4END1_1", - "LIOB_WW4END2_0", - "LIOB_WW4END2_1", - "LIOB_WW4END3_0", - "LIOB_WW4END3_1" - ] + "wires": { + "IOB_DIFFI_IN0": null, + "IOB_DIFFI_IN1": null, + "IOB_DIFFO_IN0": null, + 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"208.000", + "res": "1024.400" + }, + "LIOB_WW4END3_1": { + "cap": "208.000", + "res": "1024.400" + } + } } diff --git a/kintex7/tile_type_LIOB33_SING.json b/kintex7/tile_type_LIOB33_SING.json index a66c04b..94aa3c9 100644 --- a/kintex7/tile_type_LIOB33_SING.json +++ b/kintex7/tile_type_LIOB33_SING.json @@ -7,21 +7,129 @@ "site_pins": { "DIFFI_IN": null, "DIFFO_IN": null, - "DIFFO_OUT": "IOB_DIFFO_OUT0", + "DIFFO_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_DIFFO_OUT0" + }, "DIFF_TERM_INT_EN": null, - "I": "IOB_IBUF0", - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "INTERMDISABLE": "LIOB_IN_TERM0", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "O": "IOB_O0", + "I": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_IBUF0" + }, + "IBUFDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_IBUF_DISABLE0" + }, + "INTERMDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOB_IN_TERM0" + }, + "KEEPER_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_KEEPER_INT_EN_1" + }, + "O": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_O0" + }, "O_IN": null, - "O_OUT": "IOB_O_OUT0", - "PADOUT": "IOB_PADOUT0", - "PD_INT_EN": "IOB_PD_INT_EN_1", - "PU_INT_EN": "IOB_PU_INT_EN_1", - "T": "IOB_T0", + "O_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_O_OUT0" + }, + "PADOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_PADOUT0" + }, + "PD_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PD_INT_EN_1" + }, + "PU_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PU_INT_EN_1" + }, + "T": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_T0" + }, "T_IN": null, - "T_OUT": "IOB_T_OUT0" + "T_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_T_OUT0" + } }, "type": "IOB33", "x_coord": 0, @@ -29,147 +137,519 @@ } ], "tile_type": "LIOB33_SING", - "wires": [ - "IOB_DIFFI_IN0", - "IOB_DIFFO_IN0", - "IOB_DIFFO_OUT0", - "IOB_DIFF_TERM_INT_EN_STUB", - "IOB_IBUF0", - "IOB_IBUF_DISABLE0", - "IOB_KEEPER_INT_EN_1", - "IOB_O0", - "IOB_O_IN0", - "IOB_O_OUT0", - "IOB_PADOUT0", - "IOB_PD_INT_EN_1", - "IOB_PU_INT_EN_1", - "IOB_T0", - "IOB_T_IN0", - "IOB_T_OUT0", - "LIOB_EE2A0_0", - "LIOB_EE2A1_0", - "LIOB_EE2A2_0", - "LIOB_EE2A3_0", - "LIOB_EE2BEG0_0", - "LIOB_EE2BEG1_0", - "LIOB_EE2BEG2_0", - "LIOB_EE2BEG3_0", - "LIOB_EE4A0_0", - "LIOB_EE4A1_0", - "LIOB_EE4A2_0", - "LIOB_EE4A3_0", - "LIOB_EE4B0_0", - "LIOB_EE4B1_0", - "LIOB_EE4B2_0", - "LIOB_EE4B3_0", - "LIOB_EE4BEG0_0", - "LIOB_EE4BEG1_0", - "LIOB_EE4BEG2_0", - "LIOB_EE4BEG3_0", - "LIOB_EE4C0_0", - "LIOB_EE4C1_0", - "LIOB_EE4C2_0", - "LIOB_EE4C3_0", - "LIOB_EL1BEG0_0", - "LIOB_EL1BEG1_0", - "LIOB_EL1BEG2_0", - "LIOB_EL1BEG3_0", - "LIOB_ER1BEG0_0", - "LIOB_ER1BEG1_0", - "LIOB_ER1BEG2_0", - "LIOB_ER1BEG3_0", - "LIOB_IN_TERM0", - "LIOB_LH10_0", - "LIOB_LH11_0", - "LIOB_LH12_0", - "LIOB_LH1_0", - "LIOB_LH2_0", - "LIOB_LH3_0", - "LIOB_LH4_0", - "LIOB_LH5_0", - "LIOB_LH6_0", - "LIOB_LH7_0", - "LIOB_LH8_0", - "LIOB_LH9_0", - "LIOB_NE2A0_0", - "LIOB_NE2A1_0", - "LIOB_NE2A2_0", - "LIOB_NE2A3_0", - "LIOB_NE4BEG0_0", - "LIOB_NE4BEG1_0", - "LIOB_NE4BEG2_0", - "LIOB_NE4BEG3_0", - "LIOB_NE4C0_0", - "LIOB_NE4C1_0", - "LIOB_NE4C2_0", - "LIOB_NE4C3_0", - "LIOB_NW2A0_0", - "LIOB_NW2A1_0", - "LIOB_NW2A2_0", - "LIOB_NW2A3_0", - "LIOB_NW4A0_0", - "LIOB_NW4A1_0", - "LIOB_NW4A2_0", - "LIOB_NW4A3_0", - "LIOB_NW4END0_0", - "LIOB_NW4END1_0", - "LIOB_NW4END2_0", - "LIOB_NW4END3_0", - "LIOB_SE2A0_0", - "LIOB_SE2A1_0", - "LIOB_SE2A2_0", - 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"LIOB_LH5_0": { + "cap": "194.420", + "res": "48.990" + }, + "LIOB_LH6_0": { + "cap": "194.420", + "res": "48.990" + }, + "LIOB_LH7_0": { + "cap": "194.420", + "res": "48.990" + }, + "LIOB_LH8_0": { + "cap": "194.420", + "res": "48.990" + }, + "LIOB_LH9_0": { + "cap": "194.420", + "res": "48.990" + }, + "LIOB_NE2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_NE2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_NE2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_NE2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_NE4BEG0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NE4BEG1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NE4BEG2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NE4BEG3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NE4C0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NE4C1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NE4C2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NE4C3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NW2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_NW2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_NW2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_NW2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_NW4A0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NW4A1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NW4A2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NW4A3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NW4END0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NW4END1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NW4END2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_NW4END3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SE2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_SE2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_SE2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_SE2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_SE4BEG0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SE4BEG1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SE4BEG2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SE4BEG3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SE4C0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SE4C1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SE4C2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SE4C3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SW2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_SW2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_SW2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_SW2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_SW4A0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SW4A1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SW4A2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SW4A3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SW4END0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SW4END1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SW4END2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_SW4END3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WL1END0_0": { + "cap": "201.000", + "res": "1024.400" + }, + "LIOB_WL1END1_0": { + "cap": "201.000", + "res": "1024.400" + }, + "LIOB_WL1END2_0": { + "cap": "201.000", + "res": "1024.400" + }, + "LIOB_WL1END3_0": { + "cap": "201.000", + "res": "1024.400" + }, + "LIOB_WR1END0_0": { + "cap": "201.000", + "res": "1024.400" + }, + "LIOB_WR1END1_0": { + "cap": "201.000", + "res": "1024.400" + }, + "LIOB_WR1END2_0": { + "cap": "201.000", + "res": "1024.400" + }, + "LIOB_WR1END3_0": { + "cap": "201.000", + "res": "1024.400" + }, + "LIOB_WW2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_WW2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_WW2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_WW2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_WW2END0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_WW2END1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_WW2END2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_WW2END3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "LIOB_WW4A0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4A1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4A2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4A3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4B0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4B1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4B2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4B3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4C0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4C1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4C2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4C3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4END0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4END1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4END2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "LIOB_WW4END3_0": { + "cap": "208.000", + "res": "1024.400" + } + } } diff --git a/kintex7/tile_type_LIOI3.json b/kintex7/tile_type_LIOI3.json index 4d45adc..f57e03a 100644 --- a/kintex7/tile_type_LIOI3.json +++ b/kintex7/tile_type_LIOI3.json @@ -2,2949 +2,10120 @@ "pips": { "LIOI3.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "LIOI3.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "LIOI3.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "LIOI3.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "LIOI3.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "LIOI3.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_1" }, "LIOI3.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY1_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "LIOI3.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_1" }, "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "LIOI3.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "LIOI3.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "LIOI3.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "LIOI3.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_1" }, "LIOI3.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "LIOI3.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_1" }, "LIOI3.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY1_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "LIOI3.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_1" }, "LIOI3.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY1_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "LIOI3.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_1" }, "LIOI3.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "LIOI3.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "LIOI3.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "LIOI3.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "LIOI3.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "LIOI3.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "LIOI3.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "LIOI3.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "LIOI3.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "LIOI3.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "LIOI3.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT" }, "LIOI3.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_OUTN1" }, "LIOI3.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_OUTN65" }, "LIOI3.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_RDY" }, "LIOI3.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT" }, "LIOI3.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "LIOI3.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_I2GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_O" }, "LIOI3.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "LIOI3.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "LIOI3.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "LIOI3.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "LIOI3.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "LIOI3.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "LIOI3.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "LIOI3.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "LIOI3.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC1_O" }, "LIOI3.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q1" }, "LIOI3.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q2" }, "LIOI3.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q3" }, "LIOI3.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q4" }, "LIOI3.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q5" }, "LIOI3.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q6" }, "LIOI3.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q7" }, "LIOI3.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q8" }, "LIOI3.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "LIOI3.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_1" }, "LIOI3.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "LIOI3.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_1" }, "LIOI3.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "LIOI3.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_1" }, "LIOI3.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "LIOI3.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_1" }, "LIOI3.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "LIOI3.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_1" }, "LIOI3.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "LIOI3.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_1" }, "LIOI3.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "LIOI3.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_1" }, "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "LIOI3.IOI_IMUX21_0->IOI_OLOGIC1_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "LIOI3.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_1" }, "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "LIOI3.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAYCTRL_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX24_0" }, "LIOI3.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "LIOI3.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_1" }, "LIOI3.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "LIOI3.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_1" }, "LIOI3.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "LIOI3.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_1" }, "LIOI3.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "LIOI3.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_1" }, "LIOI3.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "LIOI3.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "LIOI3.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "LIOI3.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "LIOI3.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "LIOI3.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_1" }, "LIOI3.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "LIOI3.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_1" }, "LIOI3.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "LIOI3.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_1" }, "LIOI3.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "LIOI3.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_1" }, "LIOI3.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "LIOI3.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_1" }, "LIOI3.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "LIOI3.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_1" }, "LIOI3.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "LIOI3.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_1" }, "LIOI3.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "LIOI3.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_1" }, "LIOI3.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "LIOI3.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_1" }, "LIOI3.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "LIOI3.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_1" }, "LIOI3.IOI_IMUX42_0->IOI_OLOGIC1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "LIOI3.IOI_IMUX42_1->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_1" }, "LIOI3.IOI_IMUX43_0->IOI_OLOGIC1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "LIOI3.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_1" }, "LIOI3.IOI_IMUX44_0->IOI_OLOGIC1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "LIOI3.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_1" }, "LIOI3.IOI_IMUX45_0->IOI_OLOGIC1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "LIOI3.IOI_IMUX45_1->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_1" }, "LIOI3.IOI_IMUX46_0->IOI_OLOGIC1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "LIOI3.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_1" }, "LIOI3.IOI_IMUX47_0->IOI_OLOGIC1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "LIOI3.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_1" }, "LIOI3.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "LIOI3.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_1" }, "LIOI3.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "LIOI3.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_1" }, "LIOI3.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_DCI_T_TERM1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "LIOI3.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_1" }, "LIOI3.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "LIOI3.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_1" }, "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IBUF_DISABLE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "LIOI3.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_1" }, "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3.IOI_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3.IOI_IOCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3.IOI_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3.IOI_IOCLK1->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3.IOI_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3.IOI_IOCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3.IOI_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3.IOI_IOCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3.IOI_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + 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"0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + 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"0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, 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"0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", 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"0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, 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"0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "LIOI3.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "LIOI3.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "LIOI3.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "LIOI3.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC1_IOCLKGLITCH" }, "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "LIOI3.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "LIOI3.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0" }, "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + 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"0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO0" }, "LIOI3.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", 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"1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_TBYTEIN" }, "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_TBYTEIN" }, "LIOI3.LIOI_I0->LIOI_IDELAY0_IDATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IDELAY0_IDATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I0" }, "LIOI3.LIOI_I0->LIOI_ILOGIC0_D": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_D", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I0" }, "LIOI3.LIOI_I1->LIOI_IDELAY1_IDATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IDELAY1_IDATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I1" }, "LIOI3.LIOI_I1->LIOI_ILOGIC1_D": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC1_D", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I1" }, "LIOI3.LIOI_IBUF0->LIOI_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_IBUF0" }, "LIOI3.LIOI_IBUF1->LIOI_I1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_I1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_IBUF1" }, "LIOI3.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_IDELAY0_DATAOUT" }, "LIOI3.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.264", + "0.331", + "0.575", + "0.666" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_IDELAY0_DATAOUT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.264", + "0.331", + "0.575", + "0.666" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_IDELAY0_IDATAIN" }, "LIOI3.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC1_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_IDELAY1_DATAOUT" }, "LIOI3.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.264", + "0.331", + "0.575", + "0.666" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_IDELAY1_DATAOUT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.264", + "0.331", + "0.575", + "0.666" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_IDELAY1_IDATAIN" }, "LIOI3.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC0_D" }, "LIOI3.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC0_DDLY" }, "LIOI3.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC1_D" }, "LIOI3.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC1_DDLY" }, "LIOI3.LIOI_ISOUT10->LIOI_ISIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ISIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_ISOUT10" }, "LIOI3.LIOI_ISOUT20->LIOI_ISIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ISIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_ISOUT20" }, "LIOI3.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_OFB" }, "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_O0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_OQ" }, "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_OQ" }, "LIOI3.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB" }, "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" }, "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" }, "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_TQ" }, "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_TQ" }, "LIOI3.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_OFB" }, "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_O1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_OQ" }, "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_OQ" }, "LIOI3.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_TFB" }, "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_TFB_LOCAL" }, "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_TFB_LOCAL" }, "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_TQ" }, "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_T1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_T1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_TQ" }, "LIOI3.LIOI_OSOUT11->LIOI_OSIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OSIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OSOUT11" }, "LIOI3.LIOI_OSOUT21->LIOI_OSIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OSIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OSOUT21" } }, @@ -2953,39 +10124,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC1_CLK", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "D1": "IOI_OLOGIC1_D1", - "D2": "IOI_OLOGIC1_D2", - "D3": "IOI_OLOGIC1_D3", - "D4": "IOI_OLOGIC1_D4", - "D5": "IOI_OLOGIC1_D5", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "OCE": "IOI_OLOGIC1_OCE", - "OFB": "LIOI_OLOGIC1_OFB", - "OQ": "LIOI_OLOGIC1_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "LIOI_OSOUT11", - "SHIFTOUT2": "LIOI_OSOUT21", - "SR": "IOI_OLOGIC1_SR", - "T1": "IOI_OLOGIC1_T1", - "T2": "IOI_OLOGIC1_T2", - "T3": "IOI_OLOGIC1_T3", - "T4": "IOI_OLOGIC1_T4", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TCE": "IOI_OLOGIC1_TCE", - "TFB": "LIOI_OLOGIC1_TFB", - "TQ": "LIOI_OLOGIC1_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -2995,37 +10436,307 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "CE1": "IOI_ILOGIC1_CE1", - "CE2": "IOI_ILOGIC1_CE2", - "CLK": "IOI_ILOGIC1_CLK", - "CLKB": "IOI_ILOGIC1_CLKB", - "CLKDIV": "IOI_ILOGIC1_CLKDIV", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "D": "LIOI_ILOGIC1_D", - "DDLY": "LIOI_ILOGIC1_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "O": "IOI_ILOGIC1_O", - "OCLK": "IOI_ILOGIC1_OCLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "OFB": "LIOI_ILOGIC1_OFB", - "Q1": "IOI_ILOGIC1_Q1", - "Q2": "IOI_ILOGIC1_Q2", - "Q3": "IOI_ILOGIC1_Q3", - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q6": "IOI_ILOGIC1_Q6", - "Q7": "IOI_ILOGIC1_Q7", - "Q8": "IOI_ILOGIC1_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC1_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q8" + }, "REV": null, - "SHIFTIN1": "LIOI_ISIN11", - "SHIFTIN2": "LIOI_ISIN21", - "SHIFTOUT1": "LIOI_ISOUT11", - "SHIFTOUT2": "LIOI_ISOUT21", - "SR": "IOI_ILOGIC1_SR", - "TFB": "LIOI_ILOGIC1_TFB" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ISIN11" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ISIN21" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3035,39 +10746,327 @@ "name": "X0Y1", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "LIOI_OLOGIC0_OFB", - "OQ": "LIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_OQ" + }, "REV": null, - "SHIFTIN1": "LIOI_OSIN10", - "SHIFTIN2": "LIOI_OSIN20", - "SHIFTOUT1": "LIOI_OSOUT10", - "SHIFTOUT2": "LIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "LIOI_OLOGIC0_TFB", - "TQ": "LIOI_OLOGIC0_TQ" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OSIN10" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OSIN20" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -3077,37 +11076,289 @@ "name": "X0Y1", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "LIOI_ILOGIC0_D", - "DDLY": "LIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "LIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "LIOI_ISOUT10", - "SHIFTOUT2": "LIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "LIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3117,29 +11368,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY1_C", - "CE": "IOI_IDELAY1_CE", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY1_DATAIN", - "DATAOUT": "LIOI_IDELAY1_DATAOUT", - "IDATAIN": "LIOI_IDELAY1_IDATAIN", - "IFDLY0": "LIOI3_IDELAY1_IFDLY0", - "IFDLY1": "LIOI3_IDELAY1_IFDLY1", - "IFDLY2": "LIOI3_IDELAY1_IFDLY2", - "INC": "IOI_IDELAY1_INC", - "LD": "IOI_IDELAY1_LD", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "REGRST": "IOI_IDELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_IDELAY1_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_IDELAY1_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY1_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY1_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY1_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3149,29 +11607,236 @@ "name": "X0Y1", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "LIOI_IDELAY0_DATAOUT", - "IDATAIN": "LIOI_IDELAY0_IDATAIN", - "IFDLY0": "LIOI3_IDELAY0_IFDLY0", - "IFDLY1": "LIOI3_IDELAY0_IFDLY1", - "IFDLY2": "LIOI3_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3179,750 +11844,750 @@ } ], "tile_type": "LIOI3", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS0_1", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS1_1", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS2_1", - "IOI_BLOCK_OUTS3_0", - "IOI_BLOCK_OUTS3_1", - "IOI_BYP0_0", - "IOI_BYP0_1", - "IOI_BYP1_0", - "IOI_BYP1_1", - "IOI_BYP2_0", - "IOI_BYP2_1", - "IOI_BYP3_0", - "IOI_BYP3_1", - "IOI_BYP4_0", - "IOI_BYP4_1", - "IOI_BYP5_0", - "IOI_BYP5_1", - "IOI_BYP6_0", - "IOI_BYP6_1", - "IOI_BYP7_0", - "IOI_BYP7_1", - "IOI_CLK0_0", - "IOI_CLK0_1", - "IOI_CLK1_0", - "IOI_CLK1_1", - "IOI_CTRL0_0", - "IOI_CTRL0_1", - "IOI_CTRL1_0", - "IOI_CTRL1_1", - "IOI_DCI_DCIDONE", - "IOI_DCI_TSTCLK", - "IOI_DCI_TSTHLN", - "IOI_DCI_TSTHLP", - "IOI_DCI_TSTRST", - "IOI_DCI_TSTRST0", - "IOI_EE2A0_0", - "IOI_EE2A0_1", - "IOI_EE2A1_0", - "IOI_EE2A1_1", - "IOI_EE2A2_0", - "IOI_EE2A2_1", - "IOI_EE2A3_0", - "IOI_EE2A3_1", - "IOI_EE2BEG0_0", - "IOI_EE2BEG0_1", - "IOI_EE2BEG1_0", - "IOI_EE2BEG1_1", - "IOI_EE2BEG2_0", - "IOI_EE2BEG2_1", - "IOI_EE2BEG3_0", - "IOI_EE2BEG3_1", - "IOI_EE4A0_0", - "IOI_EE4A0_1", - "IOI_EE4A1_0", - "IOI_EE4A1_1", - "IOI_EE4A2_0", - "IOI_EE4A2_1", - "IOI_EE4A3_0", - "IOI_EE4A3_1", - "IOI_EE4B0_0", - "IOI_EE4B0_1", - "IOI_EE4B1_0", - "IOI_EE4B1_1", - "IOI_EE4B2_0", - "IOI_EE4B2_1", - "IOI_EE4B3_0", - "IOI_EE4B3_1", - "IOI_EE4BEG0_0", - "IOI_EE4BEG0_1", - "IOI_EE4BEG1_0", - "IOI_EE4BEG1_1", - "IOI_EE4BEG2_0", - "IOI_EE4BEG2_1", - "IOI_EE4BEG3_0", - "IOI_EE4BEG3_1", - "IOI_EE4C0_0", - "IOI_EE4C0_1", - "IOI_EE4C1_0", - "IOI_EE4C1_1", - "IOI_EE4C2_0", - "IOI_EE4C2_1", - "IOI_EE4C3_0", - "IOI_EE4C3_1", - "IOI_EL1BEG0_0", - "IOI_EL1BEG0_1", - "IOI_EL1BEG1_0", - "IOI_EL1BEG1_1", - "IOI_EL1BEG2_0", - "IOI_EL1BEG2_1", - "IOI_EL1BEG3_0", - "IOI_EL1BEG3_1", - "IOI_ER1BEG0_0", - "IOI_ER1BEG0_1", - "IOI_ER1BEG1_0", - "IOI_ER1BEG1_1", - "IOI_ER1BEG2_0", - "IOI_ER1BEG2_1", - "IOI_ER1BEG3_0", - "IOI_ER1BEG3_1", - "IOI_FAN0_0", - "IOI_FAN0_1", - "IOI_FAN1_0", - "IOI_FAN1_1", - "IOI_FAN2_0", - "IOI_FAN2_1", - "IOI_FAN3_0", - "IOI_FAN3_1", - "IOI_FAN4_0", - "IOI_FAN4_1", - "IOI_FAN5_0", - "IOI_FAN5_1", - "IOI_FAN6_0", - "IOI_FAN6_1", - "IOI_FAN7_0", - "IOI_FAN7_1", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY1_C", - "IOI_IDELAY1_CE", - "IOI_IDELAY1_CINVCTRL", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT0", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_IDELAY1_DATAIN", - "IOI_IDELAY1_INC", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_LDPIPEEN", - "IOI_IDELAY1_REGRST", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC1_BITSLIP", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC1_CE2", - "IOI_ILOGIC1_CLK", - "IOI_ILOGIC1_CLKB", - "IOI_ILOGIC1_CLKDIV", - "IOI_ILOGIC1_CLKDIVP", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_ILOGIC1_O", - "IOI_ILOGIC1_OCLK", - "IOI_ILOGIC1_OCLKB", - "IOI_ILOGIC1_Q1", - "IOI_ILOGIC1_Q2", - "IOI_ILOGIC1_Q3", - "IOI_ILOGIC1_Q4", - "IOI_ILOGIC1_Q5", - "IOI_ILOGIC1_Q6", - "IOI_ILOGIC1_Q7", - "IOI_ILOGIC1_Q8", - "IOI_ILOGIC1_REV", - "IOI_ILOGIC1_SR", - "IOI_IMUX0_0", - "IOI_IMUX0_1", - "IOI_IMUX10_0", - "IOI_IMUX10_1", - "IOI_IMUX11_0", - "IOI_IMUX11_1", - "IOI_IMUX12_0", - "IOI_IMUX12_1", - "IOI_IMUX13_0", - "IOI_IMUX13_1", - "IOI_IMUX14_0", - "IOI_IMUX14_1", - "IOI_IMUX15_0", - "IOI_IMUX15_1", - "IOI_IMUX16_0", - "IOI_IMUX16_1", - "IOI_IMUX17_0", - "IOI_IMUX17_1", - "IOI_IMUX18_0", - "IOI_IMUX18_1", - "IOI_IMUX19_0", - "IOI_IMUX19_1", - "IOI_IMUX1_0", - "IOI_IMUX1_1", - "IOI_IMUX20_0", - "IOI_IMUX20_1", - "IOI_IMUX21_0", - "IOI_IMUX21_1", - "IOI_IMUX22_0", - "IOI_IMUX22_1", - "IOI_IMUX23_0", - "IOI_IMUX23_1", - "IOI_IMUX24_0", - "IOI_IMUX24_1", - "IOI_IMUX25_0", - "IOI_IMUX25_1", - "IOI_IMUX26_0", - "IOI_IMUX26_1", - "IOI_IMUX27_0", - "IOI_IMUX27_1", - "IOI_IMUX28_0", - "IOI_IMUX28_1", - "IOI_IMUX29_0", - "IOI_IMUX29_1", - "IOI_IMUX2_0", - "IOI_IMUX2_1", - "IOI_IMUX30_0", - "IOI_IMUX30_1", - "IOI_IMUX31_0", - "IOI_IMUX31_1", - "IOI_IMUX32_0", - "IOI_IMUX32_1", - "IOI_IMUX33_0", - "IOI_IMUX33_1", - "IOI_IMUX34_0", - "IOI_IMUX34_1", - "IOI_IMUX35_0", - "IOI_IMUX35_1", - "IOI_IMUX36_0", - "IOI_IMUX36_1", - "IOI_IMUX37_0", - "IOI_IMUX37_1", - "IOI_IMUX38_0", - "IOI_IMUX38_1", - "IOI_IMUX39_0", - "IOI_IMUX39_1", - "IOI_IMUX3_0", - "IOI_IMUX3_1", - "IOI_IMUX40_0", - "IOI_IMUX40_1", - "IOI_IMUX41_0", - "IOI_IMUX41_1", - "IOI_IMUX42_0", - "IOI_IMUX42_1", - "IOI_IMUX43_0", - "IOI_IMUX43_1", - "IOI_IMUX44_0", - "IOI_IMUX44_1", - "IOI_IMUX45_0", - "IOI_IMUX45_1", - "IOI_IMUX46_0", - "IOI_IMUX46_1", - "IOI_IMUX47_0", - "IOI_IMUX47_1", - "IOI_IMUX4_0", - "IOI_IMUX4_1", - "IOI_IMUX5_0", - "IOI_IMUX5_1", - "IOI_IMUX6_0", - "IOI_IMUX6_1", - "IOI_IMUX7_0", - "IOI_IMUX7_1", - "IOI_IMUX8_0", - "IOI_IMUX8_1", - "IOI_IMUX9_0", - "IOI_IMUX9_1", - "IOI_IMUX_RC0", - "IOI_IMUX_RC1", - "IOI_IMUX_RC2", - "IOI_IMUX_RC3", - "IOI_INT_DCI_EN", - "IOI_IOCLK0", - "IOI_IOCLK1", - "IOI_IOCLK2", - "IOI_IOCLK3", - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK5", - "IOI_LH10_0", - "IOI_LH10_1", - "IOI_LH11_0", - "IOI_LH11_1", - "IOI_LH12_0", - "IOI_LH12_1", - "IOI_LH1_0", - "IOI_LH1_1", - "IOI_LH2_0", - "IOI_LH2_1", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_LH4_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_LH5_1", - "IOI_LH6_0", - "IOI_LH6_1", - "IOI_LH7_0", - "IOI_LH7_1", - "IOI_LH8_0", - "IOI_LH8_1", - "IOI_LH9_0", - "IOI_LH9_1", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS10_1", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS11_1", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS12_1", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS13_1", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS14_1", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS15_1", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS16_1", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS17_1", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS18_1", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS1_1", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS20_1", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS21_1", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS22_1", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS23_1", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS2_1", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS3_1", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS4_1", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS5_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS6_1", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS7_1", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS9_0", - "IOI_LOGIC_OUTS9_1", - "IOI_MONITOR_N", - "IOI_MONITOR_P", - "IOI_NE2A0_0", - "IOI_NE2A0_1", - "IOI_NE2A1_0", - "IOI_NE2A1_1", - "IOI_NE2A2_0", - "IOI_NE2A2_1", - "IOI_NE2A3_0", - "IOI_NE2A3_1", - "IOI_NE4BEG0_0", - "IOI_NE4BEG0_1", - "IOI_NE4BEG1_0", - "IOI_NE4BEG1_1", - "IOI_NE4BEG2_0", - "IOI_NE4BEG2_1", - "IOI_NE4BEG3_0", - "IOI_NE4BEG3_1", - "IOI_NE4C0_0", - "IOI_NE4C0_1", - "IOI_NE4C1_0", - "IOI_NE4C1_1", - "IOI_NE4C2_0", - "IOI_NE4C2_1", - "IOI_NE4C3_0", - "IOI_NE4C3_1", - "IOI_NW2A0_0", - "IOI_NW2A0_1", - "IOI_NW2A1_0", - "IOI_NW2A1_1", - "IOI_NW2A2_0", - "IOI_NW2A2_1", - "IOI_NW2A3_0", - "IOI_NW2A3_1", - "IOI_NW4A0_0", - "IOI_NW4A0_1", - "IOI_NW4A1_0", - "IOI_NW4A1_1", - "IOI_NW4A2_0", - "IOI_NW4A2_1", - "IOI_NW4A3_0", - "IOI_NW4A3_1", - "IOI_NW4END0_0", - "IOI_NW4END0_1", - "IOI_NW4END1_0", - "IOI_NW4END1_1", - "IOI_NW4END2_0", - "IOI_NW4END2_1", - "IOI_NW4END3_0", - "IOI_NW4END3_1", - "IOI_OCLKM_0", - "IOI_OCLKM_1", - "IOI_OCLK_0", - "IOI_OCLK_1", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_ODELAY1_C", - "IOI_ODELAY1_CE", - "IOI_ODELAY1_CINVCTRL", - "IOI_ODELAY1_CLKIN", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_ODELAY1_INC", - "IOI_ODELAY1_LD", - "IOI_ODELAY1_LDPIPEEN", - "IOI_ODELAY1_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_CLK", - "IOI_OLOGIC1_CLKB", - "IOI_OLOGIC1_CLKDIV", - "IOI_OLOGIC1_CLKDIVB", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_OLOGIC1_D1", - "IOI_OLOGIC1_D2", - "IOI_OLOGIC1_D3", - "IOI_OLOGIC1_D4", - "IOI_OLOGIC1_D5", - "IOI_OLOGIC1_D6", - "IOI_OLOGIC1_D7", - "IOI_OLOGIC1_D8", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_OLOGIC1_OCE", - "IOI_OLOGIC1_REV", - "IOI_OLOGIC1_SR", - "IOI_OLOGIC1_T1", - "IOI_OLOGIC1_T2", - "IOI_OLOGIC1_T3", - "IOI_OLOGIC1_T4", - "IOI_OLOGIC1_TBYTEIN", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_OLOGIC1_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR3", - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO3", - "IOI_SE2A0_0", - "IOI_SE2A0_1", - "IOI_SE2A1_0", - "IOI_SE2A1_1", - "IOI_SE2A2_0", - "IOI_SE2A2_1", - "IOI_SE2A3_0", - "IOI_SE2A3_1", - "IOI_SE4BEG0_0", - "IOI_SE4BEG0_1", - "IOI_SE4BEG1_0", - "IOI_SE4BEG1_1", - "IOI_SE4BEG2_0", - "IOI_SE4BEG2_1", - "IOI_SE4BEG3_0", - "IOI_SE4BEG3_1", - "IOI_SE4C0_0", - "IOI_SE4C0_1", - "IOI_SE4C1_0", - "IOI_SE4C1_1", - "IOI_SE4C2_0", - "IOI_SE4C2_1", - "IOI_SE4C3_0", - "IOI_SE4C3_1", - "IOI_SW2A0_0", - "IOI_SW2A0_1", - "IOI_SW2A1_0", - "IOI_SW2A1_1", - "IOI_SW2A2_0", - "IOI_SW2A2_1", - "IOI_SW2A3_0", - "IOI_SW2A3_1", - "IOI_SW4A0_0", - "IOI_SW4A0_1", - "IOI_SW4A1_0", - "IOI_SW4A1_1", - "IOI_SW4A2_0", - "IOI_SW4A2_1", - "IOI_SW4A3_0", - "IOI_SW4A3_1", - "IOI_SW4END0_0", - "IOI_SW4END0_1", - "IOI_SW4END1_0", - "IOI_SW4END1_1", - "IOI_SW4END2_0", - "IOI_SW4END2_1", - "IOI_SW4END3_0", - "IOI_SW4END3_1", - "IOI_TBYTEIN", - "IOI_WL1END0_0", - "IOI_WL1END0_1", - "IOI_WL1END1_0", - "IOI_WL1END1_1", - "IOI_WL1END2_0", - "IOI_WL1END2_1", - "IOI_WL1END3_0", - "IOI_WL1END3_1", - "IOI_WR1END0_0", - "IOI_WR1END0_1", - "IOI_WR1END1_0", - "IOI_WR1END1_1", - "IOI_WR1END2_0", - "IOI_WR1END2_1", - "IOI_WR1END3_0", - "IOI_WR1END3_1", - "IOI_WW2A0_0", - "IOI_WW2A0_1", - "IOI_WW2A1_0", - "IOI_WW2A1_1", - "IOI_WW2A2_0", - "IOI_WW2A2_1", - "IOI_WW2A3_0", - "IOI_WW2A3_1", - "IOI_WW2END0_0", - "IOI_WW2END0_1", - "IOI_WW2END1_0", - "IOI_WW2END1_1", - "IOI_WW2END2_0", - "IOI_WW2END2_1", - "IOI_WW2END3_0", - "IOI_WW2END3_1", - "IOI_WW4A0_0", - "IOI_WW4A0_1", - "IOI_WW4A1_0", - "IOI_WW4A1_1", - "IOI_WW4A2_0", - "IOI_WW4A2_1", - "IOI_WW4A3_0", - "IOI_WW4A3_1", - "IOI_WW4B0_0", - "IOI_WW4B0_1", - "IOI_WW4B1_0", - "IOI_WW4B1_1", - "IOI_WW4B2_0", - "IOI_WW4B2_1", - "IOI_WW4B3_0", - "IOI_WW4B3_1", - "IOI_WW4C0_0", - "IOI_WW4C0_1", - "IOI_WW4C1_0", - "IOI_WW4C1_1", - "IOI_WW4C2_0", - "IOI_WW4C2_1", - "IOI_WW4C3_0", - "IOI_WW4C3_1", - "IOI_WW4END0_0", - "IOI_WW4END0_1", - "IOI_WW4END1_0", - "IOI_WW4END1_1", - "IOI_WW4END2_0", - "IOI_WW4END2_1", - "IOI_WW4END3_0", - "IOI_WW4END3_1", - "LIOI3_IDELAY0_IFDLY0", - "LIOI3_IDELAY0_IFDLY1", - "LIOI3_IDELAY0_IFDLY2", - "LIOI3_IDELAY1_IFDLY0", - "LIOI3_IDELAY1_IFDLY1", - "LIOI3_IDELAY1_IFDLY2", - "LIOI_DCI_T_TERM0", - "LIOI_DCI_T_TERM1", - "LIOI_DIFF_TERM_INT_EN", - "LIOI_I0", - "LIOI_I1", - "LIOI_I2GCLK_BOT1", - "LIOI_I2GCLK_TOP0", - "LIOI_I2GCLK_TOP1", - "LIOI_IBUF0", - "LIOI_IBUF1", - "LIOI_IBUF_DISABLE0", - "LIOI_IBUF_DISABLE1", - "LIOI_IDELAY0_DATAOUT", - "LIOI_IDELAY0_IDATAIN", - "LIOI_IDELAY1_DATAOUT", - "LIOI_IDELAY1_IDATAIN", - "LIOI_ILOGIC0_D", - "LIOI_ILOGIC0_DDLY", - "LIOI_ILOGIC0_OFB", - "LIOI_ILOGIC0_TFB", - "LIOI_ILOGIC1_D", - "LIOI_ILOGIC1_DDLY", - "LIOI_ILOGIC1_OFB", - "LIOI_ILOGIC1_TFB", - "LIOI_ISIN10", - "LIOI_ISIN11", - "LIOI_ISIN20", - "LIOI_ISIN21", - "LIOI_ISOUT10", - "LIOI_ISOUT11", - "LIOI_ISOUT20", - "LIOI_ISOUT21", - "LIOI_KEEPER_INT_EN_0", - "LIOI_KEEPER_INT_EN_1", - "LIOI_O0", - "LIOI_O1", - "LIOI_ODELAY0_DATAOUT", - "LIOI_ODELAY0_ODATAIN", - "LIOI_ODELAY0_OFDLY0", - "LIOI_ODELAY0_OFDLY1", - "LIOI_ODELAY0_OFDLY2", - "LIOI_ODELAY1_DATAOUT", - "LIOI_ODELAY1_ODATAIN", - "LIOI_ODELAY1_OFDLY0", - "LIOI_ODELAY1_OFDLY1", - "LIOI_ODELAY1_OFDLY2", - "LIOI_OLOGIC0_CLKDIVF", - "LIOI_OLOGIC0_OFB", - "LIOI_OLOGIC0_OQ", - "LIOI_OLOGIC0_TFB", - "LIOI_OLOGIC0_TFB_LOCAL", - "LIOI_OLOGIC0_TQ", - "LIOI_OLOGIC1_CLKDIVF", - "LIOI_OLOGIC1_OFB", - "LIOI_OLOGIC1_OQ", - "LIOI_OLOGIC1_TFB", - "LIOI_OLOGIC1_TFB_LOCAL", - "LIOI_OLOGIC1_TQ", - "LIOI_OSIN10", - "LIOI_OSIN11", - "LIOI_OSIN20", - "LIOI_OSIN21", - "LIOI_OSOUT10", - "LIOI_OSOUT11", - "LIOI_OSOUT20", - "LIOI_OSOUT21", - "LIOI_PD_INT_EN_0", - "LIOI_PD_INT_EN_1", - "LIOI_PU_INT_EN_0", - "LIOI_PU_INT_EN_1", - "LIOI_T0", - "LIOI_T1" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS0_1": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS1_1": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS2_1": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BLOCK_OUTS3_1": null, + "IOI_BYP0_0": null, + "IOI_BYP0_1": null, + "IOI_BYP1_0": null, + "IOI_BYP1_1": null, + "IOI_BYP2_0": null, + "IOI_BYP2_1": null, + "IOI_BYP3_0": null, + "IOI_BYP3_1": null, + "IOI_BYP4_0": null, + "IOI_BYP4_1": null, + "IOI_BYP5_0": null, + "IOI_BYP5_1": null, + "IOI_BYP6_0": null, + "IOI_BYP6_1": null, + "IOI_BYP7_0": null, + "IOI_BYP7_1": null, + "IOI_CLK0_0": null, + "IOI_CLK0_1": null, + "IOI_CLK1_0": null, + "IOI_CLK1_1": null, + "IOI_CTRL0_0": null, + "IOI_CTRL0_1": null, + "IOI_CTRL1_0": null, + "IOI_CTRL1_1": null, + "IOI_DCI_DCIDONE": null, + "IOI_DCI_TSTCLK": null, + "IOI_DCI_TSTHLN": null, + "IOI_DCI_TSTHLP": null, + "IOI_DCI_TSTRST": null, + "IOI_DCI_TSTRST0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A0_1": null, + "IOI_EE2A1_0": null, + "IOI_EE2A1_1": null, + "IOI_EE2A2_0": null, + "IOI_EE2A2_1": null, + "IOI_EE2A3_0": null, + "IOI_EE2A3_1": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG0_1": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG1_1": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG2_1": null, + "IOI_EE2BEG3_0": null, + "IOI_EE2BEG3_1": null, + "IOI_EE4A0_0": null, + "IOI_EE4A0_1": null, + "IOI_EE4A1_0": null, + "IOI_EE4A1_1": null, + "IOI_EE4A2_0": null, + "IOI_EE4A2_1": null, + "IOI_EE4A3_0": null, + "IOI_EE4A3_1": null, + "IOI_EE4B0_0": null, + "IOI_EE4B0_1": null, + "IOI_EE4B1_0": null, + "IOI_EE4B1_1": null, + "IOI_EE4B2_0": null, + "IOI_EE4B2_1": null, + "IOI_EE4B3_0": null, + "IOI_EE4B3_1": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG0_1": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG1_1": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG2_1": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4BEG3_1": null, + "IOI_EE4C0_0": null, + "IOI_EE4C0_1": null, + "IOI_EE4C1_0": null, + "IOI_EE4C1_1": null, + "IOI_EE4C2_0": null, + "IOI_EE4C2_1": null, + "IOI_EE4C3_0": null, + "IOI_EE4C3_1": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG0_1": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG1_1": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG2_1": null, + "IOI_EL1BEG3_0": null, + "IOI_EL1BEG3_1": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG0_1": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG1_1": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG2_1": null, + "IOI_ER1BEG3_0": null, + "IOI_ER1BEG3_1": null, + "IOI_FAN0_0": null, + "IOI_FAN0_1": null, + "IOI_FAN1_0": null, + "IOI_FAN1_1": null, + "IOI_FAN2_0": null, + "IOI_FAN2_1": null, + "IOI_FAN3_0": null, + "IOI_FAN3_1": null, + "IOI_FAN4_0": null, + "IOI_FAN4_1": null, + "IOI_FAN5_0": null, + "IOI_FAN5_1": null, + "IOI_FAN6_0": null, + "IOI_FAN6_1": null, + "IOI_FAN7_0": null, + "IOI_FAN7_1": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_IDELAY1_C": null, + "IOI_IDELAY1_CE": null, + "IOI_IDELAY1_CINVCTRL": null, + "IOI_IDELAY1_CNTVALUEIN0": null, + "IOI_IDELAY1_CNTVALUEIN1": null, + "IOI_IDELAY1_CNTVALUEIN2": null, + "IOI_IDELAY1_CNTVALUEIN3": null, + "IOI_IDELAY1_CNTVALUEIN4": null, + "IOI_IDELAY1_CNTVALUEOUT0": null, + "IOI_IDELAY1_CNTVALUEOUT1": null, + "IOI_IDELAY1_CNTVALUEOUT2": null, + "IOI_IDELAY1_CNTVALUEOUT3": null, + "IOI_IDELAY1_CNTVALUEOUT4": null, + "IOI_IDELAY1_DATAIN": null, + "IOI_IDELAY1_INC": null, + "IOI_IDELAY1_LD": null, + "IOI_IDELAY1_LDPIPEEN": null, + "IOI_IDELAY1_REGRST": null, + "IOI_IDELAYCTRL_DNPULSEOUT": null, + "IOI_IDELAYCTRL_OUTN1": null, + "IOI_IDELAYCTRL_OUTN65": null, + "IOI_IDELAYCTRL_RDY": null, + "IOI_IDELAYCTRL_RST": null, + "IOI_IDELAYCTRL_UPPULSEOUT": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_ILOGIC1_BITSLIP": null, + "IOI_ILOGIC1_CE1": null, + "IOI_ILOGIC1_CE2": null, + "IOI_ILOGIC1_CLK": null, + "IOI_ILOGIC1_CLKB": null, + "IOI_ILOGIC1_CLKDIV": null, + "IOI_ILOGIC1_CLKDIVP": null, + "IOI_ILOGIC1_DYNCLKDIVPSEL": null, + "IOI_ILOGIC1_DYNCLKDIVSEL": null, + "IOI_ILOGIC1_DYNCLKSEL": null, + "IOI_ILOGIC1_O": null, + "IOI_ILOGIC1_OCLK": null, + "IOI_ILOGIC1_OCLKB": null, + "IOI_ILOGIC1_Q1": null, + "IOI_ILOGIC1_Q2": null, + "IOI_ILOGIC1_Q3": null, + "IOI_ILOGIC1_Q4": null, + "IOI_ILOGIC1_Q5": null, + "IOI_ILOGIC1_Q6": null, + "IOI_ILOGIC1_Q7": null, + "IOI_ILOGIC1_Q8": null, + "IOI_ILOGIC1_REV": null, + "IOI_ILOGIC1_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX0_1": null, + "IOI_IMUX10_0": null, + "IOI_IMUX10_1": null, + "IOI_IMUX11_0": null, + "IOI_IMUX11_1": null, + "IOI_IMUX12_0": null, + "IOI_IMUX12_1": null, + "IOI_IMUX13_0": null, + "IOI_IMUX13_1": null, + "IOI_IMUX14_0": null, + "IOI_IMUX14_1": null, + "IOI_IMUX15_0": null, + "IOI_IMUX15_1": null, + "IOI_IMUX16_0": null, + "IOI_IMUX16_1": null, + "IOI_IMUX17_0": null, + "IOI_IMUX17_1": null, + "IOI_IMUX18_0": null, + "IOI_IMUX18_1": null, + "IOI_IMUX19_0": null, + "IOI_IMUX19_1": null, + "IOI_IMUX1_0": null, + "IOI_IMUX1_1": null, + "IOI_IMUX20_0": null, + "IOI_IMUX20_1": null, + "IOI_IMUX21_0": null, + "IOI_IMUX21_1": null, + "IOI_IMUX22_0": null, + "IOI_IMUX22_1": null, + "IOI_IMUX23_0": null, + "IOI_IMUX23_1": null, + "IOI_IMUX24_0": null, + "IOI_IMUX24_1": null, + "IOI_IMUX25_0": null, + "IOI_IMUX25_1": null, + "IOI_IMUX26_0": null, + "IOI_IMUX26_1": null, + "IOI_IMUX27_0": null, + "IOI_IMUX27_1": null, + "IOI_IMUX28_0": null, + "IOI_IMUX28_1": null, + "IOI_IMUX29_0": null, + "IOI_IMUX29_1": null, + "IOI_IMUX2_0": null, + "IOI_IMUX2_1": null, + "IOI_IMUX30_0": null, + "IOI_IMUX30_1": null, + "IOI_IMUX31_0": null, + "IOI_IMUX31_1": null, + "IOI_IMUX32_0": null, + "IOI_IMUX32_1": null, + "IOI_IMUX33_0": null, + "IOI_IMUX33_1": null, + "IOI_IMUX34_0": null, + "IOI_IMUX34_1": null, + "IOI_IMUX35_0": null, + "IOI_IMUX35_1": null, + "IOI_IMUX36_0": null, + "IOI_IMUX36_1": null, + "IOI_IMUX37_0": null, + "IOI_IMUX37_1": null, + "IOI_IMUX38_0": null, + "IOI_IMUX38_1": null, + "IOI_IMUX39_0": null, + "IOI_IMUX39_1": null, + "IOI_IMUX3_0": null, + "IOI_IMUX3_1": null, + "IOI_IMUX40_0": null, + "IOI_IMUX40_1": null, + "IOI_IMUX41_0": null, + "IOI_IMUX41_1": null, + "IOI_IMUX42_0": null, + "IOI_IMUX42_1": null, + "IOI_IMUX43_0": null, + "IOI_IMUX43_1": null, + "IOI_IMUX44_0": null, + "IOI_IMUX44_1": null, + "IOI_IMUX45_0": null, + "IOI_IMUX45_1": null, + "IOI_IMUX46_0": null, + "IOI_IMUX46_1": null, + "IOI_IMUX47_0": null, + "IOI_IMUX47_1": null, + "IOI_IMUX4_0": null, + "IOI_IMUX4_1": null, + "IOI_IMUX5_0": null, + "IOI_IMUX5_1": null, + "IOI_IMUX6_0": null, + "IOI_IMUX6_1": null, + "IOI_IMUX7_0": null, + "IOI_IMUX7_1": null, + "IOI_IMUX8_0": null, + "IOI_IMUX8_1": null, + "IOI_IMUX9_0": null, + "IOI_IMUX9_1": null, + "IOI_IMUX_RC0": null, + "IOI_IMUX_RC1": null, + "IOI_IMUX_RC2": null, + "IOI_IMUX_RC3": null, + "IOI_INT_DCI_EN": null, + "IOI_IOCLK0": null, + "IOI_IOCLK1": null, + "IOI_IOCLK2": null, + "IOI_IOCLK3": null, + "IOI_LEAF_GCLK0": null, + "IOI_LEAF_GCLK1": null, + "IOI_LEAF_GCLK2": null, + "IOI_LEAF_GCLK3": null, + "IOI_LEAF_GCLK4": null, + "IOI_LEAF_GCLK5": null, + "IOI_LH10_0": null, + "IOI_LH10_1": null, + "IOI_LH11_0": null, + "IOI_LH11_1": null, + "IOI_LH12_0": null, + "IOI_LH12_1": null, + "IOI_LH1_0": null, + "IOI_LH1_1": null, + "IOI_LH2_0": null, + "IOI_LH2_1": null, + "IOI_LH3_0": null, + "IOI_LH3_1": null, + "IOI_LH4_0": null, + "IOI_LH4_1": null, + "IOI_LH5_0": null, + "IOI_LH5_1": null, + "IOI_LH6_0": null, + "IOI_LH6_1": null, + "IOI_LH7_0": null, + "IOI_LH7_1": null, + "IOI_LH8_0": null, + "IOI_LH8_1": null, + "IOI_LH9_0": null, + "IOI_LH9_1": null, + "IOI_LOGIC_OUTS0_0": null, + "IOI_LOGIC_OUTS0_1": null, + "IOI_LOGIC_OUTS10_0": null, + "IOI_LOGIC_OUTS10_1": null, + "IOI_LOGIC_OUTS11_0": null, + "IOI_LOGIC_OUTS11_1": null, + "IOI_LOGIC_OUTS12_0": null, + "IOI_LOGIC_OUTS12_1": null, + "IOI_LOGIC_OUTS13_0": null, + "IOI_LOGIC_OUTS13_1": null, + "IOI_LOGIC_OUTS14_0": null, + "IOI_LOGIC_OUTS14_1": null, + "IOI_LOGIC_OUTS15_0": null, + "IOI_LOGIC_OUTS15_1": null, + "IOI_LOGIC_OUTS16_0": null, + "IOI_LOGIC_OUTS16_1": null, + "IOI_LOGIC_OUTS17_0": null, + "IOI_LOGIC_OUTS17_1": null, + "IOI_LOGIC_OUTS18_0": null, + "IOI_LOGIC_OUTS18_1": null, + "IOI_LOGIC_OUTS19_0": null, + "IOI_LOGIC_OUTS19_1": null, + "IOI_LOGIC_OUTS1_0": null, + "IOI_LOGIC_OUTS1_1": null, + "IOI_LOGIC_OUTS20_0": null, + "IOI_LOGIC_OUTS20_1": null, + "IOI_LOGIC_OUTS21_0": null, + "IOI_LOGIC_OUTS21_1": null, + "IOI_LOGIC_OUTS22_0": null, + "IOI_LOGIC_OUTS22_1": null, + "IOI_LOGIC_OUTS23_0": null, + "IOI_LOGIC_OUTS23_1": null, + "IOI_LOGIC_OUTS2_0": null, + "IOI_LOGIC_OUTS2_1": null, + "IOI_LOGIC_OUTS3_0": null, + "IOI_LOGIC_OUTS3_1": null, + "IOI_LOGIC_OUTS4_0": null, + "IOI_LOGIC_OUTS4_1": null, + "IOI_LOGIC_OUTS5_0": null, + "IOI_LOGIC_OUTS5_1": null, + "IOI_LOGIC_OUTS6_0": null, + "IOI_LOGIC_OUTS6_1": null, + "IOI_LOGIC_OUTS7_0": null, + "IOI_LOGIC_OUTS7_1": null, + "IOI_LOGIC_OUTS8_0": null, + "IOI_LOGIC_OUTS8_1": null, + "IOI_LOGIC_OUTS9_0": null, + "IOI_LOGIC_OUTS9_1": null, + "IOI_MONITOR_N": null, + "IOI_MONITOR_P": null, + "IOI_NE2A0_0": null, + "IOI_NE2A0_1": null, + "IOI_NE2A1_0": null, + "IOI_NE2A1_1": null, + "IOI_NE2A2_0": null, + "IOI_NE2A2_1": null, + "IOI_NE2A3_0": null, + "IOI_NE2A3_1": null, + "IOI_NE4BEG0_0": null, + "IOI_NE4BEG0_1": null, + "IOI_NE4BEG1_0": null, + "IOI_NE4BEG1_1": null, + "IOI_NE4BEG2_0": null, + "IOI_NE4BEG2_1": null, + "IOI_NE4BEG3_0": null, + "IOI_NE4BEG3_1": null, + "IOI_NE4C0_0": null, + "IOI_NE4C0_1": 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"IOI_ODELAY0_CNTVALUEIN2": null, + "IOI_ODELAY0_CNTVALUEIN3": null, + "IOI_ODELAY0_CNTVALUEIN4": null, + "IOI_ODELAY0_CNTVALUEOUT0": null, + "IOI_ODELAY0_CNTVALUEOUT1": null, + "IOI_ODELAY0_CNTVALUEOUT2": null, + "IOI_ODELAY0_CNTVALUEOUT3": null, + "IOI_ODELAY0_CNTVALUEOUT4": null, + "IOI_ODELAY0_INC": null, + "IOI_ODELAY0_LD": null, + "IOI_ODELAY0_LDPIPEEN": null, + "IOI_ODELAY0_REGRST": null, + "IOI_ODELAY1_C": null, + "IOI_ODELAY1_CE": null, + "IOI_ODELAY1_CINVCTRL": null, + "IOI_ODELAY1_CLKIN": null, + "IOI_ODELAY1_CNTVALUEIN0": null, + "IOI_ODELAY1_CNTVALUEIN1": null, + "IOI_ODELAY1_CNTVALUEIN2": null, + "IOI_ODELAY1_CNTVALUEIN3": null, + "IOI_ODELAY1_CNTVALUEIN4": null, + "IOI_ODELAY1_CNTVALUEOUT0": null, + "IOI_ODELAY1_CNTVALUEOUT1": null, + "IOI_ODELAY1_CNTVALUEOUT2": null, + "IOI_ODELAY1_CNTVALUEOUT3": null, + "IOI_ODELAY1_CNTVALUEOUT4": null, + "IOI_ODELAY1_INC": null, + "IOI_ODELAY1_LD": null, + "IOI_ODELAY1_LDPIPEEN": null, + "IOI_ODELAY1_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_OLOGIC1_CLK": null, + "IOI_OLOGIC1_CLKB": null, + "IOI_OLOGIC1_CLKDIV": null, + "IOI_OLOGIC1_CLKDIVB": null, + "IOI_OLOGIC1_CLKDIVFB": null, + "IOI_OLOGIC1_D1": null, + "IOI_OLOGIC1_D2": null, + "IOI_OLOGIC1_D3": null, + "IOI_OLOGIC1_D4": null, + "IOI_OLOGIC1_D5": null, + "IOI_OLOGIC1_D6": null, + "IOI_OLOGIC1_D7": null, + "IOI_OLOGIC1_D8": null, + "IOI_OLOGIC1_IOCLKGLITCH": null, + "IOI_OLOGIC1_OCE": null, + "IOI_OLOGIC1_REV": null, + "IOI_OLOGIC1_SR": null, + "IOI_OLOGIC1_T1": null, + "IOI_OLOGIC1_T2": null, + "IOI_OLOGIC1_T3": null, + "IOI_OLOGIC1_T4": null, + "IOI_OLOGIC1_TBYTEIN": null, + "IOI_OLOGIC1_TBYTEOUT": null, + "IOI_OLOGIC1_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_ICLKDIV_0": null, + "IOI_PHASER_TO_IO_ICLK_0": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLK1X_90_0": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_PHASER_TO_IO_OCLKDIV_0": null, + "IOI_PHASER_TO_IO_OCLK_0": null, + "IOI_RCLK_DIV_CE0": null, + "IOI_RCLK_DIV_CE1": null, + "IOI_RCLK_DIV_CE2": null, + "IOI_RCLK_DIV_CE2_1": null, + "IOI_RCLK_DIV_CE3": null, + "IOI_RCLK_DIV_CE3_1": null, + "IOI_RCLK_DIV_CLR0": null, + "IOI_RCLK_DIV_CLR0_1": null, + "IOI_RCLK_DIV_CLR1": null, + "IOI_RCLK_DIV_CLR1_1": null, + "IOI_RCLK_DIV_CLR2": null, + "IOI_RCLK_DIV_CLR3": null, + "IOI_RCLK_FORIO0": null, + "IOI_RCLK_FORIO1": null, + "IOI_RCLK_FORIO2": null, + "IOI_RCLK_FORIO3": null, + "IOI_SE2A0_0": null, + "IOI_SE2A0_1": null, + "IOI_SE2A1_0": null, + "IOI_SE2A1_1": null, + "IOI_SE2A2_0": null, + "IOI_SE2A2_1": null, + "IOI_SE2A3_0": null, + "IOI_SE2A3_1": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG0_1": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG1_1": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG2_1": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4BEG3_1": null, + "IOI_SE4C0_0": null, + "IOI_SE4C0_1": null, + "IOI_SE4C1_0": null, + "IOI_SE4C1_1": null, + "IOI_SE4C2_0": null, + "IOI_SE4C2_1": null, + "IOI_SE4C3_0": null, + "IOI_SE4C3_1": null, + "IOI_SW2A0_0": null, + "IOI_SW2A0_1": null, + "IOI_SW2A1_0": null, + "IOI_SW2A1_1": null, + "IOI_SW2A2_0": null, + "IOI_SW2A2_1": null, + "IOI_SW2A3_0": null, + "IOI_SW2A3_1": null, + "IOI_SW4A0_0": null, + "IOI_SW4A0_1": null, + "IOI_SW4A1_0": null, + "IOI_SW4A1_1": null, + "IOI_SW4A2_0": null, + "IOI_SW4A2_1": null, + "IOI_SW4A3_0": null, + "IOI_SW4A3_1": null, + "IOI_SW4END0_0": null, + "IOI_SW4END0_1": null, + "IOI_SW4END1_0": null, + "IOI_SW4END1_1": null, + "IOI_SW4END2_0": null, + "IOI_SW4END2_1": null, + "IOI_SW4END3_0": null, + "IOI_SW4END3_1": null, + "IOI_TBYTEIN": null, + "IOI_WL1END0_0": null, + "IOI_WL1END0_1": null, + "IOI_WL1END1_0": null, + "IOI_WL1END1_1": null, + "IOI_WL1END2_0": null, + "IOI_WL1END2_1": null, + "IOI_WL1END3_0": null, + "IOI_WL1END3_1": null, + "IOI_WR1END0_0": null, + "IOI_WR1END0_1": null, + "IOI_WR1END1_0": null, + "IOI_WR1END1_1": null, + "IOI_WR1END2_0": null, + "IOI_WR1END2_1": null, + "IOI_WR1END3_0": null, + "IOI_WR1END3_1": null, + "IOI_WW2A0_0": null, + "IOI_WW2A0_1": null, + "IOI_WW2A1_0": null, + "IOI_WW2A1_1": null, + "IOI_WW2A2_0": null, + "IOI_WW2A2_1": null, + "IOI_WW2A3_0": null, + "IOI_WW2A3_1": null, + "IOI_WW2END0_0": null, + "IOI_WW2END0_1": null, + "IOI_WW2END1_0": null, + "IOI_WW2END1_1": null, + "IOI_WW2END2_0": null, + "IOI_WW2END2_1": null, + "IOI_WW2END3_0": null, + "IOI_WW2END3_1": null, + "IOI_WW4A0_0": null, + "IOI_WW4A0_1": null, + "IOI_WW4A1_0": null, + "IOI_WW4A1_1": null, + "IOI_WW4A2_0": null, + "IOI_WW4A2_1": null, + "IOI_WW4A3_0": null, + "IOI_WW4A3_1": null, + "IOI_WW4B0_0": null, + "IOI_WW4B0_1": null, + "IOI_WW4B1_0": null, + "IOI_WW4B1_1": null, + "IOI_WW4B2_0": null, + "IOI_WW4B2_1": null, + "IOI_WW4B3_0": null, + "IOI_WW4B3_1": null, + "IOI_WW4C0_0": null, + "IOI_WW4C0_1": null, + "IOI_WW4C1_0": null, + "IOI_WW4C1_1": null, + "IOI_WW4C2_0": null, + "IOI_WW4C2_1": null, + "IOI_WW4C3_0": null, + "IOI_WW4C3_1": null, + "IOI_WW4END0_0": null, + "IOI_WW4END0_1": null, + "IOI_WW4END1_0": null, + "IOI_WW4END1_1": null, + "IOI_WW4END2_0": null, + "IOI_WW4END2_1": null, + "IOI_WW4END3_0": null, + "IOI_WW4END3_1": null, + "LIOI3_IDELAY0_IFDLY0": null, + "LIOI3_IDELAY0_IFDLY1": null, + "LIOI3_IDELAY0_IFDLY2": null, + "LIOI3_IDELAY1_IFDLY0": null, + "LIOI3_IDELAY1_IFDLY1": null, + "LIOI3_IDELAY1_IFDLY2": null, + "LIOI_DCI_T_TERM0": null, + "LIOI_DCI_T_TERM1": null, + "LIOI_DIFF_TERM_INT_EN": null, + "LIOI_I0": null, + "LIOI_I1": null, + "LIOI_I2GCLK_BOT1": null, + "LIOI_I2GCLK_TOP0": null, + "LIOI_I2GCLK_TOP1": null, + "LIOI_IBUF0": null, + "LIOI_IBUF1": null, + "LIOI_IBUF_DISABLE0": null, + "LIOI_IBUF_DISABLE1": null, + "LIOI_IDELAY0_DATAOUT": null, + "LIOI_IDELAY0_IDATAIN": null, + "LIOI_IDELAY1_DATAOUT": null, + "LIOI_IDELAY1_IDATAIN": null, + "LIOI_ILOGIC0_D": null, + "LIOI_ILOGIC0_DDLY": null, + "LIOI_ILOGIC0_OFB": null, + "LIOI_ILOGIC0_TFB": null, + "LIOI_ILOGIC1_D": null, + "LIOI_ILOGIC1_DDLY": null, + "LIOI_ILOGIC1_OFB": null, + "LIOI_ILOGIC1_TFB": null, + "LIOI_ISIN10": null, + "LIOI_ISIN11": null, + "LIOI_ISIN20": null, + "LIOI_ISIN21": null, + "LIOI_ISOUT10": null, + "LIOI_ISOUT11": null, + "LIOI_ISOUT20": null, + "LIOI_ISOUT21": null, + "LIOI_KEEPER_INT_EN_0": null, + "LIOI_KEEPER_INT_EN_1": null, + "LIOI_O0": null, + "LIOI_O1": null, + "LIOI_ODELAY0_DATAOUT": null, + "LIOI_ODELAY0_ODATAIN": null, + "LIOI_ODELAY0_OFDLY0": null, + "LIOI_ODELAY0_OFDLY1": null, + "LIOI_ODELAY0_OFDLY2": null, + "LIOI_ODELAY1_DATAOUT": null, + "LIOI_ODELAY1_ODATAIN": null, + "LIOI_ODELAY1_OFDLY0": null, + "LIOI_ODELAY1_OFDLY1": null, + "LIOI_ODELAY1_OFDLY2": null, + "LIOI_OLOGIC0_CLKDIVF": null, + "LIOI_OLOGIC0_OFB": null, + "LIOI_OLOGIC0_OQ": null, + "LIOI_OLOGIC0_TFB": null, + "LIOI_OLOGIC0_TFB_LOCAL": null, + "LIOI_OLOGIC0_TQ": null, + "LIOI_OLOGIC1_CLKDIVF": null, + "LIOI_OLOGIC1_OFB": null, + "LIOI_OLOGIC1_OQ": null, + "LIOI_OLOGIC1_TFB": null, + "LIOI_OLOGIC1_TFB_LOCAL": null, + "LIOI_OLOGIC1_TQ": null, + "LIOI_OSIN10": null, + "LIOI_OSIN11": null, + "LIOI_OSIN20": null, + "LIOI_OSIN21": null, + "LIOI_OSOUT10": null, + "LIOI_OSOUT11": null, + "LIOI_OSOUT20": null, + "LIOI_OSOUT21": null, + "LIOI_PD_INT_EN_0": null, + "LIOI_PD_INT_EN_1": null, + "LIOI_PU_INT_EN_0": null, + "LIOI_PU_INT_EN_1": null, + "LIOI_T0": null, + "LIOI_T1": null + } } diff --git a/kintex7/tile_type_LIOI3_SING.json b/kintex7/tile_type_LIOI3_SING.json index 459376a..3020a75 100644 --- a/kintex7/tile_type_LIOI3_SING.json +++ b/kintex7/tile_type_LIOI3_SING.json @@ -2,1395 +2,4854 @@ "pips": { "LIOI3_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "LIOI3_SING.IOI_BYP7_0->LIOI3_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "LIOI3_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "LIOI3_SING.IOI_CLK1_0->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "LIOI3_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "LIOI3_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "LIOI3_SING.IOI_FAN4_0->LIOI3_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "LIOI3_SING.IOI_FAN5_0->LIOI3_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "LIOI3_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "LIOI3_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "LIOI3_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "LIOI3_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "LIOI3_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "LIOI3_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "LIOI3_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "LIOI3_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "LIOI3_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "LIOI3_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "LIOI3_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "LIOI3_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "LIOI3_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "LIOI3_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "LIOI3_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "LIOI3_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "LIOI3_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "LIOI3_SING.IOI_IMUX26_0->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "LIOI3_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "LIOI3_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "LIOI3_SING.IOI_IMUX31_0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_SING.IOI_IMUX31_0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "LIOI3_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "LIOI3_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "LIOI3_SING.IOI_IMUX35_0->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "LIOI3_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "LIOI3_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "LIOI3_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "LIOI3_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "LIOI3_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "LIOI3_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "LIOI3_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "LIOI3_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "LIOI3_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "LIOI3_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "LIOI3_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "LIOI3_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "LIOI3_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "LIOI3_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "LIOI3_SING.IOI_IMUX6_0->LIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "LIOI3_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_SING.IOI_IMUX8_0->LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_SING.IOI_IMUX9_0->LIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "LIOI3_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_SING.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_SING.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3_SING.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "LIOI3_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "LIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "LIOI3_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "LIOI3_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "LIOI3_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "LIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "LIOI3_SING.IOI_SING_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "LIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "LIOI3_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "LIOI3_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "LIOI3_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "LIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "LIOI3_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, 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"0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "LIOI3_SING.IOI_SING_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "LIOI3_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "LIOI3_SING.IOI_SING_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "LIOI3_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_TBYTEIN" }, "LIOI3_SING.LIOI_I0->LIOI_IDELAY0_IDATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IDELAY0_IDATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I0" }, "LIOI3_SING.LIOI_I0->LIOI_ILOGIC0_D": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_D", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I0" }, "LIOI3_SING.LIOI_IBUF0->LIOI_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_IBUF0" }, "LIOI3_SING.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_IDELAY0_DATAOUT" }, "LIOI3_SING.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.264", + "0.331", + "0.575", + "0.666" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_IDELAY0_DATAOUT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.264", + "0.331", + "0.575", + "0.666" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_IDELAY0_IDATAIN" }, "LIOI3_SING.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC0_D" }, "LIOI3_SING.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC0_DDLY" }, "LIOI3_SING.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_OFB" }, "LIOI3_SING.LIOI_OLOGIC0_OQ->>LIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_O0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_OQ" }, "LIOI3_SING.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_OQ" }, "LIOI3_SING.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB" }, "LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" }, "LIOI3_SING.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" }, "LIOI3_SING.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_TQ" }, "LIOI3_SING.LIOI_OLOGIC0_TQ->>LIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_TQ" } }, @@ -1399,39 +4858,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "LIOI_OLOGIC0_OFB", - "OQ": "LIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "LIOI_OSOUT10", - "SHIFTOUT2": "LIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "LIOI_OLOGIC0_TFB", - "TQ": "LIOI_OLOGIC0_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -1441,37 +5170,289 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "LIOI_ILOGIC0_D", - "DDLY": "LIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "LIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "LIOI_ISOUT10", - "SHIFTOUT2": "LIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "LIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -1481,29 +5462,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "LIOI_IDELAY0_DATAOUT", - "IDATAIN": "LIOI_IDELAY0_IDATAIN", - "IFDLY0": "LIOI3_IDELAY0_IFDLY0", - "IFDLY1": "LIOI3_IDELAY0_IFDLY1", - "IFDLY2": "LIOI3_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -1511,368 +5699,368 @@ } ], "tile_type": "LIOI3_SING", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS3_0", - "IOI_BYP0_0", - "IOI_BYP1_0", - "IOI_BYP2_0", - "IOI_BYP3_0", - "IOI_BYP4_0", - "IOI_BYP5_0", - "IOI_BYP6_0", - "IOI_BYP7_0", - "IOI_CLK0_0", - "IOI_CLK1_0", - "IOI_CTRL0_0", - "IOI_CTRL1_0", - "IOI_EE2A0_0", - "IOI_EE2A1_0", - "IOI_EE2A2_0", - "IOI_EE2A3_0", - "IOI_EE2BEG0_0", - "IOI_EE2BEG1_0", - "IOI_EE2BEG2_0", - "IOI_EE2BEG3_0", - "IOI_EE4A0_0", - "IOI_EE4A1_0", - "IOI_EE4A2_0", - "IOI_EE4A3_0", - "IOI_EE4B0_0", - "IOI_EE4B1_0", - "IOI_EE4B2_0", - "IOI_EE4B3_0", - "IOI_EE4BEG0_0", - "IOI_EE4BEG1_0", - "IOI_EE4BEG2_0", - "IOI_EE4BEG3_0", - "IOI_EE4C0_0", - "IOI_EE4C1_0", - "IOI_EE4C2_0", - "IOI_EE4C3_0", - "IOI_EL1BEG0_0", - "IOI_EL1BEG1_0", - "IOI_EL1BEG2_0", - "IOI_EL1BEG3_0", - "IOI_ER1BEG0_0", - "IOI_ER1BEG1_0", - "IOI_ER1BEG2_0", - "IOI_ER1BEG3_0", - "IOI_FAN0_0", - "IOI_FAN1_0", - "IOI_FAN2_0", - "IOI_FAN3_0", - "IOI_FAN4_0", - "IOI_FAN5_0", - "IOI_FAN6_0", - "IOI_FAN7_0", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_IMUX0_0", - "IOI_IMUX10_0", - "IOI_IMUX11_0", - "IOI_IMUX12_0", - "IOI_IMUX13_0", - "IOI_IMUX14_0", - "IOI_IMUX15_0", - "IOI_IMUX16_0", - "IOI_IMUX17_0", - "IOI_IMUX18_0", - "IOI_IMUX19_0", - "IOI_IMUX1_0", - "IOI_IMUX20_0", - "IOI_IMUX21_0", - "IOI_IMUX22_0", - "IOI_IMUX23_0", - "IOI_IMUX24_0", - "IOI_IMUX25_0", - "IOI_IMUX26_0", - "IOI_IMUX27_0", - "IOI_IMUX28_0", - "IOI_IMUX29_0", - "IOI_IMUX2_0", - "IOI_IMUX30_0", - "IOI_IMUX31_0", - "IOI_IMUX32_0", - "IOI_IMUX33_0", - "IOI_IMUX34_0", - "IOI_IMUX35_0", - "IOI_IMUX36_0", - "IOI_IMUX37_0", - "IOI_IMUX38_0", - "IOI_IMUX39_0", - "IOI_IMUX3_0", - "IOI_IMUX40_0", - "IOI_IMUX41_0", - "IOI_IMUX42_0", - "IOI_IMUX43_0", - "IOI_IMUX44_0", - "IOI_IMUX45_0", - "IOI_IMUX46_0", - "IOI_IMUX47_0", - "IOI_IMUX4_0", - "IOI_IMUX5_0", - "IOI_IMUX6_0", - "IOI_IMUX7_0", - "IOI_IMUX8_0", - "IOI_IMUX9_0", - "IOI_LH10_0", - "IOI_LH11_0", - "IOI_LH12_0", - "IOI_LH1_0", - "IOI_LH2_0", - "IOI_LH3_0", - "IOI_LH4_0", - "IOI_LH5_0", - "IOI_LH6_0", - "IOI_LH7_0", - "IOI_LH8_0", - "IOI_LH9_0", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS9_0", - "IOI_NE2A0_0", - "IOI_NE2A1_0", - "IOI_NE2A2_0", - "IOI_NE2A3_0", - "IOI_NE4BEG0_0", - "IOI_NE4BEG1_0", - "IOI_NE4BEG2_0", - "IOI_NE4BEG3_0", - "IOI_NE4C0_0", - "IOI_NE4C1_0", - "IOI_NE4C2_0", - "IOI_NE4C3_0", - "IOI_NW2A0_0", - "IOI_NW2A1_0", - "IOI_NW2A2_0", - "IOI_NW2A3_0", - "IOI_NW4A0_0", - "IOI_NW4A1_0", - "IOI_NW4A2_0", - "IOI_NW4A3_0", - "IOI_NW4END0_0", - "IOI_NW4END1_0", - "IOI_NW4END2_0", - "IOI_NW4END3_0", - "IOI_OCLKM_0", - "IOI_OCLK_0", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_SE2A0_0", - "IOI_SE2A1_0", - "IOI_SE2A2_0", - "IOI_SE2A3_0", - "IOI_SE4BEG0_0", - "IOI_SE4BEG1_0", - "IOI_SE4BEG2_0", - "IOI_SE4BEG3_0", - "IOI_SE4C0_0", - "IOI_SE4C1_0", - "IOI_SE4C2_0", - "IOI_SE4C3_0", - "IOI_SING_IOCLK0", - "IOI_SING_IOCLK1", - "IOI_SING_IOCLK2", - "IOI_SING_IOCLK3", - "IOI_SING_LEAF_GCLK0", - "IOI_SING_LEAF_GCLK1", - "IOI_SING_LEAF_GCLK2", - "IOI_SING_LEAF_GCLK3", - "IOI_SING_LEAF_GCLK4", - "IOI_SING_LEAF_GCLK5", - "IOI_SING_RCLK_FORIO0", - "IOI_SING_RCLK_FORIO1", - "IOI_SING_RCLK_FORIO2", - "IOI_SING_RCLK_FORIO3", - "IOI_SING_TBYTEIN", - "IOI_SW2A0_0", - "IOI_SW2A1_0", - "IOI_SW2A2_0", - "IOI_SW2A3_0", - "IOI_SW4A0_0", - "IOI_SW4A1_0", - "IOI_SW4A2_0", - "IOI_SW4A3_0", - "IOI_SW4END0_0", - "IOI_SW4END1_0", - "IOI_SW4END2_0", - "IOI_SW4END3_0", - "IOI_WL1END0_0", - "IOI_WL1END1_0", - "IOI_WL1END2_0", - "IOI_WL1END3_0", - "IOI_WR1END0_0", - "IOI_WR1END1_0", - "IOI_WR1END2_0", - "IOI_WR1END3_0", - "IOI_WW2A0_0", - "IOI_WW2A1_0", - "IOI_WW2A2_0", - "IOI_WW2A3_0", - "IOI_WW2END0_0", - "IOI_WW2END1_0", - "IOI_WW2END2_0", - "IOI_WW2END3_0", - "IOI_WW4A0_0", - "IOI_WW4A1_0", - "IOI_WW4A2_0", - "IOI_WW4A3_0", - "IOI_WW4B0_0", - "IOI_WW4B1_0", - "IOI_WW4B2_0", - "IOI_WW4B3_0", - "IOI_WW4C0_0", - "IOI_WW4C1_0", - "IOI_WW4C2_0", - "IOI_WW4C3_0", - "IOI_WW4END0_0", - "IOI_WW4END1_0", - "IOI_WW4END2_0", - "IOI_WW4END3_0", - "LIOI3_IDELAY0_IFDLY0", - "LIOI3_IDELAY0_IFDLY1", - "LIOI3_IDELAY0_IFDLY2", - "LIOI_DCI_T_TERM0", - "LIOI_I0", - "LIOI_IBUF0", - "LIOI_IBUF_DISABLE0", - "LIOI_IDELAY0_DATAOUT", - "LIOI_IDELAY0_IDATAIN", - "LIOI_ILOGIC0_D", - "LIOI_ILOGIC0_DDLY", - "LIOI_ILOGIC0_OFB", - "LIOI_ILOGIC0_TFB", - "LIOI_ISIN10", - "LIOI_ISIN20", - "LIOI_ISOUT10", - "LIOI_ISOUT20", - "LIOI_KEEPER_INT_EN_1", - "LIOI_O0", - "LIOI_ODELAY0_DATAOUT", - "LIOI_ODELAY0_ODATAIN", - "LIOI_ODELAY0_OFDLY0", - "LIOI_ODELAY0_OFDLY1", - "LIOI_ODELAY0_OFDLY2", - "LIOI_OLOGIC0_CLKDIVF", - "LIOI_OLOGIC0_OFB", - "LIOI_OLOGIC0_OQ", - "LIOI_OLOGIC0_TFB", - "LIOI_OLOGIC0_TFB_LOCAL", - "LIOI_OLOGIC0_TQ", - "LIOI_OSIN10", - "LIOI_OSIN20", - "LIOI_OSOUT10", - "LIOI_OSOUT20", - "LIOI_PD_INT_EN_1", - "LIOI_PU_INT_EN_1", - "LIOI_T0" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BYP0_0": null, + "IOI_BYP1_0": null, + "IOI_BYP2_0": null, + "IOI_BYP3_0": null, + "IOI_BYP4_0": null, + "IOI_BYP5_0": null, + "IOI_BYP6_0": null, + "IOI_BYP7_0": null, + "IOI_CLK0_0": null, + "IOI_CLK1_0": null, + "IOI_CTRL0_0": null, + "IOI_CTRL1_0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A1_0": null, + "IOI_EE2A2_0": null, + "IOI_EE2A3_0": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG3_0": null, + "IOI_EE4A0_0": null, + "IOI_EE4A1_0": null, + "IOI_EE4A2_0": null, + "IOI_EE4A3_0": null, + "IOI_EE4B0_0": null, + "IOI_EE4B1_0": null, + "IOI_EE4B2_0": null, + "IOI_EE4B3_0": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4C0_0": null, + "IOI_EE4C1_0": null, + "IOI_EE4C2_0": null, + "IOI_EE4C3_0": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG3_0": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG3_0": null, + "IOI_FAN0_0": null, + "IOI_FAN1_0": null, + "IOI_FAN2_0": null, + "IOI_FAN3_0": null, + "IOI_FAN4_0": null, + "IOI_FAN5_0": null, + "IOI_FAN6_0": null, + "IOI_FAN7_0": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX10_0": null, + "IOI_IMUX11_0": null, + "IOI_IMUX12_0": null, + "IOI_IMUX13_0": null, + "IOI_IMUX14_0": null, + "IOI_IMUX15_0": null, + "IOI_IMUX16_0": null, + "IOI_IMUX17_0": null, + "IOI_IMUX18_0": null, + "IOI_IMUX19_0": null, + "IOI_IMUX1_0": null, + "IOI_IMUX20_0": null, + "IOI_IMUX21_0": null, + "IOI_IMUX22_0": null, + "IOI_IMUX23_0": null, + "IOI_IMUX24_0": null, + "IOI_IMUX25_0": null, + "IOI_IMUX26_0": null, + "IOI_IMUX27_0": null, + "IOI_IMUX28_0": null, + "IOI_IMUX29_0": null, + "IOI_IMUX2_0": null, + "IOI_IMUX30_0": null, + "IOI_IMUX31_0": null, + "IOI_IMUX32_0": null, + "IOI_IMUX33_0": null, + "IOI_IMUX34_0": null, + "IOI_IMUX35_0": null, + "IOI_IMUX36_0": null, + "IOI_IMUX37_0": null, + "IOI_IMUX38_0": null, + "IOI_IMUX39_0": null, + "IOI_IMUX3_0": null, + "IOI_IMUX40_0": null, + "IOI_IMUX41_0": null, + "IOI_IMUX42_0": null, + "IOI_IMUX43_0": null, + "IOI_IMUX44_0": null, + "IOI_IMUX45_0": null, + "IOI_IMUX46_0": null, + "IOI_IMUX47_0": null, + "IOI_IMUX4_0": null, + "IOI_IMUX5_0": null, + "IOI_IMUX6_0": null, + "IOI_IMUX7_0": null, + "IOI_IMUX8_0": null, + "IOI_IMUX9_0": null, + "IOI_LH10_0": null, + "IOI_LH11_0": null, + "IOI_LH12_0": null, + "IOI_LH1_0": null, + "IOI_LH2_0": null, + "IOI_LH3_0": null, + "IOI_LH4_0": null, + "IOI_LH5_0": null, + "IOI_LH6_0": null, + "IOI_LH7_0": null, + "IOI_LH8_0": null, + "IOI_LH9_0": null, + "IOI_LOGIC_OUTS0_0": null, + "IOI_LOGIC_OUTS10_0": null, + "IOI_LOGIC_OUTS11_0": null, + "IOI_LOGIC_OUTS12_0": null, + "IOI_LOGIC_OUTS13_0": null, + "IOI_LOGIC_OUTS14_0": null, + "IOI_LOGIC_OUTS15_0": null, + "IOI_LOGIC_OUTS16_0": null, + "IOI_LOGIC_OUTS17_0": null, + "IOI_LOGIC_OUTS18_0": null, + "IOI_LOGIC_OUTS19_0": null, + "IOI_LOGIC_OUTS1_0": null, + "IOI_LOGIC_OUTS20_0": null, + "IOI_LOGIC_OUTS21_0": null, + "IOI_LOGIC_OUTS22_0": null, + "IOI_LOGIC_OUTS23_0": null, + "IOI_LOGIC_OUTS2_0": null, + "IOI_LOGIC_OUTS3_0": null, + "IOI_LOGIC_OUTS4_0": null, + "IOI_LOGIC_OUTS5_0": null, + "IOI_LOGIC_OUTS6_0": null, + "IOI_LOGIC_OUTS7_0": null, + "IOI_LOGIC_OUTS8_0": null, + "IOI_LOGIC_OUTS9_0": null, + "IOI_NE2A0_0": null, + "IOI_NE2A1_0": null, + "IOI_NE2A2_0": null, + "IOI_NE2A3_0": null, + "IOI_NE4BEG0_0": null, + "IOI_NE4BEG1_0": null, + "IOI_NE4BEG2_0": null, + "IOI_NE4BEG3_0": null, + "IOI_NE4C0_0": null, + "IOI_NE4C1_0": null, + "IOI_NE4C2_0": null, + "IOI_NE4C3_0": null, + "IOI_NW2A0_0": null, + "IOI_NW2A1_0": null, + "IOI_NW2A2_0": null, + "IOI_NW2A3_0": null, + "IOI_NW4A0_0": null, + "IOI_NW4A1_0": null, + "IOI_NW4A2_0": null, + "IOI_NW4A3_0": null, + "IOI_NW4END0_0": null, + "IOI_NW4END1_0": null, + "IOI_NW4END2_0": null, + "IOI_NW4END3_0": null, + "IOI_OCLKM_0": null, + "IOI_OCLK_0": null, + "IOI_ODELAY0_C": null, + "IOI_ODELAY0_CE": null, + "IOI_ODELAY0_CINVCTRL": null, + "IOI_ODELAY0_CLKIN": null, + "IOI_ODELAY0_CNTVALUEIN0": null, + "IOI_ODELAY0_CNTVALUEIN1": null, + "IOI_ODELAY0_CNTVALUEIN2": null, + "IOI_ODELAY0_CNTVALUEIN3": null, + "IOI_ODELAY0_CNTVALUEIN4": null, + "IOI_ODELAY0_CNTVALUEOUT0": null, + "IOI_ODELAY0_CNTVALUEOUT1": null, + "IOI_ODELAY0_CNTVALUEOUT2": null, + "IOI_ODELAY0_CNTVALUEOUT3": null, + "IOI_ODELAY0_CNTVALUEOUT4": null, + "IOI_ODELAY0_INC": null, + "IOI_ODELAY0_LD": null, + "IOI_ODELAY0_LDPIPEEN": null, + "IOI_ODELAY0_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_SE2A0_0": null, + "IOI_SE2A1_0": null, + "IOI_SE2A2_0": null, + "IOI_SE2A3_0": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4C0_0": null, + "IOI_SE4C1_0": null, + "IOI_SE4C2_0": null, + "IOI_SE4C3_0": null, + "IOI_SING_IOCLK0": null, + "IOI_SING_IOCLK1": null, + "IOI_SING_IOCLK2": null, + "IOI_SING_IOCLK3": null, + "IOI_SING_LEAF_GCLK0": null, + "IOI_SING_LEAF_GCLK1": null, + "IOI_SING_LEAF_GCLK2": null, + "IOI_SING_LEAF_GCLK3": null, + "IOI_SING_LEAF_GCLK4": null, + "IOI_SING_LEAF_GCLK5": null, + "IOI_SING_RCLK_FORIO0": null, + "IOI_SING_RCLK_FORIO1": null, + "IOI_SING_RCLK_FORIO2": null, + "IOI_SING_RCLK_FORIO3": null, + "IOI_SING_TBYTEIN": null, + "IOI_SW2A0_0": null, + "IOI_SW2A1_0": null, + "IOI_SW2A2_0": null, + "IOI_SW2A3_0": null, + "IOI_SW4A0_0": null, + "IOI_SW4A1_0": null, + "IOI_SW4A2_0": null, + "IOI_SW4A3_0": null, + "IOI_SW4END0_0": null, + "IOI_SW4END1_0": null, + "IOI_SW4END2_0": null, + "IOI_SW4END3_0": null, + "IOI_WL1END0_0": null, + "IOI_WL1END1_0": null, + "IOI_WL1END2_0": null, + "IOI_WL1END3_0": null, + "IOI_WR1END0_0": null, + "IOI_WR1END1_0": null, + "IOI_WR1END2_0": null, + "IOI_WR1END3_0": null, + "IOI_WW2A0_0": null, + "IOI_WW2A1_0": null, + "IOI_WW2A2_0": null, + "IOI_WW2A3_0": null, + "IOI_WW2END0_0": null, + "IOI_WW2END1_0": null, + "IOI_WW2END2_0": null, + "IOI_WW2END3_0": null, + "IOI_WW4A0_0": null, + "IOI_WW4A1_0": null, + "IOI_WW4A2_0": null, + "IOI_WW4A3_0": null, + "IOI_WW4B0_0": null, + "IOI_WW4B1_0": null, + "IOI_WW4B2_0": null, + "IOI_WW4B3_0": null, + "IOI_WW4C0_0": null, + "IOI_WW4C1_0": null, + "IOI_WW4C2_0": null, + "IOI_WW4C3_0": null, + "IOI_WW4END0_0": null, + "IOI_WW4END1_0": null, + "IOI_WW4END2_0": null, + "IOI_WW4END3_0": null, + "LIOI3_IDELAY0_IFDLY0": null, + "LIOI3_IDELAY0_IFDLY1": null, + "LIOI3_IDELAY0_IFDLY2": null, + "LIOI_DCI_T_TERM0": null, + "LIOI_I0": null, + "LIOI_IBUF0": null, + "LIOI_IBUF_DISABLE0": null, + "LIOI_IDELAY0_DATAOUT": null, + "LIOI_IDELAY0_IDATAIN": null, + "LIOI_ILOGIC0_D": null, + "LIOI_ILOGIC0_DDLY": null, + "LIOI_ILOGIC0_OFB": null, + "LIOI_ILOGIC0_TFB": null, + "LIOI_ISIN10": null, + "LIOI_ISIN20": null, + "LIOI_ISOUT10": null, + "LIOI_ISOUT20": null, + "LIOI_KEEPER_INT_EN_1": null, + "LIOI_O0": null, + "LIOI_ODELAY0_DATAOUT": null, + "LIOI_ODELAY0_ODATAIN": null, + "LIOI_ODELAY0_OFDLY0": null, + "LIOI_ODELAY0_OFDLY1": null, + "LIOI_ODELAY0_OFDLY2": null, + "LIOI_OLOGIC0_CLKDIVF": null, + "LIOI_OLOGIC0_OFB": null, + "LIOI_OLOGIC0_OQ": null, + "LIOI_OLOGIC0_TFB": null, + "LIOI_OLOGIC0_TFB_LOCAL": null, + "LIOI_OLOGIC0_TQ": null, + "LIOI_OSIN10": null, + "LIOI_OSIN20": null, + "LIOI_OSOUT10": null, + "LIOI_OSOUT20": null, + "LIOI_PD_INT_EN_1": null, + "LIOI_PU_INT_EN_1": null, + "LIOI_T0": null + } } diff --git a/kintex7/tile_type_LIOI3_TBYTESRC.json b/kintex7/tile_type_LIOI3_TBYTESRC.json index bde7bd6..281a5f5 100644 --- a/kintex7/tile_type_LIOI3_TBYTESRC.json +++ b/kintex7/tile_type_LIOI3_TBYTESRC.json @@ -2,2914 +2,10040 @@ "pips": { "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "LIOI3_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "LIOI3_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "LIOI3_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "LIOI3_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "LIOI3_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "LIOI3_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_1" }, "LIOI3_TBYTESRC.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY1_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "LIOI3_TBYTESRC.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_1" }, "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "LIOI3_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "LIOI3_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "LIOI3_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "LIOI3_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "LIOI3_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "LIOI3_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_1" }, "LIOI3_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "LIOI3_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_1" }, "LIOI3_TBYTESRC.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY1_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "LIOI3_TBYTESRC.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_1" }, "LIOI3_TBYTESRC.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY1_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "LIOI3_TBYTESRC.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_1" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "LIOI3_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "LIOI3_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_I2GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_O" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "LIOI3_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC1_O" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q1" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q2" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q3" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q4" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q5" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q6" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q7" }, "LIOI3_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q8" }, "LIOI3_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "LIOI3_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_1" }, "LIOI3_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "LIOI3_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_1" }, "LIOI3_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "LIOI3_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_1" }, "LIOI3_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "LIOI3_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_1" }, "LIOI3_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "LIOI3_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_1" }, "LIOI3_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "LIOI3_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_1" }, "LIOI3_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "LIOI3_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_1" }, "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "LIOI3_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "LIOI3_TBYTESRC.IOI_IMUX21_0->IOI_OLOGIC1_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "LIOI3_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_1" }, "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "LIOI3_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "LIOI3_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "LIOI3_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_1" }, "LIOI3_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "LIOI3_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_1" }, "LIOI3_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "LIOI3_TBYTESRC.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_1" }, "LIOI3_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "LIOI3_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_1" }, "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "LIOI3_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "LIOI3_TBYTESRC.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "LIOI3_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_1" }, "LIOI3_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "LIOI3_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_1" }, "LIOI3_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "LIOI3_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_1" }, "LIOI3_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "LIOI3_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_1" }, "LIOI3_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "LIOI3_TBYTESRC.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_1" }, "LIOI3_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "LIOI3_TBYTESRC.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_1" }, "LIOI3_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "LIOI3_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_1" }, "LIOI3_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "LIOI3_TBYTESRC.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_1" }, "LIOI3_TBYTESRC.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "LIOI3_TBYTESRC.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_1" }, "LIOI3_TBYTESRC.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "LIOI3_TBYTESRC.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_1" }, "LIOI3_TBYTESRC.IOI_IMUX42_0->IOI_OLOGIC1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "LIOI3_TBYTESRC.IOI_IMUX42_1->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_1" }, "LIOI3_TBYTESRC.IOI_IMUX43_0->IOI_OLOGIC1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "LIOI3_TBYTESRC.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_1" }, "LIOI3_TBYTESRC.IOI_IMUX44_0->IOI_OLOGIC1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "LIOI3_TBYTESRC.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_1" }, "LIOI3_TBYTESRC.IOI_IMUX45_0->IOI_OLOGIC1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "LIOI3_TBYTESRC.IOI_IMUX45_1->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_1" }, "LIOI3_TBYTESRC.IOI_IMUX46_0->IOI_OLOGIC1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "LIOI3_TBYTESRC.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_1" }, "LIOI3_TBYTESRC.IOI_IMUX47_0->IOI_OLOGIC1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "LIOI3_TBYTESRC.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_1" }, "LIOI3_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "LIOI3_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_1" }, "LIOI3_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "LIOI3_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_1" }, "LIOI3_TBYTESRC.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_DCI_T_TERM1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "LIOI3_TBYTESRC.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_1" }, "LIOI3_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "LIOI3_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_1" }, "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTESRC.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTESRC.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTESRC.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTESRC.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IBUF_DISABLE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "LIOI3_TBYTESRC.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_1" }, "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK1->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, 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"0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", 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"res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { "can_invert": "0", + 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}, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", 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"IOI_LEAF_GCLK2" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + 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"dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "LIOI3_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3_TBYTESRC.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC1_IOCLKGLITCH" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "LIOI3_TBYTESRC.IOI_OLOGIC1_TBYTEOUT->>IOI_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "IOI_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "IOI_OLOGIC1_TBYTEOUT" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "LIOI3_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + 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"dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": 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"0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_RCLK_FORIO3" }, "LIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_TBYTEIN" }, "LIOI3_TBYTESRC.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_TBYTEIN" }, "LIOI3_TBYTESRC.LIOI_I0->LIOI_IDELAY0_IDATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IDELAY0_IDATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I0" }, "LIOI3_TBYTESRC.LIOI_I0->LIOI_ILOGIC0_D": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_D", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I0" }, "LIOI3_TBYTESRC.LIOI_I1->LIOI_IDELAY1_IDATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IDELAY1_IDATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I1" }, "LIOI3_TBYTESRC.LIOI_I1->LIOI_ILOGIC1_D": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC1_D", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_I1" }, "LIOI3_TBYTESRC.LIOI_IBUF0->LIOI_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_IBUF0" }, "LIOI3_TBYTESRC.LIOI_IBUF1->LIOI_I1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_I1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_IBUF1" }, "LIOI3_TBYTESRC.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_IDELAY0_DATAOUT" }, "LIOI3_TBYTESRC.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { 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"is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.264", + "0.331", + "0.575", + "0.666" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_IDELAY1_IDATAIN" }, "LIOI3_TBYTESRC.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC0_D" }, "LIOI3_TBYTESRC.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC0_DDLY" }, "LIOI3_TBYTESRC.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC1_D" }, "LIOI3_TBYTESRC.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC1_DDLY" }, "LIOI3_TBYTESRC.LIOI_ISOUT10->LIOI_ISIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ISIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_ISOUT10" }, "LIOI3_TBYTESRC.LIOI_ISOUT20->LIOI_ISIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ISIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_ISOUT20" }, "LIOI3_TBYTESRC.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_OFB" }, "LIOI3_TBYTESRC.LIOI_OLOGIC0_OQ->>LIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_O0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_OQ" }, "LIOI3_TBYTESRC.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_OQ" }, "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB" }, "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" }, "LIOI3_TBYTESRC.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" }, "LIOI3_TBYTESRC.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_TQ" }, "LIOI3_TBYTESRC.LIOI_OLOGIC0_TQ->>LIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_TQ" }, "LIOI3_TBYTESRC.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_OFB" }, "LIOI3_TBYTESRC.LIOI_OLOGIC1_OQ->>LIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_O1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_OQ" }, "LIOI3_TBYTESRC.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_OQ" }, "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_TFB" }, "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_TFB_LOCAL" }, "LIOI3_TBYTESRC.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_TFB_LOCAL" }, "LIOI3_TBYTESRC.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_TQ" }, "LIOI3_TBYTESRC.LIOI_OLOGIC1_TQ->>LIOI_T1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_T1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_TQ" }, "LIOI3_TBYTESRC.LIOI_OSOUT11->LIOI_OSIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OSIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OSOUT11" }, "LIOI3_TBYTESRC.LIOI_OSOUT21->LIOI_OSIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OSIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OSOUT21" } }, @@ -2918,39 +10044,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC1_CLK", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "D1": "IOI_OLOGIC1_D1", - "D2": "IOI_OLOGIC1_D2", - "D3": "IOI_OLOGIC1_D3", - "D4": "IOI_OLOGIC1_D4", - "D5": "IOI_OLOGIC1_D5", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "OCE": "IOI_OLOGIC1_OCE", - "OFB": "LIOI_OLOGIC1_OFB", - "OQ": "LIOI_OLOGIC1_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "LIOI_OSOUT11", - "SHIFTOUT2": "LIOI_OSOUT21", - "SR": "IOI_OLOGIC1_SR", - "T1": "IOI_OLOGIC1_T1", - "T2": "IOI_OLOGIC1_T2", - "T3": "IOI_OLOGIC1_T3", - "T4": "IOI_OLOGIC1_T4", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TCE": "IOI_OLOGIC1_TCE", - "TFB": "LIOI_OLOGIC1_TFB", - "TQ": "LIOI_OLOGIC1_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -2960,37 +10356,307 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "CE1": "IOI_ILOGIC1_CE1", - "CE2": "IOI_ILOGIC1_CE2", - "CLK": "IOI_ILOGIC1_CLK", - "CLKB": "IOI_ILOGIC1_CLKB", - "CLKDIV": "IOI_ILOGIC1_CLKDIV", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "D": "LIOI_ILOGIC1_D", - "DDLY": "LIOI_ILOGIC1_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "O": "IOI_ILOGIC1_O", - "OCLK": "IOI_ILOGIC1_OCLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "OFB": "LIOI_ILOGIC1_OFB", - "Q1": "IOI_ILOGIC1_Q1", - "Q2": "IOI_ILOGIC1_Q2", - "Q3": "IOI_ILOGIC1_Q3", - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q6": "IOI_ILOGIC1_Q6", - "Q7": "IOI_ILOGIC1_Q7", - "Q8": "IOI_ILOGIC1_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC1_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q8" + }, "REV": null, - "SHIFTIN1": "LIOI_ISIN11", - "SHIFTIN2": "LIOI_ISIN21", - "SHIFTOUT1": "LIOI_ISOUT11", - "SHIFTOUT2": "LIOI_ISOUT21", - "SR": "IOI_ILOGIC1_SR", - "TFB": "LIOI_ILOGIC1_TFB" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ISIN11" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ISIN21" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3000,39 +10666,327 @@ "name": "X0Y1", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "LIOI_OLOGIC0_OFB", - "OQ": "LIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_OQ" + }, "REV": null, - "SHIFTIN1": "LIOI_OSIN10", - "SHIFTIN2": "LIOI_OSIN20", - "SHIFTOUT1": "LIOI_OSOUT10", - "SHIFTOUT2": "LIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "LIOI_OLOGIC0_TFB", - "TQ": "LIOI_OLOGIC0_TQ" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OSIN10" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OSIN20" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -3042,37 +10996,289 @@ "name": "X0Y1", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "LIOI_ILOGIC0_D", - "DDLY": "LIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "LIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "LIOI_ISOUT10", - "SHIFTOUT2": "LIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "LIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3082,29 +11288,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY1_C", - "CE": "IOI_IDELAY1_CE", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY1_DATAIN", - "DATAOUT": "LIOI_IDELAY1_DATAOUT", - "IDATAIN": "LIOI_IDELAY1_IDATAIN", - "IFDLY0": "LIOI3_IDELAY1_IFDLY0", - "IFDLY1": "LIOI3_IDELAY1_IFDLY1", - "IFDLY2": "LIOI3_IDELAY1_IFDLY2", - "INC": "IOI_IDELAY1_INC", - "LD": "IOI_IDELAY1_LD", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "REGRST": "IOI_IDELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_IDELAY1_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_IDELAY1_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY1_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY1_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY1_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3114,29 +11527,236 @@ "name": "X0Y1", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "LIOI_IDELAY0_DATAOUT", - "IDATAIN": "LIOI_IDELAY0_IDATAIN", - "IFDLY0": "LIOI3_IDELAY0_IFDLY0", - "IFDLY1": "LIOI3_IDELAY0_IFDLY1", - "IFDLY2": "LIOI3_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3144,750 +11764,750 @@ } ], "tile_type": "LIOI3_TBYTESRC", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS0_1", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS1_1", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS2_1", - "IOI_BLOCK_OUTS3_0", - "IOI_BLOCK_OUTS3_1", - "IOI_BYP0_0", - "IOI_BYP0_1", - "IOI_BYP1_0", - "IOI_BYP1_1", - "IOI_BYP2_0", - "IOI_BYP2_1", - "IOI_BYP3_0", - "IOI_BYP3_1", - "IOI_BYP4_0", - "IOI_BYP4_1", - "IOI_BYP5_0", - "IOI_BYP5_1", - "IOI_BYP6_0", - "IOI_BYP6_1", - "IOI_BYP7_0", - "IOI_BYP7_1", - "IOI_CLK0_0", - "IOI_CLK0_1", - "IOI_CLK1_0", - "IOI_CLK1_1", - "IOI_CTRL0_0", - "IOI_CTRL0_1", - "IOI_CTRL1_0", - "IOI_CTRL1_1", - "IOI_DCI_DCIDONE", - "IOI_DCI_TSTCLK", - "IOI_DCI_TSTHLN", - "IOI_DCI_TSTHLP", - "IOI_DCI_TSTRST", - "IOI_DCI_TSTRST0", - "IOI_EE2A0_0", - "IOI_EE2A0_1", - "IOI_EE2A1_0", - "IOI_EE2A1_1", - "IOI_EE2A2_0", - "IOI_EE2A2_1", - "IOI_EE2A3_0", - "IOI_EE2A3_1", - "IOI_EE2BEG0_0", - "IOI_EE2BEG0_1", - "IOI_EE2BEG1_0", - "IOI_EE2BEG1_1", - "IOI_EE2BEG2_0", - "IOI_EE2BEG2_1", - "IOI_EE2BEG3_0", - "IOI_EE2BEG3_1", - "IOI_EE4A0_0", - "IOI_EE4A0_1", - "IOI_EE4A1_0", - "IOI_EE4A1_1", - "IOI_EE4A2_0", - "IOI_EE4A2_1", - "IOI_EE4A3_0", - "IOI_EE4A3_1", - "IOI_EE4B0_0", - "IOI_EE4B0_1", - "IOI_EE4B1_0", - "IOI_EE4B1_1", - "IOI_EE4B2_0", - "IOI_EE4B2_1", - "IOI_EE4B3_0", - "IOI_EE4B3_1", - "IOI_EE4BEG0_0", - "IOI_EE4BEG0_1", - "IOI_EE4BEG1_0", - "IOI_EE4BEG1_1", - "IOI_EE4BEG2_0", - "IOI_EE4BEG2_1", - "IOI_EE4BEG3_0", - "IOI_EE4BEG3_1", - "IOI_EE4C0_0", - "IOI_EE4C0_1", - "IOI_EE4C1_0", - "IOI_EE4C1_1", - "IOI_EE4C2_0", - "IOI_EE4C2_1", - "IOI_EE4C3_0", - "IOI_EE4C3_1", - "IOI_EL1BEG0_0", - "IOI_EL1BEG0_1", - "IOI_EL1BEG1_0", - "IOI_EL1BEG1_1", - "IOI_EL1BEG2_0", - "IOI_EL1BEG2_1", - "IOI_EL1BEG3_0", - "IOI_EL1BEG3_1", - "IOI_ER1BEG0_0", - "IOI_ER1BEG0_1", - "IOI_ER1BEG1_0", - "IOI_ER1BEG1_1", - "IOI_ER1BEG2_0", - "IOI_ER1BEG2_1", - "IOI_ER1BEG3_0", - "IOI_ER1BEG3_1", - "IOI_FAN0_0", - "IOI_FAN0_1", - "IOI_FAN1_0", - "IOI_FAN1_1", - "IOI_FAN2_0", - "IOI_FAN2_1", - "IOI_FAN3_0", - "IOI_FAN3_1", - "IOI_FAN4_0", - "IOI_FAN4_1", - "IOI_FAN5_0", - "IOI_FAN5_1", - "IOI_FAN6_0", - "IOI_FAN6_1", - "IOI_FAN7_0", - "IOI_FAN7_1", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY1_C", - "IOI_IDELAY1_CE", - "IOI_IDELAY1_CINVCTRL", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT0", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_IDELAY1_DATAIN", - "IOI_IDELAY1_INC", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_LDPIPEEN", - "IOI_IDELAY1_REGRST", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC1_BITSLIP", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC1_CE2", - "IOI_ILOGIC1_CLK", - "IOI_ILOGIC1_CLKB", - "IOI_ILOGIC1_CLKDIV", - "IOI_ILOGIC1_CLKDIVP", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_ILOGIC1_O", - "IOI_ILOGIC1_OCLK", - "IOI_ILOGIC1_OCLKB", - "IOI_ILOGIC1_Q1", - "IOI_ILOGIC1_Q2", - "IOI_ILOGIC1_Q3", - "IOI_ILOGIC1_Q4", - "IOI_ILOGIC1_Q5", - "IOI_ILOGIC1_Q6", - "IOI_ILOGIC1_Q7", - "IOI_ILOGIC1_Q8", - "IOI_ILOGIC1_REV", - "IOI_ILOGIC1_SR", - "IOI_IMUX0_0", - "IOI_IMUX0_1", - "IOI_IMUX10_0", - "IOI_IMUX10_1", - "IOI_IMUX11_0", - "IOI_IMUX11_1", - "IOI_IMUX12_0", - "IOI_IMUX12_1", - "IOI_IMUX13_0", - "IOI_IMUX13_1", - "IOI_IMUX14_0", - "IOI_IMUX14_1", - "IOI_IMUX15_0", - "IOI_IMUX15_1", - "IOI_IMUX16_0", - "IOI_IMUX16_1", - "IOI_IMUX17_0", - "IOI_IMUX17_1", - "IOI_IMUX18_0", - "IOI_IMUX18_1", - "IOI_IMUX19_0", - "IOI_IMUX19_1", - "IOI_IMUX1_0", - "IOI_IMUX1_1", - "IOI_IMUX20_0", - "IOI_IMUX20_1", - "IOI_IMUX21_0", - "IOI_IMUX21_1", - "IOI_IMUX22_0", - "IOI_IMUX22_1", - "IOI_IMUX23_0", - "IOI_IMUX23_1", - "IOI_IMUX24_0", - "IOI_IMUX24_1", - "IOI_IMUX25_0", - "IOI_IMUX25_1", - "IOI_IMUX26_0", - "IOI_IMUX26_1", - "IOI_IMUX27_0", - "IOI_IMUX27_1", - "IOI_IMUX28_0", - "IOI_IMUX28_1", - "IOI_IMUX29_0", - "IOI_IMUX29_1", - "IOI_IMUX2_0", - "IOI_IMUX2_1", - "IOI_IMUX30_0", - "IOI_IMUX30_1", - "IOI_IMUX31_0", - "IOI_IMUX31_1", - "IOI_IMUX32_0", - "IOI_IMUX32_1", - "IOI_IMUX33_0", - "IOI_IMUX33_1", - "IOI_IMUX34_0", - "IOI_IMUX34_1", - "IOI_IMUX35_0", - "IOI_IMUX35_1", - "IOI_IMUX36_0", - "IOI_IMUX36_1", - "IOI_IMUX37_0", - "IOI_IMUX37_1", - "IOI_IMUX38_0", - "IOI_IMUX38_1", - "IOI_IMUX39_0", - "IOI_IMUX39_1", - "IOI_IMUX3_0", - "IOI_IMUX3_1", - "IOI_IMUX40_0", - "IOI_IMUX40_1", - "IOI_IMUX41_0", - "IOI_IMUX41_1", - "IOI_IMUX42_0", - "IOI_IMUX42_1", - "IOI_IMUX43_0", - "IOI_IMUX43_1", - "IOI_IMUX44_0", - "IOI_IMUX44_1", - "IOI_IMUX45_0", - "IOI_IMUX45_1", - "IOI_IMUX46_0", - "IOI_IMUX46_1", - "IOI_IMUX47_0", - "IOI_IMUX47_1", - "IOI_IMUX4_0", - "IOI_IMUX4_1", - "IOI_IMUX5_0", - "IOI_IMUX5_1", - "IOI_IMUX6_0", - "IOI_IMUX6_1", - "IOI_IMUX7_0", - "IOI_IMUX7_1", - "IOI_IMUX8_0", - "IOI_IMUX8_1", - "IOI_IMUX9_0", - "IOI_IMUX9_1", - "IOI_IMUX_RC0", - "IOI_IMUX_RC1", - "IOI_IMUX_RC2", - "IOI_IMUX_RC3", - "IOI_INT_DCI_EN", - "IOI_IOCLK0", - "IOI_IOCLK1", - "IOI_IOCLK2", - "IOI_IOCLK3", - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK5", - "IOI_LH10_0", - "IOI_LH10_1", - "IOI_LH11_0", - "IOI_LH11_1", - "IOI_LH12_0", - "IOI_LH12_1", - "IOI_LH1_0", - "IOI_LH1_1", - "IOI_LH2_0", - "IOI_LH2_1", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_LH4_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_LH5_1", - "IOI_LH6_0", - "IOI_LH6_1", - "IOI_LH7_0", - "IOI_LH7_1", - "IOI_LH8_0", - "IOI_LH8_1", - "IOI_LH9_0", - "IOI_LH9_1", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS10_1", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS11_1", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS12_1", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS13_1", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS14_1", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS15_1", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS16_1", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS17_1", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS18_1", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS1_1", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS20_1", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS21_1", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS22_1", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS23_1", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS2_1", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS3_1", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS4_1", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS5_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS6_1", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS7_1", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS9_0", - "IOI_LOGIC_OUTS9_1", - "IOI_MONITOR_N", - "IOI_MONITOR_P", - "IOI_NE2A0_0", - "IOI_NE2A0_1", - "IOI_NE2A1_0", - "IOI_NE2A1_1", - "IOI_NE2A2_0", - "IOI_NE2A2_1", - "IOI_NE2A3_0", - "IOI_NE2A3_1", - "IOI_NE4BEG0_0", - "IOI_NE4BEG0_1", - "IOI_NE4BEG1_0", - "IOI_NE4BEG1_1", - "IOI_NE4BEG2_0", - "IOI_NE4BEG2_1", - "IOI_NE4BEG3_0", - "IOI_NE4BEG3_1", - "IOI_NE4C0_0", - "IOI_NE4C0_1", - "IOI_NE4C1_0", - "IOI_NE4C1_1", - "IOI_NE4C2_0", - "IOI_NE4C2_1", - "IOI_NE4C3_0", - "IOI_NE4C3_1", - "IOI_NW2A0_0", - "IOI_NW2A0_1", - "IOI_NW2A1_0", - "IOI_NW2A1_1", - "IOI_NW2A2_0", - "IOI_NW2A2_1", - "IOI_NW2A3_0", - "IOI_NW2A3_1", - "IOI_NW4A0_0", - "IOI_NW4A0_1", - "IOI_NW4A1_0", - "IOI_NW4A1_1", - "IOI_NW4A2_0", - "IOI_NW4A2_1", - "IOI_NW4A3_0", - "IOI_NW4A3_1", - "IOI_NW4END0_0", - "IOI_NW4END0_1", - "IOI_NW4END1_0", - "IOI_NW4END1_1", - "IOI_NW4END2_0", - "IOI_NW4END2_1", - "IOI_NW4END3_0", - "IOI_NW4END3_1", - "IOI_OCLKM_0", - "IOI_OCLKM_1", - "IOI_OCLK_0", - "IOI_OCLK_1", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_ODELAY1_C", - "IOI_ODELAY1_CE", - "IOI_ODELAY1_CINVCTRL", - "IOI_ODELAY1_CLKIN", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_ODELAY1_INC", - "IOI_ODELAY1_LD", - "IOI_ODELAY1_LDPIPEEN", - "IOI_ODELAY1_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_CLK", - "IOI_OLOGIC1_CLKB", - "IOI_OLOGIC1_CLKDIV", - "IOI_OLOGIC1_CLKDIVB", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_OLOGIC1_D1", - "IOI_OLOGIC1_D2", - "IOI_OLOGIC1_D3", - "IOI_OLOGIC1_D4", - "IOI_OLOGIC1_D5", - "IOI_OLOGIC1_D6", - "IOI_OLOGIC1_D7", - "IOI_OLOGIC1_D8", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_OLOGIC1_OCE", - "IOI_OLOGIC1_REV", - "IOI_OLOGIC1_SR", - "IOI_OLOGIC1_T1", - "IOI_OLOGIC1_T2", - "IOI_OLOGIC1_T3", - "IOI_OLOGIC1_T4", - "IOI_OLOGIC1_TBYTEIN", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_OLOGIC1_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR3", - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO3", - "IOI_SE2A0_0", - "IOI_SE2A0_1", - "IOI_SE2A1_0", - "IOI_SE2A1_1", - "IOI_SE2A2_0", - "IOI_SE2A2_1", - "IOI_SE2A3_0", - "IOI_SE2A3_1", - "IOI_SE4BEG0_0", - "IOI_SE4BEG0_1", - "IOI_SE4BEG1_0", - "IOI_SE4BEG1_1", - "IOI_SE4BEG2_0", - "IOI_SE4BEG2_1", - "IOI_SE4BEG3_0", - "IOI_SE4BEG3_1", - "IOI_SE4C0_0", - "IOI_SE4C0_1", - "IOI_SE4C1_0", - "IOI_SE4C1_1", - "IOI_SE4C2_0", - "IOI_SE4C2_1", - "IOI_SE4C3_0", - "IOI_SE4C3_1", - "IOI_SW2A0_0", - "IOI_SW2A0_1", - "IOI_SW2A1_0", - "IOI_SW2A1_1", - "IOI_SW2A2_0", - "IOI_SW2A2_1", - "IOI_SW2A3_0", - "IOI_SW2A3_1", - "IOI_SW4A0_0", - "IOI_SW4A0_1", - "IOI_SW4A1_0", - "IOI_SW4A1_1", - "IOI_SW4A2_0", - "IOI_SW4A2_1", - "IOI_SW4A3_0", - "IOI_SW4A3_1", - "IOI_SW4END0_0", - "IOI_SW4END0_1", - "IOI_SW4END1_0", - "IOI_SW4END1_1", - "IOI_SW4END2_0", - "IOI_SW4END2_1", - "IOI_SW4END3_0", - "IOI_SW4END3_1", - "IOI_TBYTEIN", - "IOI_WL1END0_0", - "IOI_WL1END0_1", - "IOI_WL1END1_0", - "IOI_WL1END1_1", - "IOI_WL1END2_0", - "IOI_WL1END2_1", - "IOI_WL1END3_0", - "IOI_WL1END3_1", - "IOI_WR1END0_0", - "IOI_WR1END0_1", - "IOI_WR1END1_0", - "IOI_WR1END1_1", - "IOI_WR1END2_0", - "IOI_WR1END2_1", - "IOI_WR1END3_0", - "IOI_WR1END3_1", - "IOI_WW2A0_0", - "IOI_WW2A0_1", - "IOI_WW2A1_0", - "IOI_WW2A1_1", - "IOI_WW2A2_0", - "IOI_WW2A2_1", - "IOI_WW2A3_0", - "IOI_WW2A3_1", - "IOI_WW2END0_0", - "IOI_WW2END0_1", - "IOI_WW2END1_0", - "IOI_WW2END1_1", - "IOI_WW2END2_0", - "IOI_WW2END2_1", - "IOI_WW2END3_0", - "IOI_WW2END3_1", - "IOI_WW4A0_0", - "IOI_WW4A0_1", - "IOI_WW4A1_0", - "IOI_WW4A1_1", - "IOI_WW4A2_0", - "IOI_WW4A2_1", - "IOI_WW4A3_0", - "IOI_WW4A3_1", - "IOI_WW4B0_0", - "IOI_WW4B0_1", - "IOI_WW4B1_0", - "IOI_WW4B1_1", - "IOI_WW4B2_0", - "IOI_WW4B2_1", - "IOI_WW4B3_0", - "IOI_WW4B3_1", - "IOI_WW4C0_0", - "IOI_WW4C0_1", - "IOI_WW4C1_0", - "IOI_WW4C1_1", - "IOI_WW4C2_0", - "IOI_WW4C2_1", - "IOI_WW4C3_0", - "IOI_WW4C3_1", - "IOI_WW4END0_0", - "IOI_WW4END0_1", - "IOI_WW4END1_0", - "IOI_WW4END1_1", - "IOI_WW4END2_0", - "IOI_WW4END2_1", - "IOI_WW4END3_0", - "IOI_WW4END3_1", - "LIOI3_IDELAY0_IFDLY0", - "LIOI3_IDELAY0_IFDLY1", - "LIOI3_IDELAY0_IFDLY2", - "LIOI3_IDELAY1_IFDLY0", - "LIOI3_IDELAY1_IFDLY1", - "LIOI3_IDELAY1_IFDLY2", - "LIOI_DCI_T_TERM0", - "LIOI_DCI_T_TERM1", - "LIOI_DIFF_TERM_INT_EN", - "LIOI_I0", - "LIOI_I1", - "LIOI_I2GCLK_BOT1", - "LIOI_I2GCLK_TOP0", - "LIOI_I2GCLK_TOP1", - "LIOI_IBUF0", - "LIOI_IBUF1", - "LIOI_IBUF_DISABLE0", - "LIOI_IBUF_DISABLE1", - "LIOI_IDELAY0_DATAOUT", - "LIOI_IDELAY0_IDATAIN", - "LIOI_IDELAY1_DATAOUT", - "LIOI_IDELAY1_IDATAIN", - "LIOI_ILOGIC0_D", - "LIOI_ILOGIC0_DDLY", - "LIOI_ILOGIC0_OFB", - "LIOI_ILOGIC0_TFB", - "LIOI_ILOGIC1_D", - "LIOI_ILOGIC1_DDLY", - "LIOI_ILOGIC1_OFB", - "LIOI_ILOGIC1_TFB", - "LIOI_ISIN10", - "LIOI_ISIN11", - "LIOI_ISIN20", - "LIOI_ISIN21", - "LIOI_ISOUT10", - "LIOI_ISOUT11", - "LIOI_ISOUT20", - "LIOI_ISOUT21", - "LIOI_KEEPER_INT_EN_0", - "LIOI_KEEPER_INT_EN_1", - "LIOI_O0", - "LIOI_O1", - "LIOI_ODELAY0_DATAOUT", - "LIOI_ODELAY0_ODATAIN", - "LIOI_ODELAY0_OFDLY0", - "LIOI_ODELAY0_OFDLY1", - "LIOI_ODELAY0_OFDLY2", - "LIOI_ODELAY1_DATAOUT", - "LIOI_ODELAY1_ODATAIN", - "LIOI_ODELAY1_OFDLY0", - "LIOI_ODELAY1_OFDLY1", - "LIOI_ODELAY1_OFDLY2", - "LIOI_OLOGIC0_CLKDIVF", - "LIOI_OLOGIC0_OFB", - "LIOI_OLOGIC0_OQ", - "LIOI_OLOGIC0_TFB", - "LIOI_OLOGIC0_TFB_LOCAL", - "LIOI_OLOGIC0_TQ", - "LIOI_OLOGIC1_CLKDIVF", - "LIOI_OLOGIC1_OFB", - "LIOI_OLOGIC1_OQ", - "LIOI_OLOGIC1_TFB", - "LIOI_OLOGIC1_TFB_LOCAL", - "LIOI_OLOGIC1_TQ", - "LIOI_OSIN10", - "LIOI_OSIN11", - "LIOI_OSIN20", - "LIOI_OSIN21", - "LIOI_OSOUT10", - "LIOI_OSOUT11", - "LIOI_OSOUT20", - "LIOI_OSOUT21", - "LIOI_PD_INT_EN_0", - "LIOI_PD_INT_EN_1", - "LIOI_PU_INT_EN_0", - "LIOI_PU_INT_EN_1", - "LIOI_T0", - "LIOI_T1" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS0_1": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS1_1": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS2_1": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BLOCK_OUTS3_1": null, + "IOI_BYP0_0": null, + "IOI_BYP0_1": null, + "IOI_BYP1_0": null, + "IOI_BYP1_1": null, + "IOI_BYP2_0": null, + "IOI_BYP2_1": null, + "IOI_BYP3_0": null, + "IOI_BYP3_1": null, + "IOI_BYP4_0": null, + "IOI_BYP4_1": null, + "IOI_BYP5_0": null, + "IOI_BYP5_1": null, + "IOI_BYP6_0": null, + "IOI_BYP6_1": null, + "IOI_BYP7_0": null, + "IOI_BYP7_1": null, + "IOI_CLK0_0": null, + "IOI_CLK0_1": null, + "IOI_CLK1_0": null, + "IOI_CLK1_1": null, + "IOI_CTRL0_0": null, + "IOI_CTRL0_1": null, + "IOI_CTRL1_0": null, + "IOI_CTRL1_1": null, + "IOI_DCI_DCIDONE": null, + "IOI_DCI_TSTCLK": null, + "IOI_DCI_TSTHLN": null, + "IOI_DCI_TSTHLP": null, + "IOI_DCI_TSTRST": null, + "IOI_DCI_TSTRST0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A0_1": null, + "IOI_EE2A1_0": null, + "IOI_EE2A1_1": null, + "IOI_EE2A2_0": null, + "IOI_EE2A2_1": null, + "IOI_EE2A3_0": null, + "IOI_EE2A3_1": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG0_1": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG1_1": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG2_1": null, + "IOI_EE2BEG3_0": null, + "IOI_EE2BEG3_1": null, + "IOI_EE4A0_0": null, + "IOI_EE4A0_1": null, + "IOI_EE4A1_0": null, + "IOI_EE4A1_1": null, + "IOI_EE4A2_0": null, + "IOI_EE4A2_1": null, + "IOI_EE4A3_0": null, + "IOI_EE4A3_1": null, + "IOI_EE4B0_0": null, + "IOI_EE4B0_1": null, + "IOI_EE4B1_0": null, + "IOI_EE4B1_1": null, + "IOI_EE4B2_0": null, + "IOI_EE4B2_1": null, + "IOI_EE4B3_0": null, + "IOI_EE4B3_1": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG0_1": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG1_1": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG2_1": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4BEG3_1": null, + "IOI_EE4C0_0": null, + "IOI_EE4C0_1": null, + "IOI_EE4C1_0": null, + "IOI_EE4C1_1": null, + "IOI_EE4C2_0": null, + "IOI_EE4C2_1": null, + "IOI_EE4C3_0": null, + "IOI_EE4C3_1": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG0_1": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG1_1": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG2_1": null, + "IOI_EL1BEG3_0": null, + "IOI_EL1BEG3_1": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG0_1": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG1_1": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG2_1": null, + "IOI_ER1BEG3_0": null, + "IOI_ER1BEG3_1": null, + "IOI_FAN0_0": null, + "IOI_FAN0_1": null, + "IOI_FAN1_0": null, + "IOI_FAN1_1": null, + "IOI_FAN2_0": null, + "IOI_FAN2_1": null, + "IOI_FAN3_0": null, + "IOI_FAN3_1": null, + "IOI_FAN4_0": null, + "IOI_FAN4_1": null, + "IOI_FAN5_0": null, + "IOI_FAN5_1": null, + "IOI_FAN6_0": null, + "IOI_FAN6_1": null, + "IOI_FAN7_0": null, + "IOI_FAN7_1": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_IDELAY1_C": null, + "IOI_IDELAY1_CE": null, + "IOI_IDELAY1_CINVCTRL": null, + "IOI_IDELAY1_CNTVALUEIN0": null, + "IOI_IDELAY1_CNTVALUEIN1": null, + "IOI_IDELAY1_CNTVALUEIN2": null, + "IOI_IDELAY1_CNTVALUEIN3": null, + "IOI_IDELAY1_CNTVALUEIN4": null, + "IOI_IDELAY1_CNTVALUEOUT0": null, + "IOI_IDELAY1_CNTVALUEOUT1": null, + "IOI_IDELAY1_CNTVALUEOUT2": null, + "IOI_IDELAY1_CNTVALUEOUT3": null, + "IOI_IDELAY1_CNTVALUEOUT4": null, + "IOI_IDELAY1_DATAIN": null, + "IOI_IDELAY1_INC": null, + "IOI_IDELAY1_LD": null, + "IOI_IDELAY1_LDPIPEEN": null, + "IOI_IDELAY1_REGRST": null, + "IOI_IDELAYCTRL_DNPULSEOUT": null, + "IOI_IDELAYCTRL_OUTN1": null, + "IOI_IDELAYCTRL_OUTN65": null, + "IOI_IDELAYCTRL_RDY": null, + "IOI_IDELAYCTRL_RST": null, + "IOI_IDELAYCTRL_UPPULSEOUT": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_ILOGIC1_BITSLIP": null, + "IOI_ILOGIC1_CE1": null, + "IOI_ILOGIC1_CE2": null, + "IOI_ILOGIC1_CLK": null, + "IOI_ILOGIC1_CLKB": null, + "IOI_ILOGIC1_CLKDIV": null, + "IOI_ILOGIC1_CLKDIVP": null, + "IOI_ILOGIC1_DYNCLKDIVPSEL": null, + "IOI_ILOGIC1_DYNCLKDIVSEL": null, + "IOI_ILOGIC1_DYNCLKSEL": null, + "IOI_ILOGIC1_O": null, + "IOI_ILOGIC1_OCLK": null, + "IOI_ILOGIC1_OCLKB": null, + "IOI_ILOGIC1_Q1": null, + "IOI_ILOGIC1_Q2": null, + "IOI_ILOGIC1_Q3": null, + "IOI_ILOGIC1_Q4": null, + "IOI_ILOGIC1_Q5": null, + "IOI_ILOGIC1_Q6": null, + "IOI_ILOGIC1_Q7": null, + "IOI_ILOGIC1_Q8": null, + "IOI_ILOGIC1_REV": null, + "IOI_ILOGIC1_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX0_1": null, + "IOI_IMUX10_0": null, + "IOI_IMUX10_1": null, + "IOI_IMUX11_0": null, + "IOI_IMUX11_1": null, + "IOI_IMUX12_0": null, + "IOI_IMUX12_1": null, + "IOI_IMUX13_0": null, + "IOI_IMUX13_1": null, + "IOI_IMUX14_0": null, + "IOI_IMUX14_1": null, + "IOI_IMUX15_0": null, + "IOI_IMUX15_1": null, + "IOI_IMUX16_0": null, + "IOI_IMUX16_1": null, + "IOI_IMUX17_0": null, + "IOI_IMUX17_1": null, + "IOI_IMUX18_0": null, + "IOI_IMUX18_1": null, + "IOI_IMUX19_0": null, + "IOI_IMUX19_1": null, + "IOI_IMUX1_0": null, + "IOI_IMUX1_1": null, + "IOI_IMUX20_0": null, + "IOI_IMUX20_1": null, + "IOI_IMUX21_0": null, + "IOI_IMUX21_1": null, + "IOI_IMUX22_0": null, + "IOI_IMUX22_1": null, + "IOI_IMUX23_0": null, + "IOI_IMUX23_1": null, + "IOI_IMUX24_0": null, + "IOI_IMUX24_1": null, + "IOI_IMUX25_0": null, + "IOI_IMUX25_1": null, + "IOI_IMUX26_0": null, + "IOI_IMUX26_1": null, + "IOI_IMUX27_0": null, + "IOI_IMUX27_1": null, + "IOI_IMUX28_0": null, + "IOI_IMUX28_1": null, + "IOI_IMUX29_0": null, + "IOI_IMUX29_1": null, + "IOI_IMUX2_0": null, + "IOI_IMUX2_1": null, + "IOI_IMUX30_0": null, + "IOI_IMUX30_1": null, + "IOI_IMUX31_0": null, + "IOI_IMUX31_1": null, + "IOI_IMUX32_0": null, + "IOI_IMUX32_1": null, + "IOI_IMUX33_0": null, + "IOI_IMUX33_1": null, + "IOI_IMUX34_0": null, + "IOI_IMUX34_1": null, + "IOI_IMUX35_0": null, + "IOI_IMUX35_1": null, + "IOI_IMUX36_0": null, + "IOI_IMUX36_1": null, + "IOI_IMUX37_0": null, + "IOI_IMUX37_1": null, + "IOI_IMUX38_0": null, + "IOI_IMUX38_1": null, + "IOI_IMUX39_0": null, + "IOI_IMUX39_1": null, + "IOI_IMUX3_0": null, + "IOI_IMUX3_1": null, + "IOI_IMUX40_0": null, + "IOI_IMUX40_1": null, + "IOI_IMUX41_0": null, + "IOI_IMUX41_1": null, + "IOI_IMUX42_0": null, + "IOI_IMUX42_1": null, + "IOI_IMUX43_0": null, + "IOI_IMUX43_1": null, + "IOI_IMUX44_0": null, + "IOI_IMUX44_1": null, + "IOI_IMUX45_0": null, + "IOI_IMUX45_1": null, + "IOI_IMUX46_0": null, + "IOI_IMUX46_1": null, + "IOI_IMUX47_0": null, + "IOI_IMUX47_1": null, + "IOI_IMUX4_0": null, + "IOI_IMUX4_1": null, + "IOI_IMUX5_0": null, + "IOI_IMUX5_1": null, + "IOI_IMUX6_0": null, + "IOI_IMUX6_1": null, + "IOI_IMUX7_0": null, + "IOI_IMUX7_1": null, + "IOI_IMUX8_0": null, + "IOI_IMUX8_1": null, + "IOI_IMUX9_0": null, + "IOI_IMUX9_1": null, + "IOI_IMUX_RC0": null, + "IOI_IMUX_RC1": null, + "IOI_IMUX_RC2": null, + "IOI_IMUX_RC3": null, + "IOI_INT_DCI_EN": null, + "IOI_IOCLK0": null, + "IOI_IOCLK1": null, + "IOI_IOCLK2": null, + "IOI_IOCLK3": null, + "IOI_LEAF_GCLK0": null, + "IOI_LEAF_GCLK1": null, + "IOI_LEAF_GCLK2": null, + "IOI_LEAF_GCLK3": null, + "IOI_LEAF_GCLK4": null, + "IOI_LEAF_GCLK5": null, + "IOI_LH10_0": null, + "IOI_LH10_1": null, + "IOI_LH11_0": null, + "IOI_LH11_1": null, + "IOI_LH12_0": null, + "IOI_LH12_1": null, + "IOI_LH1_0": null, + "IOI_LH1_1": null, + "IOI_LH2_0": null, + "IOI_LH2_1": null, + "IOI_LH3_0": null, + "IOI_LH3_1": null, + "IOI_LH4_0": null, + "IOI_LH4_1": null, + "IOI_LH5_0": null, + "IOI_LH5_1": null, + "IOI_LH6_0": null, + "IOI_LH6_1": null, + "IOI_LH7_0": null, + "IOI_LH7_1": null, + "IOI_LH8_0": null, + "IOI_LH8_1": null, + "IOI_LH9_0": null, + "IOI_LH9_1": null, + "IOI_LOGIC_OUTS0_0": null, + "IOI_LOGIC_OUTS0_1": null, + "IOI_LOGIC_OUTS10_0": null, + "IOI_LOGIC_OUTS10_1": null, + "IOI_LOGIC_OUTS11_0": null, + "IOI_LOGIC_OUTS11_1": null, + "IOI_LOGIC_OUTS12_0": null, + "IOI_LOGIC_OUTS12_1": null, + "IOI_LOGIC_OUTS13_0": null, + "IOI_LOGIC_OUTS13_1": null, + "IOI_LOGIC_OUTS14_0": null, + "IOI_LOGIC_OUTS14_1": null, + "IOI_LOGIC_OUTS15_0": null, + "IOI_LOGIC_OUTS15_1": null, + "IOI_LOGIC_OUTS16_0": null, + "IOI_LOGIC_OUTS16_1": null, + "IOI_LOGIC_OUTS17_0": null, + "IOI_LOGIC_OUTS17_1": null, + "IOI_LOGIC_OUTS18_0": null, + "IOI_LOGIC_OUTS18_1": null, + "IOI_LOGIC_OUTS19_0": null, + "IOI_LOGIC_OUTS19_1": null, + "IOI_LOGIC_OUTS1_0": null, + "IOI_LOGIC_OUTS1_1": null, + "IOI_LOGIC_OUTS20_0": null, + "IOI_LOGIC_OUTS20_1": null, + "IOI_LOGIC_OUTS21_0": null, + "IOI_LOGIC_OUTS21_1": null, + "IOI_LOGIC_OUTS22_0": null, + "IOI_LOGIC_OUTS22_1": null, + "IOI_LOGIC_OUTS23_0": null, + "IOI_LOGIC_OUTS23_1": null, + "IOI_LOGIC_OUTS2_0": null, + "IOI_LOGIC_OUTS2_1": null, + "IOI_LOGIC_OUTS3_0": null, + "IOI_LOGIC_OUTS3_1": null, + "IOI_LOGIC_OUTS4_0": null, + "IOI_LOGIC_OUTS4_1": null, + "IOI_LOGIC_OUTS5_0": null, + "IOI_LOGIC_OUTS5_1": null, + "IOI_LOGIC_OUTS6_0": null, + "IOI_LOGIC_OUTS6_1": null, + "IOI_LOGIC_OUTS7_0": null, + "IOI_LOGIC_OUTS7_1": null, + "IOI_LOGIC_OUTS8_0": null, + "IOI_LOGIC_OUTS8_1": null, + "IOI_LOGIC_OUTS9_0": null, + "IOI_LOGIC_OUTS9_1": null, + "IOI_MONITOR_N": null, + "IOI_MONITOR_P": null, + "IOI_NE2A0_0": null, + "IOI_NE2A0_1": null, + "IOI_NE2A1_0": null, + "IOI_NE2A1_1": null, + "IOI_NE2A2_0": null, + "IOI_NE2A2_1": null, + "IOI_NE2A3_0": null, + "IOI_NE2A3_1": null, + "IOI_NE4BEG0_0": null, + "IOI_NE4BEG0_1": null, + "IOI_NE4BEG1_0": null, + "IOI_NE4BEG1_1": null, + "IOI_NE4BEG2_0": null, + "IOI_NE4BEG2_1": null, + "IOI_NE4BEG3_0": null, + "IOI_NE4BEG3_1": null, + "IOI_NE4C0_0": null, + "IOI_NE4C0_1": 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"IOI_ODELAY0_CNTVALUEIN2": null, + "IOI_ODELAY0_CNTVALUEIN3": null, + "IOI_ODELAY0_CNTVALUEIN4": null, + "IOI_ODELAY0_CNTVALUEOUT0": null, + "IOI_ODELAY0_CNTVALUEOUT1": null, + "IOI_ODELAY0_CNTVALUEOUT2": null, + "IOI_ODELAY0_CNTVALUEOUT3": null, + "IOI_ODELAY0_CNTVALUEOUT4": null, + "IOI_ODELAY0_INC": null, + "IOI_ODELAY0_LD": null, + "IOI_ODELAY0_LDPIPEEN": null, + "IOI_ODELAY0_REGRST": null, + "IOI_ODELAY1_C": null, + "IOI_ODELAY1_CE": null, + "IOI_ODELAY1_CINVCTRL": null, + "IOI_ODELAY1_CLKIN": null, + "IOI_ODELAY1_CNTVALUEIN0": null, + "IOI_ODELAY1_CNTVALUEIN1": null, + "IOI_ODELAY1_CNTVALUEIN2": null, + "IOI_ODELAY1_CNTVALUEIN3": null, + "IOI_ODELAY1_CNTVALUEIN4": null, + "IOI_ODELAY1_CNTVALUEOUT0": null, + "IOI_ODELAY1_CNTVALUEOUT1": null, + "IOI_ODELAY1_CNTVALUEOUT2": null, + "IOI_ODELAY1_CNTVALUEOUT3": null, + "IOI_ODELAY1_CNTVALUEOUT4": null, + "IOI_ODELAY1_INC": null, + "IOI_ODELAY1_LD": null, + "IOI_ODELAY1_LDPIPEEN": null, + "IOI_ODELAY1_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_OLOGIC1_CLK": null, + "IOI_OLOGIC1_CLKB": null, + "IOI_OLOGIC1_CLKDIV": null, + "IOI_OLOGIC1_CLKDIVB": null, + "IOI_OLOGIC1_CLKDIVFB": null, + "IOI_OLOGIC1_D1": null, + "IOI_OLOGIC1_D2": null, + "IOI_OLOGIC1_D3": null, + "IOI_OLOGIC1_D4": null, + "IOI_OLOGIC1_D5": null, + "IOI_OLOGIC1_D6": null, + "IOI_OLOGIC1_D7": null, + "IOI_OLOGIC1_D8": null, + "IOI_OLOGIC1_IOCLKGLITCH": null, + "IOI_OLOGIC1_OCE": null, + "IOI_OLOGIC1_REV": null, + "IOI_OLOGIC1_SR": null, + "IOI_OLOGIC1_T1": null, + "IOI_OLOGIC1_T2": null, + "IOI_OLOGIC1_T3": null, + "IOI_OLOGIC1_T4": null, + "IOI_OLOGIC1_TBYTEIN": null, + "IOI_OLOGIC1_TBYTEOUT": null, + "IOI_OLOGIC1_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_ICLKDIV_0": null, + "IOI_PHASER_TO_IO_ICLK_0": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLK1X_90_0": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_PHASER_TO_IO_OCLKDIV_0": null, + "IOI_PHASER_TO_IO_OCLK_0": null, + "IOI_RCLK_DIV_CE0": null, + "IOI_RCLK_DIV_CE1": null, + "IOI_RCLK_DIV_CE2": null, + "IOI_RCLK_DIV_CE2_1": null, + "IOI_RCLK_DIV_CE3": null, + "IOI_RCLK_DIV_CE3_1": null, + "IOI_RCLK_DIV_CLR0": null, + "IOI_RCLK_DIV_CLR0_1": null, + "IOI_RCLK_DIV_CLR1": null, + "IOI_RCLK_DIV_CLR1_1": null, + "IOI_RCLK_DIV_CLR2": null, + "IOI_RCLK_DIV_CLR3": null, + "IOI_RCLK_FORIO0": null, + "IOI_RCLK_FORIO1": null, + "IOI_RCLK_FORIO2": null, + "IOI_RCLK_FORIO3": null, + "IOI_SE2A0_0": null, + "IOI_SE2A0_1": null, + "IOI_SE2A1_0": null, + "IOI_SE2A1_1": null, + "IOI_SE2A2_0": null, + "IOI_SE2A2_1": null, + "IOI_SE2A3_0": null, + "IOI_SE2A3_1": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG0_1": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG1_1": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG2_1": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4BEG3_1": null, + "IOI_SE4C0_0": null, + "IOI_SE4C0_1": null, + "IOI_SE4C1_0": null, + "IOI_SE4C1_1": null, + "IOI_SE4C2_0": null, + "IOI_SE4C2_1": null, + "IOI_SE4C3_0": null, + "IOI_SE4C3_1": null, + "IOI_SW2A0_0": null, + "IOI_SW2A0_1": null, + "IOI_SW2A1_0": null, + "IOI_SW2A1_1": null, + "IOI_SW2A2_0": null, + "IOI_SW2A2_1": null, + "IOI_SW2A3_0": null, + "IOI_SW2A3_1": null, + "IOI_SW4A0_0": null, + "IOI_SW4A0_1": null, + "IOI_SW4A1_0": null, + "IOI_SW4A1_1": null, + "IOI_SW4A2_0": null, + "IOI_SW4A2_1": null, + "IOI_SW4A3_0": null, + "IOI_SW4A3_1": null, + "IOI_SW4END0_0": null, + "IOI_SW4END0_1": null, + "IOI_SW4END1_0": null, + "IOI_SW4END1_1": null, + "IOI_SW4END2_0": null, + "IOI_SW4END2_1": null, + "IOI_SW4END3_0": null, + "IOI_SW4END3_1": null, + "IOI_TBYTEIN": null, + "IOI_WL1END0_0": null, + "IOI_WL1END0_1": null, + "IOI_WL1END1_0": null, + "IOI_WL1END1_1": null, + "IOI_WL1END2_0": null, + "IOI_WL1END2_1": null, + "IOI_WL1END3_0": null, + "IOI_WL1END3_1": null, + "IOI_WR1END0_0": null, + "IOI_WR1END0_1": null, + "IOI_WR1END1_0": null, + "IOI_WR1END1_1": null, + "IOI_WR1END2_0": null, + "IOI_WR1END2_1": null, + "IOI_WR1END3_0": null, + "IOI_WR1END3_1": null, + "IOI_WW2A0_0": null, + "IOI_WW2A0_1": null, + "IOI_WW2A1_0": null, + "IOI_WW2A1_1": null, + "IOI_WW2A2_0": null, + "IOI_WW2A2_1": null, + "IOI_WW2A3_0": null, + "IOI_WW2A3_1": null, + "IOI_WW2END0_0": null, + "IOI_WW2END0_1": null, + "IOI_WW2END1_0": null, + "IOI_WW2END1_1": null, + "IOI_WW2END2_0": null, + "IOI_WW2END2_1": null, + "IOI_WW2END3_0": null, + "IOI_WW2END3_1": null, + "IOI_WW4A0_0": null, + "IOI_WW4A0_1": null, + "IOI_WW4A1_0": null, + "IOI_WW4A1_1": null, + "IOI_WW4A2_0": null, + "IOI_WW4A2_1": null, + "IOI_WW4A3_0": null, + "IOI_WW4A3_1": null, + "IOI_WW4B0_0": null, + "IOI_WW4B0_1": null, + "IOI_WW4B1_0": null, + "IOI_WW4B1_1": null, + "IOI_WW4B2_0": null, + "IOI_WW4B2_1": null, + "IOI_WW4B3_0": null, + "IOI_WW4B3_1": null, + "IOI_WW4C0_0": null, + "IOI_WW4C0_1": null, + "IOI_WW4C1_0": null, + "IOI_WW4C1_1": null, + "IOI_WW4C2_0": null, + "IOI_WW4C2_1": null, + "IOI_WW4C3_0": null, + "IOI_WW4C3_1": null, + "IOI_WW4END0_0": null, + "IOI_WW4END0_1": null, + "IOI_WW4END1_0": null, + "IOI_WW4END1_1": null, + "IOI_WW4END2_0": null, + "IOI_WW4END2_1": null, + "IOI_WW4END3_0": null, + "IOI_WW4END3_1": null, + "LIOI3_IDELAY0_IFDLY0": null, + "LIOI3_IDELAY0_IFDLY1": null, + "LIOI3_IDELAY0_IFDLY2": null, + "LIOI3_IDELAY1_IFDLY0": null, + "LIOI3_IDELAY1_IFDLY1": null, + "LIOI3_IDELAY1_IFDLY2": null, + "LIOI_DCI_T_TERM0": null, + "LIOI_DCI_T_TERM1": null, + "LIOI_DIFF_TERM_INT_EN": null, + "LIOI_I0": null, + "LIOI_I1": null, + "LIOI_I2GCLK_BOT1": null, + "LIOI_I2GCLK_TOP0": null, + "LIOI_I2GCLK_TOP1": null, + "LIOI_IBUF0": null, + "LIOI_IBUF1": null, + "LIOI_IBUF_DISABLE0": null, + "LIOI_IBUF_DISABLE1": null, + "LIOI_IDELAY0_DATAOUT": null, + "LIOI_IDELAY0_IDATAIN": null, + "LIOI_IDELAY1_DATAOUT": null, + "LIOI_IDELAY1_IDATAIN": null, + "LIOI_ILOGIC0_D": null, + "LIOI_ILOGIC0_DDLY": null, + "LIOI_ILOGIC0_OFB": null, + "LIOI_ILOGIC0_TFB": null, + "LIOI_ILOGIC1_D": null, + "LIOI_ILOGIC1_DDLY": null, + "LIOI_ILOGIC1_OFB": null, + "LIOI_ILOGIC1_TFB": null, + "LIOI_ISIN10": null, + "LIOI_ISIN11": null, + "LIOI_ISIN20": null, + "LIOI_ISIN21": null, + "LIOI_ISOUT10": null, + "LIOI_ISOUT11": null, + "LIOI_ISOUT20": null, + "LIOI_ISOUT21": null, + "LIOI_KEEPER_INT_EN_0": null, + "LIOI_KEEPER_INT_EN_1": null, + "LIOI_O0": null, + "LIOI_O1": null, + "LIOI_ODELAY0_DATAOUT": null, + "LIOI_ODELAY0_ODATAIN": null, + "LIOI_ODELAY0_OFDLY0": null, + "LIOI_ODELAY0_OFDLY1": null, + "LIOI_ODELAY0_OFDLY2": null, + "LIOI_ODELAY1_DATAOUT": null, + "LIOI_ODELAY1_ODATAIN": null, + "LIOI_ODELAY1_OFDLY0": null, + "LIOI_ODELAY1_OFDLY1": null, + "LIOI_ODELAY1_OFDLY2": null, + "LIOI_OLOGIC0_CLKDIVF": null, + "LIOI_OLOGIC0_OFB": null, + "LIOI_OLOGIC0_OQ": null, + "LIOI_OLOGIC0_TFB": null, + "LIOI_OLOGIC0_TFB_LOCAL": null, + "LIOI_OLOGIC0_TQ": null, + "LIOI_OLOGIC1_CLKDIVF": null, + "LIOI_OLOGIC1_OFB": null, + "LIOI_OLOGIC1_OQ": null, + "LIOI_OLOGIC1_TFB": null, + "LIOI_OLOGIC1_TFB_LOCAL": null, + "LIOI_OLOGIC1_TQ": null, + "LIOI_OSIN10": null, + "LIOI_OSIN11": null, + "LIOI_OSIN20": null, + "LIOI_OSIN21": null, + "LIOI_OSOUT10": null, + "LIOI_OSOUT11": null, + "LIOI_OSOUT20": null, + "LIOI_OSOUT21": null, + "LIOI_PD_INT_EN_0": null, + "LIOI_PD_INT_EN_1": null, + "LIOI_PU_INT_EN_0": null, + "LIOI_PU_INT_EN_1": null, + "LIOI_T0": null, + "LIOI_T1": null + } } diff --git a/kintex7/tile_type_LIOI3_TBYTETERM.json b/kintex7/tile_type_LIOI3_TBYTETERM.json index c502560..6195856 100644 --- a/kintex7/tile_type_LIOI3_TBYTETERM.json +++ b/kintex7/tile_type_LIOI3_TBYTETERM.json @@ -2,2900 +2,9994 @@ "pips": { "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "LIOI3_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "LIOI3_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "LIOI3_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "LIOI3_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "LIOI3_TBYTETERM.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "LIOI3_TBYTETERM.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_1" }, "LIOI3_TBYTETERM.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY1_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "LIOI3_TBYTETERM.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_1" }, "LIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "LIOI3_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "LIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "LIOI3_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "LIOI3_TBYTETERM.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "LIOI3_TBYTETERM.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "LIOI3_TBYTETERM.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "LIOI3_TBYTETERM.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_1" }, "LIOI3_TBYTETERM.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "LIOI3_TBYTETERM.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_1" }, "LIOI3_TBYTETERM.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY1_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "LIOI3_TBYTETERM.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_1" }, "LIOI3_TBYTETERM.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY1_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "LIOI3_TBYTETERM.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI3_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_1" }, "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "LIOI3_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "LIOI3_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "LIOI3_TBYTETERM.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "LIOI3_TBYTETERM.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC1_O" }, "LIOI3_TBYTETERM.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q1" }, "LIOI3_TBYTETERM.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q2" }, "LIOI3_TBYTETERM.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q3" }, "LIOI3_TBYTETERM.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q4" }, "LIOI3_TBYTETERM.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q5" }, "LIOI3_TBYTETERM.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q6" }, "LIOI3_TBYTETERM.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q7" }, "LIOI3_TBYTETERM.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q8" }, "LIOI3_TBYTETERM.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "LIOI3_TBYTETERM.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_1" }, "LIOI3_TBYTETERM.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "LIOI3_TBYTETERM.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_1" }, "LIOI3_TBYTETERM.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "LIOI3_TBYTETERM.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_1" }, "LIOI3_TBYTETERM.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "LIOI3_TBYTETERM.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_1" }, "LIOI3_TBYTETERM.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "LIOI3_TBYTETERM.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_1" }, "LIOI3_TBYTETERM.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "LIOI3_TBYTETERM.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_1" }, "LIOI3_TBYTETERM.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "LIOI3_TBYTETERM.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_1" }, "LIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "LIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "LIOI3_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "LIOI3_TBYTETERM.IOI_IMUX21_0->IOI_OLOGIC1_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "LIOI3_TBYTETERM.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_1" }, "LIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "LIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "LIOI3_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "LIOI3_TBYTETERM.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "LIOI3_TBYTETERM.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_1" }, "LIOI3_TBYTETERM.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "LIOI3_TBYTETERM.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_1" }, "LIOI3_TBYTETERM.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "LIOI3_TBYTETERM.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_1" }, "LIOI3_TBYTETERM.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "LIOI3_TBYTETERM.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_1" }, "LIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_TBYTETERM.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "LIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "LIOI3_TBYTETERM.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "LIOI3_TBYTETERM.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "LIOI3_TBYTETERM.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_1" }, "LIOI3_TBYTETERM.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "LIOI3_TBYTETERM.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_1" }, "LIOI3_TBYTETERM.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "LIOI3_TBYTETERM.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_1" }, "LIOI3_TBYTETERM.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "LIOI3_TBYTETERM.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_1" }, "LIOI3_TBYTETERM.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "LIOI3_TBYTETERM.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_1" }, "LIOI3_TBYTETERM.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "LIOI3_TBYTETERM.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_1" }, "LIOI3_TBYTETERM.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "LIOI3_TBYTETERM.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_1" }, "LIOI3_TBYTETERM.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "LIOI3_TBYTETERM.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_1" }, "LIOI3_TBYTETERM.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "LIOI3_TBYTETERM.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_1" }, "LIOI3_TBYTETERM.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "LIOI3_TBYTETERM.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_1" }, "LIOI3_TBYTETERM.IOI_IMUX42_0->IOI_OLOGIC1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "LIOI3_TBYTETERM.IOI_IMUX42_1->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_1" }, "LIOI3_TBYTETERM.IOI_IMUX43_0->IOI_OLOGIC1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "LIOI3_TBYTETERM.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_1" }, "LIOI3_TBYTETERM.IOI_IMUX44_0->IOI_OLOGIC1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "LIOI3_TBYTETERM.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_1" }, "LIOI3_TBYTETERM.IOI_IMUX45_0->IOI_OLOGIC1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "LIOI3_TBYTETERM.IOI_IMUX45_1->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_1" }, "LIOI3_TBYTETERM.IOI_IMUX46_0->IOI_OLOGIC1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "LIOI3_TBYTETERM.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_1" }, "LIOI3_TBYTETERM.IOI_IMUX47_0->IOI_OLOGIC1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "LIOI3_TBYTETERM.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_1" }, "LIOI3_TBYTETERM.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "LIOI3_TBYTETERM.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_1" }, "LIOI3_TBYTETERM.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "LIOI3_TBYTETERM.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_1" }, "LIOI3_TBYTETERM.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_DCI_T_TERM1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "LIOI3_TBYTETERM.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_1" }, "LIOI3_TBYTETERM.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "LIOI3_TBYTETERM.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_1" }, "LIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTETERM.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTETERM.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "LIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTETERM.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTETERM.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_1" }, "LIOI3_TBYTETERM.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IBUF_DISABLE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "LIOI3_TBYTETERM.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_1" }, "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", 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"res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, 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"is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, 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"is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "LIOI3_TBYTETERM.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_TBYTETERM.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "LIOI3_TBYTETERM.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "LIOI3_TBYTETERM.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "LIOI3_TBYTETERM.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_TBYTETERM.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "LIOI3_TBYTETERM.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "LIOI3_TBYTETERM.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": 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"delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0" }, "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" 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"src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0" }, "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK_0" }, "LIOI3_TBYTETERM.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK_0" }, 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"0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_ILOGIC1_DDLY" }, "LIOI3_TBYTETERM.LIOI_ISOUT10->LIOI_ISIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ISIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_ISOUT10" }, "LIOI3_TBYTETERM.LIOI_ISOUT20->LIOI_ISIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ISIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_ISOUT20" }, "LIOI3_TBYTETERM.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_OFB" }, "LIOI3_TBYTETERM.LIOI_OLOGIC0_OQ->>LIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_O0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_OQ" }, "LIOI3_TBYTETERM.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_OQ" }, "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB" }, "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" }, "LIOI3_TBYTETERM.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" }, "LIOI3_TBYTETERM.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_TQ" }, "LIOI3_TBYTETERM.LIOI_OLOGIC0_TQ->>LIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC0_TQ" }, "LIOI3_TBYTETERM.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_OFB" }, "LIOI3_TBYTETERM.LIOI_OLOGIC1_OQ->>LIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_O1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_OQ" }, "LIOI3_TBYTETERM.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_OQ" }, "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_TFB" }, "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_TFB_LOCAL" }, "LIOI3_TBYTETERM.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_ILOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OLOGIC1_TFB_LOCAL" }, "LIOI3_TBYTETERM.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "LIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_TQ" }, "LIOI3_TBYTETERM.LIOI_OLOGIC1_TQ->>LIOI_T1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "LIOI_T1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "LIOI_OLOGIC1_TQ" }, "LIOI3_TBYTETERM.LIOI_OSOUT11->LIOI_OSIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OSIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OSOUT11" }, "LIOI3_TBYTETERM.LIOI_OSOUT21->LIOI_OSIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "LIOI_OSIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "LIOI_OSOUT21" } }, @@ -2904,39 +9998,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC1_CLK", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "CLKDIVF": "LIOI_OLOGIC1_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "D1": "IOI_OLOGIC1_D1", - "D2": "IOI_OLOGIC1_D2", - "D3": "IOI_OLOGIC1_D3", - "D4": "IOI_OLOGIC1_D4", - "D5": "IOI_OLOGIC1_D5", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "OCE": "IOI_OLOGIC1_OCE", - "OFB": "LIOI_OLOGIC1_OFB", - "OQ": "LIOI_OLOGIC1_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OLOGIC1_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "LIOI_OSOUT11", - "SHIFTOUT2": "LIOI_OSOUT21", - "SR": "IOI_OLOGIC1_SR", - "T1": "IOI_OLOGIC1_T1", - "T2": "IOI_OLOGIC1_T2", - "T3": "IOI_OLOGIC1_T3", - "T4": "IOI_OLOGIC1_T4", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TCE": "IOI_OLOGIC1_TCE", - "TFB": "LIOI_OLOGIC1_TFB", - "TQ": "LIOI_OLOGIC1_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC1_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -2946,37 +10310,307 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "CE1": "IOI_ILOGIC1_CE1", - "CE2": "IOI_ILOGIC1_CE2", - "CLK": "IOI_ILOGIC1_CLK", - "CLKB": "IOI_ILOGIC1_CLKB", - "CLKDIV": "IOI_ILOGIC1_CLKDIV", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "D": "LIOI_ILOGIC1_D", - "DDLY": "LIOI_ILOGIC1_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "O": "IOI_ILOGIC1_O", - "OCLK": "IOI_ILOGIC1_OCLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "OFB": "LIOI_ILOGIC1_OFB", - "Q1": "IOI_ILOGIC1_Q1", - "Q2": "IOI_ILOGIC1_Q2", - "Q3": "IOI_ILOGIC1_Q3", - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q6": "IOI_ILOGIC1_Q6", - "Q7": "IOI_ILOGIC1_Q7", - "Q8": "IOI_ILOGIC1_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC1_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q8" + }, "REV": null, - "SHIFTIN1": "LIOI_ISIN11", - "SHIFTIN2": "LIOI_ISIN21", - "SHIFTOUT1": "LIOI_ISOUT11", - "SHIFTOUT2": "LIOI_ISOUT21", - "SR": "IOI_ILOGIC1_SR", - "TFB": "LIOI_ILOGIC1_TFB" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ISIN11" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ISIN21" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC1_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -2986,39 +10620,327 @@ "name": "X0Y1", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "LIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "LIOI_OLOGIC0_OFB", - "OQ": "LIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_OQ" + }, "REV": null, - "SHIFTIN1": "LIOI_OSIN10", - "SHIFTIN2": "LIOI_OSIN20", - "SHIFTOUT1": "LIOI_OSOUT10", - "SHIFTOUT2": "LIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "LIOI_OLOGIC0_TFB", - "TQ": "LIOI_OLOGIC0_TQ" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OSIN10" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_OSIN20" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE3", "x_coord": 0, @@ -3028,37 +10950,289 @@ "name": "X0Y1", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "LIOI_ILOGIC0_D", - "DDLY": "LIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "LIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "LIOI_ISOUT10", - "SHIFTOUT2": "LIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "LIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "LIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE3", "x_coord": 0, @@ -3068,29 +11242,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY1_C", - "CE": "IOI_IDELAY1_CE", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY1_DATAIN", - "DATAOUT": "LIOI_IDELAY1_DATAOUT", - "IDATAIN": "LIOI_IDELAY1_IDATAIN", - "IFDLY0": "LIOI3_IDELAY1_IFDLY0", - "IFDLY1": "LIOI3_IDELAY1_IFDLY1", - "IFDLY2": "LIOI3_IDELAY1_IFDLY2", - "INC": "IOI_IDELAY1_INC", - "LD": "IOI_IDELAY1_LD", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "REGRST": "IOI_IDELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_IDELAY1_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_IDELAY1_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY1_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY1_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY1_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3100,29 +11481,236 @@ "name": "X0Y1", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "LIOI_IDELAY0_DATAOUT", - "IDATAIN": "LIOI_IDELAY0_IDATAIN", - "IFDLY0": "LIOI3_IDELAY0_IFDLY0", - "IFDLY1": "LIOI3_IDELAY0_IFDLY1", - "IFDLY2": "LIOI3_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "LIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "LIOI3_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2", "x_coord": 0, @@ -3130,750 +11718,750 @@ } ], "tile_type": "LIOI3_TBYTETERM", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS0_1", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS1_1", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS2_1", - "IOI_BLOCK_OUTS3_0", - "IOI_BLOCK_OUTS3_1", - "IOI_BYP0_0", - "IOI_BYP0_1", - "IOI_BYP1_0", - "IOI_BYP1_1", - "IOI_BYP2_0", - "IOI_BYP2_1", - "IOI_BYP3_0", - "IOI_BYP3_1", - "IOI_BYP4_0", - "IOI_BYP4_1", - "IOI_BYP5_0", - "IOI_BYP5_1", - "IOI_BYP6_0", - "IOI_BYP6_1", - "IOI_BYP7_0", - "IOI_BYP7_1", - "IOI_CLK0_0", - "IOI_CLK0_1", - "IOI_CLK1_0", - "IOI_CLK1_1", - "IOI_CTRL0_0", - "IOI_CTRL0_1", - "IOI_CTRL1_0", - "IOI_CTRL1_1", - "IOI_DCI_DCIDONE", - "IOI_DCI_TSTCLK", - "IOI_DCI_TSTHLN", - "IOI_DCI_TSTHLP", - "IOI_DCI_TSTRST", - "IOI_DCI_TSTRST0", - "IOI_EE2A0_0", - "IOI_EE2A0_1", - "IOI_EE2A1_0", - "IOI_EE2A1_1", - "IOI_EE2A2_0", - "IOI_EE2A2_1", - "IOI_EE2A3_0", - "IOI_EE2A3_1", - "IOI_EE2BEG0_0", - "IOI_EE2BEG0_1", - "IOI_EE2BEG1_0", - "IOI_EE2BEG1_1", - "IOI_EE2BEG2_0", - "IOI_EE2BEG2_1", - "IOI_EE2BEG3_0", - "IOI_EE2BEG3_1", - "IOI_EE4A0_0", - "IOI_EE4A0_1", - "IOI_EE4A1_0", - "IOI_EE4A1_1", - "IOI_EE4A2_0", - "IOI_EE4A2_1", - "IOI_EE4A3_0", - "IOI_EE4A3_1", - "IOI_EE4B0_0", - "IOI_EE4B0_1", - "IOI_EE4B1_0", - "IOI_EE4B1_1", - "IOI_EE4B2_0", - "IOI_EE4B2_1", - "IOI_EE4B3_0", - "IOI_EE4B3_1", - "IOI_EE4BEG0_0", - "IOI_EE4BEG0_1", - "IOI_EE4BEG1_0", - "IOI_EE4BEG1_1", - "IOI_EE4BEG2_0", - "IOI_EE4BEG2_1", - "IOI_EE4BEG3_0", - "IOI_EE4BEG3_1", - "IOI_EE4C0_0", - "IOI_EE4C0_1", - "IOI_EE4C1_0", - "IOI_EE4C1_1", - "IOI_EE4C2_0", - "IOI_EE4C2_1", - "IOI_EE4C3_0", - "IOI_EE4C3_1", - "IOI_EL1BEG0_0", - "IOI_EL1BEG0_1", - "IOI_EL1BEG1_0", - "IOI_EL1BEG1_1", - "IOI_EL1BEG2_0", - "IOI_EL1BEG2_1", - "IOI_EL1BEG3_0", - "IOI_EL1BEG3_1", - "IOI_ER1BEG0_0", - "IOI_ER1BEG0_1", - "IOI_ER1BEG1_0", - "IOI_ER1BEG1_1", - "IOI_ER1BEG2_0", - "IOI_ER1BEG2_1", - "IOI_ER1BEG3_0", - "IOI_ER1BEG3_1", - "IOI_FAN0_0", - "IOI_FAN0_1", - "IOI_FAN1_0", - "IOI_FAN1_1", - "IOI_FAN2_0", - "IOI_FAN2_1", - "IOI_FAN3_0", - "IOI_FAN3_1", - "IOI_FAN4_0", - "IOI_FAN4_1", - "IOI_FAN5_0", - "IOI_FAN5_1", - "IOI_FAN6_0", - "IOI_FAN6_1", - "IOI_FAN7_0", - "IOI_FAN7_1", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY1_C", - "IOI_IDELAY1_CE", - "IOI_IDELAY1_CINVCTRL", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT0", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_IDELAY1_DATAIN", - "IOI_IDELAY1_INC", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_LDPIPEEN", - "IOI_IDELAY1_REGRST", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC1_BITSLIP", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC1_CE2", - "IOI_ILOGIC1_CLK", - "IOI_ILOGIC1_CLKB", - "IOI_ILOGIC1_CLKDIV", - "IOI_ILOGIC1_CLKDIVP", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_ILOGIC1_O", - "IOI_ILOGIC1_OCLK", - "IOI_ILOGIC1_OCLKB", - "IOI_ILOGIC1_Q1", - "IOI_ILOGIC1_Q2", - "IOI_ILOGIC1_Q3", - "IOI_ILOGIC1_Q4", - "IOI_ILOGIC1_Q5", - "IOI_ILOGIC1_Q6", - "IOI_ILOGIC1_Q7", - "IOI_ILOGIC1_Q8", - "IOI_ILOGIC1_REV", - "IOI_ILOGIC1_SR", - "IOI_IMUX0_0", - "IOI_IMUX0_1", - "IOI_IMUX10_0", - "IOI_IMUX10_1", - "IOI_IMUX11_0", - "IOI_IMUX11_1", - "IOI_IMUX12_0", - "IOI_IMUX12_1", - "IOI_IMUX13_0", - "IOI_IMUX13_1", - "IOI_IMUX14_0", - "IOI_IMUX14_1", - "IOI_IMUX15_0", - "IOI_IMUX15_1", - "IOI_IMUX16_0", - "IOI_IMUX16_1", - "IOI_IMUX17_0", - "IOI_IMUX17_1", - "IOI_IMUX18_0", - "IOI_IMUX18_1", - "IOI_IMUX19_0", - "IOI_IMUX19_1", - "IOI_IMUX1_0", - "IOI_IMUX1_1", - "IOI_IMUX20_0", - "IOI_IMUX20_1", - "IOI_IMUX21_0", - "IOI_IMUX21_1", - "IOI_IMUX22_0", - "IOI_IMUX22_1", - "IOI_IMUX23_0", - "IOI_IMUX23_1", - "IOI_IMUX24_0", - "IOI_IMUX24_1", - "IOI_IMUX25_0", - "IOI_IMUX25_1", - "IOI_IMUX26_0", - "IOI_IMUX26_1", - "IOI_IMUX27_0", - "IOI_IMUX27_1", - "IOI_IMUX28_0", - "IOI_IMUX28_1", - "IOI_IMUX29_0", - "IOI_IMUX29_1", - "IOI_IMUX2_0", - "IOI_IMUX2_1", - "IOI_IMUX30_0", - "IOI_IMUX30_1", - "IOI_IMUX31_0", - "IOI_IMUX31_1", - "IOI_IMUX32_0", - "IOI_IMUX32_1", - "IOI_IMUX33_0", - "IOI_IMUX33_1", - "IOI_IMUX34_0", - "IOI_IMUX34_1", - "IOI_IMUX35_0", - "IOI_IMUX35_1", - "IOI_IMUX36_0", - "IOI_IMUX36_1", - "IOI_IMUX37_0", - "IOI_IMUX37_1", - "IOI_IMUX38_0", - "IOI_IMUX38_1", - "IOI_IMUX39_0", - "IOI_IMUX39_1", - "IOI_IMUX3_0", - "IOI_IMUX3_1", - "IOI_IMUX40_0", - "IOI_IMUX40_1", - "IOI_IMUX41_0", - "IOI_IMUX41_1", - "IOI_IMUX42_0", - "IOI_IMUX42_1", - "IOI_IMUX43_0", - "IOI_IMUX43_1", - "IOI_IMUX44_0", - "IOI_IMUX44_1", - "IOI_IMUX45_0", - "IOI_IMUX45_1", - "IOI_IMUX46_0", - "IOI_IMUX46_1", - "IOI_IMUX47_0", - "IOI_IMUX47_1", - "IOI_IMUX4_0", - "IOI_IMUX4_1", - "IOI_IMUX5_0", - "IOI_IMUX5_1", - "IOI_IMUX6_0", - "IOI_IMUX6_1", - "IOI_IMUX7_0", - "IOI_IMUX7_1", - "IOI_IMUX8_0", - "IOI_IMUX8_1", - "IOI_IMUX9_0", - "IOI_IMUX9_1", - "IOI_IMUX_RC0", - "IOI_IMUX_RC1", - "IOI_IMUX_RC2", - "IOI_IMUX_RC3", - "IOI_INT_DCI_EN", - "IOI_IOCLK0", - "IOI_IOCLK1", - "IOI_IOCLK2", - "IOI_IOCLK3", - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK5", - "IOI_LH10_0", - "IOI_LH10_1", - "IOI_LH11_0", - "IOI_LH11_1", - "IOI_LH12_0", - "IOI_LH12_1", - "IOI_LH1_0", - "IOI_LH1_1", - "IOI_LH2_0", - "IOI_LH2_1", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_LH4_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_LH5_1", - "IOI_LH6_0", - "IOI_LH6_1", - "IOI_LH7_0", - "IOI_LH7_1", - "IOI_LH8_0", - "IOI_LH8_1", - "IOI_LH9_0", - "IOI_LH9_1", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS10_1", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS11_1", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS12_1", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS13_1", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS14_1", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS15_1", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS16_1", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS17_1", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS18_1", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS1_1", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS20_1", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS21_1", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS22_1", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS23_1", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS2_1", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS3_1", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS4_1", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS5_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS6_1", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS7_1", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS9_0", - "IOI_LOGIC_OUTS9_1", - "IOI_MONITOR_N", - "IOI_MONITOR_P", - "IOI_NE2A0_0", - "IOI_NE2A0_1", - "IOI_NE2A1_0", - "IOI_NE2A1_1", - "IOI_NE2A2_0", - "IOI_NE2A2_1", - "IOI_NE2A3_0", - "IOI_NE2A3_1", - "IOI_NE4BEG0_0", - "IOI_NE4BEG0_1", - "IOI_NE4BEG1_0", - "IOI_NE4BEG1_1", - "IOI_NE4BEG2_0", - "IOI_NE4BEG2_1", - "IOI_NE4BEG3_0", - "IOI_NE4BEG3_1", - "IOI_NE4C0_0", - "IOI_NE4C0_1", - "IOI_NE4C1_0", - "IOI_NE4C1_1", - "IOI_NE4C2_0", - "IOI_NE4C2_1", - "IOI_NE4C3_0", - "IOI_NE4C3_1", - "IOI_NW2A0_0", - "IOI_NW2A0_1", - "IOI_NW2A1_0", - "IOI_NW2A1_1", - "IOI_NW2A2_0", - "IOI_NW2A2_1", - "IOI_NW2A3_0", - "IOI_NW2A3_1", - "IOI_NW4A0_0", - "IOI_NW4A0_1", - "IOI_NW4A1_0", - "IOI_NW4A1_1", - "IOI_NW4A2_0", - "IOI_NW4A2_1", - "IOI_NW4A3_0", - "IOI_NW4A3_1", - "IOI_NW4END0_0", - "IOI_NW4END0_1", - "IOI_NW4END1_0", - "IOI_NW4END1_1", - "IOI_NW4END2_0", - "IOI_NW4END2_1", - "IOI_NW4END3_0", - "IOI_NW4END3_1", - "IOI_OCLKM_0", - "IOI_OCLKM_1", - "IOI_OCLK_0", - "IOI_OCLK_1", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_ODELAY1_C", - "IOI_ODELAY1_CE", - "IOI_ODELAY1_CINVCTRL", - "IOI_ODELAY1_CLKIN", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_ODELAY1_INC", - "IOI_ODELAY1_LD", - "IOI_ODELAY1_LDPIPEEN", - "IOI_ODELAY1_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_CLK", - "IOI_OLOGIC1_CLKB", - "IOI_OLOGIC1_CLKDIV", - "IOI_OLOGIC1_CLKDIVB", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_OLOGIC1_D1", - "IOI_OLOGIC1_D2", - "IOI_OLOGIC1_D3", - "IOI_OLOGIC1_D4", - "IOI_OLOGIC1_D5", - "IOI_OLOGIC1_D6", - "IOI_OLOGIC1_D7", - "IOI_OLOGIC1_D8", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_OLOGIC1_OCE", - "IOI_OLOGIC1_REV", - "IOI_OLOGIC1_SR", - "IOI_OLOGIC1_T1", - "IOI_OLOGIC1_T2", - "IOI_OLOGIC1_T3", - "IOI_OLOGIC1_T4", - "IOI_OLOGIC1_TBYTEIN", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_OLOGIC1_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR3", - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO3", - "IOI_SE2A0_0", - "IOI_SE2A0_1", - "IOI_SE2A1_0", - "IOI_SE2A1_1", - "IOI_SE2A2_0", - "IOI_SE2A2_1", - "IOI_SE2A3_0", - "IOI_SE2A3_1", - "IOI_SE4BEG0_0", - "IOI_SE4BEG0_1", - "IOI_SE4BEG1_0", - "IOI_SE4BEG1_1", - "IOI_SE4BEG2_0", - "IOI_SE4BEG2_1", - "IOI_SE4BEG3_0", - "IOI_SE4BEG3_1", - "IOI_SE4C0_0", - "IOI_SE4C0_1", - "IOI_SE4C1_0", - "IOI_SE4C1_1", - "IOI_SE4C2_0", - "IOI_SE4C2_1", - "IOI_SE4C3_0", - "IOI_SE4C3_1", - "IOI_SW2A0_0", - "IOI_SW2A0_1", - "IOI_SW2A1_0", - "IOI_SW2A1_1", - "IOI_SW2A2_0", - "IOI_SW2A2_1", - "IOI_SW2A3_0", - "IOI_SW2A3_1", - "IOI_SW4A0_0", - "IOI_SW4A0_1", - "IOI_SW4A1_0", - "IOI_SW4A1_1", - "IOI_SW4A2_0", - "IOI_SW4A2_1", - "IOI_SW4A3_0", - "IOI_SW4A3_1", - "IOI_SW4END0_0", - "IOI_SW4END0_1", - "IOI_SW4END1_0", - "IOI_SW4END1_1", - "IOI_SW4END2_0", - "IOI_SW4END2_1", - "IOI_SW4END3_0", - "IOI_SW4END3_1", - "IOI_TBYTEIN_TERM", - "IOI_WL1END0_0", - "IOI_WL1END0_1", - "IOI_WL1END1_0", - "IOI_WL1END1_1", - "IOI_WL1END2_0", - "IOI_WL1END2_1", - "IOI_WL1END3_0", - "IOI_WL1END3_1", - "IOI_WR1END0_0", - "IOI_WR1END0_1", - "IOI_WR1END1_0", - "IOI_WR1END1_1", - "IOI_WR1END2_0", - "IOI_WR1END2_1", - "IOI_WR1END3_0", - "IOI_WR1END3_1", - "IOI_WW2A0_0", - "IOI_WW2A0_1", - "IOI_WW2A1_0", - "IOI_WW2A1_1", - "IOI_WW2A2_0", - "IOI_WW2A2_1", - "IOI_WW2A3_0", - "IOI_WW2A3_1", - "IOI_WW2END0_0", - "IOI_WW2END0_1", - "IOI_WW2END1_0", - "IOI_WW2END1_1", - "IOI_WW2END2_0", - "IOI_WW2END2_1", - "IOI_WW2END3_0", - "IOI_WW2END3_1", - "IOI_WW4A0_0", - "IOI_WW4A0_1", - "IOI_WW4A1_0", - "IOI_WW4A1_1", - "IOI_WW4A2_0", - "IOI_WW4A2_1", - "IOI_WW4A3_0", - "IOI_WW4A3_1", - "IOI_WW4B0_0", - "IOI_WW4B0_1", - "IOI_WW4B1_0", - "IOI_WW4B1_1", - "IOI_WW4B2_0", - "IOI_WW4B2_1", - "IOI_WW4B3_0", - "IOI_WW4B3_1", - "IOI_WW4C0_0", - "IOI_WW4C0_1", - "IOI_WW4C1_0", - "IOI_WW4C1_1", - "IOI_WW4C2_0", - "IOI_WW4C2_1", - "IOI_WW4C3_0", - "IOI_WW4C3_1", - "IOI_WW4END0_0", - "IOI_WW4END0_1", - "IOI_WW4END1_0", - "IOI_WW4END1_1", - "IOI_WW4END2_0", - "IOI_WW4END2_1", - "IOI_WW4END3_0", - "IOI_WW4END3_1", - "LIOI3_IDELAY0_IFDLY0", - "LIOI3_IDELAY0_IFDLY1", - "LIOI3_IDELAY0_IFDLY2", - "LIOI3_IDELAY1_IFDLY0", - "LIOI3_IDELAY1_IFDLY1", - "LIOI3_IDELAY1_IFDLY2", - "LIOI_DCI_T_TERM0", - "LIOI_DCI_T_TERM1", - "LIOI_DIFF_TERM_INT_EN", - "LIOI_I0", - "LIOI_I1", - "LIOI_I2GCLK_BOT1", - "LIOI_I2GCLK_TOP0", - "LIOI_I2GCLK_TOP1", - "LIOI_IBUF0", - "LIOI_IBUF1", - "LIOI_IBUF_DISABLE0", - "LIOI_IBUF_DISABLE1", - "LIOI_IDELAY0_DATAOUT", - "LIOI_IDELAY0_IDATAIN", - "LIOI_IDELAY1_DATAOUT", - "LIOI_IDELAY1_IDATAIN", - "LIOI_ILOGIC0_D", - "LIOI_ILOGIC0_DDLY", - "LIOI_ILOGIC0_OFB", - "LIOI_ILOGIC0_TFB", - "LIOI_ILOGIC1_D", - "LIOI_ILOGIC1_DDLY", - "LIOI_ILOGIC1_OFB", - "LIOI_ILOGIC1_TFB", - "LIOI_ISIN10", - "LIOI_ISIN11", - "LIOI_ISIN20", - "LIOI_ISIN21", - "LIOI_ISOUT10", - "LIOI_ISOUT11", - "LIOI_ISOUT20", - "LIOI_ISOUT21", - "LIOI_KEEPER_INT_EN_0", - "LIOI_KEEPER_INT_EN_1", - "LIOI_O0", - "LIOI_O1", - "LIOI_ODELAY0_DATAOUT", - "LIOI_ODELAY0_ODATAIN", - "LIOI_ODELAY0_OFDLY0", - "LIOI_ODELAY0_OFDLY1", - "LIOI_ODELAY0_OFDLY2", - "LIOI_ODELAY1_DATAOUT", - "LIOI_ODELAY1_ODATAIN", - "LIOI_ODELAY1_OFDLY0", - "LIOI_ODELAY1_OFDLY1", - "LIOI_ODELAY1_OFDLY2", - "LIOI_OLOGIC0_CLKDIVF", - "LIOI_OLOGIC0_OFB", - "LIOI_OLOGIC0_OQ", - "LIOI_OLOGIC0_TFB", - "LIOI_OLOGIC0_TFB_LOCAL", - "LIOI_OLOGIC0_TQ", - "LIOI_OLOGIC1_CLKDIVF", - "LIOI_OLOGIC1_OFB", - "LIOI_OLOGIC1_OQ", - "LIOI_OLOGIC1_TFB", - "LIOI_OLOGIC1_TFB_LOCAL", - "LIOI_OLOGIC1_TQ", - "LIOI_OSIN10", - "LIOI_OSIN11", - "LIOI_OSIN20", - "LIOI_OSIN21", - "LIOI_OSOUT10", - "LIOI_OSOUT11", - "LIOI_OSOUT20", - "LIOI_OSOUT21", - "LIOI_PD_INT_EN_0", - "LIOI_PD_INT_EN_1", - "LIOI_PU_INT_EN_0", - "LIOI_PU_INT_EN_1", - "LIOI_T0", - "LIOI_T1" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS0_1": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS1_1": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS2_1": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BLOCK_OUTS3_1": null, + "IOI_BYP0_0": null, + "IOI_BYP0_1": null, + "IOI_BYP1_0": null, + "IOI_BYP1_1": null, + "IOI_BYP2_0": null, + "IOI_BYP2_1": null, + "IOI_BYP3_0": null, + "IOI_BYP3_1": null, + "IOI_BYP4_0": null, + "IOI_BYP4_1": null, + "IOI_BYP5_0": null, + "IOI_BYP5_1": null, + "IOI_BYP6_0": null, + "IOI_BYP6_1": null, + "IOI_BYP7_0": null, + "IOI_BYP7_1": null, + "IOI_CLK0_0": null, + "IOI_CLK0_1": null, + "IOI_CLK1_0": null, + "IOI_CLK1_1": null, + "IOI_CTRL0_0": null, + "IOI_CTRL0_1": null, + "IOI_CTRL1_0": null, + "IOI_CTRL1_1": null, + "IOI_DCI_DCIDONE": null, + "IOI_DCI_TSTCLK": null, + "IOI_DCI_TSTHLN": null, + "IOI_DCI_TSTHLP": null, + "IOI_DCI_TSTRST": null, + "IOI_DCI_TSTRST0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A0_1": null, + "IOI_EE2A1_0": null, + "IOI_EE2A1_1": null, + "IOI_EE2A2_0": null, + "IOI_EE2A2_1": null, + "IOI_EE2A3_0": null, + "IOI_EE2A3_1": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG0_1": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG1_1": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG2_1": null, + "IOI_EE2BEG3_0": null, + "IOI_EE2BEG3_1": null, + "IOI_EE4A0_0": null, + "IOI_EE4A0_1": null, + "IOI_EE4A1_0": null, + "IOI_EE4A1_1": null, + "IOI_EE4A2_0": null, + "IOI_EE4A2_1": null, + "IOI_EE4A3_0": null, + "IOI_EE4A3_1": null, + "IOI_EE4B0_0": null, + "IOI_EE4B0_1": null, + "IOI_EE4B1_0": null, + "IOI_EE4B1_1": null, + "IOI_EE4B2_0": null, + "IOI_EE4B2_1": null, + "IOI_EE4B3_0": null, + "IOI_EE4B3_1": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG0_1": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG1_1": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG2_1": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4BEG3_1": null, + "IOI_EE4C0_0": null, + "IOI_EE4C0_1": null, + "IOI_EE4C1_0": null, + "IOI_EE4C1_1": null, + "IOI_EE4C2_0": null, + "IOI_EE4C2_1": null, + "IOI_EE4C3_0": null, + "IOI_EE4C3_1": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG0_1": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG1_1": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG2_1": null, + "IOI_EL1BEG3_0": null, + "IOI_EL1BEG3_1": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG0_1": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG1_1": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG2_1": null, + "IOI_ER1BEG3_0": null, + "IOI_ER1BEG3_1": null, + "IOI_FAN0_0": null, + "IOI_FAN0_1": null, + "IOI_FAN1_0": null, + "IOI_FAN1_1": null, + "IOI_FAN2_0": null, + "IOI_FAN2_1": null, + "IOI_FAN3_0": null, + "IOI_FAN3_1": null, + "IOI_FAN4_0": null, + "IOI_FAN4_1": null, + "IOI_FAN5_0": null, + "IOI_FAN5_1": null, + "IOI_FAN6_0": null, + "IOI_FAN6_1": null, + "IOI_FAN7_0": null, + "IOI_FAN7_1": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_IDELAY1_C": null, + "IOI_IDELAY1_CE": null, + "IOI_IDELAY1_CINVCTRL": null, + "IOI_IDELAY1_CNTVALUEIN0": null, + "IOI_IDELAY1_CNTVALUEIN1": null, + "IOI_IDELAY1_CNTVALUEIN2": null, + "IOI_IDELAY1_CNTVALUEIN3": null, + "IOI_IDELAY1_CNTVALUEIN4": null, + "IOI_IDELAY1_CNTVALUEOUT0": null, + "IOI_IDELAY1_CNTVALUEOUT1": null, + "IOI_IDELAY1_CNTVALUEOUT2": null, + "IOI_IDELAY1_CNTVALUEOUT3": null, + "IOI_IDELAY1_CNTVALUEOUT4": null, + "IOI_IDELAY1_DATAIN": null, + "IOI_IDELAY1_INC": null, + "IOI_IDELAY1_LD": null, + "IOI_IDELAY1_LDPIPEEN": null, + "IOI_IDELAY1_REGRST": null, + "IOI_IDELAYCTRL_DNPULSEOUT": null, + "IOI_IDELAYCTRL_OUTN1": null, + "IOI_IDELAYCTRL_OUTN65": null, + "IOI_IDELAYCTRL_RDY": null, + "IOI_IDELAYCTRL_RST": null, + "IOI_IDELAYCTRL_UPPULSEOUT": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": 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"IOI_RCLK_DIV_CLR1": null, + "IOI_RCLK_DIV_CLR1_1": null, + "IOI_RCLK_DIV_CLR2": null, + "IOI_RCLK_DIV_CLR3": null, + "IOI_RCLK_FORIO0": null, + "IOI_RCLK_FORIO1": null, + "IOI_RCLK_FORIO2": null, + "IOI_RCLK_FORIO3": null, + "IOI_SE2A0_0": null, + "IOI_SE2A0_1": null, + "IOI_SE2A1_0": null, + "IOI_SE2A1_1": null, + "IOI_SE2A2_0": null, + "IOI_SE2A2_1": null, + "IOI_SE2A3_0": null, + "IOI_SE2A3_1": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG0_1": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG1_1": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG2_1": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4BEG3_1": null, + "IOI_SE4C0_0": null, + "IOI_SE4C0_1": null, + "IOI_SE4C1_0": null, + "IOI_SE4C1_1": null, + "IOI_SE4C2_0": null, + "IOI_SE4C2_1": null, + "IOI_SE4C3_0": null, + "IOI_SE4C3_1": null, + "IOI_SW2A0_0": null, + "IOI_SW2A0_1": null, + "IOI_SW2A1_0": null, + "IOI_SW2A1_1": null, + "IOI_SW2A2_0": null, + "IOI_SW2A2_1": null, + "IOI_SW2A3_0": null, + "IOI_SW2A3_1": null, + "IOI_SW4A0_0": null, + "IOI_SW4A0_1": null, + "IOI_SW4A1_0": null, + "IOI_SW4A1_1": null, + "IOI_SW4A2_0": null, + "IOI_SW4A2_1": null, + "IOI_SW4A3_0": null, + "IOI_SW4A3_1": null, + "IOI_SW4END0_0": null, + "IOI_SW4END0_1": null, + "IOI_SW4END1_0": null, + "IOI_SW4END1_1": null, + "IOI_SW4END2_0": null, + "IOI_SW4END2_1": null, + "IOI_SW4END3_0": null, + "IOI_SW4END3_1": null, + "IOI_TBYTEIN_TERM": null, + "IOI_WL1END0_0": null, + "IOI_WL1END0_1": null, + "IOI_WL1END1_0": null, + "IOI_WL1END1_1": null, + "IOI_WL1END2_0": null, + "IOI_WL1END2_1": null, + "IOI_WL1END3_0": null, + "IOI_WL1END3_1": null, + "IOI_WR1END0_0": null, + "IOI_WR1END0_1": null, + "IOI_WR1END1_0": null, + "IOI_WR1END1_1": null, + "IOI_WR1END2_0": null, + "IOI_WR1END2_1": null, + "IOI_WR1END3_0": null, + "IOI_WR1END3_1": null, + "IOI_WW2A0_0": null, + "IOI_WW2A0_1": null, + "IOI_WW2A1_0": null, + "IOI_WW2A1_1": null, + "IOI_WW2A2_0": null, + "IOI_WW2A2_1": null, + "IOI_WW2A3_0": null, + "IOI_WW2A3_1": null, + "IOI_WW2END0_0": null, + "IOI_WW2END0_1": null, + "IOI_WW2END1_0": null, + "IOI_WW2END1_1": null, + "IOI_WW2END2_0": null, + "IOI_WW2END2_1": null, + "IOI_WW2END3_0": null, + "IOI_WW2END3_1": null, + "IOI_WW4A0_0": null, + "IOI_WW4A0_1": null, + "IOI_WW4A1_0": null, + "IOI_WW4A1_1": null, + "IOI_WW4A2_0": null, + "IOI_WW4A2_1": null, + "IOI_WW4A3_0": null, + "IOI_WW4A3_1": null, + "IOI_WW4B0_0": null, + "IOI_WW4B0_1": null, + "IOI_WW4B1_0": null, + "IOI_WW4B1_1": null, + "IOI_WW4B2_0": null, + "IOI_WW4B2_1": null, + "IOI_WW4B3_0": null, + "IOI_WW4B3_1": null, + "IOI_WW4C0_0": null, + "IOI_WW4C0_1": null, + "IOI_WW4C1_0": null, + "IOI_WW4C1_1": null, + "IOI_WW4C2_0": null, + "IOI_WW4C2_1": null, + "IOI_WW4C3_0": null, + "IOI_WW4C3_1": null, + "IOI_WW4END0_0": null, + "IOI_WW4END0_1": null, + "IOI_WW4END1_0": null, + "IOI_WW4END1_1": null, + "IOI_WW4END2_0": null, + "IOI_WW4END2_1": null, + "IOI_WW4END3_0": null, + "IOI_WW4END3_1": null, + "LIOI3_IDELAY0_IFDLY0": null, + "LIOI3_IDELAY0_IFDLY1": null, + "LIOI3_IDELAY0_IFDLY2": null, + "LIOI3_IDELAY1_IFDLY0": null, + "LIOI3_IDELAY1_IFDLY1": null, + "LIOI3_IDELAY1_IFDLY2": null, + "LIOI_DCI_T_TERM0": null, + "LIOI_DCI_T_TERM1": null, + "LIOI_DIFF_TERM_INT_EN": null, + "LIOI_I0": null, + "LIOI_I1": null, + "LIOI_I2GCLK_BOT1": null, + "LIOI_I2GCLK_TOP0": null, + "LIOI_I2GCLK_TOP1": null, + "LIOI_IBUF0": null, + "LIOI_IBUF1": null, + "LIOI_IBUF_DISABLE0": null, + "LIOI_IBUF_DISABLE1": null, + "LIOI_IDELAY0_DATAOUT": null, + "LIOI_IDELAY0_IDATAIN": null, + "LIOI_IDELAY1_DATAOUT": null, + "LIOI_IDELAY1_IDATAIN": null, + "LIOI_ILOGIC0_D": null, + "LIOI_ILOGIC0_DDLY": null, + "LIOI_ILOGIC0_OFB": null, + "LIOI_ILOGIC0_TFB": null, + "LIOI_ILOGIC1_D": null, + "LIOI_ILOGIC1_DDLY": null, + "LIOI_ILOGIC1_OFB": null, + "LIOI_ILOGIC1_TFB": null, + "LIOI_ISIN10": null, + "LIOI_ISIN11": null, + "LIOI_ISIN20": null, + "LIOI_ISIN21": null, + "LIOI_ISOUT10": null, + "LIOI_ISOUT11": null, + "LIOI_ISOUT20": null, + "LIOI_ISOUT21": null, + "LIOI_KEEPER_INT_EN_0": null, + "LIOI_KEEPER_INT_EN_1": null, + "LIOI_O0": null, + "LIOI_O1": null, + "LIOI_ODELAY0_DATAOUT": null, + "LIOI_ODELAY0_ODATAIN": null, + "LIOI_ODELAY0_OFDLY0": null, + "LIOI_ODELAY0_OFDLY1": null, + "LIOI_ODELAY0_OFDLY2": null, + "LIOI_ODELAY1_DATAOUT": null, + "LIOI_ODELAY1_ODATAIN": null, + "LIOI_ODELAY1_OFDLY0": null, + "LIOI_ODELAY1_OFDLY1": null, + "LIOI_ODELAY1_OFDLY2": null, + "LIOI_OLOGIC0_CLKDIVF": null, + "LIOI_OLOGIC0_OFB": null, + "LIOI_OLOGIC0_OQ": null, + "LIOI_OLOGIC0_TFB": null, + "LIOI_OLOGIC0_TFB_LOCAL": null, + "LIOI_OLOGIC0_TQ": null, + "LIOI_OLOGIC1_CLKDIVF": null, + "LIOI_OLOGIC1_OFB": null, + "LIOI_OLOGIC1_OQ": null, + "LIOI_OLOGIC1_TFB": null, + "LIOI_OLOGIC1_TFB_LOCAL": null, + "LIOI_OLOGIC1_TQ": null, + "LIOI_OSIN10": null, + "LIOI_OSIN11": null, + "LIOI_OSIN20": null, + "LIOI_OSIN21": null, + "LIOI_OSOUT10": null, + "LIOI_OSOUT11": null, + "LIOI_OSOUT20": null, + "LIOI_OSOUT21": null, + "LIOI_PD_INT_EN_0": null, + "LIOI_PD_INT_EN_1": null, + "LIOI_PU_INT_EN_0": null, + "LIOI_PU_INT_EN_1": null, + "LIOI_T0": null, + "LIOI_T1": null + } } diff --git a/kintex7/tile_type_L_TERM_INT.json b/kintex7/tile_type_L_TERM_INT.json index ebf4c1d..e39b071 100644 --- a/kintex7/tile_type_L_TERM_INT.json +++ b/kintex7/tile_type_L_TERM_INT.json @@ -2,172 +2,358 @@ "pips": {}, "sites": [], "tile_type": "L_TERM_INT", - "wires": [ - "L_TERM_INT_DQS_IOTOPHASER", - "L_TERM_INT_LH0", - "L_TERM_INT_LH1", - "L_TERM_INT_LH2", - "L_TERM_INT_LH3", - "L_TERM_INT_LH4", - "L_TERM_INT_LH5", - "L_TERM_INT_NW2BEG0", - "L_TERM_INT_NW2BEG1", - "L_TERM_INT_NW2BEG2", - "L_TERM_INT_NW2BEG3", - "L_TERM_INT_NW4BEG0", - "L_TERM_INT_NW4BEG1", - "L_TERM_INT_NW4BEG2", - "L_TERM_INT_NW4BEG3", - "L_TERM_INT_NW4C0", - "L_TERM_INT_NW4C1", - "L_TERM_INT_NW4C2", - "L_TERM_INT_NW4C3", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV", - "L_TERM_INT_SW2BEG0", - "L_TERM_INT_SW2BEG1", - "L_TERM_INT_SW2BEG2", - "L_TERM_INT_SW2BEG3", - "L_TERM_INT_SW4BEG0", - "L_TERM_INT_SW4BEG1", - "L_TERM_INT_SW4BEG2", - "L_TERM_INT_SW4BEG3", - "L_TERM_INT_SW4C0", - "L_TERM_INT_SW4C1", - "L_TERM_INT_SW4C2", - "L_TERM_INT_SW4C3", - "L_TERM_INT_WL1BEG0", - "L_TERM_INT_WL1BEG1", - "L_TERM_INT_WL1BEG2", - "L_TERM_INT_WL1BEG3", - "L_TERM_INT_WR1BEG0", - "L_TERM_INT_WR1BEG1", - "L_TERM_INT_WR1BEG2", - "L_TERM_INT_WR1BEG3", - "L_TERM_INT_WW2A0", - "L_TERM_INT_WW2A1", - "L_TERM_INT_WW2A2", - "L_TERM_INT_WW2A3", - "L_TERM_INT_WW2BEG0", - "L_TERM_INT_WW2BEG1", - "L_TERM_INT_WW2BEG2", - "L_TERM_INT_WW2BEG3", - "L_TERM_INT_WW4A0", - "L_TERM_INT_WW4A1", - "L_TERM_INT_WW4A2", - "L_TERM_INT_WW4A3", - "L_TERM_INT_WW4B0", - "L_TERM_INT_WW4B1", - "L_TERM_INT_WW4B2", - "L_TERM_INT_WW4B3", - "L_TERM_INT_WW4BEG0", - "L_TERM_INT_WW4BEG1", - "L_TERM_INT_WW4BEG2", - "L_TERM_INT_WW4BEG3", - "L_TERM_INT_WW4C0", - "L_TERM_INT_WW4C1", - "L_TERM_INT_WW4C2", - "L_TERM_INT_WW4C3", - "TERM_INT_BLOCK_OUTS_L_B0", - "TERM_INT_BLOCK_OUTS_L_B1", - "TERM_INT_BLOCK_OUTS_L_B2", - "TERM_INT_BLOCK_OUTS_L_B3", - "TERM_INT_BYP0", - "TERM_INT_BYP1", - "TERM_INT_BYP2", - "TERM_INT_BYP3", - "TERM_INT_BYP4", - "TERM_INT_BYP5", - "TERM_INT_BYP6", - "TERM_INT_BYP7", - "TERM_INT_CLK0", - "TERM_INT_CLK1", - "TERM_INT_CTRL0", - "TERM_INT_CTRL1", - "TERM_INT_FAN0", - "TERM_INT_FAN1", - "TERM_INT_FAN2", - "TERM_INT_FAN3", - "TERM_INT_FAN4", - "TERM_INT_FAN5", - "TERM_INT_FAN6", - "TERM_INT_FAN7", - "TERM_INT_IMUX0", - "TERM_INT_IMUX1", - "TERM_INT_IMUX10", - "TERM_INT_IMUX11", - "TERM_INT_IMUX12", - "TERM_INT_IMUX13", - "TERM_INT_IMUX14", - "TERM_INT_IMUX15", - "TERM_INT_IMUX16", - "TERM_INT_IMUX17", - "TERM_INT_IMUX18", - "TERM_INT_IMUX19", - "TERM_INT_IMUX2", - "TERM_INT_IMUX20", - "TERM_INT_IMUX21", - "TERM_INT_IMUX22", - "TERM_INT_IMUX23", - "TERM_INT_IMUX24", - "TERM_INT_IMUX25", - "TERM_INT_IMUX26", - "TERM_INT_IMUX27", - "TERM_INT_IMUX28", - "TERM_INT_IMUX29", - "TERM_INT_IMUX3", - "TERM_INT_IMUX30", - "TERM_INT_IMUX31", - "TERM_INT_IMUX32", - "TERM_INT_IMUX33", - "TERM_INT_IMUX34", - "TERM_INT_IMUX35", - "TERM_INT_IMUX36", - "TERM_INT_IMUX37", - "TERM_INT_IMUX38", - "TERM_INT_IMUX39", - "TERM_INT_IMUX4", - "TERM_INT_IMUX40", - "TERM_INT_IMUX41", - "TERM_INT_IMUX42", - "TERM_INT_IMUX43", - "TERM_INT_IMUX44", - "TERM_INT_IMUX45", - "TERM_INT_IMUX46", - "TERM_INT_IMUX47", - "TERM_INT_IMUX5", - "TERM_INT_IMUX6", - "TERM_INT_IMUX7", - "TERM_INT_IMUX8", - "TERM_INT_IMUX9", - "TERM_INT_LOGIC_OUTS_L_B0", - "TERM_INT_LOGIC_OUTS_L_B1", - "TERM_INT_LOGIC_OUTS_L_B10", - "TERM_INT_LOGIC_OUTS_L_B11", - "TERM_INT_LOGIC_OUTS_L_B12", - "TERM_INT_LOGIC_OUTS_L_B13", - "TERM_INT_LOGIC_OUTS_L_B14", - "TERM_INT_LOGIC_OUTS_L_B15", - "TERM_INT_LOGIC_OUTS_L_B16", - "TERM_INT_LOGIC_OUTS_L_B17", - "TERM_INT_LOGIC_OUTS_L_B18", - "TERM_INT_LOGIC_OUTS_L_B19", - "TERM_INT_LOGIC_OUTS_L_B2", - "TERM_INT_LOGIC_OUTS_L_B20", - "TERM_INT_LOGIC_OUTS_L_B21", - "TERM_INT_LOGIC_OUTS_L_B22", - "TERM_INT_LOGIC_OUTS_L_B23", - "TERM_INT_LOGIC_OUTS_L_B3", - "TERM_INT_LOGIC_OUTS_L_B4", - "TERM_INT_LOGIC_OUTS_L_B5", - "TERM_INT_LOGIC_OUTS_L_B6", - "TERM_INT_LOGIC_OUTS_L_B7", - "TERM_INT_LOGIC_OUTS_L_B8", - "TERM_INT_LOGIC_OUTS_L_B9", - "TERM_INT_MONITOR_N", - "TERM_INT_MONITOR_P" - ] + "wires": { + "L_TERM_INT_DQS_IOTOPHASER": null, + "L_TERM_INT_LH0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_LH1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_LH2": { + "cap": "13.120", + "res": "4.520" + }, + "L_TERM_INT_LH3": { + "cap": "13.120", + "res": "4.520" + }, + "L_TERM_INT_LH4": { + "cap": "13.120", + "res": "4.520" + }, + "L_TERM_INT_LH5": { + "cap": "13.120", + "res": "4.520" + }, + "L_TERM_INT_NW2BEG0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW2BEG1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW2BEG2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW2BEG3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW4BEG0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW4BEG1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW4BEG2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW4BEG3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW4C0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW4C1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW4C2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_NW4C3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_PHASER_TO_IO_ICLK": null, + "L_TERM_INT_PHASER_TO_IO_ICLKDIV": null, + "L_TERM_INT_PHASER_TO_IO_OCLK": null, + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90": null, + "L_TERM_INT_PHASER_TO_IO_OCLKDIV": null, + "L_TERM_INT_SW2BEG0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW2BEG1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW2BEG2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW2BEG3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW4BEG0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW4BEG1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW4BEG2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW4BEG3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW4C0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW4C1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW4C2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_SW4C3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WL1BEG0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WL1BEG1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WL1BEG2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WL1BEG3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WR1BEG0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WR1BEG1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WR1BEG2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WR1BEG3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW2BEG0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW2BEG1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW2BEG2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW2BEG3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4B0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4B1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4B2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4B3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4BEG0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4BEG1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4BEG2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4BEG3": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4C0": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4C1": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4C2": { + "cap": "4.200", + "res": "87.290" + }, + "L_TERM_INT_WW4C3": { + "cap": "4.200", + "res": "87.290" + }, + "TERM_INT_BLOCK_OUTS_L_B0": null, + "TERM_INT_BLOCK_OUTS_L_B1": null, + "TERM_INT_BLOCK_OUTS_L_B2": null, + "TERM_INT_BLOCK_OUTS_L_B3": null, + "TERM_INT_BYP0": null, + "TERM_INT_BYP1": null, + "TERM_INT_BYP2": null, + "TERM_INT_BYP3": null, + "TERM_INT_BYP4": null, + "TERM_INT_BYP5": null, + "TERM_INT_BYP6": null, + "TERM_INT_BYP7": null, + "TERM_INT_CLK0": null, + "TERM_INT_CLK1": null, + "TERM_INT_CTRL0": null, + "TERM_INT_CTRL1": null, + "TERM_INT_FAN0": null, + "TERM_INT_FAN1": null, + "TERM_INT_FAN2": null, + "TERM_INT_FAN3": null, + "TERM_INT_FAN4": null, + "TERM_INT_FAN5": null, + "TERM_INT_FAN6": null, + "TERM_INT_FAN7": null, + "TERM_INT_IMUX0": null, + "TERM_INT_IMUX1": null, + "TERM_INT_IMUX10": null, + "TERM_INT_IMUX11": null, + "TERM_INT_IMUX12": null, + "TERM_INT_IMUX13": null, + "TERM_INT_IMUX14": null, + "TERM_INT_IMUX15": null, + "TERM_INT_IMUX16": null, + "TERM_INT_IMUX17": null, + "TERM_INT_IMUX18": null, + "TERM_INT_IMUX19": null, + "TERM_INT_IMUX2": null, + "TERM_INT_IMUX20": null, + "TERM_INT_IMUX21": null, + "TERM_INT_IMUX22": null, + "TERM_INT_IMUX23": null, + "TERM_INT_IMUX24": null, + "TERM_INT_IMUX25": null, + "TERM_INT_IMUX26": null, + "TERM_INT_IMUX27": null, + "TERM_INT_IMUX28": null, + "TERM_INT_IMUX29": null, + "TERM_INT_IMUX3": null, + "TERM_INT_IMUX30": null, + "TERM_INT_IMUX31": null, + "TERM_INT_IMUX32": null, + "TERM_INT_IMUX33": null, + "TERM_INT_IMUX34": null, + "TERM_INT_IMUX35": null, + "TERM_INT_IMUX36": null, + "TERM_INT_IMUX37": null, + "TERM_INT_IMUX38": null, + "TERM_INT_IMUX39": null, + "TERM_INT_IMUX4": null, + "TERM_INT_IMUX40": null, + "TERM_INT_IMUX41": null, + "TERM_INT_IMUX42": null, + "TERM_INT_IMUX43": null, + "TERM_INT_IMUX44": null, + "TERM_INT_IMUX45": null, + "TERM_INT_IMUX46": null, + "TERM_INT_IMUX47": null, + "TERM_INT_IMUX5": null, + "TERM_INT_IMUX6": null, + "TERM_INT_IMUX7": null, + "TERM_INT_IMUX8": null, + "TERM_INT_IMUX9": null, + "TERM_INT_LOGIC_OUTS_L_B0": null, + "TERM_INT_LOGIC_OUTS_L_B1": null, + "TERM_INT_LOGIC_OUTS_L_B10": null, + "TERM_INT_LOGIC_OUTS_L_B11": null, + "TERM_INT_LOGIC_OUTS_L_B12": null, + "TERM_INT_LOGIC_OUTS_L_B13": null, + "TERM_INT_LOGIC_OUTS_L_B14": null, + "TERM_INT_LOGIC_OUTS_L_B15": null, + "TERM_INT_LOGIC_OUTS_L_B16": null, + "TERM_INT_LOGIC_OUTS_L_B17": null, + "TERM_INT_LOGIC_OUTS_L_B18": null, + "TERM_INT_LOGIC_OUTS_L_B19": null, + "TERM_INT_LOGIC_OUTS_L_B2": null, + "TERM_INT_LOGIC_OUTS_L_B20": null, + "TERM_INT_LOGIC_OUTS_L_B21": null, + "TERM_INT_LOGIC_OUTS_L_B22": null, + "TERM_INT_LOGIC_OUTS_L_B23": null, + "TERM_INT_LOGIC_OUTS_L_B3": null, + "TERM_INT_LOGIC_OUTS_L_B4": null, + "TERM_INT_LOGIC_OUTS_L_B5": null, + "TERM_INT_LOGIC_OUTS_L_B6": null, + "TERM_INT_LOGIC_OUTS_L_B7": null, + "TERM_INT_LOGIC_OUTS_L_B8": null, + "TERM_INT_LOGIC_OUTS_L_B9": null, + "TERM_INT_MONITOR_N": null, + "TERM_INT_MONITOR_P": null + } } diff --git a/kintex7/tile_type_MONITOR_BOT_FUJI2.json b/kintex7/tile_type_MONITOR_BOT_FUJI2.json index 754cb1e..f8ea692 100644 --- a/kintex7/tile_type_MONITOR_BOT_FUJI2.json +++ b/kintex7/tile_type_MONITOR_BOT_FUJI2.json @@ -2,737 +2,1892 @@ "pips": { "MONITOR_BOT_FUJI2.MONITOR_ALM0->MONITOR_LOGIC_OUTS_B11_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B11_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM0" }, "MONITOR_BOT_FUJI2.MONITOR_ALM1->MONITOR_LOGIC_OUTS_B12_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B12_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM1" }, "MONITOR_BOT_FUJI2.MONITOR_ALM2->MONITOR_LOGIC_OUTS_B13_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B13_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM2" }, "MONITOR_BOT_FUJI2.MONITOR_ALM3->MONITOR_LOGIC_OUTS_B14_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B14_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM3" }, "MONITOR_BOT_FUJI2.MONITOR_ALM4->MONITOR_LOGIC_OUTS_B15_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B15_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM4" }, "MONITOR_BOT_FUJI2.MONITOR_ALM5->MONITOR_LOGIC_OUTS_B16_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B16_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM5" }, "MONITOR_BOT_FUJI2.MONITOR_ALM6->MONITOR_LOGIC_OUTS_B17_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B17_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM6" }, "MONITOR_BOT_FUJI2.MONITOR_ALM7->MONITOR_LOGIC_OUTS_B18_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B18_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_ALM7" }, "MONITOR_BOT_FUJI2.MONITOR_BUSY->MONITOR_LOGIC_OUTS_B20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_BUSY" }, "MONITOR_BOT_FUJI2.MONITOR_CHANNEL0->MONITOR_LOGIC_OUTS_B15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL0" }, "MONITOR_BOT_FUJI2.MONITOR_CHANNEL1->MONITOR_LOGIC_OUTS_B16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL1" }, "MONITOR_BOT_FUJI2.MONITOR_CHANNEL2->MONITOR_LOGIC_OUTS_B17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL2" }, "MONITOR_BOT_FUJI2.MONITOR_CHANNEL3->MONITOR_LOGIC_OUTS_B18_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B18_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL3" }, "MONITOR_BOT_FUJI2.MONITOR_CHANNEL4->MONITOR_LOGIC_OUTS_B19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CHANNEL4" }, "MONITOR_BOT_FUJI2.MONITOR_CLK1_0->MONITOR_DCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CLK1_0" }, "MONITOR_BOT_FUJI2.MONITOR_CLK1_1->MONITOR_CONVSTCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_CONVSTCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CLK1_1" }, "MONITOR_BOT_FUJI2.MONITOR_CTRL1_2->MONITOR_RESET": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_RESET", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_CTRL1_2" }, "MONITOR_BOT_FUJI2.MONITOR_DO0->MONITOR_LOGIC_OUTS_B8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO0" }, "MONITOR_BOT_FUJI2.MONITOR_DO1->MONITOR_LOGIC_OUTS_B9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO1" }, "MONITOR_BOT_FUJI2.MONITOR_DO10->MONITOR_LOGIC_OUTS_B18_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B18_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO10" }, "MONITOR_BOT_FUJI2.MONITOR_DO11->MONITOR_LOGIC_OUTS_B19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO11" }, "MONITOR_BOT_FUJI2.MONITOR_DO12->MONITOR_LOGIC_OUTS_B20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO12" }, "MONITOR_BOT_FUJI2.MONITOR_DO13->MONITOR_LOGIC_OUTS_B21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO13" }, "MONITOR_BOT_FUJI2.MONITOR_DO14->MONITOR_LOGIC_OUTS_B22_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B22_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO14" }, "MONITOR_BOT_FUJI2.MONITOR_DO15->MONITOR_LOGIC_OUTS_B23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO15" }, "MONITOR_BOT_FUJI2.MONITOR_DO2->MONITOR_LOGIC_OUTS_B10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO2" }, "MONITOR_BOT_FUJI2.MONITOR_DO3->MONITOR_LOGIC_OUTS_B11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO3" }, "MONITOR_BOT_FUJI2.MONITOR_DO4->MONITOR_LOGIC_OUTS_B12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO4" }, "MONITOR_BOT_FUJI2.MONITOR_DO5->MONITOR_LOGIC_OUTS_B13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO5" }, "MONITOR_BOT_FUJI2.MONITOR_DO6->MONITOR_LOGIC_OUTS_B14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO6" }, "MONITOR_BOT_FUJI2.MONITOR_DO7->MONITOR_LOGIC_OUTS_B15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO7" }, "MONITOR_BOT_FUJI2.MONITOR_DO8->MONITOR_LOGIC_OUTS_B16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO8" }, "MONITOR_BOT_FUJI2.MONITOR_DO9->MONITOR_LOGIC_OUTS_B17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DO9" }, "MONITOR_BOT_FUJI2.MONITOR_DRDY->MONITOR_LOGIC_OUTS_B14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_DRDY" }, "MONITOR_BOT_FUJI2.MONITOR_EOC->MONITOR_LOGIC_OUTS_B22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_EOC" }, "MONITOR_BOT_FUJI2.MONITOR_EOS->MONITOR_LOGIC_OUTS_B23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_EOS" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN11->MONITOR_VERT_VAUXN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN11" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN12_LEFT->MONITOR_VERT_VAUXN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN12_LEFT" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN3->MONITOR_VERT_VAUXN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN3" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN4_LEFT->MONITOR_VERT_VAUXN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN4_LEFT" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXN5_LEFT->MONITOR_VERT_VAUXN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN5_LEFT" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP11->MONITOR_VERT_VAUXP11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP11" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP12_LEFT->MONITOR_VERT_VAUXP12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP12_LEFT" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP3->MONITOR_VERT_VAUXP3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP3" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP4_LEFT->MONITOR_VERT_VAUXP4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP4_LEFT" }, "MONITOR_BOT_FUJI2.MONITOR_HORIZ_VAUXP5_LEFT->MONITOR_VERT_VAUXP5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP5_LEFT" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX28_0->MONITOR_DI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX28_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX29_0->MONITOR_DI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX29_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX30_0->MONITOR_DI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX30_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX31_0->MONITOR_DI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX31_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX32_0->MONITOR_DI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX32_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX33_0->MONITOR_DI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX33_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX34_0->MONITOR_DI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX34_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX34_1->MONITOR_DADDR0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX34_1" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX35_0->MONITOR_DI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX35_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX35_1->MONITOR_DADDR1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX35_1" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX36_0->MONITOR_DI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX36_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX36_1->MONITOR_DADDR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX36_1" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX37_0->MONITOR_DI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX37_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX37_1->MONITOR_DADDR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX37_1" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX38_0->MONITOR_DI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX38_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX38_1->MONITOR_DADDR4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX38_1" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX39_0->MONITOR_DI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX39_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX39_1->MONITOR_DADDR5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX39_1" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX40_0->MONITOR_DI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX40_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX40_1->MONITOR_DADDR6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DADDR6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX40_1" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX41_0->MONITOR_DI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX41_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX41_1->MONITOR_DEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX41_1" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX42_0->MONITOR_DI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX42_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX42_1->MONITOR_DWE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DWE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX42_1" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX43_0->MONITOR_DI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_DI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX43_0" }, "MONITOR_BOT_FUJI2.MONITOR_IMUX43_1->MONITOR_CONVST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_CONVST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_IMUX43_1" }, "MONITOR_BOT_FUJI2.MONITOR_JTAGBUSY->MONITOR_LOGIC_OUTS_B13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_JTAGBUSY" }, "MONITOR_BOT_FUJI2.MONITOR_JTAGLOCKED->MONITOR_LOGIC_OUTS_B11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_JTAGLOCKED" }, "MONITOR_BOT_FUJI2.MONITOR_JTAGMODIFIED->MONITOR_LOGIC_OUTS_B12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_JTAGMODIFIED" }, "MONITOR_BOT_FUJI2.MONITOR_MUXADDR0->MONITOR_LOGIC_OUTS_B19_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B19_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR0" }, "MONITOR_BOT_FUJI2.MONITOR_MUXADDR1->MONITOR_LOGIC_OUTS_B20_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B20_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR1" }, "MONITOR_BOT_FUJI2.MONITOR_MUXADDR2->MONITOR_LOGIC_OUTS_B21_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B21_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR2" }, "MONITOR_BOT_FUJI2.MONITOR_MUXADDR3->MONITOR_LOGIC_OUTS_B22_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B22_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR3" }, "MONITOR_BOT_FUJI2.MONITOR_MUXADDR4->MONITOR_LOGIC_OUTS_B23_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B23_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_MUXADDR4" }, "MONITOR_BOT_FUJI2.MONITOR_OT->MONITOR_LOGIC_OUTS_B21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_LOGIC_OUTS_B21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_OT" }, "MONITOR_BOT_FUJI2.MONITOR_SEG_VN->MONITOR_VN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_SEG_VN" }, "MONITOR_BOT_FUJI2.MONITOR_SEG_VP->MONITOR_VP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_SEG_VP" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN0->MONITOR_VAUXN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN0" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN1->MONITOR_VAUXN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN1" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN10->MONITOR_VAUXN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN10" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN11->MONITOR_VAUXN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN11" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN12->MONITOR_VAUXN12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN12" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN2->MONITOR_VAUXN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN2" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN3->MONITOR_VAUXN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN3" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN4->MONITOR_VAUXN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN4" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN5->MONITOR_VAUXN5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN5" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN8->MONITOR_VAUXN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN8" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXN9->MONITOR_VAUXN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXN9" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP0->MONITOR_VAUXP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP0" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP1->MONITOR_VAUXP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP1" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP10->MONITOR_VAUXP10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP10" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP11->MONITOR_VAUXP11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP11" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP12->MONITOR_VAUXP12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP12" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP2->MONITOR_VAUXP2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP2" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP3->MONITOR_VAUXP3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP3" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP4->MONITOR_VAUXP4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP4" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP5->MONITOR_VAUXP5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP5" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP8->MONITOR_VAUXP8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP8" }, "MONITOR_BOT_FUJI2.MONITOR_VERT_VAUXP9->MONITOR_VAUXP9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VAUXP9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_VERT_VAUXP9" } }, @@ -741,7 +1896,16 @@ "name": "X0Y1", "prefix": "IPAD", "site_pins": { - "O": "MONITOR_SEG_VN" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "MONITOR_SEG_VN" + } }, "type": "IPAD", "x_coord": 0, @@ -751,7 +1915,16 @@ "name": "X0Y0", "prefix": "IPAD", "site_pins": { - "O": "MONITOR_SEG_VP" + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "MONITOR_SEG_VP" + } }, "type": "IPAD", "x_coord": 0, @@ -761,226 +1934,2116 @@ "name": "X0Y0", "prefix": "XADC", "site_pins": { - "ALM0": "MONITOR_ALM0", - "ALM1": "MONITOR_ALM1", - "ALM2": "MONITOR_ALM2", - "ALM3": "MONITOR_ALM3", - "ALM4": "MONITOR_ALM4", - "ALM5": "MONITOR_ALM5", - "ALM6": "MONITOR_ALM6", - "ALM7": "MONITOR_ALM7", - "BUSY": "MONITOR_BUSY", - "CHANNEL0": "MONITOR_CHANNEL0", - "CHANNEL1": "MONITOR_CHANNEL1", - "CHANNEL2": "MONITOR_CHANNEL2", - "CHANNEL3": "MONITOR_CHANNEL3", - "CHANNEL4": "MONITOR_CHANNEL4", - "CONVST": "MONITOR_CONVST", - "CONVSTCLK": "MONITOR_CONVSTCLK", - "DADDR0": "MONITOR_DADDR0", - "DADDR1": "MONITOR_DADDR1", - "DADDR2": "MONITOR_DADDR2", - "DADDR3": "MONITOR_DADDR3", - "DADDR4": "MONITOR_DADDR4", - "DADDR5": "MONITOR_DADDR5", - "DADDR6": "MONITOR_DADDR6", - "DCLK": "MONITOR_DCLK", - "DEN": "MONITOR_DEN", - "DI0": "MONITOR_DI0", - "DI1": "MONITOR_DI1", - "DI10": "MONITOR_DI10", - "DI11": "MONITOR_DI11", - "DI12": "MONITOR_DI12", - "DI13": "MONITOR_DI13", - "DI14": "MONITOR_DI14", - "DI15": "MONITOR_DI15", - "DI2": "MONITOR_DI2", - "DI3": "MONITOR_DI3", - "DI4": "MONITOR_DI4", - "DI5": "MONITOR_DI5", - "DI6": "MONITOR_DI6", - "DI7": "MONITOR_DI7", - "DI8": "MONITOR_DI8", - "DI9": "MONITOR_DI9", - "DO0": "MONITOR_DO0", - "DO1": "MONITOR_DO1", - "DO10": "MONITOR_DO10", - "DO11": "MONITOR_DO11", - "DO12": "MONITOR_DO12", - "DO13": "MONITOR_DO13", - "DO14": "MONITOR_DO14", - "DO15": "MONITOR_DO15", - "DO2": "MONITOR_DO2", - "DO3": "MONITOR_DO3", - "DO4": "MONITOR_DO4", - "DO5": "MONITOR_DO5", - "DO6": "MONITOR_DO6", - "DO7": "MONITOR_DO7", - "DO8": "MONITOR_DO8", - "DO9": "MONITOR_DO9", - "DRDY": "MONITOR_DRDY", - "DWE": "MONITOR_DWE", - "EOC": "MONITOR_EOC", - "EOS": "MONITOR_EOS", - "JTAGBUSY": "MONITOR_JTAGBUSY", - "JTAGLOCKED": "MONITOR_JTAGLOCKED", - "JTAGMODIFIED": "MONITOR_JTAGMODIFIED", - "MUXADDR0": "MONITOR_MUXADDR0", - "MUXADDR1": "MONITOR_MUXADDR1", - "MUXADDR2": "MONITOR_MUXADDR2", - "MUXADDR3": "MONITOR_MUXADDR3", - "MUXADDR4": "MONITOR_MUXADDR4", - "OT": "MONITOR_OT", - "RESET": "MONITOR_RESET", - "TESTADCCLK0": "MONITOR_TESTADCCLK0", - "TESTADCCLK1": "MONITOR_TESTADCCLK1", - "TESTADCCLK2": "MONITOR_TESTADCCLK2", - "TESTADCCLK3": "MONITOR_TESTADCCLK3", - "TESTADCIN0": "MONITOR_TESTADCIN0", - "TESTADCIN1": "MONITOR_TESTADCIN1", - "TESTADCIN10": "MONITOR_TESTADCIN10", - "TESTADCIN11": "MONITOR_TESTADCIN11", - "TESTADCIN12": "MONITOR_TESTADCIN12", - "TESTADCIN13": "MONITOR_TESTADCIN13", - "TESTADCIN14": "MONITOR_TESTADCIN14", - "TESTADCIN15": "MONITOR_TESTADCIN15", - "TESTADCIN16": "MONITOR_TESTADCIN16", - "TESTADCIN17": "MONITOR_TESTADCIN17", - "TESTADCIN18": "MONITOR_TESTADCIN18", - "TESTADCIN19": "MONITOR_TESTADCIN19", - "TESTADCIN2": "MONITOR_TESTADCIN2", - "TESTADCIN20": "MONITOR_TESTADCIN20", - "TESTADCIN21": "MONITOR_TESTADCIN21", - "TESTADCIN210": "MONITOR_TESTADCIN210", - "TESTADCIN211": "MONITOR_TESTADCIN211", - "TESTADCIN212": "MONITOR_TESTADCIN212", - "TESTADCIN213": "MONITOR_TESTADCIN213", - "TESTADCIN214": "MONITOR_TESTADCIN214", - "TESTADCIN215": "MONITOR_TESTADCIN215", - "TESTADCIN216": "MONITOR_TESTADCIN216", - "TESTADCIN217": "MONITOR_TESTADCIN217", - "TESTADCIN218": "MONITOR_TESTADCIN218", - "TESTADCIN219": "MONITOR_TESTADCIN219", - "TESTADCIN22": "MONITOR_TESTADCIN22", - "TESTADCIN23": "MONITOR_TESTADCIN23", - "TESTADCIN24": "MONITOR_TESTADCIN24", - "TESTADCIN25": "MONITOR_TESTADCIN25", - "TESTADCIN26": "MONITOR_TESTADCIN26", - "TESTADCIN27": "MONITOR_TESTADCIN27", - "TESTADCIN28": "MONITOR_TESTADCIN28", - "TESTADCIN29": "MONITOR_TESTADCIN29", - "TESTADCIN3": "MONITOR_TESTADCIN3", - "TESTADCIN4": "MONITOR_TESTADCIN4", - "TESTADCIN5": "MONITOR_TESTADCIN5", - "TESTADCIN6": "MONITOR_TESTADCIN6", - "TESTADCIN7": "MONITOR_TESTADCIN7", - "TESTADCIN8": "MONITOR_TESTADCIN8", - "TESTADCIN9": "MONITOR_TESTADCIN9", - "TESTADCOUT0": "MONITOR_TESTADCOUT0", - "TESTADCOUT1": "MONITOR_TESTADCOUT1", - "TESTADCOUT10": "MONITOR_TESTADCOUT10", - "TESTADCOUT11": "MONITOR_TESTADCOUT11", - "TESTADCOUT12": "MONITOR_TESTADCOUT12", - "TESTADCOUT13": "MONITOR_TESTADCOUT13", - "TESTADCOUT14": "MONITOR_TESTADCOUT14", - "TESTADCOUT15": "MONITOR_TESTADCOUT15", - "TESTADCOUT16": "MONITOR_TESTADCOUT16", - "TESTADCOUT17": "MONITOR_TESTADCOUT17", - "TESTADCOUT18": "MONITOR_TESTADCOUT18", - "TESTADCOUT19": "MONITOR_TESTADCOUT19", - "TESTADCOUT2": "MONITOR_TESTADCOUT2", - "TESTADCOUT3": "MONITOR_TESTADCOUT3", - "TESTADCOUT4": "MONITOR_TESTADCOUT4", - "TESTADCOUT5": "MONITOR_TESTADCOUT5", - "TESTADCOUT6": "MONITOR_TESTADCOUT6", - "TESTADCOUT7": "MONITOR_TESTADCOUT7", - "TESTADCOUT8": "MONITOR_TESTADCOUT8", - "TESTADCOUT9": "MONITOR_TESTADCOUT9", - "TESTCAPTURE": "MONITOR_TESTCAPTURE", - "TESTDB0": "MONITOR_TESTDB0", - "TESTDB1": "MONITOR_TESTDB1", - "TESTDB10": "MONITOR_TESTDB10", - "TESTDB11": "MONITOR_TESTDB11", - "TESTDB12": "MONITOR_TESTDB12", - "TESTDB13": "MONITOR_TESTDB13", - "TESTDB14": "MONITOR_TESTDB14", - "TESTDB15": "MONITOR_TESTDB15", - "TESTDB2": "MONITOR_TESTDB2", - "TESTDB3": "MONITOR_TESTDB3", - "TESTDB4": "MONITOR_TESTDB4", - "TESTDB5": "MONITOR_TESTDB5", - "TESTDB6": "MONITOR_TESTDB6", - "TESTDB7": "MONITOR_TESTDB7", - "TESTDB8": "MONITOR_TESTDB8", - "TESTDB9": "MONITOR_TESTDB9", - "TESTDRCK": "MONITOR_TESTDRCK", - "TESTENJTAG": "MONITOR_TESTENJTAG", - "TESTRST": "MONITOR_TESTRST", - "TESTSCANCLK0": "MONITOR_TESTSCANCLK0", - "TESTSCANCLK1": "MONITOR_TESTSCANCLK1", - "TESTSCANCLK2": "MONITOR_TESTSCANCLK2", - "TESTSCANCLK3": "MONITOR_TESTSCANCLK3", - "TESTSCANCLK4": "MONITOR_TESTSCANCLK4", - "TESTSCANMODE0": "MONITOR_TESTSCANMODE0", - "TESTSCANMODE1": "MONITOR_TESTSCANMODE1", - "TESTSCANMODE2": "MONITOR_TESTSCANMODE2", - "TESTSCANMODE3": "MONITOR_TESTSCANMODE3", - "TESTSCANMODE4": "MONITOR_TESTSCANMODE4", - "TESTSCANRESET": "MONITOR_TESTSCANRESET", - "TESTSE0": "MONITOR_TESTSE0", - "TESTSE1": "MONITOR_TESTSE1", - "TESTSE2": "MONITOR_TESTSE2", - "TESTSE3": "MONITOR_TESTSE3", - "TESTSE4": "MONITOR_TESTSE4", - "TESTSEL": "MONITOR_TESTSEL", - "TESTSHIFT": "MONITOR_TESTSHIFT", - "TESTSI0": "MONITOR_TESTSI0", - "TESTSI1": "MONITOR_TESTSI1", - "TESTSI2": "MONITOR_TESTSI2", - "TESTSI3": "MONITOR_TESTSI3", - "TESTSI4": "MONITOR_TESTSI4", - "TESTSO0": "MONITOR_TESTSO0", - "TESTSO1": "MONITOR_TESTSO1", - "TESTSO2": "MONITOR_TESTSO2", - "TESTSO3": "MONITOR_TESTSO3", - "TESTSO4": "MONITOR_TESTSO4", - "TESTTDI": "MONITOR_TESTTDI", - "TESTTDO": "MONITOR_TESTTDO", - "TESTUPDATE": "MONITOR_TESTUPDATE", - "VAUXN0": "MONITOR_VAUXN0", - "VAUXN1": "MONITOR_VAUXN1", - "VAUXN10": "MONITOR_VAUXN10", - "VAUXN11": "MONITOR_VAUXN11", - "VAUXN12": "MONITOR_VAUXN12", + "ALM0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM0" + }, + "ALM1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM1" + }, + "ALM2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM2" + }, + "ALM3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM3" + }, + "ALM4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM4" + }, + "ALM5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM5" + }, + "ALM6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM6" + }, + "ALM7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_ALM7" + }, + "BUSY": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_BUSY" + }, + "CHANNEL0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL0" + }, + "CHANNEL1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL1" + }, + "CHANNEL2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL2" + }, + "CHANNEL3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL3" + }, + "CHANNEL4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_CHANNEL4" + }, + "CONVST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_CONVST" + }, + "CONVSTCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_CONVSTCLK" + }, + "DADDR0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR0" + }, + "DADDR1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR1" + }, + "DADDR2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR2" + }, + "DADDR3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR3" + }, + "DADDR4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR4" + }, + "DADDR5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR5" + }, + "DADDR6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DADDR6" + }, + "DCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DCLK" + }, + "DEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DEN" + }, + "DI0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DI0" + }, + "DI1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_DI1" + }, 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"0.000" + ], + "res": "0.0", + "wire": "MONITOR_TESTSO3" + }, + "TESTSO4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_TESTSO4" + }, + "TESTTDI": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_TESTTDI" + }, + "TESTTDO": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "MONITOR_TESTTDO" + }, + "TESTUPDATE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_TESTUPDATE" + }, + "VAUXN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN0" + }, + "VAUXN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN1" + }, + "VAUXN10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN10" + }, + "VAUXN11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN11" + }, + "VAUXN12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN12" + }, "VAUXN13": null, "VAUXN14": null, "VAUXN15": null, - "VAUXN2": "MONITOR_VAUXN2", - "VAUXN3": "MONITOR_VAUXN3", - "VAUXN4": "MONITOR_VAUXN4", - "VAUXN5": "MONITOR_VAUXN5", + "VAUXN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN2" + }, + "VAUXN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN3" + }, + "VAUXN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN4" + }, + "VAUXN5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN5" + }, "VAUXN6": null, "VAUXN7": null, - "VAUXN8": "MONITOR_VAUXN8", - "VAUXN9": "MONITOR_VAUXN9", - "VAUXP0": "MONITOR_VAUXP0", - "VAUXP1": "MONITOR_VAUXP1", - "VAUXP10": "MONITOR_VAUXP10", - "VAUXP11": "MONITOR_VAUXP11", - "VAUXP12": "MONITOR_VAUXP12", + "VAUXN8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN8" + }, + "VAUXN9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXN9" + }, + "VAUXP0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP0" + }, + "VAUXP1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP1" + }, + "VAUXP10": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP10" + }, + "VAUXP11": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP11" + }, + "VAUXP12": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP12" + }, "VAUXP13": null, "VAUXP14": null, "VAUXP15": null, - "VAUXP2": "MONITOR_VAUXP2", - "VAUXP3": "MONITOR_VAUXP3", - "VAUXP4": "MONITOR_VAUXP4", - "VAUXP5": "MONITOR_VAUXP5", + "VAUXP2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP2" + }, + "VAUXP3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP3" + }, + "VAUXP4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP4" + }, + "VAUXP5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP5" + }, "VAUXP6": null, "VAUXP7": null, - "VAUXP8": "MONITOR_VAUXP8", - "VAUXP9": "MONITOR_VAUXP9", - "VN": "MONITOR_VN", - "VP": "MONITOR_VP" + "VAUXP8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP8" + }, + "VAUXP9": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VAUXP9" + }, + "VN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VN" + }, + "VP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "MONITOR_VP" + } }, "type": "XADC", "x_coord": 0, @@ -988,2470 +4051,2470 @@ } ], "tile_type": "MONITOR_BOT_FUJI2", - "wires": [ - "MONITOR_ALM0", - "MONITOR_ALM1", - "MONITOR_ALM2", - "MONITOR_ALM3", - "MONITOR_ALM4", - "MONITOR_ALM5", - "MONITOR_ALM6", - "MONITOR_ALM7", - "MONITOR_BLOCK_OUTS_B0_0", - "MONITOR_BLOCK_OUTS_B0_1", - "MONITOR_BLOCK_OUTS_B0_2", - "MONITOR_BLOCK_OUTS_B0_3", - "MONITOR_BLOCK_OUTS_B0_4", - "MONITOR_BLOCK_OUTS_B0_5", - "MONITOR_BLOCK_OUTS_B0_6", - "MONITOR_BLOCK_OUTS_B0_7", - "MONITOR_BLOCK_OUTS_B0_8", - "MONITOR_BLOCK_OUTS_B0_9", - "MONITOR_BLOCK_OUTS_B1_0", - "MONITOR_BLOCK_OUTS_B1_1", - "MONITOR_BLOCK_OUTS_B1_2", - "MONITOR_BLOCK_OUTS_B1_3", - "MONITOR_BLOCK_OUTS_B1_4", - "MONITOR_BLOCK_OUTS_B1_5", - "MONITOR_BLOCK_OUTS_B1_6", - "MONITOR_BLOCK_OUTS_B1_7", - "MONITOR_BLOCK_OUTS_B1_8", - "MONITOR_BLOCK_OUTS_B1_9", - "MONITOR_BLOCK_OUTS_B2_0", - "MONITOR_BLOCK_OUTS_B2_1", - "MONITOR_BLOCK_OUTS_B2_2", - "MONITOR_BLOCK_OUTS_B2_3", - "MONITOR_BLOCK_OUTS_B2_4", - "MONITOR_BLOCK_OUTS_B2_5", - "MONITOR_BLOCK_OUTS_B2_6", - "MONITOR_BLOCK_OUTS_B2_7", - "MONITOR_BLOCK_OUTS_B2_8", - "MONITOR_BLOCK_OUTS_B2_9", - "MONITOR_BLOCK_OUTS_B3_0", - "MONITOR_BLOCK_OUTS_B3_1", - "MONITOR_BLOCK_OUTS_B3_2", - "MONITOR_BLOCK_OUTS_B3_3", - "MONITOR_BLOCK_OUTS_B3_4", - "MONITOR_BLOCK_OUTS_B3_5", - "MONITOR_BLOCK_OUTS_B3_6", - "MONITOR_BLOCK_OUTS_B3_7", - "MONITOR_BLOCK_OUTS_B3_8", - "MONITOR_BLOCK_OUTS_B3_9", - "MONITOR_BUSY", - "MONITOR_BYP0_0", - "MONITOR_BYP0_1", - "MONITOR_BYP0_2", - "MONITOR_BYP0_3", - "MONITOR_BYP0_4", - "MONITOR_BYP0_5", - "MONITOR_BYP0_6", - "MONITOR_BYP0_7", - "MONITOR_BYP0_8", - "MONITOR_BYP0_9", - "MONITOR_BYP1_0", - "MONITOR_BYP1_1", - "MONITOR_BYP1_2", - "MONITOR_BYP1_3", - "MONITOR_BYP1_4", - "MONITOR_BYP1_5", - "MONITOR_BYP1_6", - "MONITOR_BYP1_7", - "MONITOR_BYP1_8", - "MONITOR_BYP1_9", - "MONITOR_BYP2_0", - "MONITOR_BYP2_1", - "MONITOR_BYP2_2", - "MONITOR_BYP2_3", - "MONITOR_BYP2_4", - "MONITOR_BYP2_5", - "MONITOR_BYP2_6", - "MONITOR_BYP2_7", - "MONITOR_BYP2_8", - "MONITOR_BYP2_9", - "MONITOR_BYP3_0", - "MONITOR_BYP3_1", - "MONITOR_BYP3_2", - "MONITOR_BYP3_3", - "MONITOR_BYP3_4", - "MONITOR_BYP3_5", - "MONITOR_BYP3_6", - "MONITOR_BYP3_7", - "MONITOR_BYP3_8", - "MONITOR_BYP3_9", - "MONITOR_BYP4_0", - "MONITOR_BYP4_1", - "MONITOR_BYP4_2", - "MONITOR_BYP4_3", - "MONITOR_BYP4_4", - "MONITOR_BYP4_5", - "MONITOR_BYP4_6", - "MONITOR_BYP4_7", - "MONITOR_BYP4_8", - "MONITOR_BYP4_9", - "MONITOR_BYP5_0", - "MONITOR_BYP5_1", - "MONITOR_BYP5_2", - "MONITOR_BYP5_3", - "MONITOR_BYP5_4", - "MONITOR_BYP5_5", - "MONITOR_BYP5_6", - "MONITOR_BYP5_7", - "MONITOR_BYP5_8", - "MONITOR_BYP5_9", - "MONITOR_BYP6_0", - "MONITOR_BYP6_1", - "MONITOR_BYP6_2", - "MONITOR_BYP6_3", - "MONITOR_BYP6_4", - "MONITOR_BYP6_5", - "MONITOR_BYP6_6", - "MONITOR_BYP6_7", - "MONITOR_BYP6_8", - "MONITOR_BYP6_9", - "MONITOR_BYP7_0", - "MONITOR_BYP7_1", - "MONITOR_BYP7_2", - "MONITOR_BYP7_3", - "MONITOR_BYP7_4", - "MONITOR_BYP7_5", - "MONITOR_BYP7_6", - "MONITOR_BYP7_7", - "MONITOR_BYP7_8", - "MONITOR_BYP7_9", - "MONITOR_CHANNEL0", - "MONITOR_CHANNEL1", - "MONITOR_CHANNEL2", - "MONITOR_CHANNEL3", - "MONITOR_CHANNEL4", - "MONITOR_CLK0_0", - "MONITOR_CLK0_1", - "MONITOR_CLK0_2", - "MONITOR_CLK0_3", - "MONITOR_CLK0_4", - "MONITOR_CLK0_5", - "MONITOR_CLK0_6", - "MONITOR_CLK0_7", - "MONITOR_CLK0_8", - "MONITOR_CLK0_9", - "MONITOR_CLK1_0", - "MONITOR_CLK1_1", - "MONITOR_CLK1_2", - "MONITOR_CLK1_3", - "MONITOR_CLK1_4", - "MONITOR_CLK1_5", - "MONITOR_CLK1_6", - "MONITOR_CLK1_7", - "MONITOR_CLK1_8", - "MONITOR_CLK1_9", - "MONITOR_CONVST", - "MONITOR_CONVSTCLK", - "MONITOR_CTRL0_0", - "MONITOR_CTRL0_1", - "MONITOR_CTRL0_2", - "MONITOR_CTRL0_3", - "MONITOR_CTRL0_4", - "MONITOR_CTRL0_5", - "MONITOR_CTRL0_6", - "MONITOR_CTRL0_7", - "MONITOR_CTRL0_8", - "MONITOR_CTRL0_9", - "MONITOR_CTRL1_0", - "MONITOR_CTRL1_1", - "MONITOR_CTRL1_2", - "MONITOR_CTRL1_3", - "MONITOR_CTRL1_4", - "MONITOR_CTRL1_5", - "MONITOR_CTRL1_6", - "MONITOR_CTRL1_7", - "MONITOR_CTRL1_8", - "MONITOR_CTRL1_9", - "MONITOR_DADDR0", - "MONITOR_DADDR1", - "MONITOR_DADDR2", - "MONITOR_DADDR3", - "MONITOR_DADDR4", - "MONITOR_DADDR5", - "MONITOR_DADDR6", - "MONITOR_DCLK", - "MONITOR_DEN", - "MONITOR_DI0", - "MONITOR_DI1", - "MONITOR_DI10", - "MONITOR_DI11", - "MONITOR_DI12", - "MONITOR_DI13", - "MONITOR_DI14", - "MONITOR_DI15", - "MONITOR_DI2", - "MONITOR_DI3", - "MONITOR_DI4", - "MONITOR_DI5", - "MONITOR_DI6", - "MONITOR_DI7", - "MONITOR_DI8", - "MONITOR_DI9", - "MONITOR_DO0", - "MONITOR_DO1", - "MONITOR_DO10", - "MONITOR_DO11", - "MONITOR_DO12", - "MONITOR_DO13", - "MONITOR_DO14", - "MONITOR_DO15", - "MONITOR_DO2", - "MONITOR_DO3", - "MONITOR_DO4", - "MONITOR_DO5", - "MONITOR_DO6", - "MONITOR_DO7", - "MONITOR_DO8", - "MONITOR_DO9", - "MONITOR_DRDY", - "MONITOR_DWE", - "MONITOR_EE2A0_0", - "MONITOR_EE2A0_1", - "MONITOR_EE2A0_2", - "MONITOR_EE2A0_3", - "MONITOR_EE2A0_4", - "MONITOR_EE2A0_5", - "MONITOR_EE2A0_6", - "MONITOR_EE2A0_7", - "MONITOR_EE2A0_8", - "MONITOR_EE2A0_9", - "MONITOR_EE2A1_0", - "MONITOR_EE2A1_1", - "MONITOR_EE2A1_2", - "MONITOR_EE2A1_3", - "MONITOR_EE2A1_4", - "MONITOR_EE2A1_5", - "MONITOR_EE2A1_6", - "MONITOR_EE2A1_7", - "MONITOR_EE2A1_8", - "MONITOR_EE2A1_9", - "MONITOR_EE2A2_0", - "MONITOR_EE2A2_1", - "MONITOR_EE2A2_2", - "MONITOR_EE2A2_3", - "MONITOR_EE2A2_4", - "MONITOR_EE2A2_5", - "MONITOR_EE2A2_6", - "MONITOR_EE2A2_7", - "MONITOR_EE2A2_8", - "MONITOR_EE2A2_9", - "MONITOR_EE2A3_0", - "MONITOR_EE2A3_1", - "MONITOR_EE2A3_2", - "MONITOR_EE2A3_3", - "MONITOR_EE2A3_4", - "MONITOR_EE2A3_5", - "MONITOR_EE2A3_6", - "MONITOR_EE2A3_7", - "MONITOR_EE2A3_8", - "MONITOR_EE2A3_9", - "MONITOR_EE2BEG0_0", - "MONITOR_EE2BEG0_1", - "MONITOR_EE2BEG0_2", - "MONITOR_EE2BEG0_3", - "MONITOR_EE2BEG0_4", - "MONITOR_EE2BEG0_5", - "MONITOR_EE2BEG0_6", - "MONITOR_EE2BEG0_7", - "MONITOR_EE2BEG0_8", - "MONITOR_EE2BEG0_9", - "MONITOR_EE2BEG1_0", - "MONITOR_EE2BEG1_1", - "MONITOR_EE2BEG1_2", - "MONITOR_EE2BEG1_3", - "MONITOR_EE2BEG1_4", - "MONITOR_EE2BEG1_5", - "MONITOR_EE2BEG1_6", - "MONITOR_EE2BEG1_7", - "MONITOR_EE2BEG1_8", - "MONITOR_EE2BEG1_9", - "MONITOR_EE2BEG2_0", - "MONITOR_EE2BEG2_1", - "MONITOR_EE2BEG2_2", - "MONITOR_EE2BEG2_3", - "MONITOR_EE2BEG2_4", - "MONITOR_EE2BEG2_5", - "MONITOR_EE2BEG2_6", - "MONITOR_EE2BEG2_7", - "MONITOR_EE2BEG2_8", - "MONITOR_EE2BEG2_9", - "MONITOR_EE2BEG3_0", - "MONITOR_EE2BEG3_1", - "MONITOR_EE2BEG3_2", - "MONITOR_EE2BEG3_3", - "MONITOR_EE2BEG3_4", - "MONITOR_EE2BEG3_5", - "MONITOR_EE2BEG3_6", - "MONITOR_EE2BEG3_7", - "MONITOR_EE2BEG3_8", - "MONITOR_EE2BEG3_9", - "MONITOR_EE4A0_0", - "MONITOR_EE4A0_1", - "MONITOR_EE4A0_2", - "MONITOR_EE4A0_3", - "MONITOR_EE4A0_4", - "MONITOR_EE4A0_5", - "MONITOR_EE4A0_6", - "MONITOR_EE4A0_7", - "MONITOR_EE4A0_8", - "MONITOR_EE4A0_9", - "MONITOR_EE4A1_0", - "MONITOR_EE4A1_1", - "MONITOR_EE4A1_2", - "MONITOR_EE4A1_3", - "MONITOR_EE4A1_4", - "MONITOR_EE4A1_5", - "MONITOR_EE4A1_6", - "MONITOR_EE4A1_7", - "MONITOR_EE4A1_8", - "MONITOR_EE4A1_9", - "MONITOR_EE4A2_0", - "MONITOR_EE4A2_1", - "MONITOR_EE4A2_2", - "MONITOR_EE4A2_3", - "MONITOR_EE4A2_4", - "MONITOR_EE4A2_5", - "MONITOR_EE4A2_6", - "MONITOR_EE4A2_7", - "MONITOR_EE4A2_8", - "MONITOR_EE4A2_9", - "MONITOR_EE4A3_0", - "MONITOR_EE4A3_1", - "MONITOR_EE4A3_2", - "MONITOR_EE4A3_3", - "MONITOR_EE4A3_4", - "MONITOR_EE4A3_5", - "MONITOR_EE4A3_6", - "MONITOR_EE4A3_7", - "MONITOR_EE4A3_8", - "MONITOR_EE4A3_9", - "MONITOR_EE4B0_0", - "MONITOR_EE4B0_1", - "MONITOR_EE4B0_2", - "MONITOR_EE4B0_3", - "MONITOR_EE4B0_4", - "MONITOR_EE4B0_5", - "MONITOR_EE4B0_6", - "MONITOR_EE4B0_7", - "MONITOR_EE4B0_8", - "MONITOR_EE4B0_9", - "MONITOR_EE4B1_0", - "MONITOR_EE4B1_1", - "MONITOR_EE4B1_2", - "MONITOR_EE4B1_3", - "MONITOR_EE4B1_4", - "MONITOR_EE4B1_5", - "MONITOR_EE4B1_6", - "MONITOR_EE4B1_7", - "MONITOR_EE4B1_8", - "MONITOR_EE4B1_9", - "MONITOR_EE4B2_0", - "MONITOR_EE4B2_1", - "MONITOR_EE4B2_2", - "MONITOR_EE4B2_3", - "MONITOR_EE4B2_4", - "MONITOR_EE4B2_5", - "MONITOR_EE4B2_6", - "MONITOR_EE4B2_7", - "MONITOR_EE4B2_8", - "MONITOR_EE4B2_9", - "MONITOR_EE4B3_0", - "MONITOR_EE4B3_1", - "MONITOR_EE4B3_2", - "MONITOR_EE4B3_3", - "MONITOR_EE4B3_4", - "MONITOR_EE4B3_5", - "MONITOR_EE4B3_6", - "MONITOR_EE4B3_7", - "MONITOR_EE4B3_8", - "MONITOR_EE4B3_9", - "MONITOR_EE4BEG0_0", - "MONITOR_EE4BEG0_1", - "MONITOR_EE4BEG0_2", - "MONITOR_EE4BEG0_3", - "MONITOR_EE4BEG0_4", - "MONITOR_EE4BEG0_5", - "MONITOR_EE4BEG0_6", - "MONITOR_EE4BEG0_7", - "MONITOR_EE4BEG0_8", - "MONITOR_EE4BEG0_9", - "MONITOR_EE4BEG1_0", - "MONITOR_EE4BEG1_1", - "MONITOR_EE4BEG1_2", - "MONITOR_EE4BEG1_3", - "MONITOR_EE4BEG1_4", - "MONITOR_EE4BEG1_5", - "MONITOR_EE4BEG1_6", - "MONITOR_EE4BEG1_7", - "MONITOR_EE4BEG1_8", - "MONITOR_EE4BEG1_9", - "MONITOR_EE4BEG2_0", - "MONITOR_EE4BEG2_1", - "MONITOR_EE4BEG2_2", - "MONITOR_EE4BEG2_3", - "MONITOR_EE4BEG2_4", - "MONITOR_EE4BEG2_5", - "MONITOR_EE4BEG2_6", - "MONITOR_EE4BEG2_7", - "MONITOR_EE4BEG2_8", - "MONITOR_EE4BEG2_9", - "MONITOR_EE4BEG3_0", - "MONITOR_EE4BEG3_1", - "MONITOR_EE4BEG3_2", - "MONITOR_EE4BEG3_3", - "MONITOR_EE4BEG3_4", - "MONITOR_EE4BEG3_5", - "MONITOR_EE4BEG3_6", - "MONITOR_EE4BEG3_7", - "MONITOR_EE4BEG3_8", - "MONITOR_EE4BEG3_9", - "MONITOR_EE4C0_0", - "MONITOR_EE4C0_1", - "MONITOR_EE4C0_2", - "MONITOR_EE4C0_3", - "MONITOR_EE4C0_4", - "MONITOR_EE4C0_5", - "MONITOR_EE4C0_6", - "MONITOR_EE4C0_7", - "MONITOR_EE4C0_8", - "MONITOR_EE4C0_9", - "MONITOR_EE4C1_0", - "MONITOR_EE4C1_1", - "MONITOR_EE4C1_2", - "MONITOR_EE4C1_3", - "MONITOR_EE4C1_4", - "MONITOR_EE4C1_5", - "MONITOR_EE4C1_6", - "MONITOR_EE4C1_7", - "MONITOR_EE4C1_8", - "MONITOR_EE4C1_9", - "MONITOR_EE4C2_0", - "MONITOR_EE4C2_1", - "MONITOR_EE4C2_2", - "MONITOR_EE4C2_3", - "MONITOR_EE4C2_4", - "MONITOR_EE4C2_5", - "MONITOR_EE4C2_6", - "MONITOR_EE4C2_7", - "MONITOR_EE4C2_8", - "MONITOR_EE4C2_9", - "MONITOR_EE4C3_0", - "MONITOR_EE4C3_1", - "MONITOR_EE4C3_2", - "MONITOR_EE4C3_3", - "MONITOR_EE4C3_4", - "MONITOR_EE4C3_5", - "MONITOR_EE4C3_6", - "MONITOR_EE4C3_7", - "MONITOR_EE4C3_8", - "MONITOR_EE4C3_9", - "MONITOR_EL1BEG0_0", - "MONITOR_EL1BEG0_1", - "MONITOR_EL1BEG0_2", - "MONITOR_EL1BEG0_3", - "MONITOR_EL1BEG0_4", - "MONITOR_EL1BEG0_5", - "MONITOR_EL1BEG0_6", - "MONITOR_EL1BEG0_7", - "MONITOR_EL1BEG0_8", - "MONITOR_EL1BEG0_9", - "MONITOR_EL1BEG1_0", - "MONITOR_EL1BEG1_1", - "MONITOR_EL1BEG1_2", - "MONITOR_EL1BEG1_3", - "MONITOR_EL1BEG1_4", - "MONITOR_EL1BEG1_5", - "MONITOR_EL1BEG1_6", - "MONITOR_EL1BEG1_7", - "MONITOR_EL1BEG1_8", - "MONITOR_EL1BEG1_9", - "MONITOR_EL1BEG2_0", - "MONITOR_EL1BEG2_1", - "MONITOR_EL1BEG2_2", - "MONITOR_EL1BEG2_3", - "MONITOR_EL1BEG2_4", - "MONITOR_EL1BEG2_5", - "MONITOR_EL1BEG2_6", - "MONITOR_EL1BEG2_7", - "MONITOR_EL1BEG2_8", - "MONITOR_EL1BEG2_9", - "MONITOR_EL1BEG3_0", - "MONITOR_EL1BEG3_1", - "MONITOR_EL1BEG3_2", - "MONITOR_EL1BEG3_3", - "MONITOR_EL1BEG3_4", - "MONITOR_EL1BEG3_5", - "MONITOR_EL1BEG3_6", - "MONITOR_EL1BEG3_7", - "MONITOR_EL1BEG3_8", - "MONITOR_EL1BEG3_9", - "MONITOR_EOC", - "MONITOR_EOS", - "MONITOR_ER1BEG0_0", - "MONITOR_ER1BEG0_1", - "MONITOR_ER1BEG0_2", - "MONITOR_ER1BEG0_3", - "MONITOR_ER1BEG0_4", - "MONITOR_ER1BEG0_5", - "MONITOR_ER1BEG0_6", - "MONITOR_ER1BEG0_7", - "MONITOR_ER1BEG0_8", - "MONITOR_ER1BEG0_9", - "MONITOR_ER1BEG1_0", - "MONITOR_ER1BEG1_1", - "MONITOR_ER1BEG1_2", - "MONITOR_ER1BEG1_3", - "MONITOR_ER1BEG1_4", - "MONITOR_ER1BEG1_5", - "MONITOR_ER1BEG1_6", - "MONITOR_ER1BEG1_7", - "MONITOR_ER1BEG1_8", - "MONITOR_ER1BEG1_9", - "MONITOR_ER1BEG2_0", - "MONITOR_ER1BEG2_1", - "MONITOR_ER1BEG2_2", - "MONITOR_ER1BEG2_3", - "MONITOR_ER1BEG2_4", - "MONITOR_ER1BEG2_5", - "MONITOR_ER1BEG2_6", - "MONITOR_ER1BEG2_7", - "MONITOR_ER1BEG2_8", - "MONITOR_ER1BEG2_9", - "MONITOR_ER1BEG3_0", - "MONITOR_ER1BEG3_1", - "MONITOR_ER1BEG3_2", - "MONITOR_ER1BEG3_3", - "MONITOR_ER1BEG3_4", - "MONITOR_ER1BEG3_5", - "MONITOR_ER1BEG3_6", - "MONITOR_ER1BEG3_7", - "MONITOR_ER1BEG3_8", - "MONITOR_ER1BEG3_9", - "MONITOR_FAN0_0", - "MONITOR_FAN0_1", - "MONITOR_FAN0_2", - "MONITOR_FAN0_3", - "MONITOR_FAN0_4", - "MONITOR_FAN0_5", - "MONITOR_FAN0_6", - "MONITOR_FAN0_7", - "MONITOR_FAN0_8", - "MONITOR_FAN0_9", - "MONITOR_FAN1_0", - "MONITOR_FAN1_1", - "MONITOR_FAN1_2", - "MONITOR_FAN1_3", - "MONITOR_FAN1_4", - "MONITOR_FAN1_5", - "MONITOR_FAN1_6", - "MONITOR_FAN1_7", - "MONITOR_FAN1_8", - "MONITOR_FAN1_9", - "MONITOR_FAN2_0", - "MONITOR_FAN2_1", - "MONITOR_FAN2_2", - "MONITOR_FAN2_3", - "MONITOR_FAN2_4", - "MONITOR_FAN2_5", - "MONITOR_FAN2_6", - "MONITOR_FAN2_7", - "MONITOR_FAN2_8", - "MONITOR_FAN2_9", - "MONITOR_FAN3_0", - "MONITOR_FAN3_1", - "MONITOR_FAN3_2", - "MONITOR_FAN3_3", - "MONITOR_FAN3_4", - "MONITOR_FAN3_5", - "MONITOR_FAN3_6", - "MONITOR_FAN3_7", - "MONITOR_FAN3_8", - "MONITOR_FAN3_9", - "MONITOR_FAN4_0", - "MONITOR_FAN4_1", - "MONITOR_FAN4_2", - "MONITOR_FAN4_3", - "MONITOR_FAN4_4", - "MONITOR_FAN4_5", - "MONITOR_FAN4_6", - "MONITOR_FAN4_7", - "MONITOR_FAN4_8", - "MONITOR_FAN4_9", - "MONITOR_FAN5_0", - "MONITOR_FAN5_1", - "MONITOR_FAN5_2", - "MONITOR_FAN5_3", - "MONITOR_FAN5_4", - "MONITOR_FAN5_5", - "MONITOR_FAN5_6", - "MONITOR_FAN5_7", - "MONITOR_FAN5_8", - "MONITOR_FAN5_9", - "MONITOR_FAN6_0", - "MONITOR_FAN6_1", - "MONITOR_FAN6_2", - "MONITOR_FAN6_3", - "MONITOR_FAN6_4", - "MONITOR_FAN6_5", - "MONITOR_FAN6_6", - "MONITOR_FAN6_7", - "MONITOR_FAN6_8", - "MONITOR_FAN6_9", - "MONITOR_FAN7_0", - "MONITOR_FAN7_1", - "MONITOR_FAN7_2", - "MONITOR_FAN7_3", - "MONITOR_FAN7_4", - "MONITOR_FAN7_5", - "MONITOR_FAN7_6", - "MONITOR_FAN7_7", - "MONITOR_FAN7_8", - "MONITOR_FAN7_9", - "MONITOR_HORIZ_VAUXN11", - "MONITOR_HORIZ_VAUXN12_LEFT", - "MONITOR_HORIZ_VAUXN3", - "MONITOR_HORIZ_VAUXN4_LEFT", - "MONITOR_HORIZ_VAUXN5_LEFT", - "MONITOR_HORIZ_VAUXP11", - "MONITOR_HORIZ_VAUXP12_LEFT", - "MONITOR_HORIZ_VAUXP3", - "MONITOR_HORIZ_VAUXP4_LEFT", - "MONITOR_HORIZ_VAUXP5_LEFT", - "MONITOR_IMUX0_0", - "MONITOR_IMUX0_1", - "MONITOR_IMUX0_2", - "MONITOR_IMUX0_3", - "MONITOR_IMUX0_4", - "MONITOR_IMUX0_5", - "MONITOR_IMUX0_6", - "MONITOR_IMUX0_7", - "MONITOR_IMUX0_8", - "MONITOR_IMUX0_9", - "MONITOR_IMUX10_0", - "MONITOR_IMUX10_1", - "MONITOR_IMUX10_2", - "MONITOR_IMUX10_3", - "MONITOR_IMUX10_4", - "MONITOR_IMUX10_5", - "MONITOR_IMUX10_6", - "MONITOR_IMUX10_7", - "MONITOR_IMUX10_8", - "MONITOR_IMUX10_9", - "MONITOR_IMUX11_0", - "MONITOR_IMUX11_1", - "MONITOR_IMUX11_2", - "MONITOR_IMUX11_3", - "MONITOR_IMUX11_4", - "MONITOR_IMUX11_5", - "MONITOR_IMUX11_6", - "MONITOR_IMUX11_7", - "MONITOR_IMUX11_8", - "MONITOR_IMUX11_9", - "MONITOR_IMUX12_0", - "MONITOR_IMUX12_1", - "MONITOR_IMUX12_2", - "MONITOR_IMUX12_3", - "MONITOR_IMUX12_4", - "MONITOR_IMUX12_5", - "MONITOR_IMUX12_6", - "MONITOR_IMUX12_7", - "MONITOR_IMUX12_8", - "MONITOR_IMUX12_9", - "MONITOR_IMUX13_0", - "MONITOR_IMUX13_1", - "MONITOR_IMUX13_2", - "MONITOR_IMUX13_3", - "MONITOR_IMUX13_4", - "MONITOR_IMUX13_5", - "MONITOR_IMUX13_6", - "MONITOR_IMUX13_7", - "MONITOR_IMUX13_8", - "MONITOR_IMUX13_9", - "MONITOR_IMUX14_0", - "MONITOR_IMUX14_1", - "MONITOR_IMUX14_2", - "MONITOR_IMUX14_3", - "MONITOR_IMUX14_4", - "MONITOR_IMUX14_5", - "MONITOR_IMUX14_6", - "MONITOR_IMUX14_7", - "MONITOR_IMUX14_8", - "MONITOR_IMUX14_9", - "MONITOR_IMUX15_0", - "MONITOR_IMUX15_1", - "MONITOR_IMUX15_2", - "MONITOR_IMUX15_3", - "MONITOR_IMUX15_4", - "MONITOR_IMUX15_5", - "MONITOR_IMUX15_6", - "MONITOR_IMUX15_7", - "MONITOR_IMUX15_8", - "MONITOR_IMUX15_9", - "MONITOR_IMUX16_0", - "MONITOR_IMUX16_1", - "MONITOR_IMUX16_2", - "MONITOR_IMUX16_3", - "MONITOR_IMUX16_4", - "MONITOR_IMUX16_5", - "MONITOR_IMUX16_6", - "MONITOR_IMUX16_7", - "MONITOR_IMUX16_8", - "MONITOR_IMUX16_9", - "MONITOR_IMUX17_0", - "MONITOR_IMUX17_1", - "MONITOR_IMUX17_2", - "MONITOR_IMUX17_3", - "MONITOR_IMUX17_4", - "MONITOR_IMUX17_5", - "MONITOR_IMUX17_6", - "MONITOR_IMUX17_7", - "MONITOR_IMUX17_8", - "MONITOR_IMUX17_9", - "MONITOR_IMUX18_0", - "MONITOR_IMUX18_1", - "MONITOR_IMUX18_2", - "MONITOR_IMUX18_3", - "MONITOR_IMUX18_4", - "MONITOR_IMUX18_5", - "MONITOR_IMUX18_6", - "MONITOR_IMUX18_7", - "MONITOR_IMUX18_8", - "MONITOR_IMUX18_9", - "MONITOR_IMUX19_0", - "MONITOR_IMUX19_1", - "MONITOR_IMUX19_2", - "MONITOR_IMUX19_3", - "MONITOR_IMUX19_4", - "MONITOR_IMUX19_5", - "MONITOR_IMUX19_6", - "MONITOR_IMUX19_7", - "MONITOR_IMUX19_8", - "MONITOR_IMUX19_9", - "MONITOR_IMUX1_0", - "MONITOR_IMUX1_1", - "MONITOR_IMUX1_2", - "MONITOR_IMUX1_3", - "MONITOR_IMUX1_4", - "MONITOR_IMUX1_5", - "MONITOR_IMUX1_6", - "MONITOR_IMUX1_7", - "MONITOR_IMUX1_8", - "MONITOR_IMUX1_9", - "MONITOR_IMUX20_0", - "MONITOR_IMUX20_1", - "MONITOR_IMUX20_2", - "MONITOR_IMUX20_3", - "MONITOR_IMUX20_4", - "MONITOR_IMUX20_5", - "MONITOR_IMUX20_6", - "MONITOR_IMUX20_7", - "MONITOR_IMUX20_8", - "MONITOR_IMUX20_9", - "MONITOR_IMUX21_0", - "MONITOR_IMUX21_1", - "MONITOR_IMUX21_2", - "MONITOR_IMUX21_3", - "MONITOR_IMUX21_4", - "MONITOR_IMUX21_5", - "MONITOR_IMUX21_6", - "MONITOR_IMUX21_7", - "MONITOR_IMUX21_8", - "MONITOR_IMUX21_9", - "MONITOR_IMUX22_0", - "MONITOR_IMUX22_1", - "MONITOR_IMUX22_2", - "MONITOR_IMUX22_3", - "MONITOR_IMUX22_4", - "MONITOR_IMUX22_5", - "MONITOR_IMUX22_6", - "MONITOR_IMUX22_7", - "MONITOR_IMUX22_8", - "MONITOR_IMUX22_9", - "MONITOR_IMUX23_0", - "MONITOR_IMUX23_1", - "MONITOR_IMUX23_2", - "MONITOR_IMUX23_3", - "MONITOR_IMUX23_4", - "MONITOR_IMUX23_5", - "MONITOR_IMUX23_6", - "MONITOR_IMUX23_7", - "MONITOR_IMUX23_8", - "MONITOR_IMUX23_9", - "MONITOR_IMUX24_0", - "MONITOR_IMUX24_1", - "MONITOR_IMUX24_2", - "MONITOR_IMUX24_3", - "MONITOR_IMUX24_4", - "MONITOR_IMUX24_5", - "MONITOR_IMUX24_6", - "MONITOR_IMUX24_7", - "MONITOR_IMUX24_8", - "MONITOR_IMUX24_9", - "MONITOR_IMUX25_0", - "MONITOR_IMUX25_1", - "MONITOR_IMUX25_2", - "MONITOR_IMUX25_3", - "MONITOR_IMUX25_4", - "MONITOR_IMUX25_5", - "MONITOR_IMUX25_6", - "MONITOR_IMUX25_7", - "MONITOR_IMUX25_8", - "MONITOR_IMUX25_9", - "MONITOR_IMUX26_0", - "MONITOR_IMUX26_1", - "MONITOR_IMUX26_2", - "MONITOR_IMUX26_3", - "MONITOR_IMUX26_4", - "MONITOR_IMUX26_5", - "MONITOR_IMUX26_6", - "MONITOR_IMUX26_7", - "MONITOR_IMUX26_8", - "MONITOR_IMUX26_9", - "MONITOR_IMUX27_0", - "MONITOR_IMUX27_1", - "MONITOR_IMUX27_2", - "MONITOR_IMUX27_3", - "MONITOR_IMUX27_4", - "MONITOR_IMUX27_5", - "MONITOR_IMUX27_6", - "MONITOR_IMUX27_7", - "MONITOR_IMUX27_8", - "MONITOR_IMUX27_9", - "MONITOR_IMUX28_0", - "MONITOR_IMUX28_1", - "MONITOR_IMUX28_2", - "MONITOR_IMUX28_3", - "MONITOR_IMUX28_4", - "MONITOR_IMUX28_5", - "MONITOR_IMUX28_6", - "MONITOR_IMUX28_7", - "MONITOR_IMUX28_8", - "MONITOR_IMUX28_9", - "MONITOR_IMUX29_0", - "MONITOR_IMUX29_1", - "MONITOR_IMUX29_2", - "MONITOR_IMUX29_3", - "MONITOR_IMUX29_4", - "MONITOR_IMUX29_5", - "MONITOR_IMUX29_6", - "MONITOR_IMUX29_7", - "MONITOR_IMUX29_8", - "MONITOR_IMUX29_9", - "MONITOR_IMUX2_0", - "MONITOR_IMUX2_1", - "MONITOR_IMUX2_2", - "MONITOR_IMUX2_3", - "MONITOR_IMUX2_4", - "MONITOR_IMUX2_5", - "MONITOR_IMUX2_6", - "MONITOR_IMUX2_7", - "MONITOR_IMUX2_8", - "MONITOR_IMUX2_9", - "MONITOR_IMUX30_0", - "MONITOR_IMUX30_1", - "MONITOR_IMUX30_2", - "MONITOR_IMUX30_3", - "MONITOR_IMUX30_4", - "MONITOR_IMUX30_5", - "MONITOR_IMUX30_6", - "MONITOR_IMUX30_7", - "MONITOR_IMUX30_8", - "MONITOR_IMUX30_9", - "MONITOR_IMUX31_0", - "MONITOR_IMUX31_1", - "MONITOR_IMUX31_2", - "MONITOR_IMUX31_3", - "MONITOR_IMUX31_4", - "MONITOR_IMUX31_5", - "MONITOR_IMUX31_6", - "MONITOR_IMUX31_7", - "MONITOR_IMUX31_8", - "MONITOR_IMUX31_9", - "MONITOR_IMUX32_0", - "MONITOR_IMUX32_1", - "MONITOR_IMUX32_2", - "MONITOR_IMUX32_3", - "MONITOR_IMUX32_4", - "MONITOR_IMUX32_5", - "MONITOR_IMUX32_6", - "MONITOR_IMUX32_7", - "MONITOR_IMUX32_8", - "MONITOR_IMUX32_9", - "MONITOR_IMUX33_0", - "MONITOR_IMUX33_1", - "MONITOR_IMUX33_2", - "MONITOR_IMUX33_3", - "MONITOR_IMUX33_4", - "MONITOR_IMUX33_5", - "MONITOR_IMUX33_6", - "MONITOR_IMUX33_7", - "MONITOR_IMUX33_8", - "MONITOR_IMUX33_9", - "MONITOR_IMUX34_0", - "MONITOR_IMUX34_1", - "MONITOR_IMUX34_2", - "MONITOR_IMUX34_3", - "MONITOR_IMUX34_4", - "MONITOR_IMUX34_5", - "MONITOR_IMUX34_6", - "MONITOR_IMUX34_7", - "MONITOR_IMUX34_8", - "MONITOR_IMUX34_9", - "MONITOR_IMUX35_0", - "MONITOR_IMUX35_1", - "MONITOR_IMUX35_2", - "MONITOR_IMUX35_3", - "MONITOR_IMUX35_4", - "MONITOR_IMUX35_5", - "MONITOR_IMUX35_6", - "MONITOR_IMUX35_7", - "MONITOR_IMUX35_8", - "MONITOR_IMUX35_9", - "MONITOR_IMUX36_0", - "MONITOR_IMUX36_1", - "MONITOR_IMUX36_2", - "MONITOR_IMUX36_3", - "MONITOR_IMUX36_4", - "MONITOR_IMUX36_5", - "MONITOR_IMUX36_6", - "MONITOR_IMUX36_7", - "MONITOR_IMUX36_8", - "MONITOR_IMUX36_9", - "MONITOR_IMUX37_0", - "MONITOR_IMUX37_1", - "MONITOR_IMUX37_2", - "MONITOR_IMUX37_3", - "MONITOR_IMUX37_4", - "MONITOR_IMUX37_5", - "MONITOR_IMUX37_6", - "MONITOR_IMUX37_7", - "MONITOR_IMUX37_8", - "MONITOR_IMUX37_9", - "MONITOR_IMUX38_0", - "MONITOR_IMUX38_1", - "MONITOR_IMUX38_2", - "MONITOR_IMUX38_3", - "MONITOR_IMUX38_4", - "MONITOR_IMUX38_5", - "MONITOR_IMUX38_6", - "MONITOR_IMUX38_7", - "MONITOR_IMUX38_8", - "MONITOR_IMUX38_9", - "MONITOR_IMUX39_0", - "MONITOR_IMUX39_1", - "MONITOR_IMUX39_2", - "MONITOR_IMUX39_3", - "MONITOR_IMUX39_4", - "MONITOR_IMUX39_5", - "MONITOR_IMUX39_6", - "MONITOR_IMUX39_7", - "MONITOR_IMUX39_8", - "MONITOR_IMUX39_9", - "MONITOR_IMUX3_0", - "MONITOR_IMUX3_1", - "MONITOR_IMUX3_2", - "MONITOR_IMUX3_3", - "MONITOR_IMUX3_4", - "MONITOR_IMUX3_5", - "MONITOR_IMUX3_6", - "MONITOR_IMUX3_7", - "MONITOR_IMUX3_8", - "MONITOR_IMUX3_9", - "MONITOR_IMUX40_0", - "MONITOR_IMUX40_1", - "MONITOR_IMUX40_2", - "MONITOR_IMUX40_3", - "MONITOR_IMUX40_4", - "MONITOR_IMUX40_5", - "MONITOR_IMUX40_6", - "MONITOR_IMUX40_7", - "MONITOR_IMUX40_8", - "MONITOR_IMUX40_9", - "MONITOR_IMUX41_0", - "MONITOR_IMUX41_1", - "MONITOR_IMUX41_2", - "MONITOR_IMUX41_3", - "MONITOR_IMUX41_4", - "MONITOR_IMUX41_5", - "MONITOR_IMUX41_6", - "MONITOR_IMUX41_7", - "MONITOR_IMUX41_8", - "MONITOR_IMUX41_9", - "MONITOR_IMUX42_0", - "MONITOR_IMUX42_1", - "MONITOR_IMUX42_2", - "MONITOR_IMUX42_3", - "MONITOR_IMUX42_4", - "MONITOR_IMUX42_5", - "MONITOR_IMUX42_6", - "MONITOR_IMUX42_7", - "MONITOR_IMUX42_8", - "MONITOR_IMUX42_9", - "MONITOR_IMUX43_0", - "MONITOR_IMUX43_1", - "MONITOR_IMUX43_2", - "MONITOR_IMUX43_3", - "MONITOR_IMUX43_4", - "MONITOR_IMUX43_5", - "MONITOR_IMUX43_6", - "MONITOR_IMUX43_7", - "MONITOR_IMUX43_8", - "MONITOR_IMUX43_9", - "MONITOR_IMUX44_0", - "MONITOR_IMUX44_1", - "MONITOR_IMUX44_2", - "MONITOR_IMUX44_3", - "MONITOR_IMUX44_4", - "MONITOR_IMUX44_5", - "MONITOR_IMUX44_6", - "MONITOR_IMUX44_7", - "MONITOR_IMUX44_8", - "MONITOR_IMUX44_9", - "MONITOR_IMUX45_0", - "MONITOR_IMUX45_1", - "MONITOR_IMUX45_2", - "MONITOR_IMUX45_3", - "MONITOR_IMUX45_4", - "MONITOR_IMUX45_5", - "MONITOR_IMUX45_6", - "MONITOR_IMUX45_7", - "MONITOR_IMUX45_8", - "MONITOR_IMUX45_9", - "MONITOR_IMUX46_0", - "MONITOR_IMUX46_1", - "MONITOR_IMUX46_2", - "MONITOR_IMUX46_3", - "MONITOR_IMUX46_4", - "MONITOR_IMUX46_5", - "MONITOR_IMUX46_6", - "MONITOR_IMUX46_7", - "MONITOR_IMUX46_8", - "MONITOR_IMUX46_9", - "MONITOR_IMUX47_0", - "MONITOR_IMUX47_1", - "MONITOR_IMUX47_2", - "MONITOR_IMUX47_3", - "MONITOR_IMUX47_4", - "MONITOR_IMUX47_5", - "MONITOR_IMUX47_6", - "MONITOR_IMUX47_7", - "MONITOR_IMUX47_8", - "MONITOR_IMUX47_9", - "MONITOR_IMUX4_0", - "MONITOR_IMUX4_1", - "MONITOR_IMUX4_2", - "MONITOR_IMUX4_3", - "MONITOR_IMUX4_4", - "MONITOR_IMUX4_5", - "MONITOR_IMUX4_6", - "MONITOR_IMUX4_7", - "MONITOR_IMUX4_8", - "MONITOR_IMUX4_9", - "MONITOR_IMUX5_0", - "MONITOR_IMUX5_1", - "MONITOR_IMUX5_2", - "MONITOR_IMUX5_3", - "MONITOR_IMUX5_4", - "MONITOR_IMUX5_5", - "MONITOR_IMUX5_6", - "MONITOR_IMUX5_7", - "MONITOR_IMUX5_8", - "MONITOR_IMUX5_9", - "MONITOR_IMUX6_0", - "MONITOR_IMUX6_1", - "MONITOR_IMUX6_2", - "MONITOR_IMUX6_3", - "MONITOR_IMUX6_4", - "MONITOR_IMUX6_5", - "MONITOR_IMUX6_6", - "MONITOR_IMUX6_7", - "MONITOR_IMUX6_8", - "MONITOR_IMUX6_9", - "MONITOR_IMUX7_0", - "MONITOR_IMUX7_1", - "MONITOR_IMUX7_2", - "MONITOR_IMUX7_3", - "MONITOR_IMUX7_4", - "MONITOR_IMUX7_5", - "MONITOR_IMUX7_6", - "MONITOR_IMUX7_7", - "MONITOR_IMUX7_8", - "MONITOR_IMUX7_9", - "MONITOR_IMUX8_0", - "MONITOR_IMUX8_1", - "MONITOR_IMUX8_2", - "MONITOR_IMUX8_3", - "MONITOR_IMUX8_4", - "MONITOR_IMUX8_5", - "MONITOR_IMUX8_6", - "MONITOR_IMUX8_7", - "MONITOR_IMUX8_8", - "MONITOR_IMUX8_9", - "MONITOR_IMUX9_0", - "MONITOR_IMUX9_1", - "MONITOR_IMUX9_2", - "MONITOR_IMUX9_3", - "MONITOR_IMUX9_4", - "MONITOR_IMUX9_5", - "MONITOR_IMUX9_6", - "MONITOR_IMUX9_7", - "MONITOR_IMUX9_8", - "MONITOR_IMUX9_9", - "MONITOR_JTAGBUSY", - "MONITOR_JTAGLOCKED", - "MONITOR_JTAGMODIFIED", - "MONITOR_LH10_0", - "MONITOR_LH10_1", - "MONITOR_LH10_2", - "MONITOR_LH10_3", - "MONITOR_LH10_4", - "MONITOR_LH10_5", - "MONITOR_LH10_6", - "MONITOR_LH10_7", - "MONITOR_LH10_8", - "MONITOR_LH10_9", - "MONITOR_LH11_0", - "MONITOR_LH11_1", - "MONITOR_LH11_2", - "MONITOR_LH11_3", - "MONITOR_LH11_4", - "MONITOR_LH11_5", - "MONITOR_LH11_6", - "MONITOR_LH11_7", - "MONITOR_LH11_8", - "MONITOR_LH11_9", - "MONITOR_LH12_0", - "MONITOR_LH12_1", - "MONITOR_LH12_2", - "MONITOR_LH12_3", - "MONITOR_LH12_4", - "MONITOR_LH12_5", - "MONITOR_LH12_6", - "MONITOR_LH12_7", - "MONITOR_LH12_8", - "MONITOR_LH12_9", - "MONITOR_LH1_0", - "MONITOR_LH1_1", - "MONITOR_LH1_2", - "MONITOR_LH1_3", - "MONITOR_LH1_4", - "MONITOR_LH1_5", - "MONITOR_LH1_6", - "MONITOR_LH1_7", - "MONITOR_LH1_8", - "MONITOR_LH1_9", - "MONITOR_LH2_0", - "MONITOR_LH2_1", - "MONITOR_LH2_2", - "MONITOR_LH2_3", - "MONITOR_LH2_4", - "MONITOR_LH2_5", - "MONITOR_LH2_6", - "MONITOR_LH2_7", - "MONITOR_LH2_8", - "MONITOR_LH2_9", - "MONITOR_LH3_0", - "MONITOR_LH3_1", - "MONITOR_LH3_2", - "MONITOR_LH3_3", - "MONITOR_LH3_4", - "MONITOR_LH3_5", - "MONITOR_LH3_6", - "MONITOR_LH3_7", - "MONITOR_LH3_8", - "MONITOR_LH3_9", - "MONITOR_LH4_0", - "MONITOR_LH4_1", - "MONITOR_LH4_2", - "MONITOR_LH4_3", - "MONITOR_LH4_4", - "MONITOR_LH4_5", - "MONITOR_LH4_6", - "MONITOR_LH4_7", - "MONITOR_LH4_8", - "MONITOR_LH4_9", - "MONITOR_LH5_0", - "MONITOR_LH5_1", - "MONITOR_LH5_2", - "MONITOR_LH5_3", - "MONITOR_LH5_4", - "MONITOR_LH5_5", - "MONITOR_LH5_6", - "MONITOR_LH5_7", - "MONITOR_LH5_8", - "MONITOR_LH5_9", - "MONITOR_LH6_0", - "MONITOR_LH6_1", - "MONITOR_LH6_2", - "MONITOR_LH6_3", - "MONITOR_LH6_4", - "MONITOR_LH6_5", - "MONITOR_LH6_6", - "MONITOR_LH6_7", - "MONITOR_LH6_8", - "MONITOR_LH6_9", - "MONITOR_LH7_0", - "MONITOR_LH7_1", - "MONITOR_LH7_2", - "MONITOR_LH7_3", - "MONITOR_LH7_4", - "MONITOR_LH7_5", - "MONITOR_LH7_6", - "MONITOR_LH7_7", - "MONITOR_LH7_8", - "MONITOR_LH7_9", - "MONITOR_LH8_0", - "MONITOR_LH8_1", - "MONITOR_LH8_2", - "MONITOR_LH8_3", - "MONITOR_LH8_4", - "MONITOR_LH8_5", - "MONITOR_LH8_6", - "MONITOR_LH8_7", - "MONITOR_LH8_8", - "MONITOR_LH8_9", - "MONITOR_LH9_0", - "MONITOR_LH9_1", - "MONITOR_LH9_2", - "MONITOR_LH9_3", - "MONITOR_LH9_4", - "MONITOR_LH9_5", - "MONITOR_LH9_6", - "MONITOR_LH9_7", - "MONITOR_LH9_8", - "MONITOR_LH9_9", - "MONITOR_LOGIC_OUTS_B0_0", - "MONITOR_LOGIC_OUTS_B0_1", - "MONITOR_LOGIC_OUTS_B0_2", - "MONITOR_LOGIC_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B0_4", - "MONITOR_LOGIC_OUTS_B0_5", - "MONITOR_LOGIC_OUTS_B0_6", - "MONITOR_LOGIC_OUTS_B0_7", - "MONITOR_LOGIC_OUTS_B0_8", - "MONITOR_LOGIC_OUTS_B0_9", - "MONITOR_LOGIC_OUTS_B10_0", - "MONITOR_LOGIC_OUTS_B10_1", - "MONITOR_LOGIC_OUTS_B10_2", - "MONITOR_LOGIC_OUTS_B10_3", - "MONITOR_LOGIC_OUTS_B10_4", - "MONITOR_LOGIC_OUTS_B10_5", - "MONITOR_LOGIC_OUTS_B10_6", - "MONITOR_LOGIC_OUTS_B10_7", - "MONITOR_LOGIC_OUTS_B10_8", - "MONITOR_LOGIC_OUTS_B10_9", - "MONITOR_LOGIC_OUTS_B11_0", - "MONITOR_LOGIC_OUTS_B11_1", - "MONITOR_LOGIC_OUTS_B11_2", - "MONITOR_LOGIC_OUTS_B11_3", - "MONITOR_LOGIC_OUTS_B11_4", - "MONITOR_LOGIC_OUTS_B11_5", - "MONITOR_LOGIC_OUTS_B11_6", - "MONITOR_LOGIC_OUTS_B11_7", - "MONITOR_LOGIC_OUTS_B11_8", - "MONITOR_LOGIC_OUTS_B11_9", - "MONITOR_LOGIC_OUTS_B12_0", - "MONITOR_LOGIC_OUTS_B12_1", - "MONITOR_LOGIC_OUTS_B12_2", - "MONITOR_LOGIC_OUTS_B12_3", - "MONITOR_LOGIC_OUTS_B12_4", - "MONITOR_LOGIC_OUTS_B12_5", - "MONITOR_LOGIC_OUTS_B12_6", - "MONITOR_LOGIC_OUTS_B12_7", - "MONITOR_LOGIC_OUTS_B12_8", - "MONITOR_LOGIC_OUTS_B12_9", - "MONITOR_LOGIC_OUTS_B13_0", - "MONITOR_LOGIC_OUTS_B13_1", - "MONITOR_LOGIC_OUTS_B13_2", - "MONITOR_LOGIC_OUTS_B13_3", - "MONITOR_LOGIC_OUTS_B13_4", - "MONITOR_LOGIC_OUTS_B13_5", - "MONITOR_LOGIC_OUTS_B13_6", - "MONITOR_LOGIC_OUTS_B13_7", - "MONITOR_LOGIC_OUTS_B13_8", - "MONITOR_LOGIC_OUTS_B13_9", - "MONITOR_LOGIC_OUTS_B14_0", - "MONITOR_LOGIC_OUTS_B14_1", - "MONITOR_LOGIC_OUTS_B14_2", - "MONITOR_LOGIC_OUTS_B14_3", - "MONITOR_LOGIC_OUTS_B14_4", - "MONITOR_LOGIC_OUTS_B14_5", - "MONITOR_LOGIC_OUTS_B14_6", - "MONITOR_LOGIC_OUTS_B14_7", - "MONITOR_LOGIC_OUTS_B14_8", - "MONITOR_LOGIC_OUTS_B14_9", - "MONITOR_LOGIC_OUTS_B15_0", - "MONITOR_LOGIC_OUTS_B15_1", - "MONITOR_LOGIC_OUTS_B15_2", - "MONITOR_LOGIC_OUTS_B15_3", - "MONITOR_LOGIC_OUTS_B15_4", - "MONITOR_LOGIC_OUTS_B15_5", - "MONITOR_LOGIC_OUTS_B15_6", - "MONITOR_LOGIC_OUTS_B15_7", - "MONITOR_LOGIC_OUTS_B15_8", - "MONITOR_LOGIC_OUTS_B15_9", - "MONITOR_LOGIC_OUTS_B16_0", - "MONITOR_LOGIC_OUTS_B16_1", - "MONITOR_LOGIC_OUTS_B16_2", - "MONITOR_LOGIC_OUTS_B16_3", - "MONITOR_LOGIC_OUTS_B16_4", - "MONITOR_LOGIC_OUTS_B16_5", - "MONITOR_LOGIC_OUTS_B16_6", - "MONITOR_LOGIC_OUTS_B16_7", - "MONITOR_LOGIC_OUTS_B16_8", - "MONITOR_LOGIC_OUTS_B16_9", - "MONITOR_LOGIC_OUTS_B17_0", - "MONITOR_LOGIC_OUTS_B17_1", - "MONITOR_LOGIC_OUTS_B17_2", - "MONITOR_LOGIC_OUTS_B17_3", - "MONITOR_LOGIC_OUTS_B17_4", - "MONITOR_LOGIC_OUTS_B17_5", - "MONITOR_LOGIC_OUTS_B17_6", - "MONITOR_LOGIC_OUTS_B17_7", - "MONITOR_LOGIC_OUTS_B17_8", - "MONITOR_LOGIC_OUTS_B17_9", - "MONITOR_LOGIC_OUTS_B18_0", - "MONITOR_LOGIC_OUTS_B18_1", - "MONITOR_LOGIC_OUTS_B18_2", - "MONITOR_LOGIC_OUTS_B18_3", - "MONITOR_LOGIC_OUTS_B18_4", - "MONITOR_LOGIC_OUTS_B18_5", - "MONITOR_LOGIC_OUTS_B18_6", - "MONITOR_LOGIC_OUTS_B18_7", - "MONITOR_LOGIC_OUTS_B18_8", - "MONITOR_LOGIC_OUTS_B18_9", - "MONITOR_LOGIC_OUTS_B19_0", - "MONITOR_LOGIC_OUTS_B19_1", - "MONITOR_LOGIC_OUTS_B19_2", - "MONITOR_LOGIC_OUTS_B19_3", - "MONITOR_LOGIC_OUTS_B19_4", - "MONITOR_LOGIC_OUTS_B19_5", - "MONITOR_LOGIC_OUTS_B19_6", - "MONITOR_LOGIC_OUTS_B19_7", - "MONITOR_LOGIC_OUTS_B19_8", - "MONITOR_LOGIC_OUTS_B19_9", - "MONITOR_LOGIC_OUTS_B1_0", - "MONITOR_LOGIC_OUTS_B1_1", - "MONITOR_LOGIC_OUTS_B1_2", - "MONITOR_LOGIC_OUTS_B1_3", - "MONITOR_LOGIC_OUTS_B1_4", - "MONITOR_LOGIC_OUTS_B1_5", - "MONITOR_LOGIC_OUTS_B1_6", - "MONITOR_LOGIC_OUTS_B1_7", - "MONITOR_LOGIC_OUTS_B1_8", - "MONITOR_LOGIC_OUTS_B1_9", - "MONITOR_LOGIC_OUTS_B20_0", - "MONITOR_LOGIC_OUTS_B20_1", - "MONITOR_LOGIC_OUTS_B20_2", - "MONITOR_LOGIC_OUTS_B20_3", - "MONITOR_LOGIC_OUTS_B20_4", - "MONITOR_LOGIC_OUTS_B20_5", - "MONITOR_LOGIC_OUTS_B20_6", - "MONITOR_LOGIC_OUTS_B20_7", - "MONITOR_LOGIC_OUTS_B20_8", - "MONITOR_LOGIC_OUTS_B20_9", - "MONITOR_LOGIC_OUTS_B21_0", - "MONITOR_LOGIC_OUTS_B21_1", - "MONITOR_LOGIC_OUTS_B21_2", - "MONITOR_LOGIC_OUTS_B21_3", - "MONITOR_LOGIC_OUTS_B21_4", - "MONITOR_LOGIC_OUTS_B21_5", - "MONITOR_LOGIC_OUTS_B21_6", - "MONITOR_LOGIC_OUTS_B21_7", - "MONITOR_LOGIC_OUTS_B21_8", - "MONITOR_LOGIC_OUTS_B21_9", - "MONITOR_LOGIC_OUTS_B22_0", - "MONITOR_LOGIC_OUTS_B22_1", - "MONITOR_LOGIC_OUTS_B22_2", - "MONITOR_LOGIC_OUTS_B22_3", - "MONITOR_LOGIC_OUTS_B22_4", - "MONITOR_LOGIC_OUTS_B22_5", - "MONITOR_LOGIC_OUTS_B22_6", - "MONITOR_LOGIC_OUTS_B22_7", - "MONITOR_LOGIC_OUTS_B22_8", - "MONITOR_LOGIC_OUTS_B22_9", - "MONITOR_LOGIC_OUTS_B23_0", - "MONITOR_LOGIC_OUTS_B23_1", - "MONITOR_LOGIC_OUTS_B23_2", - "MONITOR_LOGIC_OUTS_B23_3", - "MONITOR_LOGIC_OUTS_B23_4", - "MONITOR_LOGIC_OUTS_B23_5", - "MONITOR_LOGIC_OUTS_B23_6", - "MONITOR_LOGIC_OUTS_B23_7", - "MONITOR_LOGIC_OUTS_B23_8", - "MONITOR_LOGIC_OUTS_B23_9", - "MONITOR_LOGIC_OUTS_B2_0", - "MONITOR_LOGIC_OUTS_B2_1", - "MONITOR_LOGIC_OUTS_B2_2", - "MONITOR_LOGIC_OUTS_B2_3", - "MONITOR_LOGIC_OUTS_B2_4", - "MONITOR_LOGIC_OUTS_B2_5", - "MONITOR_LOGIC_OUTS_B2_6", - "MONITOR_LOGIC_OUTS_B2_7", - "MONITOR_LOGIC_OUTS_B2_8", - "MONITOR_LOGIC_OUTS_B2_9", - "MONITOR_LOGIC_OUTS_B3_0", - "MONITOR_LOGIC_OUTS_B3_1", - "MONITOR_LOGIC_OUTS_B3_2", - "MONITOR_LOGIC_OUTS_B3_3", - "MONITOR_LOGIC_OUTS_B3_4", - "MONITOR_LOGIC_OUTS_B3_5", - "MONITOR_LOGIC_OUTS_B3_6", - "MONITOR_LOGIC_OUTS_B3_7", - "MONITOR_LOGIC_OUTS_B3_8", - "MONITOR_LOGIC_OUTS_B3_9", - "MONITOR_LOGIC_OUTS_B4_0", - "MONITOR_LOGIC_OUTS_B4_1", - "MONITOR_LOGIC_OUTS_B4_2", - "MONITOR_LOGIC_OUTS_B4_3", - "MONITOR_LOGIC_OUTS_B4_4", - "MONITOR_LOGIC_OUTS_B4_5", - "MONITOR_LOGIC_OUTS_B4_6", - "MONITOR_LOGIC_OUTS_B4_7", - "MONITOR_LOGIC_OUTS_B4_8", - "MONITOR_LOGIC_OUTS_B4_9", - "MONITOR_LOGIC_OUTS_B5_0", - "MONITOR_LOGIC_OUTS_B5_1", - "MONITOR_LOGIC_OUTS_B5_2", - "MONITOR_LOGIC_OUTS_B5_3", - "MONITOR_LOGIC_OUTS_B5_4", - "MONITOR_LOGIC_OUTS_B5_5", - "MONITOR_LOGIC_OUTS_B5_6", - "MONITOR_LOGIC_OUTS_B5_7", - "MONITOR_LOGIC_OUTS_B5_8", - "MONITOR_LOGIC_OUTS_B5_9", - "MONITOR_LOGIC_OUTS_B6_0", - "MONITOR_LOGIC_OUTS_B6_1", - "MONITOR_LOGIC_OUTS_B6_2", - "MONITOR_LOGIC_OUTS_B6_3", - "MONITOR_LOGIC_OUTS_B6_4", - "MONITOR_LOGIC_OUTS_B6_5", - "MONITOR_LOGIC_OUTS_B6_6", - "MONITOR_LOGIC_OUTS_B6_7", - "MONITOR_LOGIC_OUTS_B6_8", - "MONITOR_LOGIC_OUTS_B6_9", - "MONITOR_LOGIC_OUTS_B7_0", - "MONITOR_LOGIC_OUTS_B7_1", - "MONITOR_LOGIC_OUTS_B7_2", - "MONITOR_LOGIC_OUTS_B7_3", - "MONITOR_LOGIC_OUTS_B7_4", - "MONITOR_LOGIC_OUTS_B7_5", - "MONITOR_LOGIC_OUTS_B7_6", - "MONITOR_LOGIC_OUTS_B7_7", - "MONITOR_LOGIC_OUTS_B7_8", - "MONITOR_LOGIC_OUTS_B7_9", - "MONITOR_LOGIC_OUTS_B8_0", - "MONITOR_LOGIC_OUTS_B8_1", - "MONITOR_LOGIC_OUTS_B8_2", - "MONITOR_LOGIC_OUTS_B8_3", - "MONITOR_LOGIC_OUTS_B8_4", - "MONITOR_LOGIC_OUTS_B8_5", - "MONITOR_LOGIC_OUTS_B8_6", - "MONITOR_LOGIC_OUTS_B8_7", - "MONITOR_LOGIC_OUTS_B8_8", - "MONITOR_LOGIC_OUTS_B8_9", - "MONITOR_LOGIC_OUTS_B9_0", - "MONITOR_LOGIC_OUTS_B9_1", - "MONITOR_LOGIC_OUTS_B9_2", - "MONITOR_LOGIC_OUTS_B9_3", - "MONITOR_LOGIC_OUTS_B9_4", - "MONITOR_LOGIC_OUTS_B9_5", - "MONITOR_LOGIC_OUTS_B9_6", - "MONITOR_LOGIC_OUTS_B9_7", - "MONITOR_LOGIC_OUTS_B9_8", - "MONITOR_LOGIC_OUTS_B9_9", - "MONITOR_MUXADDR0", - "MONITOR_MUXADDR1", - "MONITOR_MUXADDR2", - "MONITOR_MUXADDR3", - "MONITOR_MUXADDR4", - "MONITOR_NE2A0_0", - "MONITOR_NE2A0_1", - "MONITOR_NE2A0_2", - "MONITOR_NE2A0_3", - "MONITOR_NE2A0_4", - "MONITOR_NE2A0_5", - "MONITOR_NE2A0_6", - "MONITOR_NE2A0_7", - "MONITOR_NE2A0_8", - "MONITOR_NE2A0_9", - "MONITOR_NE2A1_0", - "MONITOR_NE2A1_1", - "MONITOR_NE2A1_2", - "MONITOR_NE2A1_3", - "MONITOR_NE2A1_4", - "MONITOR_NE2A1_5", - "MONITOR_NE2A1_6", - "MONITOR_NE2A1_7", - "MONITOR_NE2A1_8", - "MONITOR_NE2A1_9", - "MONITOR_NE2A2_0", - "MONITOR_NE2A2_1", - "MONITOR_NE2A2_2", - "MONITOR_NE2A2_3", - "MONITOR_NE2A2_4", - "MONITOR_NE2A2_5", - "MONITOR_NE2A2_6", - "MONITOR_NE2A2_7", - "MONITOR_NE2A2_8", - "MONITOR_NE2A2_9", - "MONITOR_NE2A3_0", - "MONITOR_NE2A3_1", - "MONITOR_NE2A3_2", - "MONITOR_NE2A3_3", - "MONITOR_NE2A3_4", - "MONITOR_NE2A3_5", - "MONITOR_NE2A3_6", - "MONITOR_NE2A3_7", - "MONITOR_NE2A3_8", - "MONITOR_NE2A3_9", - "MONITOR_NE4BEG0_0", - "MONITOR_NE4BEG0_1", - "MONITOR_NE4BEG0_2", - "MONITOR_NE4BEG0_3", - "MONITOR_NE4BEG0_4", - "MONITOR_NE4BEG0_5", - "MONITOR_NE4BEG0_6", - "MONITOR_NE4BEG0_7", - "MONITOR_NE4BEG0_8", - "MONITOR_NE4BEG0_9", - "MONITOR_NE4BEG1_0", - "MONITOR_NE4BEG1_1", - "MONITOR_NE4BEG1_2", - "MONITOR_NE4BEG1_3", - "MONITOR_NE4BEG1_4", - "MONITOR_NE4BEG1_5", - "MONITOR_NE4BEG1_6", - "MONITOR_NE4BEG1_7", - "MONITOR_NE4BEG1_8", - "MONITOR_NE4BEG1_9", - "MONITOR_NE4BEG2_0", - "MONITOR_NE4BEG2_1", - "MONITOR_NE4BEG2_2", - "MONITOR_NE4BEG2_3", - "MONITOR_NE4BEG2_4", - "MONITOR_NE4BEG2_5", - "MONITOR_NE4BEG2_6", - "MONITOR_NE4BEG2_7", - "MONITOR_NE4BEG2_8", - "MONITOR_NE4BEG2_9", - "MONITOR_NE4BEG3_0", - "MONITOR_NE4BEG3_1", - "MONITOR_NE4BEG3_2", - "MONITOR_NE4BEG3_3", - "MONITOR_NE4BEG3_4", - "MONITOR_NE4BEG3_5", - "MONITOR_NE4BEG3_6", - "MONITOR_NE4BEG3_7", - "MONITOR_NE4BEG3_8", - "MONITOR_NE4BEG3_9", - "MONITOR_NE4C0_0", - "MONITOR_NE4C0_1", - "MONITOR_NE4C0_2", - "MONITOR_NE4C0_3", - "MONITOR_NE4C0_4", - "MONITOR_NE4C0_5", - "MONITOR_NE4C0_6", - "MONITOR_NE4C0_7", - "MONITOR_NE4C0_8", - "MONITOR_NE4C0_9", - "MONITOR_NE4C1_0", - "MONITOR_NE4C1_1", - "MONITOR_NE4C1_2", - "MONITOR_NE4C1_3", - "MONITOR_NE4C1_4", - "MONITOR_NE4C1_5", - "MONITOR_NE4C1_6", - "MONITOR_NE4C1_7", - "MONITOR_NE4C1_8", - "MONITOR_NE4C1_9", - "MONITOR_NE4C2_0", - "MONITOR_NE4C2_1", - "MONITOR_NE4C2_2", - "MONITOR_NE4C2_3", - "MONITOR_NE4C2_4", - "MONITOR_NE4C2_5", - "MONITOR_NE4C2_6", - "MONITOR_NE4C2_7", - "MONITOR_NE4C2_8", - "MONITOR_NE4C2_9", - "MONITOR_NE4C3_0", - "MONITOR_NE4C3_1", - "MONITOR_NE4C3_2", - "MONITOR_NE4C3_3", - "MONITOR_NE4C3_4", - "MONITOR_NE4C3_5", - "MONITOR_NE4C3_6", - "MONITOR_NE4C3_7", - "MONITOR_NE4C3_8", - "MONITOR_NE4C3_9", - "MONITOR_NW2A0_0", - "MONITOR_NW2A0_1", - "MONITOR_NW2A0_2", - "MONITOR_NW2A0_3", - "MONITOR_NW2A0_4", - "MONITOR_NW2A0_5", - "MONITOR_NW2A0_6", - "MONITOR_NW2A0_7", - "MONITOR_NW2A0_8", - "MONITOR_NW2A0_9", - "MONITOR_NW2A1_0", - "MONITOR_NW2A1_1", - "MONITOR_NW2A1_2", - "MONITOR_NW2A1_3", - "MONITOR_NW2A1_4", - "MONITOR_NW2A1_5", - "MONITOR_NW2A1_6", - "MONITOR_NW2A1_7", - "MONITOR_NW2A1_8", - "MONITOR_NW2A1_9", - "MONITOR_NW2A2_0", - "MONITOR_NW2A2_1", - "MONITOR_NW2A2_2", - "MONITOR_NW2A2_3", - "MONITOR_NW2A2_4", - "MONITOR_NW2A2_5", - "MONITOR_NW2A2_6", - "MONITOR_NW2A2_7", - "MONITOR_NW2A2_8", - "MONITOR_NW2A2_9", - "MONITOR_NW2A3_0", - "MONITOR_NW2A3_1", - "MONITOR_NW2A3_2", - "MONITOR_NW2A3_3", - "MONITOR_NW2A3_4", - "MONITOR_NW2A3_5", - "MONITOR_NW2A3_6", - "MONITOR_NW2A3_7", - "MONITOR_NW2A3_8", - "MONITOR_NW2A3_9", - "MONITOR_NW4A0_0", - "MONITOR_NW4A0_1", - "MONITOR_NW4A0_2", - "MONITOR_NW4A0_3", - "MONITOR_NW4A0_4", - "MONITOR_NW4A0_5", - "MONITOR_NW4A0_6", - "MONITOR_NW4A0_7", - "MONITOR_NW4A0_8", - "MONITOR_NW4A0_9", - "MONITOR_NW4A1_0", - "MONITOR_NW4A1_1", - "MONITOR_NW4A1_2", - "MONITOR_NW4A1_3", - "MONITOR_NW4A1_4", - "MONITOR_NW4A1_5", - "MONITOR_NW4A1_6", - "MONITOR_NW4A1_7", - "MONITOR_NW4A1_8", - "MONITOR_NW4A1_9", - "MONITOR_NW4A2_0", - "MONITOR_NW4A2_1", - "MONITOR_NW4A2_2", - "MONITOR_NW4A2_3", - "MONITOR_NW4A2_4", - "MONITOR_NW4A2_5", - "MONITOR_NW4A2_6", - "MONITOR_NW4A2_7", - "MONITOR_NW4A2_8", - "MONITOR_NW4A2_9", - "MONITOR_NW4A3_0", - "MONITOR_NW4A3_1", - "MONITOR_NW4A3_2", - "MONITOR_NW4A3_3", - "MONITOR_NW4A3_4", - "MONITOR_NW4A3_5", - "MONITOR_NW4A3_6", - "MONITOR_NW4A3_7", - "MONITOR_NW4A3_8", - "MONITOR_NW4A3_9", - "MONITOR_NW4END0_0", - "MONITOR_NW4END0_1", - "MONITOR_NW4END0_2", - "MONITOR_NW4END0_3", - "MONITOR_NW4END0_4", - "MONITOR_NW4END0_5", - "MONITOR_NW4END0_6", - "MONITOR_NW4END0_7", - "MONITOR_NW4END0_8", - "MONITOR_NW4END0_9", - "MONITOR_NW4END1_0", - "MONITOR_NW4END1_1", - "MONITOR_NW4END1_2", - "MONITOR_NW4END1_3", - "MONITOR_NW4END1_4", - "MONITOR_NW4END1_5", - "MONITOR_NW4END1_6", - "MONITOR_NW4END1_7", - "MONITOR_NW4END1_8", - "MONITOR_NW4END1_9", - "MONITOR_NW4END2_0", - "MONITOR_NW4END2_1", - "MONITOR_NW4END2_2", - "MONITOR_NW4END2_3", - "MONITOR_NW4END2_4", - "MONITOR_NW4END2_5", - "MONITOR_NW4END2_6", - "MONITOR_NW4END2_7", - "MONITOR_NW4END2_8", - "MONITOR_NW4END2_9", - "MONITOR_NW4END3_0", - "MONITOR_NW4END3_1", - "MONITOR_NW4END3_2", - "MONITOR_NW4END3_3", - "MONITOR_NW4END3_4", - "MONITOR_NW4END3_5", - "MONITOR_NW4END3_6", - "MONITOR_NW4END3_7", - "MONITOR_NW4END3_8", - "MONITOR_NW4END3_9", - "MONITOR_OT", - "MONITOR_RESET", - "MONITOR_SE2A0_0", - "MONITOR_SE2A0_1", - "MONITOR_SE2A0_2", - "MONITOR_SE2A0_3", - "MONITOR_SE2A0_4", - "MONITOR_SE2A0_5", - "MONITOR_SE2A0_6", - "MONITOR_SE2A0_7", - "MONITOR_SE2A0_8", - "MONITOR_SE2A0_9", - "MONITOR_SE2A1_0", - "MONITOR_SE2A1_1", - "MONITOR_SE2A1_2", - "MONITOR_SE2A1_3", - "MONITOR_SE2A1_4", - "MONITOR_SE2A1_5", - "MONITOR_SE2A1_6", - "MONITOR_SE2A1_7", - "MONITOR_SE2A1_8", - "MONITOR_SE2A1_9", - "MONITOR_SE2A2_0", - "MONITOR_SE2A2_1", - "MONITOR_SE2A2_2", - "MONITOR_SE2A2_3", - "MONITOR_SE2A2_4", - "MONITOR_SE2A2_5", - "MONITOR_SE2A2_6", - "MONITOR_SE2A2_7", - "MONITOR_SE2A2_8", - "MONITOR_SE2A2_9", - "MONITOR_SE2A3_0", - "MONITOR_SE2A3_1", - "MONITOR_SE2A3_2", - "MONITOR_SE2A3_3", - "MONITOR_SE2A3_4", - "MONITOR_SE2A3_5", - "MONITOR_SE2A3_6", - "MONITOR_SE2A3_7", - "MONITOR_SE2A3_8", - "MONITOR_SE2A3_9", - "MONITOR_SE4BEG0_0", - "MONITOR_SE4BEG0_1", - "MONITOR_SE4BEG0_2", - "MONITOR_SE4BEG0_3", - "MONITOR_SE4BEG0_4", - "MONITOR_SE4BEG0_5", - "MONITOR_SE4BEG0_6", - "MONITOR_SE4BEG0_7", - "MONITOR_SE4BEG0_8", - "MONITOR_SE4BEG0_9", - "MONITOR_SE4BEG1_0", - "MONITOR_SE4BEG1_1", - "MONITOR_SE4BEG1_2", - "MONITOR_SE4BEG1_3", - "MONITOR_SE4BEG1_4", - "MONITOR_SE4BEG1_5", - "MONITOR_SE4BEG1_6", - "MONITOR_SE4BEG1_7", - "MONITOR_SE4BEG1_8", - "MONITOR_SE4BEG1_9", - "MONITOR_SE4BEG2_0", - "MONITOR_SE4BEG2_1", - "MONITOR_SE4BEG2_2", - "MONITOR_SE4BEG2_3", - "MONITOR_SE4BEG2_4", - "MONITOR_SE4BEG2_5", - "MONITOR_SE4BEG2_6", - "MONITOR_SE4BEG2_7", - "MONITOR_SE4BEG2_8", - "MONITOR_SE4BEG2_9", - "MONITOR_SE4BEG3_0", - "MONITOR_SE4BEG3_1", - "MONITOR_SE4BEG3_2", - "MONITOR_SE4BEG3_3", - "MONITOR_SE4BEG3_4", - "MONITOR_SE4BEG3_5", - "MONITOR_SE4BEG3_6", - "MONITOR_SE4BEG3_7", - "MONITOR_SE4BEG3_8", - "MONITOR_SE4BEG3_9", - "MONITOR_SE4C0_0", - "MONITOR_SE4C0_1", - "MONITOR_SE4C0_2", - "MONITOR_SE4C0_3", - "MONITOR_SE4C0_4", - "MONITOR_SE4C0_5", - "MONITOR_SE4C0_6", - "MONITOR_SE4C0_7", - "MONITOR_SE4C0_8", - "MONITOR_SE4C0_9", - "MONITOR_SE4C1_0", - "MONITOR_SE4C1_1", - "MONITOR_SE4C1_2", - "MONITOR_SE4C1_3", - "MONITOR_SE4C1_4", - "MONITOR_SE4C1_5", - "MONITOR_SE4C1_6", - "MONITOR_SE4C1_7", - "MONITOR_SE4C1_8", - "MONITOR_SE4C1_9", - "MONITOR_SE4C2_0", - "MONITOR_SE4C2_1", - "MONITOR_SE4C2_2", - "MONITOR_SE4C2_3", - "MONITOR_SE4C2_4", - "MONITOR_SE4C2_5", - "MONITOR_SE4C2_6", - "MONITOR_SE4C2_7", - "MONITOR_SE4C2_8", - "MONITOR_SE4C2_9", - "MONITOR_SE4C3_0", - "MONITOR_SE4C3_1", - "MONITOR_SE4C3_2", - "MONITOR_SE4C3_3", - "MONITOR_SE4C3_4", - "MONITOR_SE4C3_5", - "MONITOR_SE4C3_6", - "MONITOR_SE4C3_7", - "MONITOR_SE4C3_8", - "MONITOR_SE4C3_9", - "MONITOR_SEG_VN", - "MONITOR_SEG_VP", - "MONITOR_SW2A0_0", - "MONITOR_SW2A0_1", - "MONITOR_SW2A0_2", - "MONITOR_SW2A0_3", - "MONITOR_SW2A0_4", - "MONITOR_SW2A0_5", - "MONITOR_SW2A0_6", - "MONITOR_SW2A0_7", - "MONITOR_SW2A0_8", - "MONITOR_SW2A0_9", - "MONITOR_SW2A1_0", - "MONITOR_SW2A1_1", - "MONITOR_SW2A1_2", - "MONITOR_SW2A1_3", - "MONITOR_SW2A1_4", - "MONITOR_SW2A1_5", - "MONITOR_SW2A1_6", - "MONITOR_SW2A1_7", - "MONITOR_SW2A1_8", - "MONITOR_SW2A1_9", - "MONITOR_SW2A2_0", - "MONITOR_SW2A2_1", - "MONITOR_SW2A2_2", - "MONITOR_SW2A2_3", - "MONITOR_SW2A2_4", - "MONITOR_SW2A2_5", - "MONITOR_SW2A2_6", - "MONITOR_SW2A2_7", - "MONITOR_SW2A2_8", - "MONITOR_SW2A2_9", - "MONITOR_SW2A3_0", - "MONITOR_SW2A3_1", - "MONITOR_SW2A3_2", - "MONITOR_SW2A3_3", - "MONITOR_SW2A3_4", - "MONITOR_SW2A3_5", - "MONITOR_SW2A3_6", - "MONITOR_SW2A3_7", - "MONITOR_SW2A3_8", - "MONITOR_SW2A3_9", - "MONITOR_SW4A0_0", - "MONITOR_SW4A0_1", - "MONITOR_SW4A0_2", - "MONITOR_SW4A0_3", - "MONITOR_SW4A0_4", - "MONITOR_SW4A0_5", - "MONITOR_SW4A0_6", - "MONITOR_SW4A0_7", - "MONITOR_SW4A0_8", - "MONITOR_SW4A0_9", - "MONITOR_SW4A1_0", - "MONITOR_SW4A1_1", - "MONITOR_SW4A1_2", - "MONITOR_SW4A1_3", - "MONITOR_SW4A1_4", - "MONITOR_SW4A1_5", - "MONITOR_SW4A1_6", - "MONITOR_SW4A1_7", - "MONITOR_SW4A1_8", - "MONITOR_SW4A1_9", - "MONITOR_SW4A2_0", - "MONITOR_SW4A2_1", - "MONITOR_SW4A2_2", - "MONITOR_SW4A2_3", - "MONITOR_SW4A2_4", - "MONITOR_SW4A2_5", - "MONITOR_SW4A2_6", - "MONITOR_SW4A2_7", - "MONITOR_SW4A2_8", - "MONITOR_SW4A2_9", - "MONITOR_SW4A3_0", - "MONITOR_SW4A3_1", - "MONITOR_SW4A3_2", - "MONITOR_SW4A3_3", - "MONITOR_SW4A3_4", - "MONITOR_SW4A3_5", - "MONITOR_SW4A3_6", - "MONITOR_SW4A3_7", - "MONITOR_SW4A3_8", - "MONITOR_SW4A3_9", - "MONITOR_SW4END0_0", - "MONITOR_SW4END0_1", - "MONITOR_SW4END0_2", - "MONITOR_SW4END0_3", - "MONITOR_SW4END0_4", - "MONITOR_SW4END0_5", - "MONITOR_SW4END0_6", - "MONITOR_SW4END0_7", - "MONITOR_SW4END0_8", - "MONITOR_SW4END0_9", - "MONITOR_SW4END1_0", - "MONITOR_SW4END1_1", - "MONITOR_SW4END1_2", - "MONITOR_SW4END1_3", - "MONITOR_SW4END1_4", - "MONITOR_SW4END1_5", - "MONITOR_SW4END1_6", - "MONITOR_SW4END1_7", - "MONITOR_SW4END1_8", - "MONITOR_SW4END1_9", - "MONITOR_SW4END2_0", - "MONITOR_SW4END2_1", - "MONITOR_SW4END2_2", - "MONITOR_SW4END2_3", - "MONITOR_SW4END2_4", - "MONITOR_SW4END2_5", - "MONITOR_SW4END2_6", - "MONITOR_SW4END2_7", - "MONITOR_SW4END2_8", - "MONITOR_SW4END2_9", - "MONITOR_SW4END3_0", - "MONITOR_SW4END3_1", - "MONITOR_SW4END3_2", - "MONITOR_SW4END3_3", - "MONITOR_SW4END3_4", - "MONITOR_SW4END3_5", - "MONITOR_SW4END3_6", - "MONITOR_SW4END3_7", - "MONITOR_SW4END3_8", - "MONITOR_SW4END3_9", - "MONITOR_TESTADCCLK0", - "MONITOR_TESTADCCLK1", - "MONITOR_TESTADCCLK2", - "MONITOR_TESTADCCLK3", - "MONITOR_TESTADCIN0", - "MONITOR_TESTADCIN1", - "MONITOR_TESTADCIN10", - "MONITOR_TESTADCIN11", - "MONITOR_TESTADCIN12", - "MONITOR_TESTADCIN13", - "MONITOR_TESTADCIN14", - "MONITOR_TESTADCIN15", - "MONITOR_TESTADCIN16", - "MONITOR_TESTADCIN17", - "MONITOR_TESTADCIN18", - "MONITOR_TESTADCIN19", - "MONITOR_TESTADCIN2", - "MONITOR_TESTADCIN20", - "MONITOR_TESTADCIN21", - "MONITOR_TESTADCIN210", - "MONITOR_TESTADCIN211", - "MONITOR_TESTADCIN212", - "MONITOR_TESTADCIN213", - "MONITOR_TESTADCIN214", - "MONITOR_TESTADCIN215", - "MONITOR_TESTADCIN216", - "MONITOR_TESTADCIN217", - "MONITOR_TESTADCIN218", - "MONITOR_TESTADCIN219", - "MONITOR_TESTADCIN22", - "MONITOR_TESTADCIN23", - "MONITOR_TESTADCIN24", - "MONITOR_TESTADCIN25", - "MONITOR_TESTADCIN26", - "MONITOR_TESTADCIN27", - "MONITOR_TESTADCIN28", - "MONITOR_TESTADCIN29", - "MONITOR_TESTADCIN3", - "MONITOR_TESTADCIN4", - "MONITOR_TESTADCIN5", - "MONITOR_TESTADCIN6", - "MONITOR_TESTADCIN7", - "MONITOR_TESTADCIN8", - "MONITOR_TESTADCIN9", - "MONITOR_TESTADCOUT0", - "MONITOR_TESTADCOUT1", - "MONITOR_TESTADCOUT10", - "MONITOR_TESTADCOUT11", - "MONITOR_TESTADCOUT12", - "MONITOR_TESTADCOUT13", - "MONITOR_TESTADCOUT14", - "MONITOR_TESTADCOUT15", - "MONITOR_TESTADCOUT16", - "MONITOR_TESTADCOUT17", - "MONITOR_TESTADCOUT18", - "MONITOR_TESTADCOUT19", - "MONITOR_TESTADCOUT2", - "MONITOR_TESTADCOUT3", - "MONITOR_TESTADCOUT4", - "MONITOR_TESTADCOUT5", - "MONITOR_TESTADCOUT6", - "MONITOR_TESTADCOUT7", - "MONITOR_TESTADCOUT8", - "MONITOR_TESTADCOUT9", - "MONITOR_TESTCAPTURE", - "MONITOR_TESTDB0", - "MONITOR_TESTDB1", - "MONITOR_TESTDB10", - "MONITOR_TESTDB11", - "MONITOR_TESTDB12", - "MONITOR_TESTDB13", - "MONITOR_TESTDB14", - "MONITOR_TESTDB15", - "MONITOR_TESTDB2", - "MONITOR_TESTDB3", - "MONITOR_TESTDB4", - "MONITOR_TESTDB5", - "MONITOR_TESTDB6", - "MONITOR_TESTDB7", - "MONITOR_TESTDB8", - "MONITOR_TESTDB9", - "MONITOR_TESTDRCK", - "MONITOR_TESTENJTAG", - "MONITOR_TESTRST", - "MONITOR_TESTSCANCLK0", - "MONITOR_TESTSCANCLK1", - "MONITOR_TESTSCANCLK2", - "MONITOR_TESTSCANCLK3", - "MONITOR_TESTSCANCLK4", - "MONITOR_TESTSCANMODE0", - "MONITOR_TESTSCANMODE1", - "MONITOR_TESTSCANMODE2", - "MONITOR_TESTSCANMODE3", - "MONITOR_TESTSCANMODE4", - "MONITOR_TESTSCANRESET", - "MONITOR_TESTSE0", - "MONITOR_TESTSE1", - "MONITOR_TESTSE2", - "MONITOR_TESTSE3", - "MONITOR_TESTSE4", - "MONITOR_TESTSEL", - "MONITOR_TESTSHIFT", - "MONITOR_TESTSI0", - "MONITOR_TESTSI1", - "MONITOR_TESTSI2", - "MONITOR_TESTSI3", - "MONITOR_TESTSI4", - "MONITOR_TESTSO0", - "MONITOR_TESTSO1", - "MONITOR_TESTSO2", - "MONITOR_TESTSO3", - "MONITOR_TESTSO4", - "MONITOR_TESTTDI", - "MONITOR_TESTTDO", - "MONITOR_TESTUPDATE", - "MONITOR_VAUXN0", - "MONITOR_VAUXN1", - "MONITOR_VAUXN10", - "MONITOR_VAUXN11", - "MONITOR_VAUXN12", - "MONITOR_VAUXN13", - "MONITOR_VAUXN14", - "MONITOR_VAUXN15", - "MONITOR_VAUXN2", - "MONITOR_VAUXN3", - "MONITOR_VAUXN4", - "MONITOR_VAUXN5", - "MONITOR_VAUXN6", - "MONITOR_VAUXN7", - "MONITOR_VAUXN8", - "MONITOR_VAUXN9", - "MONITOR_VAUXP0", - "MONITOR_VAUXP1", - "MONITOR_VAUXP10", - "MONITOR_VAUXP11", - "MONITOR_VAUXP12", - "MONITOR_VAUXP13", - "MONITOR_VAUXP14", - "MONITOR_VAUXP15", - "MONITOR_VAUXP2", - "MONITOR_VAUXP3", - "MONITOR_VAUXP4", - "MONITOR_VAUXP5", - "MONITOR_VAUXP6", - "MONITOR_VAUXP7", - "MONITOR_VAUXP8", - "MONITOR_VAUXP9", - "MONITOR_VERT_VAUXN0", - "MONITOR_VERT_VAUXN1", - "MONITOR_VERT_VAUXN10", - "MONITOR_VERT_VAUXN11", - "MONITOR_VERT_VAUXN12", - "MONITOR_VERT_VAUXN13", - "MONITOR_VERT_VAUXN14", - "MONITOR_VERT_VAUXN15", - "MONITOR_VERT_VAUXN2", - "MONITOR_VERT_VAUXN3", - "MONITOR_VERT_VAUXN4", - "MONITOR_VERT_VAUXN5", - "MONITOR_VERT_VAUXN6", - "MONITOR_VERT_VAUXN7", - "MONITOR_VERT_VAUXN8", - "MONITOR_VERT_VAUXN9", - "MONITOR_VERT_VAUXP0", - "MONITOR_VERT_VAUXP1", - "MONITOR_VERT_VAUXP10", - "MONITOR_VERT_VAUXP11", - "MONITOR_VERT_VAUXP12", - "MONITOR_VERT_VAUXP13", - "MONITOR_VERT_VAUXP14", - "MONITOR_VERT_VAUXP15", - "MONITOR_VERT_VAUXP2", - "MONITOR_VERT_VAUXP3", - "MONITOR_VERT_VAUXP4", - "MONITOR_VERT_VAUXP5", - "MONITOR_VERT_VAUXP6", - "MONITOR_VERT_VAUXP7", - "MONITOR_VERT_VAUXP8", - "MONITOR_VERT_VAUXP9", - "MONITOR_VN", - "MONITOR_VP", - "MONITOR_WL1END0_0", - "MONITOR_WL1END0_1", - "MONITOR_WL1END0_2", - "MONITOR_WL1END0_3", - "MONITOR_WL1END0_4", - "MONITOR_WL1END0_5", - "MONITOR_WL1END0_6", - "MONITOR_WL1END0_7", - "MONITOR_WL1END0_8", - "MONITOR_WL1END0_9", - "MONITOR_WL1END1_0", - "MONITOR_WL1END1_1", - "MONITOR_WL1END1_2", - "MONITOR_WL1END1_3", - "MONITOR_WL1END1_4", - "MONITOR_WL1END1_5", - "MONITOR_WL1END1_6", - "MONITOR_WL1END1_7", - "MONITOR_WL1END1_8", - "MONITOR_WL1END1_9", - "MONITOR_WL1END2_0", - "MONITOR_WL1END2_1", - "MONITOR_WL1END2_2", - "MONITOR_WL1END2_3", - "MONITOR_WL1END2_4", - "MONITOR_WL1END2_5", - "MONITOR_WL1END2_6", - "MONITOR_WL1END2_7", - "MONITOR_WL1END2_8", - "MONITOR_WL1END2_9", - "MONITOR_WL1END3_0", - "MONITOR_WL1END3_1", - "MONITOR_WL1END3_2", - "MONITOR_WL1END3_3", - "MONITOR_WL1END3_4", - "MONITOR_WL1END3_5", - "MONITOR_WL1END3_6", - "MONITOR_WL1END3_7", - "MONITOR_WL1END3_8", - "MONITOR_WL1END3_9", - "MONITOR_WR1END0_0", - "MONITOR_WR1END0_1", - "MONITOR_WR1END0_2", - "MONITOR_WR1END0_3", - "MONITOR_WR1END0_4", - "MONITOR_WR1END0_5", - "MONITOR_WR1END0_6", - "MONITOR_WR1END0_7", - "MONITOR_WR1END0_8", - "MONITOR_WR1END0_9", - "MONITOR_WR1END1_0", - "MONITOR_WR1END1_1", - "MONITOR_WR1END1_2", - "MONITOR_WR1END1_3", - "MONITOR_WR1END1_4", - "MONITOR_WR1END1_5", - "MONITOR_WR1END1_6", - "MONITOR_WR1END1_7", - "MONITOR_WR1END1_8", - "MONITOR_WR1END1_9", - "MONITOR_WR1END2_0", - "MONITOR_WR1END2_1", - "MONITOR_WR1END2_2", - "MONITOR_WR1END2_3", - "MONITOR_WR1END2_4", - "MONITOR_WR1END2_5", - "MONITOR_WR1END2_6", - "MONITOR_WR1END2_7", - "MONITOR_WR1END2_8", - "MONITOR_WR1END2_9", - "MONITOR_WR1END3_0", - "MONITOR_WR1END3_1", - "MONITOR_WR1END3_2", - "MONITOR_WR1END3_3", - "MONITOR_WR1END3_4", - "MONITOR_WR1END3_5", - "MONITOR_WR1END3_6", - "MONITOR_WR1END3_7", - "MONITOR_WR1END3_8", - "MONITOR_WR1END3_9", - "MONITOR_WW2A0_0", - "MONITOR_WW2A0_1", - "MONITOR_WW2A0_2", - "MONITOR_WW2A0_3", - "MONITOR_WW2A0_4", - "MONITOR_WW2A0_5", - "MONITOR_WW2A0_6", - "MONITOR_WW2A0_7", - "MONITOR_WW2A0_8", - "MONITOR_WW2A0_9", - "MONITOR_WW2A1_0", - "MONITOR_WW2A1_1", - "MONITOR_WW2A1_2", - "MONITOR_WW2A1_3", - "MONITOR_WW2A1_4", - "MONITOR_WW2A1_5", - "MONITOR_WW2A1_6", - "MONITOR_WW2A1_7", - "MONITOR_WW2A1_8", - "MONITOR_WW2A1_9", - "MONITOR_WW2A2_0", - "MONITOR_WW2A2_1", - "MONITOR_WW2A2_2", - "MONITOR_WW2A2_3", - "MONITOR_WW2A2_4", - "MONITOR_WW2A2_5", - "MONITOR_WW2A2_6", - "MONITOR_WW2A2_7", - "MONITOR_WW2A2_8", - "MONITOR_WW2A2_9", - "MONITOR_WW2A3_0", - "MONITOR_WW2A3_1", - "MONITOR_WW2A3_2", - "MONITOR_WW2A3_3", - "MONITOR_WW2A3_4", - "MONITOR_WW2A3_5", - "MONITOR_WW2A3_6", - "MONITOR_WW2A3_7", - "MONITOR_WW2A3_8", - "MONITOR_WW2A3_9", - "MONITOR_WW2END0_0", - "MONITOR_WW2END0_1", - "MONITOR_WW2END0_2", - "MONITOR_WW2END0_3", - "MONITOR_WW2END0_4", - "MONITOR_WW2END0_5", - "MONITOR_WW2END0_6", - "MONITOR_WW2END0_7", - "MONITOR_WW2END0_8", - "MONITOR_WW2END0_9", - "MONITOR_WW2END1_0", - "MONITOR_WW2END1_1", - "MONITOR_WW2END1_2", - "MONITOR_WW2END1_3", - "MONITOR_WW2END1_4", - "MONITOR_WW2END1_5", - "MONITOR_WW2END1_6", - "MONITOR_WW2END1_7", - "MONITOR_WW2END1_8", - "MONITOR_WW2END1_9", - "MONITOR_WW2END2_0", - "MONITOR_WW2END2_1", - "MONITOR_WW2END2_2", - "MONITOR_WW2END2_3", - "MONITOR_WW2END2_4", - "MONITOR_WW2END2_5", - "MONITOR_WW2END2_6", - "MONITOR_WW2END2_7", - "MONITOR_WW2END2_8", - "MONITOR_WW2END2_9", - "MONITOR_WW2END3_0", - "MONITOR_WW2END3_1", - "MONITOR_WW2END3_2", - "MONITOR_WW2END3_3", - "MONITOR_WW2END3_4", - "MONITOR_WW2END3_5", - "MONITOR_WW2END3_6", - "MONITOR_WW2END3_7", - "MONITOR_WW2END3_8", - "MONITOR_WW2END3_9", - "MONITOR_WW4A0_0", - "MONITOR_WW4A0_1", - "MONITOR_WW4A0_2", - "MONITOR_WW4A0_3", - "MONITOR_WW4A0_4", - "MONITOR_WW4A0_5", - "MONITOR_WW4A0_6", - "MONITOR_WW4A0_7", - "MONITOR_WW4A0_8", - "MONITOR_WW4A0_9", - "MONITOR_WW4A1_0", - "MONITOR_WW4A1_1", - "MONITOR_WW4A1_2", - "MONITOR_WW4A1_3", - "MONITOR_WW4A1_4", - "MONITOR_WW4A1_5", - "MONITOR_WW4A1_6", - "MONITOR_WW4A1_7", - "MONITOR_WW4A1_8", - "MONITOR_WW4A1_9", - "MONITOR_WW4A2_0", - "MONITOR_WW4A2_1", - "MONITOR_WW4A2_2", - "MONITOR_WW4A2_3", - "MONITOR_WW4A2_4", - "MONITOR_WW4A2_5", - "MONITOR_WW4A2_6", - "MONITOR_WW4A2_7", - "MONITOR_WW4A2_8", - "MONITOR_WW4A2_9", - "MONITOR_WW4A3_0", - "MONITOR_WW4A3_1", - "MONITOR_WW4A3_2", - "MONITOR_WW4A3_3", - "MONITOR_WW4A3_4", - "MONITOR_WW4A3_5", - "MONITOR_WW4A3_6", - "MONITOR_WW4A3_7", - "MONITOR_WW4A3_8", - "MONITOR_WW4A3_9", - "MONITOR_WW4B0_0", - "MONITOR_WW4B0_1", - "MONITOR_WW4B0_2", - "MONITOR_WW4B0_3", - "MONITOR_WW4B0_4", - "MONITOR_WW4B0_5", - "MONITOR_WW4B0_6", - "MONITOR_WW4B0_7", - "MONITOR_WW4B0_8", - "MONITOR_WW4B0_9", - "MONITOR_WW4B1_0", - "MONITOR_WW4B1_1", - "MONITOR_WW4B1_2", - "MONITOR_WW4B1_3", - "MONITOR_WW4B1_4", - "MONITOR_WW4B1_5", - "MONITOR_WW4B1_6", - "MONITOR_WW4B1_7", - "MONITOR_WW4B1_8", - "MONITOR_WW4B1_9", - "MONITOR_WW4B2_0", - "MONITOR_WW4B2_1", - "MONITOR_WW4B2_2", - "MONITOR_WW4B2_3", - "MONITOR_WW4B2_4", - "MONITOR_WW4B2_5", - "MONITOR_WW4B2_6", - "MONITOR_WW4B2_7", - "MONITOR_WW4B2_8", - "MONITOR_WW4B2_9", - "MONITOR_WW4B3_0", - "MONITOR_WW4B3_1", - "MONITOR_WW4B3_2", - "MONITOR_WW4B3_3", - "MONITOR_WW4B3_4", - "MONITOR_WW4B3_5", - "MONITOR_WW4B3_6", - "MONITOR_WW4B3_7", - "MONITOR_WW4B3_8", - "MONITOR_WW4B3_9", - "MONITOR_WW4C0_0", - "MONITOR_WW4C0_1", - "MONITOR_WW4C0_2", - "MONITOR_WW4C0_3", - "MONITOR_WW4C0_4", - "MONITOR_WW4C0_5", - "MONITOR_WW4C0_6", - "MONITOR_WW4C0_7", - "MONITOR_WW4C0_8", - "MONITOR_WW4C0_9", - "MONITOR_WW4C1_0", - "MONITOR_WW4C1_1", - "MONITOR_WW4C1_2", - "MONITOR_WW4C1_3", - "MONITOR_WW4C1_4", - "MONITOR_WW4C1_5", - "MONITOR_WW4C1_6", - "MONITOR_WW4C1_7", - "MONITOR_WW4C1_8", - "MONITOR_WW4C1_9", - "MONITOR_WW4C2_0", - "MONITOR_WW4C2_1", - "MONITOR_WW4C2_2", - "MONITOR_WW4C2_3", - "MONITOR_WW4C2_4", - "MONITOR_WW4C2_5", - "MONITOR_WW4C2_6", - "MONITOR_WW4C2_7", - "MONITOR_WW4C2_8", - "MONITOR_WW4C2_9", - "MONITOR_WW4C3_0", - "MONITOR_WW4C3_1", - "MONITOR_WW4C3_2", - "MONITOR_WW4C3_3", - "MONITOR_WW4C3_4", - "MONITOR_WW4C3_5", - "MONITOR_WW4C3_6", - "MONITOR_WW4C3_7", - "MONITOR_WW4C3_8", - "MONITOR_WW4C3_9", - "MONITOR_WW4END0_0", - "MONITOR_WW4END0_1", - "MONITOR_WW4END0_2", - "MONITOR_WW4END0_3", - "MONITOR_WW4END0_4", - "MONITOR_WW4END0_5", - "MONITOR_WW4END0_6", - "MONITOR_WW4END0_7", - "MONITOR_WW4END0_8", - "MONITOR_WW4END0_9", - "MONITOR_WW4END1_0", - "MONITOR_WW4END1_1", - "MONITOR_WW4END1_2", - "MONITOR_WW4END1_3", - "MONITOR_WW4END1_4", - "MONITOR_WW4END1_5", - "MONITOR_WW4END1_6", - "MONITOR_WW4END1_7", - "MONITOR_WW4END1_8", - "MONITOR_WW4END1_9", - "MONITOR_WW4END2_0", - "MONITOR_WW4END2_1", - "MONITOR_WW4END2_2", - "MONITOR_WW4END2_3", - "MONITOR_WW4END2_4", - "MONITOR_WW4END2_5", - "MONITOR_WW4END2_6", - "MONITOR_WW4END2_7", - "MONITOR_WW4END2_8", - "MONITOR_WW4END2_9", - "MONITOR_WW4END3_0", - "MONITOR_WW4END3_1", - "MONITOR_WW4END3_2", - "MONITOR_WW4END3_3", - "MONITOR_WW4END3_4", - "MONITOR_WW4END3_5", - "MONITOR_WW4END3_6", - "MONITOR_WW4END3_7", - "MONITOR_WW4END3_8", - "MONITOR_WW4END3_9" - ] + "wires": { + "MONITOR_ALM0": null, + "MONITOR_ALM1": null, + "MONITOR_ALM2": null, + "MONITOR_ALM3": null, + "MONITOR_ALM4": null, + "MONITOR_ALM5": null, + "MONITOR_ALM6": null, + "MONITOR_ALM7": null, + "MONITOR_BLOCK_OUTS_B0_0": null, + "MONITOR_BLOCK_OUTS_B0_1": null, + "MONITOR_BLOCK_OUTS_B0_2": null, + "MONITOR_BLOCK_OUTS_B0_3": null, + "MONITOR_BLOCK_OUTS_B0_4": null, + "MONITOR_BLOCK_OUTS_B0_5": null, + "MONITOR_BLOCK_OUTS_B0_6": null, + "MONITOR_BLOCK_OUTS_B0_7": null, + "MONITOR_BLOCK_OUTS_B0_8": null, + "MONITOR_BLOCK_OUTS_B0_9": null, + "MONITOR_BLOCK_OUTS_B1_0": null, + "MONITOR_BLOCK_OUTS_B1_1": null, + "MONITOR_BLOCK_OUTS_B1_2": null, + "MONITOR_BLOCK_OUTS_B1_3": null, + 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"MONITOR_WW2A2_3": null, + "MONITOR_WW2A2_4": null, + "MONITOR_WW2A2_5": null, + "MONITOR_WW2A2_6": null, + "MONITOR_WW2A2_7": null, + "MONITOR_WW2A2_8": null, + "MONITOR_WW2A2_9": null, + "MONITOR_WW2A3_0": null, + "MONITOR_WW2A3_1": null, + "MONITOR_WW2A3_2": null, + "MONITOR_WW2A3_3": null, + "MONITOR_WW2A3_4": null, + "MONITOR_WW2A3_5": null, + "MONITOR_WW2A3_6": null, + "MONITOR_WW2A3_7": null, + "MONITOR_WW2A3_8": null, + "MONITOR_WW2A3_9": null, + "MONITOR_WW2END0_0": null, + "MONITOR_WW2END0_1": null, + "MONITOR_WW2END0_2": null, + "MONITOR_WW2END0_3": null, + "MONITOR_WW2END0_4": null, + "MONITOR_WW2END0_5": null, + "MONITOR_WW2END0_6": null, + "MONITOR_WW2END0_7": null, + "MONITOR_WW2END0_8": null, + "MONITOR_WW2END0_9": null, + "MONITOR_WW2END1_0": null, + "MONITOR_WW2END1_1": null, + "MONITOR_WW2END1_2": null, + "MONITOR_WW2END1_3": null, + "MONITOR_WW2END1_4": null, + "MONITOR_WW2END1_5": null, + "MONITOR_WW2END1_6": null, + "MONITOR_WW2END1_7": null, + "MONITOR_WW2END1_8": null, + "MONITOR_WW2END1_9": null, + "MONITOR_WW2END2_0": null, + "MONITOR_WW2END2_1": null, + "MONITOR_WW2END2_2": null, + "MONITOR_WW2END2_3": null, + "MONITOR_WW2END2_4": null, + "MONITOR_WW2END2_5": null, + "MONITOR_WW2END2_6": null, + "MONITOR_WW2END2_7": null, + "MONITOR_WW2END2_8": null, + "MONITOR_WW2END2_9": null, + "MONITOR_WW2END3_0": null, + "MONITOR_WW2END3_1": null, + "MONITOR_WW2END3_2": null, + "MONITOR_WW2END3_3": null, + "MONITOR_WW2END3_4": null, + "MONITOR_WW2END3_5": null, + "MONITOR_WW2END3_6": null, + "MONITOR_WW2END3_7": null, + "MONITOR_WW2END3_8": null, + "MONITOR_WW2END3_9": null, + "MONITOR_WW4A0_0": null, + "MONITOR_WW4A0_1": null, + "MONITOR_WW4A0_2": null, + "MONITOR_WW4A0_3": null, + "MONITOR_WW4A0_4": null, + "MONITOR_WW4A0_5": null, + "MONITOR_WW4A0_6": null, + "MONITOR_WW4A0_7": null, + "MONITOR_WW4A0_8": null, + "MONITOR_WW4A0_9": null, + "MONITOR_WW4A1_0": null, + "MONITOR_WW4A1_1": null, + "MONITOR_WW4A1_2": null, + "MONITOR_WW4A1_3": null, + "MONITOR_WW4A1_4": null, + "MONITOR_WW4A1_5": null, + "MONITOR_WW4A1_6": null, + "MONITOR_WW4A1_7": null, + "MONITOR_WW4A1_8": null, + "MONITOR_WW4A1_9": null, + "MONITOR_WW4A2_0": null, + "MONITOR_WW4A2_1": null, + "MONITOR_WW4A2_2": null, + "MONITOR_WW4A2_3": null, + "MONITOR_WW4A2_4": null, + "MONITOR_WW4A2_5": null, + "MONITOR_WW4A2_6": null, + "MONITOR_WW4A2_7": null, + "MONITOR_WW4A2_8": null, + "MONITOR_WW4A2_9": null, + "MONITOR_WW4A3_0": null, + "MONITOR_WW4A3_1": null, + "MONITOR_WW4A3_2": null, + "MONITOR_WW4A3_3": null, + "MONITOR_WW4A3_4": null, + "MONITOR_WW4A3_5": null, + "MONITOR_WW4A3_6": null, + "MONITOR_WW4A3_7": null, + "MONITOR_WW4A3_8": null, + "MONITOR_WW4A3_9": null, + "MONITOR_WW4B0_0": null, + "MONITOR_WW4B0_1": null, + "MONITOR_WW4B0_2": null, + "MONITOR_WW4B0_3": null, + "MONITOR_WW4B0_4": null, + "MONITOR_WW4B0_5": null, + "MONITOR_WW4B0_6": null, + "MONITOR_WW4B0_7": null, + "MONITOR_WW4B0_8": null, + "MONITOR_WW4B0_9": null, + "MONITOR_WW4B1_0": null, + "MONITOR_WW4B1_1": null, + "MONITOR_WW4B1_2": null, + "MONITOR_WW4B1_3": null, + "MONITOR_WW4B1_4": null, + "MONITOR_WW4B1_5": null, + "MONITOR_WW4B1_6": null, + "MONITOR_WW4B1_7": null, + "MONITOR_WW4B1_8": null, + "MONITOR_WW4B1_9": null, + "MONITOR_WW4B2_0": null, + "MONITOR_WW4B2_1": null, + "MONITOR_WW4B2_2": null, + "MONITOR_WW4B2_3": null, + "MONITOR_WW4B2_4": null, + "MONITOR_WW4B2_5": null, + "MONITOR_WW4B2_6": null, + "MONITOR_WW4B2_7": null, + "MONITOR_WW4B2_8": null, + "MONITOR_WW4B2_9": null, + "MONITOR_WW4B3_0": null, + "MONITOR_WW4B3_1": null, + "MONITOR_WW4B3_2": null, + "MONITOR_WW4B3_3": null, + "MONITOR_WW4B3_4": null, + "MONITOR_WW4B3_5": null, + "MONITOR_WW4B3_6": null, + "MONITOR_WW4B3_7": null, + "MONITOR_WW4B3_8": null, + "MONITOR_WW4B3_9": null, + "MONITOR_WW4C0_0": null, + "MONITOR_WW4C0_1": null, + "MONITOR_WW4C0_2": null, + "MONITOR_WW4C0_3": null, + "MONITOR_WW4C0_4": null, + "MONITOR_WW4C0_5": null, + "MONITOR_WW4C0_6": null, + "MONITOR_WW4C0_7": null, + "MONITOR_WW4C0_8": null, + "MONITOR_WW4C0_9": null, + "MONITOR_WW4C1_0": null, + "MONITOR_WW4C1_1": null, + "MONITOR_WW4C1_2": null, + "MONITOR_WW4C1_3": null, + "MONITOR_WW4C1_4": null, + "MONITOR_WW4C1_5": null, + "MONITOR_WW4C1_6": null, + "MONITOR_WW4C1_7": null, + "MONITOR_WW4C1_8": null, + "MONITOR_WW4C1_9": null, + "MONITOR_WW4C2_0": null, + "MONITOR_WW4C2_1": null, + "MONITOR_WW4C2_2": null, + "MONITOR_WW4C2_3": null, + "MONITOR_WW4C2_4": null, + "MONITOR_WW4C2_5": null, + "MONITOR_WW4C2_6": null, + "MONITOR_WW4C2_7": null, + "MONITOR_WW4C2_8": null, + "MONITOR_WW4C2_9": null, + "MONITOR_WW4C3_0": null, + "MONITOR_WW4C3_1": null, + "MONITOR_WW4C3_2": null, + "MONITOR_WW4C3_3": null, + "MONITOR_WW4C3_4": null, + "MONITOR_WW4C3_5": null, + "MONITOR_WW4C3_6": null, + "MONITOR_WW4C3_7": null, + "MONITOR_WW4C3_8": null, + "MONITOR_WW4C3_9": null, + "MONITOR_WW4END0_0": null, + "MONITOR_WW4END0_1": null, + "MONITOR_WW4END0_2": null, + "MONITOR_WW4END0_3": null, + "MONITOR_WW4END0_4": null, + "MONITOR_WW4END0_5": null, + "MONITOR_WW4END0_6": null, + "MONITOR_WW4END0_7": null, + "MONITOR_WW4END0_8": null, + "MONITOR_WW4END0_9": null, + "MONITOR_WW4END1_0": null, + "MONITOR_WW4END1_1": null, + "MONITOR_WW4END1_2": null, + "MONITOR_WW4END1_3": null, + "MONITOR_WW4END1_4": null, + "MONITOR_WW4END1_5": null, + "MONITOR_WW4END1_6": null, + "MONITOR_WW4END1_7": null, + "MONITOR_WW4END1_8": null, + "MONITOR_WW4END1_9": null, + "MONITOR_WW4END2_0": null, + "MONITOR_WW4END2_1": null, + "MONITOR_WW4END2_2": null, + "MONITOR_WW4END2_3": null, + "MONITOR_WW4END2_4": null, + "MONITOR_WW4END2_5": null, + "MONITOR_WW4END2_6": null, + "MONITOR_WW4END2_7": null, + "MONITOR_WW4END2_8": null, + "MONITOR_WW4END2_9": null, + "MONITOR_WW4END3_0": null, + "MONITOR_WW4END3_1": null, + "MONITOR_WW4END3_2": null, + "MONITOR_WW4END3_3": null, + "MONITOR_WW4END3_4": null, + "MONITOR_WW4END3_5": null, + "MONITOR_WW4END3_6": null, + "MONITOR_WW4END3_7": null, + "MONITOR_WW4END3_8": null, + "MONITOR_WW4END3_9": null + } } diff --git a/kintex7/tile_type_MONITOR_MID_FUJI2.json b/kintex7/tile_type_MONITOR_MID_FUJI2.json index 45463b5..74cc014 100644 --- a/kintex7/tile_type_MONITOR_MID_FUJI2.json +++ b/kintex7/tile_type_MONITOR_MID_FUJI2.json @@ -2,2303 +2,2391 @@ "pips": { "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXN1->MONITOR_VERT_VAUXN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN1" }, "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXN10->MONITOR_VERT_VAUXN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN10" }, "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXN2->MONITOR_VERT_VAUXN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN2" }, "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXN9->MONITOR_VERT_VAUXN9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXN9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN9" }, "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXP1->MONITOR_VERT_VAUXP1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP1" }, "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXP10->MONITOR_VERT_VAUXP10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP10" }, "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXP2->MONITOR_VERT_VAUXP2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP2" }, "MONITOR_MID_FUJI2.MONITOR_HORIZ_VAUXP9->MONITOR_VERT_VAUXP9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_VAUXP9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP9" } }, "sites": [], "tile_type": "MONITOR_MID_FUJI2", - "wires": [ - "MONITOR_BLOCK_OUTS_B0_0", - "MONITOR_BLOCK_OUTS_B0_1", - "MONITOR_BLOCK_OUTS_B0_2", - "MONITOR_BLOCK_OUTS_B0_3", - "MONITOR_BLOCK_OUTS_B0_4", - "MONITOR_BLOCK_OUTS_B0_5", - "MONITOR_BLOCK_OUTS_B0_6", - "MONITOR_BLOCK_OUTS_B0_7", - "MONITOR_BLOCK_OUTS_B0_8", - "MONITOR_BLOCK_OUTS_B0_9", - "MONITOR_BLOCK_OUTS_B1_0", - "MONITOR_BLOCK_OUTS_B1_1", - "MONITOR_BLOCK_OUTS_B1_2", - "MONITOR_BLOCK_OUTS_B1_3", - "MONITOR_BLOCK_OUTS_B1_4", - "MONITOR_BLOCK_OUTS_B1_5", - "MONITOR_BLOCK_OUTS_B1_6", - "MONITOR_BLOCK_OUTS_B1_7", - "MONITOR_BLOCK_OUTS_B1_8", - "MONITOR_BLOCK_OUTS_B1_9", - "MONITOR_BLOCK_OUTS_B2_0", - "MONITOR_BLOCK_OUTS_B2_1", - "MONITOR_BLOCK_OUTS_B2_2", - "MONITOR_BLOCK_OUTS_B2_3", - "MONITOR_BLOCK_OUTS_B2_4", - "MONITOR_BLOCK_OUTS_B2_5", - "MONITOR_BLOCK_OUTS_B2_6", - "MONITOR_BLOCK_OUTS_B2_7", - "MONITOR_BLOCK_OUTS_B2_8", - "MONITOR_BLOCK_OUTS_B2_9", - "MONITOR_BLOCK_OUTS_B3_0", - "MONITOR_BLOCK_OUTS_B3_1", - "MONITOR_BLOCK_OUTS_B3_2", - "MONITOR_BLOCK_OUTS_B3_3", - "MONITOR_BLOCK_OUTS_B3_4", - "MONITOR_BLOCK_OUTS_B3_5", - "MONITOR_BLOCK_OUTS_B3_6", - "MONITOR_BLOCK_OUTS_B3_7", - "MONITOR_BLOCK_OUTS_B3_8", - "MONITOR_BLOCK_OUTS_B3_9", - "MONITOR_BYP0_0", - "MONITOR_BYP0_1", - "MONITOR_BYP0_2", - "MONITOR_BYP0_3", - "MONITOR_BYP0_4", - "MONITOR_BYP0_5", - "MONITOR_BYP0_6", - "MONITOR_BYP0_7", - "MONITOR_BYP0_8", - "MONITOR_BYP0_9", - "MONITOR_BYP1_0", - "MONITOR_BYP1_1", - "MONITOR_BYP1_2", - "MONITOR_BYP1_3", - "MONITOR_BYP1_4", - "MONITOR_BYP1_5", - "MONITOR_BYP1_6", - "MONITOR_BYP1_7", - "MONITOR_BYP1_8", - "MONITOR_BYP1_9", - "MONITOR_BYP2_0", - "MONITOR_BYP2_1", - "MONITOR_BYP2_2", - "MONITOR_BYP2_3", - "MONITOR_BYP2_4", - "MONITOR_BYP2_5", - "MONITOR_BYP2_6", - "MONITOR_BYP2_7", - "MONITOR_BYP2_8", - "MONITOR_BYP2_9", - "MONITOR_BYP3_0", - "MONITOR_BYP3_1", - "MONITOR_BYP3_2", - "MONITOR_BYP3_3", - "MONITOR_BYP3_4", - "MONITOR_BYP3_5", - "MONITOR_BYP3_6", - "MONITOR_BYP3_7", - "MONITOR_BYP3_8", - "MONITOR_BYP3_9", - "MONITOR_BYP4_0", - "MONITOR_BYP4_1", - "MONITOR_BYP4_2", - "MONITOR_BYP4_3", - "MONITOR_BYP4_4", - "MONITOR_BYP4_5", - "MONITOR_BYP4_6", - "MONITOR_BYP4_7", - "MONITOR_BYP4_8", - "MONITOR_BYP4_9", - "MONITOR_BYP5_0", - "MONITOR_BYP5_1", - "MONITOR_BYP5_2", - "MONITOR_BYP5_3", - "MONITOR_BYP5_4", - "MONITOR_BYP5_5", - "MONITOR_BYP5_6", - "MONITOR_BYP5_7", - "MONITOR_BYP5_8", - "MONITOR_BYP5_9", - "MONITOR_BYP6_0", - "MONITOR_BYP6_1", - "MONITOR_BYP6_2", - "MONITOR_BYP6_3", - "MONITOR_BYP6_4", - "MONITOR_BYP6_5", - "MONITOR_BYP6_6", - "MONITOR_BYP6_7", - "MONITOR_BYP6_8", - "MONITOR_BYP6_9", - "MONITOR_BYP7_0", - "MONITOR_BYP7_1", - "MONITOR_BYP7_2", - "MONITOR_BYP7_3", - "MONITOR_BYP7_4", - "MONITOR_BYP7_5", - "MONITOR_BYP7_6", - "MONITOR_BYP7_7", - "MONITOR_BYP7_8", - "MONITOR_BYP7_9", - "MONITOR_CLK0_0", - "MONITOR_CLK0_1", - "MONITOR_CLK0_2", - "MONITOR_CLK0_3", - "MONITOR_CLK0_4", - "MONITOR_CLK0_5", - "MONITOR_CLK0_6", - "MONITOR_CLK0_7", - "MONITOR_CLK0_8", - "MONITOR_CLK0_9", - "MONITOR_CLK1_0", - "MONITOR_CLK1_1", - "MONITOR_CLK1_2", - "MONITOR_CLK1_3", - "MONITOR_CLK1_4", - "MONITOR_CLK1_5", - "MONITOR_CLK1_6", - "MONITOR_CLK1_7", - "MONITOR_CLK1_8", - "MONITOR_CLK1_9", - "MONITOR_CTRL0_0", - "MONITOR_CTRL0_1", - "MONITOR_CTRL0_2", - "MONITOR_CTRL0_3", - "MONITOR_CTRL0_4", - "MONITOR_CTRL0_5", - "MONITOR_CTRL0_6", - "MONITOR_CTRL0_7", - "MONITOR_CTRL0_8", - "MONITOR_CTRL0_9", - "MONITOR_CTRL1_0", - "MONITOR_CTRL1_1", - "MONITOR_CTRL1_2", - "MONITOR_CTRL1_3", - "MONITOR_CTRL1_4", - "MONITOR_CTRL1_5", - "MONITOR_CTRL1_6", - "MONITOR_CTRL1_7", - "MONITOR_CTRL1_8", - "MONITOR_CTRL1_9", - "MONITOR_EE2A0_0", - "MONITOR_EE2A0_1", - "MONITOR_EE2A0_2", - "MONITOR_EE2A0_3", - "MONITOR_EE2A0_4", - "MONITOR_EE2A0_5", - "MONITOR_EE2A0_6", - "MONITOR_EE2A0_7", - "MONITOR_EE2A0_8", - "MONITOR_EE2A0_9", - "MONITOR_EE2A1_0", - "MONITOR_EE2A1_1", - "MONITOR_EE2A1_2", - "MONITOR_EE2A1_3", - "MONITOR_EE2A1_4", - "MONITOR_EE2A1_5", - "MONITOR_EE2A1_6", - "MONITOR_EE2A1_7", - "MONITOR_EE2A1_8", - "MONITOR_EE2A1_9", - "MONITOR_EE2A2_0", - "MONITOR_EE2A2_1", - "MONITOR_EE2A2_2", - "MONITOR_EE2A2_3", - "MONITOR_EE2A2_4", - "MONITOR_EE2A2_5", - "MONITOR_EE2A2_6", - "MONITOR_EE2A2_7", - "MONITOR_EE2A2_8", - "MONITOR_EE2A2_9", - "MONITOR_EE2A3_0", - "MONITOR_EE2A3_1", - "MONITOR_EE2A3_2", - "MONITOR_EE2A3_3", - "MONITOR_EE2A3_4", - "MONITOR_EE2A3_5", - "MONITOR_EE2A3_6", - "MONITOR_EE2A3_7", - "MONITOR_EE2A3_8", - "MONITOR_EE2A3_9", - "MONITOR_EE2BEG0_0", - "MONITOR_EE2BEG0_1", - "MONITOR_EE2BEG0_2", - "MONITOR_EE2BEG0_3", - "MONITOR_EE2BEG0_4", - "MONITOR_EE2BEG0_5", - "MONITOR_EE2BEG0_6", - "MONITOR_EE2BEG0_7", - "MONITOR_EE2BEG0_8", - "MONITOR_EE2BEG0_9", - "MONITOR_EE2BEG1_0", - "MONITOR_EE2BEG1_1", - "MONITOR_EE2BEG1_2", - "MONITOR_EE2BEG1_3", - "MONITOR_EE2BEG1_4", - "MONITOR_EE2BEG1_5", - "MONITOR_EE2BEG1_6", - "MONITOR_EE2BEG1_7", - "MONITOR_EE2BEG1_8", - "MONITOR_EE2BEG1_9", - "MONITOR_EE2BEG2_0", - "MONITOR_EE2BEG2_1", - "MONITOR_EE2BEG2_2", - "MONITOR_EE2BEG2_3", - "MONITOR_EE2BEG2_4", - "MONITOR_EE2BEG2_5", - "MONITOR_EE2BEG2_6", - "MONITOR_EE2BEG2_7", - "MONITOR_EE2BEG2_8", - "MONITOR_EE2BEG2_9", - "MONITOR_EE2BEG3_0", - "MONITOR_EE2BEG3_1", - "MONITOR_EE2BEG3_2", - "MONITOR_EE2BEG3_3", - "MONITOR_EE2BEG3_4", - "MONITOR_EE2BEG3_5", - "MONITOR_EE2BEG3_6", - "MONITOR_EE2BEG3_7", - "MONITOR_EE2BEG3_8", - "MONITOR_EE2BEG3_9", - "MONITOR_EE4A0_0", - "MONITOR_EE4A0_1", - "MONITOR_EE4A0_2", - "MONITOR_EE4A0_3", - "MONITOR_EE4A0_4", - "MONITOR_EE4A0_5", - "MONITOR_EE4A0_6", - "MONITOR_EE4A0_7", - "MONITOR_EE4A0_8", - "MONITOR_EE4A0_9", - "MONITOR_EE4A1_0", - "MONITOR_EE4A1_1", - "MONITOR_EE4A1_2", - "MONITOR_EE4A1_3", - "MONITOR_EE4A1_4", - "MONITOR_EE4A1_5", - "MONITOR_EE4A1_6", - "MONITOR_EE4A1_7", - "MONITOR_EE4A1_8", - "MONITOR_EE4A1_9", - "MONITOR_EE4A2_0", - "MONITOR_EE4A2_1", - "MONITOR_EE4A2_2", - "MONITOR_EE4A2_3", - "MONITOR_EE4A2_4", - "MONITOR_EE4A2_5", - "MONITOR_EE4A2_6", - "MONITOR_EE4A2_7", - "MONITOR_EE4A2_8", - "MONITOR_EE4A2_9", - "MONITOR_EE4A3_0", - "MONITOR_EE4A3_1", - "MONITOR_EE4A3_2", - "MONITOR_EE4A3_3", - "MONITOR_EE4A3_4", - "MONITOR_EE4A3_5", - "MONITOR_EE4A3_6", - "MONITOR_EE4A3_7", - "MONITOR_EE4A3_8", - "MONITOR_EE4A3_9", - "MONITOR_EE4B0_0", - "MONITOR_EE4B0_1", - "MONITOR_EE4B0_2", - "MONITOR_EE4B0_3", - "MONITOR_EE4B0_4", - "MONITOR_EE4B0_5", - "MONITOR_EE4B0_6", - "MONITOR_EE4B0_7", - "MONITOR_EE4B0_8", - "MONITOR_EE4B0_9", - "MONITOR_EE4B1_0", - "MONITOR_EE4B1_1", - "MONITOR_EE4B1_2", - "MONITOR_EE4B1_3", - "MONITOR_EE4B1_4", - "MONITOR_EE4B1_5", - "MONITOR_EE4B1_6", - "MONITOR_EE4B1_7", - "MONITOR_EE4B1_8", - "MONITOR_EE4B1_9", - "MONITOR_EE4B2_0", - "MONITOR_EE4B2_1", - "MONITOR_EE4B2_2", - "MONITOR_EE4B2_3", - "MONITOR_EE4B2_4", - "MONITOR_EE4B2_5", - "MONITOR_EE4B2_6", - "MONITOR_EE4B2_7", - "MONITOR_EE4B2_8", - "MONITOR_EE4B2_9", - "MONITOR_EE4B3_0", - "MONITOR_EE4B3_1", - "MONITOR_EE4B3_2", - "MONITOR_EE4B3_3", - "MONITOR_EE4B3_4", - "MONITOR_EE4B3_5", - "MONITOR_EE4B3_6", - "MONITOR_EE4B3_7", - "MONITOR_EE4B3_8", - "MONITOR_EE4B3_9", - "MONITOR_EE4BEG0_0", - "MONITOR_EE4BEG0_1", - "MONITOR_EE4BEG0_2", - "MONITOR_EE4BEG0_3", - "MONITOR_EE4BEG0_4", - "MONITOR_EE4BEG0_5", - "MONITOR_EE4BEG0_6", - "MONITOR_EE4BEG0_7", - "MONITOR_EE4BEG0_8", - "MONITOR_EE4BEG0_9", - "MONITOR_EE4BEG1_0", - "MONITOR_EE4BEG1_1", - "MONITOR_EE4BEG1_2", - "MONITOR_EE4BEG1_3", - "MONITOR_EE4BEG1_4", - "MONITOR_EE4BEG1_5", - "MONITOR_EE4BEG1_6", - "MONITOR_EE4BEG1_7", - "MONITOR_EE4BEG1_8", - "MONITOR_EE4BEG1_9", - "MONITOR_EE4BEG2_0", - "MONITOR_EE4BEG2_1", - "MONITOR_EE4BEG2_2", - "MONITOR_EE4BEG2_3", - "MONITOR_EE4BEG2_4", - "MONITOR_EE4BEG2_5", - "MONITOR_EE4BEG2_6", - "MONITOR_EE4BEG2_7", - "MONITOR_EE4BEG2_8", - "MONITOR_EE4BEG2_9", - "MONITOR_EE4BEG3_0", - "MONITOR_EE4BEG3_1", - "MONITOR_EE4BEG3_2", - "MONITOR_EE4BEG3_3", - "MONITOR_EE4BEG3_4", - "MONITOR_EE4BEG3_5", - "MONITOR_EE4BEG3_6", - "MONITOR_EE4BEG3_7", - "MONITOR_EE4BEG3_8", - "MONITOR_EE4BEG3_9", - "MONITOR_EE4C0_0", - "MONITOR_EE4C0_1", - "MONITOR_EE4C0_2", - "MONITOR_EE4C0_3", - "MONITOR_EE4C0_4", - "MONITOR_EE4C0_5", - "MONITOR_EE4C0_6", - "MONITOR_EE4C0_7", - "MONITOR_EE4C0_8", - "MONITOR_EE4C0_9", - "MONITOR_EE4C1_0", - "MONITOR_EE4C1_1", - "MONITOR_EE4C1_2", - "MONITOR_EE4C1_3", - "MONITOR_EE4C1_4", - "MONITOR_EE4C1_5", - "MONITOR_EE4C1_6", - "MONITOR_EE4C1_7", - "MONITOR_EE4C1_8", - "MONITOR_EE4C1_9", - "MONITOR_EE4C2_0", - "MONITOR_EE4C2_1", - "MONITOR_EE4C2_2", - "MONITOR_EE4C2_3", - "MONITOR_EE4C2_4", - "MONITOR_EE4C2_5", - "MONITOR_EE4C2_6", - "MONITOR_EE4C2_7", - "MONITOR_EE4C2_8", - "MONITOR_EE4C2_9", - "MONITOR_EE4C3_0", - "MONITOR_EE4C3_1", - "MONITOR_EE4C3_2", - "MONITOR_EE4C3_3", - "MONITOR_EE4C3_4", - "MONITOR_EE4C3_5", - "MONITOR_EE4C3_6", - "MONITOR_EE4C3_7", - "MONITOR_EE4C3_8", - "MONITOR_EE4C3_9", - "MONITOR_EL1BEG0_0", - "MONITOR_EL1BEG0_1", - "MONITOR_EL1BEG0_2", - "MONITOR_EL1BEG0_3", - "MONITOR_EL1BEG0_4", - "MONITOR_EL1BEG0_5", - "MONITOR_EL1BEG0_6", - "MONITOR_EL1BEG0_7", - "MONITOR_EL1BEG0_8", - "MONITOR_EL1BEG0_9", - "MONITOR_EL1BEG1_0", - "MONITOR_EL1BEG1_1", - "MONITOR_EL1BEG1_2", - "MONITOR_EL1BEG1_3", - "MONITOR_EL1BEG1_4", - "MONITOR_EL1BEG1_5", - "MONITOR_EL1BEG1_6", - "MONITOR_EL1BEG1_7", - "MONITOR_EL1BEG1_8", - "MONITOR_EL1BEG1_9", - "MONITOR_EL1BEG2_0", - "MONITOR_EL1BEG2_1", - "MONITOR_EL1BEG2_2", - "MONITOR_EL1BEG2_3", - "MONITOR_EL1BEG2_4", - "MONITOR_EL1BEG2_5", - "MONITOR_EL1BEG2_6", - "MONITOR_EL1BEG2_7", - "MONITOR_EL1BEG2_8", - "MONITOR_EL1BEG2_9", - "MONITOR_EL1BEG3_0", - "MONITOR_EL1BEG3_1", - "MONITOR_EL1BEG3_2", - "MONITOR_EL1BEG3_3", - "MONITOR_EL1BEG3_4", - "MONITOR_EL1BEG3_5", - "MONITOR_EL1BEG3_6", - "MONITOR_EL1BEG3_7", - "MONITOR_EL1BEG3_8", - "MONITOR_EL1BEG3_9", - "MONITOR_ER1BEG0_0", - "MONITOR_ER1BEG0_1", - "MONITOR_ER1BEG0_2", - "MONITOR_ER1BEG0_3", - "MONITOR_ER1BEG0_4", - "MONITOR_ER1BEG0_5", - "MONITOR_ER1BEG0_6", - "MONITOR_ER1BEG0_7", - "MONITOR_ER1BEG0_8", - "MONITOR_ER1BEG0_9", - "MONITOR_ER1BEG1_0", - "MONITOR_ER1BEG1_1", - "MONITOR_ER1BEG1_2", - "MONITOR_ER1BEG1_3", - "MONITOR_ER1BEG1_4", - "MONITOR_ER1BEG1_5", - "MONITOR_ER1BEG1_6", - "MONITOR_ER1BEG1_7", - "MONITOR_ER1BEG1_8", - "MONITOR_ER1BEG1_9", - "MONITOR_ER1BEG2_0", - "MONITOR_ER1BEG2_1", - "MONITOR_ER1BEG2_2", - "MONITOR_ER1BEG2_3", - "MONITOR_ER1BEG2_4", - "MONITOR_ER1BEG2_5", - "MONITOR_ER1BEG2_6", - "MONITOR_ER1BEG2_7", - "MONITOR_ER1BEG2_8", - "MONITOR_ER1BEG2_9", - "MONITOR_ER1BEG3_0", - "MONITOR_ER1BEG3_1", - "MONITOR_ER1BEG3_2", - "MONITOR_ER1BEG3_3", - "MONITOR_ER1BEG3_4", - "MONITOR_ER1BEG3_5", - "MONITOR_ER1BEG3_6", - "MONITOR_ER1BEG3_7", - "MONITOR_ER1BEG3_8", - "MONITOR_ER1BEG3_9", - "MONITOR_FAN0_0", - "MONITOR_FAN0_1", - "MONITOR_FAN0_2", - "MONITOR_FAN0_3", - "MONITOR_FAN0_4", - "MONITOR_FAN0_5", - "MONITOR_FAN0_6", - "MONITOR_FAN0_7", - "MONITOR_FAN0_8", - "MONITOR_FAN0_9", - "MONITOR_FAN1_0", - "MONITOR_FAN1_1", - "MONITOR_FAN1_2", - "MONITOR_FAN1_3", - "MONITOR_FAN1_4", - "MONITOR_FAN1_5", - "MONITOR_FAN1_6", - "MONITOR_FAN1_7", - "MONITOR_FAN1_8", - "MONITOR_FAN1_9", - "MONITOR_FAN2_0", - "MONITOR_FAN2_1", - "MONITOR_FAN2_2", - "MONITOR_FAN2_3", - "MONITOR_FAN2_4", - "MONITOR_FAN2_5", - "MONITOR_FAN2_6", - "MONITOR_FAN2_7", - "MONITOR_FAN2_8", - "MONITOR_FAN2_9", - "MONITOR_FAN3_0", - "MONITOR_FAN3_1", - "MONITOR_FAN3_2", - "MONITOR_FAN3_3", - "MONITOR_FAN3_4", - "MONITOR_FAN3_5", - "MONITOR_FAN3_6", - "MONITOR_FAN3_7", - "MONITOR_FAN3_8", - "MONITOR_FAN3_9", - "MONITOR_FAN4_0", - "MONITOR_FAN4_1", - "MONITOR_FAN4_2", - "MONITOR_FAN4_3", - "MONITOR_FAN4_4", - "MONITOR_FAN4_5", - "MONITOR_FAN4_6", - "MONITOR_FAN4_7", - "MONITOR_FAN4_8", - "MONITOR_FAN4_9", - "MONITOR_FAN5_0", - "MONITOR_FAN5_1", - "MONITOR_FAN5_2", - "MONITOR_FAN5_3", - "MONITOR_FAN5_4", - "MONITOR_FAN5_5", - "MONITOR_FAN5_6", - "MONITOR_FAN5_7", - "MONITOR_FAN5_8", - "MONITOR_FAN5_9", - "MONITOR_FAN6_0", - "MONITOR_FAN6_1", - "MONITOR_FAN6_2", - "MONITOR_FAN6_3", - "MONITOR_FAN6_4", - "MONITOR_FAN6_5", - "MONITOR_FAN6_6", - "MONITOR_FAN6_7", - "MONITOR_FAN6_8", - "MONITOR_FAN6_9", - "MONITOR_FAN7_0", - "MONITOR_FAN7_1", - "MONITOR_FAN7_2", - "MONITOR_FAN7_3", - "MONITOR_FAN7_4", - "MONITOR_FAN7_5", - "MONITOR_FAN7_6", - "MONITOR_FAN7_7", - "MONITOR_FAN7_8", - "MONITOR_FAN7_9", - "MONITOR_HORIZ_VAUXN1", - "MONITOR_HORIZ_VAUXN10", - "MONITOR_HORIZ_VAUXN2", - "MONITOR_HORIZ_VAUXN9", - "MONITOR_HORIZ_VAUXP1", - "MONITOR_HORIZ_VAUXP10", - "MONITOR_HORIZ_VAUXP2", - "MONITOR_HORIZ_VAUXP9", - "MONITOR_IMUX0_0", - "MONITOR_IMUX0_1", - "MONITOR_IMUX0_2", - "MONITOR_IMUX0_3", - "MONITOR_IMUX0_4", - "MONITOR_IMUX0_5", - "MONITOR_IMUX0_6", - "MONITOR_IMUX0_7", - "MONITOR_IMUX0_8", - "MONITOR_IMUX0_9", - "MONITOR_IMUX10_0", - "MONITOR_IMUX10_1", - "MONITOR_IMUX10_2", - "MONITOR_IMUX10_3", - "MONITOR_IMUX10_4", - "MONITOR_IMUX10_5", - "MONITOR_IMUX10_6", - "MONITOR_IMUX10_7", - "MONITOR_IMUX10_8", - "MONITOR_IMUX10_9", - "MONITOR_IMUX11_0", - "MONITOR_IMUX11_1", - "MONITOR_IMUX11_2", - "MONITOR_IMUX11_3", - "MONITOR_IMUX11_4", - "MONITOR_IMUX11_5", - "MONITOR_IMUX11_6", - "MONITOR_IMUX11_7", - "MONITOR_IMUX11_8", - "MONITOR_IMUX11_9", - "MONITOR_IMUX12_0", - "MONITOR_IMUX12_1", - "MONITOR_IMUX12_2", - "MONITOR_IMUX12_3", - "MONITOR_IMUX12_4", - "MONITOR_IMUX12_5", - "MONITOR_IMUX12_6", - "MONITOR_IMUX12_7", - "MONITOR_IMUX12_8", - "MONITOR_IMUX12_9", - "MONITOR_IMUX13_0", - "MONITOR_IMUX13_1", - "MONITOR_IMUX13_2", - "MONITOR_IMUX13_3", - "MONITOR_IMUX13_4", - "MONITOR_IMUX13_5", - "MONITOR_IMUX13_6", - "MONITOR_IMUX13_7", - "MONITOR_IMUX13_8", - "MONITOR_IMUX13_9", - "MONITOR_IMUX14_0", - "MONITOR_IMUX14_1", - "MONITOR_IMUX14_2", - "MONITOR_IMUX14_3", - "MONITOR_IMUX14_4", - "MONITOR_IMUX14_5", - "MONITOR_IMUX14_6", - "MONITOR_IMUX14_7", - "MONITOR_IMUX14_8", - "MONITOR_IMUX14_9", - "MONITOR_IMUX15_0", - "MONITOR_IMUX15_1", - "MONITOR_IMUX15_2", - "MONITOR_IMUX15_3", - "MONITOR_IMUX15_4", - "MONITOR_IMUX15_5", - "MONITOR_IMUX15_6", - "MONITOR_IMUX15_7", - "MONITOR_IMUX15_8", - "MONITOR_IMUX15_9", - "MONITOR_IMUX16_0", - "MONITOR_IMUX16_1", - "MONITOR_IMUX16_2", - "MONITOR_IMUX16_3", - "MONITOR_IMUX16_4", - "MONITOR_IMUX16_5", - "MONITOR_IMUX16_6", - "MONITOR_IMUX16_7", - "MONITOR_IMUX16_8", - "MONITOR_IMUX16_9", - "MONITOR_IMUX17_0", - "MONITOR_IMUX17_1", - "MONITOR_IMUX17_2", - "MONITOR_IMUX17_3", - "MONITOR_IMUX17_4", - "MONITOR_IMUX17_5", - "MONITOR_IMUX17_6", - "MONITOR_IMUX17_7", - "MONITOR_IMUX17_8", - "MONITOR_IMUX17_9", - "MONITOR_IMUX18_0", - "MONITOR_IMUX18_1", - "MONITOR_IMUX18_2", - "MONITOR_IMUX18_3", - "MONITOR_IMUX18_4", - "MONITOR_IMUX18_5", - "MONITOR_IMUX18_6", - "MONITOR_IMUX18_7", - "MONITOR_IMUX18_8", - "MONITOR_IMUX18_9", - "MONITOR_IMUX19_0", - "MONITOR_IMUX19_1", - "MONITOR_IMUX19_2", - "MONITOR_IMUX19_3", - "MONITOR_IMUX19_4", - "MONITOR_IMUX19_5", - "MONITOR_IMUX19_6", - "MONITOR_IMUX19_7", - "MONITOR_IMUX19_8", - "MONITOR_IMUX19_9", - "MONITOR_IMUX1_0", - "MONITOR_IMUX1_1", - "MONITOR_IMUX1_2", - "MONITOR_IMUX1_3", - "MONITOR_IMUX1_4", - "MONITOR_IMUX1_5", - "MONITOR_IMUX1_6", - "MONITOR_IMUX1_7", - "MONITOR_IMUX1_8", - "MONITOR_IMUX1_9", - "MONITOR_IMUX20_0", - "MONITOR_IMUX20_1", - "MONITOR_IMUX20_2", - "MONITOR_IMUX20_3", - "MONITOR_IMUX20_4", - "MONITOR_IMUX20_5", - "MONITOR_IMUX20_6", - "MONITOR_IMUX20_7", - "MONITOR_IMUX20_8", - "MONITOR_IMUX20_9", - "MONITOR_IMUX21_0", - "MONITOR_IMUX21_1", - "MONITOR_IMUX21_2", - "MONITOR_IMUX21_3", - "MONITOR_IMUX21_4", - "MONITOR_IMUX21_5", - "MONITOR_IMUX21_6", - "MONITOR_IMUX21_7", - "MONITOR_IMUX21_8", - "MONITOR_IMUX21_9", - "MONITOR_IMUX22_0", - "MONITOR_IMUX22_1", - "MONITOR_IMUX22_2", - "MONITOR_IMUX22_3", - "MONITOR_IMUX22_4", - "MONITOR_IMUX22_5", - "MONITOR_IMUX22_6", - "MONITOR_IMUX22_7", - "MONITOR_IMUX22_8", - "MONITOR_IMUX22_9", - "MONITOR_IMUX23_0", - "MONITOR_IMUX23_1", - "MONITOR_IMUX23_2", - "MONITOR_IMUX23_3", - "MONITOR_IMUX23_4", - "MONITOR_IMUX23_5", - "MONITOR_IMUX23_6", - "MONITOR_IMUX23_7", - "MONITOR_IMUX23_8", - "MONITOR_IMUX23_9", - "MONITOR_IMUX24_0", - "MONITOR_IMUX24_1", - "MONITOR_IMUX24_2", - "MONITOR_IMUX24_3", - "MONITOR_IMUX24_4", - "MONITOR_IMUX24_5", - "MONITOR_IMUX24_6", - "MONITOR_IMUX24_7", - "MONITOR_IMUX24_8", - "MONITOR_IMUX24_9", - "MONITOR_IMUX25_0", - "MONITOR_IMUX25_1", - "MONITOR_IMUX25_2", - "MONITOR_IMUX25_3", - "MONITOR_IMUX25_4", - "MONITOR_IMUX25_5", - "MONITOR_IMUX25_6", - "MONITOR_IMUX25_7", - "MONITOR_IMUX25_8", - "MONITOR_IMUX25_9", - "MONITOR_IMUX26_0", - "MONITOR_IMUX26_1", - "MONITOR_IMUX26_2", - "MONITOR_IMUX26_3", - "MONITOR_IMUX26_4", - "MONITOR_IMUX26_5", - "MONITOR_IMUX26_6", - "MONITOR_IMUX26_7", - "MONITOR_IMUX26_8", - "MONITOR_IMUX26_9", - "MONITOR_IMUX27_0", - "MONITOR_IMUX27_1", - "MONITOR_IMUX27_2", - "MONITOR_IMUX27_3", - "MONITOR_IMUX27_4", - "MONITOR_IMUX27_5", - "MONITOR_IMUX27_6", - "MONITOR_IMUX27_7", - "MONITOR_IMUX27_8", - "MONITOR_IMUX27_9", - "MONITOR_IMUX28_0", - "MONITOR_IMUX28_1", - "MONITOR_IMUX28_2", - "MONITOR_IMUX28_3", - "MONITOR_IMUX28_4", - "MONITOR_IMUX28_5", - "MONITOR_IMUX28_6", - "MONITOR_IMUX28_7", - "MONITOR_IMUX28_8", - "MONITOR_IMUX28_9", - "MONITOR_IMUX29_0", - "MONITOR_IMUX29_1", - "MONITOR_IMUX29_2", - "MONITOR_IMUX29_3", - "MONITOR_IMUX29_4", - "MONITOR_IMUX29_5", - "MONITOR_IMUX29_6", - "MONITOR_IMUX29_7", - "MONITOR_IMUX29_8", - "MONITOR_IMUX29_9", - "MONITOR_IMUX2_0", - "MONITOR_IMUX2_1", - "MONITOR_IMUX2_2", - "MONITOR_IMUX2_3", - "MONITOR_IMUX2_4", - "MONITOR_IMUX2_5", - "MONITOR_IMUX2_6", - "MONITOR_IMUX2_7", - "MONITOR_IMUX2_8", - "MONITOR_IMUX2_9", - "MONITOR_IMUX30_0", - "MONITOR_IMUX30_1", - "MONITOR_IMUX30_2", - "MONITOR_IMUX30_3", - "MONITOR_IMUX30_4", - "MONITOR_IMUX30_5", - "MONITOR_IMUX30_6", - "MONITOR_IMUX30_7", - "MONITOR_IMUX30_8", - "MONITOR_IMUX30_9", - "MONITOR_IMUX31_0", - "MONITOR_IMUX31_1", - "MONITOR_IMUX31_2", - "MONITOR_IMUX31_3", - "MONITOR_IMUX31_4", - "MONITOR_IMUX31_5", - "MONITOR_IMUX31_6", - "MONITOR_IMUX31_7", - "MONITOR_IMUX31_8", - "MONITOR_IMUX31_9", - "MONITOR_IMUX32_0", - "MONITOR_IMUX32_1", - "MONITOR_IMUX32_2", - "MONITOR_IMUX32_3", - "MONITOR_IMUX32_4", - "MONITOR_IMUX32_5", - "MONITOR_IMUX32_6", - "MONITOR_IMUX32_7", - "MONITOR_IMUX32_8", - "MONITOR_IMUX32_9", - "MONITOR_IMUX33_0", - "MONITOR_IMUX33_1", - "MONITOR_IMUX33_2", - "MONITOR_IMUX33_3", - "MONITOR_IMUX33_4", - "MONITOR_IMUX33_5", - "MONITOR_IMUX33_6", - "MONITOR_IMUX33_7", - "MONITOR_IMUX33_8", - "MONITOR_IMUX33_9", - "MONITOR_IMUX34_0", - "MONITOR_IMUX34_1", - "MONITOR_IMUX34_2", - "MONITOR_IMUX34_3", - "MONITOR_IMUX34_4", - "MONITOR_IMUX34_5", - "MONITOR_IMUX34_6", - "MONITOR_IMUX34_7", - "MONITOR_IMUX34_8", - "MONITOR_IMUX34_9", - "MONITOR_IMUX35_0", - "MONITOR_IMUX35_1", - "MONITOR_IMUX35_2", - "MONITOR_IMUX35_3", - "MONITOR_IMUX35_4", - "MONITOR_IMUX35_5", - "MONITOR_IMUX35_6", - "MONITOR_IMUX35_7", - "MONITOR_IMUX35_8", - "MONITOR_IMUX35_9", - "MONITOR_IMUX36_0", - "MONITOR_IMUX36_1", - "MONITOR_IMUX36_2", - "MONITOR_IMUX36_3", - "MONITOR_IMUX36_4", - "MONITOR_IMUX36_5", - "MONITOR_IMUX36_6", - "MONITOR_IMUX36_7", - "MONITOR_IMUX36_8", - "MONITOR_IMUX36_9", - "MONITOR_IMUX37_0", - "MONITOR_IMUX37_1", - "MONITOR_IMUX37_2", - "MONITOR_IMUX37_3", - "MONITOR_IMUX37_4", - "MONITOR_IMUX37_5", - "MONITOR_IMUX37_6", - "MONITOR_IMUX37_7", - "MONITOR_IMUX37_8", - "MONITOR_IMUX37_9", - "MONITOR_IMUX38_0", - "MONITOR_IMUX38_1", - "MONITOR_IMUX38_2", - "MONITOR_IMUX38_3", - "MONITOR_IMUX38_4", - "MONITOR_IMUX38_5", - "MONITOR_IMUX38_6", - "MONITOR_IMUX38_7", - "MONITOR_IMUX38_8", - "MONITOR_IMUX38_9", - "MONITOR_IMUX39_0", - "MONITOR_IMUX39_1", - "MONITOR_IMUX39_2", - "MONITOR_IMUX39_3", - "MONITOR_IMUX39_4", - "MONITOR_IMUX39_5", - "MONITOR_IMUX39_6", - "MONITOR_IMUX39_7", - "MONITOR_IMUX39_8", - "MONITOR_IMUX39_9", - "MONITOR_IMUX3_0", - "MONITOR_IMUX3_1", - "MONITOR_IMUX3_2", - "MONITOR_IMUX3_3", - "MONITOR_IMUX3_4", - "MONITOR_IMUX3_5", - "MONITOR_IMUX3_6", - "MONITOR_IMUX3_7", - "MONITOR_IMUX3_8", - "MONITOR_IMUX3_9", - "MONITOR_IMUX40_0", - "MONITOR_IMUX40_1", - "MONITOR_IMUX40_2", - "MONITOR_IMUX40_3", - "MONITOR_IMUX40_4", - "MONITOR_IMUX40_5", - "MONITOR_IMUX40_6", - "MONITOR_IMUX40_7", - "MONITOR_IMUX40_8", - "MONITOR_IMUX40_9", - "MONITOR_IMUX41_0", - "MONITOR_IMUX41_1", - "MONITOR_IMUX41_2", - "MONITOR_IMUX41_3", - "MONITOR_IMUX41_4", - "MONITOR_IMUX41_5", - "MONITOR_IMUX41_6", - "MONITOR_IMUX41_7", - "MONITOR_IMUX41_8", - "MONITOR_IMUX41_9", - "MONITOR_IMUX42_0", - "MONITOR_IMUX42_1", - "MONITOR_IMUX42_2", - "MONITOR_IMUX42_3", - "MONITOR_IMUX42_4", - "MONITOR_IMUX42_5", - "MONITOR_IMUX42_6", - "MONITOR_IMUX42_7", - "MONITOR_IMUX42_8", - "MONITOR_IMUX42_9", - "MONITOR_IMUX43_0", - "MONITOR_IMUX43_1", - "MONITOR_IMUX43_2", - "MONITOR_IMUX43_3", - "MONITOR_IMUX43_4", - "MONITOR_IMUX43_5", - "MONITOR_IMUX43_6", - "MONITOR_IMUX43_7", - "MONITOR_IMUX43_8", - "MONITOR_IMUX43_9", - "MONITOR_IMUX44_0", - "MONITOR_IMUX44_1", - "MONITOR_IMUX44_2", - "MONITOR_IMUX44_3", - "MONITOR_IMUX44_4", - "MONITOR_IMUX44_5", - "MONITOR_IMUX44_6", - "MONITOR_IMUX44_7", - "MONITOR_IMUX44_8", - "MONITOR_IMUX44_9", - "MONITOR_IMUX45_0", - "MONITOR_IMUX45_1", - "MONITOR_IMUX45_2", - "MONITOR_IMUX45_3", - "MONITOR_IMUX45_4", - "MONITOR_IMUX45_5", - "MONITOR_IMUX45_6", - "MONITOR_IMUX45_7", - "MONITOR_IMUX45_8", - "MONITOR_IMUX45_9", - "MONITOR_IMUX46_0", - "MONITOR_IMUX46_1", - "MONITOR_IMUX46_2", - "MONITOR_IMUX46_3", - "MONITOR_IMUX46_4", - "MONITOR_IMUX46_5", - "MONITOR_IMUX46_6", - "MONITOR_IMUX46_7", - "MONITOR_IMUX46_8", - "MONITOR_IMUX46_9", - "MONITOR_IMUX47_0", - "MONITOR_IMUX47_1", - "MONITOR_IMUX47_2", - "MONITOR_IMUX47_3", - "MONITOR_IMUX47_4", - "MONITOR_IMUX47_5", - "MONITOR_IMUX47_6", - "MONITOR_IMUX47_7", - "MONITOR_IMUX47_8", - "MONITOR_IMUX47_9", - "MONITOR_IMUX4_0", - "MONITOR_IMUX4_1", - "MONITOR_IMUX4_2", - "MONITOR_IMUX4_3", - "MONITOR_IMUX4_4", - "MONITOR_IMUX4_5", - "MONITOR_IMUX4_6", - "MONITOR_IMUX4_7", - "MONITOR_IMUX4_8", - "MONITOR_IMUX4_9", - "MONITOR_IMUX5_0", - "MONITOR_IMUX5_1", - "MONITOR_IMUX5_2", - "MONITOR_IMUX5_3", - "MONITOR_IMUX5_4", - "MONITOR_IMUX5_5", - "MONITOR_IMUX5_6", - "MONITOR_IMUX5_7", - "MONITOR_IMUX5_8", - "MONITOR_IMUX5_9", - "MONITOR_IMUX6_0", - "MONITOR_IMUX6_1", - "MONITOR_IMUX6_2", - "MONITOR_IMUX6_3", - "MONITOR_IMUX6_4", - "MONITOR_IMUX6_5", - "MONITOR_IMUX6_6", - "MONITOR_IMUX6_7", - "MONITOR_IMUX6_8", - "MONITOR_IMUX6_9", - "MONITOR_IMUX7_0", - "MONITOR_IMUX7_1", - "MONITOR_IMUX7_2", - "MONITOR_IMUX7_3", - "MONITOR_IMUX7_4", - "MONITOR_IMUX7_5", - "MONITOR_IMUX7_6", - "MONITOR_IMUX7_7", - "MONITOR_IMUX7_8", - "MONITOR_IMUX7_9", - "MONITOR_IMUX8_0", - "MONITOR_IMUX8_1", - "MONITOR_IMUX8_2", - "MONITOR_IMUX8_3", - "MONITOR_IMUX8_4", - "MONITOR_IMUX8_5", - "MONITOR_IMUX8_6", - "MONITOR_IMUX8_7", - "MONITOR_IMUX8_8", - "MONITOR_IMUX8_9", - "MONITOR_IMUX9_0", - "MONITOR_IMUX9_1", - "MONITOR_IMUX9_2", - "MONITOR_IMUX9_3", - "MONITOR_IMUX9_4", - "MONITOR_IMUX9_5", - "MONITOR_IMUX9_6", - "MONITOR_IMUX9_7", - "MONITOR_IMUX9_8", - "MONITOR_IMUX9_9", - "MONITOR_LH10_0", - "MONITOR_LH10_1", - "MONITOR_LH10_2", - "MONITOR_LH10_3", - "MONITOR_LH10_4", - "MONITOR_LH10_5", - "MONITOR_LH10_6", - "MONITOR_LH10_7", - "MONITOR_LH10_8", - "MONITOR_LH10_9", - "MONITOR_LH11_0", - "MONITOR_LH11_1", - "MONITOR_LH11_2", - "MONITOR_LH11_3", - "MONITOR_LH11_4", - "MONITOR_LH11_5", - "MONITOR_LH11_6", - "MONITOR_LH11_7", - "MONITOR_LH11_8", - "MONITOR_LH11_9", - "MONITOR_LH12_0", - "MONITOR_LH12_1", - "MONITOR_LH12_2", - "MONITOR_LH12_3", - "MONITOR_LH12_4", - "MONITOR_LH12_5", - "MONITOR_LH12_6", - "MONITOR_LH12_7", - "MONITOR_LH12_8", - "MONITOR_LH12_9", - "MONITOR_LH1_0", - "MONITOR_LH1_1", - "MONITOR_LH1_2", - "MONITOR_LH1_3", - "MONITOR_LH1_4", - "MONITOR_LH1_5", - "MONITOR_LH1_6", - "MONITOR_LH1_7", - "MONITOR_LH1_8", - "MONITOR_LH1_9", - "MONITOR_LH2_0", - "MONITOR_LH2_1", - "MONITOR_LH2_2", - "MONITOR_LH2_3", - "MONITOR_LH2_4", - "MONITOR_LH2_5", - "MONITOR_LH2_6", - "MONITOR_LH2_7", - "MONITOR_LH2_8", - "MONITOR_LH2_9", - "MONITOR_LH3_0", - "MONITOR_LH3_1", - "MONITOR_LH3_2", - "MONITOR_LH3_3", - "MONITOR_LH3_4", - "MONITOR_LH3_5", - "MONITOR_LH3_6", - "MONITOR_LH3_7", - "MONITOR_LH3_8", - "MONITOR_LH3_9", - "MONITOR_LH4_0", - "MONITOR_LH4_1", - "MONITOR_LH4_2", - "MONITOR_LH4_3", - "MONITOR_LH4_4", - "MONITOR_LH4_5", - "MONITOR_LH4_6", - "MONITOR_LH4_7", - "MONITOR_LH4_8", - "MONITOR_LH4_9", - "MONITOR_LH5_0", - "MONITOR_LH5_1", - "MONITOR_LH5_2", - "MONITOR_LH5_3", - "MONITOR_LH5_4", - "MONITOR_LH5_5", - "MONITOR_LH5_6", - "MONITOR_LH5_7", - "MONITOR_LH5_8", - "MONITOR_LH5_9", - "MONITOR_LH6_0", - "MONITOR_LH6_1", - "MONITOR_LH6_2", - "MONITOR_LH6_3", - "MONITOR_LH6_4", - "MONITOR_LH6_5", - "MONITOR_LH6_6", - "MONITOR_LH6_7", - "MONITOR_LH6_8", - "MONITOR_LH6_9", - "MONITOR_LH7_0", - "MONITOR_LH7_1", - "MONITOR_LH7_2", - "MONITOR_LH7_3", - "MONITOR_LH7_4", - "MONITOR_LH7_5", - "MONITOR_LH7_6", - "MONITOR_LH7_7", - "MONITOR_LH7_8", - "MONITOR_LH7_9", - "MONITOR_LH8_0", - "MONITOR_LH8_1", - "MONITOR_LH8_2", - "MONITOR_LH8_3", - "MONITOR_LH8_4", - "MONITOR_LH8_5", - "MONITOR_LH8_6", - "MONITOR_LH8_7", - "MONITOR_LH8_8", - "MONITOR_LH8_9", - "MONITOR_LH9_0", - "MONITOR_LH9_1", - "MONITOR_LH9_2", - "MONITOR_LH9_3", - "MONITOR_LH9_4", - "MONITOR_LH9_5", - "MONITOR_LH9_6", - "MONITOR_LH9_7", - "MONITOR_LH9_8", - "MONITOR_LH9_9", - "MONITOR_LOGIC_OUTS_B0_0", - "MONITOR_LOGIC_OUTS_B0_1", - "MONITOR_LOGIC_OUTS_B0_2", - "MONITOR_LOGIC_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B0_4", - "MONITOR_LOGIC_OUTS_B0_5", - "MONITOR_LOGIC_OUTS_B0_6", - "MONITOR_LOGIC_OUTS_B0_7", - "MONITOR_LOGIC_OUTS_B0_8", - "MONITOR_LOGIC_OUTS_B0_9", - "MONITOR_LOGIC_OUTS_B10_0", - "MONITOR_LOGIC_OUTS_B10_1", - "MONITOR_LOGIC_OUTS_B10_2", - "MONITOR_LOGIC_OUTS_B10_3", - "MONITOR_LOGIC_OUTS_B10_4", - "MONITOR_LOGIC_OUTS_B10_5", - "MONITOR_LOGIC_OUTS_B10_6", - "MONITOR_LOGIC_OUTS_B10_7", - "MONITOR_LOGIC_OUTS_B10_8", - "MONITOR_LOGIC_OUTS_B10_9", - "MONITOR_LOGIC_OUTS_B11_0", - "MONITOR_LOGIC_OUTS_B11_1", - "MONITOR_LOGIC_OUTS_B11_2", - "MONITOR_LOGIC_OUTS_B11_3", - "MONITOR_LOGIC_OUTS_B11_4", - "MONITOR_LOGIC_OUTS_B11_5", - "MONITOR_LOGIC_OUTS_B11_6", - "MONITOR_LOGIC_OUTS_B11_7", - "MONITOR_LOGIC_OUTS_B11_8", - "MONITOR_LOGIC_OUTS_B11_9", - "MONITOR_LOGIC_OUTS_B12_0", - "MONITOR_LOGIC_OUTS_B12_1", - "MONITOR_LOGIC_OUTS_B12_2", - "MONITOR_LOGIC_OUTS_B12_3", - "MONITOR_LOGIC_OUTS_B12_4", - "MONITOR_LOGIC_OUTS_B12_5", - "MONITOR_LOGIC_OUTS_B12_6", - "MONITOR_LOGIC_OUTS_B12_7", - "MONITOR_LOGIC_OUTS_B12_8", - "MONITOR_LOGIC_OUTS_B12_9", - "MONITOR_LOGIC_OUTS_B13_0", - "MONITOR_LOGIC_OUTS_B13_1", - "MONITOR_LOGIC_OUTS_B13_2", - "MONITOR_LOGIC_OUTS_B13_3", - "MONITOR_LOGIC_OUTS_B13_4", - "MONITOR_LOGIC_OUTS_B13_5", - "MONITOR_LOGIC_OUTS_B13_6", - "MONITOR_LOGIC_OUTS_B13_7", - "MONITOR_LOGIC_OUTS_B13_8", - "MONITOR_LOGIC_OUTS_B13_9", - "MONITOR_LOGIC_OUTS_B14_0", - "MONITOR_LOGIC_OUTS_B14_1", - "MONITOR_LOGIC_OUTS_B14_2", - "MONITOR_LOGIC_OUTS_B14_3", - "MONITOR_LOGIC_OUTS_B14_4", - "MONITOR_LOGIC_OUTS_B14_5", - "MONITOR_LOGIC_OUTS_B14_6", - "MONITOR_LOGIC_OUTS_B14_7", - "MONITOR_LOGIC_OUTS_B14_8", - "MONITOR_LOGIC_OUTS_B14_9", - "MONITOR_LOGIC_OUTS_B15_0", - "MONITOR_LOGIC_OUTS_B15_1", - "MONITOR_LOGIC_OUTS_B15_2", - "MONITOR_LOGIC_OUTS_B15_3", - "MONITOR_LOGIC_OUTS_B15_4", - "MONITOR_LOGIC_OUTS_B15_5", - "MONITOR_LOGIC_OUTS_B15_6", - "MONITOR_LOGIC_OUTS_B15_7", - "MONITOR_LOGIC_OUTS_B15_8", - "MONITOR_LOGIC_OUTS_B15_9", - "MONITOR_LOGIC_OUTS_B16_0", - "MONITOR_LOGIC_OUTS_B16_1", - "MONITOR_LOGIC_OUTS_B16_2", - "MONITOR_LOGIC_OUTS_B16_3", - "MONITOR_LOGIC_OUTS_B16_4", - "MONITOR_LOGIC_OUTS_B16_5", - "MONITOR_LOGIC_OUTS_B16_6", - "MONITOR_LOGIC_OUTS_B16_7", - "MONITOR_LOGIC_OUTS_B16_8", - "MONITOR_LOGIC_OUTS_B16_9", - "MONITOR_LOGIC_OUTS_B17_0", - "MONITOR_LOGIC_OUTS_B17_1", - "MONITOR_LOGIC_OUTS_B17_2", - "MONITOR_LOGIC_OUTS_B17_3", - "MONITOR_LOGIC_OUTS_B17_4", - "MONITOR_LOGIC_OUTS_B17_5", - "MONITOR_LOGIC_OUTS_B17_6", - "MONITOR_LOGIC_OUTS_B17_7", - "MONITOR_LOGIC_OUTS_B17_8", - "MONITOR_LOGIC_OUTS_B17_9", - "MONITOR_LOGIC_OUTS_B18_0", - "MONITOR_LOGIC_OUTS_B18_1", - "MONITOR_LOGIC_OUTS_B18_2", - "MONITOR_LOGIC_OUTS_B18_3", - "MONITOR_LOGIC_OUTS_B18_4", - "MONITOR_LOGIC_OUTS_B18_5", - "MONITOR_LOGIC_OUTS_B18_6", - "MONITOR_LOGIC_OUTS_B18_7", - "MONITOR_LOGIC_OUTS_B18_8", - "MONITOR_LOGIC_OUTS_B18_9", - "MONITOR_LOGIC_OUTS_B19_0", - "MONITOR_LOGIC_OUTS_B19_1", - "MONITOR_LOGIC_OUTS_B19_2", - "MONITOR_LOGIC_OUTS_B19_3", - "MONITOR_LOGIC_OUTS_B19_4", - "MONITOR_LOGIC_OUTS_B19_5", - "MONITOR_LOGIC_OUTS_B19_6", - "MONITOR_LOGIC_OUTS_B19_7", - "MONITOR_LOGIC_OUTS_B19_8", - "MONITOR_LOGIC_OUTS_B19_9", - "MONITOR_LOGIC_OUTS_B1_0", - "MONITOR_LOGIC_OUTS_B1_1", - "MONITOR_LOGIC_OUTS_B1_2", - "MONITOR_LOGIC_OUTS_B1_3", - "MONITOR_LOGIC_OUTS_B1_4", - "MONITOR_LOGIC_OUTS_B1_5", - "MONITOR_LOGIC_OUTS_B1_6", - "MONITOR_LOGIC_OUTS_B1_7", - "MONITOR_LOGIC_OUTS_B1_8", - "MONITOR_LOGIC_OUTS_B1_9", - "MONITOR_LOGIC_OUTS_B20_0", - "MONITOR_LOGIC_OUTS_B20_1", - "MONITOR_LOGIC_OUTS_B20_2", - "MONITOR_LOGIC_OUTS_B20_3", - "MONITOR_LOGIC_OUTS_B20_4", - "MONITOR_LOGIC_OUTS_B20_5", - "MONITOR_LOGIC_OUTS_B20_6", - "MONITOR_LOGIC_OUTS_B20_7", - "MONITOR_LOGIC_OUTS_B20_8", - "MONITOR_LOGIC_OUTS_B20_9", - "MONITOR_LOGIC_OUTS_B21_0", - "MONITOR_LOGIC_OUTS_B21_1", - "MONITOR_LOGIC_OUTS_B21_2", - "MONITOR_LOGIC_OUTS_B21_3", - "MONITOR_LOGIC_OUTS_B21_4", - "MONITOR_LOGIC_OUTS_B21_5", - "MONITOR_LOGIC_OUTS_B21_6", - "MONITOR_LOGIC_OUTS_B21_7", - "MONITOR_LOGIC_OUTS_B21_8", - "MONITOR_LOGIC_OUTS_B21_9", - "MONITOR_LOGIC_OUTS_B22_0", - "MONITOR_LOGIC_OUTS_B22_1", - "MONITOR_LOGIC_OUTS_B22_2", - "MONITOR_LOGIC_OUTS_B22_3", - "MONITOR_LOGIC_OUTS_B22_4", - "MONITOR_LOGIC_OUTS_B22_5", - "MONITOR_LOGIC_OUTS_B22_6", - "MONITOR_LOGIC_OUTS_B22_7", - "MONITOR_LOGIC_OUTS_B22_8", - "MONITOR_LOGIC_OUTS_B22_9", - "MONITOR_LOGIC_OUTS_B23_0", - "MONITOR_LOGIC_OUTS_B23_1", - "MONITOR_LOGIC_OUTS_B23_2", - "MONITOR_LOGIC_OUTS_B23_3", - "MONITOR_LOGIC_OUTS_B23_4", - "MONITOR_LOGIC_OUTS_B23_5", - "MONITOR_LOGIC_OUTS_B23_6", - "MONITOR_LOGIC_OUTS_B23_7", - "MONITOR_LOGIC_OUTS_B23_8", - "MONITOR_LOGIC_OUTS_B23_9", - "MONITOR_LOGIC_OUTS_B2_0", - "MONITOR_LOGIC_OUTS_B2_1", - "MONITOR_LOGIC_OUTS_B2_2", - "MONITOR_LOGIC_OUTS_B2_3", - "MONITOR_LOGIC_OUTS_B2_4", - "MONITOR_LOGIC_OUTS_B2_5", - "MONITOR_LOGIC_OUTS_B2_6", - "MONITOR_LOGIC_OUTS_B2_7", - "MONITOR_LOGIC_OUTS_B2_8", - "MONITOR_LOGIC_OUTS_B2_9", - "MONITOR_LOGIC_OUTS_B3_0", - "MONITOR_LOGIC_OUTS_B3_1", - "MONITOR_LOGIC_OUTS_B3_2", - "MONITOR_LOGIC_OUTS_B3_3", - "MONITOR_LOGIC_OUTS_B3_4", - "MONITOR_LOGIC_OUTS_B3_5", - "MONITOR_LOGIC_OUTS_B3_6", - "MONITOR_LOGIC_OUTS_B3_7", - "MONITOR_LOGIC_OUTS_B3_8", - "MONITOR_LOGIC_OUTS_B3_9", - "MONITOR_LOGIC_OUTS_B4_0", - "MONITOR_LOGIC_OUTS_B4_1", - "MONITOR_LOGIC_OUTS_B4_2", - "MONITOR_LOGIC_OUTS_B4_3", - "MONITOR_LOGIC_OUTS_B4_4", - "MONITOR_LOGIC_OUTS_B4_5", - "MONITOR_LOGIC_OUTS_B4_6", - "MONITOR_LOGIC_OUTS_B4_7", - "MONITOR_LOGIC_OUTS_B4_8", - "MONITOR_LOGIC_OUTS_B4_9", - "MONITOR_LOGIC_OUTS_B5_0", - "MONITOR_LOGIC_OUTS_B5_1", - "MONITOR_LOGIC_OUTS_B5_2", - "MONITOR_LOGIC_OUTS_B5_3", - "MONITOR_LOGIC_OUTS_B5_4", - "MONITOR_LOGIC_OUTS_B5_5", - "MONITOR_LOGIC_OUTS_B5_6", - "MONITOR_LOGIC_OUTS_B5_7", - "MONITOR_LOGIC_OUTS_B5_8", - "MONITOR_LOGIC_OUTS_B5_9", - "MONITOR_LOGIC_OUTS_B6_0", - "MONITOR_LOGIC_OUTS_B6_1", - "MONITOR_LOGIC_OUTS_B6_2", - "MONITOR_LOGIC_OUTS_B6_3", - "MONITOR_LOGIC_OUTS_B6_4", - "MONITOR_LOGIC_OUTS_B6_5", - "MONITOR_LOGIC_OUTS_B6_6", - "MONITOR_LOGIC_OUTS_B6_7", - "MONITOR_LOGIC_OUTS_B6_8", - "MONITOR_LOGIC_OUTS_B6_9", - "MONITOR_LOGIC_OUTS_B7_0", - "MONITOR_LOGIC_OUTS_B7_1", - "MONITOR_LOGIC_OUTS_B7_2", - "MONITOR_LOGIC_OUTS_B7_3", - "MONITOR_LOGIC_OUTS_B7_4", - "MONITOR_LOGIC_OUTS_B7_5", - "MONITOR_LOGIC_OUTS_B7_6", - "MONITOR_LOGIC_OUTS_B7_7", - "MONITOR_LOGIC_OUTS_B7_8", - "MONITOR_LOGIC_OUTS_B7_9", - "MONITOR_LOGIC_OUTS_B8_0", - "MONITOR_LOGIC_OUTS_B8_1", - "MONITOR_LOGIC_OUTS_B8_2", - "MONITOR_LOGIC_OUTS_B8_3", - "MONITOR_LOGIC_OUTS_B8_4", - "MONITOR_LOGIC_OUTS_B8_5", - "MONITOR_LOGIC_OUTS_B8_6", - "MONITOR_LOGIC_OUTS_B8_7", - "MONITOR_LOGIC_OUTS_B8_8", - "MONITOR_LOGIC_OUTS_B8_9", - "MONITOR_LOGIC_OUTS_B9_0", - "MONITOR_LOGIC_OUTS_B9_1", - "MONITOR_LOGIC_OUTS_B9_2", - "MONITOR_LOGIC_OUTS_B9_3", - "MONITOR_LOGIC_OUTS_B9_4", - "MONITOR_LOGIC_OUTS_B9_5", - "MONITOR_LOGIC_OUTS_B9_6", - "MONITOR_LOGIC_OUTS_B9_7", - "MONITOR_LOGIC_OUTS_B9_8", - "MONITOR_LOGIC_OUTS_B9_9", - "MONITOR_NE2A0_0", - "MONITOR_NE2A0_1", - "MONITOR_NE2A0_2", - "MONITOR_NE2A0_3", - "MONITOR_NE2A0_4", - "MONITOR_NE2A0_5", - "MONITOR_NE2A0_6", - "MONITOR_NE2A0_7", - "MONITOR_NE2A0_8", - "MONITOR_NE2A0_9", - "MONITOR_NE2A1_0", - "MONITOR_NE2A1_1", - "MONITOR_NE2A1_2", - "MONITOR_NE2A1_3", - "MONITOR_NE2A1_4", - "MONITOR_NE2A1_5", - "MONITOR_NE2A1_6", - "MONITOR_NE2A1_7", - "MONITOR_NE2A1_8", - "MONITOR_NE2A1_9", - "MONITOR_NE2A2_0", - "MONITOR_NE2A2_1", - "MONITOR_NE2A2_2", - "MONITOR_NE2A2_3", - "MONITOR_NE2A2_4", - "MONITOR_NE2A2_5", - "MONITOR_NE2A2_6", - "MONITOR_NE2A2_7", - "MONITOR_NE2A2_8", - "MONITOR_NE2A2_9", - "MONITOR_NE2A3_0", - "MONITOR_NE2A3_1", - "MONITOR_NE2A3_2", - "MONITOR_NE2A3_3", - "MONITOR_NE2A3_4", - "MONITOR_NE2A3_5", - "MONITOR_NE2A3_6", - "MONITOR_NE2A3_7", - "MONITOR_NE2A3_8", - "MONITOR_NE2A3_9", - "MONITOR_NE4BEG0_0", - "MONITOR_NE4BEG0_1", - "MONITOR_NE4BEG0_2", - "MONITOR_NE4BEG0_3", - "MONITOR_NE4BEG0_4", - "MONITOR_NE4BEG0_5", - "MONITOR_NE4BEG0_6", - "MONITOR_NE4BEG0_7", - "MONITOR_NE4BEG0_8", - "MONITOR_NE4BEG0_9", - "MONITOR_NE4BEG1_0", - "MONITOR_NE4BEG1_1", - "MONITOR_NE4BEG1_2", - "MONITOR_NE4BEG1_3", - "MONITOR_NE4BEG1_4", - "MONITOR_NE4BEG1_5", - "MONITOR_NE4BEG1_6", - "MONITOR_NE4BEG1_7", - "MONITOR_NE4BEG1_8", - "MONITOR_NE4BEG1_9", - "MONITOR_NE4BEG2_0", - "MONITOR_NE4BEG2_1", - "MONITOR_NE4BEG2_2", - "MONITOR_NE4BEG2_3", - "MONITOR_NE4BEG2_4", - "MONITOR_NE4BEG2_5", - "MONITOR_NE4BEG2_6", - "MONITOR_NE4BEG2_7", - "MONITOR_NE4BEG2_8", - "MONITOR_NE4BEG2_9", - "MONITOR_NE4BEG3_0", - "MONITOR_NE4BEG3_1", - "MONITOR_NE4BEG3_2", - "MONITOR_NE4BEG3_3", - "MONITOR_NE4BEG3_4", - "MONITOR_NE4BEG3_5", - "MONITOR_NE4BEG3_6", - "MONITOR_NE4BEG3_7", - "MONITOR_NE4BEG3_8", - "MONITOR_NE4BEG3_9", - "MONITOR_NE4C0_0", - "MONITOR_NE4C0_1", - "MONITOR_NE4C0_2", - "MONITOR_NE4C0_3", - "MONITOR_NE4C0_4", - "MONITOR_NE4C0_5", - "MONITOR_NE4C0_6", - "MONITOR_NE4C0_7", - "MONITOR_NE4C0_8", - "MONITOR_NE4C0_9", - "MONITOR_NE4C1_0", - "MONITOR_NE4C1_1", - "MONITOR_NE4C1_2", - "MONITOR_NE4C1_3", - "MONITOR_NE4C1_4", - "MONITOR_NE4C1_5", - "MONITOR_NE4C1_6", - "MONITOR_NE4C1_7", - "MONITOR_NE4C1_8", - "MONITOR_NE4C1_9", - "MONITOR_NE4C2_0", - "MONITOR_NE4C2_1", - "MONITOR_NE4C2_2", - "MONITOR_NE4C2_3", - "MONITOR_NE4C2_4", - "MONITOR_NE4C2_5", - "MONITOR_NE4C2_6", - "MONITOR_NE4C2_7", - "MONITOR_NE4C2_8", - "MONITOR_NE4C2_9", - "MONITOR_NE4C3_0", - "MONITOR_NE4C3_1", - "MONITOR_NE4C3_2", - "MONITOR_NE4C3_3", - "MONITOR_NE4C3_4", - "MONITOR_NE4C3_5", - "MONITOR_NE4C3_6", - "MONITOR_NE4C3_7", - "MONITOR_NE4C3_8", - "MONITOR_NE4C3_9", - "MONITOR_NW2A0_0", - "MONITOR_NW2A0_1", - "MONITOR_NW2A0_2", - "MONITOR_NW2A0_3", - "MONITOR_NW2A0_4", - "MONITOR_NW2A0_5", - "MONITOR_NW2A0_6", - "MONITOR_NW2A0_7", - "MONITOR_NW2A0_8", - "MONITOR_NW2A0_9", - "MONITOR_NW2A1_0", - "MONITOR_NW2A1_1", - "MONITOR_NW2A1_2", - "MONITOR_NW2A1_3", - "MONITOR_NW2A1_4", - "MONITOR_NW2A1_5", - "MONITOR_NW2A1_6", - "MONITOR_NW2A1_7", - "MONITOR_NW2A1_8", - "MONITOR_NW2A1_9", - "MONITOR_NW2A2_0", - "MONITOR_NW2A2_1", - "MONITOR_NW2A2_2", - "MONITOR_NW2A2_3", - "MONITOR_NW2A2_4", - "MONITOR_NW2A2_5", - "MONITOR_NW2A2_6", - "MONITOR_NW2A2_7", - "MONITOR_NW2A2_8", - "MONITOR_NW2A2_9", - "MONITOR_NW2A3_0", - "MONITOR_NW2A3_1", - "MONITOR_NW2A3_2", - "MONITOR_NW2A3_3", - "MONITOR_NW2A3_4", - "MONITOR_NW2A3_5", - "MONITOR_NW2A3_6", - "MONITOR_NW2A3_7", - "MONITOR_NW2A3_8", - "MONITOR_NW2A3_9", - "MONITOR_NW4A0_0", - "MONITOR_NW4A0_1", - "MONITOR_NW4A0_2", - "MONITOR_NW4A0_3", - "MONITOR_NW4A0_4", - "MONITOR_NW4A0_5", - "MONITOR_NW4A0_6", - "MONITOR_NW4A0_7", - "MONITOR_NW4A0_8", - "MONITOR_NW4A0_9", - "MONITOR_NW4A1_0", - "MONITOR_NW4A1_1", - "MONITOR_NW4A1_2", - "MONITOR_NW4A1_3", - "MONITOR_NW4A1_4", - "MONITOR_NW4A1_5", - "MONITOR_NW4A1_6", - "MONITOR_NW4A1_7", - "MONITOR_NW4A1_8", - "MONITOR_NW4A1_9", - "MONITOR_NW4A2_0", - "MONITOR_NW4A2_1", - "MONITOR_NW4A2_2", - "MONITOR_NW4A2_3", - "MONITOR_NW4A2_4", - "MONITOR_NW4A2_5", - "MONITOR_NW4A2_6", - "MONITOR_NW4A2_7", - "MONITOR_NW4A2_8", - "MONITOR_NW4A2_9", - "MONITOR_NW4A3_0", - "MONITOR_NW4A3_1", - "MONITOR_NW4A3_2", - "MONITOR_NW4A3_3", - "MONITOR_NW4A3_4", - "MONITOR_NW4A3_5", - "MONITOR_NW4A3_6", - "MONITOR_NW4A3_7", - "MONITOR_NW4A3_8", - "MONITOR_NW4A3_9", - "MONITOR_NW4END0_0", - "MONITOR_NW4END0_1", - "MONITOR_NW4END0_2", - "MONITOR_NW4END0_3", - "MONITOR_NW4END0_4", - "MONITOR_NW4END0_5", - "MONITOR_NW4END0_6", - "MONITOR_NW4END0_7", - "MONITOR_NW4END0_8", - "MONITOR_NW4END0_9", - "MONITOR_NW4END1_0", - "MONITOR_NW4END1_1", - "MONITOR_NW4END1_2", - "MONITOR_NW4END1_3", - "MONITOR_NW4END1_4", - "MONITOR_NW4END1_5", - "MONITOR_NW4END1_6", - "MONITOR_NW4END1_7", - "MONITOR_NW4END1_8", - "MONITOR_NW4END1_9", - "MONITOR_NW4END2_0", - "MONITOR_NW4END2_1", - "MONITOR_NW4END2_2", - "MONITOR_NW4END2_3", - "MONITOR_NW4END2_4", - "MONITOR_NW4END2_5", - "MONITOR_NW4END2_6", - "MONITOR_NW4END2_7", - "MONITOR_NW4END2_8", - "MONITOR_NW4END2_9", - "MONITOR_NW4END3_0", - "MONITOR_NW4END3_1", - "MONITOR_NW4END3_2", - "MONITOR_NW4END3_3", - "MONITOR_NW4END3_4", - "MONITOR_NW4END3_5", - "MONITOR_NW4END3_6", - "MONITOR_NW4END3_7", - "MONITOR_NW4END3_8", - "MONITOR_NW4END3_9", - "MONITOR_SE2A0_0", - "MONITOR_SE2A0_1", - "MONITOR_SE2A0_2", - "MONITOR_SE2A0_3", - "MONITOR_SE2A0_4", - "MONITOR_SE2A0_5", - "MONITOR_SE2A0_6", - "MONITOR_SE2A0_7", - "MONITOR_SE2A0_8", - "MONITOR_SE2A0_9", - "MONITOR_SE2A1_0", - "MONITOR_SE2A1_1", - "MONITOR_SE2A1_2", - "MONITOR_SE2A1_3", - "MONITOR_SE2A1_4", - "MONITOR_SE2A1_5", - "MONITOR_SE2A1_6", - "MONITOR_SE2A1_7", - "MONITOR_SE2A1_8", - "MONITOR_SE2A1_9", - "MONITOR_SE2A2_0", - "MONITOR_SE2A2_1", - "MONITOR_SE2A2_2", - "MONITOR_SE2A2_3", - "MONITOR_SE2A2_4", - "MONITOR_SE2A2_5", - "MONITOR_SE2A2_6", - "MONITOR_SE2A2_7", - "MONITOR_SE2A2_8", - "MONITOR_SE2A2_9", - "MONITOR_SE2A3_0", - "MONITOR_SE2A3_1", - "MONITOR_SE2A3_2", - "MONITOR_SE2A3_3", - "MONITOR_SE2A3_4", - "MONITOR_SE2A3_5", - "MONITOR_SE2A3_6", - "MONITOR_SE2A3_7", - "MONITOR_SE2A3_8", - "MONITOR_SE2A3_9", - "MONITOR_SE4BEG0_0", - "MONITOR_SE4BEG0_1", - "MONITOR_SE4BEG0_2", - "MONITOR_SE4BEG0_3", - "MONITOR_SE4BEG0_4", - "MONITOR_SE4BEG0_5", - "MONITOR_SE4BEG0_6", - "MONITOR_SE4BEG0_7", - "MONITOR_SE4BEG0_8", - "MONITOR_SE4BEG0_9", - "MONITOR_SE4BEG1_0", - "MONITOR_SE4BEG1_1", - "MONITOR_SE4BEG1_2", - "MONITOR_SE4BEG1_3", - "MONITOR_SE4BEG1_4", - "MONITOR_SE4BEG1_5", - "MONITOR_SE4BEG1_6", - "MONITOR_SE4BEG1_7", - "MONITOR_SE4BEG1_8", - "MONITOR_SE4BEG1_9", - "MONITOR_SE4BEG2_0", - "MONITOR_SE4BEG2_1", - "MONITOR_SE4BEG2_2", - "MONITOR_SE4BEG2_3", - "MONITOR_SE4BEG2_4", - "MONITOR_SE4BEG2_5", - "MONITOR_SE4BEG2_6", - "MONITOR_SE4BEG2_7", - "MONITOR_SE4BEG2_8", - "MONITOR_SE4BEG2_9", - "MONITOR_SE4BEG3_0", - "MONITOR_SE4BEG3_1", - "MONITOR_SE4BEG3_2", - "MONITOR_SE4BEG3_3", - "MONITOR_SE4BEG3_4", - "MONITOR_SE4BEG3_5", - "MONITOR_SE4BEG3_6", - "MONITOR_SE4BEG3_7", - "MONITOR_SE4BEG3_8", - "MONITOR_SE4BEG3_9", - "MONITOR_SE4C0_0", - "MONITOR_SE4C0_1", - "MONITOR_SE4C0_2", - "MONITOR_SE4C0_3", - "MONITOR_SE4C0_4", - "MONITOR_SE4C0_5", - "MONITOR_SE4C0_6", - "MONITOR_SE4C0_7", - "MONITOR_SE4C0_8", - "MONITOR_SE4C0_9", - "MONITOR_SE4C1_0", - "MONITOR_SE4C1_1", - "MONITOR_SE4C1_2", - "MONITOR_SE4C1_3", - "MONITOR_SE4C1_4", - "MONITOR_SE4C1_5", - "MONITOR_SE4C1_6", - "MONITOR_SE4C1_7", - "MONITOR_SE4C1_8", - "MONITOR_SE4C1_9", - "MONITOR_SE4C2_0", - "MONITOR_SE4C2_1", - "MONITOR_SE4C2_2", - "MONITOR_SE4C2_3", - "MONITOR_SE4C2_4", - "MONITOR_SE4C2_5", - "MONITOR_SE4C2_6", - "MONITOR_SE4C2_7", - "MONITOR_SE4C2_8", - "MONITOR_SE4C2_9", - "MONITOR_SE4C3_0", - "MONITOR_SE4C3_1", - "MONITOR_SE4C3_2", - "MONITOR_SE4C3_3", - "MONITOR_SE4C3_4", - "MONITOR_SE4C3_5", - "MONITOR_SE4C3_6", - "MONITOR_SE4C3_7", - "MONITOR_SE4C3_8", - "MONITOR_SE4C3_9", - "MONITOR_SW2A0_0", - "MONITOR_SW2A0_1", - "MONITOR_SW2A0_2", - "MONITOR_SW2A0_3", - "MONITOR_SW2A0_4", - "MONITOR_SW2A0_5", - "MONITOR_SW2A0_6", - "MONITOR_SW2A0_7", - "MONITOR_SW2A0_8", - "MONITOR_SW2A0_9", - "MONITOR_SW2A1_0", - "MONITOR_SW2A1_1", - "MONITOR_SW2A1_2", - "MONITOR_SW2A1_3", - "MONITOR_SW2A1_4", - "MONITOR_SW2A1_5", - "MONITOR_SW2A1_6", - "MONITOR_SW2A1_7", - "MONITOR_SW2A1_8", - "MONITOR_SW2A1_9", - "MONITOR_SW2A2_0", - "MONITOR_SW2A2_1", - "MONITOR_SW2A2_2", - "MONITOR_SW2A2_3", - "MONITOR_SW2A2_4", - "MONITOR_SW2A2_5", - "MONITOR_SW2A2_6", - "MONITOR_SW2A2_7", - "MONITOR_SW2A2_8", - "MONITOR_SW2A2_9", - "MONITOR_SW2A3_0", - "MONITOR_SW2A3_1", - "MONITOR_SW2A3_2", - "MONITOR_SW2A3_3", - "MONITOR_SW2A3_4", - "MONITOR_SW2A3_5", - "MONITOR_SW2A3_6", - "MONITOR_SW2A3_7", - "MONITOR_SW2A3_8", - "MONITOR_SW2A3_9", - "MONITOR_SW4A0_0", - "MONITOR_SW4A0_1", - "MONITOR_SW4A0_2", - "MONITOR_SW4A0_3", - "MONITOR_SW4A0_4", - "MONITOR_SW4A0_5", - "MONITOR_SW4A0_6", - "MONITOR_SW4A0_7", - "MONITOR_SW4A0_8", - "MONITOR_SW4A0_9", - "MONITOR_SW4A1_0", - "MONITOR_SW4A1_1", - "MONITOR_SW4A1_2", - "MONITOR_SW4A1_3", - "MONITOR_SW4A1_4", - "MONITOR_SW4A1_5", - "MONITOR_SW4A1_6", - "MONITOR_SW4A1_7", - "MONITOR_SW4A1_8", - "MONITOR_SW4A1_9", - "MONITOR_SW4A2_0", - "MONITOR_SW4A2_1", - "MONITOR_SW4A2_2", - "MONITOR_SW4A2_3", - "MONITOR_SW4A2_4", - "MONITOR_SW4A2_5", - "MONITOR_SW4A2_6", - "MONITOR_SW4A2_7", - "MONITOR_SW4A2_8", - "MONITOR_SW4A2_9", - "MONITOR_SW4A3_0", - "MONITOR_SW4A3_1", - "MONITOR_SW4A3_2", - "MONITOR_SW4A3_3", - "MONITOR_SW4A3_4", - "MONITOR_SW4A3_5", - "MONITOR_SW4A3_6", - "MONITOR_SW4A3_7", - "MONITOR_SW4A3_8", - "MONITOR_SW4A3_9", - "MONITOR_SW4END0_0", - "MONITOR_SW4END0_1", - "MONITOR_SW4END0_2", - "MONITOR_SW4END0_3", - "MONITOR_SW4END0_4", - "MONITOR_SW4END0_5", - "MONITOR_SW4END0_6", - "MONITOR_SW4END0_7", - "MONITOR_SW4END0_8", - "MONITOR_SW4END0_9", - "MONITOR_SW4END1_0", - "MONITOR_SW4END1_1", - "MONITOR_SW4END1_2", - "MONITOR_SW4END1_3", - "MONITOR_SW4END1_4", - "MONITOR_SW4END1_5", - "MONITOR_SW4END1_6", - "MONITOR_SW4END1_7", - "MONITOR_SW4END1_8", - "MONITOR_SW4END1_9", - "MONITOR_SW4END2_0", - "MONITOR_SW4END2_1", - "MONITOR_SW4END2_2", - "MONITOR_SW4END2_3", - "MONITOR_SW4END2_4", - "MONITOR_SW4END2_5", - "MONITOR_SW4END2_6", - "MONITOR_SW4END2_7", - "MONITOR_SW4END2_8", - "MONITOR_SW4END2_9", - "MONITOR_SW4END3_0", - "MONITOR_SW4END3_1", - "MONITOR_SW4END3_2", - "MONITOR_SW4END3_3", - "MONITOR_SW4END3_4", - "MONITOR_SW4END3_5", - "MONITOR_SW4END3_6", - "MONITOR_SW4END3_7", - "MONITOR_SW4END3_8", - "MONITOR_SW4END3_9", - "MONITOR_VERT_VAUXN0", - "MONITOR_VERT_VAUXN1", - "MONITOR_VERT_VAUXN10", - "MONITOR_VERT_VAUXN11", - "MONITOR_VERT_VAUXN12", - "MONITOR_VERT_VAUXN13", - "MONITOR_VERT_VAUXN14", - "MONITOR_VERT_VAUXN15", - "MONITOR_VERT_VAUXN2", - "MONITOR_VERT_VAUXN3", - "MONITOR_VERT_VAUXN4", - "MONITOR_VERT_VAUXN5", - "MONITOR_VERT_VAUXN6", - "MONITOR_VERT_VAUXN7", - "MONITOR_VERT_VAUXN8", - "MONITOR_VERT_VAUXN9", - "MONITOR_VERT_VAUXP0", - "MONITOR_VERT_VAUXP1", - "MONITOR_VERT_VAUXP10", - "MONITOR_VERT_VAUXP11", - "MONITOR_VERT_VAUXP12", - "MONITOR_VERT_VAUXP13", - "MONITOR_VERT_VAUXP14", - "MONITOR_VERT_VAUXP15", - "MONITOR_VERT_VAUXP2", - "MONITOR_VERT_VAUXP3", - "MONITOR_VERT_VAUXP4", - "MONITOR_VERT_VAUXP5", - "MONITOR_VERT_VAUXP6", - "MONITOR_VERT_VAUXP7", - "MONITOR_VERT_VAUXP8", - "MONITOR_VERT_VAUXP9", - "MONITOR_WL1END0_0", - "MONITOR_WL1END0_1", - "MONITOR_WL1END0_2", - "MONITOR_WL1END0_3", - "MONITOR_WL1END0_4", - "MONITOR_WL1END0_5", - "MONITOR_WL1END0_6", - "MONITOR_WL1END0_7", - "MONITOR_WL1END0_8", - "MONITOR_WL1END0_9", - "MONITOR_WL1END1_0", - "MONITOR_WL1END1_1", - "MONITOR_WL1END1_2", - "MONITOR_WL1END1_3", - "MONITOR_WL1END1_4", - "MONITOR_WL1END1_5", - "MONITOR_WL1END1_6", - "MONITOR_WL1END1_7", - "MONITOR_WL1END1_8", - "MONITOR_WL1END1_9", - "MONITOR_WL1END2_0", - "MONITOR_WL1END2_1", - "MONITOR_WL1END2_2", - "MONITOR_WL1END2_3", - "MONITOR_WL1END2_4", - "MONITOR_WL1END2_5", - "MONITOR_WL1END2_6", - "MONITOR_WL1END2_7", - "MONITOR_WL1END2_8", - "MONITOR_WL1END2_9", - "MONITOR_WL1END3_0", - "MONITOR_WL1END3_1", - "MONITOR_WL1END3_2", - "MONITOR_WL1END3_3", - "MONITOR_WL1END3_4", - "MONITOR_WL1END3_5", - "MONITOR_WL1END3_6", - "MONITOR_WL1END3_7", - "MONITOR_WL1END3_8", - "MONITOR_WL1END3_9", - "MONITOR_WR1END0_0", - "MONITOR_WR1END0_1", - "MONITOR_WR1END0_2", - "MONITOR_WR1END0_3", - "MONITOR_WR1END0_4", - "MONITOR_WR1END0_5", - "MONITOR_WR1END0_6", - "MONITOR_WR1END0_7", - "MONITOR_WR1END0_8", - "MONITOR_WR1END0_9", - "MONITOR_WR1END1_0", - "MONITOR_WR1END1_1", - "MONITOR_WR1END1_2", - "MONITOR_WR1END1_3", - "MONITOR_WR1END1_4", - "MONITOR_WR1END1_5", - "MONITOR_WR1END1_6", - "MONITOR_WR1END1_7", - "MONITOR_WR1END1_8", - "MONITOR_WR1END1_9", - "MONITOR_WR1END2_0", - "MONITOR_WR1END2_1", - "MONITOR_WR1END2_2", - "MONITOR_WR1END2_3", - "MONITOR_WR1END2_4", - "MONITOR_WR1END2_5", - "MONITOR_WR1END2_6", - "MONITOR_WR1END2_7", - "MONITOR_WR1END2_8", - "MONITOR_WR1END2_9", - "MONITOR_WR1END3_0", - "MONITOR_WR1END3_1", - "MONITOR_WR1END3_2", - "MONITOR_WR1END3_3", - "MONITOR_WR1END3_4", - "MONITOR_WR1END3_5", - "MONITOR_WR1END3_6", - "MONITOR_WR1END3_7", - "MONITOR_WR1END3_8", - "MONITOR_WR1END3_9", - "MONITOR_WW2A0_0", - "MONITOR_WW2A0_1", - "MONITOR_WW2A0_2", - "MONITOR_WW2A0_3", - "MONITOR_WW2A0_4", - "MONITOR_WW2A0_5", - "MONITOR_WW2A0_6", - "MONITOR_WW2A0_7", - "MONITOR_WW2A0_8", - "MONITOR_WW2A0_9", - "MONITOR_WW2A1_0", - "MONITOR_WW2A1_1", - "MONITOR_WW2A1_2", - "MONITOR_WW2A1_3", - "MONITOR_WW2A1_4", - "MONITOR_WW2A1_5", - "MONITOR_WW2A1_6", - "MONITOR_WW2A1_7", - "MONITOR_WW2A1_8", - "MONITOR_WW2A1_9", - "MONITOR_WW2A2_0", - "MONITOR_WW2A2_1", - "MONITOR_WW2A2_2", - "MONITOR_WW2A2_3", - "MONITOR_WW2A2_4", - "MONITOR_WW2A2_5", - "MONITOR_WW2A2_6", - "MONITOR_WW2A2_7", - "MONITOR_WW2A2_8", - "MONITOR_WW2A2_9", - "MONITOR_WW2A3_0", - "MONITOR_WW2A3_1", - "MONITOR_WW2A3_2", - "MONITOR_WW2A3_3", - "MONITOR_WW2A3_4", - "MONITOR_WW2A3_5", - "MONITOR_WW2A3_6", - "MONITOR_WW2A3_7", - "MONITOR_WW2A3_8", - "MONITOR_WW2A3_9", - "MONITOR_WW2END0_0", - "MONITOR_WW2END0_1", - "MONITOR_WW2END0_2", - "MONITOR_WW2END0_3", - "MONITOR_WW2END0_4", - "MONITOR_WW2END0_5", - "MONITOR_WW2END0_6", - "MONITOR_WW2END0_7", - "MONITOR_WW2END0_8", - "MONITOR_WW2END0_9", - "MONITOR_WW2END1_0", - "MONITOR_WW2END1_1", - "MONITOR_WW2END1_2", - "MONITOR_WW2END1_3", - "MONITOR_WW2END1_4", - "MONITOR_WW2END1_5", - "MONITOR_WW2END1_6", - "MONITOR_WW2END1_7", - "MONITOR_WW2END1_8", - "MONITOR_WW2END1_9", - "MONITOR_WW2END2_0", - "MONITOR_WW2END2_1", - "MONITOR_WW2END2_2", - "MONITOR_WW2END2_3", - "MONITOR_WW2END2_4", - "MONITOR_WW2END2_5", - "MONITOR_WW2END2_6", - "MONITOR_WW2END2_7", - "MONITOR_WW2END2_8", - "MONITOR_WW2END2_9", - "MONITOR_WW2END3_0", - "MONITOR_WW2END3_1", - "MONITOR_WW2END3_2", - "MONITOR_WW2END3_3", - "MONITOR_WW2END3_4", - "MONITOR_WW2END3_5", - "MONITOR_WW2END3_6", - "MONITOR_WW2END3_7", - "MONITOR_WW2END3_8", - "MONITOR_WW2END3_9", - "MONITOR_WW4A0_0", - "MONITOR_WW4A0_1", - "MONITOR_WW4A0_2", - "MONITOR_WW4A0_3", - "MONITOR_WW4A0_4", - "MONITOR_WW4A0_5", - "MONITOR_WW4A0_6", - "MONITOR_WW4A0_7", - "MONITOR_WW4A0_8", - "MONITOR_WW4A0_9", - "MONITOR_WW4A1_0", - "MONITOR_WW4A1_1", - "MONITOR_WW4A1_2", - "MONITOR_WW4A1_3", - "MONITOR_WW4A1_4", - "MONITOR_WW4A1_5", - "MONITOR_WW4A1_6", - "MONITOR_WW4A1_7", - "MONITOR_WW4A1_8", - "MONITOR_WW4A1_9", - "MONITOR_WW4A2_0", - "MONITOR_WW4A2_1", - "MONITOR_WW4A2_2", - "MONITOR_WW4A2_3", - "MONITOR_WW4A2_4", - "MONITOR_WW4A2_5", - "MONITOR_WW4A2_6", - "MONITOR_WW4A2_7", - "MONITOR_WW4A2_8", - "MONITOR_WW4A2_9", - "MONITOR_WW4A3_0", - "MONITOR_WW4A3_1", - "MONITOR_WW4A3_2", - "MONITOR_WW4A3_3", - "MONITOR_WW4A3_4", - "MONITOR_WW4A3_5", - "MONITOR_WW4A3_6", - "MONITOR_WW4A3_7", - "MONITOR_WW4A3_8", - "MONITOR_WW4A3_9", - "MONITOR_WW4B0_0", - "MONITOR_WW4B0_1", - "MONITOR_WW4B0_2", - "MONITOR_WW4B0_3", - "MONITOR_WW4B0_4", - "MONITOR_WW4B0_5", - "MONITOR_WW4B0_6", - "MONITOR_WW4B0_7", - "MONITOR_WW4B0_8", - "MONITOR_WW4B0_9", - "MONITOR_WW4B1_0", - "MONITOR_WW4B1_1", - "MONITOR_WW4B1_2", - "MONITOR_WW4B1_3", - "MONITOR_WW4B1_4", - "MONITOR_WW4B1_5", - "MONITOR_WW4B1_6", - "MONITOR_WW4B1_7", - "MONITOR_WW4B1_8", - "MONITOR_WW4B1_9", - "MONITOR_WW4B2_0", - "MONITOR_WW4B2_1", - "MONITOR_WW4B2_2", - "MONITOR_WW4B2_3", - "MONITOR_WW4B2_4", - "MONITOR_WW4B2_5", - "MONITOR_WW4B2_6", - "MONITOR_WW4B2_7", - "MONITOR_WW4B2_8", - "MONITOR_WW4B2_9", - "MONITOR_WW4B3_0", - "MONITOR_WW4B3_1", - "MONITOR_WW4B3_2", - "MONITOR_WW4B3_3", - "MONITOR_WW4B3_4", - "MONITOR_WW4B3_5", - "MONITOR_WW4B3_6", - "MONITOR_WW4B3_7", - "MONITOR_WW4B3_8", - "MONITOR_WW4B3_9", - "MONITOR_WW4C0_0", - "MONITOR_WW4C0_1", - "MONITOR_WW4C0_2", - "MONITOR_WW4C0_3", - "MONITOR_WW4C0_4", - "MONITOR_WW4C0_5", - "MONITOR_WW4C0_6", - "MONITOR_WW4C0_7", - "MONITOR_WW4C0_8", - "MONITOR_WW4C0_9", - "MONITOR_WW4C1_0", - "MONITOR_WW4C1_1", - "MONITOR_WW4C1_2", - "MONITOR_WW4C1_3", - "MONITOR_WW4C1_4", - "MONITOR_WW4C1_5", - "MONITOR_WW4C1_6", - "MONITOR_WW4C1_7", - "MONITOR_WW4C1_8", - "MONITOR_WW4C1_9", - "MONITOR_WW4C2_0", - "MONITOR_WW4C2_1", - "MONITOR_WW4C2_2", - "MONITOR_WW4C2_3", - "MONITOR_WW4C2_4", - "MONITOR_WW4C2_5", - "MONITOR_WW4C2_6", - "MONITOR_WW4C2_7", - "MONITOR_WW4C2_8", - "MONITOR_WW4C2_9", - "MONITOR_WW4C3_0", - "MONITOR_WW4C3_1", - "MONITOR_WW4C3_2", - "MONITOR_WW4C3_3", - "MONITOR_WW4C3_4", - "MONITOR_WW4C3_5", - "MONITOR_WW4C3_6", - "MONITOR_WW4C3_7", - "MONITOR_WW4C3_8", - "MONITOR_WW4C3_9", - "MONITOR_WW4END0_0", - "MONITOR_WW4END0_1", - "MONITOR_WW4END0_2", - "MONITOR_WW4END0_3", - "MONITOR_WW4END0_4", - "MONITOR_WW4END0_5", - "MONITOR_WW4END0_6", - "MONITOR_WW4END0_7", - "MONITOR_WW4END0_8", - "MONITOR_WW4END0_9", - "MONITOR_WW4END1_0", - "MONITOR_WW4END1_1", - "MONITOR_WW4END1_2", - "MONITOR_WW4END1_3", - "MONITOR_WW4END1_4", - "MONITOR_WW4END1_5", - "MONITOR_WW4END1_6", - "MONITOR_WW4END1_7", - "MONITOR_WW4END1_8", - "MONITOR_WW4END1_9", - "MONITOR_WW4END2_0", - "MONITOR_WW4END2_1", - "MONITOR_WW4END2_2", - "MONITOR_WW4END2_3", - "MONITOR_WW4END2_4", - "MONITOR_WW4END2_5", - "MONITOR_WW4END2_6", - "MONITOR_WW4END2_7", - "MONITOR_WW4END2_8", - "MONITOR_WW4END2_9", - "MONITOR_WW4END3_0", - "MONITOR_WW4END3_1", - "MONITOR_WW4END3_2", - "MONITOR_WW4END3_3", - "MONITOR_WW4END3_4", - "MONITOR_WW4END3_5", - "MONITOR_WW4END3_6", - "MONITOR_WW4END3_7", - "MONITOR_WW4END3_8", - "MONITOR_WW4END3_9" - ] + "wires": { + "MONITOR_BLOCK_OUTS_B0_0": null, + "MONITOR_BLOCK_OUTS_B0_1": null, + "MONITOR_BLOCK_OUTS_B0_2": null, + "MONITOR_BLOCK_OUTS_B0_3": null, + "MONITOR_BLOCK_OUTS_B0_4": null, + "MONITOR_BLOCK_OUTS_B0_5": null, + "MONITOR_BLOCK_OUTS_B0_6": null, + "MONITOR_BLOCK_OUTS_B0_7": null, + "MONITOR_BLOCK_OUTS_B0_8": null, + "MONITOR_BLOCK_OUTS_B0_9": null, + "MONITOR_BLOCK_OUTS_B1_0": null, + "MONITOR_BLOCK_OUTS_B1_1": null, + "MONITOR_BLOCK_OUTS_B1_2": null, + "MONITOR_BLOCK_OUTS_B1_3": null, + "MONITOR_BLOCK_OUTS_B1_4": null, + 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null, + "MONITOR_WW4C1_3": null, + "MONITOR_WW4C1_4": null, + "MONITOR_WW4C1_5": null, + "MONITOR_WW4C1_6": null, + "MONITOR_WW4C1_7": null, + "MONITOR_WW4C1_8": null, + "MONITOR_WW4C1_9": null, + "MONITOR_WW4C2_0": null, + "MONITOR_WW4C2_1": null, + "MONITOR_WW4C2_2": null, + "MONITOR_WW4C2_3": null, + "MONITOR_WW4C2_4": null, + "MONITOR_WW4C2_5": null, + "MONITOR_WW4C2_6": null, + "MONITOR_WW4C2_7": null, + "MONITOR_WW4C2_8": null, + "MONITOR_WW4C2_9": null, + "MONITOR_WW4C3_0": null, + "MONITOR_WW4C3_1": null, + "MONITOR_WW4C3_2": null, + "MONITOR_WW4C3_3": null, + "MONITOR_WW4C3_4": null, + "MONITOR_WW4C3_5": null, + "MONITOR_WW4C3_6": null, + "MONITOR_WW4C3_7": null, + "MONITOR_WW4C3_8": null, + "MONITOR_WW4C3_9": null, + "MONITOR_WW4END0_0": null, + "MONITOR_WW4END0_1": null, + "MONITOR_WW4END0_2": null, + "MONITOR_WW4END0_3": null, + "MONITOR_WW4END0_4": null, + "MONITOR_WW4END0_5": null, + "MONITOR_WW4END0_6": null, + "MONITOR_WW4END0_7": null, + "MONITOR_WW4END0_8": null, + "MONITOR_WW4END0_9": null, + "MONITOR_WW4END1_0": null, + "MONITOR_WW4END1_1": null, + "MONITOR_WW4END1_2": null, + "MONITOR_WW4END1_3": null, + "MONITOR_WW4END1_4": null, + "MONITOR_WW4END1_5": null, + "MONITOR_WW4END1_6": null, + "MONITOR_WW4END1_7": null, + "MONITOR_WW4END1_8": null, + "MONITOR_WW4END1_9": null, + "MONITOR_WW4END2_0": null, + "MONITOR_WW4END2_1": null, + "MONITOR_WW4END2_2": null, + "MONITOR_WW4END2_3": null, + "MONITOR_WW4END2_4": null, + "MONITOR_WW4END2_5": null, + "MONITOR_WW4END2_6": null, + "MONITOR_WW4END2_7": null, + "MONITOR_WW4END2_8": null, + "MONITOR_WW4END2_9": null, + "MONITOR_WW4END3_0": null, + "MONITOR_WW4END3_1": null, + "MONITOR_WW4END3_2": null, + "MONITOR_WW4END3_3": null, + "MONITOR_WW4END3_4": null, + "MONITOR_WW4END3_5": null, + "MONITOR_WW4END3_6": null, + "MONITOR_WW4END3_7": null, + "MONITOR_WW4END3_8": null, + "MONITOR_WW4END3_9": null + } } diff --git a/kintex7/tile_type_MONITOR_TOP_FUJI2.json b/kintex7/tile_type_MONITOR_TOP_FUJI2.json index 5f876ad..6483576 100644 --- a/kintex7/tile_type_MONITOR_TOP_FUJI2.json +++ b/kintex7/tile_type_MONITOR_TOP_FUJI2.json @@ -2,1171 +2,1215 @@ "pips": { "MONITOR_TOP_FUJI2.MONITOR_HORIZ_VAUXN0->MONITOR_VERT_SHORT_VAUXN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN0" }, "MONITOR_TOP_FUJI2.MONITOR_HORIZ_VAUXN8->MONITOR_VERT_SHORT_VAUXN8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXN8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXN8" }, "MONITOR_TOP_FUJI2.MONITOR_HORIZ_VAUXP0->MONITOR_VERT_SHORT_VAUXP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP0" }, "MONITOR_TOP_FUJI2.MONITOR_HORIZ_VAUXP8->MONITOR_VERT_SHORT_VAUXP8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "MONITOR_VERT_SHORT_VAUXP8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "MONITOR_HORIZ_VAUXP8" } }, "sites": [], "tile_type": "MONITOR_TOP_FUJI2", - "wires": [ - "MONITOR_BLOCK_OUTS_B0_0", - "MONITOR_BLOCK_OUTS_B0_1", - "MONITOR_BLOCK_OUTS_B0_2", - "MONITOR_BLOCK_OUTS_B0_3", - "MONITOR_BLOCK_OUTS_B0_4", - "MONITOR_BLOCK_OUTS_B1_0", - "MONITOR_BLOCK_OUTS_B1_1", - "MONITOR_BLOCK_OUTS_B1_2", - "MONITOR_BLOCK_OUTS_B1_3", - "MONITOR_BLOCK_OUTS_B1_4", - "MONITOR_BLOCK_OUTS_B2_0", - "MONITOR_BLOCK_OUTS_B2_1", - "MONITOR_BLOCK_OUTS_B2_2", - "MONITOR_BLOCK_OUTS_B2_3", - "MONITOR_BLOCK_OUTS_B2_4", - "MONITOR_BLOCK_OUTS_B3_0", - "MONITOR_BLOCK_OUTS_B3_1", - "MONITOR_BLOCK_OUTS_B3_2", - "MONITOR_BLOCK_OUTS_B3_3", - "MONITOR_BLOCK_OUTS_B3_4", - "MONITOR_BYP0_0", - "MONITOR_BYP0_1", - "MONITOR_BYP0_2", - "MONITOR_BYP0_3", - "MONITOR_BYP0_4", - "MONITOR_BYP1_0", - "MONITOR_BYP1_1", - "MONITOR_BYP1_2", - "MONITOR_BYP1_3", - "MONITOR_BYP1_4", - "MONITOR_BYP2_0", - "MONITOR_BYP2_1", - "MONITOR_BYP2_2", - "MONITOR_BYP2_3", - "MONITOR_BYP2_4", - "MONITOR_BYP3_0", - "MONITOR_BYP3_1", - "MONITOR_BYP3_2", - "MONITOR_BYP3_3", - "MONITOR_BYP3_4", - "MONITOR_BYP4_0", - "MONITOR_BYP4_1", - "MONITOR_BYP4_2", - "MONITOR_BYP4_3", - "MONITOR_BYP4_4", - "MONITOR_BYP5_0", - "MONITOR_BYP5_1", - "MONITOR_BYP5_2", - "MONITOR_BYP5_3", - "MONITOR_BYP5_4", - "MONITOR_BYP6_0", - "MONITOR_BYP6_1", - "MONITOR_BYP6_2", - "MONITOR_BYP6_3", - "MONITOR_BYP6_4", - "MONITOR_BYP7_0", - "MONITOR_BYP7_1", - "MONITOR_BYP7_2", - "MONITOR_BYP7_3", - "MONITOR_BYP7_4", - "MONITOR_CLK0_0", - "MONITOR_CLK0_1", - "MONITOR_CLK0_2", - "MONITOR_CLK0_3", - "MONITOR_CLK0_4", - "MONITOR_CLK1_0", - "MONITOR_CLK1_1", - "MONITOR_CLK1_2", - "MONITOR_CLK1_3", - "MONITOR_CLK1_4", - "MONITOR_CTRL0_0", - "MONITOR_CTRL0_1", - "MONITOR_CTRL0_2", - "MONITOR_CTRL0_3", - "MONITOR_CTRL0_4", - "MONITOR_CTRL1_0", - "MONITOR_CTRL1_1", - "MONITOR_CTRL1_2", - "MONITOR_CTRL1_3", - "MONITOR_CTRL1_4", - "MONITOR_EE2A0_0", - "MONITOR_EE2A0_1", - "MONITOR_EE2A0_2", - "MONITOR_EE2A0_3", - "MONITOR_EE2A0_4", - "MONITOR_EE2A1_0", - "MONITOR_EE2A1_1", - "MONITOR_EE2A1_2", - "MONITOR_EE2A1_3", - "MONITOR_EE2A1_4", - "MONITOR_EE2A2_0", - "MONITOR_EE2A2_1", - "MONITOR_EE2A2_2", - "MONITOR_EE2A2_3", - "MONITOR_EE2A2_4", - "MONITOR_EE2A3_0", - "MONITOR_EE2A3_1", - "MONITOR_EE2A3_2", - "MONITOR_EE2A3_3", - "MONITOR_EE2A3_4", - "MONITOR_EE2BEG0_0", - "MONITOR_EE2BEG0_1", - "MONITOR_EE2BEG0_2", - "MONITOR_EE2BEG0_3", - "MONITOR_EE2BEG0_4", - "MONITOR_EE2BEG1_0", - "MONITOR_EE2BEG1_1", - "MONITOR_EE2BEG1_2", - "MONITOR_EE2BEG1_3", - "MONITOR_EE2BEG1_4", - "MONITOR_EE2BEG2_0", - "MONITOR_EE2BEG2_1", - "MONITOR_EE2BEG2_2", - "MONITOR_EE2BEG2_3", - "MONITOR_EE2BEG2_4", - "MONITOR_EE2BEG3_0", - "MONITOR_EE2BEG3_1", - "MONITOR_EE2BEG3_2", - "MONITOR_EE2BEG3_3", - "MONITOR_EE2BEG3_4", - "MONITOR_EE4A0_0", - "MONITOR_EE4A0_1", - "MONITOR_EE4A0_2", - "MONITOR_EE4A0_3", - "MONITOR_EE4A0_4", - "MONITOR_EE4A1_0", - "MONITOR_EE4A1_1", - "MONITOR_EE4A1_2", - "MONITOR_EE4A1_3", - "MONITOR_EE4A1_4", - "MONITOR_EE4A2_0", - "MONITOR_EE4A2_1", - "MONITOR_EE4A2_2", - "MONITOR_EE4A2_3", - "MONITOR_EE4A2_4", - "MONITOR_EE4A3_0", - "MONITOR_EE4A3_1", - "MONITOR_EE4A3_2", - "MONITOR_EE4A3_3", - "MONITOR_EE4A3_4", - "MONITOR_EE4B0_0", - "MONITOR_EE4B0_1", - "MONITOR_EE4B0_2", - "MONITOR_EE4B0_3", - "MONITOR_EE4B0_4", - "MONITOR_EE4B1_0", - "MONITOR_EE4B1_1", - "MONITOR_EE4B1_2", - "MONITOR_EE4B1_3", - "MONITOR_EE4B1_4", - "MONITOR_EE4B2_0", - "MONITOR_EE4B2_1", - "MONITOR_EE4B2_2", - "MONITOR_EE4B2_3", - "MONITOR_EE4B2_4", - "MONITOR_EE4B3_0", - "MONITOR_EE4B3_1", - "MONITOR_EE4B3_2", - "MONITOR_EE4B3_3", - "MONITOR_EE4B3_4", - "MONITOR_EE4BEG0_0", - "MONITOR_EE4BEG0_1", - "MONITOR_EE4BEG0_2", - "MONITOR_EE4BEG0_3", - "MONITOR_EE4BEG0_4", - "MONITOR_EE4BEG1_0", - "MONITOR_EE4BEG1_1", - "MONITOR_EE4BEG1_2", - "MONITOR_EE4BEG1_3", - "MONITOR_EE4BEG1_4", - "MONITOR_EE4BEG2_0", - "MONITOR_EE4BEG2_1", - "MONITOR_EE4BEG2_2", - "MONITOR_EE4BEG2_3", - "MONITOR_EE4BEG2_4", - "MONITOR_EE4BEG3_0", - "MONITOR_EE4BEG3_1", - "MONITOR_EE4BEG3_2", - "MONITOR_EE4BEG3_3", - "MONITOR_EE4BEG3_4", - "MONITOR_EE4C0_0", - "MONITOR_EE4C0_1", - "MONITOR_EE4C0_2", - "MONITOR_EE4C0_3", - "MONITOR_EE4C0_4", - "MONITOR_EE4C1_0", - "MONITOR_EE4C1_1", - "MONITOR_EE4C1_2", - "MONITOR_EE4C1_3", - "MONITOR_EE4C1_4", - "MONITOR_EE4C2_0", - "MONITOR_EE4C2_1", - "MONITOR_EE4C2_2", - "MONITOR_EE4C2_3", - "MONITOR_EE4C2_4", - "MONITOR_EE4C3_0", - "MONITOR_EE4C3_1", - "MONITOR_EE4C3_2", - "MONITOR_EE4C3_3", - "MONITOR_EE4C3_4", - "MONITOR_EL1BEG0_0", - "MONITOR_EL1BEG0_1", - "MONITOR_EL1BEG0_2", - "MONITOR_EL1BEG0_3", - "MONITOR_EL1BEG0_4", - "MONITOR_EL1BEG1_0", - "MONITOR_EL1BEG1_1", - "MONITOR_EL1BEG1_2", - "MONITOR_EL1BEG1_3", - "MONITOR_EL1BEG1_4", - "MONITOR_EL1BEG2_0", - "MONITOR_EL1BEG2_1", - "MONITOR_EL1BEG2_2", - "MONITOR_EL1BEG2_3", - "MONITOR_EL1BEG2_4", - "MONITOR_EL1BEG3_0", - "MONITOR_EL1BEG3_1", - "MONITOR_EL1BEG3_2", - "MONITOR_EL1BEG3_3", - "MONITOR_EL1BEG3_4", - "MONITOR_ER1BEG0_0", - "MONITOR_ER1BEG0_1", - "MONITOR_ER1BEG0_2", - "MONITOR_ER1BEG0_3", - "MONITOR_ER1BEG0_4", - "MONITOR_ER1BEG1_0", - "MONITOR_ER1BEG1_1", - "MONITOR_ER1BEG1_2", - "MONITOR_ER1BEG1_3", - "MONITOR_ER1BEG1_4", - "MONITOR_ER1BEG2_0", - "MONITOR_ER1BEG2_1", - "MONITOR_ER1BEG2_2", - "MONITOR_ER1BEG2_3", - "MONITOR_ER1BEG2_4", - "MONITOR_ER1BEG3_0", - "MONITOR_ER1BEG3_1", - "MONITOR_ER1BEG3_2", - "MONITOR_ER1BEG3_3", - "MONITOR_ER1BEG3_4", - "MONITOR_FAN0_0", - "MONITOR_FAN0_1", - "MONITOR_FAN0_2", - "MONITOR_FAN0_3", - "MONITOR_FAN0_4", - "MONITOR_FAN1_0", - "MONITOR_FAN1_1", - "MONITOR_FAN1_2", - "MONITOR_FAN1_3", - "MONITOR_FAN1_4", - "MONITOR_FAN2_0", - "MONITOR_FAN2_1", - "MONITOR_FAN2_2", - "MONITOR_FAN2_3", - "MONITOR_FAN2_4", - "MONITOR_FAN3_0", - "MONITOR_FAN3_1", - "MONITOR_FAN3_2", - "MONITOR_FAN3_3", - "MONITOR_FAN3_4", - "MONITOR_FAN4_0", - "MONITOR_FAN4_1", - "MONITOR_FAN4_2", - "MONITOR_FAN4_3", - "MONITOR_FAN4_4", - "MONITOR_FAN5_0", - "MONITOR_FAN5_1", - "MONITOR_FAN5_2", - "MONITOR_FAN5_3", - "MONITOR_FAN5_4", - "MONITOR_FAN6_0", - "MONITOR_FAN6_1", - "MONITOR_FAN6_2", - "MONITOR_FAN6_3", - "MONITOR_FAN6_4", - "MONITOR_FAN7_0", - "MONITOR_FAN7_1", - "MONITOR_FAN7_2", - "MONITOR_FAN7_3", - "MONITOR_FAN7_4", - "MONITOR_HORIZ_VAUXN0", - "MONITOR_HORIZ_VAUXN8", - "MONITOR_HORIZ_VAUXP0", - "MONITOR_HORIZ_VAUXP8", - "MONITOR_IMUX0_0", - "MONITOR_IMUX0_1", - "MONITOR_IMUX0_2", - "MONITOR_IMUX0_3", - "MONITOR_IMUX0_4", - "MONITOR_IMUX10_0", - "MONITOR_IMUX10_1", - "MONITOR_IMUX10_2", - "MONITOR_IMUX10_3", - "MONITOR_IMUX10_4", - "MONITOR_IMUX11_0", - "MONITOR_IMUX11_1", - "MONITOR_IMUX11_2", - "MONITOR_IMUX11_3", - "MONITOR_IMUX11_4", - "MONITOR_IMUX12_0", - "MONITOR_IMUX12_1", - "MONITOR_IMUX12_2", - "MONITOR_IMUX12_3", - "MONITOR_IMUX12_4", - "MONITOR_IMUX13_0", - "MONITOR_IMUX13_1", - "MONITOR_IMUX13_2", - "MONITOR_IMUX13_3", - "MONITOR_IMUX13_4", - "MONITOR_IMUX14_0", - "MONITOR_IMUX14_1", - "MONITOR_IMUX14_2", - "MONITOR_IMUX14_3", - "MONITOR_IMUX14_4", - "MONITOR_IMUX15_0", - "MONITOR_IMUX15_1", - "MONITOR_IMUX15_2", - "MONITOR_IMUX15_3", - "MONITOR_IMUX15_4", - "MONITOR_IMUX16_0", - "MONITOR_IMUX16_1", - "MONITOR_IMUX16_2", - "MONITOR_IMUX16_3", - "MONITOR_IMUX16_4", - "MONITOR_IMUX17_0", - "MONITOR_IMUX17_1", - "MONITOR_IMUX17_2", - "MONITOR_IMUX17_3", - "MONITOR_IMUX17_4", - "MONITOR_IMUX18_0", - "MONITOR_IMUX18_1", - "MONITOR_IMUX18_2", - "MONITOR_IMUX18_3", - "MONITOR_IMUX18_4", - "MONITOR_IMUX19_0", - "MONITOR_IMUX19_1", - "MONITOR_IMUX19_2", - "MONITOR_IMUX19_3", - "MONITOR_IMUX19_4", - "MONITOR_IMUX1_0", - "MONITOR_IMUX1_1", - "MONITOR_IMUX1_2", - "MONITOR_IMUX1_3", - "MONITOR_IMUX1_4", - "MONITOR_IMUX20_0", - "MONITOR_IMUX20_1", - "MONITOR_IMUX20_2", - "MONITOR_IMUX20_3", - "MONITOR_IMUX20_4", - "MONITOR_IMUX21_0", - "MONITOR_IMUX21_1", - "MONITOR_IMUX21_2", - "MONITOR_IMUX21_3", - "MONITOR_IMUX21_4", - "MONITOR_IMUX22_0", - "MONITOR_IMUX22_1", - "MONITOR_IMUX22_2", - "MONITOR_IMUX22_3", - "MONITOR_IMUX22_4", - "MONITOR_IMUX23_0", - "MONITOR_IMUX23_1", - "MONITOR_IMUX23_2", - "MONITOR_IMUX23_3", - "MONITOR_IMUX23_4", - "MONITOR_IMUX24_0", - "MONITOR_IMUX24_1", - "MONITOR_IMUX24_2", - "MONITOR_IMUX24_3", - "MONITOR_IMUX24_4", - "MONITOR_IMUX25_0", - "MONITOR_IMUX25_1", - "MONITOR_IMUX25_2", - "MONITOR_IMUX25_3", - "MONITOR_IMUX25_4", - "MONITOR_IMUX26_0", - "MONITOR_IMUX26_1", - "MONITOR_IMUX26_2", - "MONITOR_IMUX26_3", - "MONITOR_IMUX26_4", - "MONITOR_IMUX27_0", - "MONITOR_IMUX27_1", - "MONITOR_IMUX27_2", - "MONITOR_IMUX27_3", - "MONITOR_IMUX27_4", - "MONITOR_IMUX28_0", - "MONITOR_IMUX28_1", - "MONITOR_IMUX28_2", - "MONITOR_IMUX28_3", - "MONITOR_IMUX28_4", - "MONITOR_IMUX29_0", - "MONITOR_IMUX29_1", - "MONITOR_IMUX29_2", - "MONITOR_IMUX29_3", - "MONITOR_IMUX29_4", - "MONITOR_IMUX2_0", - "MONITOR_IMUX2_1", - "MONITOR_IMUX2_2", - "MONITOR_IMUX2_3", - "MONITOR_IMUX2_4", - "MONITOR_IMUX30_0", - "MONITOR_IMUX30_1", - "MONITOR_IMUX30_2", - "MONITOR_IMUX30_3", - "MONITOR_IMUX30_4", - "MONITOR_IMUX31_0", - "MONITOR_IMUX31_1", - "MONITOR_IMUX31_2", - "MONITOR_IMUX31_3", - "MONITOR_IMUX31_4", - "MONITOR_IMUX32_0", - "MONITOR_IMUX32_1", - "MONITOR_IMUX32_2", - "MONITOR_IMUX32_3", - "MONITOR_IMUX32_4", - "MONITOR_IMUX33_0", - "MONITOR_IMUX33_1", - "MONITOR_IMUX33_2", - "MONITOR_IMUX33_3", - "MONITOR_IMUX33_4", - "MONITOR_IMUX34_0", - "MONITOR_IMUX34_1", - "MONITOR_IMUX34_2", - "MONITOR_IMUX34_3", - "MONITOR_IMUX34_4", - "MONITOR_IMUX35_0", - "MONITOR_IMUX35_1", - "MONITOR_IMUX35_2", - "MONITOR_IMUX35_3", - "MONITOR_IMUX35_4", - "MONITOR_IMUX36_0", - "MONITOR_IMUX36_1", - "MONITOR_IMUX36_2", - "MONITOR_IMUX36_3", - "MONITOR_IMUX36_4", - "MONITOR_IMUX37_0", - "MONITOR_IMUX37_1", - "MONITOR_IMUX37_2", - "MONITOR_IMUX37_3", - "MONITOR_IMUX37_4", - "MONITOR_IMUX38_0", - "MONITOR_IMUX38_1", - "MONITOR_IMUX38_2", - "MONITOR_IMUX38_3", - "MONITOR_IMUX38_4", - "MONITOR_IMUX39_0", - "MONITOR_IMUX39_1", - "MONITOR_IMUX39_2", - "MONITOR_IMUX39_3", - "MONITOR_IMUX39_4", - "MONITOR_IMUX3_0", - "MONITOR_IMUX3_1", - "MONITOR_IMUX3_2", - "MONITOR_IMUX3_3", - "MONITOR_IMUX3_4", - "MONITOR_IMUX40_0", - "MONITOR_IMUX40_1", - "MONITOR_IMUX40_2", - "MONITOR_IMUX40_3", - "MONITOR_IMUX40_4", - "MONITOR_IMUX41_0", - "MONITOR_IMUX41_1", - "MONITOR_IMUX41_2", - "MONITOR_IMUX41_3", - "MONITOR_IMUX41_4", - "MONITOR_IMUX42_0", - "MONITOR_IMUX42_1", - "MONITOR_IMUX42_2", - "MONITOR_IMUX42_3", - "MONITOR_IMUX42_4", - "MONITOR_IMUX43_0", - "MONITOR_IMUX43_1", - "MONITOR_IMUX43_2", - "MONITOR_IMUX43_3", - "MONITOR_IMUX43_4", - "MONITOR_IMUX44_0", - "MONITOR_IMUX44_1", - "MONITOR_IMUX44_2", - "MONITOR_IMUX44_3", - "MONITOR_IMUX44_4", - "MONITOR_IMUX45_0", - "MONITOR_IMUX45_1", - "MONITOR_IMUX45_2", - "MONITOR_IMUX45_3", - "MONITOR_IMUX45_4", - "MONITOR_IMUX46_0", - "MONITOR_IMUX46_1", - "MONITOR_IMUX46_2", - "MONITOR_IMUX46_3", - "MONITOR_IMUX46_4", - "MONITOR_IMUX47_0", - "MONITOR_IMUX47_1", - "MONITOR_IMUX47_2", - "MONITOR_IMUX47_3", - "MONITOR_IMUX47_4", - "MONITOR_IMUX4_0", - "MONITOR_IMUX4_1", - "MONITOR_IMUX4_2", - "MONITOR_IMUX4_3", - "MONITOR_IMUX4_4", - "MONITOR_IMUX5_0", - "MONITOR_IMUX5_1", - "MONITOR_IMUX5_2", - "MONITOR_IMUX5_3", - "MONITOR_IMUX5_4", - "MONITOR_IMUX6_0", - "MONITOR_IMUX6_1", - "MONITOR_IMUX6_2", - "MONITOR_IMUX6_3", - "MONITOR_IMUX6_4", - "MONITOR_IMUX7_0", - "MONITOR_IMUX7_1", - "MONITOR_IMUX7_2", - "MONITOR_IMUX7_3", - "MONITOR_IMUX7_4", - "MONITOR_IMUX8_0", - "MONITOR_IMUX8_1", - "MONITOR_IMUX8_2", - "MONITOR_IMUX8_3", - "MONITOR_IMUX8_4", - "MONITOR_IMUX9_0", - "MONITOR_IMUX9_1", - "MONITOR_IMUX9_2", - "MONITOR_IMUX9_3", - "MONITOR_IMUX9_4", - "MONITOR_LH10_0", - "MONITOR_LH10_1", - "MONITOR_LH10_2", - "MONITOR_LH10_3", - "MONITOR_LH10_4", - "MONITOR_LH11_0", - "MONITOR_LH11_1", - "MONITOR_LH11_2", - "MONITOR_LH11_3", - "MONITOR_LH11_4", - "MONITOR_LH12_0", - "MONITOR_LH12_1", - "MONITOR_LH12_2", - "MONITOR_LH12_3", - "MONITOR_LH12_4", - "MONITOR_LH1_0", - "MONITOR_LH1_1", - "MONITOR_LH1_2", - "MONITOR_LH1_3", - "MONITOR_LH1_4", - "MONITOR_LH2_0", - "MONITOR_LH2_1", - "MONITOR_LH2_2", - "MONITOR_LH2_3", - "MONITOR_LH2_4", - "MONITOR_LH3_0", - "MONITOR_LH3_1", - "MONITOR_LH3_2", - "MONITOR_LH3_3", - "MONITOR_LH3_4", - "MONITOR_LH4_0", - "MONITOR_LH4_1", - "MONITOR_LH4_2", - "MONITOR_LH4_3", - "MONITOR_LH4_4", - "MONITOR_LH5_0", - "MONITOR_LH5_1", - "MONITOR_LH5_2", - "MONITOR_LH5_3", - "MONITOR_LH5_4", - "MONITOR_LH6_0", - "MONITOR_LH6_1", - "MONITOR_LH6_2", - "MONITOR_LH6_3", - "MONITOR_LH6_4", - "MONITOR_LH7_0", - "MONITOR_LH7_1", - "MONITOR_LH7_2", - "MONITOR_LH7_3", - "MONITOR_LH7_4", - "MONITOR_LH8_0", - "MONITOR_LH8_1", - "MONITOR_LH8_2", - "MONITOR_LH8_3", - "MONITOR_LH8_4", - "MONITOR_LH9_0", - "MONITOR_LH9_1", - "MONITOR_LH9_2", - "MONITOR_LH9_3", - "MONITOR_LH9_4", - "MONITOR_LOGIC_OUTS_B0_0", - "MONITOR_LOGIC_OUTS_B0_1", - "MONITOR_LOGIC_OUTS_B0_2", - "MONITOR_LOGIC_OUTS_B0_3", - "MONITOR_LOGIC_OUTS_B0_4", - "MONITOR_LOGIC_OUTS_B10_0", - "MONITOR_LOGIC_OUTS_B10_1", - "MONITOR_LOGIC_OUTS_B10_2", - "MONITOR_LOGIC_OUTS_B10_3", - "MONITOR_LOGIC_OUTS_B10_4", - "MONITOR_LOGIC_OUTS_B11_0", - "MONITOR_LOGIC_OUTS_B11_1", - "MONITOR_LOGIC_OUTS_B11_2", - "MONITOR_LOGIC_OUTS_B11_3", - "MONITOR_LOGIC_OUTS_B11_4", - "MONITOR_LOGIC_OUTS_B12_0", - "MONITOR_LOGIC_OUTS_B12_1", - "MONITOR_LOGIC_OUTS_B12_2", - "MONITOR_LOGIC_OUTS_B12_3", - "MONITOR_LOGIC_OUTS_B12_4", - "MONITOR_LOGIC_OUTS_B13_0", - "MONITOR_LOGIC_OUTS_B13_1", - "MONITOR_LOGIC_OUTS_B13_2", - "MONITOR_LOGIC_OUTS_B13_3", - "MONITOR_LOGIC_OUTS_B13_4", - "MONITOR_LOGIC_OUTS_B14_0", - "MONITOR_LOGIC_OUTS_B14_1", - "MONITOR_LOGIC_OUTS_B14_2", - "MONITOR_LOGIC_OUTS_B14_3", - "MONITOR_LOGIC_OUTS_B14_4", - "MONITOR_LOGIC_OUTS_B15_0", - "MONITOR_LOGIC_OUTS_B15_1", - "MONITOR_LOGIC_OUTS_B15_2", - "MONITOR_LOGIC_OUTS_B15_3", - "MONITOR_LOGIC_OUTS_B15_4", - "MONITOR_LOGIC_OUTS_B16_0", - "MONITOR_LOGIC_OUTS_B16_1", - "MONITOR_LOGIC_OUTS_B16_2", - "MONITOR_LOGIC_OUTS_B16_3", - "MONITOR_LOGIC_OUTS_B16_4", - "MONITOR_LOGIC_OUTS_B17_0", - "MONITOR_LOGIC_OUTS_B17_1", - "MONITOR_LOGIC_OUTS_B17_2", - "MONITOR_LOGIC_OUTS_B17_3", - "MONITOR_LOGIC_OUTS_B17_4", - "MONITOR_LOGIC_OUTS_B18_0", - "MONITOR_LOGIC_OUTS_B18_1", - "MONITOR_LOGIC_OUTS_B18_2", - "MONITOR_LOGIC_OUTS_B18_3", - "MONITOR_LOGIC_OUTS_B18_4", - "MONITOR_LOGIC_OUTS_B19_0", - "MONITOR_LOGIC_OUTS_B19_1", - "MONITOR_LOGIC_OUTS_B19_2", - "MONITOR_LOGIC_OUTS_B19_3", - "MONITOR_LOGIC_OUTS_B19_4", - "MONITOR_LOGIC_OUTS_B1_0", - "MONITOR_LOGIC_OUTS_B1_1", - "MONITOR_LOGIC_OUTS_B1_2", - "MONITOR_LOGIC_OUTS_B1_3", - "MONITOR_LOGIC_OUTS_B1_4", - "MONITOR_LOGIC_OUTS_B20_0", - "MONITOR_LOGIC_OUTS_B20_1", - "MONITOR_LOGIC_OUTS_B20_2", - "MONITOR_LOGIC_OUTS_B20_3", - "MONITOR_LOGIC_OUTS_B20_4", - "MONITOR_LOGIC_OUTS_B21_0", - "MONITOR_LOGIC_OUTS_B21_1", - "MONITOR_LOGIC_OUTS_B21_2", - "MONITOR_LOGIC_OUTS_B21_3", - "MONITOR_LOGIC_OUTS_B21_4", - "MONITOR_LOGIC_OUTS_B22_0", - "MONITOR_LOGIC_OUTS_B22_1", - "MONITOR_LOGIC_OUTS_B22_2", - "MONITOR_LOGIC_OUTS_B22_3", - "MONITOR_LOGIC_OUTS_B22_4", - "MONITOR_LOGIC_OUTS_B23_0", - "MONITOR_LOGIC_OUTS_B23_1", - "MONITOR_LOGIC_OUTS_B23_2", - "MONITOR_LOGIC_OUTS_B23_3", - "MONITOR_LOGIC_OUTS_B23_4", - "MONITOR_LOGIC_OUTS_B2_0", - "MONITOR_LOGIC_OUTS_B2_1", - "MONITOR_LOGIC_OUTS_B2_2", - "MONITOR_LOGIC_OUTS_B2_3", - "MONITOR_LOGIC_OUTS_B2_4", - "MONITOR_LOGIC_OUTS_B3_0", - "MONITOR_LOGIC_OUTS_B3_1", - "MONITOR_LOGIC_OUTS_B3_2", - "MONITOR_LOGIC_OUTS_B3_3", - "MONITOR_LOGIC_OUTS_B3_4", - "MONITOR_LOGIC_OUTS_B4_0", - "MONITOR_LOGIC_OUTS_B4_1", - "MONITOR_LOGIC_OUTS_B4_2", - "MONITOR_LOGIC_OUTS_B4_3", - "MONITOR_LOGIC_OUTS_B4_4", - "MONITOR_LOGIC_OUTS_B5_0", - "MONITOR_LOGIC_OUTS_B5_1", - "MONITOR_LOGIC_OUTS_B5_2", - "MONITOR_LOGIC_OUTS_B5_3", - "MONITOR_LOGIC_OUTS_B5_4", - "MONITOR_LOGIC_OUTS_B6_0", - "MONITOR_LOGIC_OUTS_B6_1", - "MONITOR_LOGIC_OUTS_B6_2", - "MONITOR_LOGIC_OUTS_B6_3", - "MONITOR_LOGIC_OUTS_B6_4", - "MONITOR_LOGIC_OUTS_B7_0", - "MONITOR_LOGIC_OUTS_B7_1", - "MONITOR_LOGIC_OUTS_B7_2", - "MONITOR_LOGIC_OUTS_B7_3", - "MONITOR_LOGIC_OUTS_B7_4", - "MONITOR_LOGIC_OUTS_B8_0", - "MONITOR_LOGIC_OUTS_B8_1", - "MONITOR_LOGIC_OUTS_B8_2", - "MONITOR_LOGIC_OUTS_B8_3", - "MONITOR_LOGIC_OUTS_B8_4", - "MONITOR_LOGIC_OUTS_B9_0", - "MONITOR_LOGIC_OUTS_B9_1", - "MONITOR_LOGIC_OUTS_B9_2", - "MONITOR_LOGIC_OUTS_B9_3", - "MONITOR_LOGIC_OUTS_B9_4", - "MONITOR_NE2A0_0", - "MONITOR_NE2A0_1", - "MONITOR_NE2A0_2", - "MONITOR_NE2A0_3", - "MONITOR_NE2A0_4", - "MONITOR_NE2A1_0", - "MONITOR_NE2A1_1", - "MONITOR_NE2A1_2", - "MONITOR_NE2A1_3", - "MONITOR_NE2A1_4", - "MONITOR_NE2A2_0", - "MONITOR_NE2A2_1", - "MONITOR_NE2A2_2", - "MONITOR_NE2A2_3", - "MONITOR_NE2A2_4", - "MONITOR_NE2A3_0", - "MONITOR_NE2A3_1", - "MONITOR_NE2A3_2", - "MONITOR_NE2A3_3", - "MONITOR_NE2A3_4", - "MONITOR_NE4BEG0_0", - "MONITOR_NE4BEG0_1", - "MONITOR_NE4BEG0_2", - "MONITOR_NE4BEG0_3", - "MONITOR_NE4BEG0_4", - "MONITOR_NE4BEG1_0", - "MONITOR_NE4BEG1_1", - "MONITOR_NE4BEG1_2", - "MONITOR_NE4BEG1_3", - "MONITOR_NE4BEG1_4", - "MONITOR_NE4BEG2_0", - "MONITOR_NE4BEG2_1", - "MONITOR_NE4BEG2_2", - "MONITOR_NE4BEG2_3", - "MONITOR_NE4BEG2_4", - "MONITOR_NE4BEG3_0", - "MONITOR_NE4BEG3_1", - "MONITOR_NE4BEG3_2", - "MONITOR_NE4BEG3_3", - "MONITOR_NE4BEG3_4", - "MONITOR_NE4C0_0", - "MONITOR_NE4C0_1", - "MONITOR_NE4C0_2", - "MONITOR_NE4C0_3", - "MONITOR_NE4C0_4", - "MONITOR_NE4C1_0", - "MONITOR_NE4C1_1", - "MONITOR_NE4C1_2", - "MONITOR_NE4C1_3", - "MONITOR_NE4C1_4", - "MONITOR_NE4C2_0", - "MONITOR_NE4C2_1", - "MONITOR_NE4C2_2", - "MONITOR_NE4C2_3", - "MONITOR_NE4C2_4", - "MONITOR_NE4C3_0", - "MONITOR_NE4C3_1", - "MONITOR_NE4C3_2", - "MONITOR_NE4C3_3", - "MONITOR_NE4C3_4", - "MONITOR_NW2A0_0", - "MONITOR_NW2A0_1", - "MONITOR_NW2A0_2", - "MONITOR_NW2A0_3", - "MONITOR_NW2A0_4", - "MONITOR_NW2A1_0", - "MONITOR_NW2A1_1", - "MONITOR_NW2A1_2", - "MONITOR_NW2A1_3", - "MONITOR_NW2A1_4", - "MONITOR_NW2A2_0", - "MONITOR_NW2A2_1", - "MONITOR_NW2A2_2", - "MONITOR_NW2A2_3", - "MONITOR_NW2A2_4", - "MONITOR_NW2A3_0", - "MONITOR_NW2A3_1", - "MONITOR_NW2A3_2", - "MONITOR_NW2A3_3", - "MONITOR_NW2A3_4", - "MONITOR_NW4A0_0", - "MONITOR_NW4A0_1", - "MONITOR_NW4A0_2", - "MONITOR_NW4A0_3", - "MONITOR_NW4A0_4", - "MONITOR_NW4A1_0", - "MONITOR_NW4A1_1", - "MONITOR_NW4A1_2", - "MONITOR_NW4A1_3", - "MONITOR_NW4A1_4", - "MONITOR_NW4A2_0", - "MONITOR_NW4A2_1", - "MONITOR_NW4A2_2", - "MONITOR_NW4A2_3", - "MONITOR_NW4A2_4", - "MONITOR_NW4A3_0", - "MONITOR_NW4A3_1", - "MONITOR_NW4A3_2", - "MONITOR_NW4A3_3", - "MONITOR_NW4A3_4", - "MONITOR_NW4END0_0", - "MONITOR_NW4END0_1", - "MONITOR_NW4END0_2", - "MONITOR_NW4END0_3", - "MONITOR_NW4END0_4", - "MONITOR_NW4END1_0", - "MONITOR_NW4END1_1", - "MONITOR_NW4END1_2", - "MONITOR_NW4END1_3", - "MONITOR_NW4END1_4", - "MONITOR_NW4END2_0", - "MONITOR_NW4END2_1", - "MONITOR_NW4END2_2", - "MONITOR_NW4END2_3", - "MONITOR_NW4END2_4", - "MONITOR_NW4END3_0", - "MONITOR_NW4END3_1", - "MONITOR_NW4END3_2", - "MONITOR_NW4END3_3", - "MONITOR_NW4END3_4", - "MONITOR_SE2A0_0", - "MONITOR_SE2A0_1", - "MONITOR_SE2A0_2", - "MONITOR_SE2A0_3", - "MONITOR_SE2A0_4", - "MONITOR_SE2A1_0", - "MONITOR_SE2A1_1", - "MONITOR_SE2A1_2", - "MONITOR_SE2A1_3", - "MONITOR_SE2A1_4", - "MONITOR_SE2A2_0", - "MONITOR_SE2A2_1", - "MONITOR_SE2A2_2", - "MONITOR_SE2A2_3", - "MONITOR_SE2A2_4", - "MONITOR_SE2A3_0", - "MONITOR_SE2A3_1", - "MONITOR_SE2A3_2", - "MONITOR_SE2A3_3", - "MONITOR_SE2A3_4", - "MONITOR_SE4BEG0_0", - "MONITOR_SE4BEG0_1", - "MONITOR_SE4BEG0_2", - "MONITOR_SE4BEG0_3", - "MONITOR_SE4BEG0_4", - "MONITOR_SE4BEG1_0", - "MONITOR_SE4BEG1_1", - "MONITOR_SE4BEG1_2", - "MONITOR_SE4BEG1_3", - "MONITOR_SE4BEG1_4", - "MONITOR_SE4BEG2_0", - "MONITOR_SE4BEG2_1", - "MONITOR_SE4BEG2_2", - "MONITOR_SE4BEG2_3", - "MONITOR_SE4BEG2_4", - "MONITOR_SE4BEG3_0", - "MONITOR_SE4BEG3_1", - "MONITOR_SE4BEG3_2", - "MONITOR_SE4BEG3_3", - "MONITOR_SE4BEG3_4", - "MONITOR_SE4C0_0", - "MONITOR_SE4C0_1", - "MONITOR_SE4C0_2", - "MONITOR_SE4C0_3", - "MONITOR_SE4C0_4", - "MONITOR_SE4C1_0", - "MONITOR_SE4C1_1", - "MONITOR_SE4C1_2", - "MONITOR_SE4C1_3", - "MONITOR_SE4C1_4", - "MONITOR_SE4C2_0", - "MONITOR_SE4C2_1", - "MONITOR_SE4C2_2", - "MONITOR_SE4C2_3", - "MONITOR_SE4C2_4", - "MONITOR_SE4C3_0", - "MONITOR_SE4C3_1", - "MONITOR_SE4C3_2", - "MONITOR_SE4C3_3", - "MONITOR_SE4C3_4", - "MONITOR_SW2A0_0", - "MONITOR_SW2A0_1", - "MONITOR_SW2A0_2", - "MONITOR_SW2A0_3", - "MONITOR_SW2A0_4", - "MONITOR_SW2A1_0", - "MONITOR_SW2A1_1", - "MONITOR_SW2A1_2", - "MONITOR_SW2A1_3", - "MONITOR_SW2A1_4", - "MONITOR_SW2A2_0", - "MONITOR_SW2A2_1", - "MONITOR_SW2A2_2", - "MONITOR_SW2A2_3", - "MONITOR_SW2A2_4", - "MONITOR_SW2A3_0", - "MONITOR_SW2A3_1", - "MONITOR_SW2A3_2", - "MONITOR_SW2A3_3", - "MONITOR_SW2A3_4", - "MONITOR_SW4A0_0", - "MONITOR_SW4A0_1", - "MONITOR_SW4A0_2", - "MONITOR_SW4A0_3", - "MONITOR_SW4A0_4", - "MONITOR_SW4A1_0", - "MONITOR_SW4A1_1", - "MONITOR_SW4A1_2", - "MONITOR_SW4A1_3", - "MONITOR_SW4A1_4", - "MONITOR_SW4A2_0", - "MONITOR_SW4A2_1", - "MONITOR_SW4A2_2", - "MONITOR_SW4A2_3", - "MONITOR_SW4A2_4", - "MONITOR_SW4A3_0", - "MONITOR_SW4A3_1", - "MONITOR_SW4A3_2", - "MONITOR_SW4A3_3", - "MONITOR_SW4A3_4", - "MONITOR_SW4END0_0", - "MONITOR_SW4END0_1", - "MONITOR_SW4END0_2", - "MONITOR_SW4END0_3", - "MONITOR_SW4END0_4", - "MONITOR_SW4END1_0", - "MONITOR_SW4END1_1", - "MONITOR_SW4END1_2", - "MONITOR_SW4END1_3", - "MONITOR_SW4END1_4", - "MONITOR_SW4END2_0", - "MONITOR_SW4END2_1", - "MONITOR_SW4END2_2", - "MONITOR_SW4END2_3", - "MONITOR_SW4END2_4", - "MONITOR_SW4END3_0", - "MONITOR_SW4END3_1", - "MONITOR_SW4END3_2", - "MONITOR_SW4END3_3", - "MONITOR_SW4END3_4", - "MONITOR_VERT_SHORT_VAUXN0", - "MONITOR_VERT_SHORT_VAUXN1", - "MONITOR_VERT_SHORT_VAUXN10", - "MONITOR_VERT_SHORT_VAUXN11", - "MONITOR_VERT_SHORT_VAUXN12", - "MONITOR_VERT_SHORT_VAUXN13", - "MONITOR_VERT_SHORT_VAUXN14", - "MONITOR_VERT_SHORT_VAUXN15", - "MONITOR_VERT_SHORT_VAUXN2", - "MONITOR_VERT_SHORT_VAUXN3", - "MONITOR_VERT_SHORT_VAUXN4", - "MONITOR_VERT_SHORT_VAUXN5", - "MONITOR_VERT_SHORT_VAUXN6", - "MONITOR_VERT_SHORT_VAUXN7", - "MONITOR_VERT_SHORT_VAUXN8", - "MONITOR_VERT_SHORT_VAUXN9", - "MONITOR_VERT_SHORT_VAUXP0", - "MONITOR_VERT_SHORT_VAUXP1", - "MONITOR_VERT_SHORT_VAUXP10", - "MONITOR_VERT_SHORT_VAUXP11", - "MONITOR_VERT_SHORT_VAUXP12", - "MONITOR_VERT_SHORT_VAUXP13", - "MONITOR_VERT_SHORT_VAUXP14", - "MONITOR_VERT_SHORT_VAUXP15", - "MONITOR_VERT_SHORT_VAUXP2", - "MONITOR_VERT_SHORT_VAUXP3", - "MONITOR_VERT_SHORT_VAUXP4", - "MONITOR_VERT_SHORT_VAUXP5", - "MONITOR_VERT_SHORT_VAUXP6", - "MONITOR_VERT_SHORT_VAUXP7", - "MONITOR_VERT_SHORT_VAUXP8", - "MONITOR_VERT_SHORT_VAUXP9", - "MONITOR_WL1END0_0", - "MONITOR_WL1END0_1", - "MONITOR_WL1END0_2", - "MONITOR_WL1END0_3", - "MONITOR_WL1END0_4", - "MONITOR_WL1END1_0", - "MONITOR_WL1END1_1", - "MONITOR_WL1END1_2", - "MONITOR_WL1END1_3", - "MONITOR_WL1END1_4", - "MONITOR_WL1END2_0", - "MONITOR_WL1END2_1", - "MONITOR_WL1END2_2", - "MONITOR_WL1END2_3", - "MONITOR_WL1END2_4", - "MONITOR_WL1END3_0", - "MONITOR_WL1END3_1", - "MONITOR_WL1END3_2", - "MONITOR_WL1END3_3", - "MONITOR_WL1END3_4", - "MONITOR_WR1END0_0", - "MONITOR_WR1END0_1", - "MONITOR_WR1END0_2", - "MONITOR_WR1END0_3", - "MONITOR_WR1END0_4", - "MONITOR_WR1END1_0", - "MONITOR_WR1END1_1", - "MONITOR_WR1END1_2", - "MONITOR_WR1END1_3", - "MONITOR_WR1END1_4", - "MONITOR_WR1END2_0", - "MONITOR_WR1END2_1", - "MONITOR_WR1END2_2", - "MONITOR_WR1END2_3", - "MONITOR_WR1END2_4", - "MONITOR_WR1END3_0", - "MONITOR_WR1END3_1", - "MONITOR_WR1END3_2", - "MONITOR_WR1END3_3", - "MONITOR_WR1END3_4", - "MONITOR_WW2A0_0", - "MONITOR_WW2A0_1", - "MONITOR_WW2A0_2", - "MONITOR_WW2A0_3", - "MONITOR_WW2A0_4", - "MONITOR_WW2A1_0", - "MONITOR_WW2A1_1", - "MONITOR_WW2A1_2", - "MONITOR_WW2A1_3", - "MONITOR_WW2A1_4", - "MONITOR_WW2A2_0", - "MONITOR_WW2A2_1", - "MONITOR_WW2A2_2", - "MONITOR_WW2A2_3", - "MONITOR_WW2A2_4", - "MONITOR_WW2A3_0", - "MONITOR_WW2A3_1", - "MONITOR_WW2A3_2", - "MONITOR_WW2A3_3", - "MONITOR_WW2A3_4", - "MONITOR_WW2END0_0", - "MONITOR_WW2END0_1", - "MONITOR_WW2END0_2", - "MONITOR_WW2END0_3", - "MONITOR_WW2END0_4", - "MONITOR_WW2END1_0", - "MONITOR_WW2END1_1", - "MONITOR_WW2END1_2", - "MONITOR_WW2END1_3", - "MONITOR_WW2END1_4", - "MONITOR_WW2END2_0", - "MONITOR_WW2END2_1", - "MONITOR_WW2END2_2", - "MONITOR_WW2END2_3", - "MONITOR_WW2END2_4", - "MONITOR_WW2END3_0", - "MONITOR_WW2END3_1", - "MONITOR_WW2END3_2", - "MONITOR_WW2END3_3", - "MONITOR_WW2END3_4", - "MONITOR_WW4A0_0", - "MONITOR_WW4A0_1", - "MONITOR_WW4A0_2", - "MONITOR_WW4A0_3", - "MONITOR_WW4A0_4", - "MONITOR_WW4A1_0", - "MONITOR_WW4A1_1", - "MONITOR_WW4A1_2", - "MONITOR_WW4A1_3", - "MONITOR_WW4A1_4", - "MONITOR_WW4A2_0", - "MONITOR_WW4A2_1", - "MONITOR_WW4A2_2", - "MONITOR_WW4A2_3", - "MONITOR_WW4A2_4", - "MONITOR_WW4A3_0", - "MONITOR_WW4A3_1", - "MONITOR_WW4A3_2", - "MONITOR_WW4A3_3", - "MONITOR_WW4A3_4", - "MONITOR_WW4B0_0", - "MONITOR_WW4B0_1", - "MONITOR_WW4B0_2", - "MONITOR_WW4B0_3", - "MONITOR_WW4B0_4", - "MONITOR_WW4B1_0", - "MONITOR_WW4B1_1", - "MONITOR_WW4B1_2", - "MONITOR_WW4B1_3", - "MONITOR_WW4B1_4", - "MONITOR_WW4B2_0", - "MONITOR_WW4B2_1", - "MONITOR_WW4B2_2", - "MONITOR_WW4B2_3", - "MONITOR_WW4B2_4", - "MONITOR_WW4B3_0", - "MONITOR_WW4B3_1", - "MONITOR_WW4B3_2", - "MONITOR_WW4B3_3", - "MONITOR_WW4B3_4", - "MONITOR_WW4C0_0", - "MONITOR_WW4C0_1", - "MONITOR_WW4C0_2", - "MONITOR_WW4C0_3", - "MONITOR_WW4C0_4", - "MONITOR_WW4C1_0", - "MONITOR_WW4C1_1", - "MONITOR_WW4C1_2", - "MONITOR_WW4C1_3", - "MONITOR_WW4C1_4", - "MONITOR_WW4C2_0", - "MONITOR_WW4C2_1", - "MONITOR_WW4C2_2", - "MONITOR_WW4C2_3", - "MONITOR_WW4C2_4", - "MONITOR_WW4C3_0", - "MONITOR_WW4C3_1", - "MONITOR_WW4C3_2", - "MONITOR_WW4C3_3", - "MONITOR_WW4C3_4", - "MONITOR_WW4END0_0", - "MONITOR_WW4END0_1", - "MONITOR_WW4END0_2", - "MONITOR_WW4END0_3", - "MONITOR_WW4END0_4", - "MONITOR_WW4END1_0", - "MONITOR_WW4END1_1", - "MONITOR_WW4END1_2", - "MONITOR_WW4END1_3", - "MONITOR_WW4END1_4", - "MONITOR_WW4END2_0", - "MONITOR_WW4END2_1", - "MONITOR_WW4END2_2", - "MONITOR_WW4END2_3", - "MONITOR_WW4END2_4", - "MONITOR_WW4END3_0", - "MONITOR_WW4END3_1", - "MONITOR_WW4END3_2", - "MONITOR_WW4END3_3", - "MONITOR_WW4END3_4" - ] + "wires": { + "MONITOR_BLOCK_OUTS_B0_0": null, + "MONITOR_BLOCK_OUTS_B0_1": null, + "MONITOR_BLOCK_OUTS_B0_2": null, + "MONITOR_BLOCK_OUTS_B0_3": null, + "MONITOR_BLOCK_OUTS_B0_4": null, + "MONITOR_BLOCK_OUTS_B1_0": null, + "MONITOR_BLOCK_OUTS_B1_1": null, + "MONITOR_BLOCK_OUTS_B1_2": null, + "MONITOR_BLOCK_OUTS_B1_3": null, + "MONITOR_BLOCK_OUTS_B1_4": null, + "MONITOR_BLOCK_OUTS_B2_0": null, + "MONITOR_BLOCK_OUTS_B2_1": null, + "MONITOR_BLOCK_OUTS_B2_2": null, + "MONITOR_BLOCK_OUTS_B2_3": null, + "MONITOR_BLOCK_OUTS_B2_4": null, + "MONITOR_BLOCK_OUTS_B3_0": null, + "MONITOR_BLOCK_OUTS_B3_1": null, + "MONITOR_BLOCK_OUTS_B3_2": null, + "MONITOR_BLOCK_OUTS_B3_3": null, + "MONITOR_BLOCK_OUTS_B3_4": null, + "MONITOR_BYP0_0": null, + "MONITOR_BYP0_1": null, + "MONITOR_BYP0_2": null, + "MONITOR_BYP0_3": null, + "MONITOR_BYP0_4": null, + "MONITOR_BYP1_0": null, + "MONITOR_BYP1_1": null, + "MONITOR_BYP1_2": null, + "MONITOR_BYP1_3": null, + "MONITOR_BYP1_4": null, + "MONITOR_BYP2_0": null, + "MONITOR_BYP2_1": null, + "MONITOR_BYP2_2": null, + "MONITOR_BYP2_3": null, + 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"MONITOR_WW4C2_0": null, + "MONITOR_WW4C2_1": null, + "MONITOR_WW4C2_2": null, + "MONITOR_WW4C2_3": null, + "MONITOR_WW4C2_4": null, + "MONITOR_WW4C3_0": null, + "MONITOR_WW4C3_1": null, + "MONITOR_WW4C3_2": null, + "MONITOR_WW4C3_3": null, + "MONITOR_WW4C3_4": null, + "MONITOR_WW4END0_0": null, + "MONITOR_WW4END0_1": null, + "MONITOR_WW4END0_2": null, + "MONITOR_WW4END0_3": null, + "MONITOR_WW4END0_4": null, + "MONITOR_WW4END1_0": null, + "MONITOR_WW4END1_1": null, + "MONITOR_WW4END1_2": null, + "MONITOR_WW4END1_3": null, + "MONITOR_WW4END1_4": null, + "MONITOR_WW4END2_0": null, + "MONITOR_WW4END2_1": null, + "MONITOR_WW4END2_2": null, + "MONITOR_WW4END2_3": null, + "MONITOR_WW4END2_4": null, + "MONITOR_WW4END3_0": null, + "MONITOR_WW4END3_1": null, + "MONITOR_WW4END3_2": null, + "MONITOR_WW4END3_3": null, + "MONITOR_WW4END3_4": null + } } diff --git a/kintex7/tile_type_NULL.json b/kintex7/tile_type_NULL.json index 1c00b3c..11b43a3 100644 --- a/kintex7/tile_type_NULL.json +++ b/kintex7/tile_type_NULL.json @@ -2,7 +2,7 @@ "pips": {}, "sites": [], "tile_type": "NULL", - "wires": [ - "DUMMYFOO" - ] + "wires": { + "DUMMYFOO": null + } } diff --git a/kintex7/tile_type_PCIE_BOT.json b/kintex7/tile_type_PCIE_BOT.json index 6939251..afabecc 100644 --- a/kintex7/tile_type_PCIE_BOT.json +++ b/kintex7/tile_type_PCIE_BOT.json @@ -2,12154 +2,31250 @@ "pips": { "PCIE_BOT.PCIE_CFGAERECRCCHECKEN->PCIE_LOGIC_OUTS_B17_L_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGAERECRCCHECKEN" }, "PCIE_BOT.PCIE_CFGAERECRCGENEN->PCIE_LOGIC_OUTS_B18_L_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGAERECRCGENEN" }, "PCIE_BOT.PCIE_CFGAERROOTERRCORRERRREPORTINGEN->PCIE_LOGIC_OUTS_B19_L_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGAERROOTERRCORRERRREPORTINGEN" }, "PCIE_BOT.PCIE_CFGBRIDGESERREN->PCIE_LOGIC_OUTS_B17_L_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGBRIDGESERREN" }, "PCIE_BOT.PCIE_CFGCOMMANDSERREN->PCIE_LOGIC_OUTS_B16_L_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGCOMMANDSERREN" }, "PCIE_BOT.PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK->PCIE_LOGIC_OUTS_B21_L_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK" }, "PCIE_BOT.PCIE_CFGDEVCONTROLAUXPOWEREN->PCIE_LOGIC_OUTS_B19_L_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLAUXPOWEREN" }, "PCIE_BOT.PCIE_CFGDEVCONTROLCORRERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN" }, "PCIE_BOT.PCIE_CFGDEVCONTROLENABLERO->PCIE_LOGIC_OUTS_B18_L_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLENABLERO" }, "PCIE_BOT.PCIE_CFGDEVCONTROLEXTTAGEN->PCIE_LOGIC_OUTS_B17_L_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLEXTTAGEN" }, "PCIE_BOT.PCIE_CFGDEVCONTROLFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN" }, "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD0->PCIE_LOGIC_OUTS_B19_L_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD0" }, "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD1->PCIE_LOGIC_OUTS_B20_L_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD1" }, "PCIE_BOT.PCIE_CFGDEVCONTROLMAXPAYLOAD2->PCIE_LOGIC_OUTS_B21_L_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLMAXPAYLOAD2" }, "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ0->PCIE_LOGIC_OUTS_B16_L_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ0" }, "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ1->PCIE_LOGIC_OUTS_B17_L_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ1" }, "PCIE_BOT.PCIE_CFGDEVCONTROLMAXREADREQ2->PCIE_LOGIC_OUTS_B18_L_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLMAXREADREQ2" }, "PCIE_BOT.PCIE_CFGDEVCONTROLNONFATALREPORTINGEN->PCIE_LOGIC_OUTS_B21_L_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN" }, "PCIE_BOT.PCIE_CFGDEVCONTROLNOSNOOPEN->PCIE_LOGIC_OUTS_B20_L_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLNOSNOOPEN" }, "PCIE_BOT.PCIE_CFGDEVCONTROLPHANTOMEN->PCIE_LOGIC_OUTS_B18_L_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLPHANTOMEN" }, "PCIE_BOT.PCIE_CFGDEVCONTROLURERRREPORTINGEN->PCIE_LOGIC_OUTS_B21_L_13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVCONTROLURERRREPORTINGEN" }, "PCIE_BOT.PCIE_CFGDEVSTATUSCORRERRDETECTED->PCIE_LOGIC_OUTS_B16_L_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVSTATUSCORRERRDETECTED" }, "PCIE_BOT.PCIE_CFGDEVSTATUSFATALERRDETECTED->PCIE_LOGIC_OUTS_B16_L_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVSTATUSFATALERRDETECTED" }, "PCIE_BOT.PCIE_CFGDEVSTATUSNONFATALERRDETECTED->PCIE_LOGIC_OUTS_B17_L_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED" }, "PCIE_BOT.PCIE_CFGDEVSTATUSURDETECTED->PCIE_LOGIC_OUTS_B17_L_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGDEVSTATUSURDETECTED" }, "PCIE_BOT.PCIE_CFGERRAERHEADERLOGSETN->PCIE_LOGIC_OUTS_B17_R_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGERRAERHEADERLOGSETN" }, "PCIE_BOT.PCIE_CFGERRCPLRDYN->PCIE_LOGIC_OUTS_B14_R_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGERRCPLRDYN" }, "PCIE_BOT.PCIE_CFGINTERRUPTDO0->PCIE_LOGIC_OUTS_B17_L_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGINTERRUPTDO0" }, "PCIE_BOT.PCIE_CFGINTERRUPTDO1->PCIE_LOGIC_OUTS_B12_L_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGINTERRUPTDO1" }, "PCIE_BOT.PCIE_CFGINTERRUPTDO2->PCIE_LOGIC_OUTS_B13_L_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_8", "is_directional": "1", + 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"src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA10" }, "PCIE_BOT.PCIE_CFGMSGDATA11->PCIE_LOGIC_OUTS_B14_L_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA11" }, "PCIE_BOT.PCIE_CFGMSGDATA12->PCIE_LOGIC_OUTS_B16_L_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA12" }, "PCIE_BOT.PCIE_CFGMSGDATA13->PCIE_LOGIC_OUTS_B17_L_14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA13" }, "PCIE_BOT.PCIE_CFGMSGDATA14->PCIE_LOGIC_OUTS_B12_L_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA14" }, "PCIE_BOT.PCIE_CFGMSGDATA15->PCIE_LOGIC_OUTS_B13_L_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA15" }, 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"src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA4" }, "PCIE_BOT.PCIE_CFGMSGDATA5->PCIE_LOGIC_OUTS_B18_L_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA5" }, "PCIE_BOT.PCIE_CFGMSGDATA6->PCIE_LOGIC_OUTS_B16_L_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA6" }, "PCIE_BOT.PCIE_CFGMSGDATA7->PCIE_LOGIC_OUTS_B17_L_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA7" }, "PCIE_BOT.PCIE_CFGMSGDATA8->PCIE_LOGIC_OUTS_B18_L_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA8" }, "PCIE_BOT.PCIE_CFGMSGDATA9->PCIE_LOGIC_OUTS_B19_L_12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGDATA9" }, "PCIE_BOT.PCIE_CFGMSGRECEIVED->PCIE_LOGIC_OUTS_B15_L_9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVED" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTA->PCIE_LOGIC_OUTS_B10_L_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTA" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTB->PCIE_LOGIC_OUTS_B14_L_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTB" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTC->PCIE_LOGIC_OUTS_B17_L_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTC" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDASSERTINTD->PCIE_LOGIC_OUTS_B19_L_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDASSERTINTD" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTA->PCIE_LOGIC_OUTS_B12_L_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTA" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTB->PCIE_LOGIC_OUTS_B15_L_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTB" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTC->PCIE_LOGIC_OUTS_B18_L_17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTC" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDDEASSERTINTD->PCIE_LOGIC_OUTS_B12_L_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDDEASSERTINTD" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRCOR->PCIE_LOGIC_OUTS_B14_L_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDERRCOR" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRFATAL->PCIE_LOGIC_OUTS_B8_L_16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDERRFATAL" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDERRNONFATAL->PCIE_LOGIC_OUTS_B15_L_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDERRNONFATAL" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMASNAK->PCIE_LOGIC_OUTS_B10_L_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDPMASNAK" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETO->PCIE_LOGIC_OUTS_B17_L_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDPMETO" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMETOACK->PCIE_LOGIC_OUTS_B16_L_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDPMETOACK" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDPMPME->PCIE_LOGIC_OUTS_B14_L_18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDPMPME" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT->PCIE_LOGIC_OUTS_B8_L_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT" }, "PCIE_BOT.PCIE_CFGMSGRECEIVEDUNLOCK->PCIE_LOGIC_OUTS_B9_L_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGMSGRECEIVEDUNLOCK" }, "PCIE_BOT.PCIE_CFGPCIELINKSTATE0->PCIE_LOGIC_OUTS_B11_L_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGPCIELINKSTATE0" }, "PCIE_BOT.PCIE_CFGROOTCONTROLPMEINTEN->PCIE_LOGIC_OUTS_B16_L_19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_CFGROOTCONTROLPMEINTEN" }, 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"PCIE_TRNRDLLPDATA9" }, "PCIE_BOT.PCIE_TRNRECRCERR->PCIE_LOGIC_OUTS_B4_R_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_R_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNRECRCERR" }, "PCIE_BOT.PCIE_TRNREOF->PCIE_LOGIC_OUTS_B7_R_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_R_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNREOF" }, "PCIE_BOT.PCIE_TRNRERRFWD->PCIE_LOGIC_OUTS_B5_R_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_R_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNRERRFWD" }, "PCIE_BOT.PCIE_TRNRREM0->PCIE_LOGIC_OUTS_B1_R_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_R_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNRREM0" }, "PCIE_BOT.PCIE_TRNRREM1->PCIE_LOGIC_OUTS_B3_R_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNRREM1" }, "PCIE_BOT.PCIE_TRNRSOF->PCIE_LOGIC_OUTS_B5_R_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_R_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNRSOF" }, "PCIE_BOT.PCIE_TRNRSRCDSC->PCIE_LOGIC_OUTS_B3_R_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNRSRCDSC" }, "PCIE_BOT.PCIE_TRNRSRCRDY->PCIE_LOGIC_OUTS_B0_R_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNRSRCRDY" }, "PCIE_BOT.PCIE_TRNTBUFAV0->PCIE_LOGIC_OUTS_B4_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTBUFAV0" }, "PCIE_BOT.PCIE_TRNTBUFAV1->PCIE_LOGIC_OUTS_B5_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTBUFAV1" }, "PCIE_BOT.PCIE_TRNTBUFAV2->PCIE_LOGIC_OUTS_B1_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTBUFAV2" }, "PCIE_BOT.PCIE_TRNTBUFAV3->PCIE_LOGIC_OUTS_B3_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTBUFAV3" }, "PCIE_BOT.PCIE_TRNTBUFAV4->PCIE_LOGIC_OUTS_B5_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTBUFAV4" }, "PCIE_BOT.PCIE_TRNTBUFAV5->PCIE_LOGIC_OUTS_B7_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTBUFAV5" }, "PCIE_BOT.PCIE_TRNTCFGREQ->PCIE_LOGIC_OUTS_B0_L_5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTCFGREQ" }, "PCIE_BOT.PCIE_TRNTDLLPDSTRDY->PCIE_LOGIC_OUTS_B11_L_11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTDLLPDSTRDY" }, "PCIE_BOT.PCIE_TRNTDSTRDY0->PCIE_LOGIC_OUTS_B1_R_10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_R_10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTDSTRDY0" }, "PCIE_BOT.PCIE_TRNTDSTRDY1->PCIE_LOGIC_OUTS_B1_R_15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_R_15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTDSTRDY1" }, "PCIE_BOT.PCIE_TRNTDSTRDY2->PCIE_LOGIC_OUTS_B3_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTDSTRDY2" }, "PCIE_BOT.PCIE_TRNTERRDROP->PCIE_LOGIC_OUTS_B2_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TRNTERRDROP" }, "PCIE_BOT.PCIE_USERRSTN->PCIE_LOGIC_OUTS_B12_R_8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_USERRSTN" } }, @@ -12158,2255 +31254,22496 @@ "name": "X0Y0", "prefix": "PCIE", "site_pins": { - "CFGAERECRCCHECKEN": "PCIE_CFGAERECRCCHECKEN", - "CFGAERECRCGENEN": "PCIE_CFGAERECRCGENEN", - "CFGAERINTERRUPTMSGNUM0": "PCIE_CFGAERINTERRUPTMSGNUM0", - "CFGAERINTERRUPTMSGNUM1": "PCIE_CFGAERINTERRUPTMSGNUM1", - "CFGAERINTERRUPTMSGNUM2": "PCIE_CFGAERINTERRUPTMSGNUM2", - "CFGAERINTERRUPTMSGNUM3": "PCIE_CFGAERINTERRUPTMSGNUM3", - "CFGAERINTERRUPTMSGNUM4": "PCIE_CFGAERINTERRUPTMSGNUM4", - "CFGAERROOTERRCORRERRRECEIVED": "PCIE_CFGAERROOTERRCORRERRRECEIVED", - "CFGAERROOTERRCORRERRREPORTINGEN": "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", - "CFGAERROOTERRFATALERRRECEIVED": "PCIE_CFGAERROOTERRFATALERRRECEIVED", - "CFGAERROOTERRFATALERRREPORTINGEN": "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", - "CFGAERROOTERRNONFATALERRRECEIVED": "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", - "CFGAERROOTERRNONFATALERRREPORTINGEN": "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", - "CFGBRIDGESERREN": "PCIE_CFGBRIDGESERREN", - "CFGCOMMANDBUSMASTERENABLE": "PCIE_CFGCOMMANDBUSMASTERENABLE", - "CFGCOMMANDINTERRUPTDISABLE": "PCIE_CFGCOMMANDINTERRUPTDISABLE", - "CFGCOMMANDIOENABLE": "PCIE_CFGCOMMANDIOENABLE", - "CFGCOMMANDMEMENABLE": "PCIE_CFGCOMMANDMEMENABLE", - "CFGCOMMANDSERREN": "PCIE_CFGCOMMANDSERREN", - "CFGDEVCONTROL2ARIFORWARDEN": "PCIE_CFGDEVCONTROL2ARIFORWARDEN", - "CFGDEVCONTROL2ATOMICEGRESSBLOCK": "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", - "CFGDEVCONTROL2ATOMICREQUESTEREN": "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", - "CFGDEVCONTROL2CPLTIMEOUTDIS": "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", - "CFGDEVCONTROL2CPLTIMEOUTVAL0": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", - "CFGDEVCONTROL2CPLTIMEOUTVAL1": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", - "CFGDEVCONTROL2CPLTIMEOUTVAL2": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", - "CFGDEVCONTROL2CPLTIMEOUTVAL3": "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", - "CFGDEVCONTROL2IDOCPLEN": "PCIE_CFGDEVCONTROL2IDOCPLEN", - "CFGDEVCONTROL2IDOREQEN": "PCIE_CFGDEVCONTROL2IDOREQEN", - "CFGDEVCONTROL2LTREN": "PCIE_CFGDEVCONTROL2LTREN", - "CFGDEVCONTROL2TLPPREFIXBLOCK": "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", - "CFGDEVCONTROLAUXPOWEREN": "PCIE_CFGDEVCONTROLAUXPOWEREN", - "CFGDEVCONTROLCORRERRREPORTINGEN": "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", - "CFGDEVCONTROLENABLERO": "PCIE_CFGDEVCONTROLENABLERO", - "CFGDEVCONTROLEXTTAGEN": "PCIE_CFGDEVCONTROLEXTTAGEN", - "CFGDEVCONTROLFATALERRREPORTINGEN": "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", - "CFGDEVCONTROLMAXPAYLOAD0": "PCIE_CFGDEVCONTROLMAXPAYLOAD0", - "CFGDEVCONTROLMAXPAYLOAD1": "PCIE_CFGDEVCONTROLMAXPAYLOAD1", - "CFGDEVCONTROLMAXPAYLOAD2": "PCIE_CFGDEVCONTROLMAXPAYLOAD2", - "CFGDEVCONTROLMAXREADREQ0": "PCIE_CFGDEVCONTROLMAXREADREQ0", - "CFGDEVCONTROLMAXREADREQ1": "PCIE_CFGDEVCONTROLMAXREADREQ1", - "CFGDEVCONTROLMAXREADREQ2": "PCIE_CFGDEVCONTROLMAXREADREQ2", - "CFGDEVCONTROLNONFATALREPORTINGEN": "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", - "CFGDEVCONTROLNOSNOOPEN": "PCIE_CFGDEVCONTROLNOSNOOPEN", - "CFGDEVCONTROLPHANTOMEN": "PCIE_CFGDEVCONTROLPHANTOMEN", - "CFGDEVCONTROLURERRREPORTINGEN": "PCIE_CFGDEVCONTROLURERRREPORTINGEN", - "CFGDEVID0": "PCIE_CFGDEVID0", - "CFGDEVID1": "PCIE_CFGDEVID1", - "CFGDEVID10": "PCIE_CFGDEVID10", - "CFGDEVID11": "PCIE_CFGDEVID11", - "CFGDEVID12": "PCIE_CFGDEVID12", - "CFGDEVID13": "PCIE_CFGDEVID13", - "CFGDEVID14": "PCIE_CFGDEVID14", - "CFGDEVID15": "PCIE_CFGDEVID15", - "CFGDEVID2": "PCIE_CFGDEVID2", - "CFGDEVID3": "PCIE_CFGDEVID3", - "CFGDEVID4": "PCIE_CFGDEVID4", - "CFGDEVID5": "PCIE_CFGDEVID5", - "CFGDEVID6": "PCIE_CFGDEVID6", - "CFGDEVID7": "PCIE_CFGDEVID7", - "CFGDEVID8": "PCIE_CFGDEVID8", - "CFGDEVID9": "PCIE_CFGDEVID9", - "CFGDEVSTATUSCORRERRDETECTED": "PCIE_CFGDEVSTATUSCORRERRDETECTED", - "CFGDEVSTATUSFATALERRDETECTED": "PCIE_CFGDEVSTATUSFATALERRDETECTED", - "CFGDEVSTATUSNONFATALERRDETECTED": "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", - "CFGDEVSTATUSURDETECTED": "PCIE_CFGDEVSTATUSURDETECTED", - "CFGDSBUSNUMBER0": "PCIE_CFGDSBUSNUMBER0", - "CFGDSBUSNUMBER1": "PCIE_CFGDSBUSNUMBER1", - "CFGDSBUSNUMBER2": "PCIE_CFGDSBUSNUMBER2", - "CFGDSBUSNUMBER3": "PCIE_CFGDSBUSNUMBER3", - "CFGDSBUSNUMBER4": "PCIE_CFGDSBUSNUMBER4", - "CFGDSBUSNUMBER5": "PCIE_CFGDSBUSNUMBER5", - "CFGDSBUSNUMBER6": "PCIE_CFGDSBUSNUMBER6", - "CFGDSBUSNUMBER7": "PCIE_CFGDSBUSNUMBER7", - "CFGDSDEVICENUMBER0": "PCIE_CFGDSDEVICENUMBER0", - "CFGDSDEVICENUMBER1": "PCIE_CFGDSDEVICENUMBER1", - "CFGDSDEVICENUMBER2": "PCIE_CFGDSDEVICENUMBER2", - "CFGDSDEVICENUMBER3": "PCIE_CFGDSDEVICENUMBER3", - "CFGDSDEVICENUMBER4": "PCIE_CFGDSDEVICENUMBER4", - "CFGDSFUNCTIONNUMBER0": "PCIE_CFGDSFUNCTIONNUMBER0", - "CFGDSFUNCTIONNUMBER1": "PCIE_CFGDSFUNCTIONNUMBER1", - "CFGDSFUNCTIONNUMBER2": "PCIE_CFGDSFUNCTIONNUMBER2", - "CFGDSN0": "PCIE_CFGDSN0", - "CFGDSN1": "PCIE_CFGDSN1", - "CFGDSN10": "PCIE_CFGDSN10", - "CFGDSN11": "PCIE_CFGDSN11", - "CFGDSN12": "PCIE_CFGDSN12", - "CFGDSN13": "PCIE_CFGDSN13", - "CFGDSN14": "PCIE_CFGDSN14", - "CFGDSN15": "PCIE_CFGDSN15", - "CFGDSN16": "PCIE_CFGDSN16", - "CFGDSN17": "PCIE_CFGDSN17", - "CFGDSN18": "PCIE_CFGDSN18", - "CFGDSN19": "PCIE_CFGDSN19", - "CFGDSN2": "PCIE_CFGDSN2", - "CFGDSN20": "PCIE_CFGDSN20", - "CFGDSN21": "PCIE_CFGDSN21", - "CFGDSN22": "PCIE_CFGDSN22", - "CFGDSN23": "PCIE_CFGDSN23", - "CFGDSN24": "PCIE_CFGDSN24", - "CFGDSN25": "PCIE_CFGDSN25", - "CFGDSN26": "PCIE_CFGDSN26", - "CFGDSN27": "PCIE_CFGDSN27", - "CFGDSN28": "PCIE_CFGDSN28", - "CFGDSN29": "PCIE_CFGDSN29", - "CFGDSN3": "PCIE_CFGDSN3", - "CFGDSN30": "PCIE_CFGDSN30", - "CFGDSN31": "PCIE_CFGDSN31", - "CFGDSN32": "PCIE_CFGDSN32", - "CFGDSN33": "PCIE_CFGDSN33", - "CFGDSN34": "PCIE_CFGDSN34", - "CFGDSN35": "PCIE_CFGDSN35", - "CFGDSN36": "PCIE_CFGDSN36", - "CFGDSN37": "PCIE_CFGDSN37", - "CFGDSN38": "PCIE_CFGDSN38", - "CFGDSN39": "PCIE_CFGDSN39", - "CFGDSN4": "PCIE_CFGDSN4", - "CFGDSN40": "PCIE_CFGDSN40", - "CFGDSN41": "PCIE_CFGDSN41", - "CFGDSN42": "PCIE_CFGDSN42", - "CFGDSN43": "PCIE_CFGDSN43", - "CFGDSN44": "PCIE_CFGDSN44", - "CFGDSN45": "PCIE_CFGDSN45", - "CFGDSN46": "PCIE_CFGDSN46", - "CFGDSN47": "PCIE_CFGDSN47", - "CFGDSN48": "PCIE_CFGDSN48", - "CFGDSN49": "PCIE_CFGDSN49", - "CFGDSN5": "PCIE_CFGDSN5", - "CFGDSN50": "PCIE_CFGDSN50", - "CFGDSN51": "PCIE_CFGDSN51", - "CFGDSN52": "PCIE_CFGDSN52", - "CFGDSN53": "PCIE_CFGDSN53", - "CFGDSN54": "PCIE_CFGDSN54", - "CFGDSN55": "PCIE_CFGDSN55", - "CFGDSN56": "PCIE_CFGDSN56", - "CFGDSN57": "PCIE_CFGDSN57", - "CFGDSN58": "PCIE_CFGDSN58", - "CFGDSN59": "PCIE_CFGDSN59", - "CFGDSN6": "PCIE_CFGDSN6", - "CFGDSN60": "PCIE_CFGDSN60", - "CFGDSN61": "PCIE_CFGDSN61", - "CFGDSN62": "PCIE_CFGDSN62", - "CFGDSN63": "PCIE_CFGDSN63", - "CFGDSN7": "PCIE_CFGDSN7", - "CFGDSN8": "PCIE_CFGDSN8", - "CFGDSN9": "PCIE_CFGDSN9", - "CFGERRACSN": "PCIE_CFGERRACSN", - "CFGERRAERHEADERLOG0": "PCIE_CFGERRAERHEADERLOG0", - "CFGERRAERHEADERLOG1": "PCIE_CFGERRAERHEADERLOG1", - "CFGERRAERHEADERLOG10": "PCIE_CFGERRAERHEADERLOG10", - "CFGERRAERHEADERLOG100": "PCIE_CFGERRAERHEADERLOG100", - "CFGERRAERHEADERLOG101": "PCIE_CFGERRAERHEADERLOG101", - "CFGERRAERHEADERLOG102": "PCIE_CFGERRAERHEADERLOG102", - "CFGERRAERHEADERLOG103": "PCIE_CFGERRAERHEADERLOG103", - "CFGERRAERHEADERLOG104": "PCIE_CFGERRAERHEADERLOG104", - "CFGERRAERHEADERLOG105": "PCIE_CFGERRAERHEADERLOG105", - "CFGERRAERHEADERLOG106": "PCIE_CFGERRAERHEADERLOG106", - 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"PCIE_CFGERRINTERNALCORN", - "CFGERRINTERNALUNCORN": "PCIE_CFGERRINTERNALUNCORN", - "CFGERRLOCKEDN": "PCIE_CFGERRLOCKEDN", - "CFGERRMALFORMEDN": "PCIE_CFGERRMALFORMEDN", - "CFGERRMCBLOCKEDN": "PCIE_CFGERRMCBLOCKEDN", - "CFGERRNORECOVERYN": "PCIE_CFGERRNORECOVERYN", - "CFGERRPOISONEDN": "PCIE_CFGERRPOISONEDN", - "CFGERRPOSTEDN": "PCIE_CFGERRPOSTEDN", - "CFGERRTLPCPLHEADER0": "PCIE_CFGERRTLPCPLHEADER0", - "CFGERRTLPCPLHEADER1": "PCIE_CFGERRTLPCPLHEADER1", - "CFGERRTLPCPLHEADER10": "PCIE_CFGERRTLPCPLHEADER10", - "CFGERRTLPCPLHEADER11": "PCIE_CFGERRTLPCPLHEADER11", - "CFGERRTLPCPLHEADER12": "PCIE_CFGERRTLPCPLHEADER12", - "CFGERRTLPCPLHEADER13": "PCIE_CFGERRTLPCPLHEADER13", - "CFGERRTLPCPLHEADER14": "PCIE_CFGERRTLPCPLHEADER14", - "CFGERRTLPCPLHEADER15": "PCIE_CFGERRTLPCPLHEADER15", - "CFGERRTLPCPLHEADER16": "PCIE_CFGERRTLPCPLHEADER16", - "CFGERRTLPCPLHEADER17": "PCIE_CFGERRTLPCPLHEADER17", - "CFGERRTLPCPLHEADER18": "PCIE_CFGERRTLPCPLHEADER18", - "CFGERRTLPCPLHEADER19": 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"PCIE_CFGERRTLPCPLHEADER9", - "CFGERRURN": "PCIE_CFGERRURN", - "CFGFORCECOMMONCLOCKOFF": "PCIE_CFGFORCECOMMONCLOCKOFF", - "CFGFORCEEXTENDEDSYNCON": "PCIE_CFGFORCEEXTENDEDSYNCON", - "CFGFORCEMPS0": "PCIE_CFGFORCEMPS0", - "CFGFORCEMPS1": "PCIE_CFGFORCEMPS1", - "CFGFORCEMPS2": "PCIE_CFGFORCEMPS2", - "CFGINTERRUPTASSERTN": "PCIE_CFGINTERRUPTASSERTN", - "CFGINTERRUPTDI0": "PCIE_CFGINTERRUPTDI0", - "CFGINTERRUPTDI1": "PCIE_CFGINTERRUPTDI1", - "CFGINTERRUPTDI2": "PCIE_CFGINTERRUPTDI2", - "CFGINTERRUPTDI3": "PCIE_CFGINTERRUPTDI3", - "CFGINTERRUPTDI4": "PCIE_CFGINTERRUPTDI4", - "CFGINTERRUPTDI5": "PCIE_CFGINTERRUPTDI5", - "CFGINTERRUPTDI6": "PCIE_CFGINTERRUPTDI6", - "CFGINTERRUPTDI7": "PCIE_CFGINTERRUPTDI7", - "CFGINTERRUPTDO0": "PCIE_CFGINTERRUPTDO0", - "CFGINTERRUPTDO1": "PCIE_CFGINTERRUPTDO1", - "CFGINTERRUPTDO2": "PCIE_CFGINTERRUPTDO2", - "CFGINTERRUPTDO3": "PCIE_CFGINTERRUPTDO3", - "CFGINTERRUPTDO4": "PCIE_CFGINTERRUPTDO4", - "CFGINTERRUPTDO5": "PCIE_CFGINTERRUPTDO5", - "CFGINTERRUPTDO6": "PCIE_CFGINTERRUPTDO6", - "CFGINTERRUPTDO7": "PCIE_CFGINTERRUPTDO7", - "CFGINTERRUPTMMENABLE0": "PCIE_CFGINTERRUPTMMENABLE0", - "CFGINTERRUPTMMENABLE1": "PCIE_CFGINTERRUPTMMENABLE1", - "CFGINTERRUPTMMENABLE2": "PCIE_CFGINTERRUPTMMENABLE2", - "CFGINTERRUPTMSIENABLE": "PCIE_CFGINTERRUPTMSIENABLE", - "CFGINTERRUPTMSIXENABLE": "PCIE_CFGINTERRUPTMSIXENABLE", - "CFGINTERRUPTMSIXFM": "PCIE_CFGINTERRUPTMSIXFM", - "CFGINTERRUPTN": "PCIE_CFGINTERRUPTN", - "CFGINTERRUPTRDYN": "PCIE_CFGINTERRUPTRDYN", - "CFGINTERRUPTSTATN": "PCIE_CFGINTERRUPTSTATN", - "CFGLINKCONTROLASPMCONTROL0": "PCIE_CFGLINKCONTROLASPMCONTROL0", - "CFGLINKCONTROLASPMCONTROL1": "PCIE_CFGLINKCONTROLASPMCONTROL1", - "CFGLINKCONTROLAUTOBANDWIDTHINTEN": "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", - "CFGLINKCONTROLBANDWIDTHINTEN": "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", - "CFGLINKCONTROLCLOCKPMEN": "PCIE_CFGLINKCONTROLCLOCKPMEN", - "CFGLINKCONTROLCOMMONCLOCK": "PCIE_CFGLINKCONTROLCOMMONCLOCK", - "CFGLINKCONTROLEXTENDEDSYNC": "PCIE_CFGLINKCONTROLEXTENDEDSYNC", - "CFGLINKCONTROLHWAUTOWIDTHDIS": "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", - "CFGLINKCONTROLLINKDISABLE": "PCIE_CFGLINKCONTROLLINKDISABLE", - "CFGLINKCONTROLRCB": "PCIE_CFGLINKCONTROLRCB", - "CFGLINKCONTROLRETRAINLINK": "PCIE_CFGLINKCONTROLRETRAINLINK", - "CFGLINKSTATUSAUTOBANDWIDTHSTATUS": "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", - "CFGLINKSTATUSBANDWIDTHSTATUS": "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", - "CFGLINKSTATUSCURRENTSPEED0": "PCIE_CFGLINKSTATUSCURRENTSPEED0", - "CFGLINKSTATUSCURRENTSPEED1": "PCIE_CFGLINKSTATUSCURRENTSPEED1", - "CFGLINKSTATUSDLLACTIVE": "PCIE_CFGLINKSTATUSDLLACTIVE", - "CFGLINKSTATUSLINKTRAINING": "PCIE_CFGLINKSTATUSLINKTRAINING", - "CFGLINKSTATUSNEGOTIATEDWIDTH0": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", - "CFGLINKSTATUSNEGOTIATEDWIDTH1": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", - "CFGLINKSTATUSNEGOTIATEDWIDTH2": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", - "CFGLINKSTATUSNEGOTIATEDWIDTH3": "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", - "CFGMGMTBYTEENN0": "PCIE_CFGMGMTBYTEENN0", - "CFGMGMTBYTEENN1": "PCIE_CFGMGMTBYTEENN1", - "CFGMGMTBYTEENN2": "PCIE_CFGMGMTBYTEENN2", - "CFGMGMTBYTEENN3": "PCIE_CFGMGMTBYTEENN3", - "CFGMGMTDI0": "PCIE_CFGMGMTDI0", - "CFGMGMTDI1": "PCIE_CFGMGMTDI1", - "CFGMGMTDI10": "PCIE_CFGMGMTDI10", - "CFGMGMTDI11": "PCIE_CFGMGMTDI11", - "CFGMGMTDI12": "PCIE_CFGMGMTDI12", - "CFGMGMTDI13": "PCIE_CFGMGMTDI13", - "CFGMGMTDI14": "PCIE_CFGMGMTDI14", - "CFGMGMTDI15": "PCIE_CFGMGMTDI15", - "CFGMGMTDI16": "PCIE_CFGMGMTDI16", - "CFGMGMTDI17": "PCIE_CFGMGMTDI17", - "CFGMGMTDI18": "PCIE_CFGMGMTDI18", - "CFGMGMTDI19": "PCIE_CFGMGMTDI19", - "CFGMGMTDI2": "PCIE_CFGMGMTDI2", - "CFGMGMTDI20": "PCIE_CFGMGMTDI20", - "CFGMGMTDI21": "PCIE_CFGMGMTDI21", - "CFGMGMTDI22": "PCIE_CFGMGMTDI22", - "CFGMGMTDI23": "PCIE_CFGMGMTDI23", - "CFGMGMTDI24": "PCIE_CFGMGMTDI24", - "CFGMGMTDI25": "PCIE_CFGMGMTDI25", - "CFGMGMTDI26": "PCIE_CFGMGMTDI26", - "CFGMGMTDI27": "PCIE_CFGMGMTDI27", - "CFGMGMTDI28": "PCIE_CFGMGMTDI28", - "CFGMGMTDI29": "PCIE_CFGMGMTDI29", - "CFGMGMTDI3": "PCIE_CFGMGMTDI3", - "CFGMGMTDI30": "PCIE_CFGMGMTDI30", - "CFGMGMTDI31": "PCIE_CFGMGMTDI31", - "CFGMGMTDI4": "PCIE_CFGMGMTDI4", - "CFGMGMTDI5": "PCIE_CFGMGMTDI5", - "CFGMGMTDI6": "PCIE_CFGMGMTDI6", - "CFGMGMTDI7": "PCIE_CFGMGMTDI7", - "CFGMGMTDI8": "PCIE_CFGMGMTDI8", - "CFGMGMTDI9": "PCIE_CFGMGMTDI9", - "CFGMGMTDO0": "PCIE_CFGMGMTDO0", - "CFGMGMTDO1": "PCIE_CFGMGMTDO1", - "CFGMGMTDO10": "PCIE_CFGMGMTDO10", - "CFGMGMTDO11": "PCIE_CFGMGMTDO11", - "CFGMGMTDO12": "PCIE_CFGMGMTDO12", - "CFGMGMTDO13": "PCIE_CFGMGMTDO13", - "CFGMGMTDO14": "PCIE_CFGMGMTDO14", - "CFGMGMTDO15": "PCIE_CFGMGMTDO15", - "CFGMGMTDO16": "PCIE_CFGMGMTDO16", - "CFGMGMTDO17": "PCIE_CFGMGMTDO17", - "CFGMGMTDO18": "PCIE_CFGMGMTDO18", - "CFGMGMTDO19": "PCIE_CFGMGMTDO19", - "CFGMGMTDO2": "PCIE_CFGMGMTDO2", - "CFGMGMTDO20": "PCIE_CFGMGMTDO20", - "CFGMGMTDO21": "PCIE_CFGMGMTDO21", - "CFGMGMTDO22": "PCIE_CFGMGMTDO22", - "CFGMGMTDO23": "PCIE_CFGMGMTDO23", - "CFGMGMTDO24": "PCIE_CFGMGMTDO24", - "CFGMGMTDO25": "PCIE_CFGMGMTDO25", - "CFGMGMTDO26": "PCIE_CFGMGMTDO26", - "CFGMGMTDO27": "PCIE_CFGMGMTDO27", - "CFGMGMTDO28": "PCIE_CFGMGMTDO28", - "CFGMGMTDO29": "PCIE_CFGMGMTDO29", - "CFGMGMTDO3": "PCIE_CFGMGMTDO3", - "CFGMGMTDO30": "PCIE_CFGMGMTDO30", - "CFGMGMTDO31": "PCIE_CFGMGMTDO31", - "CFGMGMTDO4": "PCIE_CFGMGMTDO4", - "CFGMGMTDO5": "PCIE_CFGMGMTDO5", - "CFGMGMTDO6": "PCIE_CFGMGMTDO6", - "CFGMGMTDO7": "PCIE_CFGMGMTDO7", - "CFGMGMTDO8": "PCIE_CFGMGMTDO8", - "CFGMGMTDO9": "PCIE_CFGMGMTDO9", - "CFGMGMTDWADDR0": "PCIE_CFGMGMTDWADDR0", - "CFGMGMTDWADDR1": "PCIE_CFGMGMTDWADDR1", - "CFGMGMTDWADDR2": "PCIE_CFGMGMTDWADDR2", - "CFGMGMTDWADDR3": "PCIE_CFGMGMTDWADDR3", - "CFGMGMTDWADDR4": "PCIE_CFGMGMTDWADDR4", - "CFGMGMTDWADDR5": "PCIE_CFGMGMTDWADDR5", - "CFGMGMTDWADDR6": "PCIE_CFGMGMTDWADDR6", - "CFGMGMTDWADDR7": "PCIE_CFGMGMTDWADDR7", - "CFGMGMTDWADDR8": "PCIE_CFGMGMTDWADDR8", - "CFGMGMTDWADDR9": "PCIE_CFGMGMTDWADDR9", - "CFGMGMTRDENN": "PCIE_CFGMGMTRDENN", - "CFGMGMTRDWRDONEN": "PCIE_CFGMGMTRDWRDONEN", - "CFGMGMTWRENN": "PCIE_CFGMGMTWRENN", - "CFGMGMTWRREADONLYN": "PCIE_CFGMGMTWRREADONLYN", - "CFGMGMTWRRW1CASRWN": "PCIE_CFGMGMTWRRW1CASRWN", - "CFGMSGDATA0": "PCIE_CFGMSGDATA0", - "CFGMSGDATA1": "PCIE_CFGMSGDATA1", - "CFGMSGDATA10": "PCIE_CFGMSGDATA10", - "CFGMSGDATA11": "PCIE_CFGMSGDATA11", - "CFGMSGDATA12": "PCIE_CFGMSGDATA12", - "CFGMSGDATA13": "PCIE_CFGMSGDATA13", - "CFGMSGDATA14": "PCIE_CFGMSGDATA14", - "CFGMSGDATA15": "PCIE_CFGMSGDATA15", - "CFGMSGDATA2": "PCIE_CFGMSGDATA2", - "CFGMSGDATA3": "PCIE_CFGMSGDATA3", - "CFGMSGDATA4": "PCIE_CFGMSGDATA4", - "CFGMSGDATA5": "PCIE_CFGMSGDATA5", - "CFGMSGDATA6": "PCIE_CFGMSGDATA6", - "CFGMSGDATA7": "PCIE_CFGMSGDATA7", - "CFGMSGDATA8": "PCIE_CFGMSGDATA8", - "CFGMSGDATA9": "PCIE_CFGMSGDATA9", - "CFGMSGRECEIVED": "PCIE_CFGMSGRECEIVED", - "CFGMSGRECEIVEDASSERTINTA": "PCIE_CFGMSGRECEIVEDASSERTINTA", - "CFGMSGRECEIVEDASSERTINTB": "PCIE_CFGMSGRECEIVEDASSERTINTB", - "CFGMSGRECEIVEDASSERTINTC": "PCIE_CFGMSGRECEIVEDASSERTINTC", - "CFGMSGRECEIVEDASSERTINTD": "PCIE_CFGMSGRECEIVEDASSERTINTD", - "CFGMSGRECEIVEDDEASSERTINTA": "PCIE_CFGMSGRECEIVEDDEASSERTINTA", - "CFGMSGRECEIVEDDEASSERTINTB": "PCIE_CFGMSGRECEIVEDDEASSERTINTB", - "CFGMSGRECEIVEDDEASSERTINTC": "PCIE_CFGMSGRECEIVEDDEASSERTINTC", - "CFGMSGRECEIVEDDEASSERTINTD": "PCIE_CFGMSGRECEIVEDDEASSERTINTD", - "CFGMSGRECEIVEDERRCOR": "PCIE_CFGMSGRECEIVEDERRCOR", - "CFGMSGRECEIVEDERRFATAL": "PCIE_CFGMSGRECEIVEDERRFATAL", - "CFGMSGRECEIVEDERRNONFATAL": "PCIE_CFGMSGRECEIVEDERRNONFATAL", - "CFGMSGRECEIVEDPMASNAK": "PCIE_CFGMSGRECEIVEDPMASNAK", - "CFGMSGRECEIVEDPMETO": "PCIE_CFGMSGRECEIVEDPMETO", - "CFGMSGRECEIVEDPMETOACK": "PCIE_CFGMSGRECEIVEDPMETOACK", - "CFGMSGRECEIVEDPMPME": "PCIE_CFGMSGRECEIVEDPMPME", - "CFGMSGRECEIVEDSETSLOTPOWERLIMIT": "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", - "CFGMSGRECEIVEDUNLOCK": "PCIE_CFGMSGRECEIVEDUNLOCK", - "CFGPCIECAPINTERRUPTMSGNUM0": "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", - "CFGPCIECAPINTERRUPTMSGNUM1": "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", - "CFGPCIECAPINTERRUPTMSGNUM2": "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", - "CFGPCIECAPINTERRUPTMSGNUM3": "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", - "CFGPCIECAPINTERRUPTMSGNUM4": "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", - "CFGPCIELINKSTATE0": "PCIE_CFGPCIELINKSTATE0", - "CFGPCIELINKSTATE1": "PCIE_CFGPCIELINKSTATE1", - "CFGPCIELINKSTATE2": "PCIE_CFGPCIELINKSTATE2", - "CFGPMCSRPMEEN": "PCIE_CFGPMCSRPMEEN", - "CFGPMCSRPMESTATUS": "PCIE_CFGPMCSRPMESTATUS", - "CFGPMCSRPOWERSTATE0": "PCIE_CFGPMCSRPOWERSTATE0", - "CFGPMCSRPOWERSTATE1": "PCIE_CFGPMCSRPOWERSTATE1", - "CFGPMFORCESTATE0": "PCIE_CFGPMFORCESTATE0", - "CFGPMFORCESTATE1": "PCIE_CFGPMFORCESTATE1", - "CFGPMFORCESTATEENN": "PCIE_CFGPMFORCESTATEENN", - "CFGPMHALTASPML0SN": "PCIE_CFGPMHALTASPML0SN", - "CFGPMHALTASPML1N": "PCIE_CFGPMHALTASPML1N", - "CFGPMRCVASREQL1N": "PCIE_CFGPMRCVASREQL1N", - "CFGPMRCVENTERL1N": "PCIE_CFGPMRCVENTERL1N", - "CFGPMRCVENTERL23N": "PCIE_CFGPMRCVENTERL23N", - "CFGPMRCVREQACKN": "PCIE_CFGPMRCVREQACKN", - "CFGPMSENDPMETON": "PCIE_CFGPMSENDPMETON", - "CFGPMTURNOFFOKN": "PCIE_CFGPMTURNOFFOKN", - "CFGPMWAKEN": "PCIE_CFGPMWAKEN", - "CFGPORTNUMBER0": "PCIE_CFGPORTNUMBER0", - "CFGPORTNUMBER1": "PCIE_CFGPORTNUMBER1", - "CFGPORTNUMBER2": "PCIE_CFGPORTNUMBER2", - "CFGPORTNUMBER3": "PCIE_CFGPORTNUMBER3", - "CFGPORTNUMBER4": "PCIE_CFGPORTNUMBER4", - "CFGPORTNUMBER5": "PCIE_CFGPORTNUMBER5", - "CFGPORTNUMBER6": "PCIE_CFGPORTNUMBER6", - "CFGPORTNUMBER7": "PCIE_CFGPORTNUMBER7", - "CFGREVID0": "PCIE_CFGREVID0", - "CFGREVID1": "PCIE_CFGREVID1", - "CFGREVID2": "PCIE_CFGREVID2", - "CFGREVID3": "PCIE_CFGREVID3", - "CFGREVID4": "PCIE_CFGREVID4", - "CFGREVID5": "PCIE_CFGREVID5", - "CFGREVID6": "PCIE_CFGREVID6", - "CFGREVID7": "PCIE_CFGREVID7", - "CFGROOTCONTROLPMEINTEN": "PCIE_CFGROOTCONTROLPMEINTEN", - "CFGROOTCONTROLSYSERRCORRERREN": "PCIE_CFGROOTCONTROLSYSERRCORRERREN", - "CFGROOTCONTROLSYSERRFATALERREN": "PCIE_CFGROOTCONTROLSYSERRFATALERREN", - "CFGROOTCONTROLSYSERRNONFATALERREN": "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", - "CFGSLOTCONTROLELECTROMECHILCTLPULSE": "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", - "CFGSUBSYSID0": "PCIE_CFGSUBSYSID0", - "CFGSUBSYSID1": "PCIE_CFGSUBSYSID1", - "CFGSUBSYSID10": "PCIE_CFGSUBSYSID10", - "CFGSUBSYSID11": "PCIE_CFGSUBSYSID11", - "CFGSUBSYSID12": "PCIE_CFGSUBSYSID12", - "CFGSUBSYSID13": "PCIE_CFGSUBSYSID13", - "CFGSUBSYSID14": "PCIE_CFGSUBSYSID14", - "CFGSUBSYSID15": "PCIE_CFGSUBSYSID15", - "CFGSUBSYSID2": "PCIE_CFGSUBSYSID2", - "CFGSUBSYSID3": "PCIE_CFGSUBSYSID3", - "CFGSUBSYSID4": "PCIE_CFGSUBSYSID4", - "CFGSUBSYSID5": "PCIE_CFGSUBSYSID5", - "CFGSUBSYSID6": "PCIE_CFGSUBSYSID6", - "CFGSUBSYSID7": "PCIE_CFGSUBSYSID7", - "CFGSUBSYSID8": "PCIE_CFGSUBSYSID8", - "CFGSUBSYSID9": "PCIE_CFGSUBSYSID9", - "CFGSUBSYSVENDID0": "PCIE_CFGSUBSYSVENDID0", - "CFGSUBSYSVENDID1": "PCIE_CFGSUBSYSVENDID1", - "CFGSUBSYSVENDID10": "PCIE_CFGSUBSYSVENDID10", - "CFGSUBSYSVENDID11": "PCIE_CFGSUBSYSVENDID11", - "CFGSUBSYSVENDID12": "PCIE_CFGSUBSYSVENDID12", - "CFGSUBSYSVENDID13": "PCIE_CFGSUBSYSVENDID13", - "CFGSUBSYSVENDID14": "PCIE_CFGSUBSYSVENDID14", - "CFGSUBSYSVENDID15": "PCIE_CFGSUBSYSVENDID15", - "CFGSUBSYSVENDID2": "PCIE_CFGSUBSYSVENDID2", - "CFGSUBSYSVENDID3": "PCIE_CFGSUBSYSVENDID3", - "CFGSUBSYSVENDID4": "PCIE_CFGSUBSYSVENDID4", - "CFGSUBSYSVENDID5": "PCIE_CFGSUBSYSVENDID5", - "CFGSUBSYSVENDID6": "PCIE_CFGSUBSYSVENDID6", - "CFGSUBSYSVENDID7": "PCIE_CFGSUBSYSVENDID7", - "CFGSUBSYSVENDID8": "PCIE_CFGSUBSYSVENDID8", - "CFGSUBSYSVENDID9": "PCIE_CFGSUBSYSVENDID9", - "CFGTRANSACTION": "PCIE_CFGTRANSACTION", - "CFGTRANSACTIONADDR0": "PCIE_CFGTRANSACTIONADDR0", - "CFGTRANSACTIONADDR1": "PCIE_CFGTRANSACTIONADDR1", - "CFGTRANSACTIONADDR2": "PCIE_CFGTRANSACTIONADDR2", - "CFGTRANSACTIONADDR3": "PCIE_CFGTRANSACTIONADDR3", - "CFGTRANSACTIONADDR4": "PCIE_CFGTRANSACTIONADDR4", - "CFGTRANSACTIONADDR5": "PCIE_CFGTRANSACTIONADDR5", - "CFGTRANSACTIONADDR6": "PCIE_CFGTRANSACTIONADDR6", - "CFGTRANSACTIONTYPE": "PCIE_CFGTRANSACTIONTYPE", - "CFGTRNPENDINGN": "PCIE_CFGTRNPENDINGN", - "CFGVCTCVCMAP0": "PCIE_CFGVCTCVCMAP0", - "CFGVCTCVCMAP1": "PCIE_CFGVCTCVCMAP1", - "CFGVCTCVCMAP2": "PCIE_CFGVCTCVCMAP2", - "CFGVCTCVCMAP3": "PCIE_CFGVCTCVCMAP3", - "CFGVCTCVCMAP4": "PCIE_CFGVCTCVCMAP4", - "CFGVCTCVCMAP5": "PCIE_CFGVCTCVCMAP5", - "CFGVCTCVCMAP6": "PCIE_CFGVCTCVCMAP6", - "CFGVENDID0": "PCIE_CFGVENDID0", - "CFGVENDID1": "PCIE_CFGVENDID1", - "CFGVENDID10": "PCIE_CFGVENDID10", - "CFGVENDID11": "PCIE_CFGVENDID11", - "CFGVENDID12": "PCIE_CFGVENDID12", - "CFGVENDID13": "PCIE_CFGVENDID13", - "CFGVENDID14": "PCIE_CFGVENDID14", - "CFGVENDID15": "PCIE_CFGVENDID15", - "CFGVENDID2": "PCIE_CFGVENDID2", - "CFGVENDID3": "PCIE_CFGVENDID3", - "CFGVENDID4": "PCIE_CFGVENDID4", - "CFGVENDID5": "PCIE_CFGVENDID5", - "CFGVENDID6": "PCIE_CFGVENDID6", - "CFGVENDID7": "PCIE_CFGVENDID7", - "CFGVENDID8": "PCIE_CFGVENDID8", - "CFGVENDID9": "PCIE_CFGVENDID9", - "CMRSTN": "PCIE_CMRSTN", - "CMSTICKYRSTN": "PCIE_CMSTICKYRSTN", - "DBGMODE0": "PCIE_DBGMODE0", - "DBGMODE1": "PCIE_DBGMODE1", - "DBGSCLRA": "PCIE_DBGSCLRA", - "DBGSCLRB": "PCIE_DBGSCLRB", - "DBGSCLRC": "PCIE_DBGSCLRC", - "DBGSCLRD": "PCIE_DBGSCLRD", - "DBGSCLRE": "PCIE_DBGSCLRE", - "DBGSCLRF": "PCIE_DBGSCLRF", - "DBGSCLRG": "PCIE_DBGSCLRG", - "DBGSCLRH": "PCIE_DBGSCLRH", - "DBGSCLRI": "PCIE_DBGSCLRI", - "DBGSCLRJ": "PCIE_DBGSCLRJ", - "DBGSCLRK": "PCIE_DBGSCLRK", - "DBGSUBMODE": "PCIE_DBGSUBMODE", - "DBGVECA0": "PCIE_DBGVECA0", - "DBGVECA1": "PCIE_DBGVECA1", - "DBGVECA10": "PCIE_DBGVECA10", - "DBGVECA11": "PCIE_DBGVECA11", - "DBGVECA12": "PCIE_DBGVECA12", - "DBGVECA13": "PCIE_DBGVECA13", - "DBGVECA14": "PCIE_DBGVECA14", - "DBGVECA15": "PCIE_DBGVECA15", - "DBGVECA16": "PCIE_DBGVECA16", - "DBGVECA17": "PCIE_DBGVECA17", - "DBGVECA18": "PCIE_DBGVECA18", - "DBGVECA19": "PCIE_DBGVECA19", - "DBGVECA2": "PCIE_DBGVECA2", - "DBGVECA20": "PCIE_DBGVECA20", - "DBGVECA21": "PCIE_DBGVECA21", - "DBGVECA22": "PCIE_DBGVECA22", - "DBGVECA23": "PCIE_DBGVECA23", - "DBGVECA24": "PCIE_DBGVECA24", - "DBGVECA25": "PCIE_DBGVECA25", - "DBGVECA26": "PCIE_DBGVECA26", - "DBGVECA27": "PCIE_DBGVECA27", - "DBGVECA28": "PCIE_DBGVECA28", - "DBGVECA29": "PCIE_DBGVECA29", - "DBGVECA3": "PCIE_DBGVECA3", - "DBGVECA30": "PCIE_DBGVECA30", - "DBGVECA31": "PCIE_DBGVECA31", - "DBGVECA32": "PCIE_DBGVECA32", - "DBGVECA33": "PCIE_DBGVECA33", - "DBGVECA34": "PCIE_DBGVECA34", - "DBGVECA35": "PCIE_DBGVECA35", - "DBGVECA36": "PCIE_DBGVECA36", - "DBGVECA37": "PCIE_DBGVECA37", - "DBGVECA38": "PCIE_DBGVECA38", - "DBGVECA39": "PCIE_DBGVECA39", - "DBGVECA4": "PCIE_DBGVECA4", - "DBGVECA40": "PCIE_DBGVECA40", - "DBGVECA41": "PCIE_DBGVECA41", - "DBGVECA42": "PCIE_DBGVECA42", - "DBGVECA43": "PCIE_DBGVECA43", - "DBGVECA44": "PCIE_DBGVECA44", - "DBGVECA45": "PCIE_DBGVECA45", - "DBGVECA46": "PCIE_DBGVECA46", - "DBGVECA47": "PCIE_DBGVECA47", - "DBGVECA48": "PCIE_DBGVECA48", - "DBGVECA49": "PCIE_DBGVECA49", - "DBGVECA5": "PCIE_DBGVECA5", - "DBGVECA50": "PCIE_DBGVECA50", - "DBGVECA51": "PCIE_DBGVECA51", - "DBGVECA52": "PCIE_DBGVECA52", - "DBGVECA53": "PCIE_DBGVECA53", - "DBGVECA54": "PCIE_DBGVECA54", - "DBGVECA55": "PCIE_DBGVECA55", - "DBGVECA56": "PCIE_DBGVECA56", - "DBGVECA57": "PCIE_DBGVECA57", - "DBGVECA58": "PCIE_DBGVECA58", - "DBGVECA59": "PCIE_DBGVECA59", - "DBGVECA6": "PCIE_DBGVECA6", - "DBGVECA60": "PCIE_DBGVECA60", - "DBGVECA61": "PCIE_DBGVECA61", - "DBGVECA62": "PCIE_DBGVECA62", - "DBGVECA63": "PCIE_DBGVECA63", - "DBGVECA7": "PCIE_DBGVECA7", - "DBGVECA8": "PCIE_DBGVECA8", - "DBGVECA9": "PCIE_DBGVECA9", - "DBGVECB0": "PCIE_DBGVECB0", - "DBGVECB1": "PCIE_DBGVECB1", - "DBGVECB10": "PCIE_DBGVECB10", - "DBGVECB11": "PCIE_DBGVECB11", - "DBGVECB12": "PCIE_DBGVECB12", - "DBGVECB13": "PCIE_DBGVECB13", - "DBGVECB14": "PCIE_DBGVECB14", - "DBGVECB15": "PCIE_DBGVECB15", - "DBGVECB16": "PCIE_DBGVECB16", - "DBGVECB17": "PCIE_DBGVECB17", - "DBGVECB18": "PCIE_DBGVECB18", - "DBGVECB19": "PCIE_DBGVECB19", - "DBGVECB2": "PCIE_DBGVECB2", - "DBGVECB20": "PCIE_DBGVECB20", - "DBGVECB21": "PCIE_DBGVECB21", - "DBGVECB22": "PCIE_DBGVECB22", - "DBGVECB23": "PCIE_DBGVECB23", - "DBGVECB24": "PCIE_DBGVECB24", - "DBGVECB25": "PCIE_DBGVECB25", - "DBGVECB26": "PCIE_DBGVECB26", - "DBGVECB27": "PCIE_DBGVECB27", - "DBGVECB28": "PCIE_DBGVECB28", - "DBGVECB29": "PCIE_DBGVECB29", - "DBGVECB3": "PCIE_DBGVECB3", - "DBGVECB30": "PCIE_DBGVECB30", - "DBGVECB31": "PCIE_DBGVECB31", - "DBGVECB32": "PCIE_DBGVECB32", - "DBGVECB33": "PCIE_DBGVECB33", - "DBGVECB34": "PCIE_DBGVECB34", - "DBGVECB35": "PCIE_DBGVECB35", - "DBGVECB36": "PCIE_DBGVECB36", - "DBGVECB37": "PCIE_DBGVECB37", - "DBGVECB38": "PCIE_DBGVECB38", - "DBGVECB39": "PCIE_DBGVECB39", - "DBGVECB4": "PCIE_DBGVECB4", - "DBGVECB40": "PCIE_DBGVECB40", - "DBGVECB41": "PCIE_DBGVECB41", - "DBGVECB42": "PCIE_DBGVECB42", - "DBGVECB43": "PCIE_DBGVECB43", - "DBGVECB44": "PCIE_DBGVECB44", - "DBGVECB45": "PCIE_DBGVECB45", - "DBGVECB46": "PCIE_DBGVECB46", - "DBGVECB47": "PCIE_DBGVECB47", - "DBGVECB48": "PCIE_DBGVECB48", - "DBGVECB49": "PCIE_DBGVECB49", - "DBGVECB5": "PCIE_DBGVECB5", - "DBGVECB50": "PCIE_DBGVECB50", - "DBGVECB51": "PCIE_DBGVECB51", - "DBGVECB52": "PCIE_DBGVECB52", - "DBGVECB53": "PCIE_DBGVECB53", - "DBGVECB54": "PCIE_DBGVECB54", - "DBGVECB55": "PCIE_DBGVECB55", - "DBGVECB56": "PCIE_DBGVECB56", - "DBGVECB57": "PCIE_DBGVECB57", - "DBGVECB58": "PCIE_DBGVECB58", - "DBGVECB59": "PCIE_DBGVECB59", - "DBGVECB6": "PCIE_DBGVECB6", - "DBGVECB60": "PCIE_DBGVECB60", - "DBGVECB61": "PCIE_DBGVECB61", - "DBGVECB62": "PCIE_DBGVECB62", - "DBGVECB63": "PCIE_DBGVECB63", - "DBGVECB7": "PCIE_DBGVECB7", - "DBGVECB8": "PCIE_DBGVECB8", - "DBGVECB9": "PCIE_DBGVECB9", - "DBGVECC0": "PCIE_DBGVECC0", - "DBGVECC1": "PCIE_DBGVECC1", - "DBGVECC10": "PCIE_DBGVECC10", - "DBGVECC11": "PCIE_DBGVECC11", - "DBGVECC2": "PCIE_DBGVECC2", - "DBGVECC3": "PCIE_DBGVECC3", - "DBGVECC4": "PCIE_DBGVECC4", - "DBGVECC5": "PCIE_DBGVECC5", - "DBGVECC6": "PCIE_DBGVECC6", - "DBGVECC7": "PCIE_DBGVECC7", - "DBGVECC8": "PCIE_DBGVECC8", - "DBGVECC9": "PCIE_DBGVECC9", - "DLRSTN": "PCIE_DLRSTN", - "DRPADDR0": "PCIE_DRPADDR0", - "DRPADDR1": "PCIE_DRPADDR1", - "DRPADDR2": "PCIE_DRPADDR2", - "DRPADDR3": "PCIE_DRPADDR3", - "DRPADDR4": "PCIE_DRPADDR4", - "DRPADDR5": "PCIE_DRPADDR5", - "DRPADDR6": "PCIE_DRPADDR6", - "DRPADDR7": "PCIE_DRPADDR7", - "DRPADDR8": "PCIE_DRPADDR8", - "DRPCLK": "PCIE_DRPCLK", - "DRPDI0": "PCIE_DRPDI0", - "DRPDI1": "PCIE_DRPDI1", - "DRPDI10": "PCIE_DRPDI10", - "DRPDI11": "PCIE_DRPDI11", - "DRPDI12": "PCIE_DRPDI12", - "DRPDI13": "PCIE_DRPDI13", - "DRPDI14": "PCIE_DRPDI14", - "DRPDI15": "PCIE_DRPDI15", - "DRPDI2": "PCIE_DRPDI2", - "DRPDI3": "PCIE_DRPDI3", - "DRPDI4": "PCIE_DRPDI4", - "DRPDI5": "PCIE_DRPDI5", - "DRPDI6": "PCIE_DRPDI6", - "DRPDI7": "PCIE_DRPDI7", - "DRPDI8": "PCIE_DRPDI8", - "DRPDI9": "PCIE_DRPDI9", - "DRPDO0": "PCIE_DRPDO0", - "DRPDO1": "PCIE_DRPDO1", - "DRPDO10": "PCIE_DRPDO10", - "DRPDO11": "PCIE_DRPDO11", - "DRPDO12": "PCIE_DRPDO12", - "DRPDO13": "PCIE_DRPDO13", - "DRPDO14": "PCIE_DRPDO14", - "DRPDO15": "PCIE_DRPDO15", - "DRPDO2": "PCIE_DRPDO2", - "DRPDO3": "PCIE_DRPDO3", - "DRPDO4": "PCIE_DRPDO4", - "DRPDO5": "PCIE_DRPDO5", - "DRPDO6": "PCIE_DRPDO6", - "DRPDO7": "PCIE_DRPDO7", - "DRPDO8": "PCIE_DRPDO8", - "DRPDO9": "PCIE_DRPDO9", - "DRPEN": "PCIE_DRPEN", - "DRPRDY": "PCIE_DRPRDY", - "DRPWE": "PCIE_DRPWE", - "EDTBYPASS": "PCIE_EDTBYPASS", - "EDTCHANNELSIN1": "PCIE_EDTCHANNELSIN1", - "EDTCHANNELSIN2": "PCIE_EDTCHANNELSIN2", - "EDTCHANNELSIN3": "PCIE_EDTCHANNELSIN3", - "EDTCHANNELSIN4": "PCIE_EDTCHANNELSIN4", - "EDTCHANNELSIN5": "PCIE_EDTCHANNELSIN5", - "EDTCHANNELSIN6": "PCIE_EDTCHANNELSIN6", - "EDTCHANNELSIN7": "PCIE_EDTCHANNELSIN7", - "EDTCHANNELSIN8": "PCIE_EDTCHANNELSIN8", - "EDTCHANNELSOUT1": "PCIE_EDTCHANNELSOUT1", - "EDTCHANNELSOUT2": "PCIE_EDTCHANNELSOUT2", - "EDTCHANNELSOUT3": "PCIE_EDTCHANNELSOUT3", - "EDTCHANNELSOUT4": "PCIE_EDTCHANNELSOUT4", - "EDTCHANNELSOUT5": "PCIE_EDTCHANNELSOUT5", - "EDTCHANNELSOUT6": "PCIE_EDTCHANNELSOUT6", - "EDTCHANNELSOUT7": "PCIE_EDTCHANNELSOUT7", - "EDTCHANNELSOUT8": "PCIE_EDTCHANNELSOUT8", - "EDTCLK": "PCIE_EDTCLK", - "EDTCONFIGURATION": "PCIE_EDTCONFIGURATION", - "EDTSINGLEBYPASSCHAIN": "PCIE_EDTSINGLEBYPASSCHAIN", - "EDTUPDATE": "PCIE_EDTUPDATE", - "FUNCLVLRSTN": "PCIE_FUNCLVLRSTN", - "LL2BADDLLPERR": "PCIE_LL2BADDLLPERR", - "LL2BADTLPERR": "PCIE_LL2BADTLPERR", - "LL2LINKSTATUS0": "PCIE_LL2LINKSTATUS0", - "LL2LINKSTATUS1": "PCIE_LL2LINKSTATUS1", - "LL2LINKSTATUS2": "PCIE_LL2LINKSTATUS2", - "LL2LINKSTATUS3": "PCIE_LL2LINKSTATUS3", - "LL2LINKSTATUS4": "PCIE_LL2LINKSTATUS4", - "LL2PROTOCOLERR": "PCIE_LL2PROTOCOLERR", - "LL2RECEIVERERR": "PCIE_LL2RECEIVERERR", - "LL2REPLAYROERR": "PCIE_LL2REPLAYROERR", - "LL2REPLAYTOERR": "PCIE_LL2REPLAYTOERR", - "LL2SENDASREQL1": "PCIE_LL2SENDASREQL1", - "LL2SENDENTERL1": "PCIE_LL2SENDENTERL1", - "LL2SENDENTERL23": "PCIE_LL2SENDENTERL23", - "LL2SENDPMACK": "PCIE_LL2SENDPMACK", - "LL2SUSPENDNOW": "PCIE_LL2SUSPENDNOW", - "LL2SUSPENDOK": "PCIE_LL2SUSPENDOK", - "LL2TFCINIT1SEQ": "PCIE_LL2TFCINIT1SEQ", - "LL2TFCINIT2SEQ": "PCIE_LL2TFCINIT2SEQ", - "LL2TLPRCV": "PCIE_LL2TLPRCV", - "LL2TXIDLE": "PCIE_LL2TXIDLE", - "LNKCLKEN": "PCIE_LNKCLKEN", - "MIMRXRADDR0": "PCIE_MIMRXRADDR0", - "MIMRXRADDR1": "PCIE_MIMRXRADDR1", - "MIMRXRADDR10": "PCIE_MIMRXRADDR10", - "MIMRXRADDR11": "PCIE_MIMRXRADDR11", - "MIMRXRADDR12": "PCIE_MIMRXRADDR12", - "MIMRXRADDR2": "PCIE_MIMRXRADDR2", - "MIMRXRADDR3": "PCIE_MIMRXRADDR3", - "MIMRXRADDR4": "PCIE_MIMRXRADDR4", - "MIMRXRADDR5": "PCIE_MIMRXRADDR5", - "MIMRXRADDR6": "PCIE_MIMRXRADDR6", - "MIMRXRADDR7": "PCIE_MIMRXRADDR7", - "MIMRXRADDR8": "PCIE_MIMRXRADDR8", - "MIMRXRADDR9": "PCIE_MIMRXRADDR9", - "MIMRXRDATA0": "PCIE_MIMRXRDATA0", - "MIMRXRDATA1": "PCIE_MIMRXRDATA1", - "MIMRXRDATA10": "PCIE_MIMRXRDATA10", - "MIMRXRDATA11": "PCIE_MIMRXRDATA11", - "MIMRXRDATA12": "PCIE_MIMRXRDATA12", - "MIMRXRDATA13": "PCIE_MIMRXRDATA13", - "MIMRXRDATA14": "PCIE_MIMRXRDATA14", - "MIMRXRDATA15": "PCIE_MIMRXRDATA15", - "MIMRXRDATA16": "PCIE_MIMRXRDATA16", - "MIMRXRDATA17": "PCIE_MIMRXRDATA17", - "MIMRXRDATA18": "PCIE_MIMRXRDATA18", - "MIMRXRDATA19": "PCIE_MIMRXRDATA19", - "MIMRXRDATA2": "PCIE_MIMRXRDATA2", - "MIMRXRDATA20": "PCIE_MIMRXRDATA20", - "MIMRXRDATA21": "PCIE_MIMRXRDATA21", - "MIMRXRDATA22": "PCIE_MIMRXRDATA22", - "MIMRXRDATA23": "PCIE_MIMRXRDATA23", - "MIMRXRDATA24": "PCIE_MIMRXRDATA24", - "MIMRXRDATA25": "PCIE_MIMRXRDATA25", - "MIMRXRDATA26": "PCIE_MIMRXRDATA26", - "MIMRXRDATA27": "PCIE_MIMRXRDATA27", - "MIMRXRDATA28": "PCIE_MIMRXRDATA28", - "MIMRXRDATA29": "PCIE_MIMRXRDATA29", - "MIMRXRDATA3": "PCIE_MIMRXRDATA3", - "MIMRXRDATA30": "PCIE_MIMRXRDATA30", - "MIMRXRDATA31": "PCIE_MIMRXRDATA31", - "MIMRXRDATA32": "PCIE_MIMRXRDATA32", - "MIMRXRDATA33": "PCIE_MIMRXRDATA33", - "MIMRXRDATA34": "PCIE_MIMRXRDATA34", - "MIMRXRDATA35": "PCIE_MIMRXRDATA35", - "MIMRXRDATA36": "PCIE_MIMRXRDATA36", - "MIMRXRDATA37": "PCIE_MIMRXRDATA37", - "MIMRXRDATA38": "PCIE_MIMRXRDATA38", - "MIMRXRDATA39": "PCIE_MIMRXRDATA39", - "MIMRXRDATA4": "PCIE_MIMRXRDATA4", - "MIMRXRDATA40": "PCIE_MIMRXRDATA40", - "MIMRXRDATA41": "PCIE_MIMRXRDATA41", - "MIMRXRDATA42": "PCIE_MIMRXRDATA42", - "MIMRXRDATA43": "PCIE_MIMRXRDATA43", - "MIMRXRDATA44": "PCIE_MIMRXRDATA44", - "MIMRXRDATA45": "PCIE_MIMRXRDATA45", - "MIMRXRDATA46": "PCIE_MIMRXRDATA46", - "MIMRXRDATA47": "PCIE_MIMRXRDATA47", - "MIMRXRDATA48": "PCIE_MIMRXRDATA48", - "MIMRXRDATA49": "PCIE_MIMRXRDATA49", - "MIMRXRDATA5": "PCIE_MIMRXRDATA5", - "MIMRXRDATA50": "PCIE_MIMRXRDATA50", - "MIMRXRDATA51": "PCIE_MIMRXRDATA51", - "MIMRXRDATA52": "PCIE_MIMRXRDATA52", - "MIMRXRDATA53": "PCIE_MIMRXRDATA53", - "MIMRXRDATA54": "PCIE_MIMRXRDATA54", - "MIMRXRDATA55": "PCIE_MIMRXRDATA55", - "MIMRXRDATA56": "PCIE_MIMRXRDATA56", - "MIMRXRDATA57": "PCIE_MIMRXRDATA57", - "MIMRXRDATA58": "PCIE_MIMRXRDATA58", - "MIMRXRDATA59": "PCIE_MIMRXRDATA59", - "MIMRXRDATA6": "PCIE_MIMRXRDATA6", - "MIMRXRDATA60": "PCIE_MIMRXRDATA60", - "MIMRXRDATA61": "PCIE_MIMRXRDATA61", - "MIMRXRDATA62": "PCIE_MIMRXRDATA62", - "MIMRXRDATA63": "PCIE_MIMRXRDATA63", - "MIMRXRDATA64": "PCIE_MIMRXRDATA64", - "MIMRXRDATA65": "PCIE_MIMRXRDATA65", - "MIMRXRDATA66": "PCIE_MIMRXRDATA66", - "MIMRXRDATA67": "PCIE_MIMRXRDATA67", - "MIMRXRDATA7": "PCIE_MIMRXRDATA7", - "MIMRXRDATA8": "PCIE_MIMRXRDATA8", - "MIMRXRDATA9": "PCIE_MIMRXRDATA9", - "MIMRXREN": "PCIE_MIMRXREN", - "MIMRXWADDR0": "PCIE_MIMRXWADDR0", - "MIMRXWADDR1": "PCIE_MIMRXWADDR1", - "MIMRXWADDR10": "PCIE_MIMRXWADDR10", - "MIMRXWADDR11": "PCIE_MIMRXWADDR11", - "MIMRXWADDR12": "PCIE_MIMRXWADDR12", - "MIMRXWADDR2": "PCIE_MIMRXWADDR2", - "MIMRXWADDR3": "PCIE_MIMRXWADDR3", - "MIMRXWADDR4": "PCIE_MIMRXWADDR4", - "MIMRXWADDR5": "PCIE_MIMRXWADDR5", - "MIMRXWADDR6": "PCIE_MIMRXWADDR6", - "MIMRXWADDR7": "PCIE_MIMRXWADDR7", - "MIMRXWADDR8": "PCIE_MIMRXWADDR8", - "MIMRXWADDR9": "PCIE_MIMRXWADDR9", - "MIMRXWDATA0": "PCIE_MIMRXWDATA0", - "MIMRXWDATA1": "PCIE_MIMRXWDATA1", - "MIMRXWDATA10": "PCIE_MIMRXWDATA10", - "MIMRXWDATA11": "PCIE_MIMRXWDATA11", - "MIMRXWDATA12": "PCIE_MIMRXWDATA12", - "MIMRXWDATA13": "PCIE_MIMRXWDATA13", - "MIMRXWDATA14": "PCIE_MIMRXWDATA14", - "MIMRXWDATA15": "PCIE_MIMRXWDATA15", - "MIMRXWDATA16": "PCIE_MIMRXWDATA16", - "MIMRXWDATA17": "PCIE_MIMRXWDATA17", - "MIMRXWDATA18": "PCIE_MIMRXWDATA18", - "MIMRXWDATA19": "PCIE_MIMRXWDATA19", - "MIMRXWDATA2": "PCIE_MIMRXWDATA2", - "MIMRXWDATA20": "PCIE_MIMRXWDATA20", - "MIMRXWDATA21": "PCIE_MIMRXWDATA21", - "MIMRXWDATA22": "PCIE_MIMRXWDATA22", - "MIMRXWDATA23": "PCIE_MIMRXWDATA23", - "MIMRXWDATA24": "PCIE_MIMRXWDATA24", - "MIMRXWDATA25": "PCIE_MIMRXWDATA25", - "MIMRXWDATA26": "PCIE_MIMRXWDATA26", - "MIMRXWDATA27": "PCIE_MIMRXWDATA27", - "MIMRXWDATA28": "PCIE_MIMRXWDATA28", - "MIMRXWDATA29": "PCIE_MIMRXWDATA29", - "MIMRXWDATA3": "PCIE_MIMRXWDATA3", - "MIMRXWDATA30": "PCIE_MIMRXWDATA30", - "MIMRXWDATA31": "PCIE_MIMRXWDATA31", - "MIMRXWDATA32": "PCIE_MIMRXWDATA32", - "MIMRXWDATA33": "PCIE_MIMRXWDATA33", - "MIMRXWDATA34": "PCIE_MIMRXWDATA34", - "MIMRXWDATA35": "PCIE_MIMRXWDATA35", - "MIMRXWDATA36": "PCIE_MIMRXWDATA36", - "MIMRXWDATA37": "PCIE_MIMRXWDATA37", - "MIMRXWDATA38": "PCIE_MIMRXWDATA38", - "MIMRXWDATA39": "PCIE_MIMRXWDATA39", - "MIMRXWDATA4": "PCIE_MIMRXWDATA4", - "MIMRXWDATA40": "PCIE_MIMRXWDATA40", - "MIMRXWDATA41": "PCIE_MIMRXWDATA41", - "MIMRXWDATA42": "PCIE_MIMRXWDATA42", - "MIMRXWDATA43": "PCIE_MIMRXWDATA43", - "MIMRXWDATA44": "PCIE_MIMRXWDATA44", - "MIMRXWDATA45": "PCIE_MIMRXWDATA45", - "MIMRXWDATA46": "PCIE_MIMRXWDATA46", - "MIMRXWDATA47": "PCIE_MIMRXWDATA47", - "MIMRXWDATA48": "PCIE_MIMRXWDATA48", - "MIMRXWDATA49": "PCIE_MIMRXWDATA49", - "MIMRXWDATA5": "PCIE_MIMRXWDATA5", - "MIMRXWDATA50": "PCIE_MIMRXWDATA50", - "MIMRXWDATA51": "PCIE_MIMRXWDATA51", - "MIMRXWDATA52": "PCIE_MIMRXWDATA52", - "MIMRXWDATA53": "PCIE_MIMRXWDATA53", - "MIMRXWDATA54": "PCIE_MIMRXWDATA54", - "MIMRXWDATA55": "PCIE_MIMRXWDATA55", - "MIMRXWDATA56": "PCIE_MIMRXWDATA56", - "MIMRXWDATA57": "PCIE_MIMRXWDATA57", - "MIMRXWDATA58": "PCIE_MIMRXWDATA58", - "MIMRXWDATA59": "PCIE_MIMRXWDATA59", - "MIMRXWDATA6": "PCIE_MIMRXWDATA6", - "MIMRXWDATA60": "PCIE_MIMRXWDATA60", - "MIMRXWDATA61": "PCIE_MIMRXWDATA61", - "MIMRXWDATA62": "PCIE_MIMRXWDATA62", - "MIMRXWDATA63": "PCIE_MIMRXWDATA63", - "MIMRXWDATA64": "PCIE_MIMRXWDATA64", - "MIMRXWDATA65": "PCIE_MIMRXWDATA65", - "MIMRXWDATA66": "PCIE_MIMRXWDATA66", - "MIMRXWDATA67": "PCIE_MIMRXWDATA67", - "MIMRXWDATA7": "PCIE_MIMRXWDATA7", - "MIMRXWDATA8": "PCIE_MIMRXWDATA8", - "MIMRXWDATA9": "PCIE_MIMRXWDATA9", - "MIMRXWEN": "PCIE_MIMRXWEN", - "MIMTXRADDR0": "PCIE_MIMTXRADDR0", - "MIMTXRADDR1": "PCIE_MIMTXRADDR1", - "MIMTXRADDR10": "PCIE_MIMTXRADDR10", - "MIMTXRADDR11": "PCIE_MIMTXRADDR11", - "MIMTXRADDR12": "PCIE_MIMTXRADDR12", - "MIMTXRADDR2": "PCIE_MIMTXRADDR2", - "MIMTXRADDR3": "PCIE_MIMTXRADDR3", - "MIMTXRADDR4": "PCIE_MIMTXRADDR4", - "MIMTXRADDR5": "PCIE_MIMTXRADDR5", - "MIMTXRADDR6": "PCIE_MIMTXRADDR6", - "MIMTXRADDR7": "PCIE_MIMTXRADDR7", - "MIMTXRADDR8": "PCIE_MIMTXRADDR8", - "MIMTXRADDR9": "PCIE_MIMTXRADDR9", - "MIMTXRDATA0": "PCIE_MIMTXRDATA0", - "MIMTXRDATA1": "PCIE_MIMTXRDATA1", - "MIMTXRDATA10": "PCIE_MIMTXRDATA10", - "MIMTXRDATA11": "PCIE_MIMTXRDATA11", - "MIMTXRDATA12": "PCIE_MIMTXRDATA12", - "MIMTXRDATA13": "PCIE_MIMTXRDATA13", - "MIMTXRDATA14": "PCIE_MIMTXRDATA14", - "MIMTXRDATA15": "PCIE_MIMTXRDATA15", - "MIMTXRDATA16": "PCIE_MIMTXRDATA16", - "MIMTXRDATA17": "PCIE_MIMTXRDATA17", - "MIMTXRDATA18": "PCIE_MIMTXRDATA18", - "MIMTXRDATA19": "PCIE_MIMTXRDATA19", - "MIMTXRDATA2": "PCIE_MIMTXRDATA2", - "MIMTXRDATA20": "PCIE_MIMTXRDATA20", - "MIMTXRDATA21": "PCIE_MIMTXRDATA21", - "MIMTXRDATA22": "PCIE_MIMTXRDATA22", - "MIMTXRDATA23": "PCIE_MIMTXRDATA23", - "MIMTXRDATA24": "PCIE_MIMTXRDATA24", - "MIMTXRDATA25": "PCIE_MIMTXRDATA25", - "MIMTXRDATA26": "PCIE_MIMTXRDATA26", - "MIMTXRDATA27": "PCIE_MIMTXRDATA27", - "MIMTXRDATA28": "PCIE_MIMTXRDATA28", - "MIMTXRDATA29": "PCIE_MIMTXRDATA29", - "MIMTXRDATA3": "PCIE_MIMTXRDATA3", - "MIMTXRDATA30": "PCIE_MIMTXRDATA30", - "MIMTXRDATA31": "PCIE_MIMTXRDATA31", - "MIMTXRDATA32": "PCIE_MIMTXRDATA32", - "MIMTXRDATA33": "PCIE_MIMTXRDATA33", - "MIMTXRDATA34": "PCIE_MIMTXRDATA34", - "MIMTXRDATA35": "PCIE_MIMTXRDATA35", - "MIMTXRDATA36": "PCIE_MIMTXRDATA36", - "MIMTXRDATA37": "PCIE_MIMTXRDATA37", - "MIMTXRDATA38": "PCIE_MIMTXRDATA38", - "MIMTXRDATA39": "PCIE_MIMTXRDATA39", - "MIMTXRDATA4": "PCIE_MIMTXRDATA4", - "MIMTXRDATA40": "PCIE_MIMTXRDATA40", - "MIMTXRDATA41": "PCIE_MIMTXRDATA41", - "MIMTXRDATA42": "PCIE_MIMTXRDATA42", - "MIMTXRDATA43": "PCIE_MIMTXRDATA43", - "MIMTXRDATA44": "PCIE_MIMTXRDATA44", - "MIMTXRDATA45": "PCIE_MIMTXRDATA45", - "MIMTXRDATA46": "PCIE_MIMTXRDATA46", - "MIMTXRDATA47": "PCIE_MIMTXRDATA47", - "MIMTXRDATA48": "PCIE_MIMTXRDATA48", - "MIMTXRDATA49": "PCIE_MIMTXRDATA49", - "MIMTXRDATA5": "PCIE_MIMTXRDATA5", - "MIMTXRDATA50": "PCIE_MIMTXRDATA50", - "MIMTXRDATA51": "PCIE_MIMTXRDATA51", - "MIMTXRDATA52": "PCIE_MIMTXRDATA52", - "MIMTXRDATA53": "PCIE_MIMTXRDATA53", - "MIMTXRDATA54": "PCIE_MIMTXRDATA54", - "MIMTXRDATA55": "PCIE_MIMTXRDATA55", - "MIMTXRDATA56": "PCIE_MIMTXRDATA56", - "MIMTXRDATA57": "PCIE_MIMTXRDATA57", - "MIMTXRDATA58": "PCIE_MIMTXRDATA58", - "MIMTXRDATA59": "PCIE_MIMTXRDATA59", - "MIMTXRDATA6": "PCIE_MIMTXRDATA6", - "MIMTXRDATA60": "PCIE_MIMTXRDATA60", - "MIMTXRDATA61": "PCIE_MIMTXRDATA61", - "MIMTXRDATA62": "PCIE_MIMTXRDATA62", - "MIMTXRDATA63": "PCIE_MIMTXRDATA63", - "MIMTXRDATA64": "PCIE_MIMTXRDATA64", - "MIMTXRDATA65": "PCIE_MIMTXRDATA65", - "MIMTXRDATA66": "PCIE_MIMTXRDATA66", - "MIMTXRDATA67": "PCIE_MIMTXRDATA67", - "MIMTXRDATA68": "PCIE_MIMTXRDATA68", - "MIMTXRDATA7": "PCIE_MIMTXRDATA7", - "MIMTXRDATA8": "PCIE_MIMTXRDATA8", - "MIMTXRDATA9": "PCIE_MIMTXRDATA9", - "MIMTXREN": "PCIE_MIMTXREN", - "MIMTXWADDR0": "PCIE_MIMTXWADDR0", - "MIMTXWADDR1": "PCIE_MIMTXWADDR1", - "MIMTXWADDR10": "PCIE_MIMTXWADDR10", - "MIMTXWADDR11": "PCIE_MIMTXWADDR11", - "MIMTXWADDR12": "PCIE_MIMTXWADDR12", - "MIMTXWADDR2": "PCIE_MIMTXWADDR2", - "MIMTXWADDR3": "PCIE_MIMTXWADDR3", - "MIMTXWADDR4": "PCIE_MIMTXWADDR4", - "MIMTXWADDR5": "PCIE_MIMTXWADDR5", - "MIMTXWADDR6": "PCIE_MIMTXWADDR6", - "MIMTXWADDR7": "PCIE_MIMTXWADDR7", - "MIMTXWADDR8": "PCIE_MIMTXWADDR8", - "MIMTXWADDR9": "PCIE_MIMTXWADDR9", - "MIMTXWDATA0": "PCIE_MIMTXWDATA0", - "MIMTXWDATA1": "PCIE_MIMTXWDATA1", - "MIMTXWDATA10": "PCIE_MIMTXWDATA10", - "MIMTXWDATA11": "PCIE_MIMTXWDATA11", - "MIMTXWDATA12": "PCIE_MIMTXWDATA12", - "MIMTXWDATA13": "PCIE_MIMTXWDATA13", - "MIMTXWDATA14": "PCIE_MIMTXWDATA14", - "MIMTXWDATA15": "PCIE_MIMTXWDATA15", - "MIMTXWDATA16": "PCIE_MIMTXWDATA16", - "MIMTXWDATA17": "PCIE_MIMTXWDATA17", - "MIMTXWDATA18": "PCIE_MIMTXWDATA18", - "MIMTXWDATA19": "PCIE_MIMTXWDATA19", - "MIMTXWDATA2": "PCIE_MIMTXWDATA2", - "MIMTXWDATA20": "PCIE_MIMTXWDATA20", - "MIMTXWDATA21": "PCIE_MIMTXWDATA21", - "MIMTXWDATA22": "PCIE_MIMTXWDATA22", - "MIMTXWDATA23": "PCIE_MIMTXWDATA23", - "MIMTXWDATA24": "PCIE_MIMTXWDATA24", - "MIMTXWDATA25": "PCIE_MIMTXWDATA25", - "MIMTXWDATA26": "PCIE_MIMTXWDATA26", - "MIMTXWDATA27": "PCIE_MIMTXWDATA27", - "MIMTXWDATA28": "PCIE_MIMTXWDATA28", - "MIMTXWDATA29": "PCIE_MIMTXWDATA29", - "MIMTXWDATA3": "PCIE_MIMTXWDATA3", - "MIMTXWDATA30": "PCIE_MIMTXWDATA30", - "MIMTXWDATA31": "PCIE_MIMTXWDATA31", - "MIMTXWDATA32": "PCIE_MIMTXWDATA32", - "MIMTXWDATA33": "PCIE_MIMTXWDATA33", - "MIMTXWDATA34": "PCIE_MIMTXWDATA34", - "MIMTXWDATA35": "PCIE_MIMTXWDATA35", - "MIMTXWDATA36": "PCIE_MIMTXWDATA36", - "MIMTXWDATA37": "PCIE_MIMTXWDATA37", - "MIMTXWDATA38": "PCIE_MIMTXWDATA38", - "MIMTXWDATA39": "PCIE_MIMTXWDATA39", - "MIMTXWDATA4": "PCIE_MIMTXWDATA4", - "MIMTXWDATA40": "PCIE_MIMTXWDATA40", - "MIMTXWDATA41": "PCIE_MIMTXWDATA41", - "MIMTXWDATA42": "PCIE_MIMTXWDATA42", - "MIMTXWDATA43": "PCIE_MIMTXWDATA43", - "MIMTXWDATA44": "PCIE_MIMTXWDATA44", - "MIMTXWDATA45": "PCIE_MIMTXWDATA45", - "MIMTXWDATA46": "PCIE_MIMTXWDATA46", - "MIMTXWDATA47": "PCIE_MIMTXWDATA47", - "MIMTXWDATA48": "PCIE_MIMTXWDATA48", - "MIMTXWDATA49": "PCIE_MIMTXWDATA49", - "MIMTXWDATA5": "PCIE_MIMTXWDATA5", - "MIMTXWDATA50": "PCIE_MIMTXWDATA50", - "MIMTXWDATA51": "PCIE_MIMTXWDATA51", - "MIMTXWDATA52": "PCIE_MIMTXWDATA52", - "MIMTXWDATA53": "PCIE_MIMTXWDATA53", - "MIMTXWDATA54": "PCIE_MIMTXWDATA54", - "MIMTXWDATA55": "PCIE_MIMTXWDATA55", - "MIMTXWDATA56": "PCIE_MIMTXWDATA56", - "MIMTXWDATA57": "PCIE_MIMTXWDATA57", - "MIMTXWDATA58": "PCIE_MIMTXWDATA58", - "MIMTXWDATA59": "PCIE_MIMTXWDATA59", - "MIMTXWDATA6": "PCIE_MIMTXWDATA6", - "MIMTXWDATA60": "PCIE_MIMTXWDATA60", - "MIMTXWDATA61": "PCIE_MIMTXWDATA61", - "MIMTXWDATA62": "PCIE_MIMTXWDATA62", - "MIMTXWDATA63": "PCIE_MIMTXWDATA63", - "MIMTXWDATA64": "PCIE_MIMTXWDATA64", - "MIMTXWDATA65": "PCIE_MIMTXWDATA65", - "MIMTXWDATA66": "PCIE_MIMTXWDATA66", - "MIMTXWDATA67": "PCIE_MIMTXWDATA67", - "MIMTXWDATA68": "PCIE_MIMTXWDATA68", - "MIMTXWDATA7": "PCIE_MIMTXWDATA7", - "MIMTXWDATA8": "PCIE_MIMTXWDATA8", - "MIMTXWDATA9": "PCIE_MIMTXWDATA9", - "MIMTXWEN": "PCIE_MIMTXWEN", - "PIPECLK": "PCIE_PIPECLK", - "PIPERX0CHANISALIGNED": "PCIE_PIPERX0CHANISALIGNED", - "PIPERX0CHARISK0": "PCIE_PIPERX0CHARISK0", - "PIPERX0CHARISK1": "PCIE_PIPERX0CHARISK1", - "PIPERX0DATA0": "PCIE_PIPERX0DATA0", - "PIPERX0DATA1": "PCIE_PIPERX0DATA1", - "PIPERX0DATA10": "PCIE_PIPERX0DATA10", - "PIPERX0DATA11": "PCIE_PIPERX0DATA11", - "PIPERX0DATA12": "PCIE_PIPERX0DATA12", - "PIPERX0DATA13": "PCIE_PIPERX0DATA13", - "PIPERX0DATA14": "PCIE_PIPERX0DATA14", - "PIPERX0DATA15": "PCIE_PIPERX0DATA15", - "PIPERX0DATA2": "PCIE_PIPERX0DATA2", - "PIPERX0DATA3": "PCIE_PIPERX0DATA3", - "PIPERX0DATA4": "PCIE_PIPERX0DATA4", - "PIPERX0DATA5": "PCIE_PIPERX0DATA5", - "PIPERX0DATA6": "PCIE_PIPERX0DATA6", - "PIPERX0DATA7": "PCIE_PIPERX0DATA7", - "PIPERX0DATA8": "PCIE_PIPERX0DATA8", - "PIPERX0DATA9": "PCIE_PIPERX0DATA9", - "PIPERX0ELECIDLE": "PCIE_PIPERX0ELECIDLE", - "PIPERX0PHYSTATUS": "PCIE_PIPERX0PHYSTATUS", - "PIPERX0POLARITY": "PCIE_PIPERX0POLARITY", - "PIPERX0STATUS0": "PCIE_PIPERX0STATUS0", - "PIPERX0STATUS1": "PCIE_PIPERX0STATUS1", - "PIPERX0STATUS2": "PCIE_PIPERX0STATUS2", - "PIPERX0VALID": "PCIE_PIPERX0VALID", - "PIPERX1CHANISALIGNED": "PCIE_PIPERX1CHANISALIGNED", - "PIPERX1CHARISK0": "PCIE_PIPERX1CHARISK0", - "PIPERX1CHARISK1": "PCIE_PIPERX1CHARISK1", - "PIPERX1DATA0": "PCIE_PIPERX1DATA0", - "PIPERX1DATA1": "PCIE_PIPERX1DATA1", - "PIPERX1DATA10": "PCIE_PIPERX1DATA10", - "PIPERX1DATA11": "PCIE_PIPERX1DATA11", - "PIPERX1DATA12": "PCIE_PIPERX1DATA12", - "PIPERX1DATA13": "PCIE_PIPERX1DATA13", - "PIPERX1DATA14": "PCIE_PIPERX1DATA14", - "PIPERX1DATA15": "PCIE_PIPERX1DATA15", - "PIPERX1DATA2": "PCIE_PIPERX1DATA2", - "PIPERX1DATA3": "PCIE_PIPERX1DATA3", - "PIPERX1DATA4": "PCIE_PIPERX1DATA4", - "PIPERX1DATA5": "PCIE_PIPERX1DATA5", - "PIPERX1DATA6": "PCIE_PIPERX1DATA6", - "PIPERX1DATA7": "PCIE_PIPERX1DATA7", - "PIPERX1DATA8": "PCIE_PIPERX1DATA8", - "PIPERX1DATA9": "PCIE_PIPERX1DATA9", - "PIPERX1ELECIDLE": "PCIE_PIPERX1ELECIDLE", - "PIPERX1PHYSTATUS": "PCIE_PIPERX1PHYSTATUS", - "PIPERX1POLARITY": "PCIE_PIPERX1POLARITY", - "PIPERX1STATUS0": "PCIE_PIPERX1STATUS0", - "PIPERX1STATUS1": "PCIE_PIPERX1STATUS1", - "PIPERX1STATUS2": "PCIE_PIPERX1STATUS2", - "PIPERX1VALID": "PCIE_PIPERX1VALID", - "PIPERX2CHANISALIGNED": "PCIE_PIPERX2CHANISALIGNED", - "PIPERX2CHARISK0": "PCIE_PIPERX2CHARISK0", - "PIPERX2CHARISK1": "PCIE_PIPERX2CHARISK1", - "PIPERX2DATA0": "PCIE_PIPERX2DATA0", - "PIPERX2DATA1": "PCIE_PIPERX2DATA1", - "PIPERX2DATA10": "PCIE_PIPERX2DATA10", - "PIPERX2DATA11": "PCIE_PIPERX2DATA11", - "PIPERX2DATA12": "PCIE_PIPERX2DATA12", - "PIPERX2DATA13": "PCIE_PIPERX2DATA13", - "PIPERX2DATA14": "PCIE_PIPERX2DATA14", - "PIPERX2DATA15": "PCIE_PIPERX2DATA15", - "PIPERX2DATA2": "PCIE_PIPERX2DATA2", - "PIPERX2DATA3": "PCIE_PIPERX2DATA3", - "PIPERX2DATA4": "PCIE_PIPERX2DATA4", - "PIPERX2DATA5": "PCIE_PIPERX2DATA5", - "PIPERX2DATA6": "PCIE_PIPERX2DATA6", - "PIPERX2DATA7": "PCIE_PIPERX2DATA7", - "PIPERX2DATA8": "PCIE_PIPERX2DATA8", - "PIPERX2DATA9": "PCIE_PIPERX2DATA9", - "PIPERX2ELECIDLE": "PCIE_PIPERX2ELECIDLE", - "PIPERX2PHYSTATUS": "PCIE_PIPERX2PHYSTATUS", - "PIPERX2POLARITY": "PCIE_PIPERX2POLARITY", - "PIPERX2STATUS0": "PCIE_PIPERX2STATUS0", - "PIPERX2STATUS1": "PCIE_PIPERX2STATUS1", - "PIPERX2STATUS2": "PCIE_PIPERX2STATUS2", - "PIPERX2VALID": "PCIE_PIPERX2VALID", - "PIPERX3CHANISALIGNED": "PCIE_PIPERX3CHANISALIGNED", - "PIPERX3CHARISK0": "PCIE_PIPERX3CHARISK0", - "PIPERX3CHARISK1": "PCIE_PIPERX3CHARISK1", - "PIPERX3DATA0": "PCIE_PIPERX3DATA0", - "PIPERX3DATA1": "PCIE_PIPERX3DATA1", - "PIPERX3DATA10": "PCIE_PIPERX3DATA10", - "PIPERX3DATA11": "PCIE_PIPERX3DATA11", - "PIPERX3DATA12": "PCIE_PIPERX3DATA12", - "PIPERX3DATA13": "PCIE_PIPERX3DATA13", - "PIPERX3DATA14": "PCIE_PIPERX3DATA14", - "PIPERX3DATA15": "PCIE_PIPERX3DATA15", - "PIPERX3DATA2": "PCIE_PIPERX3DATA2", - "PIPERX3DATA3": "PCIE_PIPERX3DATA3", - "PIPERX3DATA4": "PCIE_PIPERX3DATA4", - "PIPERX3DATA5": "PCIE_PIPERX3DATA5", - "PIPERX3DATA6": "PCIE_PIPERX3DATA6", - "PIPERX3DATA7": "PCIE_PIPERX3DATA7", - "PIPERX3DATA8": "PCIE_PIPERX3DATA8", - "PIPERX3DATA9": "PCIE_PIPERX3DATA9", - "PIPERX3ELECIDLE": "PCIE_PIPERX3ELECIDLE", - "PIPERX3PHYSTATUS": "PCIE_PIPERX3PHYSTATUS", - "PIPERX3POLARITY": "PCIE_PIPERX3POLARITY", - "PIPERX3STATUS0": "PCIE_PIPERX3STATUS0", - "PIPERX3STATUS1": "PCIE_PIPERX3STATUS1", - "PIPERX3STATUS2": "PCIE_PIPERX3STATUS2", - "PIPERX3VALID": "PCIE_PIPERX3VALID", - "PIPERX4CHANISALIGNED": "PCIE_PIPERX4CHANISALIGNED", - "PIPERX4CHARISK0": "PCIE_PIPERX4CHARISK0", - "PIPERX4CHARISK1": "PCIE_PIPERX4CHARISK1", - "PIPERX4DATA0": "PCIE_PIPERX4DATA0", - "PIPERX4DATA1": "PCIE_PIPERX4DATA1", - "PIPERX4DATA10": "PCIE_PIPERX4DATA10", - "PIPERX4DATA11": "PCIE_PIPERX4DATA11", - "PIPERX4DATA12": "PCIE_PIPERX4DATA12", - "PIPERX4DATA13": "PCIE_PIPERX4DATA13", - "PIPERX4DATA14": "PCIE_PIPERX4DATA14", - "PIPERX4DATA15": "PCIE_PIPERX4DATA15", - "PIPERX4DATA2": "PCIE_PIPERX4DATA2", - "PIPERX4DATA3": "PCIE_PIPERX4DATA3", - "PIPERX4DATA4": "PCIE_PIPERX4DATA4", - "PIPERX4DATA5": "PCIE_PIPERX4DATA5", - "PIPERX4DATA6": "PCIE_PIPERX4DATA6", - "PIPERX4DATA7": "PCIE_PIPERX4DATA7", - "PIPERX4DATA8": "PCIE_PIPERX4DATA8", - "PIPERX4DATA9": "PCIE_PIPERX4DATA9", - "PIPERX4ELECIDLE": "PCIE_PIPERX4ELECIDLE", - "PIPERX4PHYSTATUS": "PCIE_PIPERX4PHYSTATUS", - "PIPERX4POLARITY": "PCIE_PIPERX4POLARITY", - "PIPERX4STATUS0": "PCIE_PIPERX4STATUS0", - "PIPERX4STATUS1": "PCIE_PIPERX4STATUS1", - "PIPERX4STATUS2": "PCIE_PIPERX4STATUS2", - "PIPERX4VALID": "PCIE_PIPERX4VALID", - "PIPERX5CHANISALIGNED": "PCIE_PIPERX5CHANISALIGNED", - "PIPERX5CHARISK0": "PCIE_PIPERX5CHARISK0", - "PIPERX5CHARISK1": "PCIE_PIPERX5CHARISK1", - "PIPERX5DATA0": "PCIE_PIPERX5DATA0", - "PIPERX5DATA1": "PCIE_PIPERX5DATA1", - "PIPERX5DATA10": "PCIE_PIPERX5DATA10", - "PIPERX5DATA11": "PCIE_PIPERX5DATA11", - "PIPERX5DATA12": "PCIE_PIPERX5DATA12", - "PIPERX5DATA13": "PCIE_PIPERX5DATA13", - "PIPERX5DATA14": "PCIE_PIPERX5DATA14", - "PIPERX5DATA15": "PCIE_PIPERX5DATA15", - "PIPERX5DATA2": "PCIE_PIPERX5DATA2", - "PIPERX5DATA3": "PCIE_PIPERX5DATA3", - "PIPERX5DATA4": "PCIE_PIPERX5DATA4", - "PIPERX5DATA5": "PCIE_PIPERX5DATA5", - "PIPERX5DATA6": "PCIE_PIPERX5DATA6", - "PIPERX5DATA7": "PCIE_PIPERX5DATA7", - "PIPERX5DATA8": "PCIE_PIPERX5DATA8", - "PIPERX5DATA9": "PCIE_PIPERX5DATA9", - "PIPERX5ELECIDLE": "PCIE_PIPERX5ELECIDLE", - "PIPERX5PHYSTATUS": "PCIE_PIPERX5PHYSTATUS", - "PIPERX5POLARITY": "PCIE_PIPERX5POLARITY", - "PIPERX5STATUS0": "PCIE_PIPERX5STATUS0", - "PIPERX5STATUS1": "PCIE_PIPERX5STATUS1", - "PIPERX5STATUS2": "PCIE_PIPERX5STATUS2", - "PIPERX5VALID": "PCIE_PIPERX5VALID", - "PIPERX6CHANISALIGNED": "PCIE_PIPERX6CHANISALIGNED", - "PIPERX6CHARISK0": "PCIE_PIPERX6CHARISK0", - "PIPERX6CHARISK1": "PCIE_PIPERX6CHARISK1", - "PIPERX6DATA0": "PCIE_PIPERX6DATA0", - "PIPERX6DATA1": "PCIE_PIPERX6DATA1", - "PIPERX6DATA10": "PCIE_PIPERX6DATA10", - "PIPERX6DATA11": "PCIE_PIPERX6DATA11", - "PIPERX6DATA12": "PCIE_PIPERX6DATA12", - "PIPERX6DATA13": "PCIE_PIPERX6DATA13", - "PIPERX6DATA14": "PCIE_PIPERX6DATA14", - "PIPERX6DATA15": "PCIE_PIPERX6DATA15", - "PIPERX6DATA2": "PCIE_PIPERX6DATA2", - "PIPERX6DATA3": "PCIE_PIPERX6DATA3", - "PIPERX6DATA4": "PCIE_PIPERX6DATA4", - "PIPERX6DATA5": "PCIE_PIPERX6DATA5", - "PIPERX6DATA6": "PCIE_PIPERX6DATA6", - "PIPERX6DATA7": "PCIE_PIPERX6DATA7", - "PIPERX6DATA8": "PCIE_PIPERX6DATA8", - "PIPERX6DATA9": "PCIE_PIPERX6DATA9", - "PIPERX6ELECIDLE": "PCIE_PIPERX6ELECIDLE", - "PIPERX6PHYSTATUS": "PCIE_PIPERX6PHYSTATUS", - "PIPERX6POLARITY": "PCIE_PIPERX6POLARITY", - "PIPERX6STATUS0": "PCIE_PIPERX6STATUS0", - "PIPERX6STATUS1": "PCIE_PIPERX6STATUS1", - "PIPERX6STATUS2": "PCIE_PIPERX6STATUS2", - "PIPERX6VALID": "PCIE_PIPERX6VALID", - "PIPERX7CHANISALIGNED": "PCIE_PIPERX7CHANISALIGNED", - "PIPERX7CHARISK0": "PCIE_PIPERX7CHARISK0", - "PIPERX7CHARISK1": "PCIE_PIPERX7CHARISK1", - "PIPERX7DATA0": "PCIE_PIPERX7DATA0", - "PIPERX7DATA1": "PCIE_PIPERX7DATA1", - "PIPERX7DATA10": "PCIE_PIPERX7DATA10", - "PIPERX7DATA11": "PCIE_PIPERX7DATA11", - "PIPERX7DATA12": "PCIE_PIPERX7DATA12", - "PIPERX7DATA13": "PCIE_PIPERX7DATA13", - "PIPERX7DATA14": "PCIE_PIPERX7DATA14", - "PIPERX7DATA15": "PCIE_PIPERX7DATA15", - "PIPERX7DATA2": "PCIE_PIPERX7DATA2", - "PIPERX7DATA3": "PCIE_PIPERX7DATA3", - "PIPERX7DATA4": "PCIE_PIPERX7DATA4", - "PIPERX7DATA5": "PCIE_PIPERX7DATA5", - "PIPERX7DATA6": "PCIE_PIPERX7DATA6", - "PIPERX7DATA7": "PCIE_PIPERX7DATA7", - "PIPERX7DATA8": "PCIE_PIPERX7DATA8", - "PIPERX7DATA9": "PCIE_PIPERX7DATA9", - "PIPERX7ELECIDLE": "PCIE_PIPERX7ELECIDLE", - "PIPERX7PHYSTATUS": "PCIE_PIPERX7PHYSTATUS", - "PIPERX7POLARITY": "PCIE_PIPERX7POLARITY", - "PIPERX7STATUS0": "PCIE_PIPERX7STATUS0", - "PIPERX7STATUS1": "PCIE_PIPERX7STATUS1", - "PIPERX7STATUS2": "PCIE_PIPERX7STATUS2", - "PIPERX7VALID": "PCIE_PIPERX7VALID", - "PIPETX0CHARISK0": "PCIE_PIPETX0CHARISK0", - "PIPETX0CHARISK1": "PCIE_PIPETX0CHARISK1", - "PIPETX0COMPLIANCE": "PCIE_PIPETX0COMPLIANCE", - "PIPETX0DATA0": "PCIE_PIPETX0DATA0", - "PIPETX0DATA1": "PCIE_PIPETX0DATA1", - "PIPETX0DATA10": "PCIE_PIPETX0DATA10", - "PIPETX0DATA11": "PCIE_PIPETX0DATA11", - "PIPETX0DATA12": "PCIE_PIPETX0DATA12", - "PIPETX0DATA13": "PCIE_PIPETX0DATA13", - "PIPETX0DATA14": "PCIE_PIPETX0DATA14", - "PIPETX0DATA15": "PCIE_PIPETX0DATA15", - "PIPETX0DATA2": "PCIE_PIPETX0DATA2", - "PIPETX0DATA3": "PCIE_PIPETX0DATA3", - "PIPETX0DATA4": "PCIE_PIPETX0DATA4", - "PIPETX0DATA5": "PCIE_PIPETX0DATA5", - "PIPETX0DATA6": "PCIE_PIPETX0DATA6", - "PIPETX0DATA7": "PCIE_PIPETX0DATA7", - "PIPETX0DATA8": "PCIE_PIPETX0DATA8", - "PIPETX0DATA9": "PCIE_PIPETX0DATA9", - "PIPETX0ELECIDLE": "PCIE_PIPETX0ELECIDLE", - "PIPETX0POWERDOWN0": "PCIE_PIPETX0POWERDOWN0", - "PIPETX0POWERDOWN1": "PCIE_PIPETX0POWERDOWN1", - "PIPETX1CHARISK0": "PCIE_PIPETX1CHARISK0", - "PIPETX1CHARISK1": "PCIE_PIPETX1CHARISK1", - "PIPETX1COMPLIANCE": "PCIE_PIPETX1COMPLIANCE", - "PIPETX1DATA0": "PCIE_PIPETX1DATA0", - "PIPETX1DATA1": "PCIE_PIPETX1DATA1", - "PIPETX1DATA10": "PCIE_PIPETX1DATA10", - "PIPETX1DATA11": "PCIE_PIPETX1DATA11", - "PIPETX1DATA12": "PCIE_PIPETX1DATA12", - "PIPETX1DATA13": "PCIE_PIPETX1DATA13", - "PIPETX1DATA14": "PCIE_PIPETX1DATA14", - "PIPETX1DATA15": "PCIE_PIPETX1DATA15", - "PIPETX1DATA2": "PCIE_PIPETX1DATA2", - "PIPETX1DATA3": "PCIE_PIPETX1DATA3", - "PIPETX1DATA4": "PCIE_PIPETX1DATA4", - "PIPETX1DATA5": "PCIE_PIPETX1DATA5", - "PIPETX1DATA6": "PCIE_PIPETX1DATA6", - "PIPETX1DATA7": "PCIE_PIPETX1DATA7", - "PIPETX1DATA8": "PCIE_PIPETX1DATA8", - "PIPETX1DATA9": "PCIE_PIPETX1DATA9", - "PIPETX1ELECIDLE": "PCIE_PIPETX1ELECIDLE", - "PIPETX1POWERDOWN0": "PCIE_PIPETX1POWERDOWN0", - "PIPETX1POWERDOWN1": "PCIE_PIPETX1POWERDOWN1", - "PIPETX2CHARISK0": "PCIE_PIPETX2CHARISK0", - "PIPETX2CHARISK1": "PCIE_PIPETX2CHARISK1", - "PIPETX2COMPLIANCE": "PCIE_PIPETX2COMPLIANCE", - "PIPETX2DATA0": "PCIE_PIPETX2DATA0", - "PIPETX2DATA1": "PCIE_PIPETX2DATA1", - "PIPETX2DATA10": "PCIE_PIPETX2DATA10", - "PIPETX2DATA11": "PCIE_PIPETX2DATA11", - "PIPETX2DATA12": "PCIE_PIPETX2DATA12", - "PIPETX2DATA13": "PCIE_PIPETX2DATA13", - "PIPETX2DATA14": "PCIE_PIPETX2DATA14", - "PIPETX2DATA15": "PCIE_PIPETX2DATA15", - "PIPETX2DATA2": "PCIE_PIPETX2DATA2", - "PIPETX2DATA3": "PCIE_PIPETX2DATA3", - "PIPETX2DATA4": "PCIE_PIPETX2DATA4", - "PIPETX2DATA5": "PCIE_PIPETX2DATA5", - "PIPETX2DATA6": "PCIE_PIPETX2DATA6", - "PIPETX2DATA7": "PCIE_PIPETX2DATA7", - "PIPETX2DATA8": "PCIE_PIPETX2DATA8", - "PIPETX2DATA9": "PCIE_PIPETX2DATA9", - "PIPETX2ELECIDLE": "PCIE_PIPETX2ELECIDLE", - "PIPETX2POWERDOWN0": "PCIE_PIPETX2POWERDOWN0", - "PIPETX2POWERDOWN1": "PCIE_PIPETX2POWERDOWN1", - "PIPETX3CHARISK0": "PCIE_PIPETX3CHARISK0", - "PIPETX3CHARISK1": "PCIE_PIPETX3CHARISK1", - "PIPETX3COMPLIANCE": "PCIE_PIPETX3COMPLIANCE", - "PIPETX3DATA0": "PCIE_PIPETX3DATA0", - "PIPETX3DATA1": "PCIE_PIPETX3DATA1", - "PIPETX3DATA10": "PCIE_PIPETX3DATA10", - "PIPETX3DATA11": "PCIE_PIPETX3DATA11", - "PIPETX3DATA12": "PCIE_PIPETX3DATA12", - "PIPETX3DATA13": "PCIE_PIPETX3DATA13", - "PIPETX3DATA14": "PCIE_PIPETX3DATA14", - "PIPETX3DATA15": "PCIE_PIPETX3DATA15", - "PIPETX3DATA2": "PCIE_PIPETX3DATA2", - "PIPETX3DATA3": "PCIE_PIPETX3DATA3", - "PIPETX3DATA4": "PCIE_PIPETX3DATA4", - "PIPETX3DATA5": "PCIE_PIPETX3DATA5", - "PIPETX3DATA6": "PCIE_PIPETX3DATA6", - "PIPETX3DATA7": "PCIE_PIPETX3DATA7", - "PIPETX3DATA8": "PCIE_PIPETX3DATA8", - "PIPETX3DATA9": "PCIE_PIPETX3DATA9", - "PIPETX3ELECIDLE": "PCIE_PIPETX3ELECIDLE", - "PIPETX3POWERDOWN0": "PCIE_PIPETX3POWERDOWN0", - "PIPETX3POWERDOWN1": "PCIE_PIPETX3POWERDOWN1", - "PIPETX4CHARISK0": "PCIE_PIPETX4CHARISK0", - "PIPETX4CHARISK1": "PCIE_PIPETX4CHARISK1", - "PIPETX4COMPLIANCE": "PCIE_PIPETX4COMPLIANCE", - "PIPETX4DATA0": "PCIE_PIPETX4DATA0", - "PIPETX4DATA1": "PCIE_PIPETX4DATA1", - "PIPETX4DATA10": "PCIE_PIPETX4DATA10", - "PIPETX4DATA11": "PCIE_PIPETX4DATA11", - "PIPETX4DATA12": "PCIE_PIPETX4DATA12", - "PIPETX4DATA13": "PCIE_PIPETX4DATA13", - "PIPETX4DATA14": "PCIE_PIPETX4DATA14", - "PIPETX4DATA15": "PCIE_PIPETX4DATA15", - "PIPETX4DATA2": "PCIE_PIPETX4DATA2", - "PIPETX4DATA3": "PCIE_PIPETX4DATA3", - "PIPETX4DATA4": "PCIE_PIPETX4DATA4", - "PIPETX4DATA5": "PCIE_PIPETX4DATA5", - "PIPETX4DATA6": "PCIE_PIPETX4DATA6", - "PIPETX4DATA7": "PCIE_PIPETX4DATA7", - "PIPETX4DATA8": "PCIE_PIPETX4DATA8", - "PIPETX4DATA9": "PCIE_PIPETX4DATA9", - "PIPETX4ELECIDLE": "PCIE_PIPETX4ELECIDLE", - "PIPETX4POWERDOWN0": "PCIE_PIPETX4POWERDOWN0", - "PIPETX4POWERDOWN1": "PCIE_PIPETX4POWERDOWN1", - "PIPETX5CHARISK0": "PCIE_PIPETX5CHARISK0", - "PIPETX5CHARISK1": "PCIE_PIPETX5CHARISK1", - "PIPETX5COMPLIANCE": "PCIE_PIPETX5COMPLIANCE", - "PIPETX5DATA0": "PCIE_PIPETX5DATA0", - "PIPETX5DATA1": "PCIE_PIPETX5DATA1", - "PIPETX5DATA10": "PCIE_PIPETX5DATA10", - "PIPETX5DATA11": "PCIE_PIPETX5DATA11", - "PIPETX5DATA12": "PCIE_PIPETX5DATA12", - "PIPETX5DATA13": "PCIE_PIPETX5DATA13", - "PIPETX5DATA14": "PCIE_PIPETX5DATA14", - "PIPETX5DATA15": "PCIE_PIPETX5DATA15", - "PIPETX5DATA2": "PCIE_PIPETX5DATA2", - "PIPETX5DATA3": "PCIE_PIPETX5DATA3", - "PIPETX5DATA4": "PCIE_PIPETX5DATA4", - "PIPETX5DATA5": "PCIE_PIPETX5DATA5", - "PIPETX5DATA6": "PCIE_PIPETX5DATA6", - "PIPETX5DATA7": "PCIE_PIPETX5DATA7", - "PIPETX5DATA8": "PCIE_PIPETX5DATA8", - "PIPETX5DATA9": "PCIE_PIPETX5DATA9", - "PIPETX5ELECIDLE": "PCIE_PIPETX5ELECIDLE", - "PIPETX5POWERDOWN0": "PCIE_PIPETX5POWERDOWN0", - "PIPETX5POWERDOWN1": "PCIE_PIPETX5POWERDOWN1", - "PIPETX6CHARISK0": "PCIE_PIPETX6CHARISK0", - "PIPETX6CHARISK1": "PCIE_PIPETX6CHARISK1", - "PIPETX6COMPLIANCE": "PCIE_PIPETX6COMPLIANCE", - "PIPETX6DATA0": "PCIE_PIPETX6DATA0", - "PIPETX6DATA1": "PCIE_PIPETX6DATA1", - "PIPETX6DATA10": "PCIE_PIPETX6DATA10", - "PIPETX6DATA11": "PCIE_PIPETX6DATA11", - "PIPETX6DATA12": "PCIE_PIPETX6DATA12", - "PIPETX6DATA13": "PCIE_PIPETX6DATA13", - "PIPETX6DATA14": "PCIE_PIPETX6DATA14", - "PIPETX6DATA15": "PCIE_PIPETX6DATA15", - "PIPETX6DATA2": "PCIE_PIPETX6DATA2", - "PIPETX6DATA3": "PCIE_PIPETX6DATA3", - "PIPETX6DATA4": "PCIE_PIPETX6DATA4", - "PIPETX6DATA5": "PCIE_PIPETX6DATA5", - "PIPETX6DATA6": "PCIE_PIPETX6DATA6", - "PIPETX6DATA7": "PCIE_PIPETX6DATA7", - "PIPETX6DATA8": "PCIE_PIPETX6DATA8", - "PIPETX6DATA9": "PCIE_PIPETX6DATA9", - "PIPETX6ELECIDLE": "PCIE_PIPETX6ELECIDLE", - "PIPETX6POWERDOWN0": "PCIE_PIPETX6POWERDOWN0", - "PIPETX6POWERDOWN1": "PCIE_PIPETX6POWERDOWN1", - "PIPETX7CHARISK0": "PCIE_PIPETX7CHARISK0", - "PIPETX7CHARISK1": "PCIE_PIPETX7CHARISK1", - "PIPETX7COMPLIANCE": "PCIE_PIPETX7COMPLIANCE", - "PIPETX7DATA0": "PCIE_PIPETX7DATA0", - "PIPETX7DATA1": "PCIE_PIPETX7DATA1", - "PIPETX7DATA10": "PCIE_PIPETX7DATA10", - "PIPETX7DATA11": "PCIE_PIPETX7DATA11", - "PIPETX7DATA12": "PCIE_PIPETX7DATA12", - "PIPETX7DATA13": "PCIE_PIPETX7DATA13", - "PIPETX7DATA14": "PCIE_PIPETX7DATA14", - "PIPETX7DATA15": "PCIE_PIPETX7DATA15", - "PIPETX7DATA2": "PCIE_PIPETX7DATA2", - "PIPETX7DATA3": "PCIE_PIPETX7DATA3", - "PIPETX7DATA4": "PCIE_PIPETX7DATA4", - "PIPETX7DATA5": "PCIE_PIPETX7DATA5", - "PIPETX7DATA6": "PCIE_PIPETX7DATA6", - "PIPETX7DATA7": "PCIE_PIPETX7DATA7", - "PIPETX7DATA8": "PCIE_PIPETX7DATA8", - "PIPETX7DATA9": "PCIE_PIPETX7DATA9", - "PIPETX7ELECIDLE": "PCIE_PIPETX7ELECIDLE", - "PIPETX7POWERDOWN0": "PCIE_PIPETX7POWERDOWN0", - "PIPETX7POWERDOWN1": "PCIE_PIPETX7POWERDOWN1", - "PIPETXDEEMPH": "PCIE_PIPETXDEEMPH", - "PIPETXMARGIN0": "PCIE_PIPETXMARGIN0", - "PIPETXMARGIN1": "PCIE_PIPETXMARGIN1", - "PIPETXMARGIN2": "PCIE_PIPETXMARGIN2", - "PIPETXRATE": "PCIE_PIPETXRATE", - "PIPETXRCVRDET": "PCIE_PIPETXRCVRDET", - "PIPETXRESET": "PCIE_PIPETXRESET", - "PL2DIRECTEDLSTATE0": "PCIE_PL2DIRECTEDLSTATE0", - "PL2DIRECTEDLSTATE1": "PCIE_PL2DIRECTEDLSTATE1", - "PL2DIRECTEDLSTATE2": "PCIE_PL2DIRECTEDLSTATE2", - "PL2DIRECTEDLSTATE3": "PCIE_PL2DIRECTEDLSTATE3", - "PL2DIRECTEDLSTATE4": "PCIE_PL2DIRECTEDLSTATE4", - "PL2L0REQ": "PCIE_PL2L0REQ", - "PL2LINKUP": "PCIE_PL2LINKUP", - "PL2RECEIVERERR": "PCIE_PL2RECEIVERERR", - "PL2RECOVERY": "PCIE_PL2RECOVERY", - "PL2RXELECIDLE": "PCIE_PL2RXELECIDLE", - "PL2RXPMSTATE0": "PCIE_PL2RXPMSTATE0", - "PL2RXPMSTATE1": "PCIE_PL2RXPMSTATE1", - "PL2SUSPENDOK": "PCIE_PL2SUSPENDOK", - "PLDBGMODE0": "PCIE_PLDBGMODE0", - "PLDBGMODE1": "PCIE_PLDBGMODE1", - "PLDBGMODE2": "PCIE_PLDBGMODE2", - "PLDBGVEC0": "PCIE_PLDBGVEC0", - "PLDBGVEC1": "PCIE_PLDBGVEC1", - "PLDBGVEC10": "PCIE_PLDBGVEC10", - "PLDBGVEC11": "PCIE_PLDBGVEC11", - "PLDBGVEC2": "PCIE_PLDBGVEC2", - "PLDBGVEC3": "PCIE_PLDBGVEC3", - "PLDBGVEC4": "PCIE_PLDBGVEC4", - "PLDBGVEC5": "PCIE_PLDBGVEC5", - "PLDBGVEC6": "PCIE_PLDBGVEC6", - "PLDBGVEC7": "PCIE_PLDBGVEC7", - "PLDBGVEC8": "PCIE_PLDBGVEC8", - "PLDBGVEC9": "PCIE_PLDBGVEC9", - "PLDIRECTEDCHANGEDONE": "PCIE_PLDIRECTEDCHANGEDONE", - "PLDIRECTEDLINKAUTON": "PCIE_PLDIRECTEDLINKAUTON", - "PLDIRECTEDLINKCHANGE0": "PCIE_PLDIRECTEDLINKCHANGE0", - "PLDIRECTEDLINKCHANGE1": "PCIE_PLDIRECTEDLINKCHANGE1", - "PLDIRECTEDLINKSPEED": "PCIE_PLDIRECTEDLINKSPEED", - "PLDIRECTEDLINKWIDTH0": "PCIE_PLDIRECTEDLINKWIDTH0", - "PLDIRECTEDLINKWIDTH1": "PCIE_PLDIRECTEDLINKWIDTH1", - "PLDIRECTEDLTSSMNEW0": "PCIE_PLDIRECTEDLTSSMNEW0", - "PLDIRECTEDLTSSMNEW1": "PCIE_PLDIRECTEDLTSSMNEW1", - "PLDIRECTEDLTSSMNEW2": "PCIE_PLDIRECTEDLTSSMNEW2", - "PLDIRECTEDLTSSMNEW3": "PCIE_PLDIRECTEDLTSSMNEW3", - "PLDIRECTEDLTSSMNEW4": "PCIE_PLDIRECTEDLTSSMNEW4", - "PLDIRECTEDLTSSMNEW5": "PCIE_PLDIRECTEDLTSSMNEW5", - "PLDIRECTEDLTSSMNEWVLD": "PCIE_PLDIRECTEDLTSSMNEWVLD", - "PLDIRECTEDLTSSMSTALL": "PCIE_PLDIRECTEDLTSSMSTALL", - "PLDOWNSTREAMDEEMPHSOURCE": "PCIE_PLDOWNSTREAMDEEMPHSOURCE", - "PLINITIALLINKWIDTH0": "PCIE_PLINITIALLINKWIDTH0", - "PLINITIALLINKWIDTH1": "PCIE_PLINITIALLINKWIDTH1", - "PLINITIALLINKWIDTH2": "PCIE_PLINITIALLINKWIDTH2", - "PLLANEREVERSALMODE0": "PCIE_PLLANEREVERSALMODE0", - "PLLANEREVERSALMODE1": "PCIE_PLLANEREVERSALMODE1", - "PLLINKGEN2CAP": "PCIE_PLLINKGEN2CAP", - "PLLINKPARTNERGEN2SUPPORTED": "PCIE_PLLINKPARTNERGEN2SUPPORTED", - "PLLINKUPCFGCAP": "PCIE_PLLINKUPCFGCAP", - "PLLTSSMSTATE0": "PCIE_PLLTSSMSTATE0", - "PLLTSSMSTATE1": "PCIE_PLLTSSMSTATE1", - "PLLTSSMSTATE2": "PCIE_PLLTSSMSTATE2", - "PLLTSSMSTATE3": "PCIE_PLLTSSMSTATE3", - "PLLTSSMSTATE4": "PCIE_PLLTSSMSTATE4", - "PLLTSSMSTATE5": "PCIE_PLLTSSMSTATE5", - "PLPHYLNKUPN": "PCIE_PLPHYLNKUPN", - "PLRECEIVEDHOTRST": "PCIE_PLRECEIVEDHOTRST", - "PLRSTN": "PCIE_PLRSTN", - "PLRXPMSTATE0": "PCIE_PLRXPMSTATE0", - "PLRXPMSTATE1": "PCIE_PLRXPMSTATE1", - "PLSELLNKRATE": "PCIE_PLSELLNKRATE", - "PLSELLNKWIDTH0": "PCIE_PLSELLNKWIDTH0", - "PLSELLNKWIDTH1": "PCIE_PLSELLNKWIDTH1", - "PLTRANSMITHOTRST": "PCIE_PLTRANSMITHOTRST", - "PLTXPMSTATE0": "PCIE_PLTXPMSTATE0", - "PLTXPMSTATE1": "PCIE_PLTXPMSTATE1", - "PLTXPMSTATE2": "PCIE_PLTXPMSTATE2", - "PLUPSTREAMPREFERDEEMPH": "PCIE_PLUPSTREAMPREFERDEEMPH", - "PMVDIVIDE0": "PCIE_PMVDIVIDE0", - "PMVDIVIDE1": "PCIE_PMVDIVIDE1", - "PMVENABLEN": "PCIE_PMVENABLEN", - "PMVOUT": "PCIE_PMVOUT", - "PMVSELECT0": "PCIE_PMVSELECT0", - "PMVSELECT1": "PCIE_PMVSELECT1", - "PMVSELECT2": "PCIE_PMVSELECT2", - "RECEIVEDFUNCLVLRSTN": "PCIE_RECEIVEDFUNCLVLRSTN", - "SCANENABLEN": "PCIE_SCANENABLEN", - "SCANMODEN": "PCIE_SCANMODEN", - "SYSRSTN": "PCIE_SYSRSTN", - "TL2ASPMSUSPENDCREDITCHECK": "PCIE_TL2ASPMSUSPENDCREDITCHECK", - "TL2ASPMSUSPENDCREDITCHECKOK": "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", - "TL2ASPMSUSPENDREQ": "PCIE_TL2ASPMSUSPENDREQ", - "TL2ERRFCPE": "PCIE_TL2ERRFCPE", - "TL2ERRHDR0": "PCIE_TL2ERRHDR0", - "TL2ERRHDR1": "PCIE_TL2ERRHDR1", - "TL2ERRHDR10": "PCIE_TL2ERRHDR10", - "TL2ERRHDR11": "PCIE_TL2ERRHDR11", - "TL2ERRHDR12": "PCIE_TL2ERRHDR12", - "TL2ERRHDR13": "PCIE_TL2ERRHDR13", - "TL2ERRHDR14": "PCIE_TL2ERRHDR14", - "TL2ERRHDR15": "PCIE_TL2ERRHDR15", - "TL2ERRHDR16": "PCIE_TL2ERRHDR16", - "TL2ERRHDR17": "PCIE_TL2ERRHDR17", - "TL2ERRHDR18": "PCIE_TL2ERRHDR18", - "TL2ERRHDR19": "PCIE_TL2ERRHDR19", - "TL2ERRHDR2": "PCIE_TL2ERRHDR2", - "TL2ERRHDR20": "PCIE_TL2ERRHDR20", - "TL2ERRHDR21": "PCIE_TL2ERRHDR21", - "TL2ERRHDR22": "PCIE_TL2ERRHDR22", - "TL2ERRHDR23": "PCIE_TL2ERRHDR23", - "TL2ERRHDR24": "PCIE_TL2ERRHDR24", - "TL2ERRHDR25": "PCIE_TL2ERRHDR25", - "TL2ERRHDR26": "PCIE_TL2ERRHDR26", - "TL2ERRHDR27": "PCIE_TL2ERRHDR27", - "TL2ERRHDR28": "PCIE_TL2ERRHDR28", - "TL2ERRHDR29": "PCIE_TL2ERRHDR29", - "TL2ERRHDR3": "PCIE_TL2ERRHDR3", - "TL2ERRHDR30": "PCIE_TL2ERRHDR30", - "TL2ERRHDR31": "PCIE_TL2ERRHDR31", - "TL2ERRHDR32": "PCIE_TL2ERRHDR32", - "TL2ERRHDR33": "PCIE_TL2ERRHDR33", - "TL2ERRHDR34": "PCIE_TL2ERRHDR34", - "TL2ERRHDR35": "PCIE_TL2ERRHDR35", - "TL2ERRHDR36": "PCIE_TL2ERRHDR36", - "TL2ERRHDR37": "PCIE_TL2ERRHDR37", - "TL2ERRHDR38": "PCIE_TL2ERRHDR38", - "TL2ERRHDR39": "PCIE_TL2ERRHDR39", - "TL2ERRHDR4": "PCIE_TL2ERRHDR4", - "TL2ERRHDR40": "PCIE_TL2ERRHDR40", - "TL2ERRHDR41": "PCIE_TL2ERRHDR41", - "TL2ERRHDR42": "PCIE_TL2ERRHDR42", - "TL2ERRHDR43": "PCIE_TL2ERRHDR43", - "TL2ERRHDR44": "PCIE_TL2ERRHDR44", - "TL2ERRHDR45": "PCIE_TL2ERRHDR45", - "TL2ERRHDR46": "PCIE_TL2ERRHDR46", - "TL2ERRHDR47": "PCIE_TL2ERRHDR47", - "TL2ERRHDR48": "PCIE_TL2ERRHDR48", - "TL2ERRHDR49": "PCIE_TL2ERRHDR49", - "TL2ERRHDR5": "PCIE_TL2ERRHDR5", - "TL2ERRHDR50": "PCIE_TL2ERRHDR50", - "TL2ERRHDR51": "PCIE_TL2ERRHDR51", - "TL2ERRHDR52": "PCIE_TL2ERRHDR52", - "TL2ERRHDR53": "PCIE_TL2ERRHDR53", - "TL2ERRHDR54": "PCIE_TL2ERRHDR54", - "TL2ERRHDR55": "PCIE_TL2ERRHDR55", - "TL2ERRHDR56": "PCIE_TL2ERRHDR56", - "TL2ERRHDR57": "PCIE_TL2ERRHDR57", - "TL2ERRHDR58": "PCIE_TL2ERRHDR58", - "TL2ERRHDR59": "PCIE_TL2ERRHDR59", - "TL2ERRHDR6": "PCIE_TL2ERRHDR6", - "TL2ERRHDR60": "PCIE_TL2ERRHDR60", - "TL2ERRHDR61": "PCIE_TL2ERRHDR61", - "TL2ERRHDR62": "PCIE_TL2ERRHDR62", - "TL2ERRHDR63": "PCIE_TL2ERRHDR63", - "TL2ERRHDR7": "PCIE_TL2ERRHDR7", - "TL2ERRHDR8": "PCIE_TL2ERRHDR8", - "TL2ERRHDR9": "PCIE_TL2ERRHDR9", - "TL2ERRMALFORMED": "PCIE_TL2ERRMALFORMED", - "TL2ERRRXOVERFLOW": "PCIE_TL2ERRRXOVERFLOW", - "TL2PPMSUSPENDOK": "PCIE_TL2PPMSUSPENDOK", - "TL2PPMSUSPENDREQ": "PCIE_TL2PPMSUSPENDREQ", - "TLRSTN": "PCIE_TLRSTN", - "TRNFCCPLD0": "PCIE_TRNFCCPLD0", - "TRNFCCPLD1": "PCIE_TRNFCCPLD1", - "TRNFCCPLD10": "PCIE_TRNFCCPLD10", - "TRNFCCPLD11": "PCIE_TRNFCCPLD11", - "TRNFCCPLD2": "PCIE_TRNFCCPLD2", - "TRNFCCPLD3": "PCIE_TRNFCCPLD3", - "TRNFCCPLD4": "PCIE_TRNFCCPLD4", - "TRNFCCPLD5": "PCIE_TRNFCCPLD5", - "TRNFCCPLD6": "PCIE_TRNFCCPLD6", - "TRNFCCPLD7": "PCIE_TRNFCCPLD7", - "TRNFCCPLD8": "PCIE_TRNFCCPLD8", - "TRNFCCPLD9": "PCIE_TRNFCCPLD9", - "TRNFCCPLH0": "PCIE_TRNFCCPLH0", - "TRNFCCPLH1": "PCIE_TRNFCCPLH1", - "TRNFCCPLH2": "PCIE_TRNFCCPLH2", - "TRNFCCPLH3": "PCIE_TRNFCCPLH3", - "TRNFCCPLH4": "PCIE_TRNFCCPLH4", - "TRNFCCPLH5": "PCIE_TRNFCCPLH5", - "TRNFCCPLH6": "PCIE_TRNFCCPLH6", - "TRNFCCPLH7": "PCIE_TRNFCCPLH7", - "TRNFCNPD0": "PCIE_TRNFCNPD0", - "TRNFCNPD1": "PCIE_TRNFCNPD1", - "TRNFCNPD10": "PCIE_TRNFCNPD10", - "TRNFCNPD11": "PCIE_TRNFCNPD11", - "TRNFCNPD2": "PCIE_TRNFCNPD2", - "TRNFCNPD3": "PCIE_TRNFCNPD3", - "TRNFCNPD4": "PCIE_TRNFCNPD4", - "TRNFCNPD5": "PCIE_TRNFCNPD5", - "TRNFCNPD6": "PCIE_TRNFCNPD6", - "TRNFCNPD7": "PCIE_TRNFCNPD7", - "TRNFCNPD8": "PCIE_TRNFCNPD8", - "TRNFCNPD9": "PCIE_TRNFCNPD9", - "TRNFCNPH0": "PCIE_TRNFCNPH0", - "TRNFCNPH1": "PCIE_TRNFCNPH1", - "TRNFCNPH2": "PCIE_TRNFCNPH2", - "TRNFCNPH3": "PCIE_TRNFCNPH3", - "TRNFCNPH4": "PCIE_TRNFCNPH4", - "TRNFCNPH5": "PCIE_TRNFCNPH5", - "TRNFCNPH6": "PCIE_TRNFCNPH6", - "TRNFCNPH7": "PCIE_TRNFCNPH7", - "TRNFCPD0": "PCIE_TRNFCPD0", - "TRNFCPD1": "PCIE_TRNFCPD1", - "TRNFCPD10": "PCIE_TRNFCPD10", - "TRNFCPD11": "PCIE_TRNFCPD11", - "TRNFCPD2": "PCIE_TRNFCPD2", - "TRNFCPD3": "PCIE_TRNFCPD3", - "TRNFCPD4": "PCIE_TRNFCPD4", - "TRNFCPD5": "PCIE_TRNFCPD5", - "TRNFCPD6": "PCIE_TRNFCPD6", - "TRNFCPD7": "PCIE_TRNFCPD7", - "TRNFCPD8": "PCIE_TRNFCPD8", - "TRNFCPD9": "PCIE_TRNFCPD9", - "TRNFCPH0": "PCIE_TRNFCPH0", - "TRNFCPH1": "PCIE_TRNFCPH1", - "TRNFCPH2": "PCIE_TRNFCPH2", - "TRNFCPH3": "PCIE_TRNFCPH3", - "TRNFCPH4": "PCIE_TRNFCPH4", - "TRNFCPH5": "PCIE_TRNFCPH5", - "TRNFCPH6": "PCIE_TRNFCPH6", - "TRNFCPH7": "PCIE_TRNFCPH7", - "TRNFCSEL0": "PCIE_TRNFCSEL0", - "TRNFCSEL1": "PCIE_TRNFCSEL1", - "TRNFCSEL2": "PCIE_TRNFCSEL2", - "TRNLNKUP": "PCIE_TRNLNKUP", - "TRNRBARHIT0": "PCIE_TRNRBARHIT0", - "TRNRBARHIT1": "PCIE_TRNRBARHIT1", - "TRNRBARHIT2": "PCIE_TRNRBARHIT2", - "TRNRBARHIT3": "PCIE_TRNRBARHIT3", - "TRNRBARHIT4": "PCIE_TRNRBARHIT4", - "TRNRBARHIT5": "PCIE_TRNRBARHIT5", - "TRNRBARHIT6": "PCIE_TRNRBARHIT6", - "TRNRBARHIT7": "PCIE_TRNRBARHIT7", - "TRNRD0": "PCIE_TRNRD0", - "TRNRD1": "PCIE_TRNRD1", - "TRNRD10": "PCIE_TRNRD10", - "TRNRD100": "PCIE_TRNRD100", - "TRNRD101": "PCIE_TRNRD101", - "TRNRD102": "PCIE_TRNRD102", - "TRNRD103": "PCIE_TRNRD103", - "TRNRD104": "PCIE_TRNRD104", - "TRNRD105": "PCIE_TRNRD105", - "TRNRD106": "PCIE_TRNRD106", - "TRNRD107": "PCIE_TRNRD107", - "TRNRD108": "PCIE_TRNRD108", - "TRNRD109": "PCIE_TRNRD109", - "TRNRD11": "PCIE_TRNRD11", - "TRNRD110": "PCIE_TRNRD110", - "TRNRD111": "PCIE_TRNRD111", - "TRNRD112": "PCIE_TRNRD112", - "TRNRD113": "PCIE_TRNRD113", - "TRNRD114": "PCIE_TRNRD114", - "TRNRD115": "PCIE_TRNRD115", - "TRNRD116": "PCIE_TRNRD116", - "TRNRD117": "PCIE_TRNRD117", - "TRNRD118": "PCIE_TRNRD118", - "TRNRD119": "PCIE_TRNRD119", - "TRNRD12": "PCIE_TRNRD12", - "TRNRD120": "PCIE_TRNRD120", - "TRNRD121": "PCIE_TRNRD121", - "TRNRD122": "PCIE_TRNRD122", - "TRNRD123": "PCIE_TRNRD123", - "TRNRD124": "PCIE_TRNRD124", - "TRNRD125": "PCIE_TRNRD125", - "TRNRD126": "PCIE_TRNRD126", - "TRNRD127": "PCIE_TRNRD127", - "TRNRD13": "PCIE_TRNRD13", - "TRNRD14": "PCIE_TRNRD14", - "TRNRD15": "PCIE_TRNRD15", - "TRNRD16": "PCIE_TRNRD16", - "TRNRD17": "PCIE_TRNRD17", - "TRNRD18": "PCIE_TRNRD18", - "TRNRD19": "PCIE_TRNRD19", - "TRNRD2": "PCIE_TRNRD2", - "TRNRD20": "PCIE_TRNRD20", - "TRNRD21": "PCIE_TRNRD21", - "TRNRD22": "PCIE_TRNRD22", - "TRNRD23": "PCIE_TRNRD23", - "TRNRD24": "PCIE_TRNRD24", - "TRNRD25": "PCIE_TRNRD25", - "TRNRD26": "PCIE_TRNRD26", - "TRNRD27": "PCIE_TRNRD27", - "TRNRD28": "PCIE_TRNRD28", - "TRNRD29": "PCIE_TRNRD29", - "TRNRD3": "PCIE_TRNRD3", - "TRNRD30": "PCIE_TRNRD30", - "TRNRD31": "PCIE_TRNRD31", - "TRNRD32": "PCIE_TRNRD32", - "TRNRD33": "PCIE_TRNRD33", - "TRNRD34": "PCIE_TRNRD34", - "TRNRD35": "PCIE_TRNRD35", - "TRNRD36": "PCIE_TRNRD36", - "TRNRD37": "PCIE_TRNRD37", - "TRNRD38": "PCIE_TRNRD38", - "TRNRD39": "PCIE_TRNRD39", - "TRNRD4": "PCIE_TRNRD4", - "TRNRD40": "PCIE_TRNRD40", - "TRNRD41": "PCIE_TRNRD41", - "TRNRD42": "PCIE_TRNRD42", - "TRNRD43": "PCIE_TRNRD43", - "TRNRD44": "PCIE_TRNRD44", - "TRNRD45": "PCIE_TRNRD45", - "TRNRD46": "PCIE_TRNRD46", - "TRNRD47": "PCIE_TRNRD47", - "TRNRD48": "PCIE_TRNRD48", - "TRNRD49": "PCIE_TRNRD49", - "TRNRD5": "PCIE_TRNRD5", - "TRNRD50": "PCIE_TRNRD50", - "TRNRD51": "PCIE_TRNRD51", - "TRNRD52": "PCIE_TRNRD52", - "TRNRD53": "PCIE_TRNRD53", - "TRNRD54": "PCIE_TRNRD54", - "TRNRD55": "PCIE_TRNRD55", - "TRNRD56": "PCIE_TRNRD56", - "TRNRD57": "PCIE_TRNRD57", - "TRNRD58": "PCIE_TRNRD58", - "TRNRD59": "PCIE_TRNRD59", - "TRNRD6": "PCIE_TRNRD6", - "TRNRD60": "PCIE_TRNRD60", - "TRNRD61": "PCIE_TRNRD61", - "TRNRD62": "PCIE_TRNRD62", - "TRNRD63": "PCIE_TRNRD63", - "TRNRD64": "PCIE_TRNRD64", - "TRNRD65": "PCIE_TRNRD65", - "TRNRD66": "PCIE_TRNRD66", - "TRNRD67": "PCIE_TRNRD67", - "TRNRD68": "PCIE_TRNRD68", - "TRNRD69": "PCIE_TRNRD69", - "TRNRD7": "PCIE_TRNRD7", - "TRNRD70": "PCIE_TRNRD70", - "TRNRD71": "PCIE_TRNRD71", - "TRNRD72": "PCIE_TRNRD72", - "TRNRD73": "PCIE_TRNRD73", - "TRNRD74": "PCIE_TRNRD74", - "TRNRD75": "PCIE_TRNRD75", - "TRNRD76": "PCIE_TRNRD76", - "TRNRD77": "PCIE_TRNRD77", - "TRNRD78": "PCIE_TRNRD78", - "TRNRD79": "PCIE_TRNRD79", - "TRNRD8": "PCIE_TRNRD8", - "TRNRD80": "PCIE_TRNRD80", - "TRNRD81": "PCIE_TRNRD81", - "TRNRD82": "PCIE_TRNRD82", - "TRNRD83": "PCIE_TRNRD83", - "TRNRD84": "PCIE_TRNRD84", - "TRNRD85": "PCIE_TRNRD85", - "TRNRD86": "PCIE_TRNRD86", - "TRNRD87": "PCIE_TRNRD87", - "TRNRD88": "PCIE_TRNRD88", - "TRNRD89": "PCIE_TRNRD89", - "TRNRD9": "PCIE_TRNRD9", - "TRNRD90": "PCIE_TRNRD90", - "TRNRD91": "PCIE_TRNRD91", - "TRNRD92": "PCIE_TRNRD92", - "TRNRD93": "PCIE_TRNRD93", - "TRNRD94": "PCIE_TRNRD94", - "TRNRD95": "PCIE_TRNRD95", - "TRNRD96": "PCIE_TRNRD96", - "TRNRD97": "PCIE_TRNRD97", - "TRNRD98": "PCIE_TRNRD98", - "TRNRD99": "PCIE_TRNRD99", - "TRNRDLLPDATA0": "PCIE_TRNRDLLPDATA0", - "TRNRDLLPDATA1": "PCIE_TRNRDLLPDATA1", - "TRNRDLLPDATA10": "PCIE_TRNRDLLPDATA10", - "TRNRDLLPDATA11": "PCIE_TRNRDLLPDATA11", - "TRNRDLLPDATA12": "PCIE_TRNRDLLPDATA12", - "TRNRDLLPDATA13": "PCIE_TRNRDLLPDATA13", - "TRNRDLLPDATA14": "PCIE_TRNRDLLPDATA14", - "TRNRDLLPDATA15": "PCIE_TRNRDLLPDATA15", - "TRNRDLLPDATA16": "PCIE_TRNRDLLPDATA16", - "TRNRDLLPDATA17": "PCIE_TRNRDLLPDATA17", - "TRNRDLLPDATA18": "PCIE_TRNRDLLPDATA18", - "TRNRDLLPDATA19": "PCIE_TRNRDLLPDATA19", - "TRNRDLLPDATA2": "PCIE_TRNRDLLPDATA2", - "TRNRDLLPDATA20": "PCIE_TRNRDLLPDATA20", - "TRNRDLLPDATA21": "PCIE_TRNRDLLPDATA21", - "TRNRDLLPDATA22": "PCIE_TRNRDLLPDATA22", - "TRNRDLLPDATA23": "PCIE_TRNRDLLPDATA23", - "TRNRDLLPDATA24": "PCIE_TRNRDLLPDATA24", - "TRNRDLLPDATA25": "PCIE_TRNRDLLPDATA25", - "TRNRDLLPDATA26": "PCIE_TRNRDLLPDATA26", - "TRNRDLLPDATA27": "PCIE_TRNRDLLPDATA27", - "TRNRDLLPDATA28": "PCIE_TRNRDLLPDATA28", - "TRNRDLLPDATA29": "PCIE_TRNRDLLPDATA29", - "TRNRDLLPDATA3": "PCIE_TRNRDLLPDATA3", - "TRNRDLLPDATA30": "PCIE_TRNRDLLPDATA30", - "TRNRDLLPDATA31": "PCIE_TRNRDLLPDATA31", - "TRNRDLLPDATA32": "PCIE_TRNRDLLPDATA32", - "TRNRDLLPDATA33": "PCIE_TRNRDLLPDATA33", - "TRNRDLLPDATA34": "PCIE_TRNRDLLPDATA34", - "TRNRDLLPDATA35": "PCIE_TRNRDLLPDATA35", - "TRNRDLLPDATA36": "PCIE_TRNRDLLPDATA36", - "TRNRDLLPDATA37": "PCIE_TRNRDLLPDATA37", - "TRNRDLLPDATA38": "PCIE_TRNRDLLPDATA38", - "TRNRDLLPDATA39": "PCIE_TRNRDLLPDATA39", - "TRNRDLLPDATA4": "PCIE_TRNRDLLPDATA4", - "TRNRDLLPDATA40": "PCIE_TRNRDLLPDATA40", - "TRNRDLLPDATA41": "PCIE_TRNRDLLPDATA41", - "TRNRDLLPDATA42": "PCIE_TRNRDLLPDATA42", - "TRNRDLLPDATA43": "PCIE_TRNRDLLPDATA43", - "TRNRDLLPDATA44": "PCIE_TRNRDLLPDATA44", - "TRNRDLLPDATA45": "PCIE_TRNRDLLPDATA45", - "TRNRDLLPDATA46": "PCIE_TRNRDLLPDATA46", - "TRNRDLLPDATA47": "PCIE_TRNRDLLPDATA47", - "TRNRDLLPDATA48": "PCIE_TRNRDLLPDATA48", - "TRNRDLLPDATA49": "PCIE_TRNRDLLPDATA49", - "TRNRDLLPDATA5": "PCIE_TRNRDLLPDATA5", - "TRNRDLLPDATA50": "PCIE_TRNRDLLPDATA50", - "TRNRDLLPDATA51": "PCIE_TRNRDLLPDATA51", - "TRNRDLLPDATA52": "PCIE_TRNRDLLPDATA52", - "TRNRDLLPDATA53": "PCIE_TRNRDLLPDATA53", - "TRNRDLLPDATA54": "PCIE_TRNRDLLPDATA54", - "TRNRDLLPDATA55": "PCIE_TRNRDLLPDATA55", - "TRNRDLLPDATA56": "PCIE_TRNRDLLPDATA56", - "TRNRDLLPDATA57": "PCIE_TRNRDLLPDATA57", - "TRNRDLLPDATA58": "PCIE_TRNRDLLPDATA58", - "TRNRDLLPDATA59": "PCIE_TRNRDLLPDATA59", - "TRNRDLLPDATA6": "PCIE_TRNRDLLPDATA6", - "TRNRDLLPDATA60": "PCIE_TRNRDLLPDATA60", - "TRNRDLLPDATA61": "PCIE_TRNRDLLPDATA61", - "TRNRDLLPDATA62": "PCIE_TRNRDLLPDATA62", - "TRNRDLLPDATA63": "PCIE_TRNRDLLPDATA63", - "TRNRDLLPDATA7": "PCIE_TRNRDLLPDATA7", - "TRNRDLLPDATA8": "PCIE_TRNRDLLPDATA8", - "TRNRDLLPDATA9": "PCIE_TRNRDLLPDATA9", - "TRNRDLLPSRCRDY0": "PCIE_TRNRDLLPSRCRDY0", - "TRNRDLLPSRCRDY1": "PCIE_TRNRDLLPSRCRDY1", - "TRNRDSTRDY": "PCIE_TRNRDSTRDY", - "TRNRECRCERR": "PCIE_TRNRECRCERR", - "TRNREOF": "PCIE_TRNREOF", - "TRNRERRFWD": "PCIE_TRNRERRFWD", - "TRNRFCPRET": "PCIE_TRNRFCPRET", - "TRNRNPOK": "PCIE_TRNRNPOK", - "TRNRNPREQ": "PCIE_TRNRNPREQ", - "TRNRREM0": "PCIE_TRNRREM0", - "TRNRREM1": "PCIE_TRNRREM1", - "TRNRSOF": "PCIE_TRNRSOF", - "TRNRSRCDSC": "PCIE_TRNRSRCDSC", - "TRNRSRCRDY": "PCIE_TRNRSRCRDY", - "TRNTBUFAV0": "PCIE_TRNTBUFAV0", - "TRNTBUFAV1": "PCIE_TRNTBUFAV1", - "TRNTBUFAV2": "PCIE_TRNTBUFAV2", - "TRNTBUFAV3": "PCIE_TRNTBUFAV3", - "TRNTBUFAV4": "PCIE_TRNTBUFAV4", - "TRNTBUFAV5": "PCIE_TRNTBUFAV5", - "TRNTCFGGNT": "PCIE_TRNTCFGGNT", - "TRNTCFGREQ": "PCIE_TRNTCFGREQ", - "TRNTD0": "PCIE_TRNTD0", - "TRNTD1": "PCIE_TRNTD1", - "TRNTD10": "PCIE_TRNTD10", - "TRNTD100": "PCIE_TRNTD100", - "TRNTD101": "PCIE_TRNTD101", - "TRNTD102": "PCIE_TRNTD102", - "TRNTD103": "PCIE_TRNTD103", - "TRNTD104": "PCIE_TRNTD104", - "TRNTD105": "PCIE_TRNTD105", - "TRNTD106": "PCIE_TRNTD106", - "TRNTD107": "PCIE_TRNTD107", - "TRNTD108": "PCIE_TRNTD108", - "TRNTD109": "PCIE_TRNTD109", - "TRNTD11": "PCIE_TRNTD11", - "TRNTD110": "PCIE_TRNTD110", - "TRNTD111": "PCIE_TRNTD111", - "TRNTD112": "PCIE_TRNTD112", - "TRNTD113": "PCIE_TRNTD113", - "TRNTD114": "PCIE_TRNTD114", - "TRNTD115": "PCIE_TRNTD115", - "TRNTD116": "PCIE_TRNTD116", - "TRNTD117": "PCIE_TRNTD117", - "TRNTD118": "PCIE_TRNTD118", - "TRNTD119": "PCIE_TRNTD119", - "TRNTD12": "PCIE_TRNTD12", - "TRNTD120": "PCIE_TRNTD120", - "TRNTD121": "PCIE_TRNTD121", - "TRNTD122": "PCIE_TRNTD122", - "TRNTD123": "PCIE_TRNTD123", - "TRNTD124": "PCIE_TRNTD124", - "TRNTD125": "PCIE_TRNTD125", - "TRNTD126": "PCIE_TRNTD126", - "TRNTD127": "PCIE_TRNTD127", - "TRNTD13": "PCIE_TRNTD13", - "TRNTD14": "PCIE_TRNTD14", - "TRNTD15": "PCIE_TRNTD15", - "TRNTD16": "PCIE_TRNTD16", - "TRNTD17": "PCIE_TRNTD17", - "TRNTD18": "PCIE_TRNTD18", - "TRNTD19": "PCIE_TRNTD19", - "TRNTD2": "PCIE_TRNTD2", - "TRNTD20": "PCIE_TRNTD20", - "TRNTD21": "PCIE_TRNTD21", - "TRNTD22": "PCIE_TRNTD22", - "TRNTD23": "PCIE_TRNTD23", - "TRNTD24": "PCIE_TRNTD24", - "TRNTD25": "PCIE_TRNTD25", - "TRNTD26": "PCIE_TRNTD26", - "TRNTD27": "PCIE_TRNTD27", - "TRNTD28": "PCIE_TRNTD28", - "TRNTD29": "PCIE_TRNTD29", - "TRNTD3": "PCIE_TRNTD3", - "TRNTD30": "PCIE_TRNTD30", - "TRNTD31": "PCIE_TRNTD31", - "TRNTD32": "PCIE_TRNTD32", - "TRNTD33": "PCIE_TRNTD33", - "TRNTD34": "PCIE_TRNTD34", - "TRNTD35": "PCIE_TRNTD35", - "TRNTD36": "PCIE_TRNTD36", - "TRNTD37": "PCIE_TRNTD37", - "TRNTD38": "PCIE_TRNTD38", - "TRNTD39": "PCIE_TRNTD39", - "TRNTD4": "PCIE_TRNTD4", - "TRNTD40": "PCIE_TRNTD40", - "TRNTD41": "PCIE_TRNTD41", - "TRNTD42": "PCIE_TRNTD42", - "TRNTD43": "PCIE_TRNTD43", - "TRNTD44": "PCIE_TRNTD44", - "TRNTD45": "PCIE_TRNTD45", - "TRNTD46": "PCIE_TRNTD46", - "TRNTD47": "PCIE_TRNTD47", - "TRNTD48": "PCIE_TRNTD48", - "TRNTD49": "PCIE_TRNTD49", - "TRNTD5": "PCIE_TRNTD5", - "TRNTD50": "PCIE_TRNTD50", - "TRNTD51": "PCIE_TRNTD51", - "TRNTD52": "PCIE_TRNTD52", - "TRNTD53": "PCIE_TRNTD53", - "TRNTD54": "PCIE_TRNTD54", - "TRNTD55": "PCIE_TRNTD55", - "TRNTD56": "PCIE_TRNTD56", - "TRNTD57": "PCIE_TRNTD57", - "TRNTD58": "PCIE_TRNTD58", - "TRNTD59": "PCIE_TRNTD59", - "TRNTD6": "PCIE_TRNTD6", - "TRNTD60": "PCIE_TRNTD60", - "TRNTD61": "PCIE_TRNTD61", - "TRNTD62": "PCIE_TRNTD62", - "TRNTD63": "PCIE_TRNTD63", - "TRNTD64": "PCIE_TRNTD64", - "TRNTD65": "PCIE_TRNTD65", - "TRNTD66": "PCIE_TRNTD66", - "TRNTD67": "PCIE_TRNTD67", - "TRNTD68": "PCIE_TRNTD68", - "TRNTD69": "PCIE_TRNTD69", - "TRNTD7": "PCIE_TRNTD7", - "TRNTD70": "PCIE_TRNTD70", - "TRNTD71": "PCIE_TRNTD71", - "TRNTD72": "PCIE_TRNTD72", - "TRNTD73": "PCIE_TRNTD73", - "TRNTD74": "PCIE_TRNTD74", - "TRNTD75": "PCIE_TRNTD75", - "TRNTD76": "PCIE_TRNTD76", - "TRNTD77": "PCIE_TRNTD77", - "TRNTD78": "PCIE_TRNTD78", - "TRNTD79": "PCIE_TRNTD79", - "TRNTD8": "PCIE_TRNTD8", - "TRNTD80": "PCIE_TRNTD80", - "TRNTD81": "PCIE_TRNTD81", - "TRNTD82": "PCIE_TRNTD82", - "TRNTD83": "PCIE_TRNTD83", - "TRNTD84": "PCIE_TRNTD84", - "TRNTD85": "PCIE_TRNTD85", - "TRNTD86": "PCIE_TRNTD86", - "TRNTD87": "PCIE_TRNTD87", - "TRNTD88": "PCIE_TRNTD88", - "TRNTD89": "PCIE_TRNTD89", - "TRNTD9": "PCIE_TRNTD9", - "TRNTD90": "PCIE_TRNTD90", - "TRNTD91": "PCIE_TRNTD91", - "TRNTD92": "PCIE_TRNTD92", - "TRNTD93": "PCIE_TRNTD93", - "TRNTD94": "PCIE_TRNTD94", - "TRNTD95": "PCIE_TRNTD95", - "TRNTD96": "PCIE_TRNTD96", - "TRNTD97": "PCIE_TRNTD97", - "TRNTD98": "PCIE_TRNTD98", - "TRNTD99": "PCIE_TRNTD99", - "TRNTDLLPDATA0": "PCIE_TRNTDLLPDATA0", - "TRNTDLLPDATA1": "PCIE_TRNTDLLPDATA1", - "TRNTDLLPDATA10": "PCIE_TRNTDLLPDATA10", - "TRNTDLLPDATA11": "PCIE_TRNTDLLPDATA11", - "TRNTDLLPDATA12": "PCIE_TRNTDLLPDATA12", - "TRNTDLLPDATA13": "PCIE_TRNTDLLPDATA13", - "TRNTDLLPDATA14": "PCIE_TRNTDLLPDATA14", - "TRNTDLLPDATA15": "PCIE_TRNTDLLPDATA15", - "TRNTDLLPDATA16": "PCIE_TRNTDLLPDATA16", - "TRNTDLLPDATA17": "PCIE_TRNTDLLPDATA17", - "TRNTDLLPDATA18": "PCIE_TRNTDLLPDATA18", - "TRNTDLLPDATA19": "PCIE_TRNTDLLPDATA19", - "TRNTDLLPDATA2": "PCIE_TRNTDLLPDATA2", - "TRNTDLLPDATA20": "PCIE_TRNTDLLPDATA20", - "TRNTDLLPDATA21": "PCIE_TRNTDLLPDATA21", - "TRNTDLLPDATA22": "PCIE_TRNTDLLPDATA22", - "TRNTDLLPDATA23": "PCIE_TRNTDLLPDATA23", - "TRNTDLLPDATA24": "PCIE_TRNTDLLPDATA24", - "TRNTDLLPDATA25": "PCIE_TRNTDLLPDATA25", - "TRNTDLLPDATA26": "PCIE_TRNTDLLPDATA26", - "TRNTDLLPDATA27": "PCIE_TRNTDLLPDATA27", - "TRNTDLLPDATA28": "PCIE_TRNTDLLPDATA28", - "TRNTDLLPDATA29": "PCIE_TRNTDLLPDATA29", - "TRNTDLLPDATA3": "PCIE_TRNTDLLPDATA3", - "TRNTDLLPDATA30": "PCIE_TRNTDLLPDATA30", - "TRNTDLLPDATA31": "PCIE_TRNTDLLPDATA31", - "TRNTDLLPDATA4": "PCIE_TRNTDLLPDATA4", - "TRNTDLLPDATA5": "PCIE_TRNTDLLPDATA5", - "TRNTDLLPDATA6": "PCIE_TRNTDLLPDATA6", - "TRNTDLLPDATA7": "PCIE_TRNTDLLPDATA7", - "TRNTDLLPDATA8": "PCIE_TRNTDLLPDATA8", - "TRNTDLLPDATA9": "PCIE_TRNTDLLPDATA9", - "TRNTDLLPDSTRDY": "PCIE_TRNTDLLPDSTRDY", - "TRNTDLLPSRCRDY": "PCIE_TRNTDLLPSRCRDY", - "TRNTDSTRDY0": "PCIE_TRNTDSTRDY0", - "TRNTDSTRDY1": "PCIE_TRNTDSTRDY1", - "TRNTDSTRDY2": "PCIE_TRNTDSTRDY2", - "TRNTDSTRDY3": "PCIE_TRNTDSTRDY3", - "TRNTECRCGEN": "PCIE_TRNTECRCGEN", - "TRNTEOF": "PCIE_TRNTEOF", - "TRNTERRDROP": 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"PCIE_BLOCK_OUTS_B0_L_17", - "PCIE_BLOCK_OUTS_B0_L_18", - "PCIE_BLOCK_OUTS_B0_L_19", - "PCIE_BLOCK_OUTS_B0_L_2", - "PCIE_BLOCK_OUTS_B0_L_3", - "PCIE_BLOCK_OUTS_B0_L_4", - "PCIE_BLOCK_OUTS_B0_L_5", - "PCIE_BLOCK_OUTS_B0_L_6", - "PCIE_BLOCK_OUTS_B0_L_7", - "PCIE_BLOCK_OUTS_B0_L_8", - "PCIE_BLOCK_OUTS_B0_L_9", - "PCIE_BLOCK_OUTS_B0_R_0", - "PCIE_BLOCK_OUTS_B0_R_1", - "PCIE_BLOCK_OUTS_B0_R_10", - "PCIE_BLOCK_OUTS_B0_R_11", - "PCIE_BLOCK_OUTS_B0_R_12", - "PCIE_BLOCK_OUTS_B0_R_13", - "PCIE_BLOCK_OUTS_B0_R_14", - "PCIE_BLOCK_OUTS_B0_R_15", - "PCIE_BLOCK_OUTS_B0_R_16", - "PCIE_BLOCK_OUTS_B0_R_17", - "PCIE_BLOCK_OUTS_B0_R_18", - "PCIE_BLOCK_OUTS_B0_R_19", - "PCIE_BLOCK_OUTS_B0_R_2", - "PCIE_BLOCK_OUTS_B0_R_3", - "PCIE_BLOCK_OUTS_B0_R_4", - "PCIE_BLOCK_OUTS_B0_R_5", - "PCIE_BLOCK_OUTS_B0_R_6", - "PCIE_BLOCK_OUTS_B0_R_7", - "PCIE_BLOCK_OUTS_B0_R_8", - "PCIE_BLOCK_OUTS_B0_R_9", - "PCIE_BLOCK_OUTS_B1_L_0", - "PCIE_BLOCK_OUTS_B1_L_1", - "PCIE_BLOCK_OUTS_B1_L_10", - "PCIE_BLOCK_OUTS_B1_L_11", - "PCIE_BLOCK_OUTS_B1_L_12", - "PCIE_BLOCK_OUTS_B1_L_13", - "PCIE_BLOCK_OUTS_B1_L_14", - "PCIE_BLOCK_OUTS_B1_L_15", - "PCIE_BLOCK_OUTS_B1_L_16", - "PCIE_BLOCK_OUTS_B1_L_17", - "PCIE_BLOCK_OUTS_B1_L_18", - "PCIE_BLOCK_OUTS_B1_L_19", - "PCIE_BLOCK_OUTS_B1_L_2", - "PCIE_BLOCK_OUTS_B1_L_3", - "PCIE_BLOCK_OUTS_B1_L_4", - "PCIE_BLOCK_OUTS_B1_L_5", - "PCIE_BLOCK_OUTS_B1_L_6", - "PCIE_BLOCK_OUTS_B1_L_7", - "PCIE_BLOCK_OUTS_B1_L_8", - "PCIE_BLOCK_OUTS_B1_L_9", - "PCIE_BLOCK_OUTS_B1_R_0", - "PCIE_BLOCK_OUTS_B1_R_1", - "PCIE_BLOCK_OUTS_B1_R_10", - "PCIE_BLOCK_OUTS_B1_R_11", - "PCIE_BLOCK_OUTS_B1_R_12", - "PCIE_BLOCK_OUTS_B1_R_13", - "PCIE_BLOCK_OUTS_B1_R_14", - "PCIE_BLOCK_OUTS_B1_R_15", - "PCIE_BLOCK_OUTS_B1_R_16", - "PCIE_BLOCK_OUTS_B1_R_17", - "PCIE_BLOCK_OUTS_B1_R_18", - "PCIE_BLOCK_OUTS_B1_R_19", - "PCIE_BLOCK_OUTS_B1_R_2", - "PCIE_BLOCK_OUTS_B1_R_3", - "PCIE_BLOCK_OUTS_B1_R_4", - "PCIE_BLOCK_OUTS_B1_R_5", - "PCIE_BLOCK_OUTS_B1_R_6", - "PCIE_BLOCK_OUTS_B1_R_7", - "PCIE_BLOCK_OUTS_B1_R_8", - "PCIE_BLOCK_OUTS_B1_R_9", - "PCIE_BLOCK_OUTS_B2_L_0", - "PCIE_BLOCK_OUTS_B2_L_1", - "PCIE_BLOCK_OUTS_B2_L_10", - "PCIE_BLOCK_OUTS_B2_L_11", - "PCIE_BLOCK_OUTS_B2_L_12", - "PCIE_BLOCK_OUTS_B2_L_13", - "PCIE_BLOCK_OUTS_B2_L_14", - "PCIE_BLOCK_OUTS_B2_L_15", - "PCIE_BLOCK_OUTS_B2_L_16", - "PCIE_BLOCK_OUTS_B2_L_17", - "PCIE_BLOCK_OUTS_B2_L_18", - "PCIE_BLOCK_OUTS_B2_L_19", - "PCIE_BLOCK_OUTS_B2_L_2", - "PCIE_BLOCK_OUTS_B2_L_3", - "PCIE_BLOCK_OUTS_B2_L_4", - "PCIE_BLOCK_OUTS_B2_L_5", - "PCIE_BLOCK_OUTS_B2_L_6", - "PCIE_BLOCK_OUTS_B2_L_7", - "PCIE_BLOCK_OUTS_B2_L_8", - "PCIE_BLOCK_OUTS_B2_L_9", - "PCIE_BLOCK_OUTS_B2_R_0", - "PCIE_BLOCK_OUTS_B2_R_1", - "PCIE_BLOCK_OUTS_B2_R_10", - "PCIE_BLOCK_OUTS_B2_R_11", - "PCIE_BLOCK_OUTS_B2_R_12", - "PCIE_BLOCK_OUTS_B2_R_13", - "PCIE_BLOCK_OUTS_B2_R_14", - "PCIE_BLOCK_OUTS_B2_R_15", - "PCIE_BLOCK_OUTS_B2_R_16", - "PCIE_BLOCK_OUTS_B2_R_17", - "PCIE_BLOCK_OUTS_B2_R_18", - "PCIE_BLOCK_OUTS_B2_R_19", - "PCIE_BLOCK_OUTS_B2_R_2", - "PCIE_BLOCK_OUTS_B2_R_3", - "PCIE_BLOCK_OUTS_B2_R_4", - "PCIE_BLOCK_OUTS_B2_R_5", - "PCIE_BLOCK_OUTS_B2_R_6", - "PCIE_BLOCK_OUTS_B2_R_7", - "PCIE_BLOCK_OUTS_B2_R_8", - "PCIE_BLOCK_OUTS_B2_R_9", - "PCIE_BLOCK_OUTS_B3_L_0", - "PCIE_BLOCK_OUTS_B3_L_1", - "PCIE_BLOCK_OUTS_B3_L_10", - "PCIE_BLOCK_OUTS_B3_L_11", - "PCIE_BLOCK_OUTS_B3_L_12", - "PCIE_BLOCK_OUTS_B3_L_13", - "PCIE_BLOCK_OUTS_B3_L_14", - "PCIE_BLOCK_OUTS_B3_L_15", - "PCIE_BLOCK_OUTS_B3_L_16", - "PCIE_BLOCK_OUTS_B3_L_17", - "PCIE_BLOCK_OUTS_B3_L_18", - "PCIE_BLOCK_OUTS_B3_L_19", - "PCIE_BLOCK_OUTS_B3_L_2", - "PCIE_BLOCK_OUTS_B3_L_3", - "PCIE_BLOCK_OUTS_B3_L_4", - "PCIE_BLOCK_OUTS_B3_L_5", - "PCIE_BLOCK_OUTS_B3_L_6", - "PCIE_BLOCK_OUTS_B3_L_7", - "PCIE_BLOCK_OUTS_B3_L_8", - "PCIE_BLOCK_OUTS_B3_L_9", - "PCIE_BLOCK_OUTS_B3_R_0", - "PCIE_BLOCK_OUTS_B3_R_1", - "PCIE_BLOCK_OUTS_B3_R_10", - "PCIE_BLOCK_OUTS_B3_R_11", - "PCIE_BLOCK_OUTS_B3_R_12", - "PCIE_BLOCK_OUTS_B3_R_13", - "PCIE_BLOCK_OUTS_B3_R_14", - "PCIE_BLOCK_OUTS_B3_R_15", - "PCIE_BLOCK_OUTS_B3_R_16", - "PCIE_BLOCK_OUTS_B3_R_17", - "PCIE_BLOCK_OUTS_B3_R_18", - "PCIE_BLOCK_OUTS_B3_R_19", - "PCIE_BLOCK_OUTS_B3_R_2", - "PCIE_BLOCK_OUTS_B3_R_3", - "PCIE_BLOCK_OUTS_B3_R_4", - "PCIE_BLOCK_OUTS_B3_R_5", - "PCIE_BLOCK_OUTS_B3_R_6", - "PCIE_BLOCK_OUTS_B3_R_7", - "PCIE_BLOCK_OUTS_B3_R_8", - "PCIE_BLOCK_OUTS_B3_R_9", - "PCIE_BYP0_L_0", - "PCIE_BYP0_L_1", - "PCIE_BYP0_L_10", - "PCIE_BYP0_L_11", - "PCIE_BYP0_L_12", - "PCIE_BYP0_L_13", - "PCIE_BYP0_L_14", - "PCIE_BYP0_L_15", - "PCIE_BYP0_L_16", - "PCIE_BYP0_L_17", - "PCIE_BYP0_L_18", - "PCIE_BYP0_L_19", - "PCIE_BYP0_L_2", - "PCIE_BYP0_L_3", - "PCIE_BYP0_L_4", - "PCIE_BYP0_L_5", - "PCIE_BYP0_L_6", - "PCIE_BYP0_L_7", - "PCIE_BYP0_L_8", - "PCIE_BYP0_L_9", - "PCIE_BYP0_R_0", - "PCIE_BYP0_R_1", - "PCIE_BYP0_R_10", - "PCIE_BYP0_R_11", - "PCIE_BYP0_R_12", - "PCIE_BYP0_R_13", - "PCIE_BYP0_R_14", - "PCIE_BYP0_R_15", - "PCIE_BYP0_R_16", - "PCIE_BYP0_R_17", - "PCIE_BYP0_R_18", - "PCIE_BYP0_R_19", - "PCIE_BYP0_R_2", - "PCIE_BYP0_R_3", - "PCIE_BYP0_R_4", - "PCIE_BYP0_R_5", - "PCIE_BYP0_R_6", - "PCIE_BYP0_R_7", - "PCIE_BYP0_R_8", - "PCIE_BYP0_R_9", - "PCIE_BYP1_L_0", - "PCIE_BYP1_L_1", - "PCIE_BYP1_L_10", - "PCIE_BYP1_L_11", - "PCIE_BYP1_L_12", - "PCIE_BYP1_L_13", - "PCIE_BYP1_L_14", - "PCIE_BYP1_L_15", - "PCIE_BYP1_L_16", - "PCIE_BYP1_L_17", - "PCIE_BYP1_L_18", - "PCIE_BYP1_L_19", - "PCIE_BYP1_L_2", - "PCIE_BYP1_L_3", - "PCIE_BYP1_L_4", - "PCIE_BYP1_L_5", - "PCIE_BYP1_L_6", - "PCIE_BYP1_L_7", - "PCIE_BYP1_L_8", - "PCIE_BYP1_L_9", - "PCIE_BYP1_R_0", - "PCIE_BYP1_R_1", - "PCIE_BYP1_R_10", - "PCIE_BYP1_R_11", - "PCIE_BYP1_R_12", - "PCIE_BYP1_R_13", - "PCIE_BYP1_R_14", - "PCIE_BYP1_R_15", - "PCIE_BYP1_R_16", - "PCIE_BYP1_R_17", - "PCIE_BYP1_R_18", - "PCIE_BYP1_R_19", - "PCIE_BYP1_R_2", - "PCIE_BYP1_R_3", - "PCIE_BYP1_R_4", - "PCIE_BYP1_R_5", - "PCIE_BYP1_R_6", - "PCIE_BYP1_R_7", - "PCIE_BYP1_R_8", - "PCIE_BYP1_R_9", - "PCIE_BYP2_L_0", - "PCIE_BYP2_L_1", - "PCIE_BYP2_L_10", - "PCIE_BYP2_L_11", - "PCIE_BYP2_L_12", - "PCIE_BYP2_L_13", - "PCIE_BYP2_L_14", - "PCIE_BYP2_L_15", - "PCIE_BYP2_L_16", - "PCIE_BYP2_L_17", - "PCIE_BYP2_L_18", - "PCIE_BYP2_L_19", - "PCIE_BYP2_L_2", - "PCIE_BYP2_L_3", - "PCIE_BYP2_L_4", - "PCIE_BYP2_L_5", - "PCIE_BYP2_L_6", - "PCIE_BYP2_L_7", - "PCIE_BYP2_L_8", - "PCIE_BYP2_L_9", - "PCIE_BYP2_R_0", - "PCIE_BYP2_R_1", - "PCIE_BYP2_R_10", - "PCIE_BYP2_R_11", - "PCIE_BYP2_R_12", - "PCIE_BYP2_R_13", - "PCIE_BYP2_R_14", - "PCIE_BYP2_R_15", - "PCIE_BYP2_R_16", - "PCIE_BYP2_R_17", - "PCIE_BYP2_R_18", - "PCIE_BYP2_R_19", - "PCIE_BYP2_R_2", - "PCIE_BYP2_R_3", - "PCIE_BYP2_R_4", - "PCIE_BYP2_R_5", - "PCIE_BYP2_R_6", - "PCIE_BYP2_R_7", - "PCIE_BYP2_R_8", - "PCIE_BYP2_R_9", - "PCIE_BYP3_L_0", - "PCIE_BYP3_L_1", - "PCIE_BYP3_L_10", - "PCIE_BYP3_L_11", - "PCIE_BYP3_L_12", - "PCIE_BYP3_L_13", - "PCIE_BYP3_L_14", - "PCIE_BYP3_L_15", - "PCIE_BYP3_L_16", - "PCIE_BYP3_L_17", - "PCIE_BYP3_L_18", - "PCIE_BYP3_L_19", - "PCIE_BYP3_L_2", - "PCIE_BYP3_L_3", - "PCIE_BYP3_L_4", - "PCIE_BYP3_L_5", - "PCIE_BYP3_L_6", - "PCIE_BYP3_L_7", - "PCIE_BYP3_L_8", - "PCIE_BYP3_L_9", - "PCIE_BYP3_R_0", - "PCIE_BYP3_R_1", - "PCIE_BYP3_R_10", - "PCIE_BYP3_R_11", - "PCIE_BYP3_R_12", - "PCIE_BYP3_R_13", - "PCIE_BYP3_R_14", - "PCIE_BYP3_R_15", - "PCIE_BYP3_R_16", - "PCIE_BYP3_R_17", - "PCIE_BYP3_R_18", - "PCIE_BYP3_R_19", - "PCIE_BYP3_R_2", - "PCIE_BYP3_R_3", - "PCIE_BYP3_R_4", - "PCIE_BYP3_R_5", - "PCIE_BYP3_R_6", - "PCIE_BYP3_R_7", - "PCIE_BYP3_R_8", - "PCIE_BYP3_R_9", - "PCIE_BYP4_L_0", - "PCIE_BYP4_L_1", - "PCIE_BYP4_L_10", - "PCIE_BYP4_L_11", - "PCIE_BYP4_L_12", - "PCIE_BYP4_L_13", - "PCIE_BYP4_L_14", - "PCIE_BYP4_L_15", - "PCIE_BYP4_L_16", - "PCIE_BYP4_L_17", - "PCIE_BYP4_L_18", - "PCIE_BYP4_L_19", - "PCIE_BYP4_L_2", - "PCIE_BYP4_L_3", - "PCIE_BYP4_L_4", - "PCIE_BYP4_L_5", - "PCIE_BYP4_L_6", - "PCIE_BYP4_L_7", - "PCIE_BYP4_L_8", - "PCIE_BYP4_L_9", - "PCIE_BYP4_R_0", - "PCIE_BYP4_R_1", - "PCIE_BYP4_R_10", - "PCIE_BYP4_R_11", - "PCIE_BYP4_R_12", - "PCIE_BYP4_R_13", - "PCIE_BYP4_R_14", - "PCIE_BYP4_R_15", - "PCIE_BYP4_R_16", - "PCIE_BYP4_R_17", - "PCIE_BYP4_R_18", - "PCIE_BYP4_R_19", - "PCIE_BYP4_R_2", - "PCIE_BYP4_R_3", - "PCIE_BYP4_R_4", - "PCIE_BYP4_R_5", - "PCIE_BYP4_R_6", - "PCIE_BYP4_R_7", - "PCIE_BYP4_R_8", - "PCIE_BYP4_R_9", - "PCIE_BYP5_L_0", - "PCIE_BYP5_L_1", - "PCIE_BYP5_L_10", - "PCIE_BYP5_L_11", - "PCIE_BYP5_L_12", - "PCIE_BYP5_L_13", - "PCIE_BYP5_L_14", - "PCIE_BYP5_L_15", - "PCIE_BYP5_L_16", - "PCIE_BYP5_L_17", - "PCIE_BYP5_L_18", - "PCIE_BYP5_L_19", - "PCIE_BYP5_L_2", - "PCIE_BYP5_L_3", - "PCIE_BYP5_L_4", - "PCIE_BYP5_L_5", - "PCIE_BYP5_L_6", - "PCIE_BYP5_L_7", - "PCIE_BYP5_L_8", - "PCIE_BYP5_L_9", - "PCIE_BYP5_R_0", - "PCIE_BYP5_R_1", - "PCIE_BYP5_R_10", - "PCIE_BYP5_R_11", - "PCIE_BYP5_R_12", - "PCIE_BYP5_R_13", - "PCIE_BYP5_R_14", - "PCIE_BYP5_R_15", - "PCIE_BYP5_R_16", - "PCIE_BYP5_R_17", - "PCIE_BYP5_R_18", - "PCIE_BYP5_R_19", - "PCIE_BYP5_R_2", - "PCIE_BYP5_R_3", - "PCIE_BYP5_R_4", - "PCIE_BYP5_R_5", - "PCIE_BYP5_R_6", - "PCIE_BYP5_R_7", - "PCIE_BYP5_R_8", - "PCIE_BYP5_R_9", - "PCIE_BYP6_L_0", - "PCIE_BYP6_L_1", - "PCIE_BYP6_L_10", - "PCIE_BYP6_L_11", - "PCIE_BYP6_L_12", - "PCIE_BYP6_L_13", - "PCIE_BYP6_L_14", - "PCIE_BYP6_L_15", - "PCIE_BYP6_L_16", - "PCIE_BYP6_L_17", - "PCIE_BYP6_L_18", - "PCIE_BYP6_L_19", - "PCIE_BYP6_L_2", - "PCIE_BYP6_L_3", - "PCIE_BYP6_L_4", - "PCIE_BYP6_L_5", - "PCIE_BYP6_L_6", - "PCIE_BYP6_L_7", - "PCIE_BYP6_L_8", - "PCIE_BYP6_L_9", - "PCIE_BYP6_R_0", - "PCIE_BYP6_R_1", - "PCIE_BYP6_R_10", - "PCIE_BYP6_R_11", - "PCIE_BYP6_R_12", - "PCIE_BYP6_R_13", - "PCIE_BYP6_R_14", - "PCIE_BYP6_R_15", - "PCIE_BYP6_R_16", - "PCIE_BYP6_R_17", - "PCIE_BYP6_R_18", - "PCIE_BYP6_R_19", - "PCIE_BYP6_R_2", - "PCIE_BYP6_R_3", - "PCIE_BYP6_R_4", - "PCIE_BYP6_R_5", - "PCIE_BYP6_R_6", - "PCIE_BYP6_R_7", - "PCIE_BYP6_R_8", - "PCIE_BYP6_R_9", - "PCIE_BYP7_L_0", - "PCIE_BYP7_L_1", - "PCIE_BYP7_L_10", - "PCIE_BYP7_L_11", - "PCIE_BYP7_L_12", - "PCIE_BYP7_L_13", - "PCIE_BYP7_L_14", - "PCIE_BYP7_L_15", - "PCIE_BYP7_L_16", - "PCIE_BYP7_L_17", - "PCIE_BYP7_L_18", - "PCIE_BYP7_L_19", - "PCIE_BYP7_L_2", - "PCIE_BYP7_L_3", - "PCIE_BYP7_L_4", - "PCIE_BYP7_L_5", - "PCIE_BYP7_L_6", - "PCIE_BYP7_L_7", - "PCIE_BYP7_L_8", - "PCIE_BYP7_L_9", - "PCIE_BYP7_R_0", - "PCIE_BYP7_R_1", - "PCIE_BYP7_R_10", - "PCIE_BYP7_R_11", - "PCIE_BYP7_R_12", - "PCIE_BYP7_R_13", - "PCIE_BYP7_R_14", - "PCIE_BYP7_R_15", - "PCIE_BYP7_R_16", - "PCIE_BYP7_R_17", - "PCIE_BYP7_R_18", - "PCIE_BYP7_R_19", - "PCIE_BYP7_R_2", - "PCIE_BYP7_R_3", - "PCIE_BYP7_R_4", - "PCIE_BYP7_R_5", - "PCIE_BYP7_R_6", - "PCIE_BYP7_R_7", - "PCIE_BYP7_R_8", - "PCIE_BYP7_R_9", - "PCIE_CFGAERECRCCHECKEN", - "PCIE_CFGAERECRCGENEN", - "PCIE_CFGAERINTERRUPTMSGNUM0", - "PCIE_CFGAERINTERRUPTMSGNUM1", - "PCIE_CFGAERINTERRUPTMSGNUM2", - "PCIE_CFGAERINTERRUPTMSGNUM3", - "PCIE_CFGAERINTERRUPTMSGNUM4", - "PCIE_CFGAERROOTERRCORRERRRECEIVED", - "PCIE_CFGAERROOTERRCORRERRREPORTINGEN", - "PCIE_CFGAERROOTERRFATALERRRECEIVED", - "PCIE_CFGAERROOTERRFATALERRREPORTINGEN", - "PCIE_CFGAERROOTERRNONFATALERRRECEIVED", - "PCIE_CFGAERROOTERRNONFATALERRREPORTINGEN", - "PCIE_CFGBRIDGESERREN", - "PCIE_CFGCOMMANDBUSMASTERENABLE", - "PCIE_CFGCOMMANDINTERRUPTDISABLE", - "PCIE_CFGCOMMANDIOENABLE", - "PCIE_CFGCOMMANDMEMENABLE", - "PCIE_CFGCOMMANDSERREN", - "PCIE_CFGDEVCONTROL2ARIFORWARDEN", - "PCIE_CFGDEVCONTROL2ATOMICEGRESSBLOCK", - "PCIE_CFGDEVCONTROL2ATOMICREQUESTEREN", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTDIS", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL0", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL1", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL2", - "PCIE_CFGDEVCONTROL2CPLTIMEOUTVAL3", - "PCIE_CFGDEVCONTROL2IDOCPLEN", - "PCIE_CFGDEVCONTROL2IDOREQEN", - "PCIE_CFGDEVCONTROL2LTREN", - "PCIE_CFGDEVCONTROL2TLPPREFIXBLOCK", - "PCIE_CFGDEVCONTROLAUXPOWEREN", - "PCIE_CFGDEVCONTROLCORRERRREPORTINGEN", - "PCIE_CFGDEVCONTROLENABLERO", - "PCIE_CFGDEVCONTROLEXTTAGEN", - "PCIE_CFGDEVCONTROLFATALERRREPORTINGEN", - "PCIE_CFGDEVCONTROLMAXPAYLOAD0", - "PCIE_CFGDEVCONTROLMAXPAYLOAD1", - "PCIE_CFGDEVCONTROLMAXPAYLOAD2", - "PCIE_CFGDEVCONTROLMAXREADREQ0", - "PCIE_CFGDEVCONTROLMAXREADREQ1", - "PCIE_CFGDEVCONTROLMAXREADREQ2", - "PCIE_CFGDEVCONTROLNONFATALREPORTINGEN", - "PCIE_CFGDEVCONTROLNOSNOOPEN", - "PCIE_CFGDEVCONTROLPHANTOMEN", - "PCIE_CFGDEVCONTROLURERRREPORTINGEN", - "PCIE_CFGDEVID0", - "PCIE_CFGDEVID1", - "PCIE_CFGDEVID10", - "PCIE_CFGDEVID11", - "PCIE_CFGDEVID12", - "PCIE_CFGDEVID13", - "PCIE_CFGDEVID14", - "PCIE_CFGDEVID15", - "PCIE_CFGDEVID2", - "PCIE_CFGDEVID3", - "PCIE_CFGDEVID4", - "PCIE_CFGDEVID5", - "PCIE_CFGDEVID6", - "PCIE_CFGDEVID7", - "PCIE_CFGDEVID8", - "PCIE_CFGDEVID9", - "PCIE_CFGDEVSTATUSCORRERRDETECTED", - "PCIE_CFGDEVSTATUSFATALERRDETECTED", - "PCIE_CFGDEVSTATUSNONFATALERRDETECTED", - "PCIE_CFGDEVSTATUSURDETECTED", - "PCIE_CFGDSBUSNUMBER0", - "PCIE_CFGDSBUSNUMBER1", - "PCIE_CFGDSBUSNUMBER2", - "PCIE_CFGDSBUSNUMBER3", - "PCIE_CFGDSBUSNUMBER4", - "PCIE_CFGDSBUSNUMBER5", - "PCIE_CFGDSBUSNUMBER6", - "PCIE_CFGDSBUSNUMBER7", - "PCIE_CFGDSDEVICENUMBER0", - "PCIE_CFGDSDEVICENUMBER1", - "PCIE_CFGDSDEVICENUMBER2", - "PCIE_CFGDSDEVICENUMBER3", - "PCIE_CFGDSDEVICENUMBER4", - "PCIE_CFGDSFUNCTIONNUMBER0", - "PCIE_CFGDSFUNCTIONNUMBER1", - "PCIE_CFGDSFUNCTIONNUMBER2", - "PCIE_CFGDSN0", - "PCIE_CFGDSN1", - "PCIE_CFGDSN10", - "PCIE_CFGDSN11", - "PCIE_CFGDSN12", - "PCIE_CFGDSN13", - "PCIE_CFGDSN14", - "PCIE_CFGDSN15", - "PCIE_CFGDSN16", - "PCIE_CFGDSN17", - "PCIE_CFGDSN18", - "PCIE_CFGDSN19", - "PCIE_CFGDSN2", - "PCIE_CFGDSN20", - "PCIE_CFGDSN21", - "PCIE_CFGDSN22", - "PCIE_CFGDSN23", - "PCIE_CFGDSN24", - "PCIE_CFGDSN25", - "PCIE_CFGDSN26", - "PCIE_CFGDSN27", - "PCIE_CFGDSN28", - "PCIE_CFGDSN29", - "PCIE_CFGDSN3", - "PCIE_CFGDSN30", - "PCIE_CFGDSN31", - "PCIE_CFGDSN32", - "PCIE_CFGDSN33", - "PCIE_CFGDSN34", - "PCIE_CFGDSN35", - "PCIE_CFGDSN36", - "PCIE_CFGDSN37", - "PCIE_CFGDSN38", - "PCIE_CFGDSN39", - "PCIE_CFGDSN4", - "PCIE_CFGDSN40", - "PCIE_CFGDSN41", - "PCIE_CFGDSN42", - "PCIE_CFGDSN43", - "PCIE_CFGDSN44", - "PCIE_CFGDSN45", - "PCIE_CFGDSN46", - "PCIE_CFGDSN47", - "PCIE_CFGDSN48", - "PCIE_CFGDSN49", - "PCIE_CFGDSN5", - "PCIE_CFGDSN50", - "PCIE_CFGDSN51", - "PCIE_CFGDSN52", - "PCIE_CFGDSN53", - "PCIE_CFGDSN54", - "PCIE_CFGDSN55", - "PCIE_CFGDSN56", - "PCIE_CFGDSN57", - "PCIE_CFGDSN58", - "PCIE_CFGDSN59", - "PCIE_CFGDSN6", - "PCIE_CFGDSN60", - "PCIE_CFGDSN61", - "PCIE_CFGDSN62", - "PCIE_CFGDSN63", - "PCIE_CFGDSN7", - "PCIE_CFGDSN8", - "PCIE_CFGDSN9", - "PCIE_CFGERRACSN", - "PCIE_CFGERRAERHEADERLOG0", - "PCIE_CFGERRAERHEADERLOG1", - "PCIE_CFGERRAERHEADERLOG10", - "PCIE_CFGERRAERHEADERLOG100", - "PCIE_CFGERRAERHEADERLOG101", - "PCIE_CFGERRAERHEADERLOG102", - "PCIE_CFGERRAERHEADERLOG103", - "PCIE_CFGERRAERHEADERLOG104", - "PCIE_CFGERRAERHEADERLOG105", - "PCIE_CFGERRAERHEADERLOG106", - "PCIE_CFGERRAERHEADERLOG107", - "PCIE_CFGERRAERHEADERLOG108", - "PCIE_CFGERRAERHEADERLOG109", - "PCIE_CFGERRAERHEADERLOG11", - "PCIE_CFGERRAERHEADERLOG110", - "PCIE_CFGERRAERHEADERLOG111", - "PCIE_CFGERRAERHEADERLOG112", - "PCIE_CFGERRAERHEADERLOG113", - "PCIE_CFGERRAERHEADERLOG114", - "PCIE_CFGERRAERHEADERLOG115", - "PCIE_CFGERRAERHEADERLOG116", - "PCIE_CFGERRAERHEADERLOG117", - "PCIE_CFGERRAERHEADERLOG118", - "PCIE_CFGERRAERHEADERLOG119", - "PCIE_CFGERRAERHEADERLOG12", - "PCIE_CFGERRAERHEADERLOG120", - "PCIE_CFGERRAERHEADERLOG121", - "PCIE_CFGERRAERHEADERLOG122", - "PCIE_CFGERRAERHEADERLOG123", - "PCIE_CFGERRAERHEADERLOG124", - "PCIE_CFGERRAERHEADERLOG125", - "PCIE_CFGERRAERHEADERLOG126", - "PCIE_CFGERRAERHEADERLOG127", - "PCIE_CFGERRAERHEADERLOG13", - "PCIE_CFGERRAERHEADERLOG14", - "PCIE_CFGERRAERHEADERLOG15", - "PCIE_CFGERRAERHEADERLOG16", - "PCIE_CFGERRAERHEADERLOG17", - "PCIE_CFGERRAERHEADERLOG18", - "PCIE_CFGERRAERHEADERLOG19", - "PCIE_CFGERRAERHEADERLOG2", - "PCIE_CFGERRAERHEADERLOG20", - "PCIE_CFGERRAERHEADERLOG21", - "PCIE_CFGERRAERHEADERLOG22", - "PCIE_CFGERRAERHEADERLOG23", - "PCIE_CFGERRAERHEADERLOG24", - "PCIE_CFGERRAERHEADERLOG25", - "PCIE_CFGERRAERHEADERLOG26", - "PCIE_CFGERRAERHEADERLOG27", - "PCIE_CFGERRAERHEADERLOG28", - "PCIE_CFGERRAERHEADERLOG29", - "PCIE_CFGERRAERHEADERLOG3", - "PCIE_CFGERRAERHEADERLOG30", - "PCIE_CFGERRAERHEADERLOG31", - "PCIE_CFGERRAERHEADERLOG32", - "PCIE_CFGERRAERHEADERLOG33", - "PCIE_CFGERRAERHEADERLOG34", - "PCIE_CFGERRAERHEADERLOG35", - "PCIE_CFGERRAERHEADERLOG36", - "PCIE_CFGERRAERHEADERLOG37", - "PCIE_CFGERRAERHEADERLOG38", - "PCIE_CFGERRAERHEADERLOG39", - "PCIE_CFGERRAERHEADERLOG4", - "PCIE_CFGERRAERHEADERLOG40", - "PCIE_CFGERRAERHEADERLOG41", - "PCIE_CFGERRAERHEADERLOG42", - "PCIE_CFGERRAERHEADERLOG43", - "PCIE_CFGERRAERHEADERLOG44", - "PCIE_CFGERRAERHEADERLOG45", - "PCIE_CFGERRAERHEADERLOG46", - "PCIE_CFGERRAERHEADERLOG47", - "PCIE_CFGERRAERHEADERLOG48", - "PCIE_CFGERRAERHEADERLOG49", - "PCIE_CFGERRAERHEADERLOG5", - "PCIE_CFGERRAERHEADERLOG50", - "PCIE_CFGERRAERHEADERLOG51", - "PCIE_CFGERRAERHEADERLOG52", - "PCIE_CFGERRAERHEADERLOG53", - "PCIE_CFGERRAERHEADERLOG54", - "PCIE_CFGERRAERHEADERLOG55", - "PCIE_CFGERRAERHEADERLOG56", - "PCIE_CFGERRAERHEADERLOG57", - "PCIE_CFGERRAERHEADERLOG58", - "PCIE_CFGERRAERHEADERLOG59", - "PCIE_CFGERRAERHEADERLOG6", - "PCIE_CFGERRAERHEADERLOG60", - "PCIE_CFGERRAERHEADERLOG61", - "PCIE_CFGERRAERHEADERLOG62", - "PCIE_CFGERRAERHEADERLOG63", - "PCIE_CFGERRAERHEADERLOG64", - "PCIE_CFGERRAERHEADERLOG65", - "PCIE_CFGERRAERHEADERLOG66", - "PCIE_CFGERRAERHEADERLOG67", - "PCIE_CFGERRAERHEADERLOG68", - "PCIE_CFGERRAERHEADERLOG69", - "PCIE_CFGERRAERHEADERLOG7", - "PCIE_CFGERRAERHEADERLOG70", - "PCIE_CFGERRAERHEADERLOG71", - "PCIE_CFGERRAERHEADERLOG72", - "PCIE_CFGERRAERHEADERLOG73", - "PCIE_CFGERRAERHEADERLOG74", - "PCIE_CFGERRAERHEADERLOG75", - "PCIE_CFGERRAERHEADERLOG76", - "PCIE_CFGERRAERHEADERLOG77", - "PCIE_CFGERRAERHEADERLOG78", - "PCIE_CFGERRAERHEADERLOG79", - "PCIE_CFGERRAERHEADERLOG8", - "PCIE_CFGERRAERHEADERLOG80", - "PCIE_CFGERRAERHEADERLOG81", - "PCIE_CFGERRAERHEADERLOG82", - "PCIE_CFGERRAERHEADERLOG83", - "PCIE_CFGERRAERHEADERLOG84", - "PCIE_CFGERRAERHEADERLOG85", - "PCIE_CFGERRAERHEADERLOG86", - "PCIE_CFGERRAERHEADERLOG87", - "PCIE_CFGERRAERHEADERLOG88", - "PCIE_CFGERRAERHEADERLOG89", - "PCIE_CFGERRAERHEADERLOG9", - "PCIE_CFGERRAERHEADERLOG90", - "PCIE_CFGERRAERHEADERLOG91", - "PCIE_CFGERRAERHEADERLOG92", - "PCIE_CFGERRAERHEADERLOG93", - "PCIE_CFGERRAERHEADERLOG94", - "PCIE_CFGERRAERHEADERLOG95", - "PCIE_CFGERRAERHEADERLOG96", - "PCIE_CFGERRAERHEADERLOG97", - "PCIE_CFGERRAERHEADERLOG98", - "PCIE_CFGERRAERHEADERLOG99", - "PCIE_CFGERRAERHEADERLOGSETN", - "PCIE_CFGERRATOMICEGRESSBLOCKEDN", - "PCIE_CFGERRCORN", - "PCIE_CFGERRCPLABORTN", - "PCIE_CFGERRCPLRDYN", - "PCIE_CFGERRCPLTIMEOUTN", - "PCIE_CFGERRCPLUNEXPECTN", - "PCIE_CFGERRECRCN", - "PCIE_CFGERRINTERNALCORN", - "PCIE_CFGERRINTERNALUNCORN", - "PCIE_CFGERRLOCKEDN", - "PCIE_CFGERRMALFORMEDN", - "PCIE_CFGERRMCBLOCKEDN", - "PCIE_CFGERRNORECOVERYN", - "PCIE_CFGERRPOISONEDN", - "PCIE_CFGERRPOSTEDN", - "PCIE_CFGERRTLPCPLHEADER0", - "PCIE_CFGERRTLPCPLHEADER1", - "PCIE_CFGERRTLPCPLHEADER10", - "PCIE_CFGERRTLPCPLHEADER11", - "PCIE_CFGERRTLPCPLHEADER12", - "PCIE_CFGERRTLPCPLHEADER13", - "PCIE_CFGERRTLPCPLHEADER14", - "PCIE_CFGERRTLPCPLHEADER15", - "PCIE_CFGERRTLPCPLHEADER16", - "PCIE_CFGERRTLPCPLHEADER17", - "PCIE_CFGERRTLPCPLHEADER18", - "PCIE_CFGERRTLPCPLHEADER19", - "PCIE_CFGERRTLPCPLHEADER2", - "PCIE_CFGERRTLPCPLHEADER20", - "PCIE_CFGERRTLPCPLHEADER21", - "PCIE_CFGERRTLPCPLHEADER22", - "PCIE_CFGERRTLPCPLHEADER23", - "PCIE_CFGERRTLPCPLHEADER24", - "PCIE_CFGERRTLPCPLHEADER25", - "PCIE_CFGERRTLPCPLHEADER26", - "PCIE_CFGERRTLPCPLHEADER27", - "PCIE_CFGERRTLPCPLHEADER28", - "PCIE_CFGERRTLPCPLHEADER29", - "PCIE_CFGERRTLPCPLHEADER3", - "PCIE_CFGERRTLPCPLHEADER30", - "PCIE_CFGERRTLPCPLHEADER31", - "PCIE_CFGERRTLPCPLHEADER32", - "PCIE_CFGERRTLPCPLHEADER33", - "PCIE_CFGERRTLPCPLHEADER34", - "PCIE_CFGERRTLPCPLHEADER35", - "PCIE_CFGERRTLPCPLHEADER36", - "PCIE_CFGERRTLPCPLHEADER37", - "PCIE_CFGERRTLPCPLHEADER38", - "PCIE_CFGERRTLPCPLHEADER39", - "PCIE_CFGERRTLPCPLHEADER4", - "PCIE_CFGERRTLPCPLHEADER40", - "PCIE_CFGERRTLPCPLHEADER41", - "PCIE_CFGERRTLPCPLHEADER42", - "PCIE_CFGERRTLPCPLHEADER43", - "PCIE_CFGERRTLPCPLHEADER44", - "PCIE_CFGERRTLPCPLHEADER45", - "PCIE_CFGERRTLPCPLHEADER46", - "PCIE_CFGERRTLPCPLHEADER47", - "PCIE_CFGERRTLPCPLHEADER5", - "PCIE_CFGERRTLPCPLHEADER6", - "PCIE_CFGERRTLPCPLHEADER7", - "PCIE_CFGERRTLPCPLHEADER8", - "PCIE_CFGERRTLPCPLHEADER9", - "PCIE_CFGERRURN", - "PCIE_CFGFORCECOMMONCLOCKOFF", - "PCIE_CFGFORCEEXTENDEDSYNCON", - "PCIE_CFGFORCEMPS0", - "PCIE_CFGFORCEMPS1", - "PCIE_CFGFORCEMPS2", - "PCIE_CFGINTERRUPTASSERTN", - "PCIE_CFGINTERRUPTDI0", - "PCIE_CFGINTERRUPTDI1", - "PCIE_CFGINTERRUPTDI2", - "PCIE_CFGINTERRUPTDI3", - "PCIE_CFGINTERRUPTDI4", - "PCIE_CFGINTERRUPTDI5", - "PCIE_CFGINTERRUPTDI6", - "PCIE_CFGINTERRUPTDI7", - "PCIE_CFGINTERRUPTDO0", - "PCIE_CFGINTERRUPTDO1", - "PCIE_CFGINTERRUPTDO2", - "PCIE_CFGINTERRUPTDO3", - "PCIE_CFGINTERRUPTDO4", - "PCIE_CFGINTERRUPTDO5", - "PCIE_CFGINTERRUPTDO6", - "PCIE_CFGINTERRUPTDO7", - "PCIE_CFGINTERRUPTMMENABLE0", - "PCIE_CFGINTERRUPTMMENABLE1", - "PCIE_CFGINTERRUPTMMENABLE2", - "PCIE_CFGINTERRUPTMSIENABLE", - "PCIE_CFGINTERRUPTMSIXENABLE", - "PCIE_CFGINTERRUPTMSIXFM", - "PCIE_CFGINTERRUPTN", - "PCIE_CFGINTERRUPTRDYN", - "PCIE_CFGINTERRUPTSTATN", - "PCIE_CFGLINKCONTROLASPMCONTROL0", - "PCIE_CFGLINKCONTROLASPMCONTROL1", - "PCIE_CFGLINKCONTROLAUTOBANDWIDTHINTEN", - "PCIE_CFGLINKCONTROLBANDWIDTHINTEN", - "PCIE_CFGLINKCONTROLCLOCKPMEN", - "PCIE_CFGLINKCONTROLCOMMONCLOCK", - "PCIE_CFGLINKCONTROLEXTENDEDSYNC", - "PCIE_CFGLINKCONTROLHWAUTOWIDTHDIS", - "PCIE_CFGLINKCONTROLLINKDISABLE", - "PCIE_CFGLINKCONTROLRCB", - "PCIE_CFGLINKCONTROLRETRAINLINK", - "PCIE_CFGLINKSTATUSAUTOBANDWIDTHSTATUS", - "PCIE_CFGLINKSTATUSBANDWIDTHSTATUS", - "PCIE_CFGLINKSTATUSCURRENTSPEED0", - "PCIE_CFGLINKSTATUSCURRENTSPEED1", - "PCIE_CFGLINKSTATUSDLLACTIVE", - "PCIE_CFGLINKSTATUSLINKTRAINING", - "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH0", - "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH1", - "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH2", - "PCIE_CFGLINKSTATUSNEGOTIATEDWIDTH3", - "PCIE_CFGMGMTBYTEENN0", - "PCIE_CFGMGMTBYTEENN1", - "PCIE_CFGMGMTBYTEENN2", - "PCIE_CFGMGMTBYTEENN3", - "PCIE_CFGMGMTDI0", - "PCIE_CFGMGMTDI1", - "PCIE_CFGMGMTDI10", - "PCIE_CFGMGMTDI11", - "PCIE_CFGMGMTDI12", - "PCIE_CFGMGMTDI13", - "PCIE_CFGMGMTDI14", - "PCIE_CFGMGMTDI15", - "PCIE_CFGMGMTDI16", - "PCIE_CFGMGMTDI17", - "PCIE_CFGMGMTDI18", - "PCIE_CFGMGMTDI19", - "PCIE_CFGMGMTDI2", - "PCIE_CFGMGMTDI20", - "PCIE_CFGMGMTDI21", - "PCIE_CFGMGMTDI22", - "PCIE_CFGMGMTDI23", - "PCIE_CFGMGMTDI24", - "PCIE_CFGMGMTDI25", - "PCIE_CFGMGMTDI26", - "PCIE_CFGMGMTDI27", - "PCIE_CFGMGMTDI28", - "PCIE_CFGMGMTDI29", - "PCIE_CFGMGMTDI3", - "PCIE_CFGMGMTDI30", - "PCIE_CFGMGMTDI31", - "PCIE_CFGMGMTDI4", - "PCIE_CFGMGMTDI5", - "PCIE_CFGMGMTDI6", - "PCIE_CFGMGMTDI7", - "PCIE_CFGMGMTDI8", - "PCIE_CFGMGMTDI9", - "PCIE_CFGMGMTDO0", - "PCIE_CFGMGMTDO1", - "PCIE_CFGMGMTDO10", - "PCIE_CFGMGMTDO11", - "PCIE_CFGMGMTDO12", - "PCIE_CFGMGMTDO13", - "PCIE_CFGMGMTDO14", - "PCIE_CFGMGMTDO15", - "PCIE_CFGMGMTDO16", - "PCIE_CFGMGMTDO17", - "PCIE_CFGMGMTDO18", - "PCIE_CFGMGMTDO19", - "PCIE_CFGMGMTDO2", - "PCIE_CFGMGMTDO20", - "PCIE_CFGMGMTDO21", - "PCIE_CFGMGMTDO22", - "PCIE_CFGMGMTDO23", - "PCIE_CFGMGMTDO24", - "PCIE_CFGMGMTDO25", - "PCIE_CFGMGMTDO26", - "PCIE_CFGMGMTDO27", - "PCIE_CFGMGMTDO28", - "PCIE_CFGMGMTDO29", - "PCIE_CFGMGMTDO3", - "PCIE_CFGMGMTDO30", - "PCIE_CFGMGMTDO31", - "PCIE_CFGMGMTDO4", - "PCIE_CFGMGMTDO5", - "PCIE_CFGMGMTDO6", - "PCIE_CFGMGMTDO7", - "PCIE_CFGMGMTDO8", - "PCIE_CFGMGMTDO9", - "PCIE_CFGMGMTDWADDR0", - "PCIE_CFGMGMTDWADDR1", - "PCIE_CFGMGMTDWADDR2", - "PCIE_CFGMGMTDWADDR3", - "PCIE_CFGMGMTDWADDR4", - "PCIE_CFGMGMTDWADDR5", - "PCIE_CFGMGMTDWADDR6", - "PCIE_CFGMGMTDWADDR7", - "PCIE_CFGMGMTDWADDR8", - "PCIE_CFGMGMTDWADDR9", - "PCIE_CFGMGMTRDENN", - "PCIE_CFGMGMTRDWRDONEN", - "PCIE_CFGMGMTWRENN", - "PCIE_CFGMGMTWRREADONLYN", - "PCIE_CFGMGMTWRRW1CASRWN", - "PCIE_CFGMSGDATA0", - "PCIE_CFGMSGDATA1", - "PCIE_CFGMSGDATA10", - "PCIE_CFGMSGDATA11", - "PCIE_CFGMSGDATA12", - "PCIE_CFGMSGDATA13", - "PCIE_CFGMSGDATA14", - "PCIE_CFGMSGDATA15", - "PCIE_CFGMSGDATA2", - "PCIE_CFGMSGDATA3", - "PCIE_CFGMSGDATA4", - "PCIE_CFGMSGDATA5", - "PCIE_CFGMSGDATA6", - "PCIE_CFGMSGDATA7", - "PCIE_CFGMSGDATA8", - "PCIE_CFGMSGDATA9", - "PCIE_CFGMSGRECEIVED", - "PCIE_CFGMSGRECEIVEDASSERTINTA", - "PCIE_CFGMSGRECEIVEDASSERTINTB", - "PCIE_CFGMSGRECEIVEDASSERTINTC", - "PCIE_CFGMSGRECEIVEDASSERTINTD", - "PCIE_CFGMSGRECEIVEDDEASSERTINTA", - "PCIE_CFGMSGRECEIVEDDEASSERTINTB", - "PCIE_CFGMSGRECEIVEDDEASSERTINTC", - "PCIE_CFGMSGRECEIVEDDEASSERTINTD", - "PCIE_CFGMSGRECEIVEDERRCOR", - "PCIE_CFGMSGRECEIVEDERRFATAL", - "PCIE_CFGMSGRECEIVEDERRNONFATAL", - "PCIE_CFGMSGRECEIVEDPMASNAK", - "PCIE_CFGMSGRECEIVEDPMETO", - "PCIE_CFGMSGRECEIVEDPMETOACK", - "PCIE_CFGMSGRECEIVEDPMPME", - "PCIE_CFGMSGRECEIVEDSETSLOTPOWERLIMIT", - "PCIE_CFGMSGRECEIVEDUNLOCK", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM0", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM1", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM2", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM3", - "PCIE_CFGPCIECAPINTERRUPTMSGNUM4", - "PCIE_CFGPCIELINKSTATE0", - "PCIE_CFGPCIELINKSTATE1", - "PCIE_CFGPCIELINKSTATE2", - "PCIE_CFGPMCSRPMEEN", - "PCIE_CFGPMCSRPMESTATUS", - "PCIE_CFGPMCSRPOWERSTATE0", - "PCIE_CFGPMCSRPOWERSTATE1", - "PCIE_CFGPMFORCESTATE0", - "PCIE_CFGPMFORCESTATE1", - "PCIE_CFGPMFORCESTATEENN", - "PCIE_CFGPMHALTASPML0SN", - "PCIE_CFGPMHALTASPML1N", - "PCIE_CFGPMRCVASREQL1N", - "PCIE_CFGPMRCVENTERL1N", - "PCIE_CFGPMRCVENTERL23N", - "PCIE_CFGPMRCVREQACKN", - "PCIE_CFGPMSENDPMETON", - "PCIE_CFGPMTURNOFFOKN", - "PCIE_CFGPMWAKEN", - "PCIE_CFGPORTNUMBER0", - "PCIE_CFGPORTNUMBER1", - "PCIE_CFGPORTNUMBER2", - "PCIE_CFGPORTNUMBER3", - "PCIE_CFGPORTNUMBER4", - "PCIE_CFGPORTNUMBER5", - "PCIE_CFGPORTNUMBER6", - "PCIE_CFGPORTNUMBER7", - "PCIE_CFGREVID0", - "PCIE_CFGREVID1", - "PCIE_CFGREVID2", - "PCIE_CFGREVID3", - "PCIE_CFGREVID4", - "PCIE_CFGREVID5", - "PCIE_CFGREVID6", - "PCIE_CFGREVID7", - "PCIE_CFGROOTCONTROLPMEINTEN", - "PCIE_CFGROOTCONTROLSYSERRCORRERREN", - "PCIE_CFGROOTCONTROLSYSERRFATALERREN", - "PCIE_CFGROOTCONTROLSYSERRNONFATALERREN", - "PCIE_CFGSLOTCONTROLELECTROMECHILCTLPULSE", - "PCIE_CFGSUBSYSID0", - "PCIE_CFGSUBSYSID1", - "PCIE_CFGSUBSYSID10", - "PCIE_CFGSUBSYSID11", - "PCIE_CFGSUBSYSID12", - "PCIE_CFGSUBSYSID13", - "PCIE_CFGSUBSYSID14", - "PCIE_CFGSUBSYSID15", - "PCIE_CFGSUBSYSID2", - "PCIE_CFGSUBSYSID3", - "PCIE_CFGSUBSYSID4", - "PCIE_CFGSUBSYSID5", - "PCIE_CFGSUBSYSID6", - "PCIE_CFGSUBSYSID7", - "PCIE_CFGSUBSYSID8", - "PCIE_CFGSUBSYSID9", - "PCIE_CFGSUBSYSVENDID0", - "PCIE_CFGSUBSYSVENDID1", - "PCIE_CFGSUBSYSVENDID10", - "PCIE_CFGSUBSYSVENDID11", - "PCIE_CFGSUBSYSVENDID12", - "PCIE_CFGSUBSYSVENDID13", - "PCIE_CFGSUBSYSVENDID14", - "PCIE_CFGSUBSYSVENDID15", - "PCIE_CFGSUBSYSVENDID2", - "PCIE_CFGSUBSYSVENDID3", - "PCIE_CFGSUBSYSVENDID4", - "PCIE_CFGSUBSYSVENDID5", - "PCIE_CFGSUBSYSVENDID6", - "PCIE_CFGSUBSYSVENDID7", - "PCIE_CFGSUBSYSVENDID8", - "PCIE_CFGSUBSYSVENDID9", - "PCIE_CFGTRANSACTION", - "PCIE_CFGTRANSACTIONADDR0", - "PCIE_CFGTRANSACTIONADDR1", - "PCIE_CFGTRANSACTIONADDR2", - "PCIE_CFGTRANSACTIONADDR3", - "PCIE_CFGTRANSACTIONADDR4", - "PCIE_CFGTRANSACTIONADDR5", - "PCIE_CFGTRANSACTIONADDR6", - "PCIE_CFGTRANSACTIONTYPE", - "PCIE_CFGTRNPENDINGN", - "PCIE_CFGVCTCVCMAP0", - "PCIE_CFGVCTCVCMAP1", - "PCIE_CFGVCTCVCMAP2", - "PCIE_CFGVCTCVCMAP3", - "PCIE_CFGVCTCVCMAP4", - "PCIE_CFGVCTCVCMAP5", - "PCIE_CFGVCTCVCMAP6", - "PCIE_CFGVENDID0", - "PCIE_CFGVENDID1", - "PCIE_CFGVENDID10", - "PCIE_CFGVENDID11", - "PCIE_CFGVENDID12", - "PCIE_CFGVENDID13", - "PCIE_CFGVENDID14", - "PCIE_CFGVENDID15", - "PCIE_CFGVENDID2", - "PCIE_CFGVENDID3", - "PCIE_CFGVENDID4", - "PCIE_CFGVENDID5", - "PCIE_CFGVENDID6", - "PCIE_CFGVENDID7", - "PCIE_CFGVENDID8", - "PCIE_CFGVENDID9", - "PCIE_CLK0_L_0", - "PCIE_CLK0_L_1", - "PCIE_CLK0_L_10", - "PCIE_CLK0_L_11", - "PCIE_CLK0_L_12", - "PCIE_CLK0_L_13", - "PCIE_CLK0_L_14", - "PCIE_CLK0_L_15", - "PCIE_CLK0_L_16", - "PCIE_CLK0_L_17", - "PCIE_CLK0_L_18", - "PCIE_CLK0_L_19", - "PCIE_CLK0_L_2", - "PCIE_CLK0_L_3", - "PCIE_CLK0_L_4", - "PCIE_CLK0_L_5", - "PCIE_CLK0_L_6", - "PCIE_CLK0_L_7", - "PCIE_CLK0_L_8", - "PCIE_CLK0_L_9", - "PCIE_CLK0_R_0", - "PCIE_CLK0_R_1", - "PCIE_CLK0_R_10", - "PCIE_CLK0_R_11", - "PCIE_CLK0_R_12", - "PCIE_CLK0_R_13", - "PCIE_CLK0_R_14", - "PCIE_CLK0_R_15", - "PCIE_CLK0_R_16", - "PCIE_CLK0_R_17", - "PCIE_CLK0_R_18", - "PCIE_CLK0_R_19", - "PCIE_CLK0_R_2", - "PCIE_CLK0_R_3", - "PCIE_CLK0_R_4", - "PCIE_CLK0_R_5", - "PCIE_CLK0_R_6", - "PCIE_CLK0_R_7", - "PCIE_CLK0_R_8", - "PCIE_CLK0_R_9", - "PCIE_CLK1_L_0", - "PCIE_CLK1_L_1", - "PCIE_CLK1_L_10", - "PCIE_CLK1_L_11", - "PCIE_CLK1_L_12", - "PCIE_CLK1_L_13", - "PCIE_CLK1_L_14", - "PCIE_CLK1_L_15", - "PCIE_CLK1_L_16", - "PCIE_CLK1_L_17", - "PCIE_CLK1_L_18", - "PCIE_CLK1_L_19", - "PCIE_CLK1_L_2", - "PCIE_CLK1_L_3", - "PCIE_CLK1_L_4", - "PCIE_CLK1_L_5", - "PCIE_CLK1_L_6", - "PCIE_CLK1_L_7", - "PCIE_CLK1_L_8", - "PCIE_CLK1_L_9", - "PCIE_CLK1_R_0", - "PCIE_CLK1_R_1", - "PCIE_CLK1_R_10", - "PCIE_CLK1_R_11", - "PCIE_CLK1_R_12", - "PCIE_CLK1_R_13", - "PCIE_CLK1_R_14", - "PCIE_CLK1_R_15", - "PCIE_CLK1_R_16", - "PCIE_CLK1_R_17", - "PCIE_CLK1_R_18", - "PCIE_CLK1_R_19", - "PCIE_CLK1_R_2", - "PCIE_CLK1_R_3", - "PCIE_CLK1_R_4", - "PCIE_CLK1_R_5", - "PCIE_CLK1_R_6", - "PCIE_CLK1_R_7", - "PCIE_CLK1_R_8", - "PCIE_CLK1_R_9", - "PCIE_CMRSTN", - "PCIE_CMSTICKYRSTN", - "PCIE_CTRL0_L_0", - "PCIE_CTRL0_L_1", - "PCIE_CTRL0_L_10", - "PCIE_CTRL0_L_11", - "PCIE_CTRL0_L_12", - "PCIE_CTRL0_L_13", - "PCIE_CTRL0_L_14", - "PCIE_CTRL0_L_15", - "PCIE_CTRL0_L_16", - "PCIE_CTRL0_L_17", - "PCIE_CTRL0_L_18", - "PCIE_CTRL0_L_19", - "PCIE_CTRL0_L_2", - "PCIE_CTRL0_L_3", - "PCIE_CTRL0_L_4", - "PCIE_CTRL0_L_5", - "PCIE_CTRL0_L_6", - "PCIE_CTRL0_L_7", - "PCIE_CTRL0_L_8", - "PCIE_CTRL0_L_9", - "PCIE_CTRL0_R_0", - "PCIE_CTRL0_R_1", - "PCIE_CTRL0_R_10", - "PCIE_CTRL0_R_11", - "PCIE_CTRL0_R_12", - "PCIE_CTRL0_R_13", - "PCIE_CTRL0_R_14", - "PCIE_CTRL0_R_15", - "PCIE_CTRL0_R_16", - "PCIE_CTRL0_R_17", - "PCIE_CTRL0_R_18", - "PCIE_CTRL0_R_19", - "PCIE_CTRL0_R_2", - "PCIE_CTRL0_R_3", - "PCIE_CTRL0_R_4", - "PCIE_CTRL0_R_5", - "PCIE_CTRL0_R_6", - "PCIE_CTRL0_R_7", - "PCIE_CTRL0_R_8", - "PCIE_CTRL0_R_9", - "PCIE_CTRL1_L_0", - "PCIE_CTRL1_L_1", - "PCIE_CTRL1_L_10", - "PCIE_CTRL1_L_11", - "PCIE_CTRL1_L_12", - "PCIE_CTRL1_L_13", - "PCIE_CTRL1_L_14", - "PCIE_CTRL1_L_15", - "PCIE_CTRL1_L_16", - "PCIE_CTRL1_L_17", - "PCIE_CTRL1_L_18", - "PCIE_CTRL1_L_19", - "PCIE_CTRL1_L_2", - "PCIE_CTRL1_L_3", - "PCIE_CTRL1_L_4", - "PCIE_CTRL1_L_5", - "PCIE_CTRL1_L_6", - "PCIE_CTRL1_L_7", - "PCIE_CTRL1_L_8", - "PCIE_CTRL1_L_9", - "PCIE_CTRL1_R_0", - "PCIE_CTRL1_R_1", - "PCIE_CTRL1_R_10", - "PCIE_CTRL1_R_11", - "PCIE_CTRL1_R_12", - "PCIE_CTRL1_R_13", - "PCIE_CTRL1_R_14", - "PCIE_CTRL1_R_15", - "PCIE_CTRL1_R_16", - "PCIE_CTRL1_R_17", - "PCIE_CTRL1_R_18", - "PCIE_CTRL1_R_19", - "PCIE_CTRL1_R_2", - "PCIE_CTRL1_R_3", - "PCIE_CTRL1_R_4", - "PCIE_CTRL1_R_5", - "PCIE_CTRL1_R_6", - "PCIE_CTRL1_R_7", - "PCIE_CTRL1_R_8", - "PCIE_CTRL1_R_9", - "PCIE_DBGMODE0", - "PCIE_DBGMODE1", - "PCIE_DBGSCLRA", - "PCIE_DBGSCLRB", - "PCIE_DBGSCLRC", - "PCIE_DBGSCLRD", - "PCIE_DBGSCLRE", - "PCIE_DBGSCLRF", - "PCIE_DBGSCLRG", - "PCIE_DBGSCLRH", - "PCIE_DBGSCLRI", - "PCIE_DBGSCLRJ", - "PCIE_DBGSCLRK", - "PCIE_DBGSUBMODE", - "PCIE_DBGVECA0", - "PCIE_DBGVECA1", - "PCIE_DBGVECA10", - "PCIE_DBGVECA11", - "PCIE_DBGVECA12", - "PCIE_DBGVECA13", - "PCIE_DBGVECA14", - "PCIE_DBGVECA15", - "PCIE_DBGVECA16", - "PCIE_DBGVECA17", - "PCIE_DBGVECA18", - "PCIE_DBGVECA19", - "PCIE_DBGVECA2", - "PCIE_DBGVECA20", - "PCIE_DBGVECA21", - "PCIE_DBGVECA22", - "PCIE_DBGVECA23", - "PCIE_DBGVECA24", - "PCIE_DBGVECA25", - "PCIE_DBGVECA26", - "PCIE_DBGVECA27", - "PCIE_DBGVECA28", - "PCIE_DBGVECA29", - "PCIE_DBGVECA3", - "PCIE_DBGVECA30", - "PCIE_DBGVECA31", - "PCIE_DBGVECA32", - "PCIE_DBGVECA33", - "PCIE_DBGVECA34", - "PCIE_DBGVECA35", - "PCIE_DBGVECA36", - "PCIE_DBGVECA37", - "PCIE_DBGVECA38", - "PCIE_DBGVECA39", - "PCIE_DBGVECA4", - "PCIE_DBGVECA40", - "PCIE_DBGVECA41", - "PCIE_DBGVECA42", - "PCIE_DBGVECA43", - "PCIE_DBGVECA44", - "PCIE_DBGVECA45", - "PCIE_DBGVECA46", - "PCIE_DBGVECA47", - "PCIE_DBGVECA48", - "PCIE_DBGVECA49", - "PCIE_DBGVECA5", - "PCIE_DBGVECA50", - "PCIE_DBGVECA51", - "PCIE_DBGVECA52", - "PCIE_DBGVECA53", - "PCIE_DBGVECA54", - "PCIE_DBGVECA55", - "PCIE_DBGVECA56", - "PCIE_DBGVECA57", - "PCIE_DBGVECA58", - "PCIE_DBGVECA59", - "PCIE_DBGVECA6", - "PCIE_DBGVECA60", - "PCIE_DBGVECA61", - "PCIE_DBGVECA62", - "PCIE_DBGVECA63", - "PCIE_DBGVECA7", - "PCIE_DBGVECA8", - "PCIE_DBGVECA9", - "PCIE_DBGVECB0", - "PCIE_DBGVECB1", - "PCIE_DBGVECB10", - "PCIE_DBGVECB11", - "PCIE_DBGVECB12", - "PCIE_DBGVECB13", - "PCIE_DBGVECB14", - "PCIE_DBGVECB15", - "PCIE_DBGVECB16", - "PCIE_DBGVECB17", - "PCIE_DBGVECB18", - "PCIE_DBGVECB19", - "PCIE_DBGVECB2", - "PCIE_DBGVECB20", - "PCIE_DBGVECB21", - "PCIE_DBGVECB22", - "PCIE_DBGVECB23", - "PCIE_DBGVECB24", - "PCIE_DBGVECB25", - "PCIE_DBGVECB26", - "PCIE_DBGVECB27", - "PCIE_DBGVECB28", - "PCIE_DBGVECB29", - "PCIE_DBGVECB3", - "PCIE_DBGVECB30", - "PCIE_DBGVECB31", - "PCIE_DBGVECB32", - "PCIE_DBGVECB33", - "PCIE_DBGVECB34", - "PCIE_DBGVECB35", - "PCIE_DBGVECB36", - "PCIE_DBGVECB37", - "PCIE_DBGVECB38", - "PCIE_DBGVECB39", - "PCIE_DBGVECB4", - "PCIE_DBGVECB40", - "PCIE_DBGVECB41", - "PCIE_DBGVECB42", - "PCIE_DBGVECB43", - "PCIE_DBGVECB44", - "PCIE_DBGVECB45", - "PCIE_DBGVECB46", - "PCIE_DBGVECB47", - "PCIE_DBGVECB48", - "PCIE_DBGVECB49", - "PCIE_DBGVECB5", - "PCIE_DBGVECB50", - "PCIE_DBGVECB51", - "PCIE_DBGVECB52", - "PCIE_DBGVECB53", - "PCIE_DBGVECB54", - "PCIE_DBGVECB55", - "PCIE_DBGVECB56", - "PCIE_DBGVECB57", - "PCIE_DBGVECB58", - "PCIE_DBGVECB59", - "PCIE_DBGVECB6", - "PCIE_DBGVECB60", - "PCIE_DBGVECB61", - "PCIE_DBGVECB62", - "PCIE_DBGVECB63", - "PCIE_DBGVECB7", - "PCIE_DBGVECB8", - "PCIE_DBGVECB9", - "PCIE_DBGVECC0", - "PCIE_DBGVECC1", - "PCIE_DBGVECC10", - "PCIE_DBGVECC11", - "PCIE_DBGVECC2", - "PCIE_DBGVECC3", - "PCIE_DBGVECC4", - "PCIE_DBGVECC5", - "PCIE_DBGVECC6", - "PCIE_DBGVECC7", - "PCIE_DBGVECC8", - "PCIE_DBGVECC9", - "PCIE_DLRSTN", - "PCIE_DRPADDR0", - "PCIE_DRPADDR1", - "PCIE_DRPADDR2", - "PCIE_DRPADDR3", - "PCIE_DRPADDR4", - "PCIE_DRPADDR5", - "PCIE_DRPADDR6", - "PCIE_DRPADDR7", - "PCIE_DRPADDR8", - "PCIE_DRPCLK", - "PCIE_DRPDI0", - "PCIE_DRPDI1", - "PCIE_DRPDI10", - "PCIE_DRPDI11", - "PCIE_DRPDI12", - "PCIE_DRPDI13", - "PCIE_DRPDI14", - "PCIE_DRPDI15", - "PCIE_DRPDI2", - "PCIE_DRPDI3", - "PCIE_DRPDI4", - "PCIE_DRPDI5", - "PCIE_DRPDI6", - "PCIE_DRPDI7", - "PCIE_DRPDI8", - "PCIE_DRPDI9", - "PCIE_DRPDO0", - "PCIE_DRPDO1", - "PCIE_DRPDO10", - "PCIE_DRPDO11", - "PCIE_DRPDO12", - "PCIE_DRPDO13", - "PCIE_DRPDO14", - "PCIE_DRPDO15", - "PCIE_DRPDO2", - "PCIE_DRPDO3", - "PCIE_DRPDO4", - "PCIE_DRPDO5", - "PCIE_DRPDO6", - "PCIE_DRPDO7", - "PCIE_DRPDO8", - "PCIE_DRPDO9", - "PCIE_DRPEN", - "PCIE_DRPRDY", - "PCIE_DRPWE", - "PCIE_EDTBYPASS", - "PCIE_EDTCHANNELSIN1", - "PCIE_EDTCHANNELSIN2", - "PCIE_EDTCHANNELSIN3", - "PCIE_EDTCHANNELSIN4", - "PCIE_EDTCHANNELSIN5", - "PCIE_EDTCHANNELSIN6", - "PCIE_EDTCHANNELSIN7", - "PCIE_EDTCHANNELSIN8", - "PCIE_EDTCHANNELSOUT1", - "PCIE_EDTCHANNELSOUT2", - "PCIE_EDTCHANNELSOUT3", - "PCIE_EDTCHANNELSOUT4", - "PCIE_EDTCHANNELSOUT5", - "PCIE_EDTCHANNELSOUT6", - "PCIE_EDTCHANNELSOUT7", - "PCIE_EDTCHANNELSOUT8", - "PCIE_EDTCLK", - "PCIE_EDTCONFIGURATION", - "PCIE_EDTSINGLEBYPASSCHAIN", - "PCIE_EDTUPDATE", - "PCIE_EE2A0_0", - "PCIE_EE2A0_1", - "PCIE_EE2A0_10", - "PCIE_EE2A0_11", - "PCIE_EE2A0_12", - "PCIE_EE2A0_13", - "PCIE_EE2A0_14", - "PCIE_EE2A0_15", - "PCIE_EE2A0_16", - "PCIE_EE2A0_17", - "PCIE_EE2A0_18", - "PCIE_EE2A0_19", - "PCIE_EE2A0_2", - "PCIE_EE2A0_3", - "PCIE_EE2A0_4", - "PCIE_EE2A0_5", - "PCIE_EE2A0_6", - "PCIE_EE2A0_7", - "PCIE_EE2A0_8", - "PCIE_EE2A0_9", - "PCIE_EE2A1_0", - "PCIE_EE2A1_1", - "PCIE_EE2A1_10", - "PCIE_EE2A1_11", - "PCIE_EE2A1_12", - "PCIE_EE2A1_13", - "PCIE_EE2A1_14", - "PCIE_EE2A1_15", - "PCIE_EE2A1_16", - "PCIE_EE2A1_17", - "PCIE_EE2A1_18", - "PCIE_EE2A1_19", - "PCIE_EE2A1_2", - "PCIE_EE2A1_3", - "PCIE_EE2A1_4", - "PCIE_EE2A1_5", - "PCIE_EE2A1_6", - "PCIE_EE2A1_7", - "PCIE_EE2A1_8", - "PCIE_EE2A1_9", - "PCIE_EE2A2_0", - "PCIE_EE2A2_1", - "PCIE_EE2A2_10", - "PCIE_EE2A2_11", - "PCIE_EE2A2_12", - "PCIE_EE2A2_13", - "PCIE_EE2A2_14", - "PCIE_EE2A2_15", - "PCIE_EE2A2_16", - "PCIE_EE2A2_17", - "PCIE_EE2A2_18", - "PCIE_EE2A2_19", - "PCIE_EE2A2_2", - "PCIE_EE2A2_3", - "PCIE_EE2A2_4", - "PCIE_EE2A2_5", - "PCIE_EE2A2_6", - "PCIE_EE2A2_7", - "PCIE_EE2A2_8", - "PCIE_EE2A2_9", - "PCIE_EE2A3_0", - "PCIE_EE2A3_1", - "PCIE_EE2A3_10", - "PCIE_EE2A3_11", - "PCIE_EE2A3_12", - "PCIE_EE2A3_13", - "PCIE_EE2A3_14", - "PCIE_EE2A3_15", - "PCIE_EE2A3_16", - "PCIE_EE2A3_17", - "PCIE_EE2A3_18", - "PCIE_EE2A3_19", - "PCIE_EE2A3_2", - "PCIE_EE2A3_3", - "PCIE_EE2A3_4", - "PCIE_EE2A3_5", - "PCIE_EE2A3_6", - "PCIE_EE2A3_7", - "PCIE_EE2A3_8", - "PCIE_EE2A3_9", - "PCIE_EE2BEG0_0", - "PCIE_EE2BEG0_1", - "PCIE_EE2BEG0_10", - "PCIE_EE2BEG0_11", - "PCIE_EE2BEG0_12", - "PCIE_EE2BEG0_13", - "PCIE_EE2BEG0_14", - "PCIE_EE2BEG0_15", - "PCIE_EE2BEG0_16", - "PCIE_EE2BEG0_17", - "PCIE_EE2BEG0_18", - "PCIE_EE2BEG0_19", - "PCIE_EE2BEG0_2", - "PCIE_EE2BEG0_3", - "PCIE_EE2BEG0_4", - "PCIE_EE2BEG0_5", - "PCIE_EE2BEG0_6", - "PCIE_EE2BEG0_7", - "PCIE_EE2BEG0_8", - "PCIE_EE2BEG0_9", - "PCIE_EE2BEG1_0", - "PCIE_EE2BEG1_1", - "PCIE_EE2BEG1_10", - "PCIE_EE2BEG1_11", - "PCIE_EE2BEG1_12", - "PCIE_EE2BEG1_13", - "PCIE_EE2BEG1_14", - "PCIE_EE2BEG1_15", - "PCIE_EE2BEG1_16", - "PCIE_EE2BEG1_17", - "PCIE_EE2BEG1_18", - "PCIE_EE2BEG1_19", - "PCIE_EE2BEG1_2", - "PCIE_EE2BEG1_3", - "PCIE_EE2BEG1_4", - "PCIE_EE2BEG1_5", - "PCIE_EE2BEG1_6", - "PCIE_EE2BEG1_7", - "PCIE_EE2BEG1_8", - "PCIE_EE2BEG1_9", - "PCIE_EE2BEG2_0", - "PCIE_EE2BEG2_1", - "PCIE_EE2BEG2_10", - "PCIE_EE2BEG2_11", - "PCIE_EE2BEG2_12", - "PCIE_EE2BEG2_13", - "PCIE_EE2BEG2_14", - "PCIE_EE2BEG2_15", - "PCIE_EE2BEG2_16", - "PCIE_EE2BEG2_17", - "PCIE_EE2BEG2_18", - "PCIE_EE2BEG2_19", - "PCIE_EE2BEG2_2", - "PCIE_EE2BEG2_3", - "PCIE_EE2BEG2_4", - "PCIE_EE2BEG2_5", - "PCIE_EE2BEG2_6", - "PCIE_EE2BEG2_7", - "PCIE_EE2BEG2_8", - "PCIE_EE2BEG2_9", - "PCIE_EE2BEG3_0", - "PCIE_EE2BEG3_1", - "PCIE_EE2BEG3_10", - "PCIE_EE2BEG3_11", - "PCIE_EE2BEG3_12", - "PCIE_EE2BEG3_13", - "PCIE_EE2BEG3_14", - "PCIE_EE2BEG3_15", - "PCIE_EE2BEG3_16", - "PCIE_EE2BEG3_17", - "PCIE_EE2BEG3_18", - "PCIE_EE2BEG3_19", - "PCIE_EE2BEG3_2", - "PCIE_EE2BEG3_3", - "PCIE_EE2BEG3_4", - "PCIE_EE2BEG3_5", - "PCIE_EE2BEG3_6", - "PCIE_EE2BEG3_7", - "PCIE_EE2BEG3_8", - "PCIE_EE2BEG3_9", - "PCIE_EE4A0_0", - "PCIE_EE4A0_1", - "PCIE_EE4A0_10", - "PCIE_EE4A0_11", - "PCIE_EE4A0_12", - "PCIE_EE4A0_13", - "PCIE_EE4A0_14", - "PCIE_EE4A0_15", - "PCIE_EE4A0_16", - "PCIE_EE4A0_17", - "PCIE_EE4A0_18", - "PCIE_EE4A0_19", - "PCIE_EE4A0_2", - "PCIE_EE4A0_3", - "PCIE_EE4A0_4", - "PCIE_EE4A0_5", - "PCIE_EE4A0_6", - "PCIE_EE4A0_7", - "PCIE_EE4A0_8", - "PCIE_EE4A0_9", - "PCIE_EE4A1_0", - "PCIE_EE4A1_1", - "PCIE_EE4A1_10", - "PCIE_EE4A1_11", - "PCIE_EE4A1_12", - "PCIE_EE4A1_13", - "PCIE_EE4A1_14", - "PCIE_EE4A1_15", - "PCIE_EE4A1_16", - "PCIE_EE4A1_17", - "PCIE_EE4A1_18", - "PCIE_EE4A1_19", - "PCIE_EE4A1_2", - "PCIE_EE4A1_3", - "PCIE_EE4A1_4", - "PCIE_EE4A1_5", - "PCIE_EE4A1_6", - "PCIE_EE4A1_7", - "PCIE_EE4A1_8", - "PCIE_EE4A1_9", - "PCIE_EE4A2_0", - "PCIE_EE4A2_1", - "PCIE_EE4A2_10", - "PCIE_EE4A2_11", - "PCIE_EE4A2_12", - "PCIE_EE4A2_13", - "PCIE_EE4A2_14", - "PCIE_EE4A2_15", - "PCIE_EE4A2_16", - "PCIE_EE4A2_17", - "PCIE_EE4A2_18", - "PCIE_EE4A2_19", - "PCIE_EE4A2_2", - "PCIE_EE4A2_3", - "PCIE_EE4A2_4", - "PCIE_EE4A2_5", - "PCIE_EE4A2_6", - "PCIE_EE4A2_7", - "PCIE_EE4A2_8", - "PCIE_EE4A2_9", - "PCIE_EE4A3_0", - "PCIE_EE4A3_1", - "PCIE_EE4A3_10", - "PCIE_EE4A3_11", - "PCIE_EE4A3_12", - "PCIE_EE4A3_13", - "PCIE_EE4A3_14", - "PCIE_EE4A3_15", - "PCIE_EE4A3_16", - "PCIE_EE4A3_17", - "PCIE_EE4A3_18", - "PCIE_EE4A3_19", - "PCIE_EE4A3_2", - "PCIE_EE4A3_3", - "PCIE_EE4A3_4", - "PCIE_EE4A3_5", - "PCIE_EE4A3_6", - "PCIE_EE4A3_7", - "PCIE_EE4A3_8", - "PCIE_EE4A3_9", - "PCIE_EE4B0_0", - "PCIE_EE4B0_1", - "PCIE_EE4B0_10", - "PCIE_EE4B0_11", - "PCIE_EE4B0_12", - "PCIE_EE4B0_13", - "PCIE_EE4B0_14", - "PCIE_EE4B0_15", - "PCIE_EE4B0_16", - "PCIE_EE4B0_17", - "PCIE_EE4B0_18", - "PCIE_EE4B0_19", - "PCIE_EE4B0_2", - "PCIE_EE4B0_3", - "PCIE_EE4B0_4", - "PCIE_EE4B0_5", - "PCIE_EE4B0_6", - "PCIE_EE4B0_7", - "PCIE_EE4B0_8", - "PCIE_EE4B0_9", - "PCIE_EE4B1_0", - "PCIE_EE4B1_1", - "PCIE_EE4B1_10", - "PCIE_EE4B1_11", - "PCIE_EE4B1_12", - "PCIE_EE4B1_13", - "PCIE_EE4B1_14", - "PCIE_EE4B1_15", - "PCIE_EE4B1_16", - "PCIE_EE4B1_17", - "PCIE_EE4B1_18", - "PCIE_EE4B1_19", - "PCIE_EE4B1_2", - "PCIE_EE4B1_3", - "PCIE_EE4B1_4", - "PCIE_EE4B1_5", - "PCIE_EE4B1_6", - "PCIE_EE4B1_7", - "PCIE_EE4B1_8", - "PCIE_EE4B1_9", - "PCIE_EE4B2_0", - "PCIE_EE4B2_1", - "PCIE_EE4B2_10", - "PCIE_EE4B2_11", - "PCIE_EE4B2_12", - "PCIE_EE4B2_13", - "PCIE_EE4B2_14", - "PCIE_EE4B2_15", - "PCIE_EE4B2_16", - "PCIE_EE4B2_17", - "PCIE_EE4B2_18", - "PCIE_EE4B2_19", - "PCIE_EE4B2_2", - "PCIE_EE4B2_3", - "PCIE_EE4B2_4", - "PCIE_EE4B2_5", - "PCIE_EE4B2_6", - "PCIE_EE4B2_7", - "PCIE_EE4B2_8", - "PCIE_EE4B2_9", - "PCIE_EE4B3_0", - "PCIE_EE4B3_1", - "PCIE_EE4B3_10", - "PCIE_EE4B3_11", - "PCIE_EE4B3_12", - "PCIE_EE4B3_13", - "PCIE_EE4B3_14", - "PCIE_EE4B3_15", - "PCIE_EE4B3_16", - "PCIE_EE4B3_17", - "PCIE_EE4B3_18", - "PCIE_EE4B3_19", - "PCIE_EE4B3_2", - "PCIE_EE4B3_3", - "PCIE_EE4B3_4", - "PCIE_EE4B3_5", - "PCIE_EE4B3_6", - "PCIE_EE4B3_7", - "PCIE_EE4B3_8", - "PCIE_EE4B3_9", - "PCIE_EE4BEG0_0", - "PCIE_EE4BEG0_1", - "PCIE_EE4BEG0_10", - "PCIE_EE4BEG0_11", - "PCIE_EE4BEG0_12", - "PCIE_EE4BEG0_13", - "PCIE_EE4BEG0_14", - "PCIE_EE4BEG0_15", - "PCIE_EE4BEG0_16", - "PCIE_EE4BEG0_17", - "PCIE_EE4BEG0_18", - "PCIE_EE4BEG0_19", - "PCIE_EE4BEG0_2", - "PCIE_EE4BEG0_3", - "PCIE_EE4BEG0_4", - "PCIE_EE4BEG0_5", - "PCIE_EE4BEG0_6", - "PCIE_EE4BEG0_7", - "PCIE_EE4BEG0_8", - "PCIE_EE4BEG0_9", - "PCIE_EE4BEG1_0", - "PCIE_EE4BEG1_1", - "PCIE_EE4BEG1_10", - "PCIE_EE4BEG1_11", - "PCIE_EE4BEG1_12", - "PCIE_EE4BEG1_13", - "PCIE_EE4BEG1_14", - "PCIE_EE4BEG1_15", - "PCIE_EE4BEG1_16", - "PCIE_EE4BEG1_17", - "PCIE_EE4BEG1_18", - "PCIE_EE4BEG1_19", - "PCIE_EE4BEG1_2", - "PCIE_EE4BEG1_3", - "PCIE_EE4BEG1_4", - "PCIE_EE4BEG1_5", - "PCIE_EE4BEG1_6", - "PCIE_EE4BEG1_7", - "PCIE_EE4BEG1_8", - "PCIE_EE4BEG1_9", - "PCIE_EE4BEG2_0", - "PCIE_EE4BEG2_1", - "PCIE_EE4BEG2_10", - "PCIE_EE4BEG2_11", - "PCIE_EE4BEG2_12", - "PCIE_EE4BEG2_13", - "PCIE_EE4BEG2_14", - "PCIE_EE4BEG2_15", - "PCIE_EE4BEG2_16", - "PCIE_EE4BEG2_17", - "PCIE_EE4BEG2_18", - "PCIE_EE4BEG2_19", - "PCIE_EE4BEG2_2", - "PCIE_EE4BEG2_3", - "PCIE_EE4BEG2_4", - "PCIE_EE4BEG2_5", - "PCIE_EE4BEG2_6", - "PCIE_EE4BEG2_7", - "PCIE_EE4BEG2_8", - "PCIE_EE4BEG2_9", - "PCIE_EE4BEG3_0", - "PCIE_EE4BEG3_1", - "PCIE_EE4BEG3_10", - "PCIE_EE4BEG3_11", - "PCIE_EE4BEG3_12", - "PCIE_EE4BEG3_13", - "PCIE_EE4BEG3_14", - "PCIE_EE4BEG3_15", - "PCIE_EE4BEG3_16", - "PCIE_EE4BEG3_17", - "PCIE_EE4BEG3_18", - "PCIE_EE4BEG3_19", - "PCIE_EE4BEG3_2", - "PCIE_EE4BEG3_3", - "PCIE_EE4BEG3_4", - "PCIE_EE4BEG3_5", - "PCIE_EE4BEG3_6", - "PCIE_EE4BEG3_7", - "PCIE_EE4BEG3_8", - "PCIE_EE4BEG3_9", - "PCIE_EE4C0_0", - "PCIE_EE4C0_1", - "PCIE_EE4C0_10", - "PCIE_EE4C0_11", - "PCIE_EE4C0_12", - "PCIE_EE4C0_13", - "PCIE_EE4C0_14", - "PCIE_EE4C0_15", - "PCIE_EE4C0_16", - "PCIE_EE4C0_17", - "PCIE_EE4C0_18", - "PCIE_EE4C0_19", - "PCIE_EE4C0_2", - "PCIE_EE4C0_3", - "PCIE_EE4C0_4", - "PCIE_EE4C0_5", - "PCIE_EE4C0_6", - "PCIE_EE4C0_7", - "PCIE_EE4C0_8", - "PCIE_EE4C0_9", - "PCIE_EE4C1_0", - "PCIE_EE4C1_1", - "PCIE_EE4C1_10", - "PCIE_EE4C1_11", - "PCIE_EE4C1_12", - "PCIE_EE4C1_13", - "PCIE_EE4C1_14", - "PCIE_EE4C1_15", - "PCIE_EE4C1_16", - "PCIE_EE4C1_17", - "PCIE_EE4C1_18", - "PCIE_EE4C1_19", - "PCIE_EE4C1_2", - "PCIE_EE4C1_3", - "PCIE_EE4C1_4", - "PCIE_EE4C1_5", - "PCIE_EE4C1_6", - "PCIE_EE4C1_7", - "PCIE_EE4C1_8", - "PCIE_EE4C1_9", - "PCIE_EE4C2_0", - "PCIE_EE4C2_1", - "PCIE_EE4C2_10", - "PCIE_EE4C2_11", - "PCIE_EE4C2_12", - "PCIE_EE4C2_13", - "PCIE_EE4C2_14", - "PCIE_EE4C2_15", - "PCIE_EE4C2_16", - "PCIE_EE4C2_17", - "PCIE_EE4C2_18", - "PCIE_EE4C2_19", - "PCIE_EE4C2_2", - "PCIE_EE4C2_3", - "PCIE_EE4C2_4", - "PCIE_EE4C2_5", - "PCIE_EE4C2_6", - "PCIE_EE4C2_7", - "PCIE_EE4C2_8", - "PCIE_EE4C2_9", - "PCIE_EE4C3_0", - "PCIE_EE4C3_1", - "PCIE_EE4C3_10", - "PCIE_EE4C3_11", - "PCIE_EE4C3_12", - "PCIE_EE4C3_13", - "PCIE_EE4C3_14", - "PCIE_EE4C3_15", - "PCIE_EE4C3_16", - "PCIE_EE4C3_17", - "PCIE_EE4C3_18", - "PCIE_EE4C3_19", - "PCIE_EE4C3_2", - "PCIE_EE4C3_3", - "PCIE_EE4C3_4", - "PCIE_EE4C3_5", - "PCIE_EE4C3_6", - "PCIE_EE4C3_7", - "PCIE_EE4C3_8", - "PCIE_EE4C3_9", - "PCIE_EL1BEG0_0", - "PCIE_EL1BEG0_1", - "PCIE_EL1BEG0_10", - "PCIE_EL1BEG0_11", - "PCIE_EL1BEG0_12", - "PCIE_EL1BEG0_13", - "PCIE_EL1BEG0_14", - "PCIE_EL1BEG0_15", - "PCIE_EL1BEG0_16", - "PCIE_EL1BEG0_17", - "PCIE_EL1BEG0_18", - "PCIE_EL1BEG0_19", - "PCIE_EL1BEG0_2", - "PCIE_EL1BEG0_3", - "PCIE_EL1BEG0_4", - "PCIE_EL1BEG0_5", - "PCIE_EL1BEG0_6", - "PCIE_EL1BEG0_7", - "PCIE_EL1BEG0_8", - "PCIE_EL1BEG0_9", - "PCIE_EL1BEG1_0", - "PCIE_EL1BEG1_1", - "PCIE_EL1BEG1_10", - "PCIE_EL1BEG1_11", - "PCIE_EL1BEG1_12", - "PCIE_EL1BEG1_13", - "PCIE_EL1BEG1_14", - "PCIE_EL1BEG1_15", - "PCIE_EL1BEG1_16", - "PCIE_EL1BEG1_17", - "PCIE_EL1BEG1_18", - "PCIE_EL1BEG1_19", - "PCIE_EL1BEG1_2", - "PCIE_EL1BEG1_3", - "PCIE_EL1BEG1_4", - "PCIE_EL1BEG1_5", - "PCIE_EL1BEG1_6", - "PCIE_EL1BEG1_7", - "PCIE_EL1BEG1_8", - "PCIE_EL1BEG1_9", - "PCIE_EL1BEG2_0", - "PCIE_EL1BEG2_1", - "PCIE_EL1BEG2_10", - "PCIE_EL1BEG2_11", - "PCIE_EL1BEG2_12", - "PCIE_EL1BEG2_13", - "PCIE_EL1BEG2_14", - "PCIE_EL1BEG2_15", - "PCIE_EL1BEG2_16", - "PCIE_EL1BEG2_17", - "PCIE_EL1BEG2_18", - "PCIE_EL1BEG2_19", - "PCIE_EL1BEG2_2", - "PCIE_EL1BEG2_3", - "PCIE_EL1BEG2_4", - "PCIE_EL1BEG2_5", - "PCIE_EL1BEG2_6", - "PCIE_EL1BEG2_7", - "PCIE_EL1BEG2_8", - "PCIE_EL1BEG2_9", - "PCIE_EL1BEG3_0", - "PCIE_EL1BEG3_1", - "PCIE_EL1BEG3_10", - "PCIE_EL1BEG3_11", - "PCIE_EL1BEG3_12", - "PCIE_EL1BEG3_13", - "PCIE_EL1BEG3_14", - "PCIE_EL1BEG3_15", - "PCIE_EL1BEG3_16", - "PCIE_EL1BEG3_17", - "PCIE_EL1BEG3_18", - "PCIE_EL1BEG3_19", - "PCIE_EL1BEG3_2", - "PCIE_EL1BEG3_3", - "PCIE_EL1BEG3_4", - "PCIE_EL1BEG3_5", - "PCIE_EL1BEG3_6", - "PCIE_EL1BEG3_7", - "PCIE_EL1BEG3_8", - "PCIE_EL1BEG3_9", - "PCIE_ER1BEG0_0", - "PCIE_ER1BEG0_1", - "PCIE_ER1BEG0_10", - "PCIE_ER1BEG0_11", - "PCIE_ER1BEG0_12", - "PCIE_ER1BEG0_13", - "PCIE_ER1BEG0_14", - "PCIE_ER1BEG0_15", - "PCIE_ER1BEG0_16", - "PCIE_ER1BEG0_17", - "PCIE_ER1BEG0_18", - "PCIE_ER1BEG0_19", - "PCIE_ER1BEG0_2", - "PCIE_ER1BEG0_3", - "PCIE_ER1BEG0_4", - "PCIE_ER1BEG0_5", - "PCIE_ER1BEG0_6", - "PCIE_ER1BEG0_7", - "PCIE_ER1BEG0_8", - "PCIE_ER1BEG0_9", - "PCIE_ER1BEG1_0", - "PCIE_ER1BEG1_1", - "PCIE_ER1BEG1_10", - "PCIE_ER1BEG1_11", - "PCIE_ER1BEG1_12", - "PCIE_ER1BEG1_13", - "PCIE_ER1BEG1_14", - "PCIE_ER1BEG1_15", - "PCIE_ER1BEG1_16", - "PCIE_ER1BEG1_17", - "PCIE_ER1BEG1_18", - "PCIE_ER1BEG1_19", - "PCIE_ER1BEG1_2", - "PCIE_ER1BEG1_3", - "PCIE_ER1BEG1_4", - "PCIE_ER1BEG1_5", - "PCIE_ER1BEG1_6", - "PCIE_ER1BEG1_7", - "PCIE_ER1BEG1_8", - "PCIE_ER1BEG1_9", - "PCIE_ER1BEG2_0", - "PCIE_ER1BEG2_1", - "PCIE_ER1BEG2_10", - "PCIE_ER1BEG2_11", - "PCIE_ER1BEG2_12", - "PCIE_ER1BEG2_13", - "PCIE_ER1BEG2_14", - "PCIE_ER1BEG2_15", - "PCIE_ER1BEG2_16", - "PCIE_ER1BEG2_17", - "PCIE_ER1BEG2_18", - "PCIE_ER1BEG2_19", - "PCIE_ER1BEG2_2", - "PCIE_ER1BEG2_3", - "PCIE_ER1BEG2_4", - "PCIE_ER1BEG2_5", - "PCIE_ER1BEG2_6", - "PCIE_ER1BEG2_7", - "PCIE_ER1BEG2_8", - "PCIE_ER1BEG2_9", - "PCIE_ER1BEG3_0", - "PCIE_ER1BEG3_1", - "PCIE_ER1BEG3_10", - "PCIE_ER1BEG3_11", - "PCIE_ER1BEG3_12", - "PCIE_ER1BEG3_13", - "PCIE_ER1BEG3_14", - "PCIE_ER1BEG3_15", - "PCIE_ER1BEG3_16", - "PCIE_ER1BEG3_17", - "PCIE_ER1BEG3_18", - "PCIE_ER1BEG3_19", - "PCIE_ER1BEG3_2", - "PCIE_ER1BEG3_3", - "PCIE_ER1BEG3_4", - "PCIE_ER1BEG3_5", - "PCIE_ER1BEG3_6", - "PCIE_ER1BEG3_7", - "PCIE_ER1BEG3_8", - "PCIE_ER1BEG3_9", - "PCIE_FAN0_L_0", - "PCIE_FAN0_L_1", - "PCIE_FAN0_L_10", - "PCIE_FAN0_L_11", - "PCIE_FAN0_L_12", - "PCIE_FAN0_L_13", - "PCIE_FAN0_L_14", - "PCIE_FAN0_L_15", - "PCIE_FAN0_L_16", - "PCIE_FAN0_L_17", - "PCIE_FAN0_L_18", - "PCIE_FAN0_L_19", - "PCIE_FAN0_L_2", - "PCIE_FAN0_L_3", - "PCIE_FAN0_L_4", - "PCIE_FAN0_L_5", - "PCIE_FAN0_L_6", - "PCIE_FAN0_L_7", - "PCIE_FAN0_L_8", - "PCIE_FAN0_L_9", - "PCIE_FAN0_R_0", - "PCIE_FAN0_R_1", - "PCIE_FAN0_R_10", - "PCIE_FAN0_R_11", - "PCIE_FAN0_R_12", - "PCIE_FAN0_R_13", - "PCIE_FAN0_R_14", - "PCIE_FAN0_R_15", - "PCIE_FAN0_R_16", - "PCIE_FAN0_R_17", - "PCIE_FAN0_R_18", - "PCIE_FAN0_R_19", - "PCIE_FAN0_R_2", - "PCIE_FAN0_R_3", - "PCIE_FAN0_R_4", - "PCIE_FAN0_R_5", - "PCIE_FAN0_R_6", - "PCIE_FAN0_R_7", - "PCIE_FAN0_R_8", - "PCIE_FAN0_R_9", - "PCIE_FAN1_L_0", - "PCIE_FAN1_L_1", - "PCIE_FAN1_L_10", - "PCIE_FAN1_L_11", - "PCIE_FAN1_L_12", - "PCIE_FAN1_L_13", - "PCIE_FAN1_L_14", - "PCIE_FAN1_L_15", - "PCIE_FAN1_L_16", - "PCIE_FAN1_L_17", - "PCIE_FAN1_L_18", - "PCIE_FAN1_L_19", - "PCIE_FAN1_L_2", - "PCIE_FAN1_L_3", - "PCIE_FAN1_L_4", - "PCIE_FAN1_L_5", - "PCIE_FAN1_L_6", - "PCIE_FAN1_L_7", - "PCIE_FAN1_L_8", - "PCIE_FAN1_L_9", - "PCIE_FAN1_R_0", - "PCIE_FAN1_R_1", - "PCIE_FAN1_R_10", - "PCIE_FAN1_R_11", - "PCIE_FAN1_R_12", - "PCIE_FAN1_R_13", - "PCIE_FAN1_R_14", - "PCIE_FAN1_R_15", - "PCIE_FAN1_R_16", - "PCIE_FAN1_R_17", - "PCIE_FAN1_R_18", - "PCIE_FAN1_R_19", - "PCIE_FAN1_R_2", - "PCIE_FAN1_R_3", - "PCIE_FAN1_R_4", - "PCIE_FAN1_R_5", - "PCIE_FAN1_R_6", - "PCIE_FAN1_R_7", - "PCIE_FAN1_R_8", - "PCIE_FAN1_R_9", - "PCIE_FAN2_L_0", - "PCIE_FAN2_L_1", - "PCIE_FAN2_L_10", - "PCIE_FAN2_L_11", - "PCIE_FAN2_L_12", - "PCIE_FAN2_L_13", - "PCIE_FAN2_L_14", - "PCIE_FAN2_L_15", - "PCIE_FAN2_L_16", - "PCIE_FAN2_L_17", - "PCIE_FAN2_L_18", - "PCIE_FAN2_L_19", - "PCIE_FAN2_L_2", - "PCIE_FAN2_L_3", - "PCIE_FAN2_L_4", - "PCIE_FAN2_L_5", - "PCIE_FAN2_L_6", - "PCIE_FAN2_L_7", - "PCIE_FAN2_L_8", - "PCIE_FAN2_L_9", - "PCIE_FAN2_R_0", - "PCIE_FAN2_R_1", - "PCIE_FAN2_R_10", - "PCIE_FAN2_R_11", - "PCIE_FAN2_R_12", - "PCIE_FAN2_R_13", - "PCIE_FAN2_R_14", - "PCIE_FAN2_R_15", - "PCIE_FAN2_R_16", - "PCIE_FAN2_R_17", - "PCIE_FAN2_R_18", - "PCIE_FAN2_R_19", - "PCIE_FAN2_R_2", - "PCIE_FAN2_R_3", - "PCIE_FAN2_R_4", - "PCIE_FAN2_R_5", - "PCIE_FAN2_R_6", - "PCIE_FAN2_R_7", - "PCIE_FAN2_R_8", - "PCIE_FAN2_R_9", - "PCIE_FAN3_L_0", - "PCIE_FAN3_L_1", - "PCIE_FAN3_L_10", - "PCIE_FAN3_L_11", - "PCIE_FAN3_L_12", - "PCIE_FAN3_L_13", - "PCIE_FAN3_L_14", - "PCIE_FAN3_L_15", - "PCIE_FAN3_L_16", - "PCIE_FAN3_L_17", - "PCIE_FAN3_L_18", - "PCIE_FAN3_L_19", - "PCIE_FAN3_L_2", - "PCIE_FAN3_L_3", - "PCIE_FAN3_L_4", - "PCIE_FAN3_L_5", - "PCIE_FAN3_L_6", - "PCIE_FAN3_L_7", - "PCIE_FAN3_L_8", - "PCIE_FAN3_L_9", - "PCIE_FAN3_R_0", - "PCIE_FAN3_R_1", - "PCIE_FAN3_R_10", - "PCIE_FAN3_R_11", - "PCIE_FAN3_R_12", - "PCIE_FAN3_R_13", - "PCIE_FAN3_R_14", - "PCIE_FAN3_R_15", - "PCIE_FAN3_R_16", - "PCIE_FAN3_R_17", - "PCIE_FAN3_R_18", - "PCIE_FAN3_R_19", - "PCIE_FAN3_R_2", - "PCIE_FAN3_R_3", - "PCIE_FAN3_R_4", - "PCIE_FAN3_R_5", - "PCIE_FAN3_R_6", - "PCIE_FAN3_R_7", - "PCIE_FAN3_R_8", - "PCIE_FAN3_R_9", - "PCIE_FAN4_L_0", - "PCIE_FAN4_L_1", - "PCIE_FAN4_L_10", - "PCIE_FAN4_L_11", - "PCIE_FAN4_L_12", - "PCIE_FAN4_L_13", - "PCIE_FAN4_L_14", - "PCIE_FAN4_L_15", - "PCIE_FAN4_L_16", - "PCIE_FAN4_L_17", - "PCIE_FAN4_L_18", - "PCIE_FAN4_L_19", - "PCIE_FAN4_L_2", - "PCIE_FAN4_L_3", - "PCIE_FAN4_L_4", - "PCIE_FAN4_L_5", - "PCIE_FAN4_L_6", - "PCIE_FAN4_L_7", - "PCIE_FAN4_L_8", - "PCIE_FAN4_L_9", - "PCIE_FAN4_R_0", - "PCIE_FAN4_R_1", - "PCIE_FAN4_R_10", - "PCIE_FAN4_R_11", - "PCIE_FAN4_R_12", - "PCIE_FAN4_R_13", - "PCIE_FAN4_R_14", - "PCIE_FAN4_R_15", - "PCIE_FAN4_R_16", - "PCIE_FAN4_R_17", - "PCIE_FAN4_R_18", - "PCIE_FAN4_R_19", - "PCIE_FAN4_R_2", - "PCIE_FAN4_R_3", - "PCIE_FAN4_R_4", - "PCIE_FAN4_R_5", - "PCIE_FAN4_R_6", - "PCIE_FAN4_R_7", - "PCIE_FAN4_R_8", - "PCIE_FAN4_R_9", - "PCIE_FAN5_L_0", - "PCIE_FAN5_L_1", - "PCIE_FAN5_L_10", - "PCIE_FAN5_L_11", - "PCIE_FAN5_L_12", - "PCIE_FAN5_L_13", - "PCIE_FAN5_L_14", - "PCIE_FAN5_L_15", - "PCIE_FAN5_L_16", - "PCIE_FAN5_L_17", - "PCIE_FAN5_L_18", - "PCIE_FAN5_L_19", - "PCIE_FAN5_L_2", - "PCIE_FAN5_L_3", - "PCIE_FAN5_L_4", - "PCIE_FAN5_L_5", - "PCIE_FAN5_L_6", - "PCIE_FAN5_L_7", - "PCIE_FAN5_L_8", - "PCIE_FAN5_L_9", - "PCIE_FAN5_R_0", - "PCIE_FAN5_R_1", - "PCIE_FAN5_R_10", - "PCIE_FAN5_R_11", - "PCIE_FAN5_R_12", - "PCIE_FAN5_R_13", - "PCIE_FAN5_R_14", - "PCIE_FAN5_R_15", - "PCIE_FAN5_R_16", - "PCIE_FAN5_R_17", - "PCIE_FAN5_R_18", - "PCIE_FAN5_R_19", - "PCIE_FAN5_R_2", - "PCIE_FAN5_R_3", - "PCIE_FAN5_R_4", - "PCIE_FAN5_R_5", - "PCIE_FAN5_R_6", - "PCIE_FAN5_R_7", - "PCIE_FAN5_R_8", - "PCIE_FAN5_R_9", - "PCIE_FAN6_L_0", - "PCIE_FAN6_L_1", - "PCIE_FAN6_L_10", - "PCIE_FAN6_L_11", - "PCIE_FAN6_L_12", - "PCIE_FAN6_L_13", - "PCIE_FAN6_L_14", - "PCIE_FAN6_L_15", - "PCIE_FAN6_L_16", - "PCIE_FAN6_L_17", - "PCIE_FAN6_L_18", - "PCIE_FAN6_L_19", - "PCIE_FAN6_L_2", - "PCIE_FAN6_L_3", - "PCIE_FAN6_L_4", - "PCIE_FAN6_L_5", - "PCIE_FAN6_L_6", - "PCIE_FAN6_L_7", - "PCIE_FAN6_L_8", - "PCIE_FAN6_L_9", - "PCIE_FAN6_R_0", - "PCIE_FAN6_R_1", - "PCIE_FAN6_R_10", - "PCIE_FAN6_R_11", - "PCIE_FAN6_R_12", - "PCIE_FAN6_R_13", - "PCIE_FAN6_R_14", - "PCIE_FAN6_R_15", - "PCIE_FAN6_R_16", - "PCIE_FAN6_R_17", - "PCIE_FAN6_R_18", - "PCIE_FAN6_R_19", - "PCIE_FAN6_R_2", - "PCIE_FAN6_R_3", - "PCIE_FAN6_R_4", - "PCIE_FAN6_R_5", - "PCIE_FAN6_R_6", - "PCIE_FAN6_R_7", - "PCIE_FAN6_R_8", - "PCIE_FAN6_R_9", - "PCIE_FAN7_L_0", - "PCIE_FAN7_L_1", - "PCIE_FAN7_L_10", - "PCIE_FAN7_L_11", - "PCIE_FAN7_L_12", - "PCIE_FAN7_L_13", - "PCIE_FAN7_L_14", - "PCIE_FAN7_L_15", - "PCIE_FAN7_L_16", - "PCIE_FAN7_L_17", - "PCIE_FAN7_L_18", - "PCIE_FAN7_L_19", - "PCIE_FAN7_L_2", - "PCIE_FAN7_L_3", - "PCIE_FAN7_L_4", - "PCIE_FAN7_L_5", - "PCIE_FAN7_L_6", - "PCIE_FAN7_L_7", - "PCIE_FAN7_L_8", - "PCIE_FAN7_L_9", - "PCIE_FAN7_R_0", - "PCIE_FAN7_R_1", - "PCIE_FAN7_R_10", - "PCIE_FAN7_R_11", - "PCIE_FAN7_R_12", - "PCIE_FAN7_R_13", - "PCIE_FAN7_R_14", - "PCIE_FAN7_R_15", - "PCIE_FAN7_R_16", - "PCIE_FAN7_R_17", - "PCIE_FAN7_R_18", - "PCIE_FAN7_R_19", - "PCIE_FAN7_R_2", - "PCIE_FAN7_R_3", - "PCIE_FAN7_R_4", - "PCIE_FAN7_R_5", - "PCIE_FAN7_R_6", - "PCIE_FAN7_R_7", - "PCIE_FAN7_R_8", - "PCIE_FAN7_R_9", - "PCIE_FUNCLVLRSTN", - "PCIE_IMUX0_L_0", - "PCIE_IMUX0_L_1", - "PCIE_IMUX0_L_10", - "PCIE_IMUX0_L_11", - "PCIE_IMUX0_L_12", - "PCIE_IMUX0_L_13", - "PCIE_IMUX0_L_14", - "PCIE_IMUX0_L_15", - "PCIE_IMUX0_L_16", - "PCIE_IMUX0_L_17", - "PCIE_IMUX0_L_18", - "PCIE_IMUX0_L_19", - "PCIE_IMUX0_L_2", - "PCIE_IMUX0_L_3", - "PCIE_IMUX0_L_4", - "PCIE_IMUX0_L_5", - "PCIE_IMUX0_L_6", - "PCIE_IMUX0_L_7", - "PCIE_IMUX0_L_8", - "PCIE_IMUX0_L_9", - "PCIE_IMUX0_R_0", - "PCIE_IMUX0_R_1", - "PCIE_IMUX0_R_10", - "PCIE_IMUX0_R_11", - "PCIE_IMUX0_R_12", - "PCIE_IMUX0_R_13", - "PCIE_IMUX0_R_14", - "PCIE_IMUX0_R_15", - "PCIE_IMUX0_R_16", - "PCIE_IMUX0_R_17", - "PCIE_IMUX0_R_18", - "PCIE_IMUX0_R_19", - "PCIE_IMUX0_R_2", - "PCIE_IMUX0_R_3", - "PCIE_IMUX0_R_4", - "PCIE_IMUX0_R_5", - "PCIE_IMUX0_R_6", - "PCIE_IMUX0_R_7", - "PCIE_IMUX0_R_8", - "PCIE_IMUX0_R_9", - "PCIE_IMUX10_L_0", - "PCIE_IMUX10_L_1", - "PCIE_IMUX10_L_10", - "PCIE_IMUX10_L_11", - "PCIE_IMUX10_L_12", - "PCIE_IMUX10_L_13", - "PCIE_IMUX10_L_14", - "PCIE_IMUX10_L_15", - "PCIE_IMUX10_L_16", - "PCIE_IMUX10_L_17", - "PCIE_IMUX10_L_18", - "PCIE_IMUX10_L_19", - "PCIE_IMUX10_L_2", - "PCIE_IMUX10_L_3", - "PCIE_IMUX10_L_4", - "PCIE_IMUX10_L_5", - "PCIE_IMUX10_L_6", - "PCIE_IMUX10_L_7", - "PCIE_IMUX10_L_8", - "PCIE_IMUX10_L_9", - "PCIE_IMUX10_R_0", - "PCIE_IMUX10_R_1", - "PCIE_IMUX10_R_10", - "PCIE_IMUX10_R_11", - "PCIE_IMUX10_R_12", - "PCIE_IMUX10_R_13", - "PCIE_IMUX10_R_14", - "PCIE_IMUX10_R_15", - "PCIE_IMUX10_R_16", - "PCIE_IMUX10_R_17", - "PCIE_IMUX10_R_18", - "PCIE_IMUX10_R_19", - "PCIE_IMUX10_R_2", - "PCIE_IMUX10_R_3", - "PCIE_IMUX10_R_4", - "PCIE_IMUX10_R_5", - "PCIE_IMUX10_R_6", - "PCIE_IMUX10_R_7", - "PCIE_IMUX10_R_8", - "PCIE_IMUX10_R_9", - "PCIE_IMUX11_L_0", - "PCIE_IMUX11_L_1", - "PCIE_IMUX11_L_10", - "PCIE_IMUX11_L_11", - "PCIE_IMUX11_L_12", - "PCIE_IMUX11_L_13", - "PCIE_IMUX11_L_14", - "PCIE_IMUX11_L_15", - "PCIE_IMUX11_L_16", - "PCIE_IMUX11_L_17", - "PCIE_IMUX11_L_18", - "PCIE_IMUX11_L_19", - "PCIE_IMUX11_L_2", - "PCIE_IMUX11_L_3", - "PCIE_IMUX11_L_4", - "PCIE_IMUX11_L_5", - "PCIE_IMUX11_L_6", - "PCIE_IMUX11_L_7", - "PCIE_IMUX11_L_8", - "PCIE_IMUX11_L_9", - "PCIE_IMUX11_R_0", - "PCIE_IMUX11_R_1", - "PCIE_IMUX11_R_10", - "PCIE_IMUX11_R_11", - "PCIE_IMUX11_R_12", - "PCIE_IMUX11_R_13", - "PCIE_IMUX11_R_14", - "PCIE_IMUX11_R_15", - "PCIE_IMUX11_R_16", - "PCIE_IMUX11_R_17", - "PCIE_IMUX11_R_18", - "PCIE_IMUX11_R_19", - "PCIE_IMUX11_R_2", - "PCIE_IMUX11_R_3", - "PCIE_IMUX11_R_4", - "PCIE_IMUX11_R_5", - "PCIE_IMUX11_R_6", - "PCIE_IMUX11_R_7", - "PCIE_IMUX11_R_8", - "PCIE_IMUX11_R_9", - "PCIE_IMUX12_L_0", - "PCIE_IMUX12_L_1", - "PCIE_IMUX12_L_10", - "PCIE_IMUX12_L_11", - "PCIE_IMUX12_L_12", - "PCIE_IMUX12_L_13", - "PCIE_IMUX12_L_14", - "PCIE_IMUX12_L_15", - "PCIE_IMUX12_L_16", - "PCIE_IMUX12_L_17", - "PCIE_IMUX12_L_18", - "PCIE_IMUX12_L_19", - "PCIE_IMUX12_L_2", - "PCIE_IMUX12_L_3", - "PCIE_IMUX12_L_4", - "PCIE_IMUX12_L_5", - "PCIE_IMUX12_L_6", - "PCIE_IMUX12_L_7", - "PCIE_IMUX12_L_8", - "PCIE_IMUX12_L_9", - "PCIE_IMUX12_R_0", - "PCIE_IMUX12_R_1", - "PCIE_IMUX12_R_10", - "PCIE_IMUX12_R_11", - "PCIE_IMUX12_R_12", - "PCIE_IMUX12_R_13", - "PCIE_IMUX12_R_14", - "PCIE_IMUX12_R_15", - "PCIE_IMUX12_R_16", - "PCIE_IMUX12_R_17", - "PCIE_IMUX12_R_18", - "PCIE_IMUX12_R_19", - "PCIE_IMUX12_R_2", - "PCIE_IMUX12_R_3", - "PCIE_IMUX12_R_4", - "PCIE_IMUX12_R_5", - "PCIE_IMUX12_R_6", - "PCIE_IMUX12_R_7", - "PCIE_IMUX12_R_8", - "PCIE_IMUX12_R_9", - "PCIE_IMUX13_L_0", - "PCIE_IMUX13_L_1", - "PCIE_IMUX13_L_10", - "PCIE_IMUX13_L_11", - "PCIE_IMUX13_L_12", - "PCIE_IMUX13_L_13", - "PCIE_IMUX13_L_14", - "PCIE_IMUX13_L_15", - "PCIE_IMUX13_L_16", - "PCIE_IMUX13_L_17", - "PCIE_IMUX13_L_18", - "PCIE_IMUX13_L_19", - "PCIE_IMUX13_L_2", - "PCIE_IMUX13_L_3", - "PCIE_IMUX13_L_4", - "PCIE_IMUX13_L_5", - "PCIE_IMUX13_L_6", - "PCIE_IMUX13_L_7", - "PCIE_IMUX13_L_8", - "PCIE_IMUX13_L_9", - "PCIE_IMUX13_R_0", - "PCIE_IMUX13_R_1", - "PCIE_IMUX13_R_10", - "PCIE_IMUX13_R_11", - "PCIE_IMUX13_R_12", - "PCIE_IMUX13_R_13", - "PCIE_IMUX13_R_14", - "PCIE_IMUX13_R_15", - "PCIE_IMUX13_R_16", - "PCIE_IMUX13_R_17", - "PCIE_IMUX13_R_18", - "PCIE_IMUX13_R_19", - "PCIE_IMUX13_R_2", - "PCIE_IMUX13_R_3", - "PCIE_IMUX13_R_4", - "PCIE_IMUX13_R_5", - "PCIE_IMUX13_R_6", - "PCIE_IMUX13_R_7", - "PCIE_IMUX13_R_8", - "PCIE_IMUX13_R_9", - "PCIE_IMUX14_L_0", - "PCIE_IMUX14_L_1", - "PCIE_IMUX14_L_10", - "PCIE_IMUX14_L_11", - "PCIE_IMUX14_L_12", - "PCIE_IMUX14_L_13", - "PCIE_IMUX14_L_14", - "PCIE_IMUX14_L_15", - "PCIE_IMUX14_L_16", - "PCIE_IMUX14_L_17", - "PCIE_IMUX14_L_18", - "PCIE_IMUX14_L_19", - "PCIE_IMUX14_L_2", - "PCIE_IMUX14_L_3", - "PCIE_IMUX14_L_4", - "PCIE_IMUX14_L_5", - "PCIE_IMUX14_L_6", - "PCIE_IMUX14_L_7", - "PCIE_IMUX14_L_8", - "PCIE_IMUX14_L_9", - "PCIE_IMUX14_R_0", - "PCIE_IMUX14_R_1", - "PCIE_IMUX14_R_10", - "PCIE_IMUX14_R_11", - "PCIE_IMUX14_R_12", - "PCIE_IMUX14_R_13", - "PCIE_IMUX14_R_14", - "PCIE_IMUX14_R_15", - "PCIE_IMUX14_R_16", - "PCIE_IMUX14_R_17", - "PCIE_IMUX14_R_18", - "PCIE_IMUX14_R_19", - "PCIE_IMUX14_R_2", - "PCIE_IMUX14_R_3", - "PCIE_IMUX14_R_4", - "PCIE_IMUX14_R_5", - "PCIE_IMUX14_R_6", - "PCIE_IMUX14_R_7", - "PCIE_IMUX14_R_8", - "PCIE_IMUX14_R_9", - "PCIE_IMUX15_L_0", - "PCIE_IMUX15_L_1", - "PCIE_IMUX15_L_10", - "PCIE_IMUX15_L_11", - "PCIE_IMUX15_L_12", - "PCIE_IMUX15_L_13", - "PCIE_IMUX15_L_14", - "PCIE_IMUX15_L_15", - "PCIE_IMUX15_L_16", - "PCIE_IMUX15_L_17", - "PCIE_IMUX15_L_18", - "PCIE_IMUX15_L_19", - "PCIE_IMUX15_L_2", - "PCIE_IMUX15_L_3", - "PCIE_IMUX15_L_4", - "PCIE_IMUX15_L_5", - "PCIE_IMUX15_L_6", - "PCIE_IMUX15_L_7", - "PCIE_IMUX15_L_8", - "PCIE_IMUX15_L_9", - "PCIE_IMUX15_R_0", - "PCIE_IMUX15_R_1", - "PCIE_IMUX15_R_10", - "PCIE_IMUX15_R_11", - "PCIE_IMUX15_R_12", - "PCIE_IMUX15_R_13", - "PCIE_IMUX15_R_14", - "PCIE_IMUX15_R_15", - "PCIE_IMUX15_R_16", - "PCIE_IMUX15_R_17", - "PCIE_IMUX15_R_18", - "PCIE_IMUX15_R_19", - "PCIE_IMUX15_R_2", - "PCIE_IMUX15_R_3", - "PCIE_IMUX15_R_4", - "PCIE_IMUX15_R_5", - "PCIE_IMUX15_R_6", - "PCIE_IMUX15_R_7", - "PCIE_IMUX15_R_8", - "PCIE_IMUX15_R_9", - "PCIE_IMUX16_L_0", - "PCIE_IMUX16_L_1", - "PCIE_IMUX16_L_10", - "PCIE_IMUX16_L_11", - "PCIE_IMUX16_L_12", - "PCIE_IMUX16_L_13", - "PCIE_IMUX16_L_14", - "PCIE_IMUX16_L_15", - "PCIE_IMUX16_L_16", - "PCIE_IMUX16_L_17", - "PCIE_IMUX16_L_18", - "PCIE_IMUX16_L_19", - "PCIE_IMUX16_L_2", - "PCIE_IMUX16_L_3", - "PCIE_IMUX16_L_4", - "PCIE_IMUX16_L_5", - "PCIE_IMUX16_L_6", - "PCIE_IMUX16_L_7", - "PCIE_IMUX16_L_8", - "PCIE_IMUX16_L_9", - "PCIE_IMUX16_R_0", - "PCIE_IMUX16_R_1", - "PCIE_IMUX16_R_10", - "PCIE_IMUX16_R_11", - "PCIE_IMUX16_R_12", - "PCIE_IMUX16_R_13", - "PCIE_IMUX16_R_14", - "PCIE_IMUX16_R_15", - "PCIE_IMUX16_R_16", - "PCIE_IMUX16_R_17", - "PCIE_IMUX16_R_18", - "PCIE_IMUX16_R_19", - "PCIE_IMUX16_R_2", - "PCIE_IMUX16_R_3", - "PCIE_IMUX16_R_4", - "PCIE_IMUX16_R_5", - "PCIE_IMUX16_R_6", - "PCIE_IMUX16_R_7", - "PCIE_IMUX16_R_8", - "PCIE_IMUX16_R_9", - "PCIE_IMUX17_L_0", - "PCIE_IMUX17_L_1", - "PCIE_IMUX17_L_10", - "PCIE_IMUX17_L_11", - "PCIE_IMUX17_L_12", - "PCIE_IMUX17_L_13", - "PCIE_IMUX17_L_14", - "PCIE_IMUX17_L_15", - "PCIE_IMUX17_L_16", - "PCIE_IMUX17_L_17", - "PCIE_IMUX17_L_18", - "PCIE_IMUX17_L_19", - "PCIE_IMUX17_L_2", - "PCIE_IMUX17_L_3", - "PCIE_IMUX17_L_4", - "PCIE_IMUX17_L_5", - "PCIE_IMUX17_L_6", - "PCIE_IMUX17_L_7", - "PCIE_IMUX17_L_8", - "PCIE_IMUX17_L_9", - "PCIE_IMUX17_R_0", - "PCIE_IMUX17_R_1", - "PCIE_IMUX17_R_10", - "PCIE_IMUX17_R_11", - "PCIE_IMUX17_R_12", - "PCIE_IMUX17_R_13", - "PCIE_IMUX17_R_14", - "PCIE_IMUX17_R_15", - "PCIE_IMUX17_R_16", - "PCIE_IMUX17_R_17", - "PCIE_IMUX17_R_18", - "PCIE_IMUX17_R_19", - "PCIE_IMUX17_R_2", - "PCIE_IMUX17_R_3", - "PCIE_IMUX17_R_4", - "PCIE_IMUX17_R_5", - "PCIE_IMUX17_R_6", - "PCIE_IMUX17_R_7", - "PCIE_IMUX17_R_8", - "PCIE_IMUX17_R_9", - "PCIE_IMUX18_L_0", - "PCIE_IMUX18_L_1", - "PCIE_IMUX18_L_10", - "PCIE_IMUX18_L_11", - "PCIE_IMUX18_L_12", - "PCIE_IMUX18_L_13", - "PCIE_IMUX18_L_14", - "PCIE_IMUX18_L_15", - "PCIE_IMUX18_L_16", - "PCIE_IMUX18_L_17", - "PCIE_IMUX18_L_18", - "PCIE_IMUX18_L_19", - "PCIE_IMUX18_L_2", - "PCIE_IMUX18_L_3", - "PCIE_IMUX18_L_4", - "PCIE_IMUX18_L_5", - "PCIE_IMUX18_L_6", - "PCIE_IMUX18_L_7", - "PCIE_IMUX18_L_8", - "PCIE_IMUX18_L_9", - "PCIE_IMUX18_R_0", - "PCIE_IMUX18_R_1", - "PCIE_IMUX18_R_10", - "PCIE_IMUX18_R_11", - "PCIE_IMUX18_R_12", - "PCIE_IMUX18_R_13", - "PCIE_IMUX18_R_14", - "PCIE_IMUX18_R_15", - "PCIE_IMUX18_R_16", - "PCIE_IMUX18_R_17", - "PCIE_IMUX18_R_18", - "PCIE_IMUX18_R_19", - "PCIE_IMUX18_R_2", - "PCIE_IMUX18_R_3", - "PCIE_IMUX18_R_4", - "PCIE_IMUX18_R_5", - "PCIE_IMUX18_R_6", - "PCIE_IMUX18_R_7", - "PCIE_IMUX18_R_8", - "PCIE_IMUX18_R_9", - "PCIE_IMUX19_L_0", - "PCIE_IMUX19_L_1", - "PCIE_IMUX19_L_10", - "PCIE_IMUX19_L_11", - "PCIE_IMUX19_L_12", - "PCIE_IMUX19_L_13", - "PCIE_IMUX19_L_14", - "PCIE_IMUX19_L_15", - "PCIE_IMUX19_L_16", - "PCIE_IMUX19_L_17", - "PCIE_IMUX19_L_18", - "PCIE_IMUX19_L_19", - "PCIE_IMUX19_L_2", - "PCIE_IMUX19_L_3", - "PCIE_IMUX19_L_4", - "PCIE_IMUX19_L_5", - "PCIE_IMUX19_L_6", - "PCIE_IMUX19_L_7", - "PCIE_IMUX19_L_8", - "PCIE_IMUX19_L_9", - "PCIE_IMUX19_R_0", - "PCIE_IMUX19_R_1", - "PCIE_IMUX19_R_10", - "PCIE_IMUX19_R_11", - "PCIE_IMUX19_R_12", - "PCIE_IMUX19_R_13", - "PCIE_IMUX19_R_14", - "PCIE_IMUX19_R_15", - "PCIE_IMUX19_R_16", - "PCIE_IMUX19_R_17", - "PCIE_IMUX19_R_18", - "PCIE_IMUX19_R_19", - "PCIE_IMUX19_R_2", - "PCIE_IMUX19_R_3", - "PCIE_IMUX19_R_4", - "PCIE_IMUX19_R_5", - "PCIE_IMUX19_R_6", - "PCIE_IMUX19_R_7", - "PCIE_IMUX19_R_8", - "PCIE_IMUX19_R_9", - "PCIE_IMUX1_L_0", - "PCIE_IMUX1_L_1", - "PCIE_IMUX1_L_10", - "PCIE_IMUX1_L_11", - "PCIE_IMUX1_L_12", - "PCIE_IMUX1_L_13", - "PCIE_IMUX1_L_14", - "PCIE_IMUX1_L_15", - "PCIE_IMUX1_L_16", - "PCIE_IMUX1_L_17", - "PCIE_IMUX1_L_18", - "PCIE_IMUX1_L_19", - "PCIE_IMUX1_L_2", - "PCIE_IMUX1_L_3", - "PCIE_IMUX1_L_4", - "PCIE_IMUX1_L_5", - "PCIE_IMUX1_L_6", - "PCIE_IMUX1_L_7", - "PCIE_IMUX1_L_8", - "PCIE_IMUX1_L_9", - "PCIE_IMUX1_R_0", - "PCIE_IMUX1_R_1", - "PCIE_IMUX1_R_10", - "PCIE_IMUX1_R_11", - "PCIE_IMUX1_R_12", - "PCIE_IMUX1_R_13", - "PCIE_IMUX1_R_14", - "PCIE_IMUX1_R_15", - "PCIE_IMUX1_R_16", - "PCIE_IMUX1_R_17", - "PCIE_IMUX1_R_18", - "PCIE_IMUX1_R_19", - "PCIE_IMUX1_R_2", - "PCIE_IMUX1_R_3", - "PCIE_IMUX1_R_4", - "PCIE_IMUX1_R_5", - "PCIE_IMUX1_R_6", - "PCIE_IMUX1_R_7", - "PCIE_IMUX1_R_8", - "PCIE_IMUX1_R_9", - "PCIE_IMUX20_L_0", - "PCIE_IMUX20_L_1", - "PCIE_IMUX20_L_10", - "PCIE_IMUX20_L_11", - "PCIE_IMUX20_L_12", - "PCIE_IMUX20_L_13", - "PCIE_IMUX20_L_14", - "PCIE_IMUX20_L_15", - "PCIE_IMUX20_L_16", - "PCIE_IMUX20_L_17", - "PCIE_IMUX20_L_18", - "PCIE_IMUX20_L_19", - "PCIE_IMUX20_L_2", - "PCIE_IMUX20_L_3", - "PCIE_IMUX20_L_4", - "PCIE_IMUX20_L_5", - "PCIE_IMUX20_L_6", - "PCIE_IMUX20_L_7", - "PCIE_IMUX20_L_8", - "PCIE_IMUX20_L_9", - "PCIE_IMUX20_R_0", - "PCIE_IMUX20_R_1", - "PCIE_IMUX20_R_10", - "PCIE_IMUX20_R_11", - "PCIE_IMUX20_R_12", - "PCIE_IMUX20_R_13", - "PCIE_IMUX20_R_14", - "PCIE_IMUX20_R_15", - "PCIE_IMUX20_R_16", - "PCIE_IMUX20_R_17", - "PCIE_IMUX20_R_18", - "PCIE_IMUX20_R_19", - "PCIE_IMUX20_R_2", - "PCIE_IMUX20_R_3", - "PCIE_IMUX20_R_4", - "PCIE_IMUX20_R_5", - "PCIE_IMUX20_R_6", - "PCIE_IMUX20_R_7", - "PCIE_IMUX20_R_8", - "PCIE_IMUX20_R_9", - "PCIE_IMUX21_L_0", - "PCIE_IMUX21_L_1", - "PCIE_IMUX21_L_10", - "PCIE_IMUX21_L_11", - "PCIE_IMUX21_L_12", - "PCIE_IMUX21_L_13", - "PCIE_IMUX21_L_14", - "PCIE_IMUX21_L_15", - "PCIE_IMUX21_L_16", - "PCIE_IMUX21_L_17", - "PCIE_IMUX21_L_18", - "PCIE_IMUX21_L_19", - "PCIE_IMUX21_L_2", - "PCIE_IMUX21_L_3", - "PCIE_IMUX21_L_4", - "PCIE_IMUX21_L_5", - "PCIE_IMUX21_L_6", - "PCIE_IMUX21_L_7", - "PCIE_IMUX21_L_8", - "PCIE_IMUX21_L_9", - "PCIE_IMUX21_R_0", - "PCIE_IMUX21_R_1", - "PCIE_IMUX21_R_10", - "PCIE_IMUX21_R_11", - "PCIE_IMUX21_R_12", - "PCIE_IMUX21_R_13", - "PCIE_IMUX21_R_14", - "PCIE_IMUX21_R_15", - "PCIE_IMUX21_R_16", - "PCIE_IMUX21_R_17", - "PCIE_IMUX21_R_18", - "PCIE_IMUX21_R_19", - "PCIE_IMUX21_R_2", - "PCIE_IMUX21_R_3", - "PCIE_IMUX21_R_4", - "PCIE_IMUX21_R_5", - "PCIE_IMUX21_R_6", - "PCIE_IMUX21_R_7", - "PCIE_IMUX21_R_8", - "PCIE_IMUX21_R_9", - "PCIE_IMUX22_L_0", - "PCIE_IMUX22_L_1", - "PCIE_IMUX22_L_10", - "PCIE_IMUX22_L_11", - "PCIE_IMUX22_L_12", - "PCIE_IMUX22_L_13", - "PCIE_IMUX22_L_14", - "PCIE_IMUX22_L_15", - "PCIE_IMUX22_L_16", - "PCIE_IMUX22_L_17", - "PCIE_IMUX22_L_18", - "PCIE_IMUX22_L_19", - "PCIE_IMUX22_L_2", - "PCIE_IMUX22_L_3", - "PCIE_IMUX22_L_4", - "PCIE_IMUX22_L_5", - "PCIE_IMUX22_L_6", - "PCIE_IMUX22_L_7", - "PCIE_IMUX22_L_8", - "PCIE_IMUX22_L_9", - "PCIE_IMUX22_R_0", - "PCIE_IMUX22_R_1", - "PCIE_IMUX22_R_10", - "PCIE_IMUX22_R_11", - "PCIE_IMUX22_R_12", - "PCIE_IMUX22_R_13", - "PCIE_IMUX22_R_14", - "PCIE_IMUX22_R_15", - "PCIE_IMUX22_R_16", - "PCIE_IMUX22_R_17", - "PCIE_IMUX22_R_18", - "PCIE_IMUX22_R_19", - "PCIE_IMUX22_R_2", - "PCIE_IMUX22_R_3", - "PCIE_IMUX22_R_4", - "PCIE_IMUX22_R_5", - "PCIE_IMUX22_R_6", - "PCIE_IMUX22_R_7", - "PCIE_IMUX22_R_8", - "PCIE_IMUX22_R_9", - "PCIE_IMUX23_L_0", - "PCIE_IMUX23_L_1", - "PCIE_IMUX23_L_10", - "PCIE_IMUX23_L_11", - "PCIE_IMUX23_L_12", - "PCIE_IMUX23_L_13", - "PCIE_IMUX23_L_14", - "PCIE_IMUX23_L_15", - "PCIE_IMUX23_L_16", - "PCIE_IMUX23_L_17", - "PCIE_IMUX23_L_18", - "PCIE_IMUX23_L_19", - "PCIE_IMUX23_L_2", - "PCIE_IMUX23_L_3", - "PCIE_IMUX23_L_4", - "PCIE_IMUX23_L_5", - "PCIE_IMUX23_L_6", - "PCIE_IMUX23_L_7", - "PCIE_IMUX23_L_8", - "PCIE_IMUX23_L_9", - "PCIE_IMUX23_R_0", - "PCIE_IMUX23_R_1", - "PCIE_IMUX23_R_10", - "PCIE_IMUX23_R_11", - "PCIE_IMUX23_R_12", - "PCIE_IMUX23_R_13", - "PCIE_IMUX23_R_14", - "PCIE_IMUX23_R_15", - "PCIE_IMUX23_R_16", - "PCIE_IMUX23_R_17", - "PCIE_IMUX23_R_18", - "PCIE_IMUX23_R_19", - "PCIE_IMUX23_R_2", - "PCIE_IMUX23_R_3", - "PCIE_IMUX23_R_4", - "PCIE_IMUX23_R_5", - "PCIE_IMUX23_R_6", - "PCIE_IMUX23_R_7", - "PCIE_IMUX23_R_8", - "PCIE_IMUX23_R_9", - "PCIE_IMUX24_L_0", - "PCIE_IMUX24_L_1", - "PCIE_IMUX24_L_10", - "PCIE_IMUX24_L_11", - "PCIE_IMUX24_L_12", - "PCIE_IMUX24_L_13", - "PCIE_IMUX24_L_14", - "PCIE_IMUX24_L_15", - "PCIE_IMUX24_L_16", - "PCIE_IMUX24_L_17", - "PCIE_IMUX24_L_18", - "PCIE_IMUX24_L_19", - "PCIE_IMUX24_L_2", - "PCIE_IMUX24_L_3", - "PCIE_IMUX24_L_4", - "PCIE_IMUX24_L_5", - "PCIE_IMUX24_L_6", - "PCIE_IMUX24_L_7", - "PCIE_IMUX24_L_8", - "PCIE_IMUX24_L_9", - "PCIE_IMUX24_R_0", - "PCIE_IMUX24_R_1", - "PCIE_IMUX24_R_10", - "PCIE_IMUX24_R_11", - "PCIE_IMUX24_R_12", - "PCIE_IMUX24_R_13", - "PCIE_IMUX24_R_14", - "PCIE_IMUX24_R_15", - "PCIE_IMUX24_R_16", - "PCIE_IMUX24_R_17", - "PCIE_IMUX24_R_18", - "PCIE_IMUX24_R_19", - "PCIE_IMUX24_R_2", - "PCIE_IMUX24_R_3", - "PCIE_IMUX24_R_4", - "PCIE_IMUX24_R_5", - "PCIE_IMUX24_R_6", - "PCIE_IMUX24_R_7", - "PCIE_IMUX24_R_8", - "PCIE_IMUX24_R_9", - "PCIE_IMUX25_L_0", - "PCIE_IMUX25_L_1", - "PCIE_IMUX25_L_10", - "PCIE_IMUX25_L_11", - "PCIE_IMUX25_L_12", - "PCIE_IMUX25_L_13", - "PCIE_IMUX25_L_14", - "PCIE_IMUX25_L_15", - "PCIE_IMUX25_L_16", - "PCIE_IMUX25_L_17", - "PCIE_IMUX25_L_18", - "PCIE_IMUX25_L_19", - "PCIE_IMUX25_L_2", - "PCIE_IMUX25_L_3", - "PCIE_IMUX25_L_4", - "PCIE_IMUX25_L_5", - "PCIE_IMUX25_L_6", - "PCIE_IMUX25_L_7", - "PCIE_IMUX25_L_8", - "PCIE_IMUX25_L_9", - "PCIE_IMUX25_R_0", - "PCIE_IMUX25_R_1", - "PCIE_IMUX25_R_10", - "PCIE_IMUX25_R_11", - "PCIE_IMUX25_R_12", - "PCIE_IMUX25_R_13", - "PCIE_IMUX25_R_14", - "PCIE_IMUX25_R_15", - "PCIE_IMUX25_R_16", - "PCIE_IMUX25_R_17", - "PCIE_IMUX25_R_18", - "PCIE_IMUX25_R_19", - "PCIE_IMUX25_R_2", - "PCIE_IMUX25_R_3", - "PCIE_IMUX25_R_4", - "PCIE_IMUX25_R_5", - "PCIE_IMUX25_R_6", - "PCIE_IMUX25_R_7", - "PCIE_IMUX25_R_8", - "PCIE_IMUX25_R_9", - "PCIE_IMUX26_L_0", - "PCIE_IMUX26_L_1", - "PCIE_IMUX26_L_10", - "PCIE_IMUX26_L_11", - "PCIE_IMUX26_L_12", - "PCIE_IMUX26_L_13", - "PCIE_IMUX26_L_14", - "PCIE_IMUX26_L_15", - "PCIE_IMUX26_L_16", - "PCIE_IMUX26_L_17", - "PCIE_IMUX26_L_18", - "PCIE_IMUX26_L_19", - "PCIE_IMUX26_L_2", - "PCIE_IMUX26_L_3", - "PCIE_IMUX26_L_4", - "PCIE_IMUX26_L_5", - "PCIE_IMUX26_L_6", - "PCIE_IMUX26_L_7", - "PCIE_IMUX26_L_8", - "PCIE_IMUX26_L_9", - "PCIE_IMUX26_R_0", - "PCIE_IMUX26_R_1", - "PCIE_IMUX26_R_10", - "PCIE_IMUX26_R_11", - "PCIE_IMUX26_R_12", - "PCIE_IMUX26_R_13", - "PCIE_IMUX26_R_14", - "PCIE_IMUX26_R_15", - "PCIE_IMUX26_R_16", - "PCIE_IMUX26_R_17", - "PCIE_IMUX26_R_18", - "PCIE_IMUX26_R_19", - "PCIE_IMUX26_R_2", - "PCIE_IMUX26_R_3", - "PCIE_IMUX26_R_4", - "PCIE_IMUX26_R_5", - "PCIE_IMUX26_R_6", - "PCIE_IMUX26_R_7", - "PCIE_IMUX26_R_8", - "PCIE_IMUX26_R_9", - "PCIE_IMUX27_L_0", - "PCIE_IMUX27_L_1", - "PCIE_IMUX27_L_10", - "PCIE_IMUX27_L_11", - "PCIE_IMUX27_L_12", - "PCIE_IMUX27_L_13", - "PCIE_IMUX27_L_14", - "PCIE_IMUX27_L_15", - "PCIE_IMUX27_L_16", - "PCIE_IMUX27_L_17", - "PCIE_IMUX27_L_18", - "PCIE_IMUX27_L_19", - "PCIE_IMUX27_L_2", - "PCIE_IMUX27_L_3", - "PCIE_IMUX27_L_4", - "PCIE_IMUX27_L_5", - "PCIE_IMUX27_L_6", - "PCIE_IMUX27_L_7", - "PCIE_IMUX27_L_8", - "PCIE_IMUX27_L_9", - "PCIE_IMUX27_R_0", - "PCIE_IMUX27_R_1", - "PCIE_IMUX27_R_10", - "PCIE_IMUX27_R_11", - "PCIE_IMUX27_R_12", - "PCIE_IMUX27_R_13", - "PCIE_IMUX27_R_14", - "PCIE_IMUX27_R_15", - "PCIE_IMUX27_R_16", - "PCIE_IMUX27_R_17", - "PCIE_IMUX27_R_18", - "PCIE_IMUX27_R_19", - "PCIE_IMUX27_R_2", - "PCIE_IMUX27_R_3", - "PCIE_IMUX27_R_4", - "PCIE_IMUX27_R_5", - "PCIE_IMUX27_R_6", - "PCIE_IMUX27_R_7", - "PCIE_IMUX27_R_8", - "PCIE_IMUX27_R_9", - "PCIE_IMUX28_L_0", - "PCIE_IMUX28_L_1", - "PCIE_IMUX28_L_10", - "PCIE_IMUX28_L_11", - "PCIE_IMUX28_L_12", - "PCIE_IMUX28_L_13", - "PCIE_IMUX28_L_14", - "PCIE_IMUX28_L_15", - "PCIE_IMUX28_L_16", - "PCIE_IMUX28_L_17", - "PCIE_IMUX28_L_18", - "PCIE_IMUX28_L_19", - "PCIE_IMUX28_L_2", - "PCIE_IMUX28_L_3", - "PCIE_IMUX28_L_4", - "PCIE_IMUX28_L_5", - "PCIE_IMUX28_L_6", - "PCIE_IMUX28_L_7", - "PCIE_IMUX28_L_8", - "PCIE_IMUX28_L_9", - "PCIE_IMUX28_R_0", - "PCIE_IMUX28_R_1", - "PCIE_IMUX28_R_10", - "PCIE_IMUX28_R_11", - "PCIE_IMUX28_R_12", - "PCIE_IMUX28_R_13", - "PCIE_IMUX28_R_14", - "PCIE_IMUX28_R_15", - "PCIE_IMUX28_R_16", - "PCIE_IMUX28_R_17", - "PCIE_IMUX28_R_18", - "PCIE_IMUX28_R_19", - "PCIE_IMUX28_R_2", - "PCIE_IMUX28_R_3", - "PCIE_IMUX28_R_4", - "PCIE_IMUX28_R_5", - "PCIE_IMUX28_R_6", - "PCIE_IMUX28_R_7", - "PCIE_IMUX28_R_8", - "PCIE_IMUX28_R_9", - "PCIE_IMUX29_L_0", - "PCIE_IMUX29_L_1", - "PCIE_IMUX29_L_10", - "PCIE_IMUX29_L_11", - "PCIE_IMUX29_L_12", - "PCIE_IMUX29_L_13", - "PCIE_IMUX29_L_14", - "PCIE_IMUX29_L_15", - "PCIE_IMUX29_L_16", - "PCIE_IMUX29_L_17", - "PCIE_IMUX29_L_18", - "PCIE_IMUX29_L_19", - "PCIE_IMUX29_L_2", - "PCIE_IMUX29_L_3", - "PCIE_IMUX29_L_4", - "PCIE_IMUX29_L_5", - "PCIE_IMUX29_L_6", - "PCIE_IMUX29_L_7", - "PCIE_IMUX29_L_8", - "PCIE_IMUX29_L_9", - "PCIE_IMUX29_R_0", - "PCIE_IMUX29_R_1", - "PCIE_IMUX29_R_10", - "PCIE_IMUX29_R_11", - "PCIE_IMUX29_R_12", - "PCIE_IMUX29_R_13", - "PCIE_IMUX29_R_14", - "PCIE_IMUX29_R_15", - "PCIE_IMUX29_R_16", - "PCIE_IMUX29_R_17", - "PCIE_IMUX29_R_18", - "PCIE_IMUX29_R_19", - "PCIE_IMUX29_R_2", - "PCIE_IMUX29_R_3", - "PCIE_IMUX29_R_4", - "PCIE_IMUX29_R_5", - "PCIE_IMUX29_R_6", - "PCIE_IMUX29_R_7", - "PCIE_IMUX29_R_8", - "PCIE_IMUX29_R_9", - "PCIE_IMUX2_L_0", - "PCIE_IMUX2_L_1", - "PCIE_IMUX2_L_10", - "PCIE_IMUX2_L_11", - "PCIE_IMUX2_L_12", - "PCIE_IMUX2_L_13", - "PCIE_IMUX2_L_14", - "PCIE_IMUX2_L_15", - "PCIE_IMUX2_L_16", - "PCIE_IMUX2_L_17", - "PCIE_IMUX2_L_18", - "PCIE_IMUX2_L_19", - "PCIE_IMUX2_L_2", - "PCIE_IMUX2_L_3", - "PCIE_IMUX2_L_4", - "PCIE_IMUX2_L_5", - "PCIE_IMUX2_L_6", - "PCIE_IMUX2_L_7", - "PCIE_IMUX2_L_8", - "PCIE_IMUX2_L_9", - "PCIE_IMUX2_R_0", - "PCIE_IMUX2_R_1", - "PCIE_IMUX2_R_10", - "PCIE_IMUX2_R_11", - "PCIE_IMUX2_R_12", - "PCIE_IMUX2_R_13", - "PCIE_IMUX2_R_14", - "PCIE_IMUX2_R_15", - "PCIE_IMUX2_R_16", - "PCIE_IMUX2_R_17", - "PCIE_IMUX2_R_18", - "PCIE_IMUX2_R_19", - "PCIE_IMUX2_R_2", - "PCIE_IMUX2_R_3", - "PCIE_IMUX2_R_4", - "PCIE_IMUX2_R_5", - "PCIE_IMUX2_R_6", - "PCIE_IMUX2_R_7", - "PCIE_IMUX2_R_8", - "PCIE_IMUX2_R_9", - "PCIE_IMUX30_L_0", - "PCIE_IMUX30_L_1", - "PCIE_IMUX30_L_10", - "PCIE_IMUX30_L_11", - "PCIE_IMUX30_L_12", - "PCIE_IMUX30_L_13", - "PCIE_IMUX30_L_14", - "PCIE_IMUX30_L_15", - "PCIE_IMUX30_L_16", - "PCIE_IMUX30_L_17", - "PCIE_IMUX30_L_18", - "PCIE_IMUX30_L_19", - "PCIE_IMUX30_L_2", - "PCIE_IMUX30_L_3", - "PCIE_IMUX30_L_4", - "PCIE_IMUX30_L_5", - "PCIE_IMUX30_L_6", - "PCIE_IMUX30_L_7", - "PCIE_IMUX30_L_8", - "PCIE_IMUX30_L_9", - "PCIE_IMUX30_R_0", - "PCIE_IMUX30_R_1", - "PCIE_IMUX30_R_10", - "PCIE_IMUX30_R_11", - "PCIE_IMUX30_R_12", - "PCIE_IMUX30_R_13", - "PCIE_IMUX30_R_14", - "PCIE_IMUX30_R_15", - "PCIE_IMUX30_R_16", - "PCIE_IMUX30_R_17", - "PCIE_IMUX30_R_18", - "PCIE_IMUX30_R_19", - "PCIE_IMUX30_R_2", - "PCIE_IMUX30_R_3", - "PCIE_IMUX30_R_4", - "PCIE_IMUX30_R_5", - "PCIE_IMUX30_R_6", - "PCIE_IMUX30_R_7", - "PCIE_IMUX30_R_8", - "PCIE_IMUX30_R_9", - "PCIE_IMUX31_L_0", - "PCIE_IMUX31_L_1", - "PCIE_IMUX31_L_10", - "PCIE_IMUX31_L_11", - "PCIE_IMUX31_L_12", - "PCIE_IMUX31_L_13", - "PCIE_IMUX31_L_14", - "PCIE_IMUX31_L_15", - "PCIE_IMUX31_L_16", - "PCIE_IMUX31_L_17", - "PCIE_IMUX31_L_18", - "PCIE_IMUX31_L_19", - "PCIE_IMUX31_L_2", - "PCIE_IMUX31_L_3", - "PCIE_IMUX31_L_4", - "PCIE_IMUX31_L_5", - "PCIE_IMUX31_L_6", - "PCIE_IMUX31_L_7", - "PCIE_IMUX31_L_8", - "PCIE_IMUX31_L_9", - "PCIE_IMUX31_R_0", - "PCIE_IMUX31_R_1", - "PCIE_IMUX31_R_10", - "PCIE_IMUX31_R_11", - "PCIE_IMUX31_R_12", - "PCIE_IMUX31_R_13", - "PCIE_IMUX31_R_14", - "PCIE_IMUX31_R_15", - "PCIE_IMUX31_R_16", - "PCIE_IMUX31_R_17", - "PCIE_IMUX31_R_18", - "PCIE_IMUX31_R_19", - "PCIE_IMUX31_R_2", - "PCIE_IMUX31_R_3", - "PCIE_IMUX31_R_4", - "PCIE_IMUX31_R_5", - "PCIE_IMUX31_R_6", - "PCIE_IMUX31_R_7", - "PCIE_IMUX31_R_8", - "PCIE_IMUX31_R_9", - "PCIE_IMUX32_L_0", - "PCIE_IMUX32_L_1", - "PCIE_IMUX32_L_10", - "PCIE_IMUX32_L_11", - "PCIE_IMUX32_L_12", - "PCIE_IMUX32_L_13", - "PCIE_IMUX32_L_14", - "PCIE_IMUX32_L_15", - "PCIE_IMUX32_L_16", - "PCIE_IMUX32_L_17", - "PCIE_IMUX32_L_18", - "PCIE_IMUX32_L_19", - "PCIE_IMUX32_L_2", - "PCIE_IMUX32_L_3", - "PCIE_IMUX32_L_4", - "PCIE_IMUX32_L_5", - "PCIE_IMUX32_L_6", - "PCIE_IMUX32_L_7", - "PCIE_IMUX32_L_8", - "PCIE_IMUX32_L_9", - "PCIE_IMUX32_R_0", - "PCIE_IMUX32_R_1", - "PCIE_IMUX32_R_10", - "PCIE_IMUX32_R_11", - "PCIE_IMUX32_R_12", - "PCIE_IMUX32_R_13", - "PCIE_IMUX32_R_14", - "PCIE_IMUX32_R_15", - "PCIE_IMUX32_R_16", - "PCIE_IMUX32_R_17", - "PCIE_IMUX32_R_18", - "PCIE_IMUX32_R_19", - "PCIE_IMUX32_R_2", - "PCIE_IMUX32_R_3", - "PCIE_IMUX32_R_4", - "PCIE_IMUX32_R_5", - "PCIE_IMUX32_R_6", - "PCIE_IMUX32_R_7", - "PCIE_IMUX32_R_8", - "PCIE_IMUX32_R_9", - "PCIE_IMUX33_L_0", - "PCIE_IMUX33_L_1", - "PCIE_IMUX33_L_10", - "PCIE_IMUX33_L_11", - "PCIE_IMUX33_L_12", - "PCIE_IMUX33_L_13", - "PCIE_IMUX33_L_14", - "PCIE_IMUX33_L_15", - "PCIE_IMUX33_L_16", - "PCIE_IMUX33_L_17", - "PCIE_IMUX33_L_18", - "PCIE_IMUX33_L_19", - "PCIE_IMUX33_L_2", - "PCIE_IMUX33_L_3", - "PCIE_IMUX33_L_4", - "PCIE_IMUX33_L_5", - "PCIE_IMUX33_L_6", - "PCIE_IMUX33_L_7", - "PCIE_IMUX33_L_8", - "PCIE_IMUX33_L_9", - "PCIE_IMUX33_R_0", - "PCIE_IMUX33_R_1", - "PCIE_IMUX33_R_10", - "PCIE_IMUX33_R_11", - "PCIE_IMUX33_R_12", - "PCIE_IMUX33_R_13", - "PCIE_IMUX33_R_14", - "PCIE_IMUX33_R_15", - "PCIE_IMUX33_R_16", - "PCIE_IMUX33_R_17", - "PCIE_IMUX33_R_18", - "PCIE_IMUX33_R_19", - "PCIE_IMUX33_R_2", - "PCIE_IMUX33_R_3", - "PCIE_IMUX33_R_4", - "PCIE_IMUX33_R_5", - "PCIE_IMUX33_R_6", - "PCIE_IMUX33_R_7", - "PCIE_IMUX33_R_8", - "PCIE_IMUX33_R_9", - "PCIE_IMUX34_L_0", - "PCIE_IMUX34_L_1", - "PCIE_IMUX34_L_10", - "PCIE_IMUX34_L_11", - "PCIE_IMUX34_L_12", - "PCIE_IMUX34_L_13", - "PCIE_IMUX34_L_14", - "PCIE_IMUX34_L_15", - "PCIE_IMUX34_L_16", - "PCIE_IMUX34_L_17", - "PCIE_IMUX34_L_18", - "PCIE_IMUX34_L_19", - "PCIE_IMUX34_L_2", - "PCIE_IMUX34_L_3", - "PCIE_IMUX34_L_4", - "PCIE_IMUX34_L_5", - "PCIE_IMUX34_L_6", - "PCIE_IMUX34_L_7", - "PCIE_IMUX34_L_8", - "PCIE_IMUX34_L_9", - "PCIE_IMUX34_R_0", - "PCIE_IMUX34_R_1", - "PCIE_IMUX34_R_10", - "PCIE_IMUX34_R_11", - "PCIE_IMUX34_R_12", - "PCIE_IMUX34_R_13", - "PCIE_IMUX34_R_14", - "PCIE_IMUX34_R_15", - "PCIE_IMUX34_R_16", - "PCIE_IMUX34_R_17", - "PCIE_IMUX34_R_18", - "PCIE_IMUX34_R_19", - "PCIE_IMUX34_R_2", - "PCIE_IMUX34_R_3", - "PCIE_IMUX34_R_4", - "PCIE_IMUX34_R_5", - "PCIE_IMUX34_R_6", - "PCIE_IMUX34_R_7", - "PCIE_IMUX34_R_8", - "PCIE_IMUX34_R_9", - "PCIE_IMUX35_L_0", - "PCIE_IMUX35_L_1", - "PCIE_IMUX35_L_10", - "PCIE_IMUX35_L_11", - "PCIE_IMUX35_L_12", - "PCIE_IMUX35_L_13", - "PCIE_IMUX35_L_14", - "PCIE_IMUX35_L_15", - "PCIE_IMUX35_L_16", - "PCIE_IMUX35_L_17", - "PCIE_IMUX35_L_18", - "PCIE_IMUX35_L_19", - "PCIE_IMUX35_L_2", - "PCIE_IMUX35_L_3", - "PCIE_IMUX35_L_4", - "PCIE_IMUX35_L_5", - "PCIE_IMUX35_L_6", - "PCIE_IMUX35_L_7", - "PCIE_IMUX35_L_8", - "PCIE_IMUX35_L_9", - "PCIE_IMUX35_R_0", - "PCIE_IMUX35_R_1", - "PCIE_IMUX35_R_10", - "PCIE_IMUX35_R_11", - "PCIE_IMUX35_R_12", - "PCIE_IMUX35_R_13", - "PCIE_IMUX35_R_14", - "PCIE_IMUX35_R_15", - "PCIE_IMUX35_R_16", - "PCIE_IMUX35_R_17", - "PCIE_IMUX35_R_18", - "PCIE_IMUX35_R_19", - "PCIE_IMUX35_R_2", - "PCIE_IMUX35_R_3", - "PCIE_IMUX35_R_4", - "PCIE_IMUX35_R_5", - "PCIE_IMUX35_R_6", - "PCIE_IMUX35_R_7", - "PCIE_IMUX35_R_8", - "PCIE_IMUX35_R_9", - "PCIE_IMUX36_L_0", - "PCIE_IMUX36_L_1", - "PCIE_IMUX36_L_10", - "PCIE_IMUX36_L_11", - "PCIE_IMUX36_L_12", - "PCIE_IMUX36_L_13", - "PCIE_IMUX36_L_14", - "PCIE_IMUX36_L_15", - "PCIE_IMUX36_L_16", - "PCIE_IMUX36_L_17", - "PCIE_IMUX36_L_18", - "PCIE_IMUX36_L_19", - "PCIE_IMUX36_L_2", - "PCIE_IMUX36_L_3", - "PCIE_IMUX36_L_4", - "PCIE_IMUX36_L_5", - "PCIE_IMUX36_L_6", - "PCIE_IMUX36_L_7", - "PCIE_IMUX36_L_8", - "PCIE_IMUX36_L_9", - "PCIE_IMUX36_R_0", - "PCIE_IMUX36_R_1", - "PCIE_IMUX36_R_10", - "PCIE_IMUX36_R_11", - "PCIE_IMUX36_R_12", - "PCIE_IMUX36_R_13", - "PCIE_IMUX36_R_14", - "PCIE_IMUX36_R_15", - "PCIE_IMUX36_R_16", - "PCIE_IMUX36_R_17", - "PCIE_IMUX36_R_18", - "PCIE_IMUX36_R_19", - "PCIE_IMUX36_R_2", - "PCIE_IMUX36_R_3", - "PCIE_IMUX36_R_4", - "PCIE_IMUX36_R_5", - "PCIE_IMUX36_R_6", - "PCIE_IMUX36_R_7", - "PCIE_IMUX36_R_8", - "PCIE_IMUX36_R_9", - "PCIE_IMUX37_L_0", - "PCIE_IMUX37_L_1", - "PCIE_IMUX37_L_10", - "PCIE_IMUX37_L_11", - "PCIE_IMUX37_L_12", - "PCIE_IMUX37_L_13", - "PCIE_IMUX37_L_14", - "PCIE_IMUX37_L_15", - "PCIE_IMUX37_L_16", - "PCIE_IMUX37_L_17", - "PCIE_IMUX37_L_18", - "PCIE_IMUX37_L_19", - "PCIE_IMUX37_L_2", - "PCIE_IMUX37_L_3", - "PCIE_IMUX37_L_4", - "PCIE_IMUX37_L_5", - "PCIE_IMUX37_L_6", - "PCIE_IMUX37_L_7", - "PCIE_IMUX37_L_8", - "PCIE_IMUX37_L_9", - "PCIE_IMUX37_R_0", - "PCIE_IMUX37_R_1", - "PCIE_IMUX37_R_10", - "PCIE_IMUX37_R_11", - "PCIE_IMUX37_R_12", - "PCIE_IMUX37_R_13", - "PCIE_IMUX37_R_14", - "PCIE_IMUX37_R_15", - "PCIE_IMUX37_R_16", - "PCIE_IMUX37_R_17", - "PCIE_IMUX37_R_18", - "PCIE_IMUX37_R_19", - "PCIE_IMUX37_R_2", - "PCIE_IMUX37_R_3", - "PCIE_IMUX37_R_4", - "PCIE_IMUX37_R_5", - "PCIE_IMUX37_R_6", - "PCIE_IMUX37_R_7", - "PCIE_IMUX37_R_8", - "PCIE_IMUX37_R_9", - "PCIE_IMUX38_L_0", - "PCIE_IMUX38_L_1", - "PCIE_IMUX38_L_10", - "PCIE_IMUX38_L_11", - "PCIE_IMUX38_L_12", - "PCIE_IMUX38_L_13", - "PCIE_IMUX38_L_14", - "PCIE_IMUX38_L_15", - "PCIE_IMUX38_L_16", - "PCIE_IMUX38_L_17", - "PCIE_IMUX38_L_18", - "PCIE_IMUX38_L_19", - "PCIE_IMUX38_L_2", - "PCIE_IMUX38_L_3", - "PCIE_IMUX38_L_4", - "PCIE_IMUX38_L_5", - "PCIE_IMUX38_L_6", - "PCIE_IMUX38_L_7", - "PCIE_IMUX38_L_8", - "PCIE_IMUX38_L_9", - "PCIE_IMUX38_R_0", - "PCIE_IMUX38_R_1", - "PCIE_IMUX38_R_10", - "PCIE_IMUX38_R_11", - "PCIE_IMUX38_R_12", - "PCIE_IMUX38_R_13", - "PCIE_IMUX38_R_14", - "PCIE_IMUX38_R_15", - "PCIE_IMUX38_R_16", - "PCIE_IMUX38_R_17", - "PCIE_IMUX38_R_18", - "PCIE_IMUX38_R_19", - "PCIE_IMUX38_R_2", - "PCIE_IMUX38_R_3", - "PCIE_IMUX38_R_4", - "PCIE_IMUX38_R_5", - "PCIE_IMUX38_R_6", - "PCIE_IMUX38_R_7", - "PCIE_IMUX38_R_8", - "PCIE_IMUX38_R_9", - "PCIE_IMUX39_L_0", - "PCIE_IMUX39_L_1", - "PCIE_IMUX39_L_10", - "PCIE_IMUX39_L_11", - "PCIE_IMUX39_L_12", - "PCIE_IMUX39_L_13", - "PCIE_IMUX39_L_14", - "PCIE_IMUX39_L_15", - "PCIE_IMUX39_L_16", - "PCIE_IMUX39_L_17", - "PCIE_IMUX39_L_18", - "PCIE_IMUX39_L_19", - "PCIE_IMUX39_L_2", - "PCIE_IMUX39_L_3", - "PCIE_IMUX39_L_4", - "PCIE_IMUX39_L_5", - "PCIE_IMUX39_L_6", - "PCIE_IMUX39_L_7", - "PCIE_IMUX39_L_8", - "PCIE_IMUX39_L_9", - "PCIE_IMUX39_R_0", - "PCIE_IMUX39_R_1", - "PCIE_IMUX39_R_10", - "PCIE_IMUX39_R_11", - "PCIE_IMUX39_R_12", - "PCIE_IMUX39_R_13", - "PCIE_IMUX39_R_14", - "PCIE_IMUX39_R_15", - "PCIE_IMUX39_R_16", - "PCIE_IMUX39_R_17", - "PCIE_IMUX39_R_18", - "PCIE_IMUX39_R_19", - "PCIE_IMUX39_R_2", - "PCIE_IMUX39_R_3", - "PCIE_IMUX39_R_4", - "PCIE_IMUX39_R_5", - "PCIE_IMUX39_R_6", - "PCIE_IMUX39_R_7", - "PCIE_IMUX39_R_8", - "PCIE_IMUX39_R_9", - "PCIE_IMUX3_L_0", - "PCIE_IMUX3_L_1", - "PCIE_IMUX3_L_10", - "PCIE_IMUX3_L_11", - "PCIE_IMUX3_L_12", - "PCIE_IMUX3_L_13", - "PCIE_IMUX3_L_14", - "PCIE_IMUX3_L_15", - "PCIE_IMUX3_L_16", - "PCIE_IMUX3_L_17", - "PCIE_IMUX3_L_18", - "PCIE_IMUX3_L_19", - "PCIE_IMUX3_L_2", - "PCIE_IMUX3_L_3", - "PCIE_IMUX3_L_4", - "PCIE_IMUX3_L_5", - "PCIE_IMUX3_L_6", - "PCIE_IMUX3_L_7", - "PCIE_IMUX3_L_8", - "PCIE_IMUX3_L_9", - "PCIE_IMUX3_R_0", - "PCIE_IMUX3_R_1", - "PCIE_IMUX3_R_10", - "PCIE_IMUX3_R_11", - "PCIE_IMUX3_R_12", - "PCIE_IMUX3_R_13", - "PCIE_IMUX3_R_14", - "PCIE_IMUX3_R_15", - "PCIE_IMUX3_R_16", - "PCIE_IMUX3_R_17", - "PCIE_IMUX3_R_18", - "PCIE_IMUX3_R_19", - "PCIE_IMUX3_R_2", - "PCIE_IMUX3_R_3", - "PCIE_IMUX3_R_4", - "PCIE_IMUX3_R_5", - "PCIE_IMUX3_R_6", - "PCIE_IMUX3_R_7", - "PCIE_IMUX3_R_8", - "PCIE_IMUX3_R_9", - "PCIE_IMUX40_L_0", - "PCIE_IMUX40_L_1", - "PCIE_IMUX40_L_10", - "PCIE_IMUX40_L_11", - "PCIE_IMUX40_L_12", - "PCIE_IMUX40_L_13", - "PCIE_IMUX40_L_14", - "PCIE_IMUX40_L_15", - "PCIE_IMUX40_L_16", - "PCIE_IMUX40_L_17", - "PCIE_IMUX40_L_18", - "PCIE_IMUX40_L_19", - "PCIE_IMUX40_L_2", - "PCIE_IMUX40_L_3", - "PCIE_IMUX40_L_4", - "PCIE_IMUX40_L_5", - "PCIE_IMUX40_L_6", - "PCIE_IMUX40_L_7", - "PCIE_IMUX40_L_8", - "PCIE_IMUX40_L_9", - "PCIE_IMUX40_R_0", - "PCIE_IMUX40_R_1", - "PCIE_IMUX40_R_10", - "PCIE_IMUX40_R_11", - "PCIE_IMUX40_R_12", - "PCIE_IMUX40_R_13", - "PCIE_IMUX40_R_14", - "PCIE_IMUX40_R_15", - "PCIE_IMUX40_R_16", - "PCIE_IMUX40_R_17", - "PCIE_IMUX40_R_18", - "PCIE_IMUX40_R_19", - "PCIE_IMUX40_R_2", - "PCIE_IMUX40_R_3", - "PCIE_IMUX40_R_4", - "PCIE_IMUX40_R_5", - "PCIE_IMUX40_R_6", - "PCIE_IMUX40_R_7", - "PCIE_IMUX40_R_8", - "PCIE_IMUX40_R_9", - "PCIE_IMUX41_L_0", - "PCIE_IMUX41_L_1", - "PCIE_IMUX41_L_10", - "PCIE_IMUX41_L_11", - "PCIE_IMUX41_L_12", - "PCIE_IMUX41_L_13", - "PCIE_IMUX41_L_14", - "PCIE_IMUX41_L_15", - "PCIE_IMUX41_L_16", - "PCIE_IMUX41_L_17", - "PCIE_IMUX41_L_18", - "PCIE_IMUX41_L_19", - "PCIE_IMUX41_L_2", - "PCIE_IMUX41_L_3", - "PCIE_IMUX41_L_4", - "PCIE_IMUX41_L_5", - "PCIE_IMUX41_L_6", - "PCIE_IMUX41_L_7", - "PCIE_IMUX41_L_8", - "PCIE_IMUX41_L_9", - "PCIE_IMUX41_R_0", - "PCIE_IMUX41_R_1", - "PCIE_IMUX41_R_10", - "PCIE_IMUX41_R_11", - "PCIE_IMUX41_R_12", - "PCIE_IMUX41_R_13", - "PCIE_IMUX41_R_14", - "PCIE_IMUX41_R_15", - "PCIE_IMUX41_R_16", - "PCIE_IMUX41_R_17", - "PCIE_IMUX41_R_18", - "PCIE_IMUX41_R_19", - "PCIE_IMUX41_R_2", - "PCIE_IMUX41_R_3", - "PCIE_IMUX41_R_4", - "PCIE_IMUX41_R_5", - "PCIE_IMUX41_R_6", - "PCIE_IMUX41_R_7", - "PCIE_IMUX41_R_8", - "PCIE_IMUX41_R_9", - "PCIE_IMUX42_L_0", - "PCIE_IMUX42_L_1", - "PCIE_IMUX42_L_10", - "PCIE_IMUX42_L_11", - "PCIE_IMUX42_L_12", - "PCIE_IMUX42_L_13", - "PCIE_IMUX42_L_14", - "PCIE_IMUX42_L_15", - "PCIE_IMUX42_L_16", - "PCIE_IMUX42_L_17", - "PCIE_IMUX42_L_18", - "PCIE_IMUX42_L_19", - "PCIE_IMUX42_L_2", - "PCIE_IMUX42_L_3", - "PCIE_IMUX42_L_4", - "PCIE_IMUX42_L_5", - "PCIE_IMUX42_L_6", - "PCIE_IMUX42_L_7", - "PCIE_IMUX42_L_8", - "PCIE_IMUX42_L_9", - "PCIE_IMUX42_R_0", - "PCIE_IMUX42_R_1", - "PCIE_IMUX42_R_10", - "PCIE_IMUX42_R_11", - "PCIE_IMUX42_R_12", - "PCIE_IMUX42_R_13", - "PCIE_IMUX42_R_14", - "PCIE_IMUX42_R_15", - "PCIE_IMUX42_R_16", - "PCIE_IMUX42_R_17", - "PCIE_IMUX42_R_18", - "PCIE_IMUX42_R_19", - "PCIE_IMUX42_R_2", - "PCIE_IMUX42_R_3", - "PCIE_IMUX42_R_4", - "PCIE_IMUX42_R_5", - "PCIE_IMUX42_R_6", - "PCIE_IMUX42_R_7", - "PCIE_IMUX42_R_8", - "PCIE_IMUX42_R_9", - "PCIE_IMUX43_L_0", - "PCIE_IMUX43_L_1", - "PCIE_IMUX43_L_10", - "PCIE_IMUX43_L_11", - "PCIE_IMUX43_L_12", - "PCIE_IMUX43_L_13", - "PCIE_IMUX43_L_14", - "PCIE_IMUX43_L_15", - "PCIE_IMUX43_L_16", - "PCIE_IMUX43_L_17", - "PCIE_IMUX43_L_18", - "PCIE_IMUX43_L_19", - "PCIE_IMUX43_L_2", - "PCIE_IMUX43_L_3", - "PCIE_IMUX43_L_4", - "PCIE_IMUX43_L_5", - "PCIE_IMUX43_L_6", - "PCIE_IMUX43_L_7", - "PCIE_IMUX43_L_8", - "PCIE_IMUX43_L_9", - "PCIE_IMUX43_R_0", - "PCIE_IMUX43_R_1", - "PCIE_IMUX43_R_10", - "PCIE_IMUX43_R_11", - "PCIE_IMUX43_R_12", - "PCIE_IMUX43_R_13", - "PCIE_IMUX43_R_14", - "PCIE_IMUX43_R_15", - "PCIE_IMUX43_R_16", - "PCIE_IMUX43_R_17", - "PCIE_IMUX43_R_18", - "PCIE_IMUX43_R_19", - "PCIE_IMUX43_R_2", - "PCIE_IMUX43_R_3", - "PCIE_IMUX43_R_4", - "PCIE_IMUX43_R_5", - "PCIE_IMUX43_R_6", - "PCIE_IMUX43_R_7", - "PCIE_IMUX43_R_8", - "PCIE_IMUX43_R_9", - "PCIE_IMUX44_L_0", - "PCIE_IMUX44_L_1", - "PCIE_IMUX44_L_10", - "PCIE_IMUX44_L_11", - "PCIE_IMUX44_L_12", - "PCIE_IMUX44_L_13", - "PCIE_IMUX44_L_14", - "PCIE_IMUX44_L_15", - "PCIE_IMUX44_L_16", - "PCIE_IMUX44_L_17", - "PCIE_IMUX44_L_18", - "PCIE_IMUX44_L_19", - "PCIE_IMUX44_L_2", - "PCIE_IMUX44_L_3", - "PCIE_IMUX44_L_4", - "PCIE_IMUX44_L_5", - "PCIE_IMUX44_L_6", - "PCIE_IMUX44_L_7", - "PCIE_IMUX44_L_8", - "PCIE_IMUX44_L_9", - "PCIE_IMUX44_R_0", - "PCIE_IMUX44_R_1", - "PCIE_IMUX44_R_10", - "PCIE_IMUX44_R_11", - "PCIE_IMUX44_R_12", - "PCIE_IMUX44_R_13", - "PCIE_IMUX44_R_14", - "PCIE_IMUX44_R_15", - "PCIE_IMUX44_R_16", - "PCIE_IMUX44_R_17", - "PCIE_IMUX44_R_18", - "PCIE_IMUX44_R_19", - "PCIE_IMUX44_R_2", - "PCIE_IMUX44_R_3", - "PCIE_IMUX44_R_4", - "PCIE_IMUX44_R_5", - "PCIE_IMUX44_R_6", - "PCIE_IMUX44_R_7", - "PCIE_IMUX44_R_8", - "PCIE_IMUX44_R_9", - "PCIE_IMUX45_L_0", - "PCIE_IMUX45_L_1", - "PCIE_IMUX45_L_10", - "PCIE_IMUX45_L_11", - "PCIE_IMUX45_L_12", - "PCIE_IMUX45_L_13", - "PCIE_IMUX45_L_14", - "PCIE_IMUX45_L_15", - "PCIE_IMUX45_L_16", - "PCIE_IMUX45_L_17", - "PCIE_IMUX45_L_18", - "PCIE_IMUX45_L_19", - "PCIE_IMUX45_L_2", - "PCIE_IMUX45_L_3", - "PCIE_IMUX45_L_4", - "PCIE_IMUX45_L_5", - "PCIE_IMUX45_L_6", - "PCIE_IMUX45_L_7", - "PCIE_IMUX45_L_8", - "PCIE_IMUX45_L_9", - "PCIE_IMUX45_R_0", - "PCIE_IMUX45_R_1", - "PCIE_IMUX45_R_10", - "PCIE_IMUX45_R_11", - "PCIE_IMUX45_R_12", - "PCIE_IMUX45_R_13", - "PCIE_IMUX45_R_14", - "PCIE_IMUX45_R_15", - "PCIE_IMUX45_R_16", - "PCIE_IMUX45_R_17", - "PCIE_IMUX45_R_18", - "PCIE_IMUX45_R_19", - "PCIE_IMUX45_R_2", - "PCIE_IMUX45_R_3", - "PCIE_IMUX45_R_4", - "PCIE_IMUX45_R_5", - "PCIE_IMUX45_R_6", - "PCIE_IMUX45_R_7", - "PCIE_IMUX45_R_8", - "PCIE_IMUX45_R_9", - "PCIE_IMUX46_L_0", - "PCIE_IMUX46_L_1", - "PCIE_IMUX46_L_10", - "PCIE_IMUX46_L_11", - "PCIE_IMUX46_L_12", - "PCIE_IMUX46_L_13", - "PCIE_IMUX46_L_14", - "PCIE_IMUX46_L_15", - "PCIE_IMUX46_L_16", - "PCIE_IMUX46_L_17", - "PCIE_IMUX46_L_18", - "PCIE_IMUX46_L_19", - "PCIE_IMUX46_L_2", - "PCIE_IMUX46_L_3", - "PCIE_IMUX46_L_4", - "PCIE_IMUX46_L_5", - "PCIE_IMUX46_L_6", - "PCIE_IMUX46_L_7", - "PCIE_IMUX46_L_8", - "PCIE_IMUX46_L_9", - "PCIE_IMUX46_R_0", - "PCIE_IMUX46_R_1", - "PCIE_IMUX46_R_10", - "PCIE_IMUX46_R_11", - "PCIE_IMUX46_R_12", - "PCIE_IMUX46_R_13", - "PCIE_IMUX46_R_14", - "PCIE_IMUX46_R_15", - "PCIE_IMUX46_R_16", - "PCIE_IMUX46_R_17", - "PCIE_IMUX46_R_18", - "PCIE_IMUX46_R_19", - "PCIE_IMUX46_R_2", - "PCIE_IMUX46_R_3", - "PCIE_IMUX46_R_4", - "PCIE_IMUX46_R_5", - "PCIE_IMUX46_R_6", - "PCIE_IMUX46_R_7", - "PCIE_IMUX46_R_8", - "PCIE_IMUX46_R_9", - "PCIE_IMUX47_L_0", - "PCIE_IMUX47_L_1", - "PCIE_IMUX47_L_10", - "PCIE_IMUX47_L_11", - "PCIE_IMUX47_L_12", - "PCIE_IMUX47_L_13", - "PCIE_IMUX47_L_14", - "PCIE_IMUX47_L_15", - "PCIE_IMUX47_L_16", - "PCIE_IMUX47_L_17", - "PCIE_IMUX47_L_18", - "PCIE_IMUX47_L_19", - "PCIE_IMUX47_L_2", - "PCIE_IMUX47_L_3", - "PCIE_IMUX47_L_4", - "PCIE_IMUX47_L_5", - "PCIE_IMUX47_L_6", - "PCIE_IMUX47_L_7", - "PCIE_IMUX47_L_8", - "PCIE_IMUX47_L_9", - "PCIE_IMUX47_R_0", - "PCIE_IMUX47_R_1", - "PCIE_IMUX47_R_10", - "PCIE_IMUX47_R_11", - "PCIE_IMUX47_R_12", - "PCIE_IMUX47_R_13", - "PCIE_IMUX47_R_14", - "PCIE_IMUX47_R_15", - "PCIE_IMUX47_R_16", - "PCIE_IMUX47_R_17", - "PCIE_IMUX47_R_18", - "PCIE_IMUX47_R_19", - "PCIE_IMUX47_R_2", - "PCIE_IMUX47_R_3", - "PCIE_IMUX47_R_4", - "PCIE_IMUX47_R_5", - "PCIE_IMUX47_R_6", - "PCIE_IMUX47_R_7", - "PCIE_IMUX47_R_8", - "PCIE_IMUX47_R_9", - "PCIE_IMUX4_L_0", - "PCIE_IMUX4_L_1", - "PCIE_IMUX4_L_10", - "PCIE_IMUX4_L_11", - "PCIE_IMUX4_L_12", - "PCIE_IMUX4_L_13", - "PCIE_IMUX4_L_14", - "PCIE_IMUX4_L_15", - "PCIE_IMUX4_L_16", - "PCIE_IMUX4_L_17", - "PCIE_IMUX4_L_18", - "PCIE_IMUX4_L_19", - "PCIE_IMUX4_L_2", - "PCIE_IMUX4_L_3", - "PCIE_IMUX4_L_4", - "PCIE_IMUX4_L_5", - "PCIE_IMUX4_L_6", - "PCIE_IMUX4_L_7", - "PCIE_IMUX4_L_8", - "PCIE_IMUX4_L_9", - "PCIE_IMUX4_R_0", - "PCIE_IMUX4_R_1", - "PCIE_IMUX4_R_10", - "PCIE_IMUX4_R_11", - "PCIE_IMUX4_R_12", - "PCIE_IMUX4_R_13", - "PCIE_IMUX4_R_14", - "PCIE_IMUX4_R_15", - "PCIE_IMUX4_R_16", - "PCIE_IMUX4_R_17", - "PCIE_IMUX4_R_18", - "PCIE_IMUX4_R_19", - "PCIE_IMUX4_R_2", - "PCIE_IMUX4_R_3", - "PCIE_IMUX4_R_4", - "PCIE_IMUX4_R_5", - "PCIE_IMUX4_R_6", - "PCIE_IMUX4_R_7", - "PCIE_IMUX4_R_8", - "PCIE_IMUX4_R_9", - "PCIE_IMUX5_L_0", - "PCIE_IMUX5_L_1", - "PCIE_IMUX5_L_10", - "PCIE_IMUX5_L_11", - "PCIE_IMUX5_L_12", - "PCIE_IMUX5_L_13", - "PCIE_IMUX5_L_14", - "PCIE_IMUX5_L_15", - "PCIE_IMUX5_L_16", - "PCIE_IMUX5_L_17", - "PCIE_IMUX5_L_18", - "PCIE_IMUX5_L_19", - "PCIE_IMUX5_L_2", - "PCIE_IMUX5_L_3", - "PCIE_IMUX5_L_4", - "PCIE_IMUX5_L_5", - "PCIE_IMUX5_L_6", - "PCIE_IMUX5_L_7", - "PCIE_IMUX5_L_8", - "PCIE_IMUX5_L_9", - "PCIE_IMUX5_R_0", - "PCIE_IMUX5_R_1", - "PCIE_IMUX5_R_10", - "PCIE_IMUX5_R_11", - "PCIE_IMUX5_R_12", - "PCIE_IMUX5_R_13", - "PCIE_IMUX5_R_14", - "PCIE_IMUX5_R_15", - "PCIE_IMUX5_R_16", - "PCIE_IMUX5_R_17", - "PCIE_IMUX5_R_18", - "PCIE_IMUX5_R_19", - "PCIE_IMUX5_R_2", - "PCIE_IMUX5_R_3", - "PCIE_IMUX5_R_4", - "PCIE_IMUX5_R_5", - "PCIE_IMUX5_R_6", - "PCIE_IMUX5_R_7", - "PCIE_IMUX5_R_8", - "PCIE_IMUX5_R_9", - "PCIE_IMUX6_L_0", - "PCIE_IMUX6_L_1", - "PCIE_IMUX6_L_10", - "PCIE_IMUX6_L_11", - "PCIE_IMUX6_L_12", - "PCIE_IMUX6_L_13", - "PCIE_IMUX6_L_14", - "PCIE_IMUX6_L_15", - "PCIE_IMUX6_L_16", - "PCIE_IMUX6_L_17", - "PCIE_IMUX6_L_18", - "PCIE_IMUX6_L_19", - "PCIE_IMUX6_L_2", - "PCIE_IMUX6_L_3", - "PCIE_IMUX6_L_4", - "PCIE_IMUX6_L_5", - "PCIE_IMUX6_L_6", - "PCIE_IMUX6_L_7", - "PCIE_IMUX6_L_8", - "PCIE_IMUX6_L_9", - "PCIE_IMUX6_R_0", - "PCIE_IMUX6_R_1", - "PCIE_IMUX6_R_10", - "PCIE_IMUX6_R_11", - "PCIE_IMUX6_R_12", - "PCIE_IMUX6_R_13", - "PCIE_IMUX6_R_14", - "PCIE_IMUX6_R_15", - "PCIE_IMUX6_R_16", - "PCIE_IMUX6_R_17", - "PCIE_IMUX6_R_18", - "PCIE_IMUX6_R_19", - "PCIE_IMUX6_R_2", - "PCIE_IMUX6_R_3", - "PCIE_IMUX6_R_4", - "PCIE_IMUX6_R_5", - "PCIE_IMUX6_R_6", - "PCIE_IMUX6_R_7", - "PCIE_IMUX6_R_8", - "PCIE_IMUX6_R_9", - "PCIE_IMUX7_L_0", - "PCIE_IMUX7_L_1", - "PCIE_IMUX7_L_10", - "PCIE_IMUX7_L_11", - "PCIE_IMUX7_L_12", - "PCIE_IMUX7_L_13", - "PCIE_IMUX7_L_14", - "PCIE_IMUX7_L_15", - "PCIE_IMUX7_L_16", - "PCIE_IMUX7_L_17", - "PCIE_IMUX7_L_18", - "PCIE_IMUX7_L_19", - "PCIE_IMUX7_L_2", - "PCIE_IMUX7_L_3", - "PCIE_IMUX7_L_4", - "PCIE_IMUX7_L_5", - "PCIE_IMUX7_L_6", - "PCIE_IMUX7_L_7", - "PCIE_IMUX7_L_8", - "PCIE_IMUX7_L_9", - "PCIE_IMUX7_R_0", - "PCIE_IMUX7_R_1", - "PCIE_IMUX7_R_10", - "PCIE_IMUX7_R_11", - "PCIE_IMUX7_R_12", - "PCIE_IMUX7_R_13", - "PCIE_IMUX7_R_14", - "PCIE_IMUX7_R_15", - "PCIE_IMUX7_R_16", - "PCIE_IMUX7_R_17", - "PCIE_IMUX7_R_18", - "PCIE_IMUX7_R_19", - "PCIE_IMUX7_R_2", - "PCIE_IMUX7_R_3", - "PCIE_IMUX7_R_4", - "PCIE_IMUX7_R_5", - "PCIE_IMUX7_R_6", - "PCIE_IMUX7_R_7", - "PCIE_IMUX7_R_8", - "PCIE_IMUX7_R_9", - "PCIE_IMUX8_L_0", - "PCIE_IMUX8_L_1", - "PCIE_IMUX8_L_10", - "PCIE_IMUX8_L_11", - "PCIE_IMUX8_L_12", - "PCIE_IMUX8_L_13", - "PCIE_IMUX8_L_14", - "PCIE_IMUX8_L_15", - "PCIE_IMUX8_L_16", - "PCIE_IMUX8_L_17", - "PCIE_IMUX8_L_18", - "PCIE_IMUX8_L_19", - "PCIE_IMUX8_L_2", - "PCIE_IMUX8_L_3", - "PCIE_IMUX8_L_4", - "PCIE_IMUX8_L_5", - "PCIE_IMUX8_L_6", - "PCIE_IMUX8_L_7", - "PCIE_IMUX8_L_8", - "PCIE_IMUX8_L_9", - "PCIE_IMUX8_R_0", - "PCIE_IMUX8_R_1", - "PCIE_IMUX8_R_10", - "PCIE_IMUX8_R_11", - "PCIE_IMUX8_R_12", - "PCIE_IMUX8_R_13", - "PCIE_IMUX8_R_14", - "PCIE_IMUX8_R_15", - "PCIE_IMUX8_R_16", - "PCIE_IMUX8_R_17", - "PCIE_IMUX8_R_18", - "PCIE_IMUX8_R_19", - "PCIE_IMUX8_R_2", - "PCIE_IMUX8_R_3", - "PCIE_IMUX8_R_4", - "PCIE_IMUX8_R_5", - "PCIE_IMUX8_R_6", - "PCIE_IMUX8_R_7", - "PCIE_IMUX8_R_8", - "PCIE_IMUX8_R_9", - "PCIE_IMUX9_L_0", - "PCIE_IMUX9_L_1", - "PCIE_IMUX9_L_10", - "PCIE_IMUX9_L_11", - "PCIE_IMUX9_L_12", - "PCIE_IMUX9_L_13", - "PCIE_IMUX9_L_14", - "PCIE_IMUX9_L_15", - "PCIE_IMUX9_L_16", - "PCIE_IMUX9_L_17", - "PCIE_IMUX9_L_18", - "PCIE_IMUX9_L_19", - "PCIE_IMUX9_L_2", - "PCIE_IMUX9_L_3", - "PCIE_IMUX9_L_4", - "PCIE_IMUX9_L_5", - "PCIE_IMUX9_L_6", - "PCIE_IMUX9_L_7", - "PCIE_IMUX9_L_8", - "PCIE_IMUX9_L_9", - "PCIE_IMUX9_R_0", - "PCIE_IMUX9_R_1", - "PCIE_IMUX9_R_10", - "PCIE_IMUX9_R_11", - "PCIE_IMUX9_R_12", - "PCIE_IMUX9_R_13", - "PCIE_IMUX9_R_14", - "PCIE_IMUX9_R_15", - "PCIE_IMUX9_R_16", - "PCIE_IMUX9_R_17", - "PCIE_IMUX9_R_18", - "PCIE_IMUX9_R_19", - "PCIE_IMUX9_R_2", - "PCIE_IMUX9_R_3", - "PCIE_IMUX9_R_4", - "PCIE_IMUX9_R_5", - "PCIE_IMUX9_R_6", - "PCIE_IMUX9_R_7", - "PCIE_IMUX9_R_8", - "PCIE_IMUX9_R_9", - "PCIE_LH10_0", - "PCIE_LH10_1", - "PCIE_LH10_10", - "PCIE_LH10_11", - "PCIE_LH10_12", - "PCIE_LH10_13", - "PCIE_LH10_14", - "PCIE_LH10_15", - "PCIE_LH10_16", - "PCIE_LH10_17", - "PCIE_LH10_18", - "PCIE_LH10_19", - "PCIE_LH10_2", - "PCIE_LH10_3", - "PCIE_LH10_4", - "PCIE_LH10_5", - "PCIE_LH10_6", - "PCIE_LH10_7", - "PCIE_LH10_8", - "PCIE_LH10_9", - "PCIE_LH11_0", - "PCIE_LH11_1", - "PCIE_LH11_10", - "PCIE_LH11_11", - "PCIE_LH11_12", - "PCIE_LH11_13", - "PCIE_LH11_14", - "PCIE_LH11_15", - "PCIE_LH11_16", - "PCIE_LH11_17", - "PCIE_LH11_18", - "PCIE_LH11_19", - "PCIE_LH11_2", - "PCIE_LH11_3", - "PCIE_LH11_4", - "PCIE_LH11_5", - "PCIE_LH11_6", - "PCIE_LH11_7", - "PCIE_LH11_8", - "PCIE_LH11_9", - "PCIE_LH12_0", - "PCIE_LH12_1", - "PCIE_LH12_10", - "PCIE_LH12_11", - "PCIE_LH12_12", - "PCIE_LH12_13", - "PCIE_LH12_14", - "PCIE_LH12_15", - "PCIE_LH12_16", - "PCIE_LH12_17", - "PCIE_LH12_18", - "PCIE_LH12_19", - "PCIE_LH12_2", - "PCIE_LH12_3", - "PCIE_LH12_4", - "PCIE_LH12_5", - "PCIE_LH12_6", - "PCIE_LH12_7", - "PCIE_LH12_8", - "PCIE_LH12_9", - "PCIE_LH1_0", - "PCIE_LH1_1", - "PCIE_LH1_10", - "PCIE_LH1_11", - "PCIE_LH1_12", - "PCIE_LH1_13", - "PCIE_LH1_14", - "PCIE_LH1_15", - "PCIE_LH1_16", - "PCIE_LH1_17", - "PCIE_LH1_18", - "PCIE_LH1_19", - "PCIE_LH1_2", - "PCIE_LH1_3", - "PCIE_LH1_4", - "PCIE_LH1_5", - "PCIE_LH1_6", - "PCIE_LH1_7", - "PCIE_LH1_8", - "PCIE_LH1_9", - "PCIE_LH2_0", - "PCIE_LH2_1", - "PCIE_LH2_10", - "PCIE_LH2_11", - "PCIE_LH2_12", - "PCIE_LH2_13", - "PCIE_LH2_14", - "PCIE_LH2_15", - "PCIE_LH2_16", - "PCIE_LH2_17", - "PCIE_LH2_18", - "PCIE_LH2_19", - "PCIE_LH2_2", - "PCIE_LH2_3", - "PCIE_LH2_4", - "PCIE_LH2_5", - "PCIE_LH2_6", - "PCIE_LH2_7", - "PCIE_LH2_8", - "PCIE_LH2_9", - "PCIE_LH3_0", - "PCIE_LH3_1", - "PCIE_LH3_10", - "PCIE_LH3_11", - "PCIE_LH3_12", - "PCIE_LH3_13", - "PCIE_LH3_14", - "PCIE_LH3_15", - "PCIE_LH3_16", - "PCIE_LH3_17", - "PCIE_LH3_18", - "PCIE_LH3_19", - "PCIE_LH3_2", - "PCIE_LH3_3", - "PCIE_LH3_4", - "PCIE_LH3_5", - "PCIE_LH3_6", - "PCIE_LH3_7", - "PCIE_LH3_8", - "PCIE_LH3_9", - "PCIE_LH4_0", - "PCIE_LH4_1", - "PCIE_LH4_10", - "PCIE_LH4_11", - "PCIE_LH4_12", - "PCIE_LH4_13", - "PCIE_LH4_14", - "PCIE_LH4_15", - "PCIE_LH4_16", - "PCIE_LH4_17", - "PCIE_LH4_18", - "PCIE_LH4_19", - "PCIE_LH4_2", - "PCIE_LH4_3", - "PCIE_LH4_4", - "PCIE_LH4_5", - "PCIE_LH4_6", - "PCIE_LH4_7", - "PCIE_LH4_8", - "PCIE_LH4_9", - "PCIE_LH5_0", - "PCIE_LH5_1", - "PCIE_LH5_10", - "PCIE_LH5_11", - "PCIE_LH5_12", - "PCIE_LH5_13", - "PCIE_LH5_14", - "PCIE_LH5_15", - "PCIE_LH5_16", - "PCIE_LH5_17", - "PCIE_LH5_18", - "PCIE_LH5_19", - "PCIE_LH5_2", - "PCIE_LH5_3", - "PCIE_LH5_4", - "PCIE_LH5_5", - "PCIE_LH5_6", - "PCIE_LH5_7", - "PCIE_LH5_8", - "PCIE_LH5_9", - "PCIE_LH6_0", - "PCIE_LH6_1", - "PCIE_LH6_10", - "PCIE_LH6_11", - "PCIE_LH6_12", - "PCIE_LH6_13", - "PCIE_LH6_14", - "PCIE_LH6_15", - "PCIE_LH6_16", - "PCIE_LH6_17", - "PCIE_LH6_18", - "PCIE_LH6_19", - "PCIE_LH6_2", - "PCIE_LH6_3", - "PCIE_LH6_4", - "PCIE_LH6_5", - "PCIE_LH6_6", - "PCIE_LH6_7", - "PCIE_LH6_8", - "PCIE_LH6_9", - "PCIE_LH7_0", - "PCIE_LH7_1", - "PCIE_LH7_10", - "PCIE_LH7_11", - "PCIE_LH7_12", - "PCIE_LH7_13", - "PCIE_LH7_14", - "PCIE_LH7_15", - "PCIE_LH7_16", - "PCIE_LH7_17", - "PCIE_LH7_18", - "PCIE_LH7_19", - "PCIE_LH7_2", - "PCIE_LH7_3", - "PCIE_LH7_4", - "PCIE_LH7_5", - "PCIE_LH7_6", - "PCIE_LH7_7", - "PCIE_LH7_8", - "PCIE_LH7_9", - "PCIE_LH8_0", - "PCIE_LH8_1", - "PCIE_LH8_10", - "PCIE_LH8_11", - "PCIE_LH8_12", - "PCIE_LH8_13", - "PCIE_LH8_14", - "PCIE_LH8_15", - "PCIE_LH8_16", - "PCIE_LH8_17", - "PCIE_LH8_18", - "PCIE_LH8_19", - "PCIE_LH8_2", - "PCIE_LH8_3", - "PCIE_LH8_4", - "PCIE_LH8_5", - "PCIE_LH8_6", - "PCIE_LH8_7", - "PCIE_LH8_8", - "PCIE_LH8_9", - "PCIE_LH9_0", - "PCIE_LH9_1", - "PCIE_LH9_10", - "PCIE_LH9_11", - "PCIE_LH9_12", - "PCIE_LH9_13", - "PCIE_LH9_14", - "PCIE_LH9_15", - "PCIE_LH9_16", - "PCIE_LH9_17", - "PCIE_LH9_18", - "PCIE_LH9_19", - "PCIE_LH9_2", - "PCIE_LH9_3", - "PCIE_LH9_4", - "PCIE_LH9_5", - "PCIE_LH9_6", - "PCIE_LH9_7", - "PCIE_LH9_8", - "PCIE_LH9_9", - "PCIE_LL2BADDLLPERR", - "PCIE_LL2BADTLPERR", - "PCIE_LL2LINKSTATUS0", - "PCIE_LL2LINKSTATUS1", - "PCIE_LL2LINKSTATUS2", - "PCIE_LL2LINKSTATUS3", - "PCIE_LL2LINKSTATUS4", - "PCIE_LL2PROTOCOLERR", - "PCIE_LL2RECEIVERERR", - "PCIE_LL2REPLAYROERR", - "PCIE_LL2REPLAYTOERR", - "PCIE_LL2SENDASREQL1", - "PCIE_LL2SENDENTERL1", - "PCIE_LL2SENDENTERL23", - "PCIE_LL2SENDPMACK", - "PCIE_LL2SUSPENDNOW", - "PCIE_LL2SUSPENDOK", - "PCIE_LL2TFCINIT1SEQ", - "PCIE_LL2TFCINIT2SEQ", - "PCIE_LL2TLPRCV", - "PCIE_LL2TXIDLE", - "PCIE_LNKCLKEN", - "PCIE_LOGIC_OUTS_B0_L_0", - "PCIE_LOGIC_OUTS_B0_L_1", - "PCIE_LOGIC_OUTS_B0_L_10", - "PCIE_LOGIC_OUTS_B0_L_11", - "PCIE_LOGIC_OUTS_B0_L_12", - "PCIE_LOGIC_OUTS_B0_L_13", - "PCIE_LOGIC_OUTS_B0_L_14", - "PCIE_LOGIC_OUTS_B0_L_15", - "PCIE_LOGIC_OUTS_B0_L_16", - "PCIE_LOGIC_OUTS_B0_L_17", - "PCIE_LOGIC_OUTS_B0_L_18", - "PCIE_LOGIC_OUTS_B0_L_19", - "PCIE_LOGIC_OUTS_B0_L_2", - "PCIE_LOGIC_OUTS_B0_L_3", - "PCIE_LOGIC_OUTS_B0_L_4", - "PCIE_LOGIC_OUTS_B0_L_5", - "PCIE_LOGIC_OUTS_B0_L_6", - "PCIE_LOGIC_OUTS_B0_L_7", - "PCIE_LOGIC_OUTS_B0_L_8", - "PCIE_LOGIC_OUTS_B0_L_9", - "PCIE_LOGIC_OUTS_B0_R_0", - "PCIE_LOGIC_OUTS_B0_R_1", - "PCIE_LOGIC_OUTS_B0_R_10", - "PCIE_LOGIC_OUTS_B0_R_11", - "PCIE_LOGIC_OUTS_B0_R_12", - "PCIE_LOGIC_OUTS_B0_R_13", - "PCIE_LOGIC_OUTS_B0_R_14", - "PCIE_LOGIC_OUTS_B0_R_15", - "PCIE_LOGIC_OUTS_B0_R_16", - "PCIE_LOGIC_OUTS_B0_R_17", - "PCIE_LOGIC_OUTS_B0_R_18", - "PCIE_LOGIC_OUTS_B0_R_19", - "PCIE_LOGIC_OUTS_B0_R_2", - "PCIE_LOGIC_OUTS_B0_R_3", - "PCIE_LOGIC_OUTS_B0_R_4", - "PCIE_LOGIC_OUTS_B0_R_5", - "PCIE_LOGIC_OUTS_B0_R_6", - "PCIE_LOGIC_OUTS_B0_R_7", - "PCIE_LOGIC_OUTS_B0_R_8", - "PCIE_LOGIC_OUTS_B0_R_9", - "PCIE_LOGIC_OUTS_B10_L_0", - "PCIE_LOGIC_OUTS_B10_L_1", - "PCIE_LOGIC_OUTS_B10_L_10", - "PCIE_LOGIC_OUTS_B10_L_11", - "PCIE_LOGIC_OUTS_B10_L_12", - "PCIE_LOGIC_OUTS_B10_L_13", - "PCIE_LOGIC_OUTS_B10_L_14", - "PCIE_LOGIC_OUTS_B10_L_15", - "PCIE_LOGIC_OUTS_B10_L_16", - "PCIE_LOGIC_OUTS_B10_L_17", - "PCIE_LOGIC_OUTS_B10_L_18", - "PCIE_LOGIC_OUTS_B10_L_19", - "PCIE_LOGIC_OUTS_B10_L_2", - "PCIE_LOGIC_OUTS_B10_L_3", - "PCIE_LOGIC_OUTS_B10_L_4", - "PCIE_LOGIC_OUTS_B10_L_5", - "PCIE_LOGIC_OUTS_B10_L_6", - "PCIE_LOGIC_OUTS_B10_L_7", - "PCIE_LOGIC_OUTS_B10_L_8", - "PCIE_LOGIC_OUTS_B10_L_9", - "PCIE_LOGIC_OUTS_B10_R_0", - "PCIE_LOGIC_OUTS_B10_R_1", - "PCIE_LOGIC_OUTS_B10_R_10", - "PCIE_LOGIC_OUTS_B10_R_11", - "PCIE_LOGIC_OUTS_B10_R_12", - "PCIE_LOGIC_OUTS_B10_R_13", - "PCIE_LOGIC_OUTS_B10_R_14", - "PCIE_LOGIC_OUTS_B10_R_15", - "PCIE_LOGIC_OUTS_B10_R_16", - "PCIE_LOGIC_OUTS_B10_R_17", - "PCIE_LOGIC_OUTS_B10_R_18", - "PCIE_LOGIC_OUTS_B10_R_19", - "PCIE_LOGIC_OUTS_B10_R_2", - "PCIE_LOGIC_OUTS_B10_R_3", - "PCIE_LOGIC_OUTS_B10_R_4", - "PCIE_LOGIC_OUTS_B10_R_5", - "PCIE_LOGIC_OUTS_B10_R_6", - "PCIE_LOGIC_OUTS_B10_R_7", - "PCIE_LOGIC_OUTS_B10_R_8", - "PCIE_LOGIC_OUTS_B10_R_9", - "PCIE_LOGIC_OUTS_B11_L_0", - "PCIE_LOGIC_OUTS_B11_L_1", - "PCIE_LOGIC_OUTS_B11_L_10", - "PCIE_LOGIC_OUTS_B11_L_11", - "PCIE_LOGIC_OUTS_B11_L_12", - "PCIE_LOGIC_OUTS_B11_L_13", - "PCIE_LOGIC_OUTS_B11_L_14", - "PCIE_LOGIC_OUTS_B11_L_15", - "PCIE_LOGIC_OUTS_B11_L_16", - "PCIE_LOGIC_OUTS_B11_L_17", - "PCIE_LOGIC_OUTS_B11_L_18", - "PCIE_LOGIC_OUTS_B11_L_19", - "PCIE_LOGIC_OUTS_B11_L_2", - "PCIE_LOGIC_OUTS_B11_L_3", - "PCIE_LOGIC_OUTS_B11_L_4", - "PCIE_LOGIC_OUTS_B11_L_5", - "PCIE_LOGIC_OUTS_B11_L_6", - "PCIE_LOGIC_OUTS_B11_L_7", - "PCIE_LOGIC_OUTS_B11_L_8", - "PCIE_LOGIC_OUTS_B11_L_9", - "PCIE_LOGIC_OUTS_B11_R_0", - "PCIE_LOGIC_OUTS_B11_R_1", - "PCIE_LOGIC_OUTS_B11_R_10", - "PCIE_LOGIC_OUTS_B11_R_11", - "PCIE_LOGIC_OUTS_B11_R_12", - "PCIE_LOGIC_OUTS_B11_R_13", - "PCIE_LOGIC_OUTS_B11_R_14", - "PCIE_LOGIC_OUTS_B11_R_15", - "PCIE_LOGIC_OUTS_B11_R_16", - "PCIE_LOGIC_OUTS_B11_R_17", - "PCIE_LOGIC_OUTS_B11_R_18", - "PCIE_LOGIC_OUTS_B11_R_19", - "PCIE_LOGIC_OUTS_B11_R_2", - "PCIE_LOGIC_OUTS_B11_R_3", - "PCIE_LOGIC_OUTS_B11_R_4", - "PCIE_LOGIC_OUTS_B11_R_5", - "PCIE_LOGIC_OUTS_B11_R_6", - "PCIE_LOGIC_OUTS_B11_R_7", - "PCIE_LOGIC_OUTS_B11_R_8", - "PCIE_LOGIC_OUTS_B11_R_9", - "PCIE_LOGIC_OUTS_B12_L_0", - "PCIE_LOGIC_OUTS_B12_L_1", - "PCIE_LOGIC_OUTS_B12_L_10", - "PCIE_LOGIC_OUTS_B12_L_11", - "PCIE_LOGIC_OUTS_B12_L_12", - "PCIE_LOGIC_OUTS_B12_L_13", - "PCIE_LOGIC_OUTS_B12_L_14", - "PCIE_LOGIC_OUTS_B12_L_15", - "PCIE_LOGIC_OUTS_B12_L_16", - "PCIE_LOGIC_OUTS_B12_L_17", - "PCIE_LOGIC_OUTS_B12_L_18", - "PCIE_LOGIC_OUTS_B12_L_19", - "PCIE_LOGIC_OUTS_B12_L_2", - "PCIE_LOGIC_OUTS_B12_L_3", - "PCIE_LOGIC_OUTS_B12_L_4", - "PCIE_LOGIC_OUTS_B12_L_5", - "PCIE_LOGIC_OUTS_B12_L_6", - "PCIE_LOGIC_OUTS_B12_L_7", - "PCIE_LOGIC_OUTS_B12_L_8", - "PCIE_LOGIC_OUTS_B12_L_9", - "PCIE_LOGIC_OUTS_B12_R_0", - "PCIE_LOGIC_OUTS_B12_R_1", - "PCIE_LOGIC_OUTS_B12_R_10", - "PCIE_LOGIC_OUTS_B12_R_11", - "PCIE_LOGIC_OUTS_B12_R_12", - "PCIE_LOGIC_OUTS_B12_R_13", - "PCIE_LOGIC_OUTS_B12_R_14", - "PCIE_LOGIC_OUTS_B12_R_15", - "PCIE_LOGIC_OUTS_B12_R_16", - "PCIE_LOGIC_OUTS_B12_R_17", - "PCIE_LOGIC_OUTS_B12_R_18", - "PCIE_LOGIC_OUTS_B12_R_19", - "PCIE_LOGIC_OUTS_B12_R_2", - "PCIE_LOGIC_OUTS_B12_R_3", - "PCIE_LOGIC_OUTS_B12_R_4", - "PCIE_LOGIC_OUTS_B12_R_5", - "PCIE_LOGIC_OUTS_B12_R_6", - "PCIE_LOGIC_OUTS_B12_R_7", - "PCIE_LOGIC_OUTS_B12_R_8", - "PCIE_LOGIC_OUTS_B12_R_9", - "PCIE_LOGIC_OUTS_B13_L_0", - "PCIE_LOGIC_OUTS_B13_L_1", - "PCIE_LOGIC_OUTS_B13_L_10", - "PCIE_LOGIC_OUTS_B13_L_11", - "PCIE_LOGIC_OUTS_B13_L_12", - "PCIE_LOGIC_OUTS_B13_L_13", - "PCIE_LOGIC_OUTS_B13_L_14", - "PCIE_LOGIC_OUTS_B13_L_15", - "PCIE_LOGIC_OUTS_B13_L_16", - "PCIE_LOGIC_OUTS_B13_L_17", - "PCIE_LOGIC_OUTS_B13_L_18", - "PCIE_LOGIC_OUTS_B13_L_19", - "PCIE_LOGIC_OUTS_B13_L_2", - "PCIE_LOGIC_OUTS_B13_L_3", - "PCIE_LOGIC_OUTS_B13_L_4", - "PCIE_LOGIC_OUTS_B13_L_5", - "PCIE_LOGIC_OUTS_B13_L_6", - "PCIE_LOGIC_OUTS_B13_L_7", - "PCIE_LOGIC_OUTS_B13_L_8", - "PCIE_LOGIC_OUTS_B13_L_9", - "PCIE_LOGIC_OUTS_B13_R_0", - "PCIE_LOGIC_OUTS_B13_R_1", - "PCIE_LOGIC_OUTS_B13_R_10", - "PCIE_LOGIC_OUTS_B13_R_11", - "PCIE_LOGIC_OUTS_B13_R_12", - "PCIE_LOGIC_OUTS_B13_R_13", - "PCIE_LOGIC_OUTS_B13_R_14", - "PCIE_LOGIC_OUTS_B13_R_15", - "PCIE_LOGIC_OUTS_B13_R_16", - "PCIE_LOGIC_OUTS_B13_R_17", - "PCIE_LOGIC_OUTS_B13_R_18", - "PCIE_LOGIC_OUTS_B13_R_19", - "PCIE_LOGIC_OUTS_B13_R_2", - "PCIE_LOGIC_OUTS_B13_R_3", - "PCIE_LOGIC_OUTS_B13_R_4", - "PCIE_LOGIC_OUTS_B13_R_5", - "PCIE_LOGIC_OUTS_B13_R_6", - "PCIE_LOGIC_OUTS_B13_R_7", - "PCIE_LOGIC_OUTS_B13_R_8", - "PCIE_LOGIC_OUTS_B13_R_9", - "PCIE_LOGIC_OUTS_B14_L_0", - "PCIE_LOGIC_OUTS_B14_L_1", - "PCIE_LOGIC_OUTS_B14_L_10", - "PCIE_LOGIC_OUTS_B14_L_11", - "PCIE_LOGIC_OUTS_B14_L_12", - "PCIE_LOGIC_OUTS_B14_L_13", - "PCIE_LOGIC_OUTS_B14_L_14", - "PCIE_LOGIC_OUTS_B14_L_15", - "PCIE_LOGIC_OUTS_B14_L_16", - "PCIE_LOGIC_OUTS_B14_L_17", - "PCIE_LOGIC_OUTS_B14_L_18", - "PCIE_LOGIC_OUTS_B14_L_19", - "PCIE_LOGIC_OUTS_B14_L_2", - "PCIE_LOGIC_OUTS_B14_L_3", - "PCIE_LOGIC_OUTS_B14_L_4", - "PCIE_LOGIC_OUTS_B14_L_5", - "PCIE_LOGIC_OUTS_B14_L_6", - "PCIE_LOGIC_OUTS_B14_L_7", - "PCIE_LOGIC_OUTS_B14_L_8", - "PCIE_LOGIC_OUTS_B14_L_9", - "PCIE_LOGIC_OUTS_B14_R_0", - "PCIE_LOGIC_OUTS_B14_R_1", - "PCIE_LOGIC_OUTS_B14_R_10", - "PCIE_LOGIC_OUTS_B14_R_11", - "PCIE_LOGIC_OUTS_B14_R_12", - "PCIE_LOGIC_OUTS_B14_R_13", - "PCIE_LOGIC_OUTS_B14_R_14", - "PCIE_LOGIC_OUTS_B14_R_15", - "PCIE_LOGIC_OUTS_B14_R_16", - "PCIE_LOGIC_OUTS_B14_R_17", - "PCIE_LOGIC_OUTS_B14_R_18", - "PCIE_LOGIC_OUTS_B14_R_19", - "PCIE_LOGIC_OUTS_B14_R_2", - "PCIE_LOGIC_OUTS_B14_R_3", - "PCIE_LOGIC_OUTS_B14_R_4", - "PCIE_LOGIC_OUTS_B14_R_5", - "PCIE_LOGIC_OUTS_B14_R_6", - "PCIE_LOGIC_OUTS_B14_R_7", - "PCIE_LOGIC_OUTS_B14_R_8", - "PCIE_LOGIC_OUTS_B14_R_9", - "PCIE_LOGIC_OUTS_B15_L_0", - "PCIE_LOGIC_OUTS_B15_L_1", - "PCIE_LOGIC_OUTS_B15_L_10", - "PCIE_LOGIC_OUTS_B15_L_11", - "PCIE_LOGIC_OUTS_B15_L_12", - "PCIE_LOGIC_OUTS_B15_L_13", - "PCIE_LOGIC_OUTS_B15_L_14", - "PCIE_LOGIC_OUTS_B15_L_15", - "PCIE_LOGIC_OUTS_B15_L_16", - "PCIE_LOGIC_OUTS_B15_L_17", - "PCIE_LOGIC_OUTS_B15_L_18", - "PCIE_LOGIC_OUTS_B15_L_19", - "PCIE_LOGIC_OUTS_B15_L_2", - "PCIE_LOGIC_OUTS_B15_L_3", - "PCIE_LOGIC_OUTS_B15_L_4", - "PCIE_LOGIC_OUTS_B15_L_5", - "PCIE_LOGIC_OUTS_B15_L_6", - "PCIE_LOGIC_OUTS_B15_L_7", - "PCIE_LOGIC_OUTS_B15_L_8", - "PCIE_LOGIC_OUTS_B15_L_9", - "PCIE_LOGIC_OUTS_B15_R_0", - "PCIE_LOGIC_OUTS_B15_R_1", - "PCIE_LOGIC_OUTS_B15_R_10", - "PCIE_LOGIC_OUTS_B15_R_11", - "PCIE_LOGIC_OUTS_B15_R_12", - "PCIE_LOGIC_OUTS_B15_R_13", - "PCIE_LOGIC_OUTS_B15_R_14", - "PCIE_LOGIC_OUTS_B15_R_15", - "PCIE_LOGIC_OUTS_B15_R_16", - "PCIE_LOGIC_OUTS_B15_R_17", - "PCIE_LOGIC_OUTS_B15_R_18", - "PCIE_LOGIC_OUTS_B15_R_19", - "PCIE_LOGIC_OUTS_B15_R_2", - "PCIE_LOGIC_OUTS_B15_R_3", - "PCIE_LOGIC_OUTS_B15_R_4", - "PCIE_LOGIC_OUTS_B15_R_5", - "PCIE_LOGIC_OUTS_B15_R_6", - "PCIE_LOGIC_OUTS_B15_R_7", - "PCIE_LOGIC_OUTS_B15_R_8", - "PCIE_LOGIC_OUTS_B15_R_9", - "PCIE_LOGIC_OUTS_B16_L_0", - "PCIE_LOGIC_OUTS_B16_L_1", - "PCIE_LOGIC_OUTS_B16_L_10", - "PCIE_LOGIC_OUTS_B16_L_11", - "PCIE_LOGIC_OUTS_B16_L_12", - "PCIE_LOGIC_OUTS_B16_L_13", - "PCIE_LOGIC_OUTS_B16_L_14", - "PCIE_LOGIC_OUTS_B16_L_15", - "PCIE_LOGIC_OUTS_B16_L_16", - "PCIE_LOGIC_OUTS_B16_L_17", - "PCIE_LOGIC_OUTS_B16_L_18", - "PCIE_LOGIC_OUTS_B16_L_19", - "PCIE_LOGIC_OUTS_B16_L_2", - "PCIE_LOGIC_OUTS_B16_L_3", - "PCIE_LOGIC_OUTS_B16_L_4", - "PCIE_LOGIC_OUTS_B16_L_5", - "PCIE_LOGIC_OUTS_B16_L_6", - "PCIE_LOGIC_OUTS_B16_L_7", - "PCIE_LOGIC_OUTS_B16_L_8", - "PCIE_LOGIC_OUTS_B16_L_9", - "PCIE_LOGIC_OUTS_B16_R_0", - "PCIE_LOGIC_OUTS_B16_R_1", - "PCIE_LOGIC_OUTS_B16_R_10", - "PCIE_LOGIC_OUTS_B16_R_11", - "PCIE_LOGIC_OUTS_B16_R_12", - "PCIE_LOGIC_OUTS_B16_R_13", - "PCIE_LOGIC_OUTS_B16_R_14", - "PCIE_LOGIC_OUTS_B16_R_15", - "PCIE_LOGIC_OUTS_B16_R_16", - "PCIE_LOGIC_OUTS_B16_R_17", - "PCIE_LOGIC_OUTS_B16_R_18", - "PCIE_LOGIC_OUTS_B16_R_19", - "PCIE_LOGIC_OUTS_B16_R_2", - "PCIE_LOGIC_OUTS_B16_R_3", - "PCIE_LOGIC_OUTS_B16_R_4", - "PCIE_LOGIC_OUTS_B16_R_5", - "PCIE_LOGIC_OUTS_B16_R_6", - "PCIE_LOGIC_OUTS_B16_R_7", - "PCIE_LOGIC_OUTS_B16_R_8", - "PCIE_LOGIC_OUTS_B16_R_9", - "PCIE_LOGIC_OUTS_B17_L_0", - "PCIE_LOGIC_OUTS_B17_L_1", - "PCIE_LOGIC_OUTS_B17_L_10", - "PCIE_LOGIC_OUTS_B17_L_11", - "PCIE_LOGIC_OUTS_B17_L_12", - "PCIE_LOGIC_OUTS_B17_L_13", - "PCIE_LOGIC_OUTS_B17_L_14", - "PCIE_LOGIC_OUTS_B17_L_15", - "PCIE_LOGIC_OUTS_B17_L_16", - "PCIE_LOGIC_OUTS_B17_L_17", - "PCIE_LOGIC_OUTS_B17_L_18", - "PCIE_LOGIC_OUTS_B17_L_19", - "PCIE_LOGIC_OUTS_B17_L_2", - "PCIE_LOGIC_OUTS_B17_L_3", - "PCIE_LOGIC_OUTS_B17_L_4", - "PCIE_LOGIC_OUTS_B17_L_5", - "PCIE_LOGIC_OUTS_B17_L_6", - "PCIE_LOGIC_OUTS_B17_L_7", - "PCIE_LOGIC_OUTS_B17_L_8", - "PCIE_LOGIC_OUTS_B17_L_9", - "PCIE_LOGIC_OUTS_B17_R_0", - "PCIE_LOGIC_OUTS_B17_R_1", - "PCIE_LOGIC_OUTS_B17_R_10", - "PCIE_LOGIC_OUTS_B17_R_11", - "PCIE_LOGIC_OUTS_B17_R_12", - "PCIE_LOGIC_OUTS_B17_R_13", - "PCIE_LOGIC_OUTS_B17_R_14", - "PCIE_LOGIC_OUTS_B17_R_15", - "PCIE_LOGIC_OUTS_B17_R_16", - "PCIE_LOGIC_OUTS_B17_R_17", - "PCIE_LOGIC_OUTS_B17_R_18", - "PCIE_LOGIC_OUTS_B17_R_19", - "PCIE_LOGIC_OUTS_B17_R_2", - "PCIE_LOGIC_OUTS_B17_R_3", - "PCIE_LOGIC_OUTS_B17_R_4", - "PCIE_LOGIC_OUTS_B17_R_5", - "PCIE_LOGIC_OUTS_B17_R_6", - "PCIE_LOGIC_OUTS_B17_R_7", - "PCIE_LOGIC_OUTS_B17_R_8", - "PCIE_LOGIC_OUTS_B17_R_9", - "PCIE_LOGIC_OUTS_B18_L_0", - "PCIE_LOGIC_OUTS_B18_L_1", - "PCIE_LOGIC_OUTS_B18_L_10", - "PCIE_LOGIC_OUTS_B18_L_11", - "PCIE_LOGIC_OUTS_B18_L_12", - "PCIE_LOGIC_OUTS_B18_L_13", - "PCIE_LOGIC_OUTS_B18_L_14", - "PCIE_LOGIC_OUTS_B18_L_15", - "PCIE_LOGIC_OUTS_B18_L_16", - "PCIE_LOGIC_OUTS_B18_L_17", - "PCIE_LOGIC_OUTS_B18_L_18", - "PCIE_LOGIC_OUTS_B18_L_19", - "PCIE_LOGIC_OUTS_B18_L_2", - "PCIE_LOGIC_OUTS_B18_L_3", - "PCIE_LOGIC_OUTS_B18_L_4", - "PCIE_LOGIC_OUTS_B18_L_5", - "PCIE_LOGIC_OUTS_B18_L_6", - "PCIE_LOGIC_OUTS_B18_L_7", - "PCIE_LOGIC_OUTS_B18_L_8", - "PCIE_LOGIC_OUTS_B18_L_9", - "PCIE_LOGIC_OUTS_B18_R_0", - "PCIE_LOGIC_OUTS_B18_R_1", - "PCIE_LOGIC_OUTS_B18_R_10", - "PCIE_LOGIC_OUTS_B18_R_11", - "PCIE_LOGIC_OUTS_B18_R_12", - "PCIE_LOGIC_OUTS_B18_R_13", - "PCIE_LOGIC_OUTS_B18_R_14", - "PCIE_LOGIC_OUTS_B18_R_15", - "PCIE_LOGIC_OUTS_B18_R_16", - "PCIE_LOGIC_OUTS_B18_R_17", - "PCIE_LOGIC_OUTS_B18_R_18", - "PCIE_LOGIC_OUTS_B18_R_19", - "PCIE_LOGIC_OUTS_B18_R_2", - "PCIE_LOGIC_OUTS_B18_R_3", - "PCIE_LOGIC_OUTS_B18_R_4", - "PCIE_LOGIC_OUTS_B18_R_5", - "PCIE_LOGIC_OUTS_B18_R_6", - "PCIE_LOGIC_OUTS_B18_R_7", - "PCIE_LOGIC_OUTS_B18_R_8", - "PCIE_LOGIC_OUTS_B18_R_9", - "PCIE_LOGIC_OUTS_B19_L_0", - "PCIE_LOGIC_OUTS_B19_L_1", - "PCIE_LOGIC_OUTS_B19_L_10", - "PCIE_LOGIC_OUTS_B19_L_11", - "PCIE_LOGIC_OUTS_B19_L_12", - "PCIE_LOGIC_OUTS_B19_L_13", - "PCIE_LOGIC_OUTS_B19_L_14", - "PCIE_LOGIC_OUTS_B19_L_15", - "PCIE_LOGIC_OUTS_B19_L_16", - "PCIE_LOGIC_OUTS_B19_L_17", - "PCIE_LOGIC_OUTS_B19_L_18", - "PCIE_LOGIC_OUTS_B19_L_19", - "PCIE_LOGIC_OUTS_B19_L_2", - "PCIE_LOGIC_OUTS_B19_L_3", - "PCIE_LOGIC_OUTS_B19_L_4", - "PCIE_LOGIC_OUTS_B19_L_5", - "PCIE_LOGIC_OUTS_B19_L_6", - "PCIE_LOGIC_OUTS_B19_L_7", - "PCIE_LOGIC_OUTS_B19_L_8", - "PCIE_LOGIC_OUTS_B19_L_9", - "PCIE_LOGIC_OUTS_B19_R_0", - "PCIE_LOGIC_OUTS_B19_R_1", - "PCIE_LOGIC_OUTS_B19_R_10", - "PCIE_LOGIC_OUTS_B19_R_11", - "PCIE_LOGIC_OUTS_B19_R_12", - "PCIE_LOGIC_OUTS_B19_R_13", - "PCIE_LOGIC_OUTS_B19_R_14", - "PCIE_LOGIC_OUTS_B19_R_15", - "PCIE_LOGIC_OUTS_B19_R_16", - "PCIE_LOGIC_OUTS_B19_R_17", - "PCIE_LOGIC_OUTS_B19_R_18", - "PCIE_LOGIC_OUTS_B19_R_19", - "PCIE_LOGIC_OUTS_B19_R_2", - "PCIE_LOGIC_OUTS_B19_R_3", - "PCIE_LOGIC_OUTS_B19_R_4", - "PCIE_LOGIC_OUTS_B19_R_5", - "PCIE_LOGIC_OUTS_B19_R_6", - "PCIE_LOGIC_OUTS_B19_R_7", - "PCIE_LOGIC_OUTS_B19_R_8", - "PCIE_LOGIC_OUTS_B19_R_9", - "PCIE_LOGIC_OUTS_B1_L_0", - "PCIE_LOGIC_OUTS_B1_L_1", - "PCIE_LOGIC_OUTS_B1_L_10", - "PCIE_LOGIC_OUTS_B1_L_11", - "PCIE_LOGIC_OUTS_B1_L_12", - "PCIE_LOGIC_OUTS_B1_L_13", - "PCIE_LOGIC_OUTS_B1_L_14", - "PCIE_LOGIC_OUTS_B1_L_15", - "PCIE_LOGIC_OUTS_B1_L_16", - "PCIE_LOGIC_OUTS_B1_L_17", - "PCIE_LOGIC_OUTS_B1_L_18", - "PCIE_LOGIC_OUTS_B1_L_19", - "PCIE_LOGIC_OUTS_B1_L_2", - "PCIE_LOGIC_OUTS_B1_L_3", - "PCIE_LOGIC_OUTS_B1_L_4", - "PCIE_LOGIC_OUTS_B1_L_5", - "PCIE_LOGIC_OUTS_B1_L_6", - "PCIE_LOGIC_OUTS_B1_L_7", - "PCIE_LOGIC_OUTS_B1_L_8", - "PCIE_LOGIC_OUTS_B1_L_9", - "PCIE_LOGIC_OUTS_B1_R_0", - "PCIE_LOGIC_OUTS_B1_R_1", - "PCIE_LOGIC_OUTS_B1_R_10", - "PCIE_LOGIC_OUTS_B1_R_11", - "PCIE_LOGIC_OUTS_B1_R_12", - "PCIE_LOGIC_OUTS_B1_R_13", - "PCIE_LOGIC_OUTS_B1_R_14", - "PCIE_LOGIC_OUTS_B1_R_15", - "PCIE_LOGIC_OUTS_B1_R_16", - "PCIE_LOGIC_OUTS_B1_R_17", - "PCIE_LOGIC_OUTS_B1_R_18", - "PCIE_LOGIC_OUTS_B1_R_19", - "PCIE_LOGIC_OUTS_B1_R_2", - "PCIE_LOGIC_OUTS_B1_R_3", - "PCIE_LOGIC_OUTS_B1_R_4", - "PCIE_LOGIC_OUTS_B1_R_5", - "PCIE_LOGIC_OUTS_B1_R_6", - "PCIE_LOGIC_OUTS_B1_R_7", - "PCIE_LOGIC_OUTS_B1_R_8", - "PCIE_LOGIC_OUTS_B1_R_9", - "PCIE_LOGIC_OUTS_B20_L_0", - "PCIE_LOGIC_OUTS_B20_L_1", - "PCIE_LOGIC_OUTS_B20_L_10", - "PCIE_LOGIC_OUTS_B20_L_11", - "PCIE_LOGIC_OUTS_B20_L_12", - "PCIE_LOGIC_OUTS_B20_L_13", - "PCIE_LOGIC_OUTS_B20_L_14", - "PCIE_LOGIC_OUTS_B20_L_15", - "PCIE_LOGIC_OUTS_B20_L_16", - "PCIE_LOGIC_OUTS_B20_L_17", - "PCIE_LOGIC_OUTS_B20_L_18", - "PCIE_LOGIC_OUTS_B20_L_19", - "PCIE_LOGIC_OUTS_B20_L_2", - "PCIE_LOGIC_OUTS_B20_L_3", - "PCIE_LOGIC_OUTS_B20_L_4", - "PCIE_LOGIC_OUTS_B20_L_5", - "PCIE_LOGIC_OUTS_B20_L_6", - "PCIE_LOGIC_OUTS_B20_L_7", - "PCIE_LOGIC_OUTS_B20_L_8", - "PCIE_LOGIC_OUTS_B20_L_9", - "PCIE_LOGIC_OUTS_B20_R_0", - "PCIE_LOGIC_OUTS_B20_R_1", - "PCIE_LOGIC_OUTS_B20_R_10", - "PCIE_LOGIC_OUTS_B20_R_11", - "PCIE_LOGIC_OUTS_B20_R_12", - "PCIE_LOGIC_OUTS_B20_R_13", - "PCIE_LOGIC_OUTS_B20_R_14", - "PCIE_LOGIC_OUTS_B20_R_15", - "PCIE_LOGIC_OUTS_B20_R_16", - "PCIE_LOGIC_OUTS_B20_R_17", - "PCIE_LOGIC_OUTS_B20_R_18", - "PCIE_LOGIC_OUTS_B20_R_19", - "PCIE_LOGIC_OUTS_B20_R_2", - "PCIE_LOGIC_OUTS_B20_R_3", - "PCIE_LOGIC_OUTS_B20_R_4", - "PCIE_LOGIC_OUTS_B20_R_5", - "PCIE_LOGIC_OUTS_B20_R_6", - "PCIE_LOGIC_OUTS_B20_R_7", - "PCIE_LOGIC_OUTS_B20_R_8", - "PCIE_LOGIC_OUTS_B20_R_9", - "PCIE_LOGIC_OUTS_B21_L_0", - "PCIE_LOGIC_OUTS_B21_L_1", - "PCIE_LOGIC_OUTS_B21_L_10", - "PCIE_LOGIC_OUTS_B21_L_11", - "PCIE_LOGIC_OUTS_B21_L_12", - "PCIE_LOGIC_OUTS_B21_L_13", - "PCIE_LOGIC_OUTS_B21_L_14", - "PCIE_LOGIC_OUTS_B21_L_15", - "PCIE_LOGIC_OUTS_B21_L_16", - "PCIE_LOGIC_OUTS_B21_L_17", - "PCIE_LOGIC_OUTS_B21_L_18", - "PCIE_LOGIC_OUTS_B21_L_19", - "PCIE_LOGIC_OUTS_B21_L_2", - "PCIE_LOGIC_OUTS_B21_L_3", - "PCIE_LOGIC_OUTS_B21_L_4", - "PCIE_LOGIC_OUTS_B21_L_5", - "PCIE_LOGIC_OUTS_B21_L_6", - "PCIE_LOGIC_OUTS_B21_L_7", - "PCIE_LOGIC_OUTS_B21_L_8", - "PCIE_LOGIC_OUTS_B21_L_9", - "PCIE_LOGIC_OUTS_B21_R_0", - "PCIE_LOGIC_OUTS_B21_R_1", - "PCIE_LOGIC_OUTS_B21_R_10", - "PCIE_LOGIC_OUTS_B21_R_11", - "PCIE_LOGIC_OUTS_B21_R_12", - "PCIE_LOGIC_OUTS_B21_R_13", - "PCIE_LOGIC_OUTS_B21_R_14", - "PCIE_LOGIC_OUTS_B21_R_15", - "PCIE_LOGIC_OUTS_B21_R_16", - "PCIE_LOGIC_OUTS_B21_R_17", - "PCIE_LOGIC_OUTS_B21_R_18", - "PCIE_LOGIC_OUTS_B21_R_19", - "PCIE_LOGIC_OUTS_B21_R_2", - "PCIE_LOGIC_OUTS_B21_R_3", - "PCIE_LOGIC_OUTS_B21_R_4", - "PCIE_LOGIC_OUTS_B21_R_5", - "PCIE_LOGIC_OUTS_B21_R_6", - "PCIE_LOGIC_OUTS_B21_R_7", - "PCIE_LOGIC_OUTS_B21_R_8", - "PCIE_LOGIC_OUTS_B21_R_9", - "PCIE_LOGIC_OUTS_B22_L_0", - "PCIE_LOGIC_OUTS_B22_L_1", - "PCIE_LOGIC_OUTS_B22_L_10", - "PCIE_LOGIC_OUTS_B22_L_11", - "PCIE_LOGIC_OUTS_B22_L_12", - "PCIE_LOGIC_OUTS_B22_L_13", - "PCIE_LOGIC_OUTS_B22_L_14", - "PCIE_LOGIC_OUTS_B22_L_15", - "PCIE_LOGIC_OUTS_B22_L_16", - "PCIE_LOGIC_OUTS_B22_L_17", - "PCIE_LOGIC_OUTS_B22_L_18", - "PCIE_LOGIC_OUTS_B22_L_19", - "PCIE_LOGIC_OUTS_B22_L_2", - "PCIE_LOGIC_OUTS_B22_L_3", - "PCIE_LOGIC_OUTS_B22_L_4", - "PCIE_LOGIC_OUTS_B22_L_5", - "PCIE_LOGIC_OUTS_B22_L_6", - "PCIE_LOGIC_OUTS_B22_L_7", - "PCIE_LOGIC_OUTS_B22_L_8", - "PCIE_LOGIC_OUTS_B22_L_9", - "PCIE_LOGIC_OUTS_B22_R_0", - "PCIE_LOGIC_OUTS_B22_R_1", - "PCIE_LOGIC_OUTS_B22_R_10", - "PCIE_LOGIC_OUTS_B22_R_11", - "PCIE_LOGIC_OUTS_B22_R_12", - "PCIE_LOGIC_OUTS_B22_R_13", - "PCIE_LOGIC_OUTS_B22_R_14", - "PCIE_LOGIC_OUTS_B22_R_15", - "PCIE_LOGIC_OUTS_B22_R_16", - "PCIE_LOGIC_OUTS_B22_R_17", - "PCIE_LOGIC_OUTS_B22_R_18", - "PCIE_LOGIC_OUTS_B22_R_19", - "PCIE_LOGIC_OUTS_B22_R_2", - "PCIE_LOGIC_OUTS_B22_R_3", - "PCIE_LOGIC_OUTS_B22_R_4", - "PCIE_LOGIC_OUTS_B22_R_5", - "PCIE_LOGIC_OUTS_B22_R_6", - "PCIE_LOGIC_OUTS_B22_R_7", - "PCIE_LOGIC_OUTS_B22_R_8", - "PCIE_LOGIC_OUTS_B22_R_9", - "PCIE_LOGIC_OUTS_B23_L_0", - "PCIE_LOGIC_OUTS_B23_L_1", - "PCIE_LOGIC_OUTS_B23_L_10", - "PCIE_LOGIC_OUTS_B23_L_11", - "PCIE_LOGIC_OUTS_B23_L_12", - "PCIE_LOGIC_OUTS_B23_L_13", - "PCIE_LOGIC_OUTS_B23_L_14", - "PCIE_LOGIC_OUTS_B23_L_15", - "PCIE_LOGIC_OUTS_B23_L_16", - "PCIE_LOGIC_OUTS_B23_L_17", - "PCIE_LOGIC_OUTS_B23_L_18", - "PCIE_LOGIC_OUTS_B23_L_19", - "PCIE_LOGIC_OUTS_B23_L_2", - "PCIE_LOGIC_OUTS_B23_L_3", - "PCIE_LOGIC_OUTS_B23_L_4", - "PCIE_LOGIC_OUTS_B23_L_5", - "PCIE_LOGIC_OUTS_B23_L_6", - "PCIE_LOGIC_OUTS_B23_L_7", - "PCIE_LOGIC_OUTS_B23_L_8", - "PCIE_LOGIC_OUTS_B23_L_9", - "PCIE_LOGIC_OUTS_B23_R_0", - "PCIE_LOGIC_OUTS_B23_R_1", - "PCIE_LOGIC_OUTS_B23_R_10", - "PCIE_LOGIC_OUTS_B23_R_11", - "PCIE_LOGIC_OUTS_B23_R_12", - "PCIE_LOGIC_OUTS_B23_R_13", - "PCIE_LOGIC_OUTS_B23_R_14", - "PCIE_LOGIC_OUTS_B23_R_15", - "PCIE_LOGIC_OUTS_B23_R_16", - "PCIE_LOGIC_OUTS_B23_R_17", - "PCIE_LOGIC_OUTS_B23_R_18", - "PCIE_LOGIC_OUTS_B23_R_19", - "PCIE_LOGIC_OUTS_B23_R_2", - "PCIE_LOGIC_OUTS_B23_R_3", - "PCIE_LOGIC_OUTS_B23_R_4", - "PCIE_LOGIC_OUTS_B23_R_5", - "PCIE_LOGIC_OUTS_B23_R_6", - "PCIE_LOGIC_OUTS_B23_R_7", - "PCIE_LOGIC_OUTS_B23_R_8", - "PCIE_LOGIC_OUTS_B23_R_9", - "PCIE_LOGIC_OUTS_B2_L_0", - "PCIE_LOGIC_OUTS_B2_L_1", - "PCIE_LOGIC_OUTS_B2_L_10", - "PCIE_LOGIC_OUTS_B2_L_11", - "PCIE_LOGIC_OUTS_B2_L_12", - "PCIE_LOGIC_OUTS_B2_L_13", - "PCIE_LOGIC_OUTS_B2_L_14", - "PCIE_LOGIC_OUTS_B2_L_15", - "PCIE_LOGIC_OUTS_B2_L_16", - "PCIE_LOGIC_OUTS_B2_L_17", - "PCIE_LOGIC_OUTS_B2_L_18", - "PCIE_LOGIC_OUTS_B2_L_19", - "PCIE_LOGIC_OUTS_B2_L_2", - "PCIE_LOGIC_OUTS_B2_L_3", - "PCIE_LOGIC_OUTS_B2_L_4", - "PCIE_LOGIC_OUTS_B2_L_5", - "PCIE_LOGIC_OUTS_B2_L_6", - "PCIE_LOGIC_OUTS_B2_L_7", - "PCIE_LOGIC_OUTS_B2_L_8", - "PCIE_LOGIC_OUTS_B2_L_9", - "PCIE_LOGIC_OUTS_B2_R_0", - "PCIE_LOGIC_OUTS_B2_R_1", - "PCIE_LOGIC_OUTS_B2_R_10", - "PCIE_LOGIC_OUTS_B2_R_11", - "PCIE_LOGIC_OUTS_B2_R_12", - "PCIE_LOGIC_OUTS_B2_R_13", - "PCIE_LOGIC_OUTS_B2_R_14", - "PCIE_LOGIC_OUTS_B2_R_15", - "PCIE_LOGIC_OUTS_B2_R_16", - "PCIE_LOGIC_OUTS_B2_R_17", - "PCIE_LOGIC_OUTS_B2_R_18", - "PCIE_LOGIC_OUTS_B2_R_19", - "PCIE_LOGIC_OUTS_B2_R_2", - "PCIE_LOGIC_OUTS_B2_R_3", - "PCIE_LOGIC_OUTS_B2_R_4", - "PCIE_LOGIC_OUTS_B2_R_5", - "PCIE_LOGIC_OUTS_B2_R_6", - "PCIE_LOGIC_OUTS_B2_R_7", - "PCIE_LOGIC_OUTS_B2_R_8", - "PCIE_LOGIC_OUTS_B2_R_9", - "PCIE_LOGIC_OUTS_B3_L_0", - "PCIE_LOGIC_OUTS_B3_L_1", - "PCIE_LOGIC_OUTS_B3_L_10", - "PCIE_LOGIC_OUTS_B3_L_11", - "PCIE_LOGIC_OUTS_B3_L_12", - "PCIE_LOGIC_OUTS_B3_L_13", - "PCIE_LOGIC_OUTS_B3_L_14", - "PCIE_LOGIC_OUTS_B3_L_15", - "PCIE_LOGIC_OUTS_B3_L_16", - "PCIE_LOGIC_OUTS_B3_L_17", - "PCIE_LOGIC_OUTS_B3_L_18", - "PCIE_LOGIC_OUTS_B3_L_19", - "PCIE_LOGIC_OUTS_B3_L_2", - "PCIE_LOGIC_OUTS_B3_L_3", - "PCIE_LOGIC_OUTS_B3_L_4", - "PCIE_LOGIC_OUTS_B3_L_5", - "PCIE_LOGIC_OUTS_B3_L_6", - "PCIE_LOGIC_OUTS_B3_L_7", - "PCIE_LOGIC_OUTS_B3_L_8", - "PCIE_LOGIC_OUTS_B3_L_9", - "PCIE_LOGIC_OUTS_B3_R_0", - "PCIE_LOGIC_OUTS_B3_R_1", - "PCIE_LOGIC_OUTS_B3_R_10", - "PCIE_LOGIC_OUTS_B3_R_11", - "PCIE_LOGIC_OUTS_B3_R_12", - "PCIE_LOGIC_OUTS_B3_R_13", - "PCIE_LOGIC_OUTS_B3_R_14", - "PCIE_LOGIC_OUTS_B3_R_15", - "PCIE_LOGIC_OUTS_B3_R_16", - "PCIE_LOGIC_OUTS_B3_R_17", - "PCIE_LOGIC_OUTS_B3_R_18", - "PCIE_LOGIC_OUTS_B3_R_19", - "PCIE_LOGIC_OUTS_B3_R_2", - "PCIE_LOGIC_OUTS_B3_R_3", - "PCIE_LOGIC_OUTS_B3_R_4", - "PCIE_LOGIC_OUTS_B3_R_5", - "PCIE_LOGIC_OUTS_B3_R_6", - "PCIE_LOGIC_OUTS_B3_R_7", - "PCIE_LOGIC_OUTS_B3_R_8", - "PCIE_LOGIC_OUTS_B3_R_9", - "PCIE_LOGIC_OUTS_B4_L_0", - "PCIE_LOGIC_OUTS_B4_L_1", - "PCIE_LOGIC_OUTS_B4_L_10", - "PCIE_LOGIC_OUTS_B4_L_11", - "PCIE_LOGIC_OUTS_B4_L_12", - "PCIE_LOGIC_OUTS_B4_L_13", - "PCIE_LOGIC_OUTS_B4_L_14", - "PCIE_LOGIC_OUTS_B4_L_15", - "PCIE_LOGIC_OUTS_B4_L_16", - "PCIE_LOGIC_OUTS_B4_L_17", - "PCIE_LOGIC_OUTS_B4_L_18", - "PCIE_LOGIC_OUTS_B4_L_19", - "PCIE_LOGIC_OUTS_B4_L_2", - "PCIE_LOGIC_OUTS_B4_L_3", - "PCIE_LOGIC_OUTS_B4_L_4", - "PCIE_LOGIC_OUTS_B4_L_5", - "PCIE_LOGIC_OUTS_B4_L_6", - "PCIE_LOGIC_OUTS_B4_L_7", - "PCIE_LOGIC_OUTS_B4_L_8", - "PCIE_LOGIC_OUTS_B4_L_9", - "PCIE_LOGIC_OUTS_B4_R_0", - "PCIE_LOGIC_OUTS_B4_R_1", - "PCIE_LOGIC_OUTS_B4_R_10", - "PCIE_LOGIC_OUTS_B4_R_11", - "PCIE_LOGIC_OUTS_B4_R_12", - "PCIE_LOGIC_OUTS_B4_R_13", - "PCIE_LOGIC_OUTS_B4_R_14", - "PCIE_LOGIC_OUTS_B4_R_15", - "PCIE_LOGIC_OUTS_B4_R_16", - "PCIE_LOGIC_OUTS_B4_R_17", - "PCIE_LOGIC_OUTS_B4_R_18", - "PCIE_LOGIC_OUTS_B4_R_19", - "PCIE_LOGIC_OUTS_B4_R_2", - "PCIE_LOGIC_OUTS_B4_R_3", - "PCIE_LOGIC_OUTS_B4_R_4", - "PCIE_LOGIC_OUTS_B4_R_5", - "PCIE_LOGIC_OUTS_B4_R_6", - "PCIE_LOGIC_OUTS_B4_R_7", - "PCIE_LOGIC_OUTS_B4_R_8", - "PCIE_LOGIC_OUTS_B4_R_9", - "PCIE_LOGIC_OUTS_B5_L_0", - "PCIE_LOGIC_OUTS_B5_L_1", - "PCIE_LOGIC_OUTS_B5_L_10", - "PCIE_LOGIC_OUTS_B5_L_11", - "PCIE_LOGIC_OUTS_B5_L_12", - "PCIE_LOGIC_OUTS_B5_L_13", - "PCIE_LOGIC_OUTS_B5_L_14", - "PCIE_LOGIC_OUTS_B5_L_15", - "PCIE_LOGIC_OUTS_B5_L_16", - "PCIE_LOGIC_OUTS_B5_L_17", - "PCIE_LOGIC_OUTS_B5_L_18", - "PCIE_LOGIC_OUTS_B5_L_19", - "PCIE_LOGIC_OUTS_B5_L_2", - "PCIE_LOGIC_OUTS_B5_L_3", - "PCIE_LOGIC_OUTS_B5_L_4", - "PCIE_LOGIC_OUTS_B5_L_5", - "PCIE_LOGIC_OUTS_B5_L_6", - "PCIE_LOGIC_OUTS_B5_L_7", - "PCIE_LOGIC_OUTS_B5_L_8", - "PCIE_LOGIC_OUTS_B5_L_9", - "PCIE_LOGIC_OUTS_B5_R_0", - "PCIE_LOGIC_OUTS_B5_R_1", - "PCIE_LOGIC_OUTS_B5_R_10", - "PCIE_LOGIC_OUTS_B5_R_11", - "PCIE_LOGIC_OUTS_B5_R_12", - "PCIE_LOGIC_OUTS_B5_R_13", - "PCIE_LOGIC_OUTS_B5_R_14", - "PCIE_LOGIC_OUTS_B5_R_15", - "PCIE_LOGIC_OUTS_B5_R_16", - "PCIE_LOGIC_OUTS_B5_R_17", - "PCIE_LOGIC_OUTS_B5_R_18", - "PCIE_LOGIC_OUTS_B5_R_19", - "PCIE_LOGIC_OUTS_B5_R_2", - "PCIE_LOGIC_OUTS_B5_R_3", - "PCIE_LOGIC_OUTS_B5_R_4", - "PCIE_LOGIC_OUTS_B5_R_5", - "PCIE_LOGIC_OUTS_B5_R_6", - "PCIE_LOGIC_OUTS_B5_R_7", - "PCIE_LOGIC_OUTS_B5_R_8", - "PCIE_LOGIC_OUTS_B5_R_9", - "PCIE_LOGIC_OUTS_B6_L_0", - "PCIE_LOGIC_OUTS_B6_L_1", - "PCIE_LOGIC_OUTS_B6_L_10", - "PCIE_LOGIC_OUTS_B6_L_11", - "PCIE_LOGIC_OUTS_B6_L_12", - "PCIE_LOGIC_OUTS_B6_L_13", - "PCIE_LOGIC_OUTS_B6_L_14", - "PCIE_LOGIC_OUTS_B6_L_15", - "PCIE_LOGIC_OUTS_B6_L_16", - "PCIE_LOGIC_OUTS_B6_L_17", - "PCIE_LOGIC_OUTS_B6_L_18", - "PCIE_LOGIC_OUTS_B6_L_19", - "PCIE_LOGIC_OUTS_B6_L_2", - "PCIE_LOGIC_OUTS_B6_L_3", - "PCIE_LOGIC_OUTS_B6_L_4", - "PCIE_LOGIC_OUTS_B6_L_5", - "PCIE_LOGIC_OUTS_B6_L_6", - "PCIE_LOGIC_OUTS_B6_L_7", - "PCIE_LOGIC_OUTS_B6_L_8", - "PCIE_LOGIC_OUTS_B6_L_9", - "PCIE_LOGIC_OUTS_B6_R_0", - "PCIE_LOGIC_OUTS_B6_R_1", - "PCIE_LOGIC_OUTS_B6_R_10", - "PCIE_LOGIC_OUTS_B6_R_11", - "PCIE_LOGIC_OUTS_B6_R_12", - "PCIE_LOGIC_OUTS_B6_R_13", - "PCIE_LOGIC_OUTS_B6_R_14", - "PCIE_LOGIC_OUTS_B6_R_15", - "PCIE_LOGIC_OUTS_B6_R_16", - "PCIE_LOGIC_OUTS_B6_R_17", - "PCIE_LOGIC_OUTS_B6_R_18", - "PCIE_LOGIC_OUTS_B6_R_19", - "PCIE_LOGIC_OUTS_B6_R_2", - "PCIE_LOGIC_OUTS_B6_R_3", - "PCIE_LOGIC_OUTS_B6_R_4", - "PCIE_LOGIC_OUTS_B6_R_5", - "PCIE_LOGIC_OUTS_B6_R_6", - "PCIE_LOGIC_OUTS_B6_R_7", - "PCIE_LOGIC_OUTS_B6_R_8", - "PCIE_LOGIC_OUTS_B6_R_9", - "PCIE_LOGIC_OUTS_B7_L_0", - "PCIE_LOGIC_OUTS_B7_L_1", - "PCIE_LOGIC_OUTS_B7_L_10", - "PCIE_LOGIC_OUTS_B7_L_11", - "PCIE_LOGIC_OUTS_B7_L_12", - "PCIE_LOGIC_OUTS_B7_L_13", - "PCIE_LOGIC_OUTS_B7_L_14", - "PCIE_LOGIC_OUTS_B7_L_15", - "PCIE_LOGIC_OUTS_B7_L_16", - "PCIE_LOGIC_OUTS_B7_L_17", - "PCIE_LOGIC_OUTS_B7_L_18", - "PCIE_LOGIC_OUTS_B7_L_19", - "PCIE_LOGIC_OUTS_B7_L_2", - "PCIE_LOGIC_OUTS_B7_L_3", - "PCIE_LOGIC_OUTS_B7_L_4", - "PCIE_LOGIC_OUTS_B7_L_5", - "PCIE_LOGIC_OUTS_B7_L_6", - "PCIE_LOGIC_OUTS_B7_L_7", - "PCIE_LOGIC_OUTS_B7_L_8", - "PCIE_LOGIC_OUTS_B7_L_9", - "PCIE_LOGIC_OUTS_B7_R_0", - "PCIE_LOGIC_OUTS_B7_R_1", - "PCIE_LOGIC_OUTS_B7_R_10", - "PCIE_LOGIC_OUTS_B7_R_11", - "PCIE_LOGIC_OUTS_B7_R_12", - "PCIE_LOGIC_OUTS_B7_R_13", - "PCIE_LOGIC_OUTS_B7_R_14", - "PCIE_LOGIC_OUTS_B7_R_15", - "PCIE_LOGIC_OUTS_B7_R_16", - "PCIE_LOGIC_OUTS_B7_R_17", - "PCIE_LOGIC_OUTS_B7_R_18", - "PCIE_LOGIC_OUTS_B7_R_19", - "PCIE_LOGIC_OUTS_B7_R_2", - "PCIE_LOGIC_OUTS_B7_R_3", - "PCIE_LOGIC_OUTS_B7_R_4", - "PCIE_LOGIC_OUTS_B7_R_5", - "PCIE_LOGIC_OUTS_B7_R_6", - "PCIE_LOGIC_OUTS_B7_R_7", - "PCIE_LOGIC_OUTS_B7_R_8", - "PCIE_LOGIC_OUTS_B7_R_9", - "PCIE_LOGIC_OUTS_B8_L_0", - "PCIE_LOGIC_OUTS_B8_L_1", - "PCIE_LOGIC_OUTS_B8_L_10", - "PCIE_LOGIC_OUTS_B8_L_11", - "PCIE_LOGIC_OUTS_B8_L_12", - "PCIE_LOGIC_OUTS_B8_L_13", - "PCIE_LOGIC_OUTS_B8_L_14", - "PCIE_LOGIC_OUTS_B8_L_15", - "PCIE_LOGIC_OUTS_B8_L_16", - "PCIE_LOGIC_OUTS_B8_L_17", - "PCIE_LOGIC_OUTS_B8_L_18", - "PCIE_LOGIC_OUTS_B8_L_19", - "PCIE_LOGIC_OUTS_B8_L_2", - "PCIE_LOGIC_OUTS_B8_L_3", - "PCIE_LOGIC_OUTS_B8_L_4", - "PCIE_LOGIC_OUTS_B8_L_5", - "PCIE_LOGIC_OUTS_B8_L_6", - "PCIE_LOGIC_OUTS_B8_L_7", - "PCIE_LOGIC_OUTS_B8_L_8", - "PCIE_LOGIC_OUTS_B8_L_9", - "PCIE_LOGIC_OUTS_B8_R_0", - "PCIE_LOGIC_OUTS_B8_R_1", - "PCIE_LOGIC_OUTS_B8_R_10", - "PCIE_LOGIC_OUTS_B8_R_11", - "PCIE_LOGIC_OUTS_B8_R_12", - "PCIE_LOGIC_OUTS_B8_R_13", - "PCIE_LOGIC_OUTS_B8_R_14", - "PCIE_LOGIC_OUTS_B8_R_15", - "PCIE_LOGIC_OUTS_B8_R_16", - "PCIE_LOGIC_OUTS_B8_R_17", - "PCIE_LOGIC_OUTS_B8_R_18", - "PCIE_LOGIC_OUTS_B8_R_19", - "PCIE_LOGIC_OUTS_B8_R_2", - "PCIE_LOGIC_OUTS_B8_R_3", - "PCIE_LOGIC_OUTS_B8_R_4", - "PCIE_LOGIC_OUTS_B8_R_5", - "PCIE_LOGIC_OUTS_B8_R_6", - "PCIE_LOGIC_OUTS_B8_R_7", - "PCIE_LOGIC_OUTS_B8_R_8", - "PCIE_LOGIC_OUTS_B8_R_9", - "PCIE_LOGIC_OUTS_B9_L_0", - "PCIE_LOGIC_OUTS_B9_L_1", - "PCIE_LOGIC_OUTS_B9_L_10", - "PCIE_LOGIC_OUTS_B9_L_11", - "PCIE_LOGIC_OUTS_B9_L_12", - "PCIE_LOGIC_OUTS_B9_L_13", - "PCIE_LOGIC_OUTS_B9_L_14", - "PCIE_LOGIC_OUTS_B9_L_15", - "PCIE_LOGIC_OUTS_B9_L_16", - "PCIE_LOGIC_OUTS_B9_L_17", - "PCIE_LOGIC_OUTS_B9_L_18", - "PCIE_LOGIC_OUTS_B9_L_19", - "PCIE_LOGIC_OUTS_B9_L_2", - "PCIE_LOGIC_OUTS_B9_L_3", - "PCIE_LOGIC_OUTS_B9_L_4", - "PCIE_LOGIC_OUTS_B9_L_5", - "PCIE_LOGIC_OUTS_B9_L_6", - "PCIE_LOGIC_OUTS_B9_L_7", - "PCIE_LOGIC_OUTS_B9_L_8", - "PCIE_LOGIC_OUTS_B9_L_9", - "PCIE_LOGIC_OUTS_B9_R_0", - "PCIE_LOGIC_OUTS_B9_R_1", - "PCIE_LOGIC_OUTS_B9_R_10", - "PCIE_LOGIC_OUTS_B9_R_11", - "PCIE_LOGIC_OUTS_B9_R_12", - "PCIE_LOGIC_OUTS_B9_R_13", - "PCIE_LOGIC_OUTS_B9_R_14", - "PCIE_LOGIC_OUTS_B9_R_15", - "PCIE_LOGIC_OUTS_B9_R_16", - "PCIE_LOGIC_OUTS_B9_R_17", - "PCIE_LOGIC_OUTS_B9_R_18", - "PCIE_LOGIC_OUTS_B9_R_19", - "PCIE_LOGIC_OUTS_B9_R_2", - "PCIE_LOGIC_OUTS_B9_R_3", - "PCIE_LOGIC_OUTS_B9_R_4", - "PCIE_LOGIC_OUTS_B9_R_5", - "PCIE_LOGIC_OUTS_B9_R_6", - "PCIE_LOGIC_OUTS_B9_R_7", - "PCIE_LOGIC_OUTS_B9_R_8", - "PCIE_LOGIC_OUTS_B9_R_9", - "PCIE_MIMRXRADDR0", - "PCIE_MIMRXRADDR1", - "PCIE_MIMRXRADDR10", - "PCIE_MIMRXRADDR11", - "PCIE_MIMRXRADDR12", - "PCIE_MIMRXRADDR2", - "PCIE_MIMRXRADDR3", - "PCIE_MIMRXRADDR4", - "PCIE_MIMRXRADDR5", - "PCIE_MIMRXRADDR6", - "PCIE_MIMRXRADDR7", - "PCIE_MIMRXRADDR8", - "PCIE_MIMRXRADDR9", - "PCIE_MIMRXRDATA0", - "PCIE_MIMRXRDATA1", - "PCIE_MIMRXRDATA10", - "PCIE_MIMRXRDATA11", - "PCIE_MIMRXRDATA12", - "PCIE_MIMRXRDATA13", - "PCIE_MIMRXRDATA14", - "PCIE_MIMRXRDATA15", - "PCIE_MIMRXRDATA16", - "PCIE_MIMRXRDATA17", - "PCIE_MIMRXRDATA18", - "PCIE_MIMRXRDATA19", - "PCIE_MIMRXRDATA2", - "PCIE_MIMRXRDATA20", - "PCIE_MIMRXRDATA21", - "PCIE_MIMRXRDATA22", - "PCIE_MIMRXRDATA23", - "PCIE_MIMRXRDATA24", - "PCIE_MIMRXRDATA25", - "PCIE_MIMRXRDATA26", - "PCIE_MIMRXRDATA27", - "PCIE_MIMRXRDATA28", - "PCIE_MIMRXRDATA29", - "PCIE_MIMRXRDATA3", - "PCIE_MIMRXRDATA30", - "PCIE_MIMRXRDATA31", - "PCIE_MIMRXRDATA32", - "PCIE_MIMRXRDATA33", - "PCIE_MIMRXRDATA34", - "PCIE_MIMRXRDATA35", - "PCIE_MIMRXRDATA36", - "PCIE_MIMRXRDATA37", - "PCIE_MIMRXRDATA38", - "PCIE_MIMRXRDATA39", - "PCIE_MIMRXRDATA4", - "PCIE_MIMRXRDATA40", - "PCIE_MIMRXRDATA41", - "PCIE_MIMRXRDATA42", - "PCIE_MIMRXRDATA43", - "PCIE_MIMRXRDATA44", - "PCIE_MIMRXRDATA45", - "PCIE_MIMRXRDATA46", - "PCIE_MIMRXRDATA47", - "PCIE_MIMRXRDATA48", - "PCIE_MIMRXRDATA49", - "PCIE_MIMRXRDATA5", - "PCIE_MIMRXRDATA50", - "PCIE_MIMRXRDATA51", - "PCIE_MIMRXRDATA52", - "PCIE_MIMRXRDATA53", - "PCIE_MIMRXRDATA54", - "PCIE_MIMRXRDATA55", - "PCIE_MIMRXRDATA56", - "PCIE_MIMRXRDATA57", - "PCIE_MIMRXRDATA58", - "PCIE_MIMRXRDATA59", - "PCIE_MIMRXRDATA6", - "PCIE_MIMRXRDATA60", - "PCIE_MIMRXRDATA61", - "PCIE_MIMRXRDATA62", - "PCIE_MIMRXRDATA63", - "PCIE_MIMRXRDATA64", - "PCIE_MIMRXRDATA65", - "PCIE_MIMRXRDATA66", - "PCIE_MIMRXRDATA67", - "PCIE_MIMRXRDATA7", - "PCIE_MIMRXRDATA8", - "PCIE_MIMRXRDATA9", - "PCIE_MIMRXREN", - "PCIE_MIMRXWADDR0", - "PCIE_MIMRXWADDR1", - "PCIE_MIMRXWADDR10", - "PCIE_MIMRXWADDR11", - "PCIE_MIMRXWADDR12", - "PCIE_MIMRXWADDR2", - "PCIE_MIMRXWADDR3", - "PCIE_MIMRXWADDR4", - "PCIE_MIMRXWADDR5", - "PCIE_MIMRXWADDR6", - "PCIE_MIMRXWADDR7", - "PCIE_MIMRXWADDR8", - "PCIE_MIMRXWADDR9", - "PCIE_MIMRXWDATA0", - "PCIE_MIMRXWDATA1", - "PCIE_MIMRXWDATA10", - "PCIE_MIMRXWDATA11", - "PCIE_MIMRXWDATA12", - "PCIE_MIMRXWDATA13", - "PCIE_MIMRXWDATA14", - "PCIE_MIMRXWDATA15", - "PCIE_MIMRXWDATA16", - "PCIE_MIMRXWDATA17", - "PCIE_MIMRXWDATA18", - "PCIE_MIMRXWDATA19", - "PCIE_MIMRXWDATA2", - "PCIE_MIMRXWDATA20", - "PCIE_MIMRXWDATA21", - "PCIE_MIMRXWDATA22", - "PCIE_MIMRXWDATA23", - "PCIE_MIMRXWDATA24", - "PCIE_MIMRXWDATA25", - "PCIE_MIMRXWDATA26", - "PCIE_MIMRXWDATA27", - "PCIE_MIMRXWDATA28", - "PCIE_MIMRXWDATA29", - "PCIE_MIMRXWDATA3", - "PCIE_MIMRXWDATA30", - "PCIE_MIMRXWDATA31", - "PCIE_MIMRXWDATA32", - "PCIE_MIMRXWDATA33", - "PCIE_MIMRXWDATA34", - "PCIE_MIMRXWDATA35", - "PCIE_MIMRXWDATA36", - "PCIE_MIMRXWDATA37", - "PCIE_MIMRXWDATA38", - "PCIE_MIMRXWDATA39", - "PCIE_MIMRXWDATA4", - "PCIE_MIMRXWDATA40", - "PCIE_MIMRXWDATA41", - "PCIE_MIMRXWDATA42", - "PCIE_MIMRXWDATA43", - "PCIE_MIMRXWDATA44", - "PCIE_MIMRXWDATA45", - "PCIE_MIMRXWDATA46", - "PCIE_MIMRXWDATA47", - "PCIE_MIMRXWDATA48", - "PCIE_MIMRXWDATA49", - "PCIE_MIMRXWDATA5", - "PCIE_MIMRXWDATA50", - "PCIE_MIMRXWDATA51", - "PCIE_MIMRXWDATA52", - "PCIE_MIMRXWDATA53", - "PCIE_MIMRXWDATA54", - "PCIE_MIMRXWDATA55", - "PCIE_MIMRXWDATA56", - "PCIE_MIMRXWDATA57", - "PCIE_MIMRXWDATA58", - "PCIE_MIMRXWDATA59", - "PCIE_MIMRXWDATA6", - "PCIE_MIMRXWDATA60", - "PCIE_MIMRXWDATA61", - "PCIE_MIMRXWDATA62", - "PCIE_MIMRXWDATA63", - "PCIE_MIMRXWDATA64", - "PCIE_MIMRXWDATA65", - "PCIE_MIMRXWDATA66", - "PCIE_MIMRXWDATA67", - "PCIE_MIMRXWDATA7", - "PCIE_MIMRXWDATA8", - "PCIE_MIMRXWDATA9", - "PCIE_MIMRXWEN", - "PCIE_MIMTXRADDR0", - "PCIE_MIMTXRADDR1", - "PCIE_MIMTXRADDR10", - "PCIE_MIMTXRADDR11", - "PCIE_MIMTXRADDR12", - "PCIE_MIMTXRADDR2", - "PCIE_MIMTXRADDR3", - "PCIE_MIMTXRADDR4", - "PCIE_MIMTXRADDR5", - "PCIE_MIMTXRADDR6", - "PCIE_MIMTXRADDR7", - "PCIE_MIMTXRADDR8", - "PCIE_MIMTXRADDR9", - "PCIE_MIMTXRDATA0", - "PCIE_MIMTXRDATA1", - "PCIE_MIMTXRDATA10", - "PCIE_MIMTXRDATA11", - "PCIE_MIMTXRDATA12", - "PCIE_MIMTXRDATA13", - "PCIE_MIMTXRDATA14", - "PCIE_MIMTXRDATA15", - "PCIE_MIMTXRDATA16", - "PCIE_MIMTXRDATA17", - "PCIE_MIMTXRDATA18", - "PCIE_MIMTXRDATA19", - "PCIE_MIMTXRDATA2", - "PCIE_MIMTXRDATA20", - "PCIE_MIMTXRDATA21", - "PCIE_MIMTXRDATA22", - "PCIE_MIMTXRDATA23", - "PCIE_MIMTXRDATA24", - "PCIE_MIMTXRDATA25", - "PCIE_MIMTXRDATA26", - "PCIE_MIMTXRDATA27", - "PCIE_MIMTXRDATA28", - "PCIE_MIMTXRDATA29", - "PCIE_MIMTXRDATA3", - "PCIE_MIMTXRDATA30", - "PCIE_MIMTXRDATA31", - "PCIE_MIMTXRDATA32", - "PCIE_MIMTXRDATA33", - "PCIE_MIMTXRDATA34", - "PCIE_MIMTXRDATA35", - "PCIE_MIMTXRDATA36", - "PCIE_MIMTXRDATA37", - "PCIE_MIMTXRDATA38", - "PCIE_MIMTXRDATA39", - "PCIE_MIMTXRDATA4", - "PCIE_MIMTXRDATA40", - "PCIE_MIMTXRDATA41", - "PCIE_MIMTXRDATA42", - "PCIE_MIMTXRDATA43", - "PCIE_MIMTXRDATA44", - "PCIE_MIMTXRDATA45", - "PCIE_MIMTXRDATA46", - "PCIE_MIMTXRDATA47", - "PCIE_MIMTXRDATA48", - "PCIE_MIMTXRDATA49", - "PCIE_MIMTXRDATA5", - "PCIE_MIMTXRDATA50", - "PCIE_MIMTXRDATA51", - "PCIE_MIMTXRDATA52", - "PCIE_MIMTXRDATA53", - "PCIE_MIMTXRDATA54", - "PCIE_MIMTXRDATA55", - "PCIE_MIMTXRDATA56", - "PCIE_MIMTXRDATA57", - "PCIE_MIMTXRDATA58", - "PCIE_MIMTXRDATA59", - "PCIE_MIMTXRDATA6", - "PCIE_MIMTXRDATA60", - "PCIE_MIMTXRDATA61", - "PCIE_MIMTXRDATA62", - "PCIE_MIMTXRDATA63", - "PCIE_MIMTXRDATA64", - "PCIE_MIMTXRDATA65", - "PCIE_MIMTXRDATA66", - "PCIE_MIMTXRDATA67", - "PCIE_MIMTXRDATA68", - "PCIE_MIMTXRDATA7", - "PCIE_MIMTXRDATA8", - "PCIE_MIMTXRDATA9", - "PCIE_MIMTXREN", - "PCIE_MIMTXWADDR0", - "PCIE_MIMTXWADDR1", - "PCIE_MIMTXWADDR10", - "PCIE_MIMTXWADDR11", - "PCIE_MIMTXWADDR12", - "PCIE_MIMTXWADDR2", - "PCIE_MIMTXWADDR3", - "PCIE_MIMTXWADDR4", - "PCIE_MIMTXWADDR5", - "PCIE_MIMTXWADDR6", - "PCIE_MIMTXWADDR7", - "PCIE_MIMTXWADDR8", - "PCIE_MIMTXWADDR9", - "PCIE_MIMTXWDATA0", - "PCIE_MIMTXWDATA1", - "PCIE_MIMTXWDATA10", - "PCIE_MIMTXWDATA11", - "PCIE_MIMTXWDATA12", - "PCIE_MIMTXWDATA13", - "PCIE_MIMTXWDATA14", - "PCIE_MIMTXWDATA15", - "PCIE_MIMTXWDATA16", - "PCIE_MIMTXWDATA17", - "PCIE_MIMTXWDATA18", - "PCIE_MIMTXWDATA19", - "PCIE_MIMTXWDATA2", - "PCIE_MIMTXWDATA20", - "PCIE_MIMTXWDATA21", - "PCIE_MIMTXWDATA22", - "PCIE_MIMTXWDATA23", - "PCIE_MIMTXWDATA24", - "PCIE_MIMTXWDATA25", - "PCIE_MIMTXWDATA26", - "PCIE_MIMTXWDATA27", - "PCIE_MIMTXWDATA28", - "PCIE_MIMTXWDATA29", - "PCIE_MIMTXWDATA3", - "PCIE_MIMTXWDATA30", - "PCIE_MIMTXWDATA31", - "PCIE_MIMTXWDATA32", - "PCIE_MIMTXWDATA33", - "PCIE_MIMTXWDATA34", - "PCIE_MIMTXWDATA35", - "PCIE_MIMTXWDATA36", - "PCIE_MIMTXWDATA37", - "PCIE_MIMTXWDATA38", - "PCIE_MIMTXWDATA39", - "PCIE_MIMTXWDATA4", - "PCIE_MIMTXWDATA40", - "PCIE_MIMTXWDATA41", - "PCIE_MIMTXWDATA42", - "PCIE_MIMTXWDATA43", - "PCIE_MIMTXWDATA44", - "PCIE_MIMTXWDATA45", - "PCIE_MIMTXWDATA46", - "PCIE_MIMTXWDATA47", - "PCIE_MIMTXWDATA48", - "PCIE_MIMTXWDATA49", - "PCIE_MIMTXWDATA5", - "PCIE_MIMTXWDATA50", - "PCIE_MIMTXWDATA51", - "PCIE_MIMTXWDATA52", - "PCIE_MIMTXWDATA53", - "PCIE_MIMTXWDATA54", - "PCIE_MIMTXWDATA55", - "PCIE_MIMTXWDATA56", - "PCIE_MIMTXWDATA57", - "PCIE_MIMTXWDATA58", - "PCIE_MIMTXWDATA59", - "PCIE_MIMTXWDATA6", - "PCIE_MIMTXWDATA60", - "PCIE_MIMTXWDATA61", - "PCIE_MIMTXWDATA62", - "PCIE_MIMTXWDATA63", - "PCIE_MIMTXWDATA64", - "PCIE_MIMTXWDATA65", - "PCIE_MIMTXWDATA66", - "PCIE_MIMTXWDATA67", - "PCIE_MIMTXWDATA68", - "PCIE_MIMTXWDATA7", - "PCIE_MIMTXWDATA8", - "PCIE_MIMTXWDATA9", - "PCIE_MIMTXWEN", - "PCIE_MONITOR_N_0", - "PCIE_MONITOR_N_1", - "PCIE_MONITOR_N_10", - "PCIE_MONITOR_N_11", - "PCIE_MONITOR_N_12", - "PCIE_MONITOR_N_13", - "PCIE_MONITOR_N_14", - "PCIE_MONITOR_N_15", - "PCIE_MONITOR_N_16", - "PCIE_MONITOR_N_17", - "PCIE_MONITOR_N_18", - "PCIE_MONITOR_N_19", - "PCIE_MONITOR_N_2", - "PCIE_MONITOR_N_3", - "PCIE_MONITOR_N_4", - "PCIE_MONITOR_N_5", - "PCIE_MONITOR_N_6", - "PCIE_MONITOR_N_7", - "PCIE_MONITOR_N_8", - "PCIE_MONITOR_N_9", - "PCIE_MONITOR_P_0", - "PCIE_MONITOR_P_1", - "PCIE_MONITOR_P_10", - "PCIE_MONITOR_P_11", - "PCIE_MONITOR_P_12", - "PCIE_MONITOR_P_13", - "PCIE_MONITOR_P_14", - "PCIE_MONITOR_P_15", - "PCIE_MONITOR_P_16", - "PCIE_MONITOR_P_17", - "PCIE_MONITOR_P_18", - "PCIE_MONITOR_P_19", - "PCIE_MONITOR_P_2", - "PCIE_MONITOR_P_3", - "PCIE_MONITOR_P_4", - "PCIE_MONITOR_P_5", - "PCIE_MONITOR_P_6", - "PCIE_MONITOR_P_7", - "PCIE_MONITOR_P_8", - "PCIE_MONITOR_P_9", - "PCIE_NE2A0_0", - "PCIE_NE2A0_1", - "PCIE_NE2A0_10", - "PCIE_NE2A0_11", - "PCIE_NE2A0_12", - "PCIE_NE2A0_13", - "PCIE_NE2A0_14", - "PCIE_NE2A0_15", - "PCIE_NE2A0_16", - "PCIE_NE2A0_17", - "PCIE_NE2A0_18", - "PCIE_NE2A0_19", - "PCIE_NE2A0_2", - "PCIE_NE2A0_3", - "PCIE_NE2A0_4", - "PCIE_NE2A0_5", - "PCIE_NE2A0_6", - "PCIE_NE2A0_7", - "PCIE_NE2A0_8", - "PCIE_NE2A0_9", - "PCIE_NE2A1_0", - "PCIE_NE2A1_1", - "PCIE_NE2A1_10", - "PCIE_NE2A1_11", - "PCIE_NE2A1_12", - "PCIE_NE2A1_13", - "PCIE_NE2A1_14", - "PCIE_NE2A1_15", - "PCIE_NE2A1_16", - "PCIE_NE2A1_17", - "PCIE_NE2A1_18", - "PCIE_NE2A1_19", - "PCIE_NE2A1_2", - "PCIE_NE2A1_3", - "PCIE_NE2A1_4", - "PCIE_NE2A1_5", - "PCIE_NE2A1_6", - "PCIE_NE2A1_7", - "PCIE_NE2A1_8", - "PCIE_NE2A1_9", - "PCIE_NE2A2_0", - "PCIE_NE2A2_1", - "PCIE_NE2A2_10", - "PCIE_NE2A2_11", - "PCIE_NE2A2_12", - "PCIE_NE2A2_13", - "PCIE_NE2A2_14", - "PCIE_NE2A2_15", - "PCIE_NE2A2_16", - "PCIE_NE2A2_17", - "PCIE_NE2A2_18", - "PCIE_NE2A2_19", - "PCIE_NE2A2_2", - "PCIE_NE2A2_3", - "PCIE_NE2A2_4", - "PCIE_NE2A2_5", - "PCIE_NE2A2_6", - "PCIE_NE2A2_7", - "PCIE_NE2A2_8", - "PCIE_NE2A2_9", - "PCIE_NE2A3_0", - "PCIE_NE2A3_1", - "PCIE_NE2A3_10", - "PCIE_NE2A3_11", - "PCIE_NE2A3_12", - "PCIE_NE2A3_13", - "PCIE_NE2A3_14", - "PCIE_NE2A3_15", - "PCIE_NE2A3_16", - "PCIE_NE2A3_17", - "PCIE_NE2A3_18", - "PCIE_NE2A3_19", - "PCIE_NE2A3_2", - "PCIE_NE2A3_3", - "PCIE_NE2A3_4", - "PCIE_NE2A3_5", - "PCIE_NE2A3_6", - "PCIE_NE2A3_7", - "PCIE_NE2A3_8", - "PCIE_NE2A3_9", - "PCIE_NE4BEG0_0", - "PCIE_NE4BEG0_1", - "PCIE_NE4BEG0_10", - "PCIE_NE4BEG0_11", - "PCIE_NE4BEG0_12", - "PCIE_NE4BEG0_13", - "PCIE_NE4BEG0_14", - "PCIE_NE4BEG0_15", - "PCIE_NE4BEG0_16", - "PCIE_NE4BEG0_17", - "PCIE_NE4BEG0_18", - "PCIE_NE4BEG0_19", - "PCIE_NE4BEG0_2", - "PCIE_NE4BEG0_3", - "PCIE_NE4BEG0_4", - "PCIE_NE4BEG0_5", - "PCIE_NE4BEG0_6", - "PCIE_NE4BEG0_7", - "PCIE_NE4BEG0_8", - "PCIE_NE4BEG0_9", - "PCIE_NE4BEG1_0", - "PCIE_NE4BEG1_1", - "PCIE_NE4BEG1_10", - "PCIE_NE4BEG1_11", - "PCIE_NE4BEG1_12", - "PCIE_NE4BEG1_13", - "PCIE_NE4BEG1_14", - "PCIE_NE4BEG1_15", - "PCIE_NE4BEG1_16", - "PCIE_NE4BEG1_17", - "PCIE_NE4BEG1_18", - "PCIE_NE4BEG1_19", - "PCIE_NE4BEG1_2", - "PCIE_NE4BEG1_3", - "PCIE_NE4BEG1_4", - "PCIE_NE4BEG1_5", - "PCIE_NE4BEG1_6", - "PCIE_NE4BEG1_7", - "PCIE_NE4BEG1_8", - "PCIE_NE4BEG1_9", - "PCIE_NE4BEG2_0", - "PCIE_NE4BEG2_1", - "PCIE_NE4BEG2_10", - "PCIE_NE4BEG2_11", - "PCIE_NE4BEG2_12", - "PCIE_NE4BEG2_13", - "PCIE_NE4BEG2_14", - "PCIE_NE4BEG2_15", - "PCIE_NE4BEG2_16", - "PCIE_NE4BEG2_17", - "PCIE_NE4BEG2_18", - "PCIE_NE4BEG2_19", - "PCIE_NE4BEG2_2", - "PCIE_NE4BEG2_3", - "PCIE_NE4BEG2_4", - "PCIE_NE4BEG2_5", - "PCIE_NE4BEG2_6", - "PCIE_NE4BEG2_7", - "PCIE_NE4BEG2_8", - "PCIE_NE4BEG2_9", - "PCIE_NE4BEG3_0", - "PCIE_NE4BEG3_1", - "PCIE_NE4BEG3_10", - "PCIE_NE4BEG3_11", - "PCIE_NE4BEG3_12", - "PCIE_NE4BEG3_13", - "PCIE_NE4BEG3_14", - "PCIE_NE4BEG3_15", - "PCIE_NE4BEG3_16", - "PCIE_NE4BEG3_17", - "PCIE_NE4BEG3_18", - "PCIE_NE4BEG3_19", - "PCIE_NE4BEG3_2", - "PCIE_NE4BEG3_3", - "PCIE_NE4BEG3_4", - "PCIE_NE4BEG3_5", - "PCIE_NE4BEG3_6", - "PCIE_NE4BEG3_7", - "PCIE_NE4BEG3_8", - "PCIE_NE4BEG3_9", - "PCIE_NE4C0_0", - "PCIE_NE4C0_1", - "PCIE_NE4C0_10", - "PCIE_NE4C0_11", - "PCIE_NE4C0_12", - "PCIE_NE4C0_13", - "PCIE_NE4C0_14", - "PCIE_NE4C0_15", - "PCIE_NE4C0_16", - "PCIE_NE4C0_17", - "PCIE_NE4C0_18", - "PCIE_NE4C0_19", - "PCIE_NE4C0_2", - "PCIE_NE4C0_3", - "PCIE_NE4C0_4", - "PCIE_NE4C0_5", - "PCIE_NE4C0_6", - "PCIE_NE4C0_7", - "PCIE_NE4C0_8", - "PCIE_NE4C0_9", - "PCIE_NE4C1_0", - "PCIE_NE4C1_1", - "PCIE_NE4C1_10", - "PCIE_NE4C1_11", - "PCIE_NE4C1_12", - "PCIE_NE4C1_13", - "PCIE_NE4C1_14", - "PCIE_NE4C1_15", - "PCIE_NE4C1_16", - "PCIE_NE4C1_17", - "PCIE_NE4C1_18", - "PCIE_NE4C1_19", - "PCIE_NE4C1_2", - "PCIE_NE4C1_3", - "PCIE_NE4C1_4", - "PCIE_NE4C1_5", - "PCIE_NE4C1_6", - "PCIE_NE4C1_7", - "PCIE_NE4C1_8", - "PCIE_NE4C1_9", - "PCIE_NE4C2_0", - "PCIE_NE4C2_1", - "PCIE_NE4C2_10", - "PCIE_NE4C2_11", - "PCIE_NE4C2_12", - "PCIE_NE4C2_13", - "PCIE_NE4C2_14", - "PCIE_NE4C2_15", - "PCIE_NE4C2_16", - "PCIE_NE4C2_17", - "PCIE_NE4C2_18", - "PCIE_NE4C2_19", - "PCIE_NE4C2_2", - "PCIE_NE4C2_3", - "PCIE_NE4C2_4", - "PCIE_NE4C2_5", - "PCIE_NE4C2_6", - "PCIE_NE4C2_7", - "PCIE_NE4C2_8", - "PCIE_NE4C2_9", - "PCIE_NE4C3_0", - "PCIE_NE4C3_1", - "PCIE_NE4C3_10", - "PCIE_NE4C3_11", - "PCIE_NE4C3_12", - "PCIE_NE4C3_13", - "PCIE_NE4C3_14", - "PCIE_NE4C3_15", - "PCIE_NE4C3_16", - "PCIE_NE4C3_17", - "PCIE_NE4C3_18", - "PCIE_NE4C3_19", - "PCIE_NE4C3_2", - "PCIE_NE4C3_3", - "PCIE_NE4C3_4", - "PCIE_NE4C3_5", - "PCIE_NE4C3_6", - "PCIE_NE4C3_7", - "PCIE_NE4C3_8", - "PCIE_NE4C3_9", - "PCIE_NW2A0_0", - "PCIE_NW2A0_1", - "PCIE_NW2A0_10", - "PCIE_NW2A0_11", - "PCIE_NW2A0_12", - "PCIE_NW2A0_13", - "PCIE_NW2A0_14", - "PCIE_NW2A0_15", - "PCIE_NW2A0_16", - "PCIE_NW2A0_17", - "PCIE_NW2A0_18", - "PCIE_NW2A0_19", - "PCIE_NW2A0_2", - "PCIE_NW2A0_3", - "PCIE_NW2A0_4", - "PCIE_NW2A0_5", - "PCIE_NW2A0_6", - "PCIE_NW2A0_7", - "PCIE_NW2A0_8", - "PCIE_NW2A0_9", - "PCIE_NW2A1_0", - "PCIE_NW2A1_1", - "PCIE_NW2A1_10", - "PCIE_NW2A1_11", - "PCIE_NW2A1_12", - "PCIE_NW2A1_13", - "PCIE_NW2A1_14", - "PCIE_NW2A1_15", - "PCIE_NW2A1_16", - "PCIE_NW2A1_17", - "PCIE_NW2A1_18", - "PCIE_NW2A1_19", - "PCIE_NW2A1_2", - "PCIE_NW2A1_3", - "PCIE_NW2A1_4", - "PCIE_NW2A1_5", - "PCIE_NW2A1_6", - "PCIE_NW2A1_7", - "PCIE_NW2A1_8", - "PCIE_NW2A1_9", - "PCIE_NW2A2_0", - "PCIE_NW2A2_1", - "PCIE_NW2A2_10", - "PCIE_NW2A2_11", - "PCIE_NW2A2_12", - "PCIE_NW2A2_13", - "PCIE_NW2A2_14", - "PCIE_NW2A2_15", - "PCIE_NW2A2_16", - "PCIE_NW2A2_17", - "PCIE_NW2A2_18", - "PCIE_NW2A2_19", - "PCIE_NW2A2_2", - "PCIE_NW2A2_3", - "PCIE_NW2A2_4", - "PCIE_NW2A2_5", - "PCIE_NW2A2_6", - "PCIE_NW2A2_7", - "PCIE_NW2A2_8", - "PCIE_NW2A2_9", - "PCIE_NW2A3_0", - "PCIE_NW2A3_1", - "PCIE_NW2A3_10", - "PCIE_NW2A3_11", - "PCIE_NW2A3_12", - "PCIE_NW2A3_13", - "PCIE_NW2A3_14", - "PCIE_NW2A3_15", - "PCIE_NW2A3_16", - "PCIE_NW2A3_17", - "PCIE_NW2A3_18", - "PCIE_NW2A3_19", - "PCIE_NW2A3_2", - "PCIE_NW2A3_3", - "PCIE_NW2A3_4", - "PCIE_NW2A3_5", - "PCIE_NW2A3_6", - "PCIE_NW2A3_7", - "PCIE_NW2A3_8", - "PCIE_NW2A3_9", - "PCIE_NW4A0_0", - "PCIE_NW4A0_1", - "PCIE_NW4A0_10", - "PCIE_NW4A0_11", - "PCIE_NW4A0_12", - "PCIE_NW4A0_13", - "PCIE_NW4A0_14", - "PCIE_NW4A0_15", - "PCIE_NW4A0_16", - "PCIE_NW4A0_17", - "PCIE_NW4A0_18", - "PCIE_NW4A0_19", - "PCIE_NW4A0_2", - "PCIE_NW4A0_3", - "PCIE_NW4A0_4", - "PCIE_NW4A0_5", - "PCIE_NW4A0_6", - "PCIE_NW4A0_7", - "PCIE_NW4A0_8", - "PCIE_NW4A0_9", - "PCIE_NW4A1_0", - "PCIE_NW4A1_1", - "PCIE_NW4A1_10", - "PCIE_NW4A1_11", - "PCIE_NW4A1_12", - "PCIE_NW4A1_13", - "PCIE_NW4A1_14", - "PCIE_NW4A1_15", - "PCIE_NW4A1_16", - "PCIE_NW4A1_17", - "PCIE_NW4A1_18", - "PCIE_NW4A1_19", - "PCIE_NW4A1_2", - "PCIE_NW4A1_3", - "PCIE_NW4A1_4", - "PCIE_NW4A1_5", - "PCIE_NW4A1_6", - "PCIE_NW4A1_7", - "PCIE_NW4A1_8", - "PCIE_NW4A1_9", - "PCIE_NW4A2_0", - "PCIE_NW4A2_1", - "PCIE_NW4A2_10", - "PCIE_NW4A2_11", - "PCIE_NW4A2_12", - "PCIE_NW4A2_13", - "PCIE_NW4A2_14", - "PCIE_NW4A2_15", - "PCIE_NW4A2_16", - "PCIE_NW4A2_17", - "PCIE_NW4A2_18", - "PCIE_NW4A2_19", - "PCIE_NW4A2_2", - "PCIE_NW4A2_3", - "PCIE_NW4A2_4", - "PCIE_NW4A2_5", - "PCIE_NW4A2_6", - "PCIE_NW4A2_7", - "PCIE_NW4A2_8", - "PCIE_NW4A2_9", - "PCIE_NW4A3_0", - "PCIE_NW4A3_1", - "PCIE_NW4A3_10", - "PCIE_NW4A3_11", - "PCIE_NW4A3_12", - "PCIE_NW4A3_13", - "PCIE_NW4A3_14", - "PCIE_NW4A3_15", - "PCIE_NW4A3_16", - "PCIE_NW4A3_17", - "PCIE_NW4A3_18", - "PCIE_NW4A3_19", - "PCIE_NW4A3_2", - "PCIE_NW4A3_3", - "PCIE_NW4A3_4", - "PCIE_NW4A3_5", - "PCIE_NW4A3_6", - "PCIE_NW4A3_7", - "PCIE_NW4A3_8", - "PCIE_NW4A3_9", - "PCIE_NW4END0_0", - "PCIE_NW4END0_1", - "PCIE_NW4END0_10", - "PCIE_NW4END0_11", - "PCIE_NW4END0_12", - "PCIE_NW4END0_13", - "PCIE_NW4END0_14", - "PCIE_NW4END0_15", - "PCIE_NW4END0_16", - "PCIE_NW4END0_17", - "PCIE_NW4END0_18", - "PCIE_NW4END0_19", - "PCIE_NW4END0_2", - "PCIE_NW4END0_3", - "PCIE_NW4END0_4", - "PCIE_NW4END0_5", - "PCIE_NW4END0_6", - "PCIE_NW4END0_7", - "PCIE_NW4END0_8", - "PCIE_NW4END0_9", - "PCIE_NW4END1_0", - "PCIE_NW4END1_1", - "PCIE_NW4END1_10", - "PCIE_NW4END1_11", - "PCIE_NW4END1_12", - "PCIE_NW4END1_13", - "PCIE_NW4END1_14", - "PCIE_NW4END1_15", - "PCIE_NW4END1_16", - "PCIE_NW4END1_17", - "PCIE_NW4END1_18", - "PCIE_NW4END1_19", - "PCIE_NW4END1_2", - "PCIE_NW4END1_3", - "PCIE_NW4END1_4", - "PCIE_NW4END1_5", - "PCIE_NW4END1_6", - "PCIE_NW4END1_7", - "PCIE_NW4END1_8", - "PCIE_NW4END1_9", - "PCIE_NW4END2_0", - "PCIE_NW4END2_1", - "PCIE_NW4END2_10", - "PCIE_NW4END2_11", - "PCIE_NW4END2_12", - "PCIE_NW4END2_13", - "PCIE_NW4END2_14", - "PCIE_NW4END2_15", - "PCIE_NW4END2_16", - "PCIE_NW4END2_17", - "PCIE_NW4END2_18", - "PCIE_NW4END2_19", - "PCIE_NW4END2_2", - "PCIE_NW4END2_3", - "PCIE_NW4END2_4", - "PCIE_NW4END2_5", - "PCIE_NW4END2_6", - "PCIE_NW4END2_7", - "PCIE_NW4END2_8", - "PCIE_NW4END2_9", - "PCIE_NW4END3_0", - "PCIE_NW4END3_1", - "PCIE_NW4END3_10", - "PCIE_NW4END3_11", - "PCIE_NW4END3_12", - "PCIE_NW4END3_13", - "PCIE_NW4END3_14", - "PCIE_NW4END3_15", - "PCIE_NW4END3_16", - "PCIE_NW4END3_17", - "PCIE_NW4END3_18", - "PCIE_NW4END3_19", - "PCIE_NW4END3_2", - "PCIE_NW4END3_3", - "PCIE_NW4END3_4", - "PCIE_NW4END3_5", - "PCIE_NW4END3_6", - "PCIE_NW4END3_7", - "PCIE_NW4END3_8", - "PCIE_NW4END3_9", - "PCIE_PIPECLK", - "PCIE_PIPERX0CHANISALIGNED", - "PCIE_PIPERX0CHARISK0", - "PCIE_PIPERX0CHARISK1", - "PCIE_PIPERX0DATA0", - "PCIE_PIPERX0DATA1", - "PCIE_PIPERX0DATA10", - "PCIE_PIPERX0DATA11", - "PCIE_PIPERX0DATA12", - "PCIE_PIPERX0DATA13", - "PCIE_PIPERX0DATA14", - "PCIE_PIPERX0DATA15", - "PCIE_PIPERX0DATA2", - "PCIE_PIPERX0DATA3", - "PCIE_PIPERX0DATA4", - "PCIE_PIPERX0DATA5", - "PCIE_PIPERX0DATA6", - "PCIE_PIPERX0DATA7", - "PCIE_PIPERX0DATA8", - "PCIE_PIPERX0DATA9", - "PCIE_PIPERX0ELECIDLE", - "PCIE_PIPERX0PHYSTATUS", - "PCIE_PIPERX0POLARITY", - "PCIE_PIPERX0STATUS0", - "PCIE_PIPERX0STATUS1", - "PCIE_PIPERX0STATUS2", - "PCIE_PIPERX0VALID", - "PCIE_PIPERX1CHANISALIGNED", - "PCIE_PIPERX1CHARISK0", - "PCIE_PIPERX1CHARISK1", - "PCIE_PIPERX1DATA0", - "PCIE_PIPERX1DATA1", - "PCIE_PIPERX1DATA10", - "PCIE_PIPERX1DATA11", - "PCIE_PIPERX1DATA12", - "PCIE_PIPERX1DATA13", - "PCIE_PIPERX1DATA14", - "PCIE_PIPERX1DATA15", - "PCIE_PIPERX1DATA2", - "PCIE_PIPERX1DATA3", - "PCIE_PIPERX1DATA4", - "PCIE_PIPERX1DATA5", - "PCIE_PIPERX1DATA6", - "PCIE_PIPERX1DATA7", - "PCIE_PIPERX1DATA8", - "PCIE_PIPERX1DATA9", - "PCIE_PIPERX1ELECIDLE", - "PCIE_PIPERX1PHYSTATUS", - "PCIE_PIPERX1POLARITY", - "PCIE_PIPERX1STATUS0", - "PCIE_PIPERX1STATUS1", - "PCIE_PIPERX1STATUS2", - "PCIE_PIPERX1VALID", - "PCIE_PIPERX2CHANISALIGNED", - "PCIE_PIPERX2CHARISK0", - "PCIE_PIPERX2CHARISK1", - "PCIE_PIPERX2DATA0", - "PCIE_PIPERX2DATA1", - "PCIE_PIPERX2DATA10", - "PCIE_PIPERX2DATA11", - "PCIE_PIPERX2DATA12", - "PCIE_PIPERX2DATA13", - "PCIE_PIPERX2DATA14", - "PCIE_PIPERX2DATA15", - "PCIE_PIPERX2DATA2", - "PCIE_PIPERX2DATA3", - "PCIE_PIPERX2DATA4", - "PCIE_PIPERX2DATA5", - "PCIE_PIPERX2DATA6", - "PCIE_PIPERX2DATA7", - "PCIE_PIPERX2DATA8", - "PCIE_PIPERX2DATA9", - "PCIE_PIPERX2ELECIDLE", - "PCIE_PIPERX2PHYSTATUS", - "PCIE_PIPERX2POLARITY", - "PCIE_PIPERX2STATUS0", - "PCIE_PIPERX2STATUS1", - "PCIE_PIPERX2STATUS2", - "PCIE_PIPERX2VALID", - "PCIE_PIPERX3CHANISALIGNED", - "PCIE_PIPERX3CHARISK0", - "PCIE_PIPERX3CHARISK1", - "PCIE_PIPERX3DATA0", - "PCIE_PIPERX3DATA1", - "PCIE_PIPERX3DATA10", - "PCIE_PIPERX3DATA11", - "PCIE_PIPERX3DATA12", - "PCIE_PIPERX3DATA13", - "PCIE_PIPERX3DATA14", - "PCIE_PIPERX3DATA15", - "PCIE_PIPERX3DATA2", - "PCIE_PIPERX3DATA3", - "PCIE_PIPERX3DATA4", - "PCIE_PIPERX3DATA5", - "PCIE_PIPERX3DATA6", - "PCIE_PIPERX3DATA7", - "PCIE_PIPERX3DATA8", - "PCIE_PIPERX3DATA9", - "PCIE_PIPERX3ELECIDLE", - "PCIE_PIPERX3PHYSTATUS", - "PCIE_PIPERX3POLARITY", - "PCIE_PIPERX3STATUS0", - "PCIE_PIPERX3STATUS1", - "PCIE_PIPERX3STATUS2", - "PCIE_PIPERX3VALID", - "PCIE_PIPERX4CHANISALIGNED", - "PCIE_PIPERX4CHARISK0", - "PCIE_PIPERX4CHARISK1", - "PCIE_PIPERX4DATA0", - "PCIE_PIPERX4DATA1", - "PCIE_PIPERX4DATA10", - "PCIE_PIPERX4DATA11", - "PCIE_PIPERX4DATA12", - "PCIE_PIPERX4DATA13", - "PCIE_PIPERX4DATA14", - "PCIE_PIPERX4DATA15", - "PCIE_PIPERX4DATA2", - "PCIE_PIPERX4DATA3", - "PCIE_PIPERX4DATA4", - "PCIE_PIPERX4DATA5", - "PCIE_PIPERX4DATA6", - "PCIE_PIPERX4DATA7", - "PCIE_PIPERX4DATA8", - "PCIE_PIPERX4DATA9", - "PCIE_PIPERX4ELECIDLE", - "PCIE_PIPERX4PHYSTATUS", - "PCIE_PIPERX4POLARITY", - "PCIE_PIPERX4STATUS0", - "PCIE_PIPERX4STATUS1", - "PCIE_PIPERX4STATUS2", - "PCIE_PIPERX4VALID", - "PCIE_PIPERX5CHANISALIGNED", - "PCIE_PIPERX5CHARISK0", - "PCIE_PIPERX5CHARISK1", - "PCIE_PIPERX5DATA0", - "PCIE_PIPERX5DATA1", - "PCIE_PIPERX5DATA10", - "PCIE_PIPERX5DATA11", - "PCIE_PIPERX5DATA12", - "PCIE_PIPERX5DATA13", - "PCIE_PIPERX5DATA14", - "PCIE_PIPERX5DATA15", - "PCIE_PIPERX5DATA2", - "PCIE_PIPERX5DATA3", - "PCIE_PIPERX5DATA4", - "PCIE_PIPERX5DATA5", - "PCIE_PIPERX5DATA6", - "PCIE_PIPERX5DATA7", - "PCIE_PIPERX5DATA8", - "PCIE_PIPERX5DATA9", - "PCIE_PIPERX5ELECIDLE", - "PCIE_PIPERX5PHYSTATUS", - "PCIE_PIPERX5POLARITY", - "PCIE_PIPERX5STATUS0", - "PCIE_PIPERX5STATUS1", - "PCIE_PIPERX5STATUS2", - "PCIE_PIPERX5VALID", - "PCIE_PIPERX6CHANISALIGNED", - "PCIE_PIPERX6CHARISK0", - "PCIE_PIPERX6CHARISK1", - "PCIE_PIPERX6DATA0", - "PCIE_PIPERX6DATA1", - "PCIE_PIPERX6DATA10", - "PCIE_PIPERX6DATA11", - "PCIE_PIPERX6DATA12", - "PCIE_PIPERX6DATA13", - "PCIE_PIPERX6DATA14", - "PCIE_PIPERX6DATA15", - "PCIE_PIPERX6DATA2", - "PCIE_PIPERX6DATA3", - "PCIE_PIPERX6DATA4", - "PCIE_PIPERX6DATA5", - "PCIE_PIPERX6DATA6", - "PCIE_PIPERX6DATA7", - "PCIE_PIPERX6DATA8", - "PCIE_PIPERX6DATA9", - "PCIE_PIPERX6ELECIDLE", - "PCIE_PIPERX6PHYSTATUS", - "PCIE_PIPERX6POLARITY", - "PCIE_PIPERX6STATUS0", - "PCIE_PIPERX6STATUS1", - "PCIE_PIPERX6STATUS2", - "PCIE_PIPERX6VALID", - "PCIE_PIPERX7CHANISALIGNED", - "PCIE_PIPERX7CHARISK0", - "PCIE_PIPERX7CHARISK1", - "PCIE_PIPERX7DATA0", - "PCIE_PIPERX7DATA1", - "PCIE_PIPERX7DATA10", - "PCIE_PIPERX7DATA11", - "PCIE_PIPERX7DATA12", - "PCIE_PIPERX7DATA13", - "PCIE_PIPERX7DATA14", - "PCIE_PIPERX7DATA15", - "PCIE_PIPERX7DATA2", - "PCIE_PIPERX7DATA3", - "PCIE_PIPERX7DATA4", - "PCIE_PIPERX7DATA5", - "PCIE_PIPERX7DATA6", - "PCIE_PIPERX7DATA7", - "PCIE_PIPERX7DATA8", - "PCIE_PIPERX7DATA9", - "PCIE_PIPERX7ELECIDLE", - "PCIE_PIPERX7PHYSTATUS", - "PCIE_PIPERX7POLARITY", - "PCIE_PIPERX7STATUS0", - "PCIE_PIPERX7STATUS1", - "PCIE_PIPERX7STATUS2", - "PCIE_PIPERX7VALID", - "PCIE_PIPETX0CHARISK0", - "PCIE_PIPETX0CHARISK1", - "PCIE_PIPETX0COMPLIANCE", - "PCIE_PIPETX0DATA0", - "PCIE_PIPETX0DATA1", - "PCIE_PIPETX0DATA10", - "PCIE_PIPETX0DATA11", - "PCIE_PIPETX0DATA12", - "PCIE_PIPETX0DATA13", - "PCIE_PIPETX0DATA14", - "PCIE_PIPETX0DATA15", - "PCIE_PIPETX0DATA2", - "PCIE_PIPETX0DATA3", - "PCIE_PIPETX0DATA4", - "PCIE_PIPETX0DATA5", - "PCIE_PIPETX0DATA6", - "PCIE_PIPETX0DATA7", - "PCIE_PIPETX0DATA8", - "PCIE_PIPETX0DATA9", - "PCIE_PIPETX0ELECIDLE", - "PCIE_PIPETX0POWERDOWN0", - "PCIE_PIPETX0POWERDOWN1", - "PCIE_PIPETX1CHARISK0", - "PCIE_PIPETX1CHARISK1", - "PCIE_PIPETX1COMPLIANCE", - "PCIE_PIPETX1DATA0", - "PCIE_PIPETX1DATA1", - "PCIE_PIPETX1DATA10", - "PCIE_PIPETX1DATA11", - "PCIE_PIPETX1DATA12", - "PCIE_PIPETX1DATA13", - "PCIE_PIPETX1DATA14", - "PCIE_PIPETX1DATA15", - "PCIE_PIPETX1DATA2", - "PCIE_PIPETX1DATA3", - "PCIE_PIPETX1DATA4", - "PCIE_PIPETX1DATA5", - "PCIE_PIPETX1DATA6", - "PCIE_PIPETX1DATA7", - "PCIE_PIPETX1DATA8", - "PCIE_PIPETX1DATA9", - "PCIE_PIPETX1ELECIDLE", - "PCIE_PIPETX1POWERDOWN0", - "PCIE_PIPETX1POWERDOWN1", - "PCIE_PIPETX2CHARISK0", - "PCIE_PIPETX2CHARISK1", - "PCIE_PIPETX2COMPLIANCE", - "PCIE_PIPETX2DATA0", - "PCIE_PIPETX2DATA1", - "PCIE_PIPETX2DATA10", - "PCIE_PIPETX2DATA11", - "PCIE_PIPETX2DATA12", - "PCIE_PIPETX2DATA13", - "PCIE_PIPETX2DATA14", - "PCIE_PIPETX2DATA15", - "PCIE_PIPETX2DATA2", - "PCIE_PIPETX2DATA3", - "PCIE_PIPETX2DATA4", - "PCIE_PIPETX2DATA5", - "PCIE_PIPETX2DATA6", - "PCIE_PIPETX2DATA7", - "PCIE_PIPETX2DATA8", - "PCIE_PIPETX2DATA9", - "PCIE_PIPETX2ELECIDLE", - "PCIE_PIPETX2POWERDOWN0", - "PCIE_PIPETX2POWERDOWN1", - "PCIE_PIPETX3CHARISK0", - "PCIE_PIPETX3CHARISK1", - "PCIE_PIPETX3COMPLIANCE", - "PCIE_PIPETX3DATA0", - "PCIE_PIPETX3DATA1", - "PCIE_PIPETX3DATA10", - "PCIE_PIPETX3DATA11", - "PCIE_PIPETX3DATA12", - "PCIE_PIPETX3DATA13", - "PCIE_PIPETX3DATA14", - "PCIE_PIPETX3DATA15", - "PCIE_PIPETX3DATA2", - "PCIE_PIPETX3DATA3", - "PCIE_PIPETX3DATA4", - "PCIE_PIPETX3DATA5", - "PCIE_PIPETX3DATA6", - "PCIE_PIPETX3DATA7", - "PCIE_PIPETX3DATA8", - "PCIE_PIPETX3DATA9", - "PCIE_PIPETX3ELECIDLE", - "PCIE_PIPETX3POWERDOWN0", - "PCIE_PIPETX3POWERDOWN1", - "PCIE_PIPETX4CHARISK0", - "PCIE_PIPETX4CHARISK1", - "PCIE_PIPETX4COMPLIANCE", - "PCIE_PIPETX4DATA0", - "PCIE_PIPETX4DATA1", - "PCIE_PIPETX4DATA10", - "PCIE_PIPETX4DATA11", - "PCIE_PIPETX4DATA12", - "PCIE_PIPETX4DATA13", - "PCIE_PIPETX4DATA14", - "PCIE_PIPETX4DATA15", - "PCIE_PIPETX4DATA2", - "PCIE_PIPETX4DATA3", - "PCIE_PIPETX4DATA4", - "PCIE_PIPETX4DATA5", - "PCIE_PIPETX4DATA6", - "PCIE_PIPETX4DATA7", - "PCIE_PIPETX4DATA8", - "PCIE_PIPETX4DATA9", - "PCIE_PIPETX4ELECIDLE", - "PCIE_PIPETX4POWERDOWN0", - "PCIE_PIPETX4POWERDOWN1", - "PCIE_PIPETX5CHARISK0", - "PCIE_PIPETX5CHARISK1", - "PCIE_PIPETX5COMPLIANCE", - "PCIE_PIPETX5DATA0", - "PCIE_PIPETX5DATA1", - "PCIE_PIPETX5DATA10", - "PCIE_PIPETX5DATA11", - "PCIE_PIPETX5DATA12", - "PCIE_PIPETX5DATA13", - "PCIE_PIPETX5DATA14", - "PCIE_PIPETX5DATA15", - "PCIE_PIPETX5DATA2", - "PCIE_PIPETX5DATA3", - "PCIE_PIPETX5DATA4", - "PCIE_PIPETX5DATA5", - "PCIE_PIPETX5DATA6", - "PCIE_PIPETX5DATA7", - "PCIE_PIPETX5DATA8", - "PCIE_PIPETX5DATA9", - "PCIE_PIPETX5ELECIDLE", - "PCIE_PIPETX5POWERDOWN0", - "PCIE_PIPETX5POWERDOWN1", - "PCIE_PIPETX6CHARISK0", - "PCIE_PIPETX6CHARISK1", - "PCIE_PIPETX6COMPLIANCE", - "PCIE_PIPETX6DATA0", - "PCIE_PIPETX6DATA1", - "PCIE_PIPETX6DATA10", - "PCIE_PIPETX6DATA11", - "PCIE_PIPETX6DATA12", - "PCIE_PIPETX6DATA13", - "PCIE_PIPETX6DATA14", - "PCIE_PIPETX6DATA15", - "PCIE_PIPETX6DATA2", - "PCIE_PIPETX6DATA3", - "PCIE_PIPETX6DATA4", - "PCIE_PIPETX6DATA5", - "PCIE_PIPETX6DATA6", - "PCIE_PIPETX6DATA7", - "PCIE_PIPETX6DATA8", - "PCIE_PIPETX6DATA9", - "PCIE_PIPETX6ELECIDLE", - "PCIE_PIPETX6POWERDOWN0", - "PCIE_PIPETX6POWERDOWN1", - "PCIE_PIPETX7CHARISK0", - "PCIE_PIPETX7CHARISK1", - "PCIE_PIPETX7COMPLIANCE", - "PCIE_PIPETX7DATA0", - "PCIE_PIPETX7DATA1", - "PCIE_PIPETX7DATA10", - "PCIE_PIPETX7DATA11", - "PCIE_PIPETX7DATA12", - "PCIE_PIPETX7DATA13", - "PCIE_PIPETX7DATA14", - "PCIE_PIPETX7DATA15", - "PCIE_PIPETX7DATA2", - "PCIE_PIPETX7DATA3", - "PCIE_PIPETX7DATA4", - "PCIE_PIPETX7DATA5", - "PCIE_PIPETX7DATA6", - "PCIE_PIPETX7DATA7", - "PCIE_PIPETX7DATA8", - "PCIE_PIPETX7DATA9", - "PCIE_PIPETX7ELECIDLE", - "PCIE_PIPETX7POWERDOWN0", - "PCIE_PIPETX7POWERDOWN1", - "PCIE_PIPETXDEEMPH", - "PCIE_PIPETXMARGIN0", - "PCIE_PIPETXMARGIN1", - "PCIE_PIPETXMARGIN2", - "PCIE_PIPETXRATE", - "PCIE_PIPETXRCVRDET", - "PCIE_PIPETXRESET", - "PCIE_PL2DIRECTEDLSTATE0", - "PCIE_PL2DIRECTEDLSTATE1", - "PCIE_PL2DIRECTEDLSTATE2", - "PCIE_PL2DIRECTEDLSTATE3", - "PCIE_PL2DIRECTEDLSTATE4", - "PCIE_PL2L0REQ", - "PCIE_PL2LINKUP", - "PCIE_PL2RECEIVERERR", - "PCIE_PL2RECOVERY", - "PCIE_PL2RXELECIDLE", - "PCIE_PL2RXPMSTATE0", - "PCIE_PL2RXPMSTATE1", - "PCIE_PL2SUSPENDOK", - "PCIE_PLDBGMODE0", - "PCIE_PLDBGMODE1", - "PCIE_PLDBGMODE2", - "PCIE_PLDBGVEC0", - "PCIE_PLDBGVEC1", - "PCIE_PLDBGVEC10", - "PCIE_PLDBGVEC11", - "PCIE_PLDBGVEC2", - "PCIE_PLDBGVEC3", - "PCIE_PLDBGVEC4", - "PCIE_PLDBGVEC5", - "PCIE_PLDBGVEC6", - "PCIE_PLDBGVEC7", - "PCIE_PLDBGVEC8", - "PCIE_PLDBGVEC9", - "PCIE_PLDIRECTEDCHANGEDONE", - "PCIE_PLDIRECTEDLINKAUTON", - "PCIE_PLDIRECTEDLINKCHANGE0", - "PCIE_PLDIRECTEDLINKCHANGE1", - "PCIE_PLDIRECTEDLINKSPEED", - "PCIE_PLDIRECTEDLINKWIDTH0", - "PCIE_PLDIRECTEDLINKWIDTH1", - "PCIE_PLDIRECTEDLTSSMNEW0", - "PCIE_PLDIRECTEDLTSSMNEW1", - "PCIE_PLDIRECTEDLTSSMNEW2", - "PCIE_PLDIRECTEDLTSSMNEW3", - "PCIE_PLDIRECTEDLTSSMNEW4", - "PCIE_PLDIRECTEDLTSSMNEW5", - "PCIE_PLDIRECTEDLTSSMNEWVLD", - "PCIE_PLDIRECTEDLTSSMSTALL", - "PCIE_PLDOWNSTREAMDEEMPHSOURCE", - "PCIE_PLINITIALLINKWIDTH0", - "PCIE_PLINITIALLINKWIDTH1", - "PCIE_PLINITIALLINKWIDTH2", - "PCIE_PLLANEREVERSALMODE0", - "PCIE_PLLANEREVERSALMODE1", - "PCIE_PLLINKGEN2CAP", - "PCIE_PLLINKPARTNERGEN2SUPPORTED", - "PCIE_PLLINKUPCFGCAP", - "PCIE_PLLTSSMSTATE0", - "PCIE_PLLTSSMSTATE1", - "PCIE_PLLTSSMSTATE2", - "PCIE_PLLTSSMSTATE3", - "PCIE_PLLTSSMSTATE4", - "PCIE_PLLTSSMSTATE5", - "PCIE_PLPHYLNKUPN", - "PCIE_PLRECEIVEDHOTRST", - "PCIE_PLRSTN", - "PCIE_PLRXPMSTATE0", - "PCIE_PLRXPMSTATE1", - "PCIE_PLSELLNKRATE", - "PCIE_PLSELLNKWIDTH0", - "PCIE_PLSELLNKWIDTH1", - "PCIE_PLTRANSMITHOTRST", - "PCIE_PLTXPMSTATE0", - "PCIE_PLTXPMSTATE1", - "PCIE_PLTXPMSTATE2", - "PCIE_PLUPSTREAMPREFERDEEMPH", - "PCIE_PMVDIVIDE0", - "PCIE_PMVDIVIDE1", - "PCIE_PMVENABLEN", - "PCIE_PMVOUT", - "PCIE_PMVSELECT0", - "PCIE_PMVSELECT1", - "PCIE_PMVSELECT2", - "PCIE_RECEIVEDFUNCLVLRSTN", - "PCIE_SCANENABLEN", - "PCIE_SCANMODEN", - "PCIE_SE2A0_0", - "PCIE_SE2A0_1", - "PCIE_SE2A0_10", - "PCIE_SE2A0_11", - "PCIE_SE2A0_12", - "PCIE_SE2A0_13", - "PCIE_SE2A0_14", - "PCIE_SE2A0_15", - "PCIE_SE2A0_16", - "PCIE_SE2A0_17", - "PCIE_SE2A0_18", - "PCIE_SE2A0_19", - "PCIE_SE2A0_2", - "PCIE_SE2A0_3", - "PCIE_SE2A0_4", - "PCIE_SE2A0_5", - "PCIE_SE2A0_6", - "PCIE_SE2A0_7", - "PCIE_SE2A0_8", - "PCIE_SE2A0_9", - "PCIE_SE2A1_0", - "PCIE_SE2A1_1", - "PCIE_SE2A1_10", - "PCIE_SE2A1_11", - "PCIE_SE2A1_12", - "PCIE_SE2A1_13", - "PCIE_SE2A1_14", - "PCIE_SE2A1_15", - "PCIE_SE2A1_16", - "PCIE_SE2A1_17", - "PCIE_SE2A1_18", - "PCIE_SE2A1_19", - "PCIE_SE2A1_2", - "PCIE_SE2A1_3", - "PCIE_SE2A1_4", - "PCIE_SE2A1_5", - "PCIE_SE2A1_6", - "PCIE_SE2A1_7", - "PCIE_SE2A1_8", - "PCIE_SE2A1_9", - "PCIE_SE2A2_0", - "PCIE_SE2A2_1", - "PCIE_SE2A2_10", - "PCIE_SE2A2_11", - "PCIE_SE2A2_12", - "PCIE_SE2A2_13", - "PCIE_SE2A2_14", - "PCIE_SE2A2_15", - "PCIE_SE2A2_16", - "PCIE_SE2A2_17", - "PCIE_SE2A2_18", - "PCIE_SE2A2_19", - "PCIE_SE2A2_2", - "PCIE_SE2A2_3", - "PCIE_SE2A2_4", - "PCIE_SE2A2_5", - "PCIE_SE2A2_6", - "PCIE_SE2A2_7", - "PCIE_SE2A2_8", - "PCIE_SE2A2_9", - "PCIE_SE2A3_0", - "PCIE_SE2A3_1", - "PCIE_SE2A3_10", - "PCIE_SE2A3_11", - "PCIE_SE2A3_12", - "PCIE_SE2A3_13", - "PCIE_SE2A3_14", - "PCIE_SE2A3_15", - "PCIE_SE2A3_16", - "PCIE_SE2A3_17", - "PCIE_SE2A3_18", - "PCIE_SE2A3_19", - "PCIE_SE2A3_2", - "PCIE_SE2A3_3", - "PCIE_SE2A3_4", - "PCIE_SE2A3_5", - "PCIE_SE2A3_6", - "PCIE_SE2A3_7", - "PCIE_SE2A3_8", - "PCIE_SE2A3_9", - "PCIE_SE4BEG0_0", - "PCIE_SE4BEG0_1", - "PCIE_SE4BEG0_10", - "PCIE_SE4BEG0_11", - "PCIE_SE4BEG0_12", - "PCIE_SE4BEG0_13", - "PCIE_SE4BEG0_14", - "PCIE_SE4BEG0_15", - "PCIE_SE4BEG0_16", - "PCIE_SE4BEG0_17", - "PCIE_SE4BEG0_18", - "PCIE_SE4BEG0_19", - "PCIE_SE4BEG0_2", - "PCIE_SE4BEG0_3", - "PCIE_SE4BEG0_4", - "PCIE_SE4BEG0_5", - "PCIE_SE4BEG0_6", - "PCIE_SE4BEG0_7", - "PCIE_SE4BEG0_8", - "PCIE_SE4BEG0_9", - "PCIE_SE4BEG1_0", - "PCIE_SE4BEG1_1", - "PCIE_SE4BEG1_10", - "PCIE_SE4BEG1_11", - "PCIE_SE4BEG1_12", - "PCIE_SE4BEG1_13", - "PCIE_SE4BEG1_14", - "PCIE_SE4BEG1_15", - "PCIE_SE4BEG1_16", - "PCIE_SE4BEG1_17", - "PCIE_SE4BEG1_18", - "PCIE_SE4BEG1_19", - "PCIE_SE4BEG1_2", - "PCIE_SE4BEG1_3", - "PCIE_SE4BEG1_4", - "PCIE_SE4BEG1_5", - "PCIE_SE4BEG1_6", - "PCIE_SE4BEG1_7", - "PCIE_SE4BEG1_8", - "PCIE_SE4BEG1_9", - "PCIE_SE4BEG2_0", - "PCIE_SE4BEG2_1", - "PCIE_SE4BEG2_10", - "PCIE_SE4BEG2_11", - "PCIE_SE4BEG2_12", - "PCIE_SE4BEG2_13", - "PCIE_SE4BEG2_14", - "PCIE_SE4BEG2_15", - "PCIE_SE4BEG2_16", - "PCIE_SE4BEG2_17", - "PCIE_SE4BEG2_18", - "PCIE_SE4BEG2_19", - "PCIE_SE4BEG2_2", - "PCIE_SE4BEG2_3", - "PCIE_SE4BEG2_4", - "PCIE_SE4BEG2_5", - "PCIE_SE4BEG2_6", - "PCIE_SE4BEG2_7", - "PCIE_SE4BEG2_8", - "PCIE_SE4BEG2_9", - "PCIE_SE4BEG3_0", - "PCIE_SE4BEG3_1", - "PCIE_SE4BEG3_10", - "PCIE_SE4BEG3_11", - "PCIE_SE4BEG3_12", - "PCIE_SE4BEG3_13", - "PCIE_SE4BEG3_14", - "PCIE_SE4BEG3_15", - "PCIE_SE4BEG3_16", - "PCIE_SE4BEG3_17", - "PCIE_SE4BEG3_18", - "PCIE_SE4BEG3_19", - "PCIE_SE4BEG3_2", - "PCIE_SE4BEG3_3", - "PCIE_SE4BEG3_4", - "PCIE_SE4BEG3_5", - "PCIE_SE4BEG3_6", - "PCIE_SE4BEG3_7", - "PCIE_SE4BEG3_8", - "PCIE_SE4BEG3_9", - "PCIE_SE4C0_0", - "PCIE_SE4C0_1", - "PCIE_SE4C0_10", - "PCIE_SE4C0_11", - "PCIE_SE4C0_12", - "PCIE_SE4C0_13", - "PCIE_SE4C0_14", - "PCIE_SE4C0_15", - "PCIE_SE4C0_16", - "PCIE_SE4C0_17", - "PCIE_SE4C0_18", - "PCIE_SE4C0_19", - "PCIE_SE4C0_2", - "PCIE_SE4C0_3", - "PCIE_SE4C0_4", - "PCIE_SE4C0_5", - "PCIE_SE4C0_6", - "PCIE_SE4C0_7", - "PCIE_SE4C0_8", - "PCIE_SE4C0_9", - "PCIE_SE4C1_0", - "PCIE_SE4C1_1", - "PCIE_SE4C1_10", - "PCIE_SE4C1_11", - "PCIE_SE4C1_12", - "PCIE_SE4C1_13", - "PCIE_SE4C1_14", - "PCIE_SE4C1_15", - "PCIE_SE4C1_16", - "PCIE_SE4C1_17", - "PCIE_SE4C1_18", - "PCIE_SE4C1_19", - "PCIE_SE4C1_2", - "PCIE_SE4C1_3", - "PCIE_SE4C1_4", - "PCIE_SE4C1_5", - "PCIE_SE4C1_6", - "PCIE_SE4C1_7", - "PCIE_SE4C1_8", - "PCIE_SE4C1_9", - "PCIE_SE4C2_0", - "PCIE_SE4C2_1", - "PCIE_SE4C2_10", - "PCIE_SE4C2_11", - "PCIE_SE4C2_12", - "PCIE_SE4C2_13", - "PCIE_SE4C2_14", - "PCIE_SE4C2_15", - "PCIE_SE4C2_16", - "PCIE_SE4C2_17", - "PCIE_SE4C2_18", - "PCIE_SE4C2_19", - "PCIE_SE4C2_2", - "PCIE_SE4C2_3", - "PCIE_SE4C2_4", - "PCIE_SE4C2_5", - "PCIE_SE4C2_6", - "PCIE_SE4C2_7", - "PCIE_SE4C2_8", - "PCIE_SE4C2_9", - "PCIE_SE4C3_0", - "PCIE_SE4C3_1", - "PCIE_SE4C3_10", - "PCIE_SE4C3_11", - "PCIE_SE4C3_12", - "PCIE_SE4C3_13", - "PCIE_SE4C3_14", - "PCIE_SE4C3_15", - "PCIE_SE4C3_16", - "PCIE_SE4C3_17", - "PCIE_SE4C3_18", - "PCIE_SE4C3_19", - "PCIE_SE4C3_2", - "PCIE_SE4C3_3", - "PCIE_SE4C3_4", - "PCIE_SE4C3_5", - "PCIE_SE4C3_6", - "PCIE_SE4C3_7", - "PCIE_SE4C3_8", - "PCIE_SE4C3_9", - "PCIE_SW2A0_0", - "PCIE_SW2A0_1", - "PCIE_SW2A0_10", - "PCIE_SW2A0_11", - "PCIE_SW2A0_12", - "PCIE_SW2A0_13", - "PCIE_SW2A0_14", - "PCIE_SW2A0_15", - "PCIE_SW2A0_16", - "PCIE_SW2A0_17", - "PCIE_SW2A0_18", - "PCIE_SW2A0_19", - "PCIE_SW2A0_2", - "PCIE_SW2A0_3", - "PCIE_SW2A0_4", - "PCIE_SW2A0_5", - "PCIE_SW2A0_6", - "PCIE_SW2A0_7", - "PCIE_SW2A0_8", - "PCIE_SW2A0_9", - "PCIE_SW2A1_0", - "PCIE_SW2A1_1", - "PCIE_SW2A1_10", - "PCIE_SW2A1_11", - "PCIE_SW2A1_12", - "PCIE_SW2A1_13", - "PCIE_SW2A1_14", - "PCIE_SW2A1_15", - "PCIE_SW2A1_16", - "PCIE_SW2A1_17", - "PCIE_SW2A1_18", - "PCIE_SW2A1_19", - "PCIE_SW2A1_2", - "PCIE_SW2A1_3", - "PCIE_SW2A1_4", - "PCIE_SW2A1_5", - "PCIE_SW2A1_6", - "PCIE_SW2A1_7", - "PCIE_SW2A1_8", - "PCIE_SW2A1_9", - "PCIE_SW2A2_0", - "PCIE_SW2A2_1", - "PCIE_SW2A2_10", - "PCIE_SW2A2_11", - "PCIE_SW2A2_12", - "PCIE_SW2A2_13", - "PCIE_SW2A2_14", - "PCIE_SW2A2_15", - "PCIE_SW2A2_16", - "PCIE_SW2A2_17", - "PCIE_SW2A2_18", - "PCIE_SW2A2_19", - "PCIE_SW2A2_2", - "PCIE_SW2A2_3", - "PCIE_SW2A2_4", - "PCIE_SW2A2_5", - "PCIE_SW2A2_6", - "PCIE_SW2A2_7", - "PCIE_SW2A2_8", - "PCIE_SW2A2_9", - "PCIE_SW2A3_0", - "PCIE_SW2A3_1", - "PCIE_SW2A3_10", - "PCIE_SW2A3_11", - "PCIE_SW2A3_12", - "PCIE_SW2A3_13", - "PCIE_SW2A3_14", - "PCIE_SW2A3_15", - "PCIE_SW2A3_16", - "PCIE_SW2A3_17", - "PCIE_SW2A3_18", - "PCIE_SW2A3_19", - "PCIE_SW2A3_2", - "PCIE_SW2A3_3", - "PCIE_SW2A3_4", - "PCIE_SW2A3_5", - "PCIE_SW2A3_6", - "PCIE_SW2A3_7", - "PCIE_SW2A3_8", - "PCIE_SW2A3_9", - "PCIE_SW4A0_0", - "PCIE_SW4A0_1", - "PCIE_SW4A0_10", - "PCIE_SW4A0_11", - "PCIE_SW4A0_12", - "PCIE_SW4A0_13", - "PCIE_SW4A0_14", - "PCIE_SW4A0_15", - "PCIE_SW4A0_16", - "PCIE_SW4A0_17", - "PCIE_SW4A0_18", - "PCIE_SW4A0_19", - "PCIE_SW4A0_2", - "PCIE_SW4A0_3", - "PCIE_SW4A0_4", - "PCIE_SW4A0_5", - "PCIE_SW4A0_6", - "PCIE_SW4A0_7", - "PCIE_SW4A0_8", - "PCIE_SW4A0_9", - "PCIE_SW4A1_0", - "PCIE_SW4A1_1", - "PCIE_SW4A1_10", - "PCIE_SW4A1_11", - "PCIE_SW4A1_12", - "PCIE_SW4A1_13", - "PCIE_SW4A1_14", - "PCIE_SW4A1_15", - "PCIE_SW4A1_16", - "PCIE_SW4A1_17", - "PCIE_SW4A1_18", - "PCIE_SW4A1_19", - "PCIE_SW4A1_2", - "PCIE_SW4A1_3", - "PCIE_SW4A1_4", - "PCIE_SW4A1_5", - "PCIE_SW4A1_6", - "PCIE_SW4A1_7", - "PCIE_SW4A1_8", - "PCIE_SW4A1_9", - "PCIE_SW4A2_0", - "PCIE_SW4A2_1", - "PCIE_SW4A2_10", - "PCIE_SW4A2_11", - "PCIE_SW4A2_12", - "PCIE_SW4A2_13", - "PCIE_SW4A2_14", - "PCIE_SW4A2_15", - "PCIE_SW4A2_16", - "PCIE_SW4A2_17", - "PCIE_SW4A2_18", - "PCIE_SW4A2_19", - "PCIE_SW4A2_2", - "PCIE_SW4A2_3", - "PCIE_SW4A2_4", - "PCIE_SW4A2_5", - "PCIE_SW4A2_6", - "PCIE_SW4A2_7", - "PCIE_SW4A2_8", - "PCIE_SW4A2_9", - "PCIE_SW4A3_0", - "PCIE_SW4A3_1", - "PCIE_SW4A3_10", - "PCIE_SW4A3_11", - "PCIE_SW4A3_12", - "PCIE_SW4A3_13", - "PCIE_SW4A3_14", - "PCIE_SW4A3_15", - "PCIE_SW4A3_16", - "PCIE_SW4A3_17", - "PCIE_SW4A3_18", - "PCIE_SW4A3_19", - "PCIE_SW4A3_2", - "PCIE_SW4A3_3", - "PCIE_SW4A3_4", - "PCIE_SW4A3_5", - "PCIE_SW4A3_6", - "PCIE_SW4A3_7", - "PCIE_SW4A3_8", - "PCIE_SW4A3_9", - "PCIE_SW4END0_0", - "PCIE_SW4END0_1", - "PCIE_SW4END0_10", - "PCIE_SW4END0_11", - "PCIE_SW4END0_12", - "PCIE_SW4END0_13", - "PCIE_SW4END0_14", - "PCIE_SW4END0_15", - "PCIE_SW4END0_16", - "PCIE_SW4END0_17", - "PCIE_SW4END0_18", - "PCIE_SW4END0_19", - "PCIE_SW4END0_2", - "PCIE_SW4END0_3", - "PCIE_SW4END0_4", - "PCIE_SW4END0_5", - "PCIE_SW4END0_6", - "PCIE_SW4END0_7", - "PCIE_SW4END0_8", - "PCIE_SW4END0_9", - "PCIE_SW4END1_0", - "PCIE_SW4END1_1", - "PCIE_SW4END1_10", - "PCIE_SW4END1_11", - "PCIE_SW4END1_12", - "PCIE_SW4END1_13", - "PCIE_SW4END1_14", - "PCIE_SW4END1_15", - "PCIE_SW4END1_16", - "PCIE_SW4END1_17", - "PCIE_SW4END1_18", - "PCIE_SW4END1_19", - "PCIE_SW4END1_2", - "PCIE_SW4END1_3", - "PCIE_SW4END1_4", - "PCIE_SW4END1_5", - "PCIE_SW4END1_6", - "PCIE_SW4END1_7", - "PCIE_SW4END1_8", - "PCIE_SW4END1_9", - "PCIE_SW4END2_0", - "PCIE_SW4END2_1", - "PCIE_SW4END2_10", - "PCIE_SW4END2_11", - "PCIE_SW4END2_12", - "PCIE_SW4END2_13", - "PCIE_SW4END2_14", - "PCIE_SW4END2_15", - "PCIE_SW4END2_16", - "PCIE_SW4END2_17", - "PCIE_SW4END2_18", - "PCIE_SW4END2_19", - "PCIE_SW4END2_2", - "PCIE_SW4END2_3", - "PCIE_SW4END2_4", - "PCIE_SW4END2_5", - "PCIE_SW4END2_6", - "PCIE_SW4END2_7", - "PCIE_SW4END2_8", - "PCIE_SW4END2_9", - "PCIE_SW4END3_0", - "PCIE_SW4END3_1", - "PCIE_SW4END3_10", - "PCIE_SW4END3_11", - "PCIE_SW4END3_12", - "PCIE_SW4END3_13", - "PCIE_SW4END3_14", - "PCIE_SW4END3_15", - "PCIE_SW4END3_16", - "PCIE_SW4END3_17", - "PCIE_SW4END3_18", - "PCIE_SW4END3_19", - "PCIE_SW4END3_2", - "PCIE_SW4END3_3", - "PCIE_SW4END3_4", - "PCIE_SW4END3_5", - "PCIE_SW4END3_6", - "PCIE_SW4END3_7", - "PCIE_SW4END3_8", - "PCIE_SW4END3_9", - "PCIE_SYSRSTN", - "PCIE_TL2ASPMSUSPENDCREDITCHECK", - "PCIE_TL2ASPMSUSPENDCREDITCHECKOK", - "PCIE_TL2ASPMSUSPENDREQ", - "PCIE_TL2ERRFCPE", - "PCIE_TL2ERRHDR0", - "PCIE_TL2ERRHDR1", - "PCIE_TL2ERRHDR10", - "PCIE_TL2ERRHDR11", - "PCIE_TL2ERRHDR12", - "PCIE_TL2ERRHDR13", - "PCIE_TL2ERRHDR14", - "PCIE_TL2ERRHDR15", - "PCIE_TL2ERRHDR16", - "PCIE_TL2ERRHDR17", - "PCIE_TL2ERRHDR18", - "PCIE_TL2ERRHDR19", - "PCIE_TL2ERRHDR2", - "PCIE_TL2ERRHDR20", - "PCIE_TL2ERRHDR21", - "PCIE_TL2ERRHDR22", - "PCIE_TL2ERRHDR23", - "PCIE_TL2ERRHDR24", - "PCIE_TL2ERRHDR25", - "PCIE_TL2ERRHDR26", - "PCIE_TL2ERRHDR27", - "PCIE_TL2ERRHDR28", - "PCIE_TL2ERRHDR29", - "PCIE_TL2ERRHDR3", - "PCIE_TL2ERRHDR30", - "PCIE_TL2ERRHDR31", - "PCIE_TL2ERRHDR32", - "PCIE_TL2ERRHDR33", - "PCIE_TL2ERRHDR34", - "PCIE_TL2ERRHDR35", - "PCIE_TL2ERRHDR36", - "PCIE_TL2ERRHDR37", - "PCIE_TL2ERRHDR38", - "PCIE_TL2ERRHDR39", - "PCIE_TL2ERRHDR4", - "PCIE_TL2ERRHDR40", - "PCIE_TL2ERRHDR41", - "PCIE_TL2ERRHDR42", - "PCIE_TL2ERRHDR43", - "PCIE_TL2ERRHDR44", - "PCIE_TL2ERRHDR45", - "PCIE_TL2ERRHDR46", - "PCIE_TL2ERRHDR47", - "PCIE_TL2ERRHDR48", - "PCIE_TL2ERRHDR49", - "PCIE_TL2ERRHDR5", - "PCIE_TL2ERRHDR50", - "PCIE_TL2ERRHDR51", - "PCIE_TL2ERRHDR52", - "PCIE_TL2ERRHDR53", - "PCIE_TL2ERRHDR54", - "PCIE_TL2ERRHDR55", - "PCIE_TL2ERRHDR56", - "PCIE_TL2ERRHDR57", - "PCIE_TL2ERRHDR58", - "PCIE_TL2ERRHDR59", - "PCIE_TL2ERRHDR6", - "PCIE_TL2ERRHDR60", - "PCIE_TL2ERRHDR61", - "PCIE_TL2ERRHDR62", - "PCIE_TL2ERRHDR63", - "PCIE_TL2ERRHDR7", - "PCIE_TL2ERRHDR8", - "PCIE_TL2ERRHDR9", - "PCIE_TL2ERRMALFORMED", - "PCIE_TL2ERRRXOVERFLOW", - "PCIE_TL2PPMSUSPENDOK", - "PCIE_TL2PPMSUSPENDREQ", - "PCIE_TLRSTN", - "PCIE_TRNFCCPLD0", - "PCIE_TRNFCCPLD1", - "PCIE_TRNFCCPLD10", - "PCIE_TRNFCCPLD11", - "PCIE_TRNFCCPLD2", - "PCIE_TRNFCCPLD3", - "PCIE_TRNFCCPLD4", - "PCIE_TRNFCCPLD5", - "PCIE_TRNFCCPLD6", - "PCIE_TRNFCCPLD7", - "PCIE_TRNFCCPLD8", - "PCIE_TRNFCCPLD9", - "PCIE_TRNFCCPLH0", - "PCIE_TRNFCCPLH1", - "PCIE_TRNFCCPLH2", - "PCIE_TRNFCCPLH3", - "PCIE_TRNFCCPLH4", - "PCIE_TRNFCCPLH5", - "PCIE_TRNFCCPLH6", - "PCIE_TRNFCCPLH7", - "PCIE_TRNFCNPD0", - "PCIE_TRNFCNPD1", - "PCIE_TRNFCNPD10", - "PCIE_TRNFCNPD11", - "PCIE_TRNFCNPD2", - "PCIE_TRNFCNPD3", - "PCIE_TRNFCNPD4", - "PCIE_TRNFCNPD5", - "PCIE_TRNFCNPD6", - "PCIE_TRNFCNPD7", - "PCIE_TRNFCNPD8", - "PCIE_TRNFCNPD9", - "PCIE_TRNFCNPH0", - "PCIE_TRNFCNPH1", - "PCIE_TRNFCNPH2", - "PCIE_TRNFCNPH3", - "PCIE_TRNFCNPH4", - "PCIE_TRNFCNPH5", - "PCIE_TRNFCNPH6", - "PCIE_TRNFCNPH7", - "PCIE_TRNFCPD0", - "PCIE_TRNFCPD1", - "PCIE_TRNFCPD10", - "PCIE_TRNFCPD11", - "PCIE_TRNFCPD2", - "PCIE_TRNFCPD3", - "PCIE_TRNFCPD4", - "PCIE_TRNFCPD5", - "PCIE_TRNFCPD6", - "PCIE_TRNFCPD7", - "PCIE_TRNFCPD8", - "PCIE_TRNFCPD9", - "PCIE_TRNFCPH0", - "PCIE_TRNFCPH1", - "PCIE_TRNFCPH2", - "PCIE_TRNFCPH3", - "PCIE_TRNFCPH4", - "PCIE_TRNFCPH5", - "PCIE_TRNFCPH6", - "PCIE_TRNFCPH7", - "PCIE_TRNFCSEL0", - "PCIE_TRNFCSEL1", - "PCIE_TRNFCSEL2", - "PCIE_TRNLNKUP", - "PCIE_TRNRBARHIT0", - "PCIE_TRNRBARHIT1", - "PCIE_TRNRBARHIT2", - "PCIE_TRNRBARHIT3", - "PCIE_TRNRBARHIT4", - "PCIE_TRNRBARHIT5", - "PCIE_TRNRBARHIT6", - "PCIE_TRNRBARHIT7", - "PCIE_TRNRD0", - "PCIE_TRNRD1", - "PCIE_TRNRD10", - "PCIE_TRNRD100", - "PCIE_TRNRD101", - "PCIE_TRNRD102", - "PCIE_TRNRD103", - "PCIE_TRNRD104", - "PCIE_TRNRD105", - "PCIE_TRNRD106", - "PCIE_TRNRD107", - "PCIE_TRNRD108", - "PCIE_TRNRD109", - "PCIE_TRNRD11", - "PCIE_TRNRD110", - "PCIE_TRNRD111", - "PCIE_TRNRD112", - "PCIE_TRNRD113", - "PCIE_TRNRD114", - "PCIE_TRNRD115", - "PCIE_TRNRD116", - "PCIE_TRNRD117", - "PCIE_TRNRD118", - "PCIE_TRNRD119", - "PCIE_TRNRD12", - "PCIE_TRNRD120", - "PCIE_TRNRD121", - "PCIE_TRNRD122", - "PCIE_TRNRD123", - "PCIE_TRNRD124", - "PCIE_TRNRD125", - "PCIE_TRNRD126", - "PCIE_TRNRD127", - "PCIE_TRNRD13", - "PCIE_TRNRD14", - "PCIE_TRNRD15", - "PCIE_TRNRD16", - "PCIE_TRNRD17", - "PCIE_TRNRD18", - "PCIE_TRNRD19", - "PCIE_TRNRD2", - "PCIE_TRNRD20", - "PCIE_TRNRD21", - "PCIE_TRNRD22", - "PCIE_TRNRD23", - "PCIE_TRNRD24", - "PCIE_TRNRD25", - "PCIE_TRNRD26", - "PCIE_TRNRD27", - "PCIE_TRNRD28", - "PCIE_TRNRD29", - "PCIE_TRNRD3", - "PCIE_TRNRD30", - "PCIE_TRNRD31", - "PCIE_TRNRD32", - "PCIE_TRNRD33", - "PCIE_TRNRD34", - "PCIE_TRNRD35", - "PCIE_TRNRD36", - "PCIE_TRNRD37", - "PCIE_TRNRD38", - "PCIE_TRNRD39", - "PCIE_TRNRD4", - "PCIE_TRNRD40", - "PCIE_TRNRD41", - "PCIE_TRNRD42", - "PCIE_TRNRD43", - "PCIE_TRNRD44", - "PCIE_TRNRD45", - "PCIE_TRNRD46", - "PCIE_TRNRD47", - "PCIE_TRNRD48", - "PCIE_TRNRD49", - "PCIE_TRNRD5", - "PCIE_TRNRD50", - "PCIE_TRNRD51", - "PCIE_TRNRD52", - "PCIE_TRNRD53", - "PCIE_TRNRD54", - "PCIE_TRNRD55", - "PCIE_TRNRD56", - "PCIE_TRNRD57", - "PCIE_TRNRD58", - "PCIE_TRNRD59", - "PCIE_TRNRD6", - "PCIE_TRNRD60", - "PCIE_TRNRD61", - "PCIE_TRNRD62", - "PCIE_TRNRD63", - "PCIE_TRNRD64", - "PCIE_TRNRD65", - "PCIE_TRNRD66", - "PCIE_TRNRD67", - "PCIE_TRNRD68", - "PCIE_TRNRD69", - "PCIE_TRNRD7", - "PCIE_TRNRD70", - "PCIE_TRNRD71", - "PCIE_TRNRD72", - "PCIE_TRNRD73", - "PCIE_TRNRD74", - "PCIE_TRNRD75", - "PCIE_TRNRD76", - "PCIE_TRNRD77", - "PCIE_TRNRD78", - "PCIE_TRNRD79", - "PCIE_TRNRD8", - "PCIE_TRNRD80", - "PCIE_TRNRD81", - "PCIE_TRNRD82", - "PCIE_TRNRD83", - "PCIE_TRNRD84", - "PCIE_TRNRD85", - "PCIE_TRNRD86", - "PCIE_TRNRD87", - "PCIE_TRNRD88", - "PCIE_TRNRD89", - "PCIE_TRNRD9", - "PCIE_TRNRD90", - "PCIE_TRNRD91", - "PCIE_TRNRD92", - "PCIE_TRNRD93", - "PCIE_TRNRD94", - "PCIE_TRNRD95", - "PCIE_TRNRD96", - "PCIE_TRNRD97", - "PCIE_TRNRD98", - "PCIE_TRNRD99", - "PCIE_TRNRDLLPDATA0", - "PCIE_TRNRDLLPDATA1", - "PCIE_TRNRDLLPDATA10", - "PCIE_TRNRDLLPDATA11", - "PCIE_TRNRDLLPDATA12", - "PCIE_TRNRDLLPDATA13", - "PCIE_TRNRDLLPDATA14", - "PCIE_TRNRDLLPDATA15", - "PCIE_TRNRDLLPDATA16", - "PCIE_TRNRDLLPDATA17", - "PCIE_TRNRDLLPDATA18", - "PCIE_TRNRDLLPDATA19", - "PCIE_TRNRDLLPDATA2", - "PCIE_TRNRDLLPDATA20", - "PCIE_TRNRDLLPDATA21", - "PCIE_TRNRDLLPDATA22", - "PCIE_TRNRDLLPDATA23", - "PCIE_TRNRDLLPDATA24", - "PCIE_TRNRDLLPDATA25", - "PCIE_TRNRDLLPDATA26", - "PCIE_TRNRDLLPDATA27", - "PCIE_TRNRDLLPDATA28", - "PCIE_TRNRDLLPDATA29", - "PCIE_TRNRDLLPDATA3", - "PCIE_TRNRDLLPDATA30", - "PCIE_TRNRDLLPDATA31", - "PCIE_TRNRDLLPDATA32", - "PCIE_TRNRDLLPDATA33", - "PCIE_TRNRDLLPDATA34", - "PCIE_TRNRDLLPDATA35", - "PCIE_TRNRDLLPDATA36", - "PCIE_TRNRDLLPDATA37", - "PCIE_TRNRDLLPDATA38", - "PCIE_TRNRDLLPDATA39", - "PCIE_TRNRDLLPDATA4", - "PCIE_TRNRDLLPDATA40", - "PCIE_TRNRDLLPDATA41", - "PCIE_TRNRDLLPDATA42", - "PCIE_TRNRDLLPDATA43", - "PCIE_TRNRDLLPDATA44", - "PCIE_TRNRDLLPDATA45", - "PCIE_TRNRDLLPDATA46", - "PCIE_TRNRDLLPDATA47", - "PCIE_TRNRDLLPDATA48", - "PCIE_TRNRDLLPDATA49", - "PCIE_TRNRDLLPDATA5", - "PCIE_TRNRDLLPDATA50", - "PCIE_TRNRDLLPDATA51", - "PCIE_TRNRDLLPDATA52", - "PCIE_TRNRDLLPDATA53", - "PCIE_TRNRDLLPDATA54", - "PCIE_TRNRDLLPDATA55", - "PCIE_TRNRDLLPDATA56", - "PCIE_TRNRDLLPDATA57", - "PCIE_TRNRDLLPDATA58", - "PCIE_TRNRDLLPDATA59", - "PCIE_TRNRDLLPDATA6", - "PCIE_TRNRDLLPDATA60", - "PCIE_TRNRDLLPDATA61", - "PCIE_TRNRDLLPDATA62", - "PCIE_TRNRDLLPDATA63", - "PCIE_TRNRDLLPDATA7", - "PCIE_TRNRDLLPDATA8", - "PCIE_TRNRDLLPDATA9", - "PCIE_TRNRDLLPSRCRDY0", - "PCIE_TRNRDLLPSRCRDY1", - "PCIE_TRNRDSTRDY", - "PCIE_TRNRECRCERR", - "PCIE_TRNREOF", - "PCIE_TRNRERRFWD", - "PCIE_TRNRFCPRET", - "PCIE_TRNRNPOK", - "PCIE_TRNRNPREQ", - "PCIE_TRNRREM0", - "PCIE_TRNRREM1", - "PCIE_TRNRSOF", - "PCIE_TRNRSRCDSC", - "PCIE_TRNRSRCRDY", - "PCIE_TRNTBUFAV0", - "PCIE_TRNTBUFAV1", - "PCIE_TRNTBUFAV2", - "PCIE_TRNTBUFAV3", - "PCIE_TRNTBUFAV4", - "PCIE_TRNTBUFAV5", - "PCIE_TRNTCFGGNT", - "PCIE_TRNTCFGREQ", - "PCIE_TRNTD0", - "PCIE_TRNTD1", - "PCIE_TRNTD10", - "PCIE_TRNTD100", - "PCIE_TRNTD101", - "PCIE_TRNTD102", - "PCIE_TRNTD103", - "PCIE_TRNTD104", - "PCIE_TRNTD105", - "PCIE_TRNTD106", - "PCIE_TRNTD107", - "PCIE_TRNTD108", - "PCIE_TRNTD109", - "PCIE_TRNTD11", - "PCIE_TRNTD110", - "PCIE_TRNTD111", - "PCIE_TRNTD112", - "PCIE_TRNTD113", - "PCIE_TRNTD114", - "PCIE_TRNTD115", - "PCIE_TRNTD116", - "PCIE_TRNTD117", - "PCIE_TRNTD118", - "PCIE_TRNTD119", - "PCIE_TRNTD12", - "PCIE_TRNTD120", - "PCIE_TRNTD121", - "PCIE_TRNTD122", - "PCIE_TRNTD123", - "PCIE_TRNTD124", - "PCIE_TRNTD125", - "PCIE_TRNTD126", - "PCIE_TRNTD127", - "PCIE_TRNTD13", - "PCIE_TRNTD14", - "PCIE_TRNTD15", - "PCIE_TRNTD16", - "PCIE_TRNTD17", - "PCIE_TRNTD18", - "PCIE_TRNTD19", - "PCIE_TRNTD2", - "PCIE_TRNTD20", - "PCIE_TRNTD21", - "PCIE_TRNTD22", - "PCIE_TRNTD23", - "PCIE_TRNTD24", - "PCIE_TRNTD25", - "PCIE_TRNTD26", - "PCIE_TRNTD27", - "PCIE_TRNTD28", - "PCIE_TRNTD29", - "PCIE_TRNTD3", - "PCIE_TRNTD30", - "PCIE_TRNTD31", - "PCIE_TRNTD32", - "PCIE_TRNTD33", - "PCIE_TRNTD34", - "PCIE_TRNTD35", - "PCIE_TRNTD36", - "PCIE_TRNTD37", - "PCIE_TRNTD38", - "PCIE_TRNTD39", - "PCIE_TRNTD4", - "PCIE_TRNTD40", - "PCIE_TRNTD41", - "PCIE_TRNTD42", - "PCIE_TRNTD43", - "PCIE_TRNTD44", - "PCIE_TRNTD45", - "PCIE_TRNTD46", - "PCIE_TRNTD47", - "PCIE_TRNTD48", - "PCIE_TRNTD49", - "PCIE_TRNTD5", - "PCIE_TRNTD50", - "PCIE_TRNTD51", - "PCIE_TRNTD52", - "PCIE_TRNTD53", - "PCIE_TRNTD54", - "PCIE_TRNTD55", - "PCIE_TRNTD56", - "PCIE_TRNTD57", - "PCIE_TRNTD58", - "PCIE_TRNTD59", - "PCIE_TRNTD6", - "PCIE_TRNTD60", - "PCIE_TRNTD61", - "PCIE_TRNTD62", - "PCIE_TRNTD63", - "PCIE_TRNTD64", - "PCIE_TRNTD65", - "PCIE_TRNTD66", - "PCIE_TRNTD67", - "PCIE_TRNTD68", - "PCIE_TRNTD69", - "PCIE_TRNTD7", - "PCIE_TRNTD70", - "PCIE_TRNTD71", - "PCIE_TRNTD72", - "PCIE_TRNTD73", - "PCIE_TRNTD74", - "PCIE_TRNTD75", - "PCIE_TRNTD76", - "PCIE_TRNTD77", - "PCIE_TRNTD78", - "PCIE_TRNTD79", - "PCIE_TRNTD8", - "PCIE_TRNTD80", - "PCIE_TRNTD81", - "PCIE_TRNTD82", - "PCIE_TRNTD83", - "PCIE_TRNTD84", - "PCIE_TRNTD85", - "PCIE_TRNTD86", - "PCIE_TRNTD87", - "PCIE_TRNTD88", - "PCIE_TRNTD89", - "PCIE_TRNTD9", - "PCIE_TRNTD90", - "PCIE_TRNTD91", - "PCIE_TRNTD92", - "PCIE_TRNTD93", - "PCIE_TRNTD94", - "PCIE_TRNTD95", - "PCIE_TRNTD96", - "PCIE_TRNTD97", - "PCIE_TRNTD98", - "PCIE_TRNTD99", - "PCIE_TRNTDLLPDATA0", - "PCIE_TRNTDLLPDATA1", - "PCIE_TRNTDLLPDATA10", - "PCIE_TRNTDLLPDATA11", - "PCIE_TRNTDLLPDATA12", - "PCIE_TRNTDLLPDATA13", - "PCIE_TRNTDLLPDATA14", - "PCIE_TRNTDLLPDATA15", - "PCIE_TRNTDLLPDATA16", - "PCIE_TRNTDLLPDATA17", - "PCIE_TRNTDLLPDATA18", - "PCIE_TRNTDLLPDATA19", - "PCIE_TRNTDLLPDATA2", - "PCIE_TRNTDLLPDATA20", - "PCIE_TRNTDLLPDATA21", - "PCIE_TRNTDLLPDATA22", - "PCIE_TRNTDLLPDATA23", - "PCIE_TRNTDLLPDATA24", - "PCIE_TRNTDLLPDATA25", - "PCIE_TRNTDLLPDATA26", - "PCIE_TRNTDLLPDATA27", - "PCIE_TRNTDLLPDATA28", - "PCIE_TRNTDLLPDATA29", - "PCIE_TRNTDLLPDATA3", - "PCIE_TRNTDLLPDATA30", - "PCIE_TRNTDLLPDATA31", - "PCIE_TRNTDLLPDATA4", - "PCIE_TRNTDLLPDATA5", - "PCIE_TRNTDLLPDATA6", - "PCIE_TRNTDLLPDATA7", - "PCIE_TRNTDLLPDATA8", - "PCIE_TRNTDLLPDATA9", - "PCIE_TRNTDLLPDSTRDY", - "PCIE_TRNTDLLPSRCRDY", - "PCIE_TRNTDSTRDY0", - "PCIE_TRNTDSTRDY1", - "PCIE_TRNTDSTRDY2", - "PCIE_TRNTDSTRDY3", - "PCIE_TRNTECRCGEN", - "PCIE_TRNTEOF", - "PCIE_TRNTERRDROP", - "PCIE_TRNTERRFWD", - "PCIE_TRNTREM0", - "PCIE_TRNTREM1", - "PCIE_TRNTSOF", - "PCIE_TRNTSRCDSC", - "PCIE_TRNTSRCRDY", - "PCIE_TRNTSTR", - "PCIE_USERCLK", - "PCIE_USERCLK2", - "PCIE_USERCLKPREBUF", - "PCIE_USERCLKPREBUFEN", - "PCIE_USERRSTN", - "PCIE_WL1END0_0", - "PCIE_WL1END0_1", - "PCIE_WL1END0_10", - "PCIE_WL1END0_11", - "PCIE_WL1END0_12", - "PCIE_WL1END0_13", - "PCIE_WL1END0_14", - "PCIE_WL1END0_15", - "PCIE_WL1END0_16", - "PCIE_WL1END0_17", - "PCIE_WL1END0_18", - "PCIE_WL1END0_19", - "PCIE_WL1END0_2", - "PCIE_WL1END0_3", - "PCIE_WL1END0_4", - "PCIE_WL1END0_5", - "PCIE_WL1END0_6", - "PCIE_WL1END0_7", - "PCIE_WL1END0_8", - "PCIE_WL1END0_9", - "PCIE_WL1END1_0", - "PCIE_WL1END1_1", - "PCIE_WL1END1_10", - "PCIE_WL1END1_11", - "PCIE_WL1END1_12", - "PCIE_WL1END1_13", - "PCIE_WL1END1_14", - "PCIE_WL1END1_15", - "PCIE_WL1END1_16", - "PCIE_WL1END1_17", - "PCIE_WL1END1_18", - "PCIE_WL1END1_19", - "PCIE_WL1END1_2", - "PCIE_WL1END1_3", - "PCIE_WL1END1_4", - "PCIE_WL1END1_5", - "PCIE_WL1END1_6", - "PCIE_WL1END1_7", - "PCIE_WL1END1_8", - "PCIE_WL1END1_9", - "PCIE_WL1END2_0", - "PCIE_WL1END2_1", - "PCIE_WL1END2_10", - "PCIE_WL1END2_11", - "PCIE_WL1END2_12", - "PCIE_WL1END2_13", - "PCIE_WL1END2_14", - "PCIE_WL1END2_15", - "PCIE_WL1END2_16", - "PCIE_WL1END2_17", - "PCIE_WL1END2_18", - "PCIE_WL1END2_19", - "PCIE_WL1END2_2", - "PCIE_WL1END2_3", - "PCIE_WL1END2_4", - "PCIE_WL1END2_5", - "PCIE_WL1END2_6", - "PCIE_WL1END2_7", - "PCIE_WL1END2_8", - "PCIE_WL1END2_9", - "PCIE_WL1END3_0", - "PCIE_WL1END3_1", - "PCIE_WL1END3_10", - "PCIE_WL1END3_11", - "PCIE_WL1END3_12", - "PCIE_WL1END3_13", - "PCIE_WL1END3_14", - "PCIE_WL1END3_15", - "PCIE_WL1END3_16", - "PCIE_WL1END3_17", - "PCIE_WL1END3_18", - "PCIE_WL1END3_19", - "PCIE_WL1END3_2", - "PCIE_WL1END3_3", - "PCIE_WL1END3_4", - "PCIE_WL1END3_5", - "PCIE_WL1END3_6", - "PCIE_WL1END3_7", - "PCIE_WL1END3_8", - "PCIE_WL1END3_9", - "PCIE_WR1END0_0", - "PCIE_WR1END0_1", - "PCIE_WR1END0_10", - "PCIE_WR1END0_11", - "PCIE_WR1END0_12", - "PCIE_WR1END0_13", - "PCIE_WR1END0_14", - "PCIE_WR1END0_15", - "PCIE_WR1END0_16", - "PCIE_WR1END0_17", - "PCIE_WR1END0_18", - "PCIE_WR1END0_19", - "PCIE_WR1END0_2", - "PCIE_WR1END0_3", - "PCIE_WR1END0_4", - "PCIE_WR1END0_5", - "PCIE_WR1END0_6", - "PCIE_WR1END0_7", - "PCIE_WR1END0_8", - "PCIE_WR1END0_9", - "PCIE_WR1END1_0", - "PCIE_WR1END1_1", - "PCIE_WR1END1_10", - "PCIE_WR1END1_11", - "PCIE_WR1END1_12", - "PCIE_WR1END1_13", - "PCIE_WR1END1_14", - "PCIE_WR1END1_15", - "PCIE_WR1END1_16", - "PCIE_WR1END1_17", - "PCIE_WR1END1_18", - "PCIE_WR1END1_19", - "PCIE_WR1END1_2", - "PCIE_WR1END1_3", - "PCIE_WR1END1_4", - "PCIE_WR1END1_5", - "PCIE_WR1END1_6", - "PCIE_WR1END1_7", - "PCIE_WR1END1_8", - "PCIE_WR1END1_9", - "PCIE_WR1END2_0", - "PCIE_WR1END2_1", - "PCIE_WR1END2_10", - "PCIE_WR1END2_11", - "PCIE_WR1END2_12", - "PCIE_WR1END2_13", - "PCIE_WR1END2_14", - "PCIE_WR1END2_15", - "PCIE_WR1END2_16", - "PCIE_WR1END2_17", - "PCIE_WR1END2_18", - "PCIE_WR1END2_19", - "PCIE_WR1END2_2", - "PCIE_WR1END2_3", - "PCIE_WR1END2_4", - "PCIE_WR1END2_5", - "PCIE_WR1END2_6", - "PCIE_WR1END2_7", - "PCIE_WR1END2_8", - "PCIE_WR1END2_9", - "PCIE_WR1END3_0", - "PCIE_WR1END3_1", - "PCIE_WR1END3_10", - "PCIE_WR1END3_11", - "PCIE_WR1END3_12", - "PCIE_WR1END3_13", - "PCIE_WR1END3_14", - "PCIE_WR1END3_15", - "PCIE_WR1END3_16", - "PCIE_WR1END3_17", - "PCIE_WR1END3_18", - "PCIE_WR1END3_19", - "PCIE_WR1END3_2", - "PCIE_WR1END3_3", - "PCIE_WR1END3_4", - "PCIE_WR1END3_5", - "PCIE_WR1END3_6", - "PCIE_WR1END3_7", - "PCIE_WR1END3_8", - "PCIE_WR1END3_9", - "PCIE_WW2A0_0", - "PCIE_WW2A0_1", - "PCIE_WW2A0_10", - "PCIE_WW2A0_11", - "PCIE_WW2A0_12", - "PCIE_WW2A0_13", - "PCIE_WW2A0_14", - "PCIE_WW2A0_15", - "PCIE_WW2A0_16", - "PCIE_WW2A0_17", - "PCIE_WW2A0_18", - "PCIE_WW2A0_19", - "PCIE_WW2A0_2", - "PCIE_WW2A0_3", - "PCIE_WW2A0_4", - "PCIE_WW2A0_5", - "PCIE_WW2A0_6", - "PCIE_WW2A0_7", - "PCIE_WW2A0_8", - "PCIE_WW2A0_9", - "PCIE_WW2A1_0", - "PCIE_WW2A1_1", - "PCIE_WW2A1_10", - "PCIE_WW2A1_11", - "PCIE_WW2A1_12", - "PCIE_WW2A1_13", - "PCIE_WW2A1_14", - "PCIE_WW2A1_15", - "PCIE_WW2A1_16", - "PCIE_WW2A1_17", - "PCIE_WW2A1_18", - "PCIE_WW2A1_19", - "PCIE_WW2A1_2", - "PCIE_WW2A1_3", - "PCIE_WW2A1_4", - "PCIE_WW2A1_5", - "PCIE_WW2A1_6", - "PCIE_WW2A1_7", - "PCIE_WW2A1_8", - "PCIE_WW2A1_9", - "PCIE_WW2A2_0", - "PCIE_WW2A2_1", - "PCIE_WW2A2_10", - "PCIE_WW2A2_11", - "PCIE_WW2A2_12", - "PCIE_WW2A2_13", - "PCIE_WW2A2_14", - "PCIE_WW2A2_15", - "PCIE_WW2A2_16", - "PCIE_WW2A2_17", - "PCIE_WW2A2_18", - "PCIE_WW2A2_19", - "PCIE_WW2A2_2", - "PCIE_WW2A2_3", - "PCIE_WW2A2_4", - "PCIE_WW2A2_5", - "PCIE_WW2A2_6", - "PCIE_WW2A2_7", - "PCIE_WW2A2_8", - "PCIE_WW2A2_9", - "PCIE_WW2A3_0", - "PCIE_WW2A3_1", - "PCIE_WW2A3_10", - "PCIE_WW2A3_11", - "PCIE_WW2A3_12", - "PCIE_WW2A3_13", - "PCIE_WW2A3_14", - "PCIE_WW2A3_15", - "PCIE_WW2A3_16", - "PCIE_WW2A3_17", - "PCIE_WW2A3_18", - "PCIE_WW2A3_19", - "PCIE_WW2A3_2", - "PCIE_WW2A3_3", - "PCIE_WW2A3_4", - "PCIE_WW2A3_5", - "PCIE_WW2A3_6", - "PCIE_WW2A3_7", - "PCIE_WW2A3_8", - "PCIE_WW2A3_9", - "PCIE_WW2END0_0", - "PCIE_WW2END0_1", - "PCIE_WW2END0_10", - "PCIE_WW2END0_11", - "PCIE_WW2END0_12", - "PCIE_WW2END0_13", - "PCIE_WW2END0_14", - "PCIE_WW2END0_15", - "PCIE_WW2END0_16", - "PCIE_WW2END0_17", - "PCIE_WW2END0_18", - "PCIE_WW2END0_19", - "PCIE_WW2END0_2", - "PCIE_WW2END0_3", - "PCIE_WW2END0_4", - "PCIE_WW2END0_5", - "PCIE_WW2END0_6", - "PCIE_WW2END0_7", - "PCIE_WW2END0_8", - "PCIE_WW2END0_9", - "PCIE_WW2END1_0", - "PCIE_WW2END1_1", - "PCIE_WW2END1_10", - "PCIE_WW2END1_11", - "PCIE_WW2END1_12", - "PCIE_WW2END1_13", - "PCIE_WW2END1_14", - "PCIE_WW2END1_15", - "PCIE_WW2END1_16", - "PCIE_WW2END1_17", - "PCIE_WW2END1_18", - "PCIE_WW2END1_19", - "PCIE_WW2END1_2", - "PCIE_WW2END1_3", - "PCIE_WW2END1_4", - "PCIE_WW2END1_5", - "PCIE_WW2END1_6", - "PCIE_WW2END1_7", - "PCIE_WW2END1_8", - "PCIE_WW2END1_9", - "PCIE_WW2END2_0", - "PCIE_WW2END2_1", - "PCIE_WW2END2_10", - "PCIE_WW2END2_11", - "PCIE_WW2END2_12", - "PCIE_WW2END2_13", - "PCIE_WW2END2_14", - "PCIE_WW2END2_15", - "PCIE_WW2END2_16", - "PCIE_WW2END2_17", - "PCIE_WW2END2_18", - "PCIE_WW2END2_19", - "PCIE_WW2END2_2", - "PCIE_WW2END2_3", - "PCIE_WW2END2_4", - "PCIE_WW2END2_5", - "PCIE_WW2END2_6", - "PCIE_WW2END2_7", - "PCIE_WW2END2_8", - "PCIE_WW2END2_9", - "PCIE_WW2END3_0", - "PCIE_WW2END3_1", - "PCIE_WW2END3_10", - "PCIE_WW2END3_11", - "PCIE_WW2END3_12", - "PCIE_WW2END3_13", - "PCIE_WW2END3_14", - "PCIE_WW2END3_15", - "PCIE_WW2END3_16", - "PCIE_WW2END3_17", - "PCIE_WW2END3_18", - "PCIE_WW2END3_19", - "PCIE_WW2END3_2", - "PCIE_WW2END3_3", - "PCIE_WW2END3_4", - "PCIE_WW2END3_5", - "PCIE_WW2END3_6", - "PCIE_WW2END3_7", - "PCIE_WW2END3_8", - "PCIE_WW2END3_9", - "PCIE_WW4A0_0", - "PCIE_WW4A0_1", - "PCIE_WW4A0_10", - "PCIE_WW4A0_11", - "PCIE_WW4A0_12", - "PCIE_WW4A0_13", - "PCIE_WW4A0_14", - "PCIE_WW4A0_15", - "PCIE_WW4A0_16", - "PCIE_WW4A0_17", - "PCIE_WW4A0_18", - "PCIE_WW4A0_19", - "PCIE_WW4A0_2", - "PCIE_WW4A0_3", - "PCIE_WW4A0_4", - "PCIE_WW4A0_5", - "PCIE_WW4A0_6", - "PCIE_WW4A0_7", - "PCIE_WW4A0_8", - "PCIE_WW4A0_9", - "PCIE_WW4A1_0", - "PCIE_WW4A1_1", - "PCIE_WW4A1_10", - "PCIE_WW4A1_11", - "PCIE_WW4A1_12", - "PCIE_WW4A1_13", - "PCIE_WW4A1_14", - "PCIE_WW4A1_15", - "PCIE_WW4A1_16", - "PCIE_WW4A1_17", - "PCIE_WW4A1_18", - "PCIE_WW4A1_19", - "PCIE_WW4A1_2", - "PCIE_WW4A1_3", - "PCIE_WW4A1_4", - "PCIE_WW4A1_5", - "PCIE_WW4A1_6", - "PCIE_WW4A1_7", - "PCIE_WW4A1_8", - "PCIE_WW4A1_9", - "PCIE_WW4A2_0", - "PCIE_WW4A2_1", - "PCIE_WW4A2_10", - "PCIE_WW4A2_11", - "PCIE_WW4A2_12", - "PCIE_WW4A2_13", - "PCIE_WW4A2_14", - "PCIE_WW4A2_15", - "PCIE_WW4A2_16", - "PCIE_WW4A2_17", - "PCIE_WW4A2_18", - "PCIE_WW4A2_19", - "PCIE_WW4A2_2", - "PCIE_WW4A2_3", - "PCIE_WW4A2_4", - "PCIE_WW4A2_5", - "PCIE_WW4A2_6", - "PCIE_WW4A2_7", - "PCIE_WW4A2_8", - "PCIE_WW4A2_9", - "PCIE_WW4A3_0", - "PCIE_WW4A3_1", - "PCIE_WW4A3_10", - "PCIE_WW4A3_11", - "PCIE_WW4A3_12", - "PCIE_WW4A3_13", - "PCIE_WW4A3_14", - "PCIE_WW4A3_15", - "PCIE_WW4A3_16", - "PCIE_WW4A3_17", - "PCIE_WW4A3_18", - "PCIE_WW4A3_19", - "PCIE_WW4A3_2", - "PCIE_WW4A3_3", - "PCIE_WW4A3_4", - "PCIE_WW4A3_5", - "PCIE_WW4A3_6", - "PCIE_WW4A3_7", - "PCIE_WW4A3_8", - "PCIE_WW4A3_9", - "PCIE_WW4B0_0", - "PCIE_WW4B0_1", - "PCIE_WW4B0_10", - "PCIE_WW4B0_11", - "PCIE_WW4B0_12", - "PCIE_WW4B0_13", - "PCIE_WW4B0_14", - "PCIE_WW4B0_15", - "PCIE_WW4B0_16", - "PCIE_WW4B0_17", - "PCIE_WW4B0_18", - "PCIE_WW4B0_19", - "PCIE_WW4B0_2", - "PCIE_WW4B0_3", - "PCIE_WW4B0_4", - "PCIE_WW4B0_5", - "PCIE_WW4B0_6", - "PCIE_WW4B0_7", - "PCIE_WW4B0_8", - "PCIE_WW4B0_9", - "PCIE_WW4B1_0", - "PCIE_WW4B1_1", - "PCIE_WW4B1_10", - "PCIE_WW4B1_11", - "PCIE_WW4B1_12", - "PCIE_WW4B1_13", - "PCIE_WW4B1_14", - "PCIE_WW4B1_15", - "PCIE_WW4B1_16", - "PCIE_WW4B1_17", - "PCIE_WW4B1_18", - "PCIE_WW4B1_19", - "PCIE_WW4B1_2", - "PCIE_WW4B1_3", - "PCIE_WW4B1_4", - "PCIE_WW4B1_5", - "PCIE_WW4B1_6", - "PCIE_WW4B1_7", - "PCIE_WW4B1_8", - "PCIE_WW4B1_9", - "PCIE_WW4B2_0", - "PCIE_WW4B2_1", - "PCIE_WW4B2_10", - "PCIE_WW4B2_11", - "PCIE_WW4B2_12", - "PCIE_WW4B2_13", - "PCIE_WW4B2_14", - "PCIE_WW4B2_15", - "PCIE_WW4B2_16", - "PCIE_WW4B2_17", - "PCIE_WW4B2_18", - "PCIE_WW4B2_19", - "PCIE_WW4B2_2", - "PCIE_WW4B2_3", - "PCIE_WW4B2_4", - "PCIE_WW4B2_5", - "PCIE_WW4B2_6", - "PCIE_WW4B2_7", - "PCIE_WW4B2_8", - "PCIE_WW4B2_9", - "PCIE_WW4B3_0", - "PCIE_WW4B3_1", - "PCIE_WW4B3_10", - "PCIE_WW4B3_11", - "PCIE_WW4B3_12", - "PCIE_WW4B3_13", - "PCIE_WW4B3_14", - "PCIE_WW4B3_15", - "PCIE_WW4B3_16", - "PCIE_WW4B3_17", - "PCIE_WW4B3_18", - "PCIE_WW4B3_19", - "PCIE_WW4B3_2", - "PCIE_WW4B3_3", - "PCIE_WW4B3_4", - "PCIE_WW4B3_5", - "PCIE_WW4B3_6", - "PCIE_WW4B3_7", - "PCIE_WW4B3_8", - "PCIE_WW4B3_9", - "PCIE_WW4C0_0", - "PCIE_WW4C0_1", - "PCIE_WW4C0_10", - "PCIE_WW4C0_11", - "PCIE_WW4C0_12", - "PCIE_WW4C0_13", - "PCIE_WW4C0_14", - "PCIE_WW4C0_15", - "PCIE_WW4C0_16", - "PCIE_WW4C0_17", - "PCIE_WW4C0_18", - "PCIE_WW4C0_19", - "PCIE_WW4C0_2", - "PCIE_WW4C0_3", - "PCIE_WW4C0_4", - "PCIE_WW4C0_5", - "PCIE_WW4C0_6", - "PCIE_WW4C0_7", - "PCIE_WW4C0_8", - "PCIE_WW4C0_9", - "PCIE_WW4C1_0", - "PCIE_WW4C1_1", - "PCIE_WW4C1_10", - "PCIE_WW4C1_11", - "PCIE_WW4C1_12", - "PCIE_WW4C1_13", - "PCIE_WW4C1_14", - "PCIE_WW4C1_15", - "PCIE_WW4C1_16", - "PCIE_WW4C1_17", - "PCIE_WW4C1_18", - "PCIE_WW4C1_19", - "PCIE_WW4C1_2", - "PCIE_WW4C1_3", - "PCIE_WW4C1_4", - "PCIE_WW4C1_5", - "PCIE_WW4C1_6", - "PCIE_WW4C1_7", - "PCIE_WW4C1_8", - "PCIE_WW4C1_9", - "PCIE_WW4C2_0", - "PCIE_WW4C2_1", - "PCIE_WW4C2_10", - "PCIE_WW4C2_11", - "PCIE_WW4C2_12", - "PCIE_WW4C2_13", - "PCIE_WW4C2_14", - "PCIE_WW4C2_15", - "PCIE_WW4C2_16", - "PCIE_WW4C2_17", - "PCIE_WW4C2_18", - "PCIE_WW4C2_19", - "PCIE_WW4C2_2", - "PCIE_WW4C2_3", - "PCIE_WW4C2_4", - "PCIE_WW4C2_5", - "PCIE_WW4C2_6", - "PCIE_WW4C2_7", - "PCIE_WW4C2_8", - "PCIE_WW4C2_9", - "PCIE_WW4C3_0", - "PCIE_WW4C3_1", - "PCIE_WW4C3_10", - "PCIE_WW4C3_11", - "PCIE_WW4C3_12", - "PCIE_WW4C3_13", - "PCIE_WW4C3_14", - "PCIE_WW4C3_15", - "PCIE_WW4C3_16", - "PCIE_WW4C3_17", - "PCIE_WW4C3_18", - "PCIE_WW4C3_19", - "PCIE_WW4C3_2", - "PCIE_WW4C3_3", - "PCIE_WW4C3_4", - "PCIE_WW4C3_5", - "PCIE_WW4C3_6", - "PCIE_WW4C3_7", - "PCIE_WW4C3_8", - "PCIE_WW4C3_9", - "PCIE_WW4END0_0", - "PCIE_WW4END0_1", - "PCIE_WW4END0_10", - "PCIE_WW4END0_11", - "PCIE_WW4END0_12", - "PCIE_WW4END0_13", - "PCIE_WW4END0_14", - "PCIE_WW4END0_15", - "PCIE_WW4END0_16", - "PCIE_WW4END0_17", - "PCIE_WW4END0_18", - "PCIE_WW4END0_19", - "PCIE_WW4END0_2", - "PCIE_WW4END0_3", - "PCIE_WW4END0_4", - "PCIE_WW4END0_5", - "PCIE_WW4END0_6", - "PCIE_WW4END0_7", - "PCIE_WW4END0_8", - "PCIE_WW4END0_9", - "PCIE_WW4END1_0", - "PCIE_WW4END1_1", - "PCIE_WW4END1_10", - "PCIE_WW4END1_11", - "PCIE_WW4END1_12", - "PCIE_WW4END1_13", - "PCIE_WW4END1_14", - "PCIE_WW4END1_15", - "PCIE_WW4END1_16", - "PCIE_WW4END1_17", - "PCIE_WW4END1_18", - "PCIE_WW4END1_19", - "PCIE_WW4END1_2", - "PCIE_WW4END1_3", - "PCIE_WW4END1_4", - "PCIE_WW4END1_5", - "PCIE_WW4END1_6", - "PCIE_WW4END1_7", - "PCIE_WW4END1_8", - "PCIE_WW4END1_9", - "PCIE_WW4END2_0", - "PCIE_WW4END2_1", - "PCIE_WW4END2_10", - "PCIE_WW4END2_11", - "PCIE_WW4END2_12", - "PCIE_WW4END2_13", - "PCIE_WW4END2_14", - "PCIE_WW4END2_15", - "PCIE_WW4END2_16", - "PCIE_WW4END2_17", - "PCIE_WW4END2_18", - "PCIE_WW4END2_19", - "PCIE_WW4END2_2", - "PCIE_WW4END2_3", - "PCIE_WW4END2_4", - "PCIE_WW4END2_5", - "PCIE_WW4END2_6", - "PCIE_WW4END2_7", - "PCIE_WW4END2_8", - "PCIE_WW4END2_9", - "PCIE_WW4END3_0", - "PCIE_WW4END3_1", - "PCIE_WW4END3_10", - "PCIE_WW4END3_11", - "PCIE_WW4END3_12", - "PCIE_WW4END3_13", - "PCIE_WW4END3_14", - "PCIE_WW4END3_15", - "PCIE_WW4END3_16", - "PCIE_WW4END3_17", - "PCIE_WW4END3_18", - "PCIE_WW4END3_19", - "PCIE_WW4END3_2", - "PCIE_WW4END3_3", - "PCIE_WW4END3_4", - "PCIE_WW4END3_5", - "PCIE_WW4END3_6", - "PCIE_WW4END3_7", - "PCIE_WW4END3_8", - "PCIE_WW4END3_9", - "PCIE_XILUNCONNOUT0", - "PCIE_XILUNCONNOUT1", - "PCIE_XILUNCONNOUT10", - "PCIE_XILUNCONNOUT11", - "PCIE_XILUNCONNOUT12", - "PCIE_XILUNCONNOUT13", - "PCIE_XILUNCONNOUT14", - "PCIE_XILUNCONNOUT15", - "PCIE_XILUNCONNOUT16", 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"PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY24->PCIE_INT_INTERFACE_IMUX_L_OUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY24" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY25->PCIE_INT_INTERFACE_IMUX_L_OUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY25" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY26->PCIE_INT_INTERFACE_IMUX_L_OUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY26" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY27->PCIE_INT_INTERFACE_IMUX_L_OUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY27" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY28->PCIE_INT_INTERFACE_IMUX_L_OUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY28" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY29->PCIE_INT_INTERFACE_IMUX_L_OUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY29" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY3->PCIE_INT_INTERFACE_IMUX_L_OUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY3" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY30->PCIE_INT_INTERFACE_IMUX_L_OUT30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY30" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY31->PCIE_INT_INTERFACE_IMUX_L_OUT31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY31" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY32->PCIE_INT_INTERFACE_IMUX_L_OUT32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY32" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY33->PCIE_INT_INTERFACE_IMUX_L_OUT33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY33" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY34->PCIE_INT_INTERFACE_IMUX_L_OUT34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY34" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY35->PCIE_INT_INTERFACE_IMUX_L_OUT35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY35" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY36->PCIE_INT_INTERFACE_IMUX_L_OUT36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY36" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY37->PCIE_INT_INTERFACE_IMUX_L_OUT37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY37" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY38->PCIE_INT_INTERFACE_IMUX_L_OUT38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY38" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY39->PCIE_INT_INTERFACE_IMUX_L_OUT39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY39" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY4->PCIE_INT_INTERFACE_IMUX_L_OUT4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY4" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY40->PCIE_INT_INTERFACE_IMUX_L_OUT40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY40" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY41->PCIE_INT_INTERFACE_IMUX_L_OUT41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY41" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY42->PCIE_INT_INTERFACE_IMUX_L_OUT42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY42" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY43->PCIE_INT_INTERFACE_IMUX_L_OUT43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY43" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY44->PCIE_INT_INTERFACE_IMUX_L_OUT44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY44" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY45->PCIE_INT_INTERFACE_IMUX_L_OUT45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY45" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY46->PCIE_INT_INTERFACE_IMUX_L_OUT46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY46" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY47->PCIE_INT_INTERFACE_IMUX_L_OUT47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY47" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY5->PCIE_INT_INTERFACE_IMUX_L_OUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY5" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY6->PCIE_INT_INTERFACE_IMUX_L_OUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY6" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY7->PCIE_INT_INTERFACE_IMUX_L_OUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY7" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY8->PCIE_INT_INTERFACE_IMUX_L_OUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY8" }, "PCIE_INT_INTERFACE_L.PCIE_INT_INTERFACE_IMUX_L_DELAY9->PCIE_INT_INTERFACE_IMUX_L_OUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_L_OUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_L_DELAY9" } }, "sites": [], "tile_type": "PCIE_INT_INTERFACE_L", - "wires": [ - "INT_INTERFACE_BLOCK_OUTS_L_B0", - "INT_INTERFACE_BLOCK_OUTS_L_B1", - "INT_INTERFACE_BLOCK_OUTS_L_B2", - "INT_INTERFACE_BLOCK_OUTS_L_B3", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_BYP1", - "INT_INTERFACE_BYP2", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_BYP5", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_CLK0", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_EE2A0", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_ER1BEG1", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_LH1", - "INT_INTERFACE_LH10", - "INT_INTERFACE_LH11", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH2", - "INT_INTERFACE_LH3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_LH5", - "INT_INTERFACE_LH6", - "INT_INTERFACE_LH7", - "INT_INTERFACE_LH8", - "INT_INTERFACE_LH9", - "INT_INTERFACE_LOGIC_OUTS_L0", - "INT_INTERFACE_LOGIC_OUTS_L1", - "INT_INTERFACE_LOGIC_OUTS_L10", - "INT_INTERFACE_LOGIC_OUTS_L11", - "INT_INTERFACE_LOGIC_OUTS_L12", - "INT_INTERFACE_LOGIC_OUTS_L13", - "INT_INTERFACE_LOGIC_OUTS_L14", - "INT_INTERFACE_LOGIC_OUTS_L15", - "INT_INTERFACE_LOGIC_OUTS_L16", - "INT_INTERFACE_LOGIC_OUTS_L17", - "INT_INTERFACE_LOGIC_OUTS_L18", - "INT_INTERFACE_LOGIC_OUTS_L19", - "INT_INTERFACE_LOGIC_OUTS_L2", - "INT_INTERFACE_LOGIC_OUTS_L20", - "INT_INTERFACE_LOGIC_OUTS_L21", - "INT_INTERFACE_LOGIC_OUTS_L22", - "INT_INTERFACE_LOGIC_OUTS_L23", - "INT_INTERFACE_LOGIC_OUTS_L3", - "INT_INTERFACE_LOGIC_OUTS_L4", - "INT_INTERFACE_LOGIC_OUTS_L5", - "INT_INTERFACE_LOGIC_OUTS_L6", - "INT_INTERFACE_LOGIC_OUTS_L7", - "INT_INTERFACE_LOGIC_OUTS_L8", - "INT_INTERFACE_LOGIC_OUTS_L9", - "INT_INTERFACE_LOGIC_OUTS_L_B0", - "INT_INTERFACE_LOGIC_OUTS_L_B1", - "INT_INTERFACE_LOGIC_OUTS_L_B10", - "INT_INTERFACE_LOGIC_OUTS_L_B11", - "INT_INTERFACE_LOGIC_OUTS_L_B12", - "INT_INTERFACE_LOGIC_OUTS_L_B13", - "INT_INTERFACE_LOGIC_OUTS_L_B14", - "INT_INTERFACE_LOGIC_OUTS_L_B15", - "INT_INTERFACE_LOGIC_OUTS_L_B16", - "INT_INTERFACE_LOGIC_OUTS_L_B17", - "INT_INTERFACE_LOGIC_OUTS_L_B18", - "INT_INTERFACE_LOGIC_OUTS_L_B19", - "INT_INTERFACE_LOGIC_OUTS_L_B2", - "INT_INTERFACE_LOGIC_OUTS_L_B20", - "INT_INTERFACE_LOGIC_OUTS_L_B21", - "INT_INTERFACE_LOGIC_OUTS_L_B22", - "INT_INTERFACE_LOGIC_OUTS_L_B23", - "INT_INTERFACE_LOGIC_OUTS_L_B3", - "INT_INTERFACE_LOGIC_OUTS_L_B4", - "INT_INTERFACE_LOGIC_OUTS_L_B5", - "INT_INTERFACE_LOGIC_OUTS_L_B6", - "INT_INTERFACE_LOGIC_OUTS_L_B7", - "INT_INTERFACE_LOGIC_OUTS_L_B8", - "INT_INTERFACE_LOGIC_OUTS_L_B9", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW4END3", - "PCIE_INT_INTERFACE_IMUX_L0", - "PCIE_INT_INTERFACE_IMUX_L1", - "PCIE_INT_INTERFACE_IMUX_L10", - "PCIE_INT_INTERFACE_IMUX_L11", - "PCIE_INT_INTERFACE_IMUX_L12", - "PCIE_INT_INTERFACE_IMUX_L13", - "PCIE_INT_INTERFACE_IMUX_L14", - "PCIE_INT_INTERFACE_IMUX_L15", - "PCIE_INT_INTERFACE_IMUX_L16", - "PCIE_INT_INTERFACE_IMUX_L17", - "PCIE_INT_INTERFACE_IMUX_L18", - "PCIE_INT_INTERFACE_IMUX_L19", - "PCIE_INT_INTERFACE_IMUX_L2", - "PCIE_INT_INTERFACE_IMUX_L20", - "PCIE_INT_INTERFACE_IMUX_L21", - "PCIE_INT_INTERFACE_IMUX_L22", - "PCIE_INT_INTERFACE_IMUX_L23", - "PCIE_INT_INTERFACE_IMUX_L24", - "PCIE_INT_INTERFACE_IMUX_L25", - "PCIE_INT_INTERFACE_IMUX_L26", - "PCIE_INT_INTERFACE_IMUX_L27", - "PCIE_INT_INTERFACE_IMUX_L28", - "PCIE_INT_INTERFACE_IMUX_L29", - "PCIE_INT_INTERFACE_IMUX_L3", - "PCIE_INT_INTERFACE_IMUX_L30", - "PCIE_INT_INTERFACE_IMUX_L31", - "PCIE_INT_INTERFACE_IMUX_L32", - "PCIE_INT_INTERFACE_IMUX_L33", - "PCIE_INT_INTERFACE_IMUX_L34", - "PCIE_INT_INTERFACE_IMUX_L35", - "PCIE_INT_INTERFACE_IMUX_L36", - "PCIE_INT_INTERFACE_IMUX_L37", - "PCIE_INT_INTERFACE_IMUX_L38", - "PCIE_INT_INTERFACE_IMUX_L39", - "PCIE_INT_INTERFACE_IMUX_L4", - "PCIE_INT_INTERFACE_IMUX_L40", - "PCIE_INT_INTERFACE_IMUX_L41", - "PCIE_INT_INTERFACE_IMUX_L42", - "PCIE_INT_INTERFACE_IMUX_L43", - "PCIE_INT_INTERFACE_IMUX_L44", - "PCIE_INT_INTERFACE_IMUX_L45", - "PCIE_INT_INTERFACE_IMUX_L46", - "PCIE_INT_INTERFACE_IMUX_L47", - "PCIE_INT_INTERFACE_IMUX_L5", - "PCIE_INT_INTERFACE_IMUX_L6", - "PCIE_INT_INTERFACE_IMUX_L7", - "PCIE_INT_INTERFACE_IMUX_L8", - "PCIE_INT_INTERFACE_IMUX_L9", - "PCIE_INT_INTERFACE_IMUX_L_DELAY0", - "PCIE_INT_INTERFACE_IMUX_L_DELAY1", - "PCIE_INT_INTERFACE_IMUX_L_DELAY10", - "PCIE_INT_INTERFACE_IMUX_L_DELAY11", - "PCIE_INT_INTERFACE_IMUX_L_DELAY12", - "PCIE_INT_INTERFACE_IMUX_L_DELAY13", - "PCIE_INT_INTERFACE_IMUX_L_DELAY14", - "PCIE_INT_INTERFACE_IMUX_L_DELAY15", - "PCIE_INT_INTERFACE_IMUX_L_DELAY16", - "PCIE_INT_INTERFACE_IMUX_L_DELAY17", - "PCIE_INT_INTERFACE_IMUX_L_DELAY18", - "PCIE_INT_INTERFACE_IMUX_L_DELAY19", - "PCIE_INT_INTERFACE_IMUX_L_DELAY2", - "PCIE_INT_INTERFACE_IMUX_L_DELAY20", - "PCIE_INT_INTERFACE_IMUX_L_DELAY21", - "PCIE_INT_INTERFACE_IMUX_L_DELAY22", - "PCIE_INT_INTERFACE_IMUX_L_DELAY23", - "PCIE_INT_INTERFACE_IMUX_L_DELAY24", - "PCIE_INT_INTERFACE_IMUX_L_DELAY25", - "PCIE_INT_INTERFACE_IMUX_L_DELAY26", - "PCIE_INT_INTERFACE_IMUX_L_DELAY27", - "PCIE_INT_INTERFACE_IMUX_L_DELAY28", - "PCIE_INT_INTERFACE_IMUX_L_DELAY29", - "PCIE_INT_INTERFACE_IMUX_L_DELAY3", - "PCIE_INT_INTERFACE_IMUX_L_DELAY30", - "PCIE_INT_INTERFACE_IMUX_L_DELAY31", - "PCIE_INT_INTERFACE_IMUX_L_DELAY32", - "PCIE_INT_INTERFACE_IMUX_L_DELAY33", - "PCIE_INT_INTERFACE_IMUX_L_DELAY34", - "PCIE_INT_INTERFACE_IMUX_L_DELAY35", - "PCIE_INT_INTERFACE_IMUX_L_DELAY36", - "PCIE_INT_INTERFACE_IMUX_L_DELAY37", - "PCIE_INT_INTERFACE_IMUX_L_DELAY38", - "PCIE_INT_INTERFACE_IMUX_L_DELAY39", - "PCIE_INT_INTERFACE_IMUX_L_DELAY4", - "PCIE_INT_INTERFACE_IMUX_L_DELAY40", - "PCIE_INT_INTERFACE_IMUX_L_DELAY41", - "PCIE_INT_INTERFACE_IMUX_L_DELAY42", - "PCIE_INT_INTERFACE_IMUX_L_DELAY43", - "PCIE_INT_INTERFACE_IMUX_L_DELAY44", - "PCIE_INT_INTERFACE_IMUX_L_DELAY45", - "PCIE_INT_INTERFACE_IMUX_L_DELAY46", - "PCIE_INT_INTERFACE_IMUX_L_DELAY47", - "PCIE_INT_INTERFACE_IMUX_L_DELAY5", - "PCIE_INT_INTERFACE_IMUX_L_DELAY6", - "PCIE_INT_INTERFACE_IMUX_L_DELAY7", - "PCIE_INT_INTERFACE_IMUX_L_DELAY8", - "PCIE_INT_INTERFACE_IMUX_L_DELAY9", - "PCIE_INT_INTERFACE_IMUX_L_OUT0", - "PCIE_INT_INTERFACE_IMUX_L_OUT1", - "PCIE_INT_INTERFACE_IMUX_L_OUT10", - "PCIE_INT_INTERFACE_IMUX_L_OUT11", - "PCIE_INT_INTERFACE_IMUX_L_OUT12", - "PCIE_INT_INTERFACE_IMUX_L_OUT13", - "PCIE_INT_INTERFACE_IMUX_L_OUT14", - "PCIE_INT_INTERFACE_IMUX_L_OUT15", - "PCIE_INT_INTERFACE_IMUX_L_OUT16", - "PCIE_INT_INTERFACE_IMUX_L_OUT17", - "PCIE_INT_INTERFACE_IMUX_L_OUT18", - "PCIE_INT_INTERFACE_IMUX_L_OUT19", - "PCIE_INT_INTERFACE_IMUX_L_OUT2", - "PCIE_INT_INTERFACE_IMUX_L_OUT20", - "PCIE_INT_INTERFACE_IMUX_L_OUT21", - "PCIE_INT_INTERFACE_IMUX_L_OUT22", - "PCIE_INT_INTERFACE_IMUX_L_OUT23", - "PCIE_INT_INTERFACE_IMUX_L_OUT24", - "PCIE_INT_INTERFACE_IMUX_L_OUT25", - "PCIE_INT_INTERFACE_IMUX_L_OUT26", - "PCIE_INT_INTERFACE_IMUX_L_OUT27", - "PCIE_INT_INTERFACE_IMUX_L_OUT28", - "PCIE_INT_INTERFACE_IMUX_L_OUT29", - "PCIE_INT_INTERFACE_IMUX_L_OUT3", - "PCIE_INT_INTERFACE_IMUX_L_OUT30", - "PCIE_INT_INTERFACE_IMUX_L_OUT31", - "PCIE_INT_INTERFACE_IMUX_L_OUT32", - "PCIE_INT_INTERFACE_IMUX_L_OUT33", - "PCIE_INT_INTERFACE_IMUX_L_OUT34", - "PCIE_INT_INTERFACE_IMUX_L_OUT35", - "PCIE_INT_INTERFACE_IMUX_L_OUT36", - "PCIE_INT_INTERFACE_IMUX_L_OUT37", - "PCIE_INT_INTERFACE_IMUX_L_OUT38", - "PCIE_INT_INTERFACE_IMUX_L_OUT39", - "PCIE_INT_INTERFACE_IMUX_L_OUT4", - "PCIE_INT_INTERFACE_IMUX_L_OUT40", - "PCIE_INT_INTERFACE_IMUX_L_OUT41", - "PCIE_INT_INTERFACE_IMUX_L_OUT42", - "PCIE_INT_INTERFACE_IMUX_L_OUT43", - "PCIE_INT_INTERFACE_IMUX_L_OUT44", - "PCIE_INT_INTERFACE_IMUX_L_OUT45", - "PCIE_INT_INTERFACE_IMUX_L_OUT46", - "PCIE_INT_INTERFACE_IMUX_L_OUT47", - "PCIE_INT_INTERFACE_IMUX_L_OUT5", - "PCIE_INT_INTERFACE_IMUX_L_OUT6", - "PCIE_INT_INTERFACE_IMUX_L_OUT7", - "PCIE_INT_INTERFACE_IMUX_L_OUT8", - "PCIE_INT_INTERFACE_IMUX_L_OUT9" - ] + "wires": { + "INT_INTERFACE_BLOCK_OUTS_L_B0": null, + "INT_INTERFACE_BLOCK_OUTS_L_B1": null, + "INT_INTERFACE_BLOCK_OUTS_L_B2": null, + "INT_INTERFACE_BLOCK_OUTS_L_B3": null, + "INT_INTERFACE_BYP0": null, + "INT_INTERFACE_BYP1": null, + "INT_INTERFACE_BYP2": null, + "INT_INTERFACE_BYP3": null, + "INT_INTERFACE_BYP4": null, + "INT_INTERFACE_BYP5": null, + "INT_INTERFACE_BYP6": null, + "INT_INTERFACE_BYP7": null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS_L0": null, + "INT_INTERFACE_LOGIC_OUTS_L1": null, + "INT_INTERFACE_LOGIC_OUTS_L10": null, + "INT_INTERFACE_LOGIC_OUTS_L11": null, + "INT_INTERFACE_LOGIC_OUTS_L12": null, + "INT_INTERFACE_LOGIC_OUTS_L13": null, + "INT_INTERFACE_LOGIC_OUTS_L14": null, + "INT_INTERFACE_LOGIC_OUTS_L15": null, + "INT_INTERFACE_LOGIC_OUTS_L16": null, + "INT_INTERFACE_LOGIC_OUTS_L17": null, + "INT_INTERFACE_LOGIC_OUTS_L18": null, + "INT_INTERFACE_LOGIC_OUTS_L19": null, + "INT_INTERFACE_LOGIC_OUTS_L2": null, + "INT_INTERFACE_LOGIC_OUTS_L20": null, + "INT_INTERFACE_LOGIC_OUTS_L21": null, + "INT_INTERFACE_LOGIC_OUTS_L22": null, + "INT_INTERFACE_LOGIC_OUTS_L23": null, + "INT_INTERFACE_LOGIC_OUTS_L3": null, + "INT_INTERFACE_LOGIC_OUTS_L4": null, + "INT_INTERFACE_LOGIC_OUTS_L5": null, + "INT_INTERFACE_LOGIC_OUTS_L6": null, + "INT_INTERFACE_LOGIC_OUTS_L7": null, + "INT_INTERFACE_LOGIC_OUTS_L8": null, + "INT_INTERFACE_LOGIC_OUTS_L9": null, + "INT_INTERFACE_LOGIC_OUTS_L_B0": null, + "INT_INTERFACE_LOGIC_OUTS_L_B1": null, + "INT_INTERFACE_LOGIC_OUTS_L_B10": null, + "INT_INTERFACE_LOGIC_OUTS_L_B11": null, + "INT_INTERFACE_LOGIC_OUTS_L_B12": null, + "INT_INTERFACE_LOGIC_OUTS_L_B13": null, + "INT_INTERFACE_LOGIC_OUTS_L_B14": null, + "INT_INTERFACE_LOGIC_OUTS_L_B15": null, + "INT_INTERFACE_LOGIC_OUTS_L_B16": null, + "INT_INTERFACE_LOGIC_OUTS_L_B17": null, + "INT_INTERFACE_LOGIC_OUTS_L_B18": null, + "INT_INTERFACE_LOGIC_OUTS_L_B19": null, + "INT_INTERFACE_LOGIC_OUTS_L_B2": null, + "INT_INTERFACE_LOGIC_OUTS_L_B20": null, + "INT_INTERFACE_LOGIC_OUTS_L_B21": null, + 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"res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY20" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY21->PCIE_INT_INTERFACE_IMUX_OUT21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY21" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY22->PCIE_INT_INTERFACE_IMUX_OUT22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY22" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY23->PCIE_INT_INTERFACE_IMUX_OUT23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY23" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY24->PCIE_INT_INTERFACE_IMUX_OUT24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY24" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY25->PCIE_INT_INTERFACE_IMUX_OUT25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY25" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY26->PCIE_INT_INTERFACE_IMUX_OUT26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY26" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY27->PCIE_INT_INTERFACE_IMUX_OUT27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY27" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY28->PCIE_INT_INTERFACE_IMUX_OUT28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY28" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY29->PCIE_INT_INTERFACE_IMUX_OUT29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY29" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY3->PCIE_INT_INTERFACE_IMUX_OUT3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY3" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY30->PCIE_INT_INTERFACE_IMUX_OUT30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY30" }, 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"delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY35" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY36->PCIE_INT_INTERFACE_IMUX_OUT36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY36" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY37->PCIE_INT_INTERFACE_IMUX_OUT37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY37" }, 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"res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY4" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY40->PCIE_INT_INTERFACE_IMUX_OUT40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY40" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY41->PCIE_INT_INTERFACE_IMUX_OUT41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY41" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY42->PCIE_INT_INTERFACE_IMUX_OUT42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY42" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY43->PCIE_INT_INTERFACE_IMUX_OUT43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY43" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY44->PCIE_INT_INTERFACE_IMUX_OUT44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY44" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY45->PCIE_INT_INTERFACE_IMUX_OUT45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY45" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY46->PCIE_INT_INTERFACE_IMUX_OUT46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY46" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY47->PCIE_INT_INTERFACE_IMUX_OUT47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY47" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY5->PCIE_INT_INTERFACE_IMUX_OUT5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY5" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY6->PCIE_INT_INTERFACE_IMUX_OUT6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY6" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY7->PCIE_INT_INTERFACE_IMUX_OUT7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY7" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY8->PCIE_INT_INTERFACE_IMUX_OUT8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY8" }, "PCIE_INT_INTERFACE_R.PCIE_INT_INTERFACE_IMUX_DELAY9->PCIE_INT_INTERFACE_IMUX_OUT9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_INT_INTERFACE_IMUX_OUT9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_INT_INTERFACE_IMUX_DELAY9" } }, "sites": [], "tile_type": "PCIE_INT_INTERFACE_R", - "wires": [ - "INT_INTERFACE_BLOCK_OUTS_B0", - "INT_INTERFACE_BLOCK_OUTS_B1", - "INT_INTERFACE_BLOCK_OUTS_B2", - "INT_INTERFACE_BLOCK_OUTS_B3", - "INT_INTERFACE_BYP0", - "INT_INTERFACE_BYP1", - "INT_INTERFACE_BYP2", - "INT_INTERFACE_BYP3", - "INT_INTERFACE_BYP4", - "INT_INTERFACE_BYP5", - "INT_INTERFACE_BYP6", - "INT_INTERFACE_BYP7", - "INT_INTERFACE_CLK0", - "INT_INTERFACE_CLK1", - "INT_INTERFACE_CTRL0", - "INT_INTERFACE_CTRL1", - "INT_INTERFACE_EE2A0", - "INT_INTERFACE_EE2A1", - "INT_INTERFACE_EE2A2", - "INT_INTERFACE_EE2A3", - "INT_INTERFACE_EE2BEG0", - "INT_INTERFACE_EE2BEG1", - "INT_INTERFACE_EE2BEG2", - "INT_INTERFACE_EE2BEG3", - "INT_INTERFACE_EE4A0", - "INT_INTERFACE_EE4A1", - "INT_INTERFACE_EE4A2", - "INT_INTERFACE_EE4A3", - "INT_INTERFACE_EE4B0", - "INT_INTERFACE_EE4B1", - "INT_INTERFACE_EE4B2", - "INT_INTERFACE_EE4B3", - "INT_INTERFACE_EE4BEG0", - "INT_INTERFACE_EE4BEG1", - "INT_INTERFACE_EE4BEG2", - "INT_INTERFACE_EE4BEG3", - "INT_INTERFACE_EE4C0", - "INT_INTERFACE_EE4C1", - "INT_INTERFACE_EE4C2", - "INT_INTERFACE_EE4C3", - "INT_INTERFACE_EL1BEG0", - "INT_INTERFACE_EL1BEG1", - "INT_INTERFACE_EL1BEG2", - "INT_INTERFACE_EL1BEG3", - "INT_INTERFACE_ER1BEG0", - "INT_INTERFACE_ER1BEG1", - "INT_INTERFACE_ER1BEG2", - "INT_INTERFACE_ER1BEG3", - "INT_INTERFACE_FAN0", - "INT_INTERFACE_FAN1", - "INT_INTERFACE_FAN2", - "INT_INTERFACE_FAN3", - "INT_INTERFACE_FAN4", - "INT_INTERFACE_FAN5", - "INT_INTERFACE_FAN6", - "INT_INTERFACE_FAN7", - "INT_INTERFACE_LH1", - "INT_INTERFACE_LH10", - "INT_INTERFACE_LH11", - "INT_INTERFACE_LH12", - "INT_INTERFACE_LH2", - "INT_INTERFACE_LH3", - "INT_INTERFACE_LH4", - "INT_INTERFACE_LH5", - "INT_INTERFACE_LH6", - "INT_INTERFACE_LH7", - "INT_INTERFACE_LH8", - "INT_INTERFACE_LH9", - "INT_INTERFACE_LOGIC_OUTS0", - "INT_INTERFACE_LOGIC_OUTS1", - "INT_INTERFACE_LOGIC_OUTS10", - "INT_INTERFACE_LOGIC_OUTS11", - "INT_INTERFACE_LOGIC_OUTS12", - "INT_INTERFACE_LOGIC_OUTS13", - "INT_INTERFACE_LOGIC_OUTS14", - "INT_INTERFACE_LOGIC_OUTS15", - "INT_INTERFACE_LOGIC_OUTS16", - "INT_INTERFACE_LOGIC_OUTS17", - "INT_INTERFACE_LOGIC_OUTS18", - "INT_INTERFACE_LOGIC_OUTS19", - "INT_INTERFACE_LOGIC_OUTS2", - "INT_INTERFACE_LOGIC_OUTS20", - "INT_INTERFACE_LOGIC_OUTS21", - "INT_INTERFACE_LOGIC_OUTS22", - "INT_INTERFACE_LOGIC_OUTS23", - "INT_INTERFACE_LOGIC_OUTS3", - "INT_INTERFACE_LOGIC_OUTS4", - "INT_INTERFACE_LOGIC_OUTS5", - "INT_INTERFACE_LOGIC_OUTS6", - "INT_INTERFACE_LOGIC_OUTS7", - "INT_INTERFACE_LOGIC_OUTS8", - "INT_INTERFACE_LOGIC_OUTS9", - "INT_INTERFACE_LOGIC_OUTS_B0", - "INT_INTERFACE_LOGIC_OUTS_B1", - "INT_INTERFACE_LOGIC_OUTS_B10", - "INT_INTERFACE_LOGIC_OUTS_B11", - "INT_INTERFACE_LOGIC_OUTS_B12", - "INT_INTERFACE_LOGIC_OUTS_B13", - "INT_INTERFACE_LOGIC_OUTS_B14", - "INT_INTERFACE_LOGIC_OUTS_B15", - "INT_INTERFACE_LOGIC_OUTS_B16", - "INT_INTERFACE_LOGIC_OUTS_B17", - "INT_INTERFACE_LOGIC_OUTS_B18", - "INT_INTERFACE_LOGIC_OUTS_B19", - "INT_INTERFACE_LOGIC_OUTS_B2", - "INT_INTERFACE_LOGIC_OUTS_B20", - "INT_INTERFACE_LOGIC_OUTS_B21", - "INT_INTERFACE_LOGIC_OUTS_B22", - "INT_INTERFACE_LOGIC_OUTS_B23", - "INT_INTERFACE_LOGIC_OUTS_B3", - "INT_INTERFACE_LOGIC_OUTS_B4", - "INT_INTERFACE_LOGIC_OUTS_B5", - "INT_INTERFACE_LOGIC_OUTS_B6", - "INT_INTERFACE_LOGIC_OUTS_B7", - "INT_INTERFACE_LOGIC_OUTS_B8", - "INT_INTERFACE_LOGIC_OUTS_B9", - "INT_INTERFACE_MONITOR_N", - "INT_INTERFACE_MONITOR_P", - "INT_INTERFACE_NE2A0", - "INT_INTERFACE_NE2A1", - "INT_INTERFACE_NE2A2", - "INT_INTERFACE_NE2A3", - "INT_INTERFACE_NE4BEG0", - "INT_INTERFACE_NE4BEG1", - "INT_INTERFACE_NE4BEG2", - "INT_INTERFACE_NE4BEG3", - "INT_INTERFACE_NE4C0", - "INT_INTERFACE_NE4C1", - "INT_INTERFACE_NE4C2", - "INT_INTERFACE_NE4C3", - "INT_INTERFACE_NW2A0", - "INT_INTERFACE_NW2A1", - "INT_INTERFACE_NW2A2", - "INT_INTERFACE_NW2A3", - "INT_INTERFACE_NW4A0", - "INT_INTERFACE_NW4A1", - "INT_INTERFACE_NW4A2", - "INT_INTERFACE_NW4A3", - "INT_INTERFACE_NW4END0", - "INT_INTERFACE_NW4END1", - "INT_INTERFACE_NW4END2", - "INT_INTERFACE_NW4END3", - "INT_INTERFACE_SE2A0", - "INT_INTERFACE_SE2A1", - "INT_INTERFACE_SE2A2", - "INT_INTERFACE_SE2A3", - "INT_INTERFACE_SE4BEG0", - "INT_INTERFACE_SE4BEG1", - "INT_INTERFACE_SE4BEG2", - "INT_INTERFACE_SE4BEG3", - "INT_INTERFACE_SE4C0", - "INT_INTERFACE_SE4C1", - "INT_INTERFACE_SE4C2", - "INT_INTERFACE_SE4C3", - "INT_INTERFACE_SW2A0", - "INT_INTERFACE_SW2A1", - "INT_INTERFACE_SW2A2", - "INT_INTERFACE_SW2A3", - "INT_INTERFACE_SW4A0", - "INT_INTERFACE_SW4A1", - "INT_INTERFACE_SW4A2", - "INT_INTERFACE_SW4A3", - "INT_INTERFACE_SW4END0", - "INT_INTERFACE_SW4END1", - "INT_INTERFACE_SW4END2", - "INT_INTERFACE_SW4END3", - "INT_INTERFACE_WL1END0", - "INT_INTERFACE_WL1END1", - "INT_INTERFACE_WL1END2", - "INT_INTERFACE_WL1END3", - "INT_INTERFACE_WR1END0", - "INT_INTERFACE_WR1END1", - "INT_INTERFACE_WR1END2", - "INT_INTERFACE_WR1END3", - "INT_INTERFACE_WW2A0", - "INT_INTERFACE_WW2A1", - "INT_INTERFACE_WW2A2", - "INT_INTERFACE_WW2A3", - "INT_INTERFACE_WW2END0", - "INT_INTERFACE_WW2END1", - "INT_INTERFACE_WW2END2", - "INT_INTERFACE_WW2END3", - "INT_INTERFACE_WW4A0", - "INT_INTERFACE_WW4A1", - "INT_INTERFACE_WW4A2", - "INT_INTERFACE_WW4A3", - "INT_INTERFACE_WW4B0", - "INT_INTERFACE_WW4B1", - "INT_INTERFACE_WW4B2", - "INT_INTERFACE_WW4B3", - "INT_INTERFACE_WW4C0", - "INT_INTERFACE_WW4C1", - "INT_INTERFACE_WW4C2", - "INT_INTERFACE_WW4C3", - "INT_INTERFACE_WW4END0", - "INT_INTERFACE_WW4END1", - "INT_INTERFACE_WW4END2", - "INT_INTERFACE_WW4END3", - "PCIE_INT_INTERFACE_IMUX0", - "PCIE_INT_INTERFACE_IMUX1", - "PCIE_INT_INTERFACE_IMUX10", - "PCIE_INT_INTERFACE_IMUX11", - "PCIE_INT_INTERFACE_IMUX12", - "PCIE_INT_INTERFACE_IMUX13", - "PCIE_INT_INTERFACE_IMUX14", - "PCIE_INT_INTERFACE_IMUX15", - "PCIE_INT_INTERFACE_IMUX16", - "PCIE_INT_INTERFACE_IMUX17", - "PCIE_INT_INTERFACE_IMUX18", - "PCIE_INT_INTERFACE_IMUX19", - "PCIE_INT_INTERFACE_IMUX2", - "PCIE_INT_INTERFACE_IMUX20", - "PCIE_INT_INTERFACE_IMUX21", - "PCIE_INT_INTERFACE_IMUX22", - "PCIE_INT_INTERFACE_IMUX23", - "PCIE_INT_INTERFACE_IMUX24", - "PCIE_INT_INTERFACE_IMUX25", - "PCIE_INT_INTERFACE_IMUX26", - "PCIE_INT_INTERFACE_IMUX27", - "PCIE_INT_INTERFACE_IMUX28", - "PCIE_INT_INTERFACE_IMUX29", - "PCIE_INT_INTERFACE_IMUX3", - "PCIE_INT_INTERFACE_IMUX30", - "PCIE_INT_INTERFACE_IMUX31", - "PCIE_INT_INTERFACE_IMUX32", - "PCIE_INT_INTERFACE_IMUX33", - "PCIE_INT_INTERFACE_IMUX34", - "PCIE_INT_INTERFACE_IMUX35", - "PCIE_INT_INTERFACE_IMUX36", - "PCIE_INT_INTERFACE_IMUX37", - "PCIE_INT_INTERFACE_IMUX38", - "PCIE_INT_INTERFACE_IMUX39", - "PCIE_INT_INTERFACE_IMUX4", - "PCIE_INT_INTERFACE_IMUX40", - "PCIE_INT_INTERFACE_IMUX41", - "PCIE_INT_INTERFACE_IMUX42", - "PCIE_INT_INTERFACE_IMUX43", - "PCIE_INT_INTERFACE_IMUX44", - "PCIE_INT_INTERFACE_IMUX45", - "PCIE_INT_INTERFACE_IMUX46", - "PCIE_INT_INTERFACE_IMUX47", - "PCIE_INT_INTERFACE_IMUX5", - "PCIE_INT_INTERFACE_IMUX6", - "PCIE_INT_INTERFACE_IMUX7", - "PCIE_INT_INTERFACE_IMUX8", - "PCIE_INT_INTERFACE_IMUX9", - "PCIE_INT_INTERFACE_IMUX_DELAY0", - "PCIE_INT_INTERFACE_IMUX_DELAY1", - "PCIE_INT_INTERFACE_IMUX_DELAY10", - "PCIE_INT_INTERFACE_IMUX_DELAY11", - "PCIE_INT_INTERFACE_IMUX_DELAY12", - "PCIE_INT_INTERFACE_IMUX_DELAY13", - "PCIE_INT_INTERFACE_IMUX_DELAY14", - "PCIE_INT_INTERFACE_IMUX_DELAY15", - "PCIE_INT_INTERFACE_IMUX_DELAY16", - "PCIE_INT_INTERFACE_IMUX_DELAY17", - "PCIE_INT_INTERFACE_IMUX_DELAY18", - "PCIE_INT_INTERFACE_IMUX_DELAY19", - "PCIE_INT_INTERFACE_IMUX_DELAY2", - "PCIE_INT_INTERFACE_IMUX_DELAY20", - "PCIE_INT_INTERFACE_IMUX_DELAY21", - "PCIE_INT_INTERFACE_IMUX_DELAY22", - "PCIE_INT_INTERFACE_IMUX_DELAY23", - "PCIE_INT_INTERFACE_IMUX_DELAY24", - "PCIE_INT_INTERFACE_IMUX_DELAY25", - "PCIE_INT_INTERFACE_IMUX_DELAY26", - "PCIE_INT_INTERFACE_IMUX_DELAY27", - "PCIE_INT_INTERFACE_IMUX_DELAY28", - "PCIE_INT_INTERFACE_IMUX_DELAY29", - "PCIE_INT_INTERFACE_IMUX_DELAY3", - "PCIE_INT_INTERFACE_IMUX_DELAY30", - "PCIE_INT_INTERFACE_IMUX_DELAY31", - "PCIE_INT_INTERFACE_IMUX_DELAY32", - "PCIE_INT_INTERFACE_IMUX_DELAY33", - "PCIE_INT_INTERFACE_IMUX_DELAY34", - "PCIE_INT_INTERFACE_IMUX_DELAY35", - "PCIE_INT_INTERFACE_IMUX_DELAY36", - "PCIE_INT_INTERFACE_IMUX_DELAY37", - "PCIE_INT_INTERFACE_IMUX_DELAY38", - "PCIE_INT_INTERFACE_IMUX_DELAY39", - "PCIE_INT_INTERFACE_IMUX_DELAY4", - "PCIE_INT_INTERFACE_IMUX_DELAY40", - "PCIE_INT_INTERFACE_IMUX_DELAY41", - "PCIE_INT_INTERFACE_IMUX_DELAY42", - "PCIE_INT_INTERFACE_IMUX_DELAY43", - "PCIE_INT_INTERFACE_IMUX_DELAY44", - "PCIE_INT_INTERFACE_IMUX_DELAY45", - "PCIE_INT_INTERFACE_IMUX_DELAY46", - "PCIE_INT_INTERFACE_IMUX_DELAY47", - "PCIE_INT_INTERFACE_IMUX_DELAY5", - "PCIE_INT_INTERFACE_IMUX_DELAY6", - "PCIE_INT_INTERFACE_IMUX_DELAY7", - "PCIE_INT_INTERFACE_IMUX_DELAY8", - "PCIE_INT_INTERFACE_IMUX_DELAY9", - "PCIE_INT_INTERFACE_IMUX_OUT0", - "PCIE_INT_INTERFACE_IMUX_OUT1", - "PCIE_INT_INTERFACE_IMUX_OUT10", - "PCIE_INT_INTERFACE_IMUX_OUT11", - "PCIE_INT_INTERFACE_IMUX_OUT12", - "PCIE_INT_INTERFACE_IMUX_OUT13", - "PCIE_INT_INTERFACE_IMUX_OUT14", - "PCIE_INT_INTERFACE_IMUX_OUT15", - "PCIE_INT_INTERFACE_IMUX_OUT16", - "PCIE_INT_INTERFACE_IMUX_OUT17", - "PCIE_INT_INTERFACE_IMUX_OUT18", - "PCIE_INT_INTERFACE_IMUX_OUT19", - "PCIE_INT_INTERFACE_IMUX_OUT2", - "PCIE_INT_INTERFACE_IMUX_OUT20", - "PCIE_INT_INTERFACE_IMUX_OUT21", - "PCIE_INT_INTERFACE_IMUX_OUT22", - "PCIE_INT_INTERFACE_IMUX_OUT23", - "PCIE_INT_INTERFACE_IMUX_OUT24", - "PCIE_INT_INTERFACE_IMUX_OUT25", - "PCIE_INT_INTERFACE_IMUX_OUT26", - "PCIE_INT_INTERFACE_IMUX_OUT27", - "PCIE_INT_INTERFACE_IMUX_OUT28", - "PCIE_INT_INTERFACE_IMUX_OUT29", - "PCIE_INT_INTERFACE_IMUX_OUT3", - "PCIE_INT_INTERFACE_IMUX_OUT30", - "PCIE_INT_INTERFACE_IMUX_OUT31", - "PCIE_INT_INTERFACE_IMUX_OUT32", - "PCIE_INT_INTERFACE_IMUX_OUT33", - "PCIE_INT_INTERFACE_IMUX_OUT34", - "PCIE_INT_INTERFACE_IMUX_OUT35", - "PCIE_INT_INTERFACE_IMUX_OUT36", - "PCIE_INT_INTERFACE_IMUX_OUT37", - "PCIE_INT_INTERFACE_IMUX_OUT38", - "PCIE_INT_INTERFACE_IMUX_OUT39", - "PCIE_INT_INTERFACE_IMUX_OUT4", - "PCIE_INT_INTERFACE_IMUX_OUT40", - "PCIE_INT_INTERFACE_IMUX_OUT41", - "PCIE_INT_INTERFACE_IMUX_OUT42", - "PCIE_INT_INTERFACE_IMUX_OUT43", - "PCIE_INT_INTERFACE_IMUX_OUT44", - "PCIE_INT_INTERFACE_IMUX_OUT45", - "PCIE_INT_INTERFACE_IMUX_OUT46", - "PCIE_INT_INTERFACE_IMUX_OUT47", - "PCIE_INT_INTERFACE_IMUX_OUT5", - "PCIE_INT_INTERFACE_IMUX_OUT6", - "PCIE_INT_INTERFACE_IMUX_OUT7", - "PCIE_INT_INTERFACE_IMUX_OUT8", - "PCIE_INT_INTERFACE_IMUX_OUT9" - ] + "wires": { + "INT_INTERFACE_BLOCK_OUTS_B0": null, + "INT_INTERFACE_BLOCK_OUTS_B1": null, + "INT_INTERFACE_BLOCK_OUTS_B2": null, + "INT_INTERFACE_BLOCK_OUTS_B3": null, + "INT_INTERFACE_BYP0": null, + "INT_INTERFACE_BYP1": null, + "INT_INTERFACE_BYP2": null, + "INT_INTERFACE_BYP3": null, + "INT_INTERFACE_BYP4": null, + "INT_INTERFACE_BYP5": null, + "INT_INTERFACE_BYP6": null, + "INT_INTERFACE_BYP7": null, + "INT_INTERFACE_CLK0": null, + "INT_INTERFACE_CLK1": null, + "INT_INTERFACE_CTRL0": null, + "INT_INTERFACE_CTRL1": null, + "INT_INTERFACE_EE2A0": null, + "INT_INTERFACE_EE2A1": null, + "INT_INTERFACE_EE2A2": null, + "INT_INTERFACE_EE2A3": null, + "INT_INTERFACE_EE2BEG0": null, + "INT_INTERFACE_EE2BEG1": null, + "INT_INTERFACE_EE2BEG2": null, + "INT_INTERFACE_EE2BEG3": null, + "INT_INTERFACE_EE4A0": null, + "INT_INTERFACE_EE4A1": null, + "INT_INTERFACE_EE4A2": null, + "INT_INTERFACE_EE4A3": null, + "INT_INTERFACE_EE4B0": null, + "INT_INTERFACE_EE4B1": null, + "INT_INTERFACE_EE4B2": null, + "INT_INTERFACE_EE4B3": null, + "INT_INTERFACE_EE4BEG0": null, + "INT_INTERFACE_EE4BEG1": null, + "INT_INTERFACE_EE4BEG2": null, + "INT_INTERFACE_EE4BEG3": null, + "INT_INTERFACE_EE4C0": null, + "INT_INTERFACE_EE4C1": null, + "INT_INTERFACE_EE4C2": null, + "INT_INTERFACE_EE4C3": null, + "INT_INTERFACE_EL1BEG0": null, + "INT_INTERFACE_EL1BEG1": null, + "INT_INTERFACE_EL1BEG2": null, + "INT_INTERFACE_EL1BEG3": null, + "INT_INTERFACE_ER1BEG0": null, + "INT_INTERFACE_ER1BEG1": null, + "INT_INTERFACE_ER1BEG2": null, + "INT_INTERFACE_ER1BEG3": null, + "INT_INTERFACE_FAN0": null, + "INT_INTERFACE_FAN1": null, + "INT_INTERFACE_FAN2": null, + "INT_INTERFACE_FAN3": null, + "INT_INTERFACE_FAN4": null, + "INT_INTERFACE_FAN5": null, + "INT_INTERFACE_FAN6": null, + "INT_INTERFACE_FAN7": null, + "INT_INTERFACE_LH1": null, + "INT_INTERFACE_LH10": null, + "INT_INTERFACE_LH11": null, + "INT_INTERFACE_LH12": null, + "INT_INTERFACE_LH2": null, + "INT_INTERFACE_LH3": null, + "INT_INTERFACE_LH4": null, + "INT_INTERFACE_LH5": null, + "INT_INTERFACE_LH6": null, + "INT_INTERFACE_LH7": null, + "INT_INTERFACE_LH8": null, + "INT_INTERFACE_LH9": null, + "INT_INTERFACE_LOGIC_OUTS0": null, + "INT_INTERFACE_LOGIC_OUTS1": null, + "INT_INTERFACE_LOGIC_OUTS10": null, + "INT_INTERFACE_LOGIC_OUTS11": null, + "INT_INTERFACE_LOGIC_OUTS12": null, + "INT_INTERFACE_LOGIC_OUTS13": null, + "INT_INTERFACE_LOGIC_OUTS14": null, + "INT_INTERFACE_LOGIC_OUTS15": null, + "INT_INTERFACE_LOGIC_OUTS16": null, + "INT_INTERFACE_LOGIC_OUTS17": null, + "INT_INTERFACE_LOGIC_OUTS18": null, + "INT_INTERFACE_LOGIC_OUTS19": null, + "INT_INTERFACE_LOGIC_OUTS2": null, + "INT_INTERFACE_LOGIC_OUTS20": null, + "INT_INTERFACE_LOGIC_OUTS21": null, + "INT_INTERFACE_LOGIC_OUTS22": null, + "INT_INTERFACE_LOGIC_OUTS23": null, + "INT_INTERFACE_LOGIC_OUTS3": null, + "INT_INTERFACE_LOGIC_OUTS4": null, + "INT_INTERFACE_LOGIC_OUTS5": null, + "INT_INTERFACE_LOGIC_OUTS6": null, + "INT_INTERFACE_LOGIC_OUTS7": null, + "INT_INTERFACE_LOGIC_OUTS8": null, + "INT_INTERFACE_LOGIC_OUTS9": null, + "INT_INTERFACE_LOGIC_OUTS_B0": null, + "INT_INTERFACE_LOGIC_OUTS_B1": null, + "INT_INTERFACE_LOGIC_OUTS_B10": null, + "INT_INTERFACE_LOGIC_OUTS_B11": null, + "INT_INTERFACE_LOGIC_OUTS_B12": null, + "INT_INTERFACE_LOGIC_OUTS_B13": null, + "INT_INTERFACE_LOGIC_OUTS_B14": null, + "INT_INTERFACE_LOGIC_OUTS_B15": null, + "INT_INTERFACE_LOGIC_OUTS_B16": null, + "INT_INTERFACE_LOGIC_OUTS_B17": null, + "INT_INTERFACE_LOGIC_OUTS_B18": null, + "INT_INTERFACE_LOGIC_OUTS_B19": null, + "INT_INTERFACE_LOGIC_OUTS_B2": null, + "INT_INTERFACE_LOGIC_OUTS_B20": null, + "INT_INTERFACE_LOGIC_OUTS_B21": null, + "INT_INTERFACE_LOGIC_OUTS_B22": null, + "INT_INTERFACE_LOGIC_OUTS_B23": null, + "INT_INTERFACE_LOGIC_OUTS_B3": null, + "INT_INTERFACE_LOGIC_OUTS_B4": null, + "INT_INTERFACE_LOGIC_OUTS_B5": null, + "INT_INTERFACE_LOGIC_OUTS_B6": null, + "INT_INTERFACE_LOGIC_OUTS_B7": null, + "INT_INTERFACE_LOGIC_OUTS_B8": null, + "INT_INTERFACE_LOGIC_OUTS_B9": null, + "INT_INTERFACE_MONITOR_N": null, + "INT_INTERFACE_MONITOR_P": null, + "INT_INTERFACE_NE2A0": null, + "INT_INTERFACE_NE2A1": null, + "INT_INTERFACE_NE2A2": null, + "INT_INTERFACE_NE2A3": null, + "INT_INTERFACE_NE4BEG0": null, + "INT_INTERFACE_NE4BEG1": null, + "INT_INTERFACE_NE4BEG2": null, + "INT_INTERFACE_NE4BEG3": null, + "INT_INTERFACE_NE4C0": null, + "INT_INTERFACE_NE4C1": null, + "INT_INTERFACE_NE4C2": null, + "INT_INTERFACE_NE4C3": null, + "INT_INTERFACE_NW2A0": null, + "INT_INTERFACE_NW2A1": null, + "INT_INTERFACE_NW2A2": null, + "INT_INTERFACE_NW2A3": null, + "INT_INTERFACE_NW4A0": null, + "INT_INTERFACE_NW4A1": null, + "INT_INTERFACE_NW4A2": null, + "INT_INTERFACE_NW4A3": null, + "INT_INTERFACE_NW4END0": null, + "INT_INTERFACE_NW4END1": null, + "INT_INTERFACE_NW4END2": null, + "INT_INTERFACE_NW4END3": null, + "INT_INTERFACE_SE2A0": null, + "INT_INTERFACE_SE2A1": null, + "INT_INTERFACE_SE2A2": null, + "INT_INTERFACE_SE2A3": null, + "INT_INTERFACE_SE4BEG0": null, + "INT_INTERFACE_SE4BEG1": null, + "INT_INTERFACE_SE4BEG2": null, + "INT_INTERFACE_SE4BEG3": null, + "INT_INTERFACE_SE4C0": null, + "INT_INTERFACE_SE4C1": null, + "INT_INTERFACE_SE4C2": null, + "INT_INTERFACE_SE4C3": null, + "INT_INTERFACE_SW2A0": null, + "INT_INTERFACE_SW2A1": null, + "INT_INTERFACE_SW2A2": null, + "INT_INTERFACE_SW2A3": null, + "INT_INTERFACE_SW4A0": null, + "INT_INTERFACE_SW4A1": null, + "INT_INTERFACE_SW4A2": null, + "INT_INTERFACE_SW4A3": null, + "INT_INTERFACE_SW4END0": null, + "INT_INTERFACE_SW4END1": null, + "INT_INTERFACE_SW4END2": null, + "INT_INTERFACE_SW4END3": null, + "INT_INTERFACE_WL1END0": null, + "INT_INTERFACE_WL1END1": null, + "INT_INTERFACE_WL1END2": null, + "INT_INTERFACE_WL1END3": null, + "INT_INTERFACE_WR1END0": null, + "INT_INTERFACE_WR1END1": null, + "INT_INTERFACE_WR1END2": null, + "INT_INTERFACE_WR1END3": null, + "INT_INTERFACE_WW2A0": null, + "INT_INTERFACE_WW2A1": null, + "INT_INTERFACE_WW2A2": null, + "INT_INTERFACE_WW2A3": null, + "INT_INTERFACE_WW2END0": null, + "INT_INTERFACE_WW2END1": null, + "INT_INTERFACE_WW2END2": null, + "INT_INTERFACE_WW2END3": null, + "INT_INTERFACE_WW4A0": null, + "INT_INTERFACE_WW4A1": null, + "INT_INTERFACE_WW4A2": null, + "INT_INTERFACE_WW4A3": null, + "INT_INTERFACE_WW4B0": null, + "INT_INTERFACE_WW4B1": null, + "INT_INTERFACE_WW4B2": null, + "INT_INTERFACE_WW4B3": null, + "INT_INTERFACE_WW4C0": null, + "INT_INTERFACE_WW4C1": null, + "INT_INTERFACE_WW4C2": null, + "INT_INTERFACE_WW4C3": null, + "INT_INTERFACE_WW4END0": null, + "INT_INTERFACE_WW4END1": null, + "INT_INTERFACE_WW4END2": null, + "INT_INTERFACE_WW4END3": null, + "PCIE_INT_INTERFACE_IMUX0": null, + "PCIE_INT_INTERFACE_IMUX1": null, + "PCIE_INT_INTERFACE_IMUX10": null, + "PCIE_INT_INTERFACE_IMUX11": null, + "PCIE_INT_INTERFACE_IMUX12": null, + "PCIE_INT_INTERFACE_IMUX13": null, + "PCIE_INT_INTERFACE_IMUX14": null, + "PCIE_INT_INTERFACE_IMUX15": null, + "PCIE_INT_INTERFACE_IMUX16": null, + "PCIE_INT_INTERFACE_IMUX17": null, + "PCIE_INT_INTERFACE_IMUX18": null, + "PCIE_INT_INTERFACE_IMUX19": null, + "PCIE_INT_INTERFACE_IMUX2": null, + "PCIE_INT_INTERFACE_IMUX20": null, + "PCIE_INT_INTERFACE_IMUX21": null, + "PCIE_INT_INTERFACE_IMUX22": null, + "PCIE_INT_INTERFACE_IMUX23": null, + "PCIE_INT_INTERFACE_IMUX24": null, + "PCIE_INT_INTERFACE_IMUX25": null, + "PCIE_INT_INTERFACE_IMUX26": null, + "PCIE_INT_INTERFACE_IMUX27": null, + "PCIE_INT_INTERFACE_IMUX28": null, + "PCIE_INT_INTERFACE_IMUX29": null, + "PCIE_INT_INTERFACE_IMUX3": null, + "PCIE_INT_INTERFACE_IMUX30": null, + "PCIE_INT_INTERFACE_IMUX31": null, + "PCIE_INT_INTERFACE_IMUX32": null, + "PCIE_INT_INTERFACE_IMUX33": null, + "PCIE_INT_INTERFACE_IMUX34": null, + "PCIE_INT_INTERFACE_IMUX35": null, + "PCIE_INT_INTERFACE_IMUX36": null, + "PCIE_INT_INTERFACE_IMUX37": null, + "PCIE_INT_INTERFACE_IMUX38": null, + "PCIE_INT_INTERFACE_IMUX39": null, + "PCIE_INT_INTERFACE_IMUX4": null, + "PCIE_INT_INTERFACE_IMUX40": null, + "PCIE_INT_INTERFACE_IMUX41": null, + "PCIE_INT_INTERFACE_IMUX42": null, + "PCIE_INT_INTERFACE_IMUX43": null, + "PCIE_INT_INTERFACE_IMUX44": null, + "PCIE_INT_INTERFACE_IMUX45": null, + "PCIE_INT_INTERFACE_IMUX46": null, + "PCIE_INT_INTERFACE_IMUX47": null, + "PCIE_INT_INTERFACE_IMUX5": null, + "PCIE_INT_INTERFACE_IMUX6": null, + "PCIE_INT_INTERFACE_IMUX7": null, + "PCIE_INT_INTERFACE_IMUX8": null, + "PCIE_INT_INTERFACE_IMUX9": null, + "PCIE_INT_INTERFACE_IMUX_DELAY0": null, + "PCIE_INT_INTERFACE_IMUX_DELAY1": null, + "PCIE_INT_INTERFACE_IMUX_DELAY10": null, + "PCIE_INT_INTERFACE_IMUX_DELAY11": null, + "PCIE_INT_INTERFACE_IMUX_DELAY12": null, + "PCIE_INT_INTERFACE_IMUX_DELAY13": null, + "PCIE_INT_INTERFACE_IMUX_DELAY14": null, + "PCIE_INT_INTERFACE_IMUX_DELAY15": null, + "PCIE_INT_INTERFACE_IMUX_DELAY16": null, + "PCIE_INT_INTERFACE_IMUX_DELAY17": null, + "PCIE_INT_INTERFACE_IMUX_DELAY18": null, + "PCIE_INT_INTERFACE_IMUX_DELAY19": null, + "PCIE_INT_INTERFACE_IMUX_DELAY2": null, + "PCIE_INT_INTERFACE_IMUX_DELAY20": null, + "PCIE_INT_INTERFACE_IMUX_DELAY21": null, + "PCIE_INT_INTERFACE_IMUX_DELAY22": null, + "PCIE_INT_INTERFACE_IMUX_DELAY23": null, + "PCIE_INT_INTERFACE_IMUX_DELAY24": null, + "PCIE_INT_INTERFACE_IMUX_DELAY25": null, + "PCIE_INT_INTERFACE_IMUX_DELAY26": null, + "PCIE_INT_INTERFACE_IMUX_DELAY27": null, + "PCIE_INT_INTERFACE_IMUX_DELAY28": null, + "PCIE_INT_INTERFACE_IMUX_DELAY29": null, + "PCIE_INT_INTERFACE_IMUX_DELAY3": null, + "PCIE_INT_INTERFACE_IMUX_DELAY30": null, + "PCIE_INT_INTERFACE_IMUX_DELAY31": null, + "PCIE_INT_INTERFACE_IMUX_DELAY32": null, + "PCIE_INT_INTERFACE_IMUX_DELAY33": null, + "PCIE_INT_INTERFACE_IMUX_DELAY34": null, + "PCIE_INT_INTERFACE_IMUX_DELAY35": null, + "PCIE_INT_INTERFACE_IMUX_DELAY36": null, + "PCIE_INT_INTERFACE_IMUX_DELAY37": null, + "PCIE_INT_INTERFACE_IMUX_DELAY38": null, + "PCIE_INT_INTERFACE_IMUX_DELAY39": null, + "PCIE_INT_INTERFACE_IMUX_DELAY4": null, + "PCIE_INT_INTERFACE_IMUX_DELAY40": null, + "PCIE_INT_INTERFACE_IMUX_DELAY41": null, + "PCIE_INT_INTERFACE_IMUX_DELAY42": null, + "PCIE_INT_INTERFACE_IMUX_DELAY43": null, + "PCIE_INT_INTERFACE_IMUX_DELAY44": null, + "PCIE_INT_INTERFACE_IMUX_DELAY45": null, + "PCIE_INT_INTERFACE_IMUX_DELAY46": null, + "PCIE_INT_INTERFACE_IMUX_DELAY47": null, + "PCIE_INT_INTERFACE_IMUX_DELAY5": null, + "PCIE_INT_INTERFACE_IMUX_DELAY6": null, + "PCIE_INT_INTERFACE_IMUX_DELAY7": null, + "PCIE_INT_INTERFACE_IMUX_DELAY8": null, + "PCIE_INT_INTERFACE_IMUX_DELAY9": null, + "PCIE_INT_INTERFACE_IMUX_OUT0": null, + "PCIE_INT_INTERFACE_IMUX_OUT1": null, + "PCIE_INT_INTERFACE_IMUX_OUT10": null, + "PCIE_INT_INTERFACE_IMUX_OUT11": null, + "PCIE_INT_INTERFACE_IMUX_OUT12": null, + "PCIE_INT_INTERFACE_IMUX_OUT13": null, + "PCIE_INT_INTERFACE_IMUX_OUT14": null, + "PCIE_INT_INTERFACE_IMUX_OUT15": null, + "PCIE_INT_INTERFACE_IMUX_OUT16": null, + "PCIE_INT_INTERFACE_IMUX_OUT17": null, + "PCIE_INT_INTERFACE_IMUX_OUT18": null, + "PCIE_INT_INTERFACE_IMUX_OUT19": null, + "PCIE_INT_INTERFACE_IMUX_OUT2": null, + "PCIE_INT_INTERFACE_IMUX_OUT20": null, + "PCIE_INT_INTERFACE_IMUX_OUT21": null, + "PCIE_INT_INTERFACE_IMUX_OUT22": null, + "PCIE_INT_INTERFACE_IMUX_OUT23": null, + "PCIE_INT_INTERFACE_IMUX_OUT24": null, + "PCIE_INT_INTERFACE_IMUX_OUT25": null, + "PCIE_INT_INTERFACE_IMUX_OUT26": null, + "PCIE_INT_INTERFACE_IMUX_OUT27": null, + "PCIE_INT_INTERFACE_IMUX_OUT28": null, + "PCIE_INT_INTERFACE_IMUX_OUT29": null, + "PCIE_INT_INTERFACE_IMUX_OUT3": null, + "PCIE_INT_INTERFACE_IMUX_OUT30": null, + "PCIE_INT_INTERFACE_IMUX_OUT31": null, + "PCIE_INT_INTERFACE_IMUX_OUT32": null, + "PCIE_INT_INTERFACE_IMUX_OUT33": null, + "PCIE_INT_INTERFACE_IMUX_OUT34": null, + "PCIE_INT_INTERFACE_IMUX_OUT35": null, + "PCIE_INT_INTERFACE_IMUX_OUT36": null, + "PCIE_INT_INTERFACE_IMUX_OUT37": null, + "PCIE_INT_INTERFACE_IMUX_OUT38": null, + "PCIE_INT_INTERFACE_IMUX_OUT39": null, + "PCIE_INT_INTERFACE_IMUX_OUT4": null, + "PCIE_INT_INTERFACE_IMUX_OUT40": null, + "PCIE_INT_INTERFACE_IMUX_OUT41": null, + "PCIE_INT_INTERFACE_IMUX_OUT42": null, + "PCIE_INT_INTERFACE_IMUX_OUT43": null, + "PCIE_INT_INTERFACE_IMUX_OUT44": null, + "PCIE_INT_INTERFACE_IMUX_OUT45": null, + "PCIE_INT_INTERFACE_IMUX_OUT46": null, + "PCIE_INT_INTERFACE_IMUX_OUT47": null, + "PCIE_INT_INTERFACE_IMUX_OUT5": null, + "PCIE_INT_INTERFACE_IMUX_OUT6": null, + "PCIE_INT_INTERFACE_IMUX_OUT7": null, + "PCIE_INT_INTERFACE_IMUX_OUT8": null, + "PCIE_INT_INTERFACE_IMUX_OUT9": null + } } diff --git a/kintex7/tile_type_PCIE_NULL.json b/kintex7/tile_type_PCIE_NULL.json index 374eb7c..526cbce 100644 --- a/kintex7/tile_type_PCIE_NULL.json +++ b/kintex7/tile_type_PCIE_NULL.json @@ -2,7 +2,7 @@ "pips": {}, "sites": [], "tile_type": "PCIE_NULL", - "wires": [ - "DUMMYFOO" - ] + "wires": { + "DUMMYFOO": null + } } diff --git a/kintex7/tile_type_PCIE_TOP.json b/kintex7/tile_type_PCIE_TOP.json index 89d0d21..4865803 100644 --- a/kintex7/tile_type_PCIE_TOP.json +++ b/kintex7/tile_type_PCIE_TOP.json @@ -2,5131 +2,13402 @@ "pips": { "PCIE_TOP.PCIE_IMUX0_L_0->PCIE_TOP_TRNTDLLPDATA19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_L_0" }, "PCIE_TOP.PCIE_IMUX0_L_1->PCIE_TOP_TRNTDLLPDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_L_1" }, "PCIE_TOP.PCIE_IMUX0_L_2->PCIE_TOP_TRNTDLLPDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_L_2" }, "PCIE_TOP.PCIE_IMUX0_L_3->PCIE_TOP_TRNTDLLPDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_L_3" }, "PCIE_TOP.PCIE_IMUX0_L_4->PCIE_TOP_LL2SENDENTERL23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_LL2SENDENTERL23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_L_4" }, "PCIE_TOP.PCIE_IMUX0_R_0->PCIE_TOP_MIMRXRDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_R_0" }, "PCIE_TOP.PCIE_IMUX0_R_1->PCIE_TOP_MIMRXRDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_R_1" }, "PCIE_TOP.PCIE_IMUX0_R_2->PCIE_TOP_MIMRXRDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_R_2" }, "PCIE_TOP.PCIE_IMUX0_R_3->PCIE_TOP_MIMRXRDATA32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_R_3" }, "PCIE_TOP.PCIE_IMUX0_R_4->PCIE_TOP_MIMRXRDATA36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX0_R_4" }, "PCIE_TOP.PCIE_IMUX10_L_0->PCIE_TOP_CFGDSN59": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDSN59", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_L_0" }, "PCIE_TOP.PCIE_IMUX10_L_1->PCIE_TOP_CFGDSN63": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDSN63", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_L_1" }, "PCIE_TOP.PCIE_IMUX10_L_2->PCIE_TOP_CFGDEVID3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_L_2" }, "PCIE_TOP.PCIE_IMUX10_L_3->PCIE_TOP_CFGDEVID7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_L_3" }, "PCIE_TOP.PCIE_IMUX10_L_4->PCIE_TOP_CFGDEVID11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_L_4" }, "PCIE_TOP.PCIE_IMUX10_R_0->PCIE_TOP_TRNTD10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_R_0" }, "PCIE_TOP.PCIE_IMUX10_R_1->PCIE_TOP_TRNTD14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_R_1" }, "PCIE_TOP.PCIE_IMUX10_R_2->PCIE_TOP_TRNTD18": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD18", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_R_2" }, "PCIE_TOP.PCIE_IMUX10_R_3->PCIE_TOP_TRNTD22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_R_3" }, "PCIE_TOP.PCIE_IMUX10_R_4->PCIE_TOP_PL2DIRECTEDLSTATE3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX10_R_4" }, "PCIE_TOP.PCIE_IMUX11_L_0->PCIE_TOP_CFGDSN60": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDSN60", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_L_0" }, "PCIE_TOP.PCIE_IMUX11_L_1->PCIE_TOP_CFGDEVID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_L_1" }, "PCIE_TOP.PCIE_IMUX11_L_2->PCIE_TOP_CFGDEVID4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_L_2" }, "PCIE_TOP.PCIE_IMUX11_L_3->PCIE_TOP_CFGDEVID8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_L_3" }, "PCIE_TOP.PCIE_IMUX11_L_4->PCIE_TOP_CFGDEVID12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_L_4" }, "PCIE_TOP.PCIE_IMUX11_R_0->PCIE_TOP_TRNTD11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_R_0" }, "PCIE_TOP.PCIE_IMUX11_R_1->PCIE_TOP_TRNTD15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_R_1" }, "PCIE_TOP.PCIE_IMUX11_R_2->PCIE_TOP_TRNTD19": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD19", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_R_2" }, "PCIE_TOP.PCIE_IMUX11_R_3->PCIE_TOP_TRNTD23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_R_3" }, "PCIE_TOP.PCIE_IMUX11_R_4->PCIE_TOP_PL2DIRECTEDLSTATE4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX11_R_4" }, "PCIE_TOP.PCIE_IMUX12_L_0->PCIE_TOP_DRPADDR7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPADDR7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX12_L_0" }, "PCIE_TOP.PCIE_IMUX12_L_1->PCIE_TOP_DRPDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX12_L_1" }, "PCIE_TOP.PCIE_IMUX12_L_2->PCIE_TOP_DRPDI4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX12_L_2" }, "PCIE_TOP.PCIE_IMUX12_L_3->PCIE_TOP_DRPDI8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX12_L_3" }, "PCIE_TOP.PCIE_IMUX12_L_4->PCIE_TOP_DRPDI12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX12_L_4" }, "PCIE_TOP.PCIE_IMUX12_R_0->PCIE_TOP_TRNTD40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX12_R_0" }, "PCIE_TOP.PCIE_IMUX12_R_1->PCIE_TOP_TRNTD36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX12_R_1" }, "PCIE_TOP.PCIE_IMUX12_R_2->PCIE_TOP_TRNTD32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX12_R_2" }, "PCIE_TOP.PCIE_IMUX12_R_3->PCIE_TOP_TRNTD28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX12_R_3" }, "PCIE_TOP.PCIE_IMUX13_L_0->PCIE_TOP_DRPADDR8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPADDR8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_L_0" }, "PCIE_TOP.PCIE_IMUX13_L_1->PCIE_TOP_DRPDI1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_L_1" }, "PCIE_TOP.PCIE_IMUX13_L_2->PCIE_TOP_DRPDI5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_L_2" }, "PCIE_TOP.PCIE_IMUX13_L_3->PCIE_TOP_DRPDI9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_L_3" }, "PCIE_TOP.PCIE_IMUX13_L_4->PCIE_TOP_DRPDI13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_L_4" }, "PCIE_TOP.PCIE_IMUX13_R_0->PCIE_TOP_TRNTD41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_R_0" }, "PCIE_TOP.PCIE_IMUX13_R_1->PCIE_TOP_TRNTD37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_R_1" }, "PCIE_TOP.PCIE_IMUX13_R_2->PCIE_TOP_TRNTD33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_R_2" }, "PCIE_TOP.PCIE_IMUX13_R_3->PCIE_TOP_TRNTD29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_R_3" }, "PCIE_TOP.PCIE_IMUX13_R_4->PCIE_TOP_CFGERRAERHEADERLOG6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX13_R_4" }, "PCIE_TOP.PCIE_IMUX14_L_1->PCIE_TOP_DRPDI2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX14_L_1" }, "PCIE_TOP.PCIE_IMUX14_L_2->PCIE_TOP_DRPDI6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX14_L_2" }, "PCIE_TOP.PCIE_IMUX14_L_3->PCIE_TOP_DRPDI10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX14_L_3" }, "PCIE_TOP.PCIE_IMUX14_L_4->PCIE_TOP_DRPDI14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX14_L_4" }, "PCIE_TOP.PCIE_IMUX14_R_1->PCIE_TOP_TRNTD38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX14_R_1" }, "PCIE_TOP.PCIE_IMUX14_R_2->PCIE_TOP_TRNTD34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX14_R_2" }, "PCIE_TOP.PCIE_IMUX14_R_3->PCIE_TOP_TRNTD30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX14_R_3" }, "PCIE_TOP.PCIE_IMUX14_R_4->PCIE_TOP_CFGERRAERHEADERLOG7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX14_R_4" }, "PCIE_TOP.PCIE_IMUX15_L_1->PCIE_TOP_DRPDI3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX15_L_1" }, "PCIE_TOP.PCIE_IMUX15_L_2->PCIE_TOP_DRPDI7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX15_L_2" }, "PCIE_TOP.PCIE_IMUX15_L_3->PCIE_TOP_DRPDI11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX15_L_3" }, "PCIE_TOP.PCIE_IMUX15_L_4->PCIE_TOP_DRPDI15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DRPDI15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX15_L_4" }, "PCIE_TOP.PCIE_IMUX15_R_1->PCIE_TOP_TRNTD39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX15_R_1" }, "PCIE_TOP.PCIE_IMUX15_R_2->PCIE_TOP_TRNTD35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX15_R_2" }, "PCIE_TOP.PCIE_IMUX15_R_3->PCIE_TOP_TRNTD31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX15_R_3" }, "PCIE_TOP.PCIE_IMUX15_R_4->PCIE_TOP_CFGERRAERHEADERLOG8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX15_R_4" }, "PCIE_TOP.PCIE_IMUX16_L_1->PCIE_TOP_PIPERX0CHARISK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0CHARISK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX16_L_1" }, "PCIE_TOP.PCIE_IMUX16_R_1->PCIE_TOP_PIPERX4CHARISK0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4CHARISK0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX16_R_1" }, "PCIE_TOP.PCIE_IMUX16_R_3->PCIE_TOP_LL2SUSPENDNOW": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_LL2SUSPENDNOW", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX16_R_3" }, "PCIE_TOP.PCIE_IMUX16_R_4->PCIE_TOP_CFGERRAERHEADERLOG9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX16_R_4" }, "PCIE_TOP.PCIE_IMUX17_R_2->PCIE_TOP_CFGERRLOCKEDN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRLOCKEDN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX17_R_2" }, "PCIE_TOP.PCIE_IMUX17_R_3->PCIE_TOP_TL2PPMSUSPENDREQ": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TL2PPMSUSPENDREQ", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX17_R_3" }, "PCIE_TOP.PCIE_IMUX17_R_4->PCIE_TOP_CFGERRTLPCPLHEADER46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX17_R_4" }, "PCIE_TOP.PCIE_IMUX18_R_2->PCIE_TOP_CFGERRNORECOVERYN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRNORECOVERYN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX18_R_2" }, "PCIE_TOP.PCIE_IMUX18_R_3->PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX18_R_3" }, "PCIE_TOP.PCIE_IMUX18_R_4->PCIE_TOP_CFGERRTLPCPLHEADER47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX18_R_4" }, "PCIE_TOP.PCIE_IMUX19_R_2->PCIE_TOP_CFGERRAERHEADERLOG0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX19_R_2" }, "PCIE_TOP.PCIE_IMUX19_R_4->PCIE_TOP_CFGINTERRUPTN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGINTERRUPTN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX19_R_4" }, "PCIE_TOP.PCIE_IMUX1_L_0->PCIE_TOP_TRNTDLLPDATA20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_L_0" }, "PCIE_TOP.PCIE_IMUX1_L_1->PCIE_TOP_TRNTDLLPDATA24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_L_1" }, "PCIE_TOP.PCIE_IMUX1_L_2->PCIE_TOP_TRNTDLLPDATA28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_L_2" }, "PCIE_TOP.PCIE_IMUX1_L_3->PCIE_TOP_TRNTDLLPSRCRDY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPSRCRDY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_L_3" }, "PCIE_TOP.PCIE_IMUX1_L_4->PCIE_TOP_LL2SENDASREQL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_LL2SENDASREQL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_L_4" }, "PCIE_TOP.PCIE_IMUX1_R_0->PCIE_TOP_MIMRXRDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_R_0" }, "PCIE_TOP.PCIE_IMUX1_R_1->PCIE_TOP_MIMRXRDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_R_1" }, "PCIE_TOP.PCIE_IMUX1_R_2->PCIE_TOP_MIMRXRDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_R_2" }, "PCIE_TOP.PCIE_IMUX1_R_3->PCIE_TOP_MIMRXRDATA33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_R_3" }, "PCIE_TOP.PCIE_IMUX1_R_4->PCIE_TOP_MIMRXRDATA37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX1_R_4" }, "PCIE_TOP.PCIE_IMUX20_R_2->PCIE_TOP_CFGERRAERHEADERLOG1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX20_R_2" }, "PCIE_TOP.PCIE_IMUX20_R_3->PCIE_TOP_CFGERRAERHEADERLOG2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX20_R_3" }, "PCIE_TOP.PCIE_IMUX20_R_4->PCIE_TOP_CFGINTERRUPTDI0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGINTERRUPTDI0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX20_R_4" }, "PCIE_TOP.PCIE_IMUX21_R_2->PCIE_TOP_CFGERRAERHEADERLOG11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX21_R_2" }, "PCIE_TOP.PCIE_IMUX21_R_3->PCIE_TOP_CFGERRAERHEADERLOG3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX21_R_3" }, "PCIE_TOP.PCIE_IMUX21_R_4->PCIE_TOP_CFGDEVID13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX21_R_4" }, "PCIE_TOP.PCIE_IMUX22_R_3->PCIE_TOP_CFGERRAERHEADERLOG4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX22_R_3" }, "PCIE_TOP.PCIE_IMUX22_R_4->PCIE_TOP_CFGDEVID14": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID14", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX22_R_4" }, "PCIE_TOP.PCIE_IMUX23_R_3->PCIE_TOP_CFGERRAERHEADERLOG5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX23_R_3" }, "PCIE_TOP.PCIE_IMUX23_R_4->PCIE_TOP_CFGDEVID15": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID15", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX23_R_4" }, "PCIE_TOP.PCIE_IMUX24_R_3->PCIE_TOP_CFGERRAERHEADERLOG10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRAERHEADERLOG10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX24_R_3" }, "PCIE_TOP.PCIE_IMUX24_R_4->PCIE_TOP_CFGVENDID0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGVENDID0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX24_R_4" }, "PCIE_TOP.PCIE_IMUX25_R_4->PCIE_TOP_DBGMODE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_DBGMODE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX25_R_4" }, "PCIE_TOP.PCIE_IMUX2_L_0->PCIE_TOP_TRNTDLLPDATA21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_L_0" }, "PCIE_TOP.PCIE_IMUX2_L_1->PCIE_TOP_TRNTDLLPDATA25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_L_1" }, "PCIE_TOP.PCIE_IMUX2_L_2->PCIE_TOP_TRNTDLLPDATA29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_L_2" }, "PCIE_TOP.PCIE_IMUX2_L_3->PCIE_TOP_LL2TLPRCV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_LL2TLPRCV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_L_3" }, "PCIE_TOP.PCIE_IMUX2_L_4->PCIE_TOP_LL2SENDPMACK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_LL2SENDPMACK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_L_4" }, "PCIE_TOP.PCIE_IMUX2_R_0->PCIE_TOP_MIMRXRDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_R_0" }, "PCIE_TOP.PCIE_IMUX2_R_1->PCIE_TOP_MIMRXRDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_R_1" }, "PCIE_TOP.PCIE_IMUX2_R_2->PCIE_TOP_MIMRXRDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_R_2" }, "PCIE_TOP.PCIE_IMUX2_R_3->PCIE_TOP_MIMRXRDATA34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_R_3" }, "PCIE_TOP.PCIE_IMUX2_R_4->PCIE_TOP_MIMRXRDATA38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX2_R_4" }, "PCIE_TOP.PCIE_IMUX32_L_1->PCIE_TOP_PIPERX0DATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0DATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX32_L_1" }, "PCIE_TOP.PCIE_IMUX32_R_1->PCIE_TOP_PIPERX4DATA3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4DATA3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX32_R_1" }, "PCIE_TOP.PCIE_IMUX33_L_0->PCIE_TOP_PIPERX0CHANISALIGNED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0CHANISALIGNED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX33_L_0" }, "PCIE_TOP.PCIE_IMUX33_L_1->PCIE_TOP_PIPERX0DATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0DATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX33_L_1" }, "PCIE_TOP.PCIE_IMUX33_R_0->PCIE_TOP_PIPERX4CHANISALIGNED": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4CHANISALIGNED", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX33_R_0" }, "PCIE_TOP.PCIE_IMUX33_R_1->PCIE_TOP_PIPERX4DATA2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4DATA2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX33_R_1" }, "PCIE_TOP.PCIE_IMUX34_L_0->PCIE_TOP_PIPERX0DATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0DATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX34_L_0" }, "PCIE_TOP.PCIE_IMUX34_R_0->PCIE_TOP_PIPERX4DATA7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4DATA7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX34_R_0" }, "PCIE_TOP.PCIE_IMUX35_L_0->PCIE_TOP_PIPERX0DATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0DATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX35_L_0" }, "PCIE_TOP.PCIE_IMUX35_R_0->PCIE_TOP_PIPERX4DATA6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4DATA6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX35_R_0" }, "PCIE_TOP.PCIE_IMUX36_L_0->PCIE_TOP_PIPERX0VALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0VALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX36_L_0" }, "PCIE_TOP.PCIE_IMUX36_L_1->PCIE_TOP_PIPERX0DATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0DATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX36_L_1" }, "PCIE_TOP.PCIE_IMUX36_R_0->PCIE_TOP_PIPERX4VALID": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4VALID", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX36_R_0" }, "PCIE_TOP.PCIE_IMUX36_R_1->PCIE_TOP_PIPERX4DATA1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4DATA1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX36_R_1" }, "PCIE_TOP.PCIE_IMUX37_L_0->PCIE_TOP_PIPERX0PHYSTATUS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0PHYSTATUS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX37_L_0" }, "PCIE_TOP.PCIE_IMUX37_L_1->PCIE_TOP_PIPERX0DATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0DATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX37_L_1" }, "PCIE_TOP.PCIE_IMUX37_R_0->PCIE_TOP_PIPERX4PHYSTATUS": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4PHYSTATUS", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX37_R_0" }, "PCIE_TOP.PCIE_IMUX37_R_1->PCIE_TOP_PIPERX4DATA0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4DATA0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX37_R_1" }, "PCIE_TOP.PCIE_IMUX38_L_0->PCIE_TOP_PIPERX0DATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0DATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX38_L_0" }, "PCIE_TOP.PCIE_IMUX38_R_0->PCIE_TOP_PIPERX4DATA5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4DATA5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX38_R_0" }, "PCIE_TOP.PCIE_IMUX39_L_0->PCIE_TOP_PIPERX0DATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX0DATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX39_L_0" }, "PCIE_TOP.PCIE_IMUX39_R_0->PCIE_TOP_PIPERX4DATA4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PIPERX4DATA4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX39_R_0" }, "PCIE_TOP.PCIE_IMUX3_L_0->PCIE_TOP_TRNTDLLPDATA22": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA22", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_L_0" }, "PCIE_TOP.PCIE_IMUX3_L_1->PCIE_TOP_TRNTDLLPDATA26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_L_1" }, "PCIE_TOP.PCIE_IMUX3_L_2->PCIE_TOP_TRNTDLLPDATA30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTDLLPDATA30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_L_2" }, "PCIE_TOP.PCIE_IMUX3_L_3->PCIE_TOP_LL2SENDENTERL1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_LL2SENDENTERL1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_L_3" }, "PCIE_TOP.PCIE_IMUX3_L_4->PCIE_TOP_PL2DIRECTEDLSTATE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_L_4" }, "PCIE_TOP.PCIE_IMUX3_R_0->PCIE_TOP_MIMRXRDATA23": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA23", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_R_0" }, "PCIE_TOP.PCIE_IMUX3_R_1->PCIE_TOP_MIMRXRDATA27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_R_1" }, "PCIE_TOP.PCIE_IMUX3_R_2->PCIE_TOP_MIMRXRDATA31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_R_2" }, "PCIE_TOP.PCIE_IMUX3_R_3->PCIE_TOP_MIMRXRDATA35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_R_3" }, "PCIE_TOP.PCIE_IMUX3_R_4->PCIE_TOP_MIMRXRDATA39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX3_R_4" }, "PCIE_TOP.PCIE_IMUX4_L_0->PCIE_TOP_CFGERRTLPCPLHEADER26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_L_0" }, "PCIE_TOP.PCIE_IMUX4_L_1->PCIE_TOP_CFGERRTLPCPLHEADER30": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER30", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_L_1" }, "PCIE_TOP.PCIE_IMUX4_L_2->PCIE_TOP_CFGERRTLPCPLHEADER34": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER34", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_L_2" }, "PCIE_TOP.PCIE_IMUX4_L_3->PCIE_TOP_CFGERRTLPCPLHEADER38": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER38", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_L_3" }, "PCIE_TOP.PCIE_IMUX4_L_4->PCIE_TOP_CFGERRTLPCPLHEADER42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_L_4" }, "PCIE_TOP.PCIE_IMUX4_R_0->PCIE_TOP_MIMRXRDATA52": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA52", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_R_0" }, "PCIE_TOP.PCIE_IMUX4_R_1->PCIE_TOP_MIMRXRDATA48": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA48", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_R_1" }, "PCIE_TOP.PCIE_IMUX4_R_2->PCIE_TOP_MIMRXRDATA44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_R_2" }, "PCIE_TOP.PCIE_IMUX4_R_3->PCIE_TOP_MIMRXRDATA40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_R_3" }, "PCIE_TOP.PCIE_IMUX4_R_4->PCIE_TOP_TRNTD24": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD24", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX4_R_4" }, "PCIE_TOP.PCIE_IMUX5_L_0->PCIE_TOP_CFGERRTLPCPLHEADER27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_L_0" }, "PCIE_TOP.PCIE_IMUX5_L_1->PCIE_TOP_CFGERRTLPCPLHEADER31": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER31", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_L_1" }, "PCIE_TOP.PCIE_IMUX5_L_2->PCIE_TOP_CFGERRTLPCPLHEADER35": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER35", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_L_2" }, "PCIE_TOP.PCIE_IMUX5_L_3->PCIE_TOP_CFGERRTLPCPLHEADER39": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER39", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_L_3" }, "PCIE_TOP.PCIE_IMUX5_L_4->PCIE_TOP_CFGERRTLPCPLHEADER43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_L_4" }, "PCIE_TOP.PCIE_IMUX5_R_0->PCIE_TOP_MIMRXRDATA53": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA53", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_R_0" }, "PCIE_TOP.PCIE_IMUX5_R_1->PCIE_TOP_MIMRXRDATA49": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA49", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_R_1" }, "PCIE_TOP.PCIE_IMUX5_R_2->PCIE_TOP_MIMRXRDATA45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_R_2" }, "PCIE_TOP.PCIE_IMUX5_R_3->PCIE_TOP_MIMRXRDATA41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_R_3" }, "PCIE_TOP.PCIE_IMUX5_R_4->PCIE_TOP_TRNTD25": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD25", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX5_R_4" }, "PCIE_TOP.PCIE_IMUX6_L_0->PCIE_TOP_CFGERRTLPCPLHEADER28": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER28", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_L_0" }, "PCIE_TOP.PCIE_IMUX6_L_1->PCIE_TOP_CFGERRTLPCPLHEADER32": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER32", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_L_1" }, "PCIE_TOP.PCIE_IMUX6_L_2->PCIE_TOP_CFGERRTLPCPLHEADER36": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER36", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_L_2" }, "PCIE_TOP.PCIE_IMUX6_L_3->PCIE_TOP_CFGERRTLPCPLHEADER40": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER40", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_L_3" }, "PCIE_TOP.PCIE_IMUX6_L_4->PCIE_TOP_CFGERRTLPCPLHEADER44": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER44", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_L_4" }, "PCIE_TOP.PCIE_IMUX6_R_0->PCIE_TOP_MIMRXRDATA54": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA54", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_R_0" }, "PCIE_TOP.PCIE_IMUX6_R_1->PCIE_TOP_MIMRXRDATA50": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA50", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_R_1" }, "PCIE_TOP.PCIE_IMUX6_R_2->PCIE_TOP_MIMRXRDATA46": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA46", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_R_2" }, "PCIE_TOP.PCIE_IMUX6_R_3->PCIE_TOP_MIMRXRDATA42": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA42", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_R_3" }, "PCIE_TOP.PCIE_IMUX6_R_4->PCIE_TOP_TRNTD26": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD26", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX6_R_4" }, "PCIE_TOP.PCIE_IMUX7_L_0->PCIE_TOP_CFGERRTLPCPLHEADER29": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER29", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_L_0" }, "PCIE_TOP.PCIE_IMUX7_L_1->PCIE_TOP_CFGERRTLPCPLHEADER33": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER33", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_L_1" }, "PCIE_TOP.PCIE_IMUX7_L_2->PCIE_TOP_CFGERRTLPCPLHEADER37": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER37", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_L_2" }, "PCIE_TOP.PCIE_IMUX7_L_3->PCIE_TOP_CFGERRTLPCPLHEADER41": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER41", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_L_3" }, "PCIE_TOP.PCIE_IMUX7_L_4->PCIE_TOP_CFGERRTLPCPLHEADER45": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGERRTLPCPLHEADER45", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_L_4" }, "PCIE_TOP.PCIE_IMUX7_R_0->PCIE_TOP_MIMRXRDATA55": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA55", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_R_0" }, "PCIE_TOP.PCIE_IMUX7_R_1->PCIE_TOP_MIMRXRDATA51": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA51", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_R_1" }, "PCIE_TOP.PCIE_IMUX7_R_2->PCIE_TOP_MIMRXRDATA47": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA47", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_R_2" }, "PCIE_TOP.PCIE_IMUX7_R_3->PCIE_TOP_MIMRXRDATA43": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_MIMRXRDATA43", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_R_3" }, "PCIE_TOP.PCIE_IMUX7_R_4->PCIE_TOP_TRNTD27": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD27", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX7_R_4" }, "PCIE_TOP.PCIE_IMUX8_L_0->PCIE_TOP_CFGDSN57": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDSN57", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_L_0" }, "PCIE_TOP.PCIE_IMUX8_L_1->PCIE_TOP_CFGDSN61": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDSN61", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_L_1" }, "PCIE_TOP.PCIE_IMUX8_L_2->PCIE_TOP_CFGDEVID1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_L_2" }, "PCIE_TOP.PCIE_IMUX8_L_3->PCIE_TOP_CFGDEVID5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_L_3" }, "PCIE_TOP.PCIE_IMUX8_L_4->PCIE_TOP_CFGDEVID9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_L_4" }, "PCIE_TOP.PCIE_IMUX8_R_0->PCIE_TOP_TRNTD8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_R_0" }, "PCIE_TOP.PCIE_IMUX8_R_1->PCIE_TOP_TRNTD12": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD12", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_R_1" }, "PCIE_TOP.PCIE_IMUX8_R_2->PCIE_TOP_TRNTD16": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD16", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_R_2" }, "PCIE_TOP.PCIE_IMUX8_R_3->PCIE_TOP_TRNTD20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_R_3" }, "PCIE_TOP.PCIE_IMUX8_R_4->PCIE_TOP_PL2DIRECTEDLSTATE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX8_R_4" }, "PCIE_TOP.PCIE_IMUX9_L_0->PCIE_TOP_CFGDSN58": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDSN58", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_L_0" }, "PCIE_TOP.PCIE_IMUX9_L_1->PCIE_TOP_CFGDSN62": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDSN62", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_L_1" }, "PCIE_TOP.PCIE_IMUX9_L_2->PCIE_TOP_CFGDEVID2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_L_2" }, "PCIE_TOP.PCIE_IMUX9_L_3->PCIE_TOP_CFGDEVID6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_L_3" }, "PCIE_TOP.PCIE_IMUX9_L_4->PCIE_TOP_CFGDEVID10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_CFGDEVID10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_L_4" }, "PCIE_TOP.PCIE_IMUX9_R_0->PCIE_TOP_TRNTD9": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD9", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_R_0" }, "PCIE_TOP.PCIE_IMUX9_R_1->PCIE_TOP_TRNTD13": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD13", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_R_1" }, "PCIE_TOP.PCIE_IMUX9_R_2->PCIE_TOP_TRNTD17": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD17", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_R_2" }, "PCIE_TOP.PCIE_IMUX9_R_3->PCIE_TOP_TRNTD21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_TRNTD21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_R_3" }, "PCIE_TOP.PCIE_IMUX9_R_4->PCIE_TOP_PL2DIRECTEDLSTATE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_TOP_PL2DIRECTEDLSTATE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_IMUX9_R_4" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED->PCIE_LOGIC_OUTS_B21_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED->PCIE_LOGIC_OUTS_B16_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B20_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED->PCIE_LOGIC_OUTS_B22_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED" }, "PCIE_TOP.PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN->PCIE_LOGIC_OUTS_B19_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN" }, "PCIE_TOP.PCIE_TOP_CFGCOMMANDBUSMASTERENABLE->PCIE_LOGIC_OUTS_B20_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE" }, "PCIE_TOP.PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE->PCIE_LOGIC_OUTS_B21_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE" }, "PCIE_TOP.PCIE_TOP_CFGCOMMANDIOENABLE->PCIE_LOGIC_OUTS_B11_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGCOMMANDIOENABLE" }, "PCIE_TOP.PCIE_TOP_CFGCOMMANDMEMENABLE->PCIE_LOGIC_OUTS_B17_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGCOMMANDMEMENABLE" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN->PCIE_LOGIC_OUTS_B15_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK->PCIE_LOGIC_OUTS_B13_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN->PCIE_LOGIC_OUTS_B12_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS->PCIE_LOGIC_OUTS_B14_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0->PCIE_LOGIC_OUTS_B14_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1->PCIE_LOGIC_OUTS_B15_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2->PCIE_LOGIC_OUTS_B12_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3->PCIE_LOGIC_OUTS_B13_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOCPLEN->PCIE_LOGIC_OUTS_B15_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2IDOREQEN->PCIE_LOGIC_OUTS_B14_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2IDOREQEN" }, "PCIE_TOP.PCIE_TOP_CFGDEVCONTROL2LTREN->PCIE_LOGIC_OUTS_B23_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B23_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGDEVCONTROL2LTREN" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLASPMCONTROL1->PCIE_LOGIC_OUTS_B13_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B13_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN->PCIE_LOGIC_OUTS_B12_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCLOCKPMEN->PCIE_LOGIC_OUTS_B14_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK->PCIE_LOGIC_OUTS_B12_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC->PCIE_LOGIC_OUTS_B13_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS->PCIE_LOGIC_OUTS_B15_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLLINKDISABLE->PCIE_LOGIC_OUTS_B15_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLLINKDISABLE" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLRCB->PCIE_LOGIC_OUTS_B14_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLRCB" }, "PCIE_TOP.PCIE_TOP_CFGLINKCONTROLRETRAINLINK->PCIE_LOGIC_OUTS_B17_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGLINKCONTROLRETRAINLINK" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO16->PCIE_LOGIC_OUTS_B21_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO16" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO17->PCIE_LOGIC_OUTS_B16_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO17" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO18->PCIE_LOGIC_OUTS_B17_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO18" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO19->PCIE_LOGIC_OUTS_B19_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO19" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO20->PCIE_LOGIC_OUTS_B11_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO20" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO21->PCIE_LOGIC_OUTS_B12_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO21" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO22->PCIE_LOGIC_OUTS_B13_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO22" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO23->PCIE_LOGIC_OUTS_B15_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO23" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO24->PCIE_LOGIC_OUTS_B13_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO24" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO25->PCIE_LOGIC_OUTS_B14_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO25" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO26->PCIE_LOGIC_OUTS_B15_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO26" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO27->PCIE_LOGIC_OUTS_B16_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO27" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO28->PCIE_LOGIC_OUTS_B16_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO28" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO29->PCIE_LOGIC_OUTS_B17_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO29" }, "PCIE_TOP.PCIE_TOP_CFGMGMTDO30->PCIE_LOGIC_OUTS_B18_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGMGMTDO30" }, "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE1->PCIE_LOGIC_OUTS_B9_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPCIELINKSTATE1" }, "PCIE_TOP.PCIE_TOP_CFGPCIELINKSTATE2->PCIE_LOGIC_OUTS_B10_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPCIELINKSTATE2" }, "PCIE_TOP.PCIE_TOP_CFGPMCSRPMEEN->PCIE_LOGIC_OUTS_B8_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPMCSRPMEEN" }, "PCIE_TOP.PCIE_TOP_CFGPMCSRPMESTATUS->PCIE_LOGIC_OUTS_B9_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPMCSRPMESTATUS" }, "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE0->PCIE_LOGIC_OUTS_B10_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE0" }, "PCIE_TOP.PCIE_TOP_CFGPMCSRPOWERSTATE1->PCIE_LOGIC_OUTS_B11_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPMCSRPOWERSTATE1" }, "PCIE_TOP.PCIE_TOP_CFGPMRCVASREQL1N->PCIE_LOGIC_OUTS_B11_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPMRCVASREQL1N" }, "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL1N->PCIE_LOGIC_OUTS_B12_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPMRCVENTERL1N" }, "PCIE_TOP.PCIE_TOP_CFGPMRCVENTERL23N->PCIE_LOGIC_OUTS_B8_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPMRCVENTERL23N" }, "PCIE_TOP.PCIE_TOP_CFGPMRCVREQACKN->PCIE_LOGIC_OUTS_B9_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGPMRCVREQACKN" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTION->PCIE_LOGIC_OUTS_B10_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGTRANSACTION" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR0->PCIE_LOGIC_OUTS_B8_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR0" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR1->PCIE_LOGIC_OUTS_B9_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR1" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR2->PCIE_LOGIC_OUTS_B10_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR2" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR3->PCIE_LOGIC_OUTS_B11_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR3" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR4->PCIE_LOGIC_OUTS_B8_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR4" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR5->PCIE_LOGIC_OUTS_B9_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR5" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONADDR6->PCIE_LOGIC_OUTS_B10_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGTRANSACTIONADDR6" }, "PCIE_TOP.PCIE_TOP_CFGTRANSACTIONTYPE->PCIE_LOGIC_OUTS_B11_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGTRANSACTIONTYPE" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP0->PCIE_LOGIC_OUTS_B17_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP0" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP1->PCIE_LOGIC_OUTS_B18_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP1" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP2->PCIE_LOGIC_OUTS_B19_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP2" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP3->PCIE_LOGIC_OUTS_B16_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP3" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP4->PCIE_LOGIC_OUTS_B17_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP4" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP5->PCIE_LOGIC_OUTS_B18_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP5" }, "PCIE_TOP.PCIE_TOP_CFGVCTCVCMAP6->PCIE_LOGIC_OUTS_B19_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_CFGVCTCVCMAP6" }, "PCIE_TOP.PCIE_TOP_DBGVECA0->PCIE_LOGIC_OUTS_B21_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA0" }, "PCIE_TOP.PCIE_TOP_DBGVECA1->PCIE_LOGIC_OUTS_B22_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA1" }, "PCIE_TOP.PCIE_TOP_DBGVECA10->PCIE_LOGIC_OUTS_B23_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA10" }, "PCIE_TOP.PCIE_TOP_DBGVECA11->PCIE_LOGIC_OUTS_B22_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA11" }, "PCIE_TOP.PCIE_TOP_DBGVECA12->PCIE_LOGIC_OUTS_B20_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA12" }, "PCIE_TOP.PCIE_TOP_DBGVECA13->PCIE_LOGIC_OUTS_B21_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA13" }, "PCIE_TOP.PCIE_TOP_DBGVECA14->PCIE_LOGIC_OUTS_B20_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA14" }, "PCIE_TOP.PCIE_TOP_DBGVECA15->PCIE_LOGIC_OUTS_B23_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B23_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA15" }, "PCIE_TOP.PCIE_TOP_DBGVECA16->PCIE_LOGIC_OUTS_B22_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA16" }, "PCIE_TOP.PCIE_TOP_DBGVECA17->PCIE_LOGIC_OUTS_B23_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B23_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA17" }, "PCIE_TOP.PCIE_TOP_DBGVECA18->PCIE_LOGIC_OUTS_B14_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA18" }, "PCIE_TOP.PCIE_TOP_DBGVECA19->PCIE_LOGIC_OUTS_B19_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA19" }, "PCIE_TOP.PCIE_TOP_DBGVECA2->PCIE_LOGIC_OUTS_B23_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA2" }, "PCIE_TOP.PCIE_TOP_DBGVECA20->PCIE_LOGIC_OUTS_B20_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA20" }, "PCIE_TOP.PCIE_TOP_DBGVECA21->PCIE_LOGIC_OUTS_B21_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA21" }, "PCIE_TOP.PCIE_TOP_DBGVECA3->PCIE_LOGIC_OUTS_B20_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA3" }, "PCIE_TOP.PCIE_TOP_DBGVECA4->PCIE_LOGIC_OUTS_B21_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA4" }, "PCIE_TOP.PCIE_TOP_DBGVECA5->PCIE_LOGIC_OUTS_B22_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA5" }, "PCIE_TOP.PCIE_TOP_DBGVECA6->PCIE_LOGIC_OUTS_B23_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA6" }, "PCIE_TOP.PCIE_TOP_DBGVECA7->PCIE_LOGIC_OUTS_B20_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA7" }, "PCIE_TOP.PCIE_TOP_DBGVECA8->PCIE_LOGIC_OUTS_B21_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA8" }, "PCIE_TOP.PCIE_TOP_DBGVECA9->PCIE_LOGIC_OUTS_B22_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECA9" }, "PCIE_TOP.PCIE_TOP_DBGVECB10->PCIE_LOGIC_OUTS_B22_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DBGVECB10" }, "PCIE_TOP.PCIE_TOP_DRPDO0->PCIE_LOGIC_OUTS_B17_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO0" }, "PCIE_TOP.PCIE_TOP_DRPDO1->PCIE_LOGIC_OUTS_B18_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO1" }, "PCIE_TOP.PCIE_TOP_DRPDO11->PCIE_LOGIC_OUTS_B20_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO11" }, "PCIE_TOP.PCIE_TOP_DRPDO12->PCIE_LOGIC_OUTS_B21_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO12" }, "PCIE_TOP.PCIE_TOP_DRPDO13->PCIE_LOGIC_OUTS_B22_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO13" }, "PCIE_TOP.PCIE_TOP_DRPDO14->PCIE_LOGIC_OUTS_B23_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO14" }, "PCIE_TOP.PCIE_TOP_DRPDO15->PCIE_LOGIC_OUTS_B20_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO15" }, "PCIE_TOP.PCIE_TOP_DRPDO2->PCIE_LOGIC_OUTS_B19_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO2" }, "PCIE_TOP.PCIE_TOP_DRPDO3->PCIE_LOGIC_OUTS_B16_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO3" }, "PCIE_TOP.PCIE_TOP_DRPDO4->PCIE_LOGIC_OUTS_B17_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO4" }, "PCIE_TOP.PCIE_TOP_DRPDO5->PCIE_LOGIC_OUTS_B18_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO5" }, "PCIE_TOP.PCIE_TOP_DRPDO6->PCIE_LOGIC_OUTS_B19_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPDO6" }, "PCIE_TOP.PCIE_TOP_DRPRDY->PCIE_LOGIC_OUTS_B16_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_DRPRDY" }, "PCIE_TOP.PCIE_TOP_LL2TFCINIT1SEQ->PCIE_LOGIC_OUTS_B16_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_LL2TFCINIT1SEQ" }, "PCIE_TOP.PCIE_TOP_LL2TFCINIT2SEQ->PCIE_LOGIC_OUTS_B20_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B20_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_LL2TFCINIT2SEQ" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR0->PCIE_LOGIC_OUTS_B13_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXRADDR0" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR1->PCIE_LOGIC_OUTS_B11_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXRADDR1" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR10->PCIE_LOGIC_OUTS_B3_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXRADDR10" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR11->PCIE_LOGIC_OUTS_B10_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXRADDR11" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR2->PCIE_LOGIC_OUTS_B12_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXRADDR2" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR4->PCIE_LOGIC_OUTS_B5_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXRADDR4" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR8->PCIE_LOGIC_OUTS_B17_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXRADDR8" }, "PCIE_TOP.PCIE_TOP_MIMRXRADDR9->PCIE_LOGIC_OUTS_B8_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXRADDR9" }, "PCIE_TOP.PCIE_TOP_MIMRXREN->PCIE_LOGIC_OUTS_B12_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXREN" }, "PCIE_TOP.PCIE_TOP_MIMRXWADDR1->PCIE_LOGIC_OUTS_B15_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWADDR1" }, "PCIE_TOP.PCIE_TOP_MIMRXWADDR12->PCIE_LOGIC_OUTS_B1_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWADDR12" }, "PCIE_TOP.PCIE_TOP_MIMRXWADDR2->PCIE_LOGIC_OUTS_B0_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWADDR2" }, "PCIE_TOP.PCIE_TOP_MIMRXWADDR5->PCIE_LOGIC_OUTS_B9_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWADDR5" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA0->PCIE_LOGIC_OUTS_B11_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA0" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA1->PCIE_LOGIC_OUTS_B13_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA1" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA10->PCIE_LOGIC_OUTS_B19_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA10" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA11->PCIE_LOGIC_OUTS_B18_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA11" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA12->PCIE_LOGIC_OUTS_B2_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA12" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA13->PCIE_LOGIC_OUTS_B9_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA13" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA15->PCIE_LOGIC_OUTS_B10_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA15" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA17->PCIE_LOGIC_OUTS_B9_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA17" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA19->PCIE_LOGIC_OUTS_B8_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA19" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA2->PCIE_LOGIC_OUTS_B18_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA2" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA20->PCIE_LOGIC_OUTS_B0_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA20" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA21->PCIE_LOGIC_OUTS_B19_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA21" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA22->PCIE_LOGIC_OUTS_B15_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA22" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA23->PCIE_LOGIC_OUTS_B14_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA23" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA24->PCIE_LOGIC_OUTS_B0_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA24" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA25->PCIE_LOGIC_OUTS_B10_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA25" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA26->PCIE_LOGIC_OUTS_B13_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B13_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA26" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA27->PCIE_LOGIC_OUTS_B19_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B19_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA27" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA28->PCIE_LOGIC_OUTS_B14_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA28" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA29->PCIE_LOGIC_OUTS_B8_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA29" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA3->PCIE_LOGIC_OUTS_B15_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B15_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA3" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA30->PCIE_LOGIC_OUTS_B18_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA30" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA31->PCIE_LOGIC_OUTS_B21_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B21_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA31" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA32->PCIE_LOGIC_OUTS_B1_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA32" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA33->PCIE_LOGIC_OUTS_B22_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA33" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA34->PCIE_LOGIC_OUTS_B17_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B17_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA34" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA35->PCIE_LOGIC_OUTS_B11_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA35" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA4->PCIE_LOGIC_OUTS_B9_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA4" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA49->PCIE_LOGIC_OUTS_B5_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA49" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA5->PCIE_LOGIC_OUTS_B22_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B22_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA5" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA51->PCIE_LOGIC_OUTS_B7_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA51" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA6->PCIE_LOGIC_OUTS_B16_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA6" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA7->PCIE_LOGIC_OUTS_B23_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B23_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA7" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA8->PCIE_LOGIC_OUTS_B8_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA8" }, "PCIE_TOP.PCIE_TOP_MIMRXWDATA9->PCIE_LOGIC_OUTS_B3_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWDATA9" }, "PCIE_TOP.PCIE_TOP_MIMRXWEN->PCIE_LOGIC_OUTS_B18_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_MIMRXWEN" }, "PCIE_TOP.PCIE_TOP_PIPETXMARGIN0->PCIE_LOGIC_OUTS_B18_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B18_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_PIPETXMARGIN0" }, "PCIE_TOP.PCIE_TOP_PIPETXMARGIN1->PCIE_LOGIC_OUTS_B16_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B16_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_PIPETXMARGIN1" }, "PCIE_TOP.PCIE_TOP_PIPETXMARGIN2->PCIE_LOGIC_OUTS_B6_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_PIPETXMARGIN2" }, "PCIE_TOP.PCIE_TOP_PL2RECOVERY->PCIE_LOGIC_OUTS_B12_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_PL2RECOVERY" }, "PCIE_TOP.PCIE_TOP_PL2SUSPENDOK->PCIE_LOGIC_OUTS_B7_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_PL2SUSPENDOK" }, "PCIE_TOP.PCIE_TOP_PLDBGVEC8->PCIE_LOGIC_OUTS_B23_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B23_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_PLDBGVEC8" }, "PCIE_TOP.PCIE_TOP_TRNRD59->PCIE_LOGIC_OUTS_B0_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD59" }, "PCIE_TOP.PCIE_TOP_TRNRD60->PCIE_LOGIC_OUTS_B1_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD60" }, "PCIE_TOP.PCIE_TOP_TRNRD61->PCIE_LOGIC_OUTS_B2_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD61" }, "PCIE_TOP.PCIE_TOP_TRNRD62->PCIE_LOGIC_OUTS_B3_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD62" }, "PCIE_TOP.PCIE_TOP_TRNRD63->PCIE_LOGIC_OUTS_B0_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD63" }, "PCIE_TOP.PCIE_TOP_TRNRD64->PCIE_LOGIC_OUTS_B1_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD64" }, "PCIE_TOP.PCIE_TOP_TRNRD65->PCIE_LOGIC_OUTS_B2_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD65" }, "PCIE_TOP.PCIE_TOP_TRNRD66->PCIE_LOGIC_OUTS_B3_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD66" }, "PCIE_TOP.PCIE_TOP_TRNRD67->PCIE_LOGIC_OUTS_B0_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD67" }, "PCIE_TOP.PCIE_TOP_TRNRD68->PCIE_LOGIC_OUTS_B1_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD68" }, "PCIE_TOP.PCIE_TOP_TRNRD69->PCIE_LOGIC_OUTS_B2_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD69" }, "PCIE_TOP.PCIE_TOP_TRNRD70->PCIE_LOGIC_OUTS_B3_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD70" }, "PCIE_TOP.PCIE_TOP_TRNRD71->PCIE_LOGIC_OUTS_B0_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD71" }, "PCIE_TOP.PCIE_TOP_TRNRD72->PCIE_LOGIC_OUTS_B1_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD72" }, "PCIE_TOP.PCIE_TOP_TRNRD73->PCIE_LOGIC_OUTS_B2_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD73" }, "PCIE_TOP.PCIE_TOP_TRNRD74->PCIE_LOGIC_OUTS_B3_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD74" }, "PCIE_TOP.PCIE_TOP_TRNRD75->PCIE_LOGIC_OUTS_B0_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD75" }, "PCIE_TOP.PCIE_TOP_TRNRD76->PCIE_LOGIC_OUTS_B1_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD76" }, "PCIE_TOP.PCIE_TOP_TRNRD77->PCIE_LOGIC_OUTS_B2_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD77" }, "PCIE_TOP.PCIE_TOP_TRNRD78->PCIE_LOGIC_OUTS_B3_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD78" }, "PCIE_TOP.PCIE_TOP_TRNRD79->PCIE_LOGIC_OUTS_B0_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD79" }, "PCIE_TOP.PCIE_TOP_TRNRD80->PCIE_LOGIC_OUTS_B2_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD80" }, "PCIE_TOP.PCIE_TOP_TRNRD81->PCIE_LOGIC_OUTS_B3_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD81" }, "PCIE_TOP.PCIE_TOP_TRNRD82->PCIE_LOGIC_OUTS_B4_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD82" }, "PCIE_TOP.PCIE_TOP_TRNRD83->PCIE_LOGIC_OUTS_B0_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B0_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD83" }, "PCIE_TOP.PCIE_TOP_TRNRD84->PCIE_LOGIC_OUTS_B1_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD84" }, "PCIE_TOP.PCIE_TOP_TRNRD85->PCIE_LOGIC_OUTS_B2_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD85" }, "PCIE_TOP.PCIE_TOP_TRNRD86->PCIE_LOGIC_OUTS_B4_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD86" }, "PCIE_TOP.PCIE_TOP_TRNRD87->PCIE_LOGIC_OUTS_B2_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD87" }, "PCIE_TOP.PCIE_TOP_TRNRD88->PCIE_LOGIC_OUTS_B3_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD88" }, "PCIE_TOP.PCIE_TOP_TRNRD89->PCIE_LOGIC_OUTS_B4_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD89" }, "PCIE_TOP.PCIE_TOP_TRNRD90->PCIE_LOGIC_OUTS_B6_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD90" }, "PCIE_TOP.PCIE_TOP_TRNRD91->PCIE_LOGIC_OUTS_B1_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD91" }, "PCIE_TOP.PCIE_TOP_TRNRD92->PCIE_LOGIC_OUTS_B3_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B3_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD92" }, "PCIE_TOP.PCIE_TOP_TRNRD93->PCIE_LOGIC_OUTS_B4_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD93" }, "PCIE_TOP.PCIE_TOP_TRNRD94->PCIE_LOGIC_OUTS_B6_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD94" }, "PCIE_TOP.PCIE_TOP_TRNRD95->PCIE_LOGIC_OUTS_B2_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B2_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD95" }, "PCIE_TOP.PCIE_TOP_TRNRD96->PCIE_LOGIC_OUTS_B4_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD96" }, "PCIE_TOP.PCIE_TOP_TRNRD97->PCIE_LOGIC_OUTS_B5_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD97" }, "PCIE_TOP.PCIE_TOP_TRNRD98->PCIE_LOGIC_OUTS_B6_R_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_R_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRD98" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA32->PCIE_LOGIC_OUTS_B4_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA32" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA33->PCIE_LOGIC_OUTS_B5_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA33" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA34->PCIE_LOGIC_OUTS_B7_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA34" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA35->PCIE_LOGIC_OUTS_B8_L_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_L_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA35" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA36->PCIE_LOGIC_OUTS_B4_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA36" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA37->PCIE_LOGIC_OUTS_B5_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA37" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA38->PCIE_LOGIC_OUTS_B6_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA38" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA39->PCIE_LOGIC_OUTS_B7_L_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_L_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA39" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA40->PCIE_LOGIC_OUTS_B4_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA40" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA41->PCIE_LOGIC_OUTS_B5_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA41" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA42->PCIE_LOGIC_OUTS_B6_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA42" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA43->PCIE_LOGIC_OUTS_B7_L_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_L_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA43" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA44->PCIE_LOGIC_OUTS_B4_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA44" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA45->PCIE_LOGIC_OUTS_B5_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA45" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA46->PCIE_LOGIC_OUTS_B6_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA46" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA47->PCIE_LOGIC_OUTS_B7_L_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_L_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA47" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA48->PCIE_LOGIC_OUTS_B4_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B4_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA48" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA49->PCIE_LOGIC_OUTS_B5_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA49" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA50->PCIE_LOGIC_OUTS_B6_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA50" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA51->PCIE_LOGIC_OUTS_B7_L_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_L_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA51" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA52->PCIE_LOGIC_OUTS_B5_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA52" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA53->PCIE_LOGIC_OUTS_B6_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA53" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA54->PCIE_LOGIC_OUTS_B7_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA54" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA55->PCIE_LOGIC_OUTS_B12_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B12_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA55" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA56->PCIE_LOGIC_OUTS_B5_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B5_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA56" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA57->PCIE_LOGIC_OUTS_B6_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B6_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA57" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA58->PCIE_LOGIC_OUTS_B7_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA58" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA59->PCIE_LOGIC_OUTS_B9_R_3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B9_R_3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA59" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA60->PCIE_LOGIC_OUTS_B7_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B7_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA60" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA61->PCIE_LOGIC_OUTS_B8_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B8_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA61" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA62->PCIE_LOGIC_OUTS_B10_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA62" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPDATA63->PCIE_LOGIC_OUTS_B11_R_2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B11_R_2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPDATA63" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPSRCRDY0->PCIE_LOGIC_OUTS_B10_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B10_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPSRCRDY0" }, "PCIE_TOP.PCIE_TOP_TRNRDLLPSRCRDY1->PCIE_LOGIC_OUTS_B14_R_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B14_R_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNRDLLPSRCRDY1" }, "PCIE_TOP.PCIE_TOP_TRNTDSTRDY3->PCIE_LOGIC_OUTS_B1_R_4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "PCIE_LOGIC_OUTS_B1_R_4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "PCIE_TOP_TRNTDSTRDY3" } }, "sites": [], "tile_type": "PCIE_TOP", - "wires": [ - "PCIE_BLOCK_OUTS_B0_L_0", - "PCIE_BLOCK_OUTS_B0_L_1", - "PCIE_BLOCK_OUTS_B0_L_2", - "PCIE_BLOCK_OUTS_B0_L_3", - "PCIE_BLOCK_OUTS_B0_L_4", - "PCIE_BLOCK_OUTS_B0_R_0", - "PCIE_BLOCK_OUTS_B0_R_1", - "PCIE_BLOCK_OUTS_B0_R_2", - "PCIE_BLOCK_OUTS_B0_R_3", - "PCIE_BLOCK_OUTS_B0_R_4", - "PCIE_BLOCK_OUTS_B1_L_0", - "PCIE_BLOCK_OUTS_B1_L_1", - "PCIE_BLOCK_OUTS_B1_L_2", - "PCIE_BLOCK_OUTS_B1_L_3", - "PCIE_BLOCK_OUTS_B1_L_4", - "PCIE_BLOCK_OUTS_B1_R_0", - "PCIE_BLOCK_OUTS_B1_R_1", - "PCIE_BLOCK_OUTS_B1_R_2", - "PCIE_BLOCK_OUTS_B1_R_3", - "PCIE_BLOCK_OUTS_B1_R_4", - "PCIE_BLOCK_OUTS_B2_L_0", - "PCIE_BLOCK_OUTS_B2_L_1", - "PCIE_BLOCK_OUTS_B2_L_2", - "PCIE_BLOCK_OUTS_B2_L_3", - "PCIE_BLOCK_OUTS_B2_L_4", - "PCIE_BLOCK_OUTS_B2_R_0", - "PCIE_BLOCK_OUTS_B2_R_1", - "PCIE_BLOCK_OUTS_B2_R_2", - "PCIE_BLOCK_OUTS_B2_R_3", - "PCIE_BLOCK_OUTS_B2_R_4", - "PCIE_BLOCK_OUTS_B3_L_0", - "PCIE_BLOCK_OUTS_B3_L_1", - "PCIE_BLOCK_OUTS_B3_L_2", - "PCIE_BLOCK_OUTS_B3_L_3", - "PCIE_BLOCK_OUTS_B3_L_4", - "PCIE_BLOCK_OUTS_B3_R_0", - "PCIE_BLOCK_OUTS_B3_R_1", - "PCIE_BLOCK_OUTS_B3_R_2", - "PCIE_BLOCK_OUTS_B3_R_3", - "PCIE_BLOCK_OUTS_B3_R_4", - "PCIE_BYP0_L_0", - "PCIE_BYP0_L_1", - "PCIE_BYP0_L_2", - "PCIE_BYP0_L_3", - "PCIE_BYP0_L_4", - "PCIE_BYP0_R_0", - "PCIE_BYP0_R_1", - "PCIE_BYP0_R_2", - "PCIE_BYP0_R_3", - "PCIE_BYP0_R_4", - "PCIE_BYP1_L_0", - "PCIE_BYP1_L_1", - "PCIE_BYP1_L_2", - "PCIE_BYP1_L_3", - "PCIE_BYP1_L_4", - "PCIE_BYP1_R_0", - "PCIE_BYP1_R_1", - "PCIE_BYP1_R_2", - "PCIE_BYP1_R_3", - "PCIE_BYP1_R_4", - "PCIE_BYP2_L_0", - "PCIE_BYP2_L_1", - "PCIE_BYP2_L_2", - "PCIE_BYP2_L_3", - "PCIE_BYP2_L_4", - "PCIE_BYP2_R_0", - "PCIE_BYP2_R_1", - "PCIE_BYP2_R_2", - "PCIE_BYP2_R_3", - "PCIE_BYP2_R_4", - "PCIE_BYP3_L_0", - "PCIE_BYP3_L_1", - "PCIE_BYP3_L_2", - "PCIE_BYP3_L_3", - "PCIE_BYP3_L_4", - "PCIE_BYP3_R_0", - "PCIE_BYP3_R_1", - "PCIE_BYP3_R_2", - "PCIE_BYP3_R_3", - "PCIE_BYP3_R_4", - "PCIE_BYP4_L_0", - "PCIE_BYP4_L_1", - "PCIE_BYP4_L_2", - "PCIE_BYP4_L_3", - "PCIE_BYP4_L_4", - "PCIE_BYP4_R_0", - "PCIE_BYP4_R_1", - "PCIE_BYP4_R_2", - "PCIE_BYP4_R_3", - "PCIE_BYP4_R_4", - "PCIE_BYP5_L_0", - "PCIE_BYP5_L_1", - "PCIE_BYP5_L_2", - "PCIE_BYP5_L_3", - "PCIE_BYP5_L_4", - "PCIE_BYP5_R_0", - "PCIE_BYP5_R_1", - "PCIE_BYP5_R_2", - "PCIE_BYP5_R_3", - "PCIE_BYP5_R_4", - "PCIE_BYP6_L_0", - "PCIE_BYP6_L_1", - "PCIE_BYP6_L_2", - "PCIE_BYP6_L_3", - "PCIE_BYP6_L_4", - "PCIE_BYP6_R_0", - "PCIE_BYP6_R_1", - "PCIE_BYP6_R_2", - "PCIE_BYP6_R_3", - "PCIE_BYP6_R_4", - "PCIE_BYP7_L_0", - "PCIE_BYP7_L_1", - "PCIE_BYP7_L_2", - "PCIE_BYP7_L_3", - "PCIE_BYP7_L_4", - "PCIE_BYP7_R_0", - "PCIE_BYP7_R_1", - "PCIE_BYP7_R_2", - "PCIE_BYP7_R_3", - "PCIE_BYP7_R_4", - "PCIE_CLK0_L_0", - "PCIE_CLK0_L_1", - "PCIE_CLK0_L_2", - "PCIE_CLK0_L_3", - "PCIE_CLK0_L_4", - "PCIE_CLK0_R_0", - "PCIE_CLK0_R_1", - "PCIE_CLK0_R_2", - "PCIE_CLK0_R_3", - "PCIE_CLK0_R_4", - "PCIE_CLK1_L_0", - "PCIE_CLK1_L_1", - "PCIE_CLK1_L_2", - "PCIE_CLK1_L_3", - "PCIE_CLK1_L_4", - "PCIE_CLK1_R_0", - "PCIE_CLK1_R_1", - "PCIE_CLK1_R_2", - "PCIE_CLK1_R_3", - "PCIE_CLK1_R_4", - "PCIE_CTRL0_L_0", - "PCIE_CTRL0_L_1", - "PCIE_CTRL0_L_2", - "PCIE_CTRL0_L_3", - "PCIE_CTRL0_L_4", - "PCIE_CTRL0_R_0", - "PCIE_CTRL0_R_1", - "PCIE_CTRL0_R_2", - "PCIE_CTRL0_R_3", - "PCIE_CTRL0_R_4", - "PCIE_CTRL1_L_0", - "PCIE_CTRL1_L_1", - "PCIE_CTRL1_L_2", - "PCIE_CTRL1_L_3", - "PCIE_CTRL1_L_4", - "PCIE_CTRL1_R_0", - "PCIE_CTRL1_R_1", - "PCIE_CTRL1_R_2", - "PCIE_CTRL1_R_3", - "PCIE_CTRL1_R_4", - "PCIE_EE2A0_0", - "PCIE_EE2A0_1", - "PCIE_EE2A0_2", - "PCIE_EE2A0_3", - "PCIE_EE2A0_4", - "PCIE_EE2A1_0", - "PCIE_EE2A1_1", - "PCIE_EE2A1_2", - "PCIE_EE2A1_3", - "PCIE_EE2A1_4", - "PCIE_EE2A2_0", - "PCIE_EE2A2_1", - "PCIE_EE2A2_2", - "PCIE_EE2A2_3", - "PCIE_EE2A2_4", - "PCIE_EE2A3_0", - "PCIE_EE2A3_1", - "PCIE_EE2A3_2", - "PCIE_EE2A3_3", - "PCIE_EE2A3_4", - "PCIE_EE2BEG0_0", - "PCIE_EE2BEG0_1", - "PCIE_EE2BEG0_2", - "PCIE_EE2BEG0_3", - "PCIE_EE2BEG0_4", - "PCIE_EE2BEG1_0", - "PCIE_EE2BEG1_1", - "PCIE_EE2BEG1_2", - "PCIE_EE2BEG1_3", - "PCIE_EE2BEG1_4", - "PCIE_EE2BEG2_0", - "PCIE_EE2BEG2_1", - "PCIE_EE2BEG2_2", - "PCIE_EE2BEG2_3", - "PCIE_EE2BEG2_4", - "PCIE_EE2BEG3_0", - "PCIE_EE2BEG3_1", - "PCIE_EE2BEG3_2", - "PCIE_EE2BEG3_3", - "PCIE_EE2BEG3_4", - "PCIE_EE4A0_0", - "PCIE_EE4A0_1", - "PCIE_EE4A0_2", - "PCIE_EE4A0_3", - "PCIE_EE4A0_4", - "PCIE_EE4A1_0", - "PCIE_EE4A1_1", - "PCIE_EE4A1_2", - "PCIE_EE4A1_3", - "PCIE_EE4A1_4", - "PCIE_EE4A2_0", - "PCIE_EE4A2_1", - "PCIE_EE4A2_2", - "PCIE_EE4A2_3", - "PCIE_EE4A2_4", - "PCIE_EE4A3_0", - "PCIE_EE4A3_1", - "PCIE_EE4A3_2", - "PCIE_EE4A3_3", - "PCIE_EE4A3_4", - "PCIE_EE4B0_0", - "PCIE_EE4B0_1", - "PCIE_EE4B0_2", - "PCIE_EE4B0_3", - "PCIE_EE4B0_4", - "PCIE_EE4B1_0", - "PCIE_EE4B1_1", - "PCIE_EE4B1_2", - "PCIE_EE4B1_3", - "PCIE_EE4B1_4", - "PCIE_EE4B2_0", - "PCIE_EE4B2_1", - "PCIE_EE4B2_2", - "PCIE_EE4B2_3", - "PCIE_EE4B2_4", - "PCIE_EE4B3_0", - "PCIE_EE4B3_1", - "PCIE_EE4B3_2", - "PCIE_EE4B3_3", - "PCIE_EE4B3_4", - "PCIE_EE4BEG0_0", - "PCIE_EE4BEG0_1", - "PCIE_EE4BEG0_2", - "PCIE_EE4BEG0_3", - "PCIE_EE4BEG0_4", - "PCIE_EE4BEG1_0", - "PCIE_EE4BEG1_1", - "PCIE_EE4BEG1_2", - "PCIE_EE4BEG1_3", - "PCIE_EE4BEG1_4", - "PCIE_EE4BEG2_0", - "PCIE_EE4BEG2_1", - "PCIE_EE4BEG2_2", - "PCIE_EE4BEG2_3", - "PCIE_EE4BEG2_4", - "PCIE_EE4BEG3_0", - "PCIE_EE4BEG3_1", - "PCIE_EE4BEG3_2", - "PCIE_EE4BEG3_3", - "PCIE_EE4BEG3_4", - "PCIE_EE4C0_0", - "PCIE_EE4C0_1", - "PCIE_EE4C0_2", - "PCIE_EE4C0_3", - "PCIE_EE4C0_4", - "PCIE_EE4C1_0", - "PCIE_EE4C1_1", - "PCIE_EE4C1_2", - "PCIE_EE4C1_3", - "PCIE_EE4C1_4", - "PCIE_EE4C2_0", - "PCIE_EE4C2_1", - "PCIE_EE4C2_2", - "PCIE_EE4C2_3", - "PCIE_EE4C2_4", - "PCIE_EE4C3_0", - "PCIE_EE4C3_1", - "PCIE_EE4C3_2", - "PCIE_EE4C3_3", - "PCIE_EE4C3_4", - "PCIE_EL1BEG0_0", - "PCIE_EL1BEG0_1", - "PCIE_EL1BEG0_2", - "PCIE_EL1BEG0_3", - "PCIE_EL1BEG0_4", - "PCIE_EL1BEG1_0", - "PCIE_EL1BEG1_1", - "PCIE_EL1BEG1_2", - "PCIE_EL1BEG1_3", - "PCIE_EL1BEG1_4", - "PCIE_EL1BEG2_0", - "PCIE_EL1BEG2_1", - "PCIE_EL1BEG2_2", - "PCIE_EL1BEG2_3", - "PCIE_EL1BEG2_4", - "PCIE_EL1BEG3_0", - "PCIE_EL1BEG3_1", - "PCIE_EL1BEG3_2", - "PCIE_EL1BEG3_3", - "PCIE_EL1BEG3_4", - "PCIE_ER1BEG0_0", - "PCIE_ER1BEG0_1", - "PCIE_ER1BEG0_2", - "PCIE_ER1BEG0_3", - "PCIE_ER1BEG0_4", - "PCIE_ER1BEG1_0", - "PCIE_ER1BEG1_1", - "PCIE_ER1BEG1_2", - "PCIE_ER1BEG1_3", - "PCIE_ER1BEG1_4", - "PCIE_ER1BEG2_0", - "PCIE_ER1BEG2_1", - "PCIE_ER1BEG2_2", - "PCIE_ER1BEG2_3", - "PCIE_ER1BEG2_4", - "PCIE_ER1BEG3_0", - "PCIE_ER1BEG3_1", - "PCIE_ER1BEG3_2", - "PCIE_ER1BEG3_3", - "PCIE_ER1BEG3_4", - "PCIE_FAN0_L_0", - "PCIE_FAN0_L_1", - "PCIE_FAN0_L_2", - "PCIE_FAN0_L_3", - "PCIE_FAN0_L_4", - "PCIE_FAN0_R_0", - "PCIE_FAN0_R_1", - "PCIE_FAN0_R_2", - "PCIE_FAN0_R_3", - "PCIE_FAN0_R_4", - "PCIE_FAN1_L_0", - "PCIE_FAN1_L_1", - "PCIE_FAN1_L_2", - "PCIE_FAN1_L_3", - "PCIE_FAN1_L_4", - "PCIE_FAN1_R_0", - "PCIE_FAN1_R_1", - "PCIE_FAN1_R_2", - "PCIE_FAN1_R_3", - "PCIE_FAN1_R_4", - "PCIE_FAN2_L_0", - "PCIE_FAN2_L_1", - "PCIE_FAN2_L_2", - "PCIE_FAN2_L_3", - "PCIE_FAN2_L_4", - "PCIE_FAN2_R_0", - "PCIE_FAN2_R_1", - "PCIE_FAN2_R_2", - "PCIE_FAN2_R_3", - "PCIE_FAN2_R_4", - "PCIE_FAN3_L_0", - "PCIE_FAN3_L_1", - "PCIE_FAN3_L_2", - "PCIE_FAN3_L_3", - "PCIE_FAN3_L_4", - "PCIE_FAN3_R_0", - "PCIE_FAN3_R_1", - "PCIE_FAN3_R_2", - "PCIE_FAN3_R_3", - "PCIE_FAN3_R_4", - "PCIE_FAN4_L_0", - "PCIE_FAN4_L_1", - "PCIE_FAN4_L_2", - "PCIE_FAN4_L_3", - "PCIE_FAN4_L_4", - "PCIE_FAN4_R_0", - "PCIE_FAN4_R_1", - "PCIE_FAN4_R_2", - "PCIE_FAN4_R_3", - "PCIE_FAN4_R_4", - "PCIE_FAN5_L_0", - "PCIE_FAN5_L_1", - "PCIE_FAN5_L_2", - "PCIE_FAN5_L_3", - "PCIE_FAN5_L_4", - "PCIE_FAN5_R_0", - "PCIE_FAN5_R_1", - "PCIE_FAN5_R_2", - "PCIE_FAN5_R_3", - "PCIE_FAN5_R_4", - "PCIE_FAN6_L_0", - "PCIE_FAN6_L_1", - "PCIE_FAN6_L_2", - "PCIE_FAN6_L_3", - "PCIE_FAN6_L_4", - "PCIE_FAN6_R_0", - "PCIE_FAN6_R_1", - "PCIE_FAN6_R_2", - "PCIE_FAN6_R_3", - "PCIE_FAN6_R_4", - "PCIE_FAN7_L_0", - "PCIE_FAN7_L_1", - "PCIE_FAN7_L_2", - "PCIE_FAN7_L_3", - "PCIE_FAN7_L_4", - "PCIE_FAN7_R_0", - "PCIE_FAN7_R_1", - "PCIE_FAN7_R_2", - "PCIE_FAN7_R_3", - "PCIE_FAN7_R_4", - "PCIE_IMUX0_L_0", - "PCIE_IMUX0_L_1", - "PCIE_IMUX0_L_2", - "PCIE_IMUX0_L_3", - "PCIE_IMUX0_L_4", - "PCIE_IMUX0_R_0", - "PCIE_IMUX0_R_1", - "PCIE_IMUX0_R_2", - "PCIE_IMUX0_R_3", - "PCIE_IMUX0_R_4", - "PCIE_IMUX10_L_0", - "PCIE_IMUX10_L_1", - "PCIE_IMUX10_L_2", - "PCIE_IMUX10_L_3", - "PCIE_IMUX10_L_4", - "PCIE_IMUX10_R_0", - "PCIE_IMUX10_R_1", - "PCIE_IMUX10_R_2", - "PCIE_IMUX10_R_3", - "PCIE_IMUX10_R_4", - "PCIE_IMUX11_L_0", - "PCIE_IMUX11_L_1", - "PCIE_IMUX11_L_2", - "PCIE_IMUX11_L_3", - "PCIE_IMUX11_L_4", - "PCIE_IMUX11_R_0", - "PCIE_IMUX11_R_1", - "PCIE_IMUX11_R_2", - "PCIE_IMUX11_R_3", - "PCIE_IMUX11_R_4", - "PCIE_IMUX12_L_0", - "PCIE_IMUX12_L_1", - "PCIE_IMUX12_L_2", - "PCIE_IMUX12_L_3", - "PCIE_IMUX12_L_4", - "PCIE_IMUX12_R_0", - "PCIE_IMUX12_R_1", - "PCIE_IMUX12_R_2", - "PCIE_IMUX12_R_3", - "PCIE_IMUX12_R_4", - "PCIE_IMUX13_L_0", - "PCIE_IMUX13_L_1", - "PCIE_IMUX13_L_2", - "PCIE_IMUX13_L_3", - "PCIE_IMUX13_L_4", - "PCIE_IMUX13_R_0", - "PCIE_IMUX13_R_1", - "PCIE_IMUX13_R_2", - "PCIE_IMUX13_R_3", - "PCIE_IMUX13_R_4", - "PCIE_IMUX14_L_0", - "PCIE_IMUX14_L_1", - "PCIE_IMUX14_L_2", - "PCIE_IMUX14_L_3", - "PCIE_IMUX14_L_4", - "PCIE_IMUX14_R_0", - "PCIE_IMUX14_R_1", - "PCIE_IMUX14_R_2", - "PCIE_IMUX14_R_3", - "PCIE_IMUX14_R_4", - "PCIE_IMUX15_L_0", - "PCIE_IMUX15_L_1", - "PCIE_IMUX15_L_2", - "PCIE_IMUX15_L_3", - "PCIE_IMUX15_L_4", - "PCIE_IMUX15_R_0", - "PCIE_IMUX15_R_1", - "PCIE_IMUX15_R_2", - "PCIE_IMUX15_R_3", - "PCIE_IMUX15_R_4", - "PCIE_IMUX16_L_0", - "PCIE_IMUX16_L_1", - "PCIE_IMUX16_L_2", - "PCIE_IMUX16_L_3", - "PCIE_IMUX16_L_4", - "PCIE_IMUX16_R_0", - "PCIE_IMUX16_R_1", - "PCIE_IMUX16_R_2", - "PCIE_IMUX16_R_3", - "PCIE_IMUX16_R_4", - "PCIE_IMUX17_L_0", - "PCIE_IMUX17_L_1", - "PCIE_IMUX17_L_2", - "PCIE_IMUX17_L_3", - "PCIE_IMUX17_L_4", - "PCIE_IMUX17_R_0", - "PCIE_IMUX17_R_1", - "PCIE_IMUX17_R_2", - "PCIE_IMUX17_R_3", - "PCIE_IMUX17_R_4", - "PCIE_IMUX18_L_0", - "PCIE_IMUX18_L_1", - "PCIE_IMUX18_L_2", - "PCIE_IMUX18_L_3", - "PCIE_IMUX18_L_4", - "PCIE_IMUX18_R_0", - "PCIE_IMUX18_R_1", - "PCIE_IMUX18_R_2", - "PCIE_IMUX18_R_3", - "PCIE_IMUX18_R_4", - "PCIE_IMUX19_L_0", - "PCIE_IMUX19_L_1", - "PCIE_IMUX19_L_2", - "PCIE_IMUX19_L_3", - "PCIE_IMUX19_L_4", - "PCIE_IMUX19_R_0", - "PCIE_IMUX19_R_1", - "PCIE_IMUX19_R_2", - "PCIE_IMUX19_R_3", - "PCIE_IMUX19_R_4", - "PCIE_IMUX1_L_0", - "PCIE_IMUX1_L_1", - "PCIE_IMUX1_L_2", - "PCIE_IMUX1_L_3", - "PCIE_IMUX1_L_4", - "PCIE_IMUX1_R_0", - "PCIE_IMUX1_R_1", - "PCIE_IMUX1_R_2", - "PCIE_IMUX1_R_3", - "PCIE_IMUX1_R_4", - "PCIE_IMUX20_L_0", - "PCIE_IMUX20_L_1", - "PCIE_IMUX20_L_2", - "PCIE_IMUX20_L_3", - "PCIE_IMUX20_L_4", - "PCIE_IMUX20_R_0", - "PCIE_IMUX20_R_1", - "PCIE_IMUX20_R_2", - "PCIE_IMUX20_R_3", - "PCIE_IMUX20_R_4", - "PCIE_IMUX21_L_0", - "PCIE_IMUX21_L_1", - "PCIE_IMUX21_L_2", - "PCIE_IMUX21_L_3", - "PCIE_IMUX21_L_4", - "PCIE_IMUX21_R_0", - "PCIE_IMUX21_R_1", - "PCIE_IMUX21_R_2", - "PCIE_IMUX21_R_3", - "PCIE_IMUX21_R_4", - "PCIE_IMUX22_L_0", - "PCIE_IMUX22_L_1", - "PCIE_IMUX22_L_2", - "PCIE_IMUX22_L_3", - "PCIE_IMUX22_L_4", - "PCIE_IMUX22_R_0", - "PCIE_IMUX22_R_1", - "PCIE_IMUX22_R_2", - "PCIE_IMUX22_R_3", - "PCIE_IMUX22_R_4", - "PCIE_IMUX23_L_0", - "PCIE_IMUX23_L_1", - "PCIE_IMUX23_L_2", - "PCIE_IMUX23_L_3", - "PCIE_IMUX23_L_4", - "PCIE_IMUX23_R_0", - "PCIE_IMUX23_R_1", - "PCIE_IMUX23_R_2", - "PCIE_IMUX23_R_3", - "PCIE_IMUX23_R_4", - "PCIE_IMUX24_L_0", - "PCIE_IMUX24_L_1", - "PCIE_IMUX24_L_2", - "PCIE_IMUX24_L_3", - "PCIE_IMUX24_L_4", - "PCIE_IMUX24_R_0", - "PCIE_IMUX24_R_1", - "PCIE_IMUX24_R_2", - "PCIE_IMUX24_R_3", - "PCIE_IMUX24_R_4", - "PCIE_IMUX25_L_0", - "PCIE_IMUX25_L_1", - "PCIE_IMUX25_L_2", - "PCIE_IMUX25_L_3", - "PCIE_IMUX25_L_4", - "PCIE_IMUX25_R_0", - "PCIE_IMUX25_R_1", - "PCIE_IMUX25_R_2", - "PCIE_IMUX25_R_3", - "PCIE_IMUX25_R_4", - "PCIE_IMUX26_L_0", - "PCIE_IMUX26_L_1", - "PCIE_IMUX26_L_2", - "PCIE_IMUX26_L_3", - "PCIE_IMUX26_L_4", - "PCIE_IMUX26_R_0", - "PCIE_IMUX26_R_1", - "PCIE_IMUX26_R_2", - "PCIE_IMUX26_R_3", - "PCIE_IMUX26_R_4", - "PCIE_IMUX27_L_0", - "PCIE_IMUX27_L_1", - "PCIE_IMUX27_L_2", - "PCIE_IMUX27_L_3", - "PCIE_IMUX27_L_4", - "PCIE_IMUX27_R_0", - "PCIE_IMUX27_R_1", - "PCIE_IMUX27_R_2", - "PCIE_IMUX27_R_3", - "PCIE_IMUX27_R_4", - "PCIE_IMUX28_L_0", - "PCIE_IMUX28_L_1", - "PCIE_IMUX28_L_2", - "PCIE_IMUX28_L_3", - "PCIE_IMUX28_L_4", - "PCIE_IMUX28_R_0", - "PCIE_IMUX28_R_1", - "PCIE_IMUX28_R_2", - "PCIE_IMUX28_R_3", - "PCIE_IMUX28_R_4", - "PCIE_IMUX29_L_0", - "PCIE_IMUX29_L_1", - "PCIE_IMUX29_L_2", - "PCIE_IMUX29_L_3", - "PCIE_IMUX29_L_4", - "PCIE_IMUX29_R_0", - "PCIE_IMUX29_R_1", - "PCIE_IMUX29_R_2", - "PCIE_IMUX29_R_3", - "PCIE_IMUX29_R_4", - "PCIE_IMUX2_L_0", - "PCIE_IMUX2_L_1", - "PCIE_IMUX2_L_2", - "PCIE_IMUX2_L_3", - "PCIE_IMUX2_L_4", - "PCIE_IMUX2_R_0", - "PCIE_IMUX2_R_1", - "PCIE_IMUX2_R_2", - "PCIE_IMUX2_R_3", - "PCIE_IMUX2_R_4", - "PCIE_IMUX30_L_0", - "PCIE_IMUX30_L_1", - "PCIE_IMUX30_L_2", - "PCIE_IMUX30_L_3", - "PCIE_IMUX30_L_4", - "PCIE_IMUX30_R_0", - "PCIE_IMUX30_R_1", - "PCIE_IMUX30_R_2", - "PCIE_IMUX30_R_3", - "PCIE_IMUX30_R_4", - "PCIE_IMUX31_L_0", - "PCIE_IMUX31_L_1", - "PCIE_IMUX31_L_2", - "PCIE_IMUX31_L_3", - "PCIE_IMUX31_L_4", - "PCIE_IMUX31_R_0", - "PCIE_IMUX31_R_1", - "PCIE_IMUX31_R_2", - "PCIE_IMUX31_R_3", - "PCIE_IMUX31_R_4", - "PCIE_IMUX32_L_0", - "PCIE_IMUX32_L_1", - "PCIE_IMUX32_L_2", - "PCIE_IMUX32_L_3", - "PCIE_IMUX32_L_4", - "PCIE_IMUX32_R_0", - "PCIE_IMUX32_R_1", - "PCIE_IMUX32_R_2", - "PCIE_IMUX32_R_3", - "PCIE_IMUX32_R_4", - "PCIE_IMUX33_L_0", - "PCIE_IMUX33_L_1", - "PCIE_IMUX33_L_2", - "PCIE_IMUX33_L_3", - "PCIE_IMUX33_L_4", - "PCIE_IMUX33_R_0", - "PCIE_IMUX33_R_1", - "PCIE_IMUX33_R_2", - "PCIE_IMUX33_R_3", - "PCIE_IMUX33_R_4", - "PCIE_IMUX34_L_0", - "PCIE_IMUX34_L_1", - "PCIE_IMUX34_L_2", - "PCIE_IMUX34_L_3", - "PCIE_IMUX34_L_4", - "PCIE_IMUX34_R_0", - "PCIE_IMUX34_R_1", - "PCIE_IMUX34_R_2", - "PCIE_IMUX34_R_3", - "PCIE_IMUX34_R_4", - "PCIE_IMUX35_L_0", - "PCIE_IMUX35_L_1", - "PCIE_IMUX35_L_2", - "PCIE_IMUX35_L_3", - "PCIE_IMUX35_L_4", - "PCIE_IMUX35_R_0", - "PCIE_IMUX35_R_1", - "PCIE_IMUX35_R_2", - "PCIE_IMUX35_R_3", - "PCIE_IMUX35_R_4", - "PCIE_IMUX36_L_0", - "PCIE_IMUX36_L_1", - "PCIE_IMUX36_L_2", - "PCIE_IMUX36_L_3", - "PCIE_IMUX36_L_4", - "PCIE_IMUX36_R_0", - "PCIE_IMUX36_R_1", - "PCIE_IMUX36_R_2", - "PCIE_IMUX36_R_3", - "PCIE_IMUX36_R_4", - "PCIE_IMUX37_L_0", - "PCIE_IMUX37_L_1", - "PCIE_IMUX37_L_2", - "PCIE_IMUX37_L_3", - "PCIE_IMUX37_L_4", - "PCIE_IMUX37_R_0", - "PCIE_IMUX37_R_1", - "PCIE_IMUX37_R_2", - "PCIE_IMUX37_R_3", - "PCIE_IMUX37_R_4", - "PCIE_IMUX38_L_0", - "PCIE_IMUX38_L_1", - "PCIE_IMUX38_L_2", - "PCIE_IMUX38_L_3", - "PCIE_IMUX38_L_4", - "PCIE_IMUX38_R_0", - "PCIE_IMUX38_R_1", - "PCIE_IMUX38_R_2", - "PCIE_IMUX38_R_3", - "PCIE_IMUX38_R_4", - "PCIE_IMUX39_L_0", - "PCIE_IMUX39_L_1", - "PCIE_IMUX39_L_2", - "PCIE_IMUX39_L_3", - "PCIE_IMUX39_L_4", - "PCIE_IMUX39_R_0", - "PCIE_IMUX39_R_1", - "PCIE_IMUX39_R_2", - "PCIE_IMUX39_R_3", - "PCIE_IMUX39_R_4", - "PCIE_IMUX3_L_0", - "PCIE_IMUX3_L_1", - "PCIE_IMUX3_L_2", - "PCIE_IMUX3_L_3", - "PCIE_IMUX3_L_4", - "PCIE_IMUX3_R_0", - "PCIE_IMUX3_R_1", - "PCIE_IMUX3_R_2", - "PCIE_IMUX3_R_3", - "PCIE_IMUX3_R_4", - "PCIE_IMUX40_L_0", - "PCIE_IMUX40_L_1", - "PCIE_IMUX40_L_2", - "PCIE_IMUX40_L_3", - "PCIE_IMUX40_L_4", - "PCIE_IMUX40_R_0", - "PCIE_IMUX40_R_1", - "PCIE_IMUX40_R_2", - "PCIE_IMUX40_R_3", - "PCIE_IMUX40_R_4", - "PCIE_IMUX41_L_0", - "PCIE_IMUX41_L_1", - "PCIE_IMUX41_L_2", - "PCIE_IMUX41_L_3", - "PCIE_IMUX41_L_4", - "PCIE_IMUX41_R_0", - "PCIE_IMUX41_R_1", - "PCIE_IMUX41_R_2", - "PCIE_IMUX41_R_3", - "PCIE_IMUX41_R_4", - "PCIE_IMUX42_L_0", - "PCIE_IMUX42_L_1", - "PCIE_IMUX42_L_2", - "PCIE_IMUX42_L_3", - "PCIE_IMUX42_L_4", - "PCIE_IMUX42_R_0", - "PCIE_IMUX42_R_1", - "PCIE_IMUX42_R_2", - "PCIE_IMUX42_R_3", - "PCIE_IMUX42_R_4", - "PCIE_IMUX43_L_0", - "PCIE_IMUX43_L_1", - "PCIE_IMUX43_L_2", - "PCIE_IMUX43_L_3", - "PCIE_IMUX43_L_4", - "PCIE_IMUX43_R_0", - "PCIE_IMUX43_R_1", - "PCIE_IMUX43_R_2", - "PCIE_IMUX43_R_3", - "PCIE_IMUX43_R_4", - "PCIE_IMUX44_L_0", - "PCIE_IMUX44_L_1", - "PCIE_IMUX44_L_2", - "PCIE_IMUX44_L_3", - "PCIE_IMUX44_L_4", - "PCIE_IMUX44_R_0", - "PCIE_IMUX44_R_1", - "PCIE_IMUX44_R_2", - "PCIE_IMUX44_R_3", - "PCIE_IMUX44_R_4", - "PCIE_IMUX45_L_0", - "PCIE_IMUX45_L_1", - "PCIE_IMUX45_L_2", - "PCIE_IMUX45_L_3", - "PCIE_IMUX45_L_4", - "PCIE_IMUX45_R_0", - "PCIE_IMUX45_R_1", - "PCIE_IMUX45_R_2", - "PCIE_IMUX45_R_3", - "PCIE_IMUX45_R_4", - "PCIE_IMUX46_L_0", - "PCIE_IMUX46_L_1", - "PCIE_IMUX46_L_2", - "PCIE_IMUX46_L_3", - "PCIE_IMUX46_L_4", - "PCIE_IMUX46_R_0", - "PCIE_IMUX46_R_1", - "PCIE_IMUX46_R_2", - "PCIE_IMUX46_R_3", - "PCIE_IMUX46_R_4", - "PCIE_IMUX47_L_0", - "PCIE_IMUX47_L_1", - "PCIE_IMUX47_L_2", - "PCIE_IMUX47_L_3", - "PCIE_IMUX47_L_4", - "PCIE_IMUX47_R_0", - "PCIE_IMUX47_R_1", - "PCIE_IMUX47_R_2", - "PCIE_IMUX47_R_3", - "PCIE_IMUX47_R_4", - "PCIE_IMUX4_L_0", - "PCIE_IMUX4_L_1", - "PCIE_IMUX4_L_2", - "PCIE_IMUX4_L_3", - "PCIE_IMUX4_L_4", - "PCIE_IMUX4_R_0", - "PCIE_IMUX4_R_1", - "PCIE_IMUX4_R_2", - "PCIE_IMUX4_R_3", - "PCIE_IMUX4_R_4", - "PCIE_IMUX5_L_0", - "PCIE_IMUX5_L_1", - "PCIE_IMUX5_L_2", - "PCIE_IMUX5_L_3", - "PCIE_IMUX5_L_4", - "PCIE_IMUX5_R_0", - "PCIE_IMUX5_R_1", - "PCIE_IMUX5_R_2", - "PCIE_IMUX5_R_3", - "PCIE_IMUX5_R_4", - "PCIE_IMUX6_L_0", - "PCIE_IMUX6_L_1", - "PCIE_IMUX6_L_2", - "PCIE_IMUX6_L_3", - "PCIE_IMUX6_L_4", - "PCIE_IMUX6_R_0", - "PCIE_IMUX6_R_1", - "PCIE_IMUX6_R_2", - "PCIE_IMUX6_R_3", - "PCIE_IMUX6_R_4", - "PCIE_IMUX7_L_0", - "PCIE_IMUX7_L_1", - "PCIE_IMUX7_L_2", - "PCIE_IMUX7_L_3", - "PCIE_IMUX7_L_4", - "PCIE_IMUX7_R_0", - "PCIE_IMUX7_R_1", - "PCIE_IMUX7_R_2", - "PCIE_IMUX7_R_3", - "PCIE_IMUX7_R_4", - "PCIE_IMUX8_L_0", - "PCIE_IMUX8_L_1", - "PCIE_IMUX8_L_2", - "PCIE_IMUX8_L_3", - "PCIE_IMUX8_L_4", - "PCIE_IMUX8_R_0", - "PCIE_IMUX8_R_1", - "PCIE_IMUX8_R_2", - "PCIE_IMUX8_R_3", - "PCIE_IMUX8_R_4", - "PCIE_IMUX9_L_0", - "PCIE_IMUX9_L_1", - "PCIE_IMUX9_L_2", - "PCIE_IMUX9_L_3", - "PCIE_IMUX9_L_4", - "PCIE_IMUX9_R_0", - "PCIE_IMUX9_R_1", - "PCIE_IMUX9_R_2", - "PCIE_IMUX9_R_3", - "PCIE_IMUX9_R_4", - "PCIE_LH10_0", - "PCIE_LH10_1", - "PCIE_LH10_2", - "PCIE_LH10_3", - "PCIE_LH10_4", - "PCIE_LH11_0", - "PCIE_LH11_1", - "PCIE_LH11_2", - "PCIE_LH11_3", - "PCIE_LH11_4", - "PCIE_LH12_0", - "PCIE_LH12_1", - "PCIE_LH12_2", - "PCIE_LH12_3", - "PCIE_LH12_4", - "PCIE_LH1_0", - "PCIE_LH1_1", - "PCIE_LH1_2", - "PCIE_LH1_3", - "PCIE_LH1_4", - "PCIE_LH2_0", - "PCIE_LH2_1", - "PCIE_LH2_2", - "PCIE_LH2_3", - "PCIE_LH2_4", - "PCIE_LH3_0", - "PCIE_LH3_1", - "PCIE_LH3_2", - "PCIE_LH3_3", - "PCIE_LH3_4", - "PCIE_LH4_0", - "PCIE_LH4_1", - "PCIE_LH4_2", - "PCIE_LH4_3", - "PCIE_LH4_4", - "PCIE_LH5_0", - "PCIE_LH5_1", - "PCIE_LH5_2", - "PCIE_LH5_3", - "PCIE_LH5_4", - "PCIE_LH6_0", - "PCIE_LH6_1", - "PCIE_LH6_2", - "PCIE_LH6_3", - "PCIE_LH6_4", - "PCIE_LH7_0", - "PCIE_LH7_1", - "PCIE_LH7_2", - "PCIE_LH7_3", - "PCIE_LH7_4", - "PCIE_LH8_0", - "PCIE_LH8_1", - "PCIE_LH8_2", - "PCIE_LH8_3", - "PCIE_LH8_4", - "PCIE_LH9_0", - "PCIE_LH9_1", - "PCIE_LH9_2", - "PCIE_LH9_3", - "PCIE_LH9_4", - "PCIE_LOGIC_OUTS_B0_L_0", - "PCIE_LOGIC_OUTS_B0_L_1", - "PCIE_LOGIC_OUTS_B0_L_2", - "PCIE_LOGIC_OUTS_B0_L_3", - "PCIE_LOGIC_OUTS_B0_L_4", - "PCIE_LOGIC_OUTS_B0_R_0", - "PCIE_LOGIC_OUTS_B0_R_1", - "PCIE_LOGIC_OUTS_B0_R_2", - "PCIE_LOGIC_OUTS_B0_R_3", - "PCIE_LOGIC_OUTS_B0_R_4", - "PCIE_LOGIC_OUTS_B10_L_0", - "PCIE_LOGIC_OUTS_B10_L_1", - "PCIE_LOGIC_OUTS_B10_L_2", - "PCIE_LOGIC_OUTS_B10_L_3", - "PCIE_LOGIC_OUTS_B10_L_4", - "PCIE_LOGIC_OUTS_B10_R_0", - "PCIE_LOGIC_OUTS_B10_R_1", - "PCIE_LOGIC_OUTS_B10_R_2", - "PCIE_LOGIC_OUTS_B10_R_3", - "PCIE_LOGIC_OUTS_B10_R_4", - "PCIE_LOGIC_OUTS_B11_L_0", - "PCIE_LOGIC_OUTS_B11_L_1", - "PCIE_LOGIC_OUTS_B11_L_2", - "PCIE_LOGIC_OUTS_B11_L_3", - "PCIE_LOGIC_OUTS_B11_L_4", - "PCIE_LOGIC_OUTS_B11_R_0", - "PCIE_LOGIC_OUTS_B11_R_1", - "PCIE_LOGIC_OUTS_B11_R_2", - "PCIE_LOGIC_OUTS_B11_R_3", - "PCIE_LOGIC_OUTS_B11_R_4", - "PCIE_LOGIC_OUTS_B12_L_0", - "PCIE_LOGIC_OUTS_B12_L_1", - "PCIE_LOGIC_OUTS_B12_L_2", - "PCIE_LOGIC_OUTS_B12_L_3", - "PCIE_LOGIC_OUTS_B12_L_4", - "PCIE_LOGIC_OUTS_B12_R_0", - "PCIE_LOGIC_OUTS_B12_R_1", - "PCIE_LOGIC_OUTS_B12_R_2", - "PCIE_LOGIC_OUTS_B12_R_3", - "PCIE_LOGIC_OUTS_B12_R_4", - "PCIE_LOGIC_OUTS_B13_L_0", - "PCIE_LOGIC_OUTS_B13_L_1", - "PCIE_LOGIC_OUTS_B13_L_2", - "PCIE_LOGIC_OUTS_B13_L_3", - "PCIE_LOGIC_OUTS_B13_L_4", - "PCIE_LOGIC_OUTS_B13_R_0", - "PCIE_LOGIC_OUTS_B13_R_1", - "PCIE_LOGIC_OUTS_B13_R_2", - "PCIE_LOGIC_OUTS_B13_R_3", - "PCIE_LOGIC_OUTS_B13_R_4", - "PCIE_LOGIC_OUTS_B14_L_0", - "PCIE_LOGIC_OUTS_B14_L_1", - "PCIE_LOGIC_OUTS_B14_L_2", - "PCIE_LOGIC_OUTS_B14_L_3", - "PCIE_LOGIC_OUTS_B14_L_4", - "PCIE_LOGIC_OUTS_B14_R_0", - "PCIE_LOGIC_OUTS_B14_R_1", - "PCIE_LOGIC_OUTS_B14_R_2", - "PCIE_LOGIC_OUTS_B14_R_3", - "PCIE_LOGIC_OUTS_B14_R_4", - "PCIE_LOGIC_OUTS_B15_L_0", - "PCIE_LOGIC_OUTS_B15_L_1", - "PCIE_LOGIC_OUTS_B15_L_2", - "PCIE_LOGIC_OUTS_B15_L_3", - "PCIE_LOGIC_OUTS_B15_L_4", - "PCIE_LOGIC_OUTS_B15_R_0", - "PCIE_LOGIC_OUTS_B15_R_1", - "PCIE_LOGIC_OUTS_B15_R_2", - "PCIE_LOGIC_OUTS_B15_R_3", - "PCIE_LOGIC_OUTS_B15_R_4", - "PCIE_LOGIC_OUTS_B16_L_0", - "PCIE_LOGIC_OUTS_B16_L_1", - "PCIE_LOGIC_OUTS_B16_L_2", - "PCIE_LOGIC_OUTS_B16_L_3", - "PCIE_LOGIC_OUTS_B16_L_4", - "PCIE_LOGIC_OUTS_B16_R_0", - "PCIE_LOGIC_OUTS_B16_R_1", - "PCIE_LOGIC_OUTS_B16_R_2", - "PCIE_LOGIC_OUTS_B16_R_3", - "PCIE_LOGIC_OUTS_B16_R_4", - "PCIE_LOGIC_OUTS_B17_L_0", - "PCIE_LOGIC_OUTS_B17_L_1", - "PCIE_LOGIC_OUTS_B17_L_2", - "PCIE_LOGIC_OUTS_B17_L_3", - "PCIE_LOGIC_OUTS_B17_L_4", - "PCIE_LOGIC_OUTS_B17_R_0", - "PCIE_LOGIC_OUTS_B17_R_1", - "PCIE_LOGIC_OUTS_B17_R_2", - "PCIE_LOGIC_OUTS_B17_R_3", - "PCIE_LOGIC_OUTS_B17_R_4", - "PCIE_LOGIC_OUTS_B18_L_0", - "PCIE_LOGIC_OUTS_B18_L_1", - "PCIE_LOGIC_OUTS_B18_L_2", - "PCIE_LOGIC_OUTS_B18_L_3", - "PCIE_LOGIC_OUTS_B18_L_4", - "PCIE_LOGIC_OUTS_B18_R_0", - "PCIE_LOGIC_OUTS_B18_R_1", - "PCIE_LOGIC_OUTS_B18_R_2", - "PCIE_LOGIC_OUTS_B18_R_3", - "PCIE_LOGIC_OUTS_B18_R_4", - "PCIE_LOGIC_OUTS_B19_L_0", - "PCIE_LOGIC_OUTS_B19_L_1", - "PCIE_LOGIC_OUTS_B19_L_2", - "PCIE_LOGIC_OUTS_B19_L_3", - "PCIE_LOGIC_OUTS_B19_L_4", - "PCIE_LOGIC_OUTS_B19_R_0", - "PCIE_LOGIC_OUTS_B19_R_1", - "PCIE_LOGIC_OUTS_B19_R_2", - "PCIE_LOGIC_OUTS_B19_R_3", - "PCIE_LOGIC_OUTS_B19_R_4", - "PCIE_LOGIC_OUTS_B1_L_0", - "PCIE_LOGIC_OUTS_B1_L_1", - "PCIE_LOGIC_OUTS_B1_L_2", - "PCIE_LOGIC_OUTS_B1_L_3", - "PCIE_LOGIC_OUTS_B1_L_4", - "PCIE_LOGIC_OUTS_B1_R_0", - "PCIE_LOGIC_OUTS_B1_R_1", - "PCIE_LOGIC_OUTS_B1_R_2", - "PCIE_LOGIC_OUTS_B1_R_3", - "PCIE_LOGIC_OUTS_B1_R_4", - "PCIE_LOGIC_OUTS_B20_L_0", - "PCIE_LOGIC_OUTS_B20_L_1", - "PCIE_LOGIC_OUTS_B20_L_2", - "PCIE_LOGIC_OUTS_B20_L_3", - "PCIE_LOGIC_OUTS_B20_L_4", - "PCIE_LOGIC_OUTS_B20_R_0", - "PCIE_LOGIC_OUTS_B20_R_1", - "PCIE_LOGIC_OUTS_B20_R_2", - "PCIE_LOGIC_OUTS_B20_R_3", - "PCIE_LOGIC_OUTS_B20_R_4", - "PCIE_LOGIC_OUTS_B21_L_0", - "PCIE_LOGIC_OUTS_B21_L_1", - "PCIE_LOGIC_OUTS_B21_L_2", - "PCIE_LOGIC_OUTS_B21_L_3", - "PCIE_LOGIC_OUTS_B21_L_4", - "PCIE_LOGIC_OUTS_B21_R_0", - "PCIE_LOGIC_OUTS_B21_R_1", - "PCIE_LOGIC_OUTS_B21_R_2", - "PCIE_LOGIC_OUTS_B21_R_3", - "PCIE_LOGIC_OUTS_B21_R_4", - "PCIE_LOGIC_OUTS_B22_L_0", - "PCIE_LOGIC_OUTS_B22_L_1", - "PCIE_LOGIC_OUTS_B22_L_2", - "PCIE_LOGIC_OUTS_B22_L_3", - "PCIE_LOGIC_OUTS_B22_L_4", - "PCIE_LOGIC_OUTS_B22_R_0", - "PCIE_LOGIC_OUTS_B22_R_1", - "PCIE_LOGIC_OUTS_B22_R_2", - "PCIE_LOGIC_OUTS_B22_R_3", - "PCIE_LOGIC_OUTS_B22_R_4", - "PCIE_LOGIC_OUTS_B23_L_0", - "PCIE_LOGIC_OUTS_B23_L_1", - "PCIE_LOGIC_OUTS_B23_L_2", - "PCIE_LOGIC_OUTS_B23_L_3", - "PCIE_LOGIC_OUTS_B23_L_4", - "PCIE_LOGIC_OUTS_B23_R_0", - "PCIE_LOGIC_OUTS_B23_R_1", - "PCIE_LOGIC_OUTS_B23_R_2", - "PCIE_LOGIC_OUTS_B23_R_3", - "PCIE_LOGIC_OUTS_B23_R_4", - "PCIE_LOGIC_OUTS_B2_L_0", - "PCIE_LOGIC_OUTS_B2_L_1", - "PCIE_LOGIC_OUTS_B2_L_2", - "PCIE_LOGIC_OUTS_B2_L_3", - "PCIE_LOGIC_OUTS_B2_L_4", - "PCIE_LOGIC_OUTS_B2_R_0", - "PCIE_LOGIC_OUTS_B2_R_1", - "PCIE_LOGIC_OUTS_B2_R_2", - "PCIE_LOGIC_OUTS_B2_R_3", - "PCIE_LOGIC_OUTS_B2_R_4", - "PCIE_LOGIC_OUTS_B3_L_0", - "PCIE_LOGIC_OUTS_B3_L_1", - "PCIE_LOGIC_OUTS_B3_L_2", - "PCIE_LOGIC_OUTS_B3_L_3", - "PCIE_LOGIC_OUTS_B3_L_4", - "PCIE_LOGIC_OUTS_B3_R_0", - "PCIE_LOGIC_OUTS_B3_R_1", - "PCIE_LOGIC_OUTS_B3_R_2", - "PCIE_LOGIC_OUTS_B3_R_3", - "PCIE_LOGIC_OUTS_B3_R_4", - "PCIE_LOGIC_OUTS_B4_L_0", - "PCIE_LOGIC_OUTS_B4_L_1", - "PCIE_LOGIC_OUTS_B4_L_2", - "PCIE_LOGIC_OUTS_B4_L_3", - "PCIE_LOGIC_OUTS_B4_L_4", - "PCIE_LOGIC_OUTS_B4_R_0", - "PCIE_LOGIC_OUTS_B4_R_1", - "PCIE_LOGIC_OUTS_B4_R_2", - "PCIE_LOGIC_OUTS_B4_R_3", - "PCIE_LOGIC_OUTS_B4_R_4", - "PCIE_LOGIC_OUTS_B5_L_0", - "PCIE_LOGIC_OUTS_B5_L_1", - "PCIE_LOGIC_OUTS_B5_L_2", - "PCIE_LOGIC_OUTS_B5_L_3", - "PCIE_LOGIC_OUTS_B5_L_4", - "PCIE_LOGIC_OUTS_B5_R_0", - "PCIE_LOGIC_OUTS_B5_R_1", - "PCIE_LOGIC_OUTS_B5_R_2", - "PCIE_LOGIC_OUTS_B5_R_3", - "PCIE_LOGIC_OUTS_B5_R_4", - "PCIE_LOGIC_OUTS_B6_L_0", - "PCIE_LOGIC_OUTS_B6_L_1", - "PCIE_LOGIC_OUTS_B6_L_2", - "PCIE_LOGIC_OUTS_B6_L_3", - "PCIE_LOGIC_OUTS_B6_L_4", - "PCIE_LOGIC_OUTS_B6_R_0", - "PCIE_LOGIC_OUTS_B6_R_1", - "PCIE_LOGIC_OUTS_B6_R_2", - "PCIE_LOGIC_OUTS_B6_R_3", - "PCIE_LOGIC_OUTS_B6_R_4", - "PCIE_LOGIC_OUTS_B7_L_0", - "PCIE_LOGIC_OUTS_B7_L_1", - "PCIE_LOGIC_OUTS_B7_L_2", - "PCIE_LOGIC_OUTS_B7_L_3", - "PCIE_LOGIC_OUTS_B7_L_4", - "PCIE_LOGIC_OUTS_B7_R_0", - "PCIE_LOGIC_OUTS_B7_R_1", - "PCIE_LOGIC_OUTS_B7_R_2", - "PCIE_LOGIC_OUTS_B7_R_3", - "PCIE_LOGIC_OUTS_B7_R_4", - "PCIE_LOGIC_OUTS_B8_L_0", - "PCIE_LOGIC_OUTS_B8_L_1", - "PCIE_LOGIC_OUTS_B8_L_2", - "PCIE_LOGIC_OUTS_B8_L_3", - "PCIE_LOGIC_OUTS_B8_L_4", - "PCIE_LOGIC_OUTS_B8_R_0", - "PCIE_LOGIC_OUTS_B8_R_1", - "PCIE_LOGIC_OUTS_B8_R_2", - "PCIE_LOGIC_OUTS_B8_R_3", - "PCIE_LOGIC_OUTS_B8_R_4", - "PCIE_LOGIC_OUTS_B9_L_0", - "PCIE_LOGIC_OUTS_B9_L_1", - "PCIE_LOGIC_OUTS_B9_L_2", - "PCIE_LOGIC_OUTS_B9_L_3", - "PCIE_LOGIC_OUTS_B9_L_4", - "PCIE_LOGIC_OUTS_B9_R_0", - "PCIE_LOGIC_OUTS_B9_R_1", - "PCIE_LOGIC_OUTS_B9_R_2", - "PCIE_LOGIC_OUTS_B9_R_3", - "PCIE_LOGIC_OUTS_B9_R_4", - "PCIE_MONITOR_N_0", - "PCIE_MONITOR_N_1", - "PCIE_MONITOR_N_2", - "PCIE_MONITOR_N_3", - "PCIE_MONITOR_N_4", - "PCIE_MONITOR_P_0", - "PCIE_MONITOR_P_1", - "PCIE_MONITOR_P_2", - "PCIE_MONITOR_P_3", - "PCIE_MONITOR_P_4", - "PCIE_NE2A0_0", - "PCIE_NE2A0_1", - "PCIE_NE2A0_2", - "PCIE_NE2A0_3", - "PCIE_NE2A0_4", - "PCIE_NE2A1_0", - "PCIE_NE2A1_1", - "PCIE_NE2A1_2", - "PCIE_NE2A1_3", - "PCIE_NE2A1_4", - "PCIE_NE2A2_0", - "PCIE_NE2A2_1", - "PCIE_NE2A2_2", - "PCIE_NE2A2_3", - "PCIE_NE2A2_4", - "PCIE_NE2A3_0", - "PCIE_NE2A3_1", - "PCIE_NE2A3_2", - "PCIE_NE2A3_3", - "PCIE_NE2A3_4", - "PCIE_NE4BEG0_0", - "PCIE_NE4BEG0_1", - "PCIE_NE4BEG0_2", - "PCIE_NE4BEG0_3", - "PCIE_NE4BEG0_4", - "PCIE_NE4BEG1_0", - "PCIE_NE4BEG1_1", - "PCIE_NE4BEG1_2", - "PCIE_NE4BEG1_3", - "PCIE_NE4BEG1_4", - "PCIE_NE4BEG2_0", - "PCIE_NE4BEG2_1", - "PCIE_NE4BEG2_2", - "PCIE_NE4BEG2_3", - "PCIE_NE4BEG2_4", - "PCIE_NE4BEG3_0", - "PCIE_NE4BEG3_1", - "PCIE_NE4BEG3_2", - "PCIE_NE4BEG3_3", - "PCIE_NE4BEG3_4", - "PCIE_NE4C0_0", - "PCIE_NE4C0_1", - "PCIE_NE4C0_2", - "PCIE_NE4C0_3", - "PCIE_NE4C0_4", - "PCIE_NE4C1_0", - "PCIE_NE4C1_1", - "PCIE_NE4C1_2", - "PCIE_NE4C1_3", - "PCIE_NE4C1_4", - "PCIE_NE4C2_0", - "PCIE_NE4C2_1", - "PCIE_NE4C2_2", - "PCIE_NE4C2_3", - "PCIE_NE4C2_4", - "PCIE_NE4C3_0", - "PCIE_NE4C3_1", - "PCIE_NE4C3_2", - "PCIE_NE4C3_3", - "PCIE_NE4C3_4", - "PCIE_NW2A0_0", - "PCIE_NW2A0_1", - "PCIE_NW2A0_2", - "PCIE_NW2A0_3", - "PCIE_NW2A0_4", - "PCIE_NW2A1_0", - "PCIE_NW2A1_1", - "PCIE_NW2A1_2", - "PCIE_NW2A1_3", - "PCIE_NW2A1_4", - "PCIE_NW2A2_0", - "PCIE_NW2A2_1", - "PCIE_NW2A2_2", - "PCIE_NW2A2_3", - "PCIE_NW2A2_4", - "PCIE_NW2A3_0", - "PCIE_NW2A3_1", - "PCIE_NW2A3_2", - "PCIE_NW2A3_3", - "PCIE_NW2A3_4", - "PCIE_NW4A0_0", - "PCIE_NW4A0_1", - "PCIE_NW4A0_2", - "PCIE_NW4A0_3", - "PCIE_NW4A0_4", - "PCIE_NW4A1_0", - "PCIE_NW4A1_1", - "PCIE_NW4A1_2", - "PCIE_NW4A1_3", - "PCIE_NW4A1_4", - "PCIE_NW4A2_0", - "PCIE_NW4A2_1", - "PCIE_NW4A2_2", - "PCIE_NW4A2_3", - "PCIE_NW4A2_4", - "PCIE_NW4A3_0", - "PCIE_NW4A3_1", - "PCIE_NW4A3_2", - "PCIE_NW4A3_3", - "PCIE_NW4A3_4", - "PCIE_NW4END0_0", - "PCIE_NW4END0_1", - "PCIE_NW4END0_2", - "PCIE_NW4END0_3", - "PCIE_NW4END0_4", - "PCIE_NW4END1_0", - "PCIE_NW4END1_1", - "PCIE_NW4END1_2", - "PCIE_NW4END1_3", - "PCIE_NW4END1_4", - "PCIE_NW4END2_0", - "PCIE_NW4END2_1", - "PCIE_NW4END2_2", - "PCIE_NW4END2_3", - "PCIE_NW4END2_4", - "PCIE_NW4END3_0", - "PCIE_NW4END3_1", - "PCIE_NW4END3_2", - "PCIE_NW4END3_3", - "PCIE_NW4END3_4", - "PCIE_SE2A0_0", - "PCIE_SE2A0_1", - "PCIE_SE2A0_2", - "PCIE_SE2A0_3", - "PCIE_SE2A0_4", - "PCIE_SE2A1_0", - "PCIE_SE2A1_1", - "PCIE_SE2A1_2", - "PCIE_SE2A1_3", - "PCIE_SE2A1_4", - "PCIE_SE2A2_0", - "PCIE_SE2A2_1", - "PCIE_SE2A2_2", - "PCIE_SE2A2_3", - "PCIE_SE2A2_4", - "PCIE_SE2A3_0", - "PCIE_SE2A3_1", - "PCIE_SE2A3_2", - "PCIE_SE2A3_3", - "PCIE_SE2A3_4", - "PCIE_SE4BEG0_0", - "PCIE_SE4BEG0_1", - "PCIE_SE4BEG0_2", - "PCIE_SE4BEG0_3", - "PCIE_SE4BEG0_4", - "PCIE_SE4BEG1_0", - "PCIE_SE4BEG1_1", - "PCIE_SE4BEG1_2", - "PCIE_SE4BEG1_3", - "PCIE_SE4BEG1_4", - "PCIE_SE4BEG2_0", - "PCIE_SE4BEG2_1", - "PCIE_SE4BEG2_2", - "PCIE_SE4BEG2_3", - "PCIE_SE4BEG2_4", - "PCIE_SE4BEG3_0", - "PCIE_SE4BEG3_1", - "PCIE_SE4BEG3_2", - "PCIE_SE4BEG3_3", - "PCIE_SE4BEG3_4", - "PCIE_SE4C0_0", - "PCIE_SE4C0_1", - "PCIE_SE4C0_2", - "PCIE_SE4C0_3", - "PCIE_SE4C0_4", - "PCIE_SE4C1_0", - "PCIE_SE4C1_1", - "PCIE_SE4C1_2", - "PCIE_SE4C1_3", - "PCIE_SE4C1_4", - "PCIE_SE4C2_0", - "PCIE_SE4C2_1", - "PCIE_SE4C2_2", - "PCIE_SE4C2_3", - "PCIE_SE4C2_4", - "PCIE_SE4C3_0", - "PCIE_SE4C3_1", - "PCIE_SE4C3_2", - "PCIE_SE4C3_3", - "PCIE_SE4C3_4", - "PCIE_SW2A0_0", - "PCIE_SW2A0_1", - "PCIE_SW2A0_2", - "PCIE_SW2A0_3", - "PCIE_SW2A0_4", - "PCIE_SW2A1_0", - "PCIE_SW2A1_1", - "PCIE_SW2A1_2", - "PCIE_SW2A1_3", - "PCIE_SW2A1_4", - "PCIE_SW2A2_0", - "PCIE_SW2A2_1", - "PCIE_SW2A2_2", - "PCIE_SW2A2_3", - "PCIE_SW2A2_4", - "PCIE_SW2A3_0", - "PCIE_SW2A3_1", - "PCIE_SW2A3_2", - "PCIE_SW2A3_3", - "PCIE_SW2A3_4", - "PCIE_SW4A0_0", - "PCIE_SW4A0_1", - "PCIE_SW4A0_2", - "PCIE_SW4A0_3", - "PCIE_SW4A0_4", - "PCIE_SW4A1_0", - "PCIE_SW4A1_1", - "PCIE_SW4A1_2", - "PCIE_SW4A1_3", - "PCIE_SW4A1_4", - "PCIE_SW4A2_0", - "PCIE_SW4A2_1", - "PCIE_SW4A2_2", - "PCIE_SW4A2_3", - "PCIE_SW4A2_4", - "PCIE_SW4A3_0", - "PCIE_SW4A3_1", - "PCIE_SW4A3_2", - "PCIE_SW4A3_3", - "PCIE_SW4A3_4", - "PCIE_SW4END0_0", - "PCIE_SW4END0_1", - "PCIE_SW4END0_2", - "PCIE_SW4END0_3", - "PCIE_SW4END0_4", - "PCIE_SW4END1_0", - "PCIE_SW4END1_1", - "PCIE_SW4END1_2", - "PCIE_SW4END1_3", - "PCIE_SW4END1_4", - "PCIE_SW4END2_0", - "PCIE_SW4END2_1", - "PCIE_SW4END2_2", - "PCIE_SW4END2_3", - "PCIE_SW4END2_4", - "PCIE_SW4END3_0", - "PCIE_SW4END3_1", - "PCIE_SW4END3_2", - "PCIE_SW4END3_3", - "PCIE_SW4END3_4", - "PCIE_TOP_CFGAERROOTERRCORRERRRECEIVED", - "PCIE_TOP_CFGAERROOTERRFATALERRRECEIVED", - "PCIE_TOP_CFGAERROOTERRFATALERRREPORTINGEN", - "PCIE_TOP_CFGAERROOTERRNONFATALERRRECEIVED", - "PCIE_TOP_CFGAERROOTERRNONFATALERRREPORTINGEN", - "PCIE_TOP_CFGCOMMANDBUSMASTERENABLE", - "PCIE_TOP_CFGCOMMANDINTERRUPTDISABLE", - "PCIE_TOP_CFGCOMMANDIOENABLE", - "PCIE_TOP_CFGCOMMANDMEMENABLE", - "PCIE_TOP_CFGDEVCONTROL2ARIFORWARDEN", - "PCIE_TOP_CFGDEVCONTROL2ATOMICEGRESSBLOCK", - "PCIE_TOP_CFGDEVCONTROL2ATOMICREQUESTEREN", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTDIS", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL0", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL1", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL2", - "PCIE_TOP_CFGDEVCONTROL2CPLTIMEOUTVAL3", - "PCIE_TOP_CFGDEVCONTROL2IDOCPLEN", - "PCIE_TOP_CFGDEVCONTROL2IDOREQEN", - "PCIE_TOP_CFGDEVCONTROL2LTREN", - "PCIE_TOP_CFGDEVID0", - "PCIE_TOP_CFGDEVID1", - "PCIE_TOP_CFGDEVID10", - "PCIE_TOP_CFGDEVID11", - "PCIE_TOP_CFGDEVID12", - "PCIE_TOP_CFGDEVID13", - "PCIE_TOP_CFGDEVID14", - "PCIE_TOP_CFGDEVID15", - "PCIE_TOP_CFGDEVID2", - "PCIE_TOP_CFGDEVID3", - "PCIE_TOP_CFGDEVID4", - "PCIE_TOP_CFGDEVID5", - "PCIE_TOP_CFGDEVID6", - "PCIE_TOP_CFGDEVID7", - "PCIE_TOP_CFGDEVID8", - "PCIE_TOP_CFGDEVID9", - "PCIE_TOP_CFGDSN57", - "PCIE_TOP_CFGDSN58", - "PCIE_TOP_CFGDSN59", - "PCIE_TOP_CFGDSN60", - "PCIE_TOP_CFGDSN61", - "PCIE_TOP_CFGDSN62", - "PCIE_TOP_CFGDSN63", - "PCIE_TOP_CFGERRAERHEADERLOG0", - "PCIE_TOP_CFGERRAERHEADERLOG1", - "PCIE_TOP_CFGERRAERHEADERLOG10", - "PCIE_TOP_CFGERRAERHEADERLOG11", - "PCIE_TOP_CFGERRAERHEADERLOG2", - "PCIE_TOP_CFGERRAERHEADERLOG3", - "PCIE_TOP_CFGERRAERHEADERLOG4", - "PCIE_TOP_CFGERRAERHEADERLOG5", - "PCIE_TOP_CFGERRAERHEADERLOG6", - "PCIE_TOP_CFGERRAERHEADERLOG7", - "PCIE_TOP_CFGERRAERHEADERLOG8", - "PCIE_TOP_CFGERRAERHEADERLOG9", - "PCIE_TOP_CFGERRLOCKEDN", - "PCIE_TOP_CFGERRNORECOVERYN", - "PCIE_TOP_CFGERRTLPCPLHEADER26", - "PCIE_TOP_CFGERRTLPCPLHEADER27", - "PCIE_TOP_CFGERRTLPCPLHEADER28", - "PCIE_TOP_CFGERRTLPCPLHEADER29", - "PCIE_TOP_CFGERRTLPCPLHEADER30", - "PCIE_TOP_CFGERRTLPCPLHEADER31", - "PCIE_TOP_CFGERRTLPCPLHEADER32", - "PCIE_TOP_CFGERRTLPCPLHEADER33", - "PCIE_TOP_CFGERRTLPCPLHEADER34", - "PCIE_TOP_CFGERRTLPCPLHEADER35", - "PCIE_TOP_CFGERRTLPCPLHEADER36", - "PCIE_TOP_CFGERRTLPCPLHEADER37", - "PCIE_TOP_CFGERRTLPCPLHEADER38", - "PCIE_TOP_CFGERRTLPCPLHEADER39", - "PCIE_TOP_CFGERRTLPCPLHEADER40", - "PCIE_TOP_CFGERRTLPCPLHEADER41", - "PCIE_TOP_CFGERRTLPCPLHEADER42", - "PCIE_TOP_CFGERRTLPCPLHEADER43", - "PCIE_TOP_CFGERRTLPCPLHEADER44", - "PCIE_TOP_CFGERRTLPCPLHEADER45", - "PCIE_TOP_CFGERRTLPCPLHEADER46", - "PCIE_TOP_CFGERRTLPCPLHEADER47", - "PCIE_TOP_CFGINTERRUPTDI0", - "PCIE_TOP_CFGINTERRUPTN", - "PCIE_TOP_CFGLINKCONTROLASPMCONTROL1", - "PCIE_TOP_CFGLINKCONTROLAUTOBANDWIDTHINTEN", - "PCIE_TOP_CFGLINKCONTROLBANDWIDTHINTEN", - "PCIE_TOP_CFGLINKCONTROLCLOCKPMEN", - "PCIE_TOP_CFGLINKCONTROLCOMMONCLOCK", - "PCIE_TOP_CFGLINKCONTROLEXTENDEDSYNC", - "PCIE_TOP_CFGLINKCONTROLHWAUTOWIDTHDIS", - "PCIE_TOP_CFGLINKCONTROLLINKDISABLE", - "PCIE_TOP_CFGLINKCONTROLRCB", - "PCIE_TOP_CFGLINKCONTROLRETRAINLINK", - "PCIE_TOP_CFGMGMTDO16", - "PCIE_TOP_CFGMGMTDO17", - "PCIE_TOP_CFGMGMTDO18", - "PCIE_TOP_CFGMGMTDO19", - "PCIE_TOP_CFGMGMTDO20", - "PCIE_TOP_CFGMGMTDO21", - "PCIE_TOP_CFGMGMTDO22", - "PCIE_TOP_CFGMGMTDO23", - "PCIE_TOP_CFGMGMTDO24", - "PCIE_TOP_CFGMGMTDO25", - "PCIE_TOP_CFGMGMTDO26", - "PCIE_TOP_CFGMGMTDO27", - "PCIE_TOP_CFGMGMTDO28", - "PCIE_TOP_CFGMGMTDO29", - "PCIE_TOP_CFGMGMTDO30", - "PCIE_TOP_CFGPCIELINKSTATE1", - "PCIE_TOP_CFGPCIELINKSTATE2", - "PCIE_TOP_CFGPMCSRPMEEN", - "PCIE_TOP_CFGPMCSRPMESTATUS", - "PCIE_TOP_CFGPMCSRPOWERSTATE0", - "PCIE_TOP_CFGPMCSRPOWERSTATE1", - "PCIE_TOP_CFGPMRCVASREQL1N", - "PCIE_TOP_CFGPMRCVENTERL1N", - "PCIE_TOP_CFGPMRCVENTERL23N", - "PCIE_TOP_CFGPMRCVREQACKN", - "PCIE_TOP_CFGTRANSACTION", - "PCIE_TOP_CFGTRANSACTIONADDR0", - "PCIE_TOP_CFGTRANSACTIONADDR1", - "PCIE_TOP_CFGTRANSACTIONADDR2", - "PCIE_TOP_CFGTRANSACTIONADDR3", - "PCIE_TOP_CFGTRANSACTIONADDR4", - "PCIE_TOP_CFGTRANSACTIONADDR5", - "PCIE_TOP_CFGTRANSACTIONADDR6", - "PCIE_TOP_CFGTRANSACTIONTYPE", - "PCIE_TOP_CFGVCTCVCMAP0", - "PCIE_TOP_CFGVCTCVCMAP1", - "PCIE_TOP_CFGVCTCVCMAP2", - "PCIE_TOP_CFGVCTCVCMAP3", - "PCIE_TOP_CFGVCTCVCMAP4", - "PCIE_TOP_CFGVCTCVCMAP5", - "PCIE_TOP_CFGVCTCVCMAP6", - "PCIE_TOP_CFGVENDID0", - "PCIE_TOP_DBGMODE0", - "PCIE_TOP_DBGVECA0", - "PCIE_TOP_DBGVECA1", - "PCIE_TOP_DBGVECA10", - "PCIE_TOP_DBGVECA11", - "PCIE_TOP_DBGVECA12", - "PCIE_TOP_DBGVECA13", - "PCIE_TOP_DBGVECA14", - "PCIE_TOP_DBGVECA15", - "PCIE_TOP_DBGVECA16", - "PCIE_TOP_DBGVECA17", - "PCIE_TOP_DBGVECA18", - "PCIE_TOP_DBGVECA19", - "PCIE_TOP_DBGVECA2", - "PCIE_TOP_DBGVECA20", - "PCIE_TOP_DBGVECA21", - "PCIE_TOP_DBGVECA3", - "PCIE_TOP_DBGVECA4", - "PCIE_TOP_DBGVECA5", - "PCIE_TOP_DBGVECA6", - "PCIE_TOP_DBGVECA7", - "PCIE_TOP_DBGVECA8", - "PCIE_TOP_DBGVECA9", - "PCIE_TOP_DBGVECB10", - "PCIE_TOP_DRPADDR7", - "PCIE_TOP_DRPADDR8", - "PCIE_TOP_DRPDI0", - "PCIE_TOP_DRPDI1", - "PCIE_TOP_DRPDI10", - "PCIE_TOP_DRPDI11", - "PCIE_TOP_DRPDI12", - "PCIE_TOP_DRPDI13", - "PCIE_TOP_DRPDI14", - "PCIE_TOP_DRPDI15", - "PCIE_TOP_DRPDI2", - "PCIE_TOP_DRPDI3", - "PCIE_TOP_DRPDI4", - "PCIE_TOP_DRPDI5", - "PCIE_TOP_DRPDI6", - "PCIE_TOP_DRPDI7", - "PCIE_TOP_DRPDI8", - "PCIE_TOP_DRPDI9", - "PCIE_TOP_DRPDO0", - "PCIE_TOP_DRPDO1", - "PCIE_TOP_DRPDO11", - "PCIE_TOP_DRPDO12", - "PCIE_TOP_DRPDO13", - "PCIE_TOP_DRPDO14", - "PCIE_TOP_DRPDO15", - "PCIE_TOP_DRPDO2", - "PCIE_TOP_DRPDO3", - "PCIE_TOP_DRPDO4", - "PCIE_TOP_DRPDO5", - "PCIE_TOP_DRPDO6", - "PCIE_TOP_DRPRDY", - "PCIE_TOP_EDTBYPASS", - "PCIE_TOP_EDTCONFIGURATION", - "PCIE_TOP_EDTUPDATE", - "PCIE_TOP_LL2SENDASREQL1", - "PCIE_TOP_LL2SENDENTERL1", - "PCIE_TOP_LL2SENDENTERL23", - "PCIE_TOP_LL2SENDPMACK", - "PCIE_TOP_LL2SUSPENDNOW", - "PCIE_TOP_LL2TFCINIT1SEQ", - "PCIE_TOP_LL2TFCINIT2SEQ", - "PCIE_TOP_LL2TLPRCV", - "PCIE_TOP_MIMRXRADDR0", - "PCIE_TOP_MIMRXRADDR1", - "PCIE_TOP_MIMRXRADDR10", - "PCIE_TOP_MIMRXRADDR11", - "PCIE_TOP_MIMRXRADDR2", - "PCIE_TOP_MIMRXRADDR4", - "PCIE_TOP_MIMRXRADDR8", - "PCIE_TOP_MIMRXRADDR9", - "PCIE_TOP_MIMRXRDATA20", - "PCIE_TOP_MIMRXRDATA21", - "PCIE_TOP_MIMRXRDATA22", - "PCIE_TOP_MIMRXRDATA23", - "PCIE_TOP_MIMRXRDATA24", - "PCIE_TOP_MIMRXRDATA25", - "PCIE_TOP_MIMRXRDATA26", - "PCIE_TOP_MIMRXRDATA27", - "PCIE_TOP_MIMRXRDATA28", - "PCIE_TOP_MIMRXRDATA29", - "PCIE_TOP_MIMRXRDATA30", - "PCIE_TOP_MIMRXRDATA31", - "PCIE_TOP_MIMRXRDATA32", - "PCIE_TOP_MIMRXRDATA33", - "PCIE_TOP_MIMRXRDATA34", - "PCIE_TOP_MIMRXRDATA35", - "PCIE_TOP_MIMRXRDATA36", - "PCIE_TOP_MIMRXRDATA37", - "PCIE_TOP_MIMRXRDATA38", - "PCIE_TOP_MIMRXRDATA39", - "PCIE_TOP_MIMRXRDATA40", - "PCIE_TOP_MIMRXRDATA41", - "PCIE_TOP_MIMRXRDATA42", - "PCIE_TOP_MIMRXRDATA43", - "PCIE_TOP_MIMRXRDATA44", - "PCIE_TOP_MIMRXRDATA45", - "PCIE_TOP_MIMRXRDATA46", - "PCIE_TOP_MIMRXRDATA47", - "PCIE_TOP_MIMRXRDATA48", - "PCIE_TOP_MIMRXRDATA49", - "PCIE_TOP_MIMRXRDATA50", - "PCIE_TOP_MIMRXRDATA51", - "PCIE_TOP_MIMRXRDATA52", - "PCIE_TOP_MIMRXRDATA53", - "PCIE_TOP_MIMRXRDATA54", - "PCIE_TOP_MIMRXRDATA55", - "PCIE_TOP_MIMRXREN", - "PCIE_TOP_MIMRXWADDR1", - "PCIE_TOP_MIMRXWADDR12", - "PCIE_TOP_MIMRXWADDR2", - "PCIE_TOP_MIMRXWADDR5", - "PCIE_TOP_MIMRXWDATA0", - "PCIE_TOP_MIMRXWDATA1", - "PCIE_TOP_MIMRXWDATA10", - "PCIE_TOP_MIMRXWDATA11", - "PCIE_TOP_MIMRXWDATA12", - "PCIE_TOP_MIMRXWDATA13", - "PCIE_TOP_MIMRXWDATA15", - "PCIE_TOP_MIMRXWDATA17", - "PCIE_TOP_MIMRXWDATA19", - "PCIE_TOP_MIMRXWDATA2", - "PCIE_TOP_MIMRXWDATA20", - "PCIE_TOP_MIMRXWDATA21", - "PCIE_TOP_MIMRXWDATA22", - "PCIE_TOP_MIMRXWDATA23", - "PCIE_TOP_MIMRXWDATA24", - "PCIE_TOP_MIMRXWDATA25", - "PCIE_TOP_MIMRXWDATA26", - "PCIE_TOP_MIMRXWDATA27", - "PCIE_TOP_MIMRXWDATA28", - "PCIE_TOP_MIMRXWDATA29", - "PCIE_TOP_MIMRXWDATA3", - "PCIE_TOP_MIMRXWDATA30", - "PCIE_TOP_MIMRXWDATA31", - "PCIE_TOP_MIMRXWDATA32", - "PCIE_TOP_MIMRXWDATA33", - "PCIE_TOP_MIMRXWDATA34", - "PCIE_TOP_MIMRXWDATA35", - "PCIE_TOP_MIMRXWDATA4", - "PCIE_TOP_MIMRXWDATA49", - "PCIE_TOP_MIMRXWDATA5", - "PCIE_TOP_MIMRXWDATA51", - "PCIE_TOP_MIMRXWDATA6", - "PCIE_TOP_MIMRXWDATA7", - "PCIE_TOP_MIMRXWDATA8", - "PCIE_TOP_MIMRXWDATA9", - "PCIE_TOP_MIMRXWEN", - "PCIE_TOP_PIPERX0CHANISALIGNED", - "PCIE_TOP_PIPERX0CHARISK0", - "PCIE_TOP_PIPERX0DATA0", - "PCIE_TOP_PIPERX0DATA1", - "PCIE_TOP_PIPERX0DATA2", - "PCIE_TOP_PIPERX0DATA3", - "PCIE_TOP_PIPERX0DATA4", - "PCIE_TOP_PIPERX0DATA5", - "PCIE_TOP_PIPERX0DATA6", - "PCIE_TOP_PIPERX0DATA7", - "PCIE_TOP_PIPERX0PHYSTATUS", - "PCIE_TOP_PIPERX0VALID", - "PCIE_TOP_PIPERX4CHANISALIGNED", - "PCIE_TOP_PIPERX4CHARISK0", - "PCIE_TOP_PIPERX4DATA0", - "PCIE_TOP_PIPERX4DATA1", - "PCIE_TOP_PIPERX4DATA2", - "PCIE_TOP_PIPERX4DATA3", - "PCIE_TOP_PIPERX4DATA4", - "PCIE_TOP_PIPERX4DATA5", - "PCIE_TOP_PIPERX4DATA6", - "PCIE_TOP_PIPERX4DATA7", - "PCIE_TOP_PIPERX4PHYSTATUS", - "PCIE_TOP_PIPERX4VALID", - "PCIE_TOP_PIPETXMARGIN0", - "PCIE_TOP_PIPETXMARGIN1", - "PCIE_TOP_PIPETXMARGIN2", - "PCIE_TOP_PL2DIRECTEDLSTATE0", - "PCIE_TOP_PL2DIRECTEDLSTATE1", - "PCIE_TOP_PL2DIRECTEDLSTATE2", - "PCIE_TOP_PL2DIRECTEDLSTATE3", - "PCIE_TOP_PL2DIRECTEDLSTATE4", - "PCIE_TOP_PL2RECOVERY", - "PCIE_TOP_PL2SUSPENDOK", - "PCIE_TOP_PLDBGVEC8", - "PCIE_TOP_SCANENABLEN", - "PCIE_TOP_SCANMODEN", - "PCIE_TOP_TL2ASPMSUSPENDCREDITCHECK", - "PCIE_TOP_TL2PPMSUSPENDREQ", - "PCIE_TOP_TRNRD59", - "PCIE_TOP_TRNRD60", - "PCIE_TOP_TRNRD61", - "PCIE_TOP_TRNRD62", - "PCIE_TOP_TRNRD63", - "PCIE_TOP_TRNRD64", - "PCIE_TOP_TRNRD65", - "PCIE_TOP_TRNRD66", - "PCIE_TOP_TRNRD67", - "PCIE_TOP_TRNRD68", - "PCIE_TOP_TRNRD69", - "PCIE_TOP_TRNRD70", - "PCIE_TOP_TRNRD71", - "PCIE_TOP_TRNRD72", - "PCIE_TOP_TRNRD73", - "PCIE_TOP_TRNRD74", - "PCIE_TOP_TRNRD75", - "PCIE_TOP_TRNRD76", - "PCIE_TOP_TRNRD77", - "PCIE_TOP_TRNRD78", - "PCIE_TOP_TRNRD79", - "PCIE_TOP_TRNRD80", - "PCIE_TOP_TRNRD81", - "PCIE_TOP_TRNRD82", - "PCIE_TOP_TRNRD83", - "PCIE_TOP_TRNRD84", - "PCIE_TOP_TRNRD85", - "PCIE_TOP_TRNRD86", - "PCIE_TOP_TRNRD87", - "PCIE_TOP_TRNRD88", - "PCIE_TOP_TRNRD89", - "PCIE_TOP_TRNRD90", - "PCIE_TOP_TRNRD91", - "PCIE_TOP_TRNRD92", - "PCIE_TOP_TRNRD93", - "PCIE_TOP_TRNRD94", - "PCIE_TOP_TRNRD95", - "PCIE_TOP_TRNRD96", - "PCIE_TOP_TRNRD97", - "PCIE_TOP_TRNRD98", - "PCIE_TOP_TRNRDLLPDATA32", - "PCIE_TOP_TRNRDLLPDATA33", - "PCIE_TOP_TRNRDLLPDATA34", - "PCIE_TOP_TRNRDLLPDATA35", - "PCIE_TOP_TRNRDLLPDATA36", - "PCIE_TOP_TRNRDLLPDATA37", - "PCIE_TOP_TRNRDLLPDATA38", - "PCIE_TOP_TRNRDLLPDATA39", - "PCIE_TOP_TRNRDLLPDATA40", - "PCIE_TOP_TRNRDLLPDATA41", - "PCIE_TOP_TRNRDLLPDATA42", - "PCIE_TOP_TRNRDLLPDATA43", - "PCIE_TOP_TRNRDLLPDATA44", - "PCIE_TOP_TRNRDLLPDATA45", - "PCIE_TOP_TRNRDLLPDATA46", - "PCIE_TOP_TRNRDLLPDATA47", - "PCIE_TOP_TRNRDLLPDATA48", - "PCIE_TOP_TRNRDLLPDATA49", - "PCIE_TOP_TRNRDLLPDATA50", - "PCIE_TOP_TRNRDLLPDATA51", - "PCIE_TOP_TRNRDLLPDATA52", - "PCIE_TOP_TRNRDLLPDATA53", - "PCIE_TOP_TRNRDLLPDATA54", - "PCIE_TOP_TRNRDLLPDATA55", - "PCIE_TOP_TRNRDLLPDATA56", - "PCIE_TOP_TRNRDLLPDATA57", - "PCIE_TOP_TRNRDLLPDATA58", - "PCIE_TOP_TRNRDLLPDATA59", - "PCIE_TOP_TRNRDLLPDATA60", - "PCIE_TOP_TRNRDLLPDATA61", - "PCIE_TOP_TRNRDLLPDATA62", - "PCIE_TOP_TRNRDLLPDATA63", - "PCIE_TOP_TRNRDLLPSRCRDY0", - "PCIE_TOP_TRNRDLLPSRCRDY1", - "PCIE_TOP_TRNTD10", - "PCIE_TOP_TRNTD11", - "PCIE_TOP_TRNTD12", - "PCIE_TOP_TRNTD13", - "PCIE_TOP_TRNTD14", - "PCIE_TOP_TRNTD15", - "PCIE_TOP_TRNTD16", - "PCIE_TOP_TRNTD17", - "PCIE_TOP_TRNTD18", - "PCIE_TOP_TRNTD19", - "PCIE_TOP_TRNTD20", - "PCIE_TOP_TRNTD21", - "PCIE_TOP_TRNTD22", - "PCIE_TOP_TRNTD23", - "PCIE_TOP_TRNTD24", - "PCIE_TOP_TRNTD25", - "PCIE_TOP_TRNTD26", - "PCIE_TOP_TRNTD27", - "PCIE_TOP_TRNTD28", - "PCIE_TOP_TRNTD29", - "PCIE_TOP_TRNTD30", - "PCIE_TOP_TRNTD31", - "PCIE_TOP_TRNTD32", - "PCIE_TOP_TRNTD33", - "PCIE_TOP_TRNTD34", - "PCIE_TOP_TRNTD35", - "PCIE_TOP_TRNTD36", - "PCIE_TOP_TRNTD37", - "PCIE_TOP_TRNTD38", - "PCIE_TOP_TRNTD39", - "PCIE_TOP_TRNTD40", - "PCIE_TOP_TRNTD41", - "PCIE_TOP_TRNTD8", - "PCIE_TOP_TRNTD9", - "PCIE_TOP_TRNTDLLPDATA19", - "PCIE_TOP_TRNTDLLPDATA20", - "PCIE_TOP_TRNTDLLPDATA21", - "PCIE_TOP_TRNTDLLPDATA22", - "PCIE_TOP_TRNTDLLPDATA23", - "PCIE_TOP_TRNTDLLPDATA24", - "PCIE_TOP_TRNTDLLPDATA25", - "PCIE_TOP_TRNTDLLPDATA26", - "PCIE_TOP_TRNTDLLPDATA27", - "PCIE_TOP_TRNTDLLPDATA28", - "PCIE_TOP_TRNTDLLPDATA29", - "PCIE_TOP_TRNTDLLPDATA30", - "PCIE_TOP_TRNTDLLPDATA31", - "PCIE_TOP_TRNTDLLPSRCRDY", - "PCIE_TOP_TRNTDSTRDY3", - "PCIE_TOP_XILUNCONNOUT28", - "PCIE_WL1END0_0", - "PCIE_WL1END0_1", - "PCIE_WL1END0_2", - "PCIE_WL1END0_3", - "PCIE_WL1END0_4", - "PCIE_WL1END1_0", - "PCIE_WL1END1_1", - "PCIE_WL1END1_2", - "PCIE_WL1END1_3", - "PCIE_WL1END1_4", - "PCIE_WL1END2_0", - "PCIE_WL1END2_1", - "PCIE_WL1END2_2", - "PCIE_WL1END2_3", - "PCIE_WL1END2_4", - "PCIE_WL1END3_0", - "PCIE_WL1END3_1", - "PCIE_WL1END3_2", - "PCIE_WL1END3_3", - "PCIE_WL1END3_4", - "PCIE_WR1END0_0", - "PCIE_WR1END0_1", - "PCIE_WR1END0_2", - "PCIE_WR1END0_3", - "PCIE_WR1END0_4", - "PCIE_WR1END1_0", - "PCIE_WR1END1_1", - "PCIE_WR1END1_2", - "PCIE_WR1END1_3", - "PCIE_WR1END1_4", - "PCIE_WR1END2_0", - "PCIE_WR1END2_1", - "PCIE_WR1END2_2", - "PCIE_WR1END2_3", - "PCIE_WR1END2_4", - "PCIE_WR1END3_0", - "PCIE_WR1END3_1", - "PCIE_WR1END3_2", - "PCIE_WR1END3_3", - "PCIE_WR1END3_4", - "PCIE_WW2A0_0", - "PCIE_WW2A0_1", - "PCIE_WW2A0_2", - "PCIE_WW2A0_3", - "PCIE_WW2A0_4", - "PCIE_WW2A1_0", - "PCIE_WW2A1_1", - "PCIE_WW2A1_2", - "PCIE_WW2A1_3", - "PCIE_WW2A1_4", - "PCIE_WW2A2_0", - "PCIE_WW2A2_1", - "PCIE_WW2A2_2", - "PCIE_WW2A2_3", - "PCIE_WW2A2_4", - "PCIE_WW2A3_0", - "PCIE_WW2A3_1", - "PCIE_WW2A3_2", - "PCIE_WW2A3_3", - "PCIE_WW2A3_4", - "PCIE_WW2END0_0", - "PCIE_WW2END0_1", - "PCIE_WW2END0_2", - "PCIE_WW2END0_3", - "PCIE_WW2END0_4", - "PCIE_WW2END1_0", - "PCIE_WW2END1_1", - "PCIE_WW2END1_2", - "PCIE_WW2END1_3", - "PCIE_WW2END1_4", - "PCIE_WW2END2_0", - "PCIE_WW2END2_1", - "PCIE_WW2END2_2", - "PCIE_WW2END2_3", - "PCIE_WW2END2_4", - "PCIE_WW2END3_0", - "PCIE_WW2END3_1", - "PCIE_WW2END3_2", - "PCIE_WW2END3_3", - "PCIE_WW2END3_4", - "PCIE_WW4A0_0", - "PCIE_WW4A0_1", - "PCIE_WW4A0_2", - "PCIE_WW4A0_3", - "PCIE_WW4A0_4", - "PCIE_WW4A1_0", - "PCIE_WW4A1_1", - "PCIE_WW4A1_2", - "PCIE_WW4A1_3", - "PCIE_WW4A1_4", - "PCIE_WW4A2_0", - "PCIE_WW4A2_1", - "PCIE_WW4A2_2", - "PCIE_WW4A2_3", - "PCIE_WW4A2_4", - "PCIE_WW4A3_0", - "PCIE_WW4A3_1", - "PCIE_WW4A3_2", - "PCIE_WW4A3_3", - "PCIE_WW4A3_4", - "PCIE_WW4B0_0", - "PCIE_WW4B0_1", - "PCIE_WW4B0_2", - "PCIE_WW4B0_3", - "PCIE_WW4B0_4", - "PCIE_WW4B1_0", - "PCIE_WW4B1_1", - "PCIE_WW4B1_2", - "PCIE_WW4B1_3", - "PCIE_WW4B1_4", - "PCIE_WW4B2_0", - "PCIE_WW4B2_1", - "PCIE_WW4B2_2", - "PCIE_WW4B2_3", - "PCIE_WW4B2_4", - "PCIE_WW4B3_0", - "PCIE_WW4B3_1", - "PCIE_WW4B3_2", - "PCIE_WW4B3_3", - "PCIE_WW4B3_4", - "PCIE_WW4C0_0", - "PCIE_WW4C0_1", - "PCIE_WW4C0_2", - "PCIE_WW4C0_3", - "PCIE_WW4C0_4", - "PCIE_WW4C1_0", - "PCIE_WW4C1_1", - "PCIE_WW4C1_2", - "PCIE_WW4C1_3", - "PCIE_WW4C1_4", - "PCIE_WW4C2_0", - "PCIE_WW4C2_1", - "PCIE_WW4C2_2", - "PCIE_WW4C2_3", - "PCIE_WW4C2_4", - "PCIE_WW4C3_0", - "PCIE_WW4C3_1", - "PCIE_WW4C3_2", - "PCIE_WW4C3_3", - "PCIE_WW4C3_4", - "PCIE_WW4END0_0", - "PCIE_WW4END0_1", - "PCIE_WW4END0_2", - "PCIE_WW4END0_3", - "PCIE_WW4END0_4", - "PCIE_WW4END1_0", - "PCIE_WW4END1_1", - "PCIE_WW4END1_2", - "PCIE_WW4END1_3", - "PCIE_WW4END1_4", - "PCIE_WW4END2_0", - "PCIE_WW4END2_1", - "PCIE_WW4END2_2", - "PCIE_WW4END2_3", - "PCIE_WW4END2_4", - "PCIE_WW4END3_0", - "PCIE_WW4END3_1", - "PCIE_WW4END3_2", - "PCIE_WW4END3_3", - "PCIE_WW4END3_4" - ] + "wires": { + "PCIE_BLOCK_OUTS_B0_L_0": null, + "PCIE_BLOCK_OUTS_B0_L_1": null, + "PCIE_BLOCK_OUTS_B0_L_2": null, + "PCIE_BLOCK_OUTS_B0_L_3": null, + "PCIE_BLOCK_OUTS_B0_L_4": null, + "PCIE_BLOCK_OUTS_B0_R_0": null, + "PCIE_BLOCK_OUTS_B0_R_1": null, + "PCIE_BLOCK_OUTS_B0_R_2": null, + "PCIE_BLOCK_OUTS_B0_R_3": null, + "PCIE_BLOCK_OUTS_B0_R_4": null, + "PCIE_BLOCK_OUTS_B1_L_0": null, + "PCIE_BLOCK_OUTS_B1_L_1": null, + "PCIE_BLOCK_OUTS_B1_L_2": null, + "PCIE_BLOCK_OUTS_B1_L_3": null, + "PCIE_BLOCK_OUTS_B1_L_4": null, + "PCIE_BLOCK_OUTS_B1_R_0": null, + "PCIE_BLOCK_OUTS_B1_R_1": null, + "PCIE_BLOCK_OUTS_B1_R_2": null, + "PCIE_BLOCK_OUTS_B1_R_3": null, + "PCIE_BLOCK_OUTS_B1_R_4": null, + "PCIE_BLOCK_OUTS_B2_L_0": null, + "PCIE_BLOCK_OUTS_B2_L_1": null, + "PCIE_BLOCK_OUTS_B2_L_2": null, + "PCIE_BLOCK_OUTS_B2_L_3": null, + "PCIE_BLOCK_OUTS_B2_L_4": null, + "PCIE_BLOCK_OUTS_B2_R_0": null, + "PCIE_BLOCK_OUTS_B2_R_1": null, + "PCIE_BLOCK_OUTS_B2_R_2": null, + "PCIE_BLOCK_OUTS_B2_R_3": null, + "PCIE_BLOCK_OUTS_B2_R_4": null, + "PCIE_BLOCK_OUTS_B3_L_0": null, + "PCIE_BLOCK_OUTS_B3_L_1": null, + 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"PCIE_WR1END3_2": { + "cap": "105.000", + "res": "487.600" + }, + "PCIE_WR1END3_3": { + "cap": "105.000", + "res": "487.600" + }, + "PCIE_WR1END3_4": { + "cap": "105.000", + "res": "487.600" + }, + "PCIE_WW2A0_0": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A0_1": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A0_2": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A0_3": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A0_4": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A1_0": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A1_1": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A1_2": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A1_3": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A1_4": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A2_0": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A2_1": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2A2_2": { + "cap": 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"487.600" + }, + "PCIE_WW2END1_3": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END1_4": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END2_0": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END2_1": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END2_2": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END2_3": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END2_4": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END3_0": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END3_1": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END3_2": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END3_3": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW2END3_4": { + "cap": "103.000", + "res": "487.600" + }, + "PCIE_WW4A0_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A0_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A0_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A0_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A0_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A1_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A1_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A1_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A1_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A1_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A2_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A2_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A2_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A2_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A2_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A3_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A3_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A3_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A3_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4A3_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B0_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B0_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B0_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B0_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B0_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B1_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B1_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B1_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B1_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B1_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B2_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B2_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B2_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B2_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B2_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B3_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B3_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B3_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B3_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4B3_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C0_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C0_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C0_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C0_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C0_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C1_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C1_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C1_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C1_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C1_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C2_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C2_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C2_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C2_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C2_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C3_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C3_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C3_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C3_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4C3_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END0_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END0_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END0_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END0_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END0_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END1_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END1_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END1_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END1_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END1_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END2_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END2_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END2_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END2_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END2_4": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END3_0": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END3_1": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END3_2": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END3_3": { + "cap": "104.000", + "res": "487.600" + }, + "PCIE_WW4END3_4": { + "cap": "104.000", + "res": "487.600" + } + } } diff --git a/kintex7/tile_type_RIOB18.json b/kintex7/tile_type_RIOB18.json index 8445037..2b742cf 100644 --- a/kintex7/tile_type_RIOB18.json +++ b/kintex7/tile_type_RIOB18.json @@ -2,72 +2,212 @@ "pips": { "RIOB18.IOB_DIFFO_IN1->>IOB_PADOUT1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOB_PADOUT1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOB_DIFFO_IN1" }, "RIOB18.IOB_DIFFO_OUT0->IOB_DIFFO_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_DIFFO_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_DIFFO_OUT0" }, "RIOB18.IOB_O0->>IOB_O_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOB_O_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOB_O0" }, "RIOB18.IOB_O_OUT0->IOB_O_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_O_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_O_OUT0" }, "RIOB18.IOB_PADOUT0->IOB_DIFFI_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_DIFFI_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT0" }, "RIOB18.IOB_PADOUT0->RIOB_MONITOR_P": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOB_MONITOR_P", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT0" }, "RIOB18.IOB_PADOUT1->IOB_DIFFI_IN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_DIFFI_IN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT1" }, "RIOB18.IOB_PADOUT1->RIOB_MONITOR_N": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOB_MONITOR_N", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_PADOUT1" }, "RIOB18.IOB_T0->>IOB_T_OUT0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOB_T_OUT0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOB_T0" }, "RIOB18.IOB_T_OUT0->IOB_T_IN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOB_T_IN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOB_T_OUT0" } }, @@ -76,23 +216,176 @@ "name": "X0Y0", "prefix": "IOB", "site_pins": { - "DCITERMDISABLE": "IOB_DCI_T_TERM1", - "DIFFI_IN": "IOB_DIFFI_IN1", - "DIFFO_IN": "IOB_DIFFO_IN1", - "DIFFO_OUT": "IOB_DIFFO_OUT1", - "DIFF_TERM_INT_EN": "IOB_DIFF_TERM_INT_EN", - "I": "IOB_IBUF1", - "IBUFDISABLE": "IOB_IBUF_DISABLE1", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_0", - "O": "IOB_O1", - "O_IN": "IOB_O_IN1", - "O_OUT": "IOB_O_OUT1", - "PADOUT": "IOB_PADOUT1", - "PD_INT_EN": "IOB_PD_INT_EN_0", - "PU_INT_EN": "IOB_PU_INT_EN_0", - "T": "IOB_T1", - "T_IN": "IOB_T_IN1", - "T_OUT": "IOB_T_OUT1" + "DCITERMDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DCI_T_TERM1" + }, + "DIFFI_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFFI_IN1" + }, + "DIFFO_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFFO_IN1" + }, + "DIFFO_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_DIFFO_OUT1" + }, + "DIFF_TERM_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFF_TERM_INT_EN" + }, + "I": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_IBUF1" + }, + "IBUFDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_IBUF_DISABLE1" + }, + "KEEPER_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_KEEPER_INT_EN_0" + }, + "O": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_O1" + }, + "O_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_O_IN1" + }, + "O_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_O_OUT1" + }, + "PADOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_PADOUT1" + }, + "PD_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PD_INT_EN_0" + }, + "PU_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PU_INT_EN_0" + }, + "T": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_T1" + }, + "T_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_T_IN1" + }, + "T_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_T_OUT1" + } }, "type": "IOB18S", "x_coord": 0, @@ -102,23 +395,140 @@ "name": "X0Y1", "prefix": "IOB", "site_pins": { - "DCITERMDISABLE": "IOB_DCI_T_TERM0", - "DIFFI_IN": "IOB_DIFFI_IN0", + "DCITERMDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DCI_T_TERM0" + }, + "DIFFI_IN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DIFFI_IN0" + }, "DIFFO_IN": null, - "DIFFO_OUT": "IOB_DIFFO_OUT0", + "DIFFO_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_DIFFO_OUT0" + }, "DIFF_TERM_INT_EN": null, - "I": "IOB_IBUF0", - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "O": "IOB_O0", + "I": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_IBUF0" + }, + "IBUFDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_IBUF_DISABLE0" + }, + "KEEPER_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_KEEPER_INT_EN_1" + }, + "O": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_O0" + }, "O_IN": null, - "O_OUT": "IOB_O_OUT0", - "PADOUT": "IOB_PADOUT0", - "PD_INT_EN": "IOB_PD_INT_EN_1", - "PU_INT_EN": "IOB_PU_INT_EN_1", - "T": "IOB_T0", + "O_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_O_OUT0" + }, + "PADOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_PADOUT0" + }, + "PD_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PD_INT_EN_1" + }, + "PU_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PU_INT_EN_1" + }, + "T": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_T0" + }, "T_IN": null, - "T_OUT": "IOB_T_OUT0" + "T_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_T_OUT0" + } }, "type": "IOB18M", "x_coord": 0, @@ -126,290 +536,1034 @@ } ], "tile_type": "RIOB18", - "wires": [ - "IOB_DCI_T_TERM0", - "IOB_DCI_T_TERM1", - "IOB_DIFFI_IN0", - "IOB_DIFFI_IN1", - "IOB_DIFFO_IN0", - "IOB_DIFFO_IN1", - "IOB_DIFFO_OUT0", - "IOB_DIFFO_OUT1", - "IOB_DIFF_TERM_INT_EN", - "IOB_DIFF_TERM_INT_EN_STUB", - "IOB_IBUF0", - "IOB_IBUF1", - "IOB_IBUF_DISABLE0", - "IOB_IBUF_DISABLE1", - "IOB_KEEPER_INT_EN_0", - "IOB_KEEPER_INT_EN_1", - "IOB_O0", - "IOB_O1", - "IOB_O_IN0", - "IOB_O_IN1", - "IOB_O_OUT0", - "IOB_O_OUT1", - "IOB_PADOUT0", - "IOB_PADOUT1", - "IOB_PD_INT_EN_0", - "IOB_PD_INT_EN_1", - "IOB_PU_INT_EN_0", - "IOB_PU_INT_EN_1", - "IOB_T0", - "IOB_T1", - "IOB_T_IN0", - "IOB_T_IN1", - "IOB_T_OUT0", - "IOB_T_OUT1", - "RIOB_EE2A0_0", - "RIOB_EE2A0_1", - "RIOB_EE2A1_0", - "RIOB_EE2A1_1", - "RIOB_EE2A2_0", - "RIOB_EE2A2_1", - "RIOB_EE2A3_0", - "RIOB_EE2A3_1", - "RIOB_EE2BEG0_0", - "RIOB_EE2BEG0_1", - "RIOB_EE2BEG1_0", - "RIOB_EE2BEG1_1", - "RIOB_EE2BEG2_0", - "RIOB_EE2BEG2_1", - "RIOB_EE2BEG3_0", - "RIOB_EE2BEG3_1", - "RIOB_EE4A0_0", - "RIOB_EE4A0_1", - "RIOB_EE4A1_0", - "RIOB_EE4A1_1", - "RIOB_EE4A2_0", - "RIOB_EE4A2_1", - "RIOB_EE4A3_0", - "RIOB_EE4A3_1", - "RIOB_EE4B0_0", - "RIOB_EE4B0_1", - "RIOB_EE4B1_0", - "RIOB_EE4B1_1", - "RIOB_EE4B2_0", - "RIOB_EE4B2_1", - "RIOB_EE4B3_0", - "RIOB_EE4B3_1", - "RIOB_EE4BEG0_0", - "RIOB_EE4BEG0_1", - "RIOB_EE4BEG1_0", - "RIOB_EE4BEG1_1", - "RIOB_EE4BEG2_0", - "RIOB_EE4BEG2_1", - "RIOB_EE4BEG3_0", - "RIOB_EE4BEG3_1", - "RIOB_EE4C0_0", - "RIOB_EE4C0_1", - "RIOB_EE4C1_0", - "RIOB_EE4C1_1", - "RIOB_EE4C2_0", - "RIOB_EE4C2_1", - "RIOB_EE4C3_0", - "RIOB_EE4C3_1", - "RIOB_EL1BEG0_0", - "RIOB_EL1BEG0_1", - "RIOB_EL1BEG1_0", - "RIOB_EL1BEG1_1", - "RIOB_EL1BEG2_0", - "RIOB_EL1BEG2_1", - "RIOB_EL1BEG3_0", - "RIOB_EL1BEG3_1", - "RIOB_ER1BEG0_0", - "RIOB_ER1BEG0_1", - "RIOB_ER1BEG1_0", - "RIOB_ER1BEG1_1", - "RIOB_ER1BEG2_0", - "RIOB_ER1BEG2_1", - "RIOB_ER1BEG3_0", - "RIOB_ER1BEG3_1", - "RIOB_LH10_0", - "RIOB_LH10_1", - "RIOB_LH11_0", - "RIOB_LH11_1", - "RIOB_LH12_0", - "RIOB_LH12_1", - "RIOB_LH1_0", - "RIOB_LH1_1", - "RIOB_LH2_0", - "RIOB_LH2_1", - "RIOB_LH3_0", - "RIOB_LH3_1", - "RIOB_LH4_0", - "RIOB_LH4_1", - "RIOB_LH5_0", - "RIOB_LH5_1", - "RIOB_LH6_0", - "RIOB_LH6_1", - "RIOB_LH7_0", - "RIOB_LH7_1", - "RIOB_LH8_0", - "RIOB_LH8_1", - "RIOB_LH9_0", - "RIOB_LH9_1", - "RIOB_MONITOR_N", - "RIOB_MONITOR_P", - "RIOB_NE2A0_0", - "RIOB_NE2A0_1", - "RIOB_NE2A1_0", - "RIOB_NE2A1_1", - "RIOB_NE2A2_0", - "RIOB_NE2A2_1", - "RIOB_NE2A3_0", - "RIOB_NE2A3_1", - "RIOB_NE4BEG0_0", - "RIOB_NE4BEG0_1", - "RIOB_NE4BEG1_0", - "RIOB_NE4BEG1_1", - "RIOB_NE4BEG2_0", - "RIOB_NE4BEG2_1", - "RIOB_NE4BEG3_0", - "RIOB_NE4BEG3_1", - "RIOB_NE4C0_0", - "RIOB_NE4C0_1", - "RIOB_NE4C1_0", - "RIOB_NE4C1_1", - "RIOB_NE4C2_0", - "RIOB_NE4C2_1", - "RIOB_NE4C3_0", - "RIOB_NE4C3_1", - "RIOB_NW2A0_0", - "RIOB_NW2A0_1", - "RIOB_NW2A1_0", - "RIOB_NW2A1_1", - "RIOB_NW2A2_0", - "RIOB_NW2A2_1", - "RIOB_NW2A3_0", - "RIOB_NW2A3_1", - "RIOB_NW4A0_0", - "RIOB_NW4A0_1", - "RIOB_NW4A1_0", - "RIOB_NW4A1_1", - "RIOB_NW4A2_0", - "RIOB_NW4A2_1", - "RIOB_NW4A3_0", - "RIOB_NW4A3_1", - "RIOB_NW4END0_0", - "RIOB_NW4END0_1", - "RIOB_NW4END1_0", - "RIOB_NW4END1_1", - "RIOB_NW4END2_0", - "RIOB_NW4END2_1", - "RIOB_NW4END3_0", - "RIOB_NW4END3_1", - "RIOB_SE2A0_0", - "RIOB_SE2A0_1", - "RIOB_SE2A1_0", - "RIOB_SE2A1_1", - "RIOB_SE2A2_0", - "RIOB_SE2A2_1", - "RIOB_SE2A3_0", - "RIOB_SE2A3_1", - "RIOB_SE4BEG0_0", - "RIOB_SE4BEG0_1", - "RIOB_SE4BEG1_0", - "RIOB_SE4BEG1_1", - "RIOB_SE4BEG2_0", - "RIOB_SE4BEG2_1", - "RIOB_SE4BEG3_0", - "RIOB_SE4BEG3_1", - "RIOB_SE4C0_0", - "RIOB_SE4C0_1", - "RIOB_SE4C1_0", - "RIOB_SE4C1_1", - "RIOB_SE4C2_0", - "RIOB_SE4C2_1", - "RIOB_SE4C3_0", - "RIOB_SE4C3_1", - "RIOB_SW2A0_0", - "RIOB_SW2A0_1", - "RIOB_SW2A1_0", - "RIOB_SW2A1_1", - "RIOB_SW2A2_0", - "RIOB_SW2A2_1", - "RIOB_SW2A3_0", - "RIOB_SW2A3_1", - "RIOB_SW4A0_0", - "RIOB_SW4A0_1", - "RIOB_SW4A1_0", - "RIOB_SW4A1_1", - "RIOB_SW4A2_0", - "RIOB_SW4A2_1", - "RIOB_SW4A3_0", - "RIOB_SW4A3_1", - "RIOB_SW4END0_0", - "RIOB_SW4END0_1", - "RIOB_SW4END1_0", - "RIOB_SW4END1_1", - "RIOB_SW4END2_0", - "RIOB_SW4END2_1", - "RIOB_SW4END3_0", - "RIOB_SW4END3_1", - "RIOB_WL1END0_0", - "RIOB_WL1END0_1", - "RIOB_WL1END1_0", - "RIOB_WL1END1_1", - "RIOB_WL1END2_0", - "RIOB_WL1END2_1", - "RIOB_WL1END3_0", - "RIOB_WL1END3_1", - "RIOB_WR1END0_0", - "RIOB_WR1END0_1", - "RIOB_WR1END1_0", - "RIOB_WR1END1_1", - "RIOB_WR1END2_0", - "RIOB_WR1END2_1", - "RIOB_WR1END3_0", - "RIOB_WR1END3_1", - "RIOB_WW2A0_0", - "RIOB_WW2A0_1", - "RIOB_WW2A1_0", - "RIOB_WW2A1_1", - "RIOB_WW2A2_0", - "RIOB_WW2A2_1", - "RIOB_WW2A3_0", - "RIOB_WW2A3_1", - "RIOB_WW2END0_0", - "RIOB_WW2END0_1", - "RIOB_WW2END1_0", - "RIOB_WW2END1_1", - "RIOB_WW2END2_0", - "RIOB_WW2END2_1", - "RIOB_WW2END3_0", - "RIOB_WW2END3_1", - "RIOB_WW4A0_0", - "RIOB_WW4A0_1", - "RIOB_WW4A1_0", - "RIOB_WW4A1_1", - "RIOB_WW4A2_0", - "RIOB_WW4A2_1", - "RIOB_WW4A3_0", - "RIOB_WW4A3_1", - "RIOB_WW4B0_0", - "RIOB_WW4B0_1", - "RIOB_WW4B1_0", - "RIOB_WW4B1_1", - "RIOB_WW4B2_0", - "RIOB_WW4B2_1", - "RIOB_WW4B3_0", - "RIOB_WW4B3_1", - "RIOB_WW4C0_0", - "RIOB_WW4C0_1", - "RIOB_WW4C1_0", - "RIOB_WW4C1_1", - "RIOB_WW4C2_0", - "RIOB_WW4C2_1", - "RIOB_WW4C3_0", - "RIOB_WW4C3_1", - "RIOB_WW4END0_0", - "RIOB_WW4END0_1", - "RIOB_WW4END1_0", - "RIOB_WW4END1_1", - "RIOB_WW4END2_0", - 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"208.000", + "res": "1024.400" + }, + "RIOB_WL1END0_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END0_1": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END1_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END1_1": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END2_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END2_1": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END3_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END3_1": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END0_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END0_1": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END1_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END1_1": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END2_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END2_1": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END3_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END3_1": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WW2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A0_1": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A1_1": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A2_1": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A3_1": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END0_1": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END1_1": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END2_1": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END3_1": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW4A0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A0_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A1_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A2_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A3_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B0_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B1_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B2_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B3_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C0_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C1_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C2_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C3_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END0_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END1_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END2_1": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END3_1": { + "cap": "208.000", + "res": "1024.400" + } + } } diff --git a/kintex7/tile_type_RIOB18_SING.json b/kintex7/tile_type_RIOB18_SING.json index 569985b..3bb5cb9 100644 --- a/kintex7/tile_type_RIOB18_SING.json +++ b/kintex7/tile_type_RIOB18_SING.json @@ -5,23 +5,131 @@ "name": "X0Y0", "prefix": "IOB", "site_pins": { - "DCITERMDISABLE": "IOB_DCI_T_TERM0", + "DCITERMDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_DCI_T_TERM0" + }, "DIFFI_IN": null, "DIFFO_IN": null, - "DIFFO_OUT": "IOB_DIFFO_OUT0", + "DIFFO_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_DIFFO_OUT0" + }, "DIFF_TERM_INT_EN": null, - "I": "IOB_IBUF0", - "IBUFDISABLE": "IOB_IBUF_DISABLE0", - "KEEPER_INT_EN": "IOB_KEEPER_INT_EN_1", - "O": "IOB_O0", + "I": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_IBUF0" + }, + "IBUFDISABLE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_IBUF_DISABLE0" + }, + "KEEPER_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_KEEPER_INT_EN_1" + }, + "O": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_O0" + }, "O_IN": null, - "O_OUT": "IOB_O_OUT0", - "PADOUT": "IOB_PADOUT0", - "PD_INT_EN": "IOB_PD_INT_EN_1", - "PU_INT_EN": "IOB_PU_INT_EN_1", - "T": "IOB_T0", + "O_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_O_OUT0" + }, + "PADOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_PADOUT0" + }, + "PD_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PD_INT_EN_1" + }, + "PU_INT_EN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_PU_INT_EN_1" + }, + "T": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOB_T0" + }, "T_IN": null, - "T_OUT": "IOB_T_OUT0" + "T_OUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOB_T_OUT0" + } }, "type": "IOB18", "x_coord": 0, @@ -29,147 +137,519 @@ } ], "tile_type": "RIOB18_SING", - "wires": [ - "IOB_DCI_T_TERM0", - "IOB_DIFFI_IN0", - "IOB_DIFFO_IN0", - "IOB_DIFFO_OUT0", - "IOB_DIFF_TERM_INT_EN_STUB", - "IOB_IBUF0", - "IOB_IBUF_DISABLE0", - "IOB_KEEPER_INT_EN_1", - "IOB_O0", - "IOB_O_IN0", - "IOB_O_OUT0", - "IOB_PADOUT0", - "IOB_PD_INT_EN_1", - "IOB_PU_INT_EN_1", - "IOB_T0", - "IOB_T_IN0", - "IOB_T_OUT0", - "RIOB_EE2A0_0", - "RIOB_EE2A1_0", - "RIOB_EE2A2_0", - "RIOB_EE2A3_0", - "RIOB_EE2BEG0_0", - "RIOB_EE2BEG1_0", - "RIOB_EE2BEG2_0", - "RIOB_EE2BEG3_0", - "RIOB_EE4A0_0", - "RIOB_EE4A1_0", - "RIOB_EE4A2_0", - "RIOB_EE4A3_0", - "RIOB_EE4B0_0", - "RIOB_EE4B1_0", - "RIOB_EE4B2_0", - "RIOB_EE4B3_0", - "RIOB_EE4BEG0_0", - "RIOB_EE4BEG1_0", - "RIOB_EE4BEG2_0", - "RIOB_EE4BEG3_0", - "RIOB_EE4C0_0", - "RIOB_EE4C1_0", - "RIOB_EE4C2_0", - "RIOB_EE4C3_0", - "RIOB_EL1BEG0_0", - "RIOB_EL1BEG1_0", - "RIOB_EL1BEG2_0", - "RIOB_EL1BEG3_0", - "RIOB_ER1BEG0_0", - "RIOB_ER1BEG1_0", - "RIOB_ER1BEG2_0", - "RIOB_ER1BEG3_0", - "RIOB_LH10_0", - "RIOB_LH11_0", - "RIOB_LH12_0", - "RIOB_LH1_0", - "RIOB_LH2_0", - "RIOB_LH3_0", - "RIOB_LH4_0", - "RIOB_LH5_0", - "RIOB_LH6_0", - "RIOB_LH7_0", - "RIOB_LH8_0", - "RIOB_LH9_0", - "RIOB_NE2A0_0", - "RIOB_NE2A1_0", - "RIOB_NE2A2_0", - "RIOB_NE2A3_0", - "RIOB_NE4BEG0_0", - "RIOB_NE4BEG1_0", - "RIOB_NE4BEG2_0", - "RIOB_NE4BEG3_0", - "RIOB_NE4C0_0", - "RIOB_NE4C1_0", - "RIOB_NE4C2_0", - "RIOB_NE4C3_0", - "RIOB_NW2A0_0", - "RIOB_NW2A1_0", - "RIOB_NW2A2_0", - "RIOB_NW2A3_0", - "RIOB_NW4A0_0", - "RIOB_NW4A1_0", - "RIOB_NW4A2_0", - "RIOB_NW4A3_0", - "RIOB_NW4END0_0", - "RIOB_NW4END1_0", - "RIOB_NW4END2_0", - "RIOB_NW4END3_0", - "RIOB_SE2A0_0", - "RIOB_SE2A1_0", - "RIOB_SE2A2_0", - "RIOB_SE2A3_0", - "RIOB_SE4BEG0_0", - "RIOB_SE4BEG1_0", - "RIOB_SE4BEG2_0", - "RIOB_SE4BEG3_0", - "RIOB_SE4C0_0", - "RIOB_SE4C1_0", - "RIOB_SE4C2_0", - "RIOB_SE4C3_0", - "RIOB_SW2A0_0", - "RIOB_SW2A1_0", - "RIOB_SW2A2_0", - "RIOB_SW2A3_0", - "RIOB_SW4A0_0", - "RIOB_SW4A1_0", - "RIOB_SW4A2_0", - "RIOB_SW4A3_0", - "RIOB_SW4END0_0", - "RIOB_SW4END1_0", - "RIOB_SW4END2_0", - "RIOB_SW4END3_0", - "RIOB_WL1END0_0", - "RIOB_WL1END1_0", - "RIOB_WL1END2_0", - "RIOB_WL1END3_0", - "RIOB_WR1END0_0", - "RIOB_WR1END1_0", - "RIOB_WR1END2_0", - "RIOB_WR1END3_0", - "RIOB_WW2A0_0", - "RIOB_WW2A1_0", - "RIOB_WW2A2_0", - "RIOB_WW2A3_0", - "RIOB_WW2END0_0", - "RIOB_WW2END1_0", - "RIOB_WW2END2_0", - "RIOB_WW2END3_0", - "RIOB_WW4A0_0", - "RIOB_WW4A1_0", - "RIOB_WW4A2_0", - "RIOB_WW4A3_0", - "RIOB_WW4B0_0", - "RIOB_WW4B1_0", - "RIOB_WW4B2_0", - "RIOB_WW4B3_0", - "RIOB_WW4C0_0", - "RIOB_WW4C1_0", - "RIOB_WW4C2_0", - "RIOB_WW4C3_0", - "RIOB_WW4END0_0", - "RIOB_WW4END1_0", - "RIOB_WW4END2_0", - "RIOB_WW4END3_0" - ] + "wires": { + "IOB_DCI_T_TERM0": null, + "IOB_DIFFI_IN0": null, + "IOB_DIFFO_IN0": null, + "IOB_DIFFO_OUT0": null, + "IOB_DIFF_TERM_INT_EN_STUB": null, + "IOB_IBUF0": null, + "IOB_IBUF_DISABLE0": null, + "IOB_KEEPER_INT_EN_1": null, + "IOB_O0": null, + "IOB_O_IN0": null, + "IOB_O_OUT0": null, + "IOB_PADOUT0": null, + "IOB_PD_INT_EN_1": null, + "IOB_PU_INT_EN_1": null, + "IOB_T0": null, + "IOB_T_IN0": null, + "IOB_T_OUT0": null, + "RIOB_EE2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_EE2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_EE2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_EE2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_EE2BEG0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_EE2BEG1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_EE2BEG2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_EE2BEG3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_EE4A0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4A1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4A2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4A3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4B0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4B1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4B2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4B3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4BEG0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4BEG1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4BEG2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4BEG3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4C0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4C1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4C2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EE4C3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_EL1BEG0_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_EL1BEG1_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_EL1BEG2_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_EL1BEG3_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_ER1BEG0_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_ER1BEG1_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_ER1BEG2_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_ER1BEG3_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_LH10_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH11_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH12_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH1_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH2_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH3_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH4_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH5_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH6_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH7_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH8_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_LH9_0": { + "cap": "194.420", + "res": "48.990" + }, + "RIOB_NE2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_NE2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_NE2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_NE2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_NE4BEG0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NE4BEG1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NE4BEG2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NE4BEG3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NE4C0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NE4C1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NE4C2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NE4C3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NW2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_NW2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_NW2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_NW2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_NW4A0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NW4A1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NW4A2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NW4A3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NW4END0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NW4END1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NW4END2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_NW4END3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SE2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_SE2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_SE2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_SE2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_SE4BEG0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SE4BEG1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SE4BEG2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SE4BEG3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SE4C0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SE4C1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SE4C2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SE4C3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SW2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_SW2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_SW2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_SW2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_SW4A0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SW4A1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SW4A2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SW4A3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SW4END0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SW4END1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SW4END2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_SW4END3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WL1END0_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END1_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END2_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WL1END3_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END0_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END1_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END2_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WR1END3_0": { + "cap": "201.000", + "res": "1024.400" + }, + "RIOB_WW2A0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2A3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END0_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END1_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END2_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW2END3_0": { + "cap": "215.000", + "res": "1024.400" + }, + "RIOB_WW4A0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4A3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4B3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4C3_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END0_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END1_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END2_0": { + "cap": "208.000", + "res": "1024.400" + }, + "RIOB_WW4END3_0": { + "cap": "208.000", + "res": "1024.400" + } + } } diff --git a/kintex7/tile_type_RIOI.json b/kintex7/tile_type_RIOI.json index f74e376..03f12f0 100644 --- a/kintex7/tile_type_RIOI.json +++ b/kintex7/tile_type_RIOI.json @@ -2,3271 +2,10988 @@ "pips": { "RIOI.IOI_BYP0_0->RIOI_ODELAY1_OFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_OFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP0_0" }, "RIOI.IOI_BYP0_1->RIOI_ODELAY0_OFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP0_1" }, "RIOI.IOI_BYP1_0->RIOI_ODELAY1_OFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_OFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP1_0" }, "RIOI.IOI_BYP1_1->RIOI_ODELAY0_OFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP1_1" }, "RIOI.IOI_BYP2_0->IOI_ODELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP2_0" }, "RIOI.IOI_BYP2_1->IOI_ODELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP2_1" }, "RIOI.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI.IOI_BYP5_0->RIOI_ODELAY1_OFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_OFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP5_0" }, "RIOI.IOI_BYP5_1->RIOI_ODELAY0_OFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP5_1" }, "RIOI.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "RIOI.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_1" }, "RIOI.IOI_BYP7_0->RIOI_IDELAY1_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "RIOI.IOI_BYP7_1->RIOI_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_1" }, "RIOI.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI.IOI_CLK1_0->IOI_ODELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "RIOI.IOI_CLK1_1->IOI_ODELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "RIOI.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "RIOI.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_1" }, "RIOI.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "RIOI.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_1" }, "RIOI.IOI_FAN4_0->RIOI_IDELAY1_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "RIOI.IOI_FAN4_1->RIOI_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_1" }, "RIOI.IOI_FAN5_0->RIOI_IDELAY1_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "RIOI.IOI_FAN5_1->RIOI_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_1" }, "RIOI.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "RIOI.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "RIOI.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "RIOI.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "RIOI.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "RIOI.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "RIOI.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "RIOI.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "RIOI.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "RIOI.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "RIOI.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS13_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT" }, "RIOI.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS13_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_OUTN1" }, "RIOI.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS16_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_OUTN65" }, "RIOI.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS22_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_RDY" }, "RIOI.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS16_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT" }, "RIOI.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I2GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "RIOI.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "RIOI.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "RIOI.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "RIOI.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "RIOI.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "RIOI.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "RIOI.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "RIOI.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC1_O" }, "RIOI.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q1" }, "RIOI.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q2" }, "RIOI.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q3" }, "RIOI.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q4" }, "RIOI.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q5" }, "RIOI.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q6" }, "RIOI.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q7" }, "RIOI.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q8" }, "RIOI.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "RIOI.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_1" }, "RIOI.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "RIOI.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_1" }, "RIOI.IOI_IMUX11_0->IOI_ODELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX11_0" }, "RIOI.IOI_IMUX11_1->IOI_ODELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX11_1" }, "RIOI.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "RIOI.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_1" }, "RIOI.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "RIOI.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_1" }, "RIOI.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "RIOI.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_1" }, "RIOI.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "RIOI.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_1" }, "RIOI.IOI_IMUX16_0->IOI_ODELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX16_0" }, "RIOI.IOI_IMUX16_1->IOI_ODELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX16_1" }, "RIOI.IOI_IMUX17_0->IOI_ODELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX17_0" }, "RIOI.IOI_IMUX17_1->IOI_ODELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX17_1" }, "RIOI.IOI_IMUX18_0->IOI_ODELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX18_0" }, "RIOI.IOI_IMUX18_1->IOI_ODELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX18_1" }, "RIOI.IOI_IMUX19_0->IOI_ODELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX19_0" }, "RIOI.IOI_IMUX19_1->IOI_ODELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX19_1" }, "RIOI.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "RIOI.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_1" }, "RIOI.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI.IOI_IMUX21_0->IOI_OLOGIC1_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "RIOI.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_1" }, "RIOI.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI.IOI_IMUX23_0->IOI_ODELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX23_0" }, "RIOI.IOI_IMUX23_1->IOI_ODELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX23_1" }, "RIOI.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAYCTRL_RST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX24_0" }, "RIOI.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "RIOI.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_1" }, "RIOI.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "RIOI.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_1" }, "RIOI.IOI_IMUX27_0->IOI_ODELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX27_0" }, "RIOI.IOI_IMUX27_1->IOI_ODELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX27_1" }, "RIOI.IOI_IMUX28_0->IOI_ODELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX28_0" }, "RIOI.IOI_IMUX28_1->IOI_ODELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX28_1" }, "RIOI.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "RIOI.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_1" }, "RIOI.IOI_IMUX2_0->IOI_ODELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX2_0" }, "RIOI.IOI_IMUX2_1->IOI_ODELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX2_1" }, "RIOI.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "RIOI.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_1" }, "RIOI.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "RIOI.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_1" }, "RIOI.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "RIOI.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_1" }, "RIOI.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "RIOI.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_1" }, "RIOI.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "RIOI.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_1" }, "RIOI.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "RIOI.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_1" }, "RIOI.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "RIOI.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_1" }, "RIOI.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "RIOI.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_1" }, "RIOI.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "RIOI.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_1" }, "RIOI.IOI_IMUX3_0->IOI_ODELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX3_0" }, "RIOI.IOI_IMUX3_1->IOI_ODELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX3_1" }, "RIOI.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "RIOI.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_1" }, "RIOI.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "RIOI.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_1" }, "RIOI.IOI_IMUX42_0->IOI_OLOGIC1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "RIOI.IOI_IMUX42_1->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_1" }, "RIOI.IOI_IMUX43_0->IOI_OLOGIC1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "RIOI.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_1" }, "RIOI.IOI_IMUX44_0->IOI_OLOGIC1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "RIOI.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_1" }, "RIOI.IOI_IMUX45_0->IOI_OLOGIC1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "RIOI.IOI_IMUX45_1->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_1" }, "RIOI.IOI_IMUX46_0->IOI_OLOGIC1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "RIOI.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_1" }, "RIOI.IOI_IMUX47_0->IOI_OLOGIC1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "RIOI.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_1" }, "RIOI.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "RIOI.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_1" }, "RIOI.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "RIOI.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_1" }, "RIOI.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "RIOI.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_1" }, "RIOI.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "RIOI.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_1" }, "RIOI.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "RIOI.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_1" }, "RIOI.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI.IOI_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI.IOI_IOCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI.IOI_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI.IOI_IOCLK1->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ 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"in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI.IOI_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI.IOI_IOCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + 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"is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { 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"0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK1->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK1" }, "RIOI.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK2->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" 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"0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI.IOI_OCLK_0->IOI_ODELAY0_CLKIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CLKIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI.IOI_OCLK_1->IOI_ODELAY1_CLKIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CLKIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI.IOI_ODELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT0" }, "RIOI.IOI_ODELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT1" }, "RIOI.IOI_ODELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT2" }, "RIOI.IOI_ODELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT3" }, "RIOI.IOI_ODELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT4" }, "RIOI.IOI_ODELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT0" }, "RIOI.IOI_ODELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT1" }, "RIOI.IOI_ODELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT2" }, "RIOI.IOI_ODELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT3" }, "RIOI.IOI_ODELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT4" }, "RIOI.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "RIOI.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC1_IOCLKGLITCH" }, "RIOI.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "RIOI.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0" }, "RIOI.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "RIOI.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "RIOI.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90" }, "RIOI.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0" }, "RIOI.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "RIOI.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "RIOI.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0" }, "RIOI.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": 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"is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ODELAY0_DATAOUT" }, "RIOI.RIOI_ODELAY1_DATAOUT->RIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_O1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ODELAY1_DATAOUT" }, "RIOI.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_OFB" }, "RIOI.RIOI_OLOGIC0_OFB->RIOI_ODELAY0_ODATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": 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"res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB" }, "RIOI.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI.RIOI_OLOGIC0_TQ->>RIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_OFB" }, "RIOI.RIOI_OLOGIC1_OFB->RIOI_ODELAY1_ODATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_ODATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_OFB" }, "RIOI.RIOI_OLOGIC1_OQ->>RIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB" }, "RIOI.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI.RIOI_OLOGIC1_TQ->>RIOI_T1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI.RIOI_OSOUT11->RIOI_OSIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT11" }, "RIOI.RIOI_OSOUT21->RIOI_OSIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT21" } }, @@ -3275,39 +10992,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC1_CLK", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "D1": "IOI_OLOGIC1_D1", - "D2": "IOI_OLOGIC1_D2", - "D3": "IOI_OLOGIC1_D3", - "D4": "IOI_OLOGIC1_D4", - "D5": "IOI_OLOGIC1_D5", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "OCE": "IOI_OLOGIC1_OCE", - "OFB": "RIOI_OLOGIC1_OFB", - "OQ": "RIOI_OLOGIC1_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_OSOUT11", - "SHIFTOUT2": "RIOI_OSOUT21", - "SR": "IOI_OLOGIC1_SR", - "T1": "IOI_OLOGIC1_T1", - "T2": "IOI_OLOGIC1_T2", - "T3": "IOI_OLOGIC1_T3", - "T4": "IOI_OLOGIC1_T4", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TCE": "IOI_OLOGIC1_TCE", - "TFB": "RIOI_OLOGIC1_TFB", - "TQ": "RIOI_OLOGIC1_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TQ" + } }, "type": "OLOGICE2", "x_coord": 0, @@ -3317,29 +11304,236 @@ "name": "X0Y0", "prefix": "ODELAY", "site_pins": { - "C": "IOI_ODELAY1_C", - "CE": "IOI_ODELAY1_CE", - "CINVCTRL": "IOI_ODELAY1_CINVCTRL", - "CLKIN": "IOI_ODELAY1_CLKIN", - "CNTVALUEIN0": "IOI_ODELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_ODELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_ODELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_ODELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_ODELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_ODELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_ODELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_ODELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_ODELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_ODELAY1_CNTVALUEOUT4", - "DATAOUT": "RIOI_ODELAY1_DATAOUT", - "INC": "IOI_ODELAY1_INC", - "LD": "IOI_ODELAY1_LD", - "LDPIPEEN": "IOI_ODELAY1_LDPIPEEN", - "ODATAIN": "RIOI_ODELAY1_ODATAIN", - "OFDLY0": "RIOI_ODELAY1_OFDLY0", - "OFDLY1": "RIOI_ODELAY1_OFDLY1", - "OFDLY2": "RIOI_ODELAY1_OFDLY2", - "REGRST": "IOI_ODELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CINVCTRL" + }, + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CLKIN" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT4" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_ODELAY1_DATAOUT" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_LDPIPEEN" + }, + "ODATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_ODATAIN" + }, + "OFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_OFDLY0" + }, + "OFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_OFDLY1" + }, + "OFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_OFDLY2" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_REGRST" + } }, "type": "ODELAYE2", "x_coord": 0, @@ -3349,37 +11543,307 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "CE1": "IOI_ILOGIC1_CE1", - "CE2": "IOI_ILOGIC1_CE2", - "CLK": "IOI_ILOGIC1_CLK", - "CLKB": "IOI_ILOGIC1_CLKB", - "CLKDIV": "IOI_ILOGIC1_CLKDIV", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "D": "RIOI_ILOGIC1_D", - "DDLY": "RIOI_ILOGIC1_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "O": "IOI_ILOGIC1_O", - "OCLK": "IOI_ILOGIC1_OCLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "OFB": "RIOI_ILOGIC1_OFB", - "Q1": "IOI_ILOGIC1_Q1", - "Q2": "IOI_ILOGIC1_Q2", - "Q3": "IOI_ILOGIC1_Q3", - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q6": "IOI_ILOGIC1_Q6", - "Q7": "IOI_ILOGIC1_Q7", - "Q8": "IOI_ILOGIC1_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC1_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q1" + }, + "Q2": { + "delay": [ + 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"RIOI_ILOGIC1_TFB" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN11" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN21" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_TFB" + } }, "type": "ILOGICE2", "x_coord": 0, @@ -3389,39 +11853,327 @@ "name": "X0Y1", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "RIOI_OLOGIC0_OFB", - "OQ": "RIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OQ" + }, "REV": null, - "SHIFTIN1": "RIOI_OSIN10", - "SHIFTIN2": "RIOI_OSIN20", - "SHIFTOUT1": "RIOI_OSOUT10", - "SHIFTOUT2": "RIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "RIOI_OLOGIC0_TFB", - "TQ": "RIOI_OLOGIC0_TQ" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN10" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN20" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE2", "x_coord": 0, @@ -3431,29 +12183,236 @@ "name": "X0Y1", "prefix": "ODELAY", "site_pins": { - "C": "IOI_ODELAY0_C", - "CE": "IOI_ODELAY0_CE", - "CINVCTRL": "IOI_ODELAY0_CINVCTRL", - "CLKIN": "IOI_ODELAY0_CLKIN", - "CNTVALUEIN0": "IOI_ODELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_ODELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_ODELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_ODELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_ODELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_ODELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_ODELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_ODELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_ODELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_ODELAY0_CNTVALUEOUT4", - "DATAOUT": "RIOI_ODELAY0_DATAOUT", - "INC": "IOI_ODELAY0_INC", - "LD": "IOI_ODELAY0_LD", - "LDPIPEEN": "IOI_ODELAY0_LDPIPEEN", - "ODATAIN": "RIOI_ODELAY0_ODATAIN", - "OFDLY0": "RIOI_ODELAY0_OFDLY0", - "OFDLY1": "RIOI_ODELAY0_OFDLY1", - "OFDLY2": "RIOI_ODELAY0_OFDLY2", - "REGRST": "IOI_ODELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CINVCTRL" + }, + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CLKIN" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT4" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_ODELAY0_DATAOUT" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_LDPIPEEN" + }, + "ODATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_ODATAIN" + }, + "OFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY0" + }, + "OFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY1" + }, + "OFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY2" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_REGRST" + } }, "type": "ODELAYE2", "x_coord": 0, @@ -3463,37 +12422,289 @@ "name": "X0Y1", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "RIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "RIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE2", "x_coord": 0, @@ -3503,29 +12714,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY1_C", - "CE": "IOI_IDELAY1_CE", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY1_DATAIN", - "DATAOUT": "RIOI_IDELAY1_DATAOUT", - "IDATAIN": "RIOI_IDELAY1_IDATAIN", - "IFDLY0": "RIOI_IDELAY1_IFDLY0", - "IFDLY1": "RIOI_IDELAY1_IFDLY1", - "IFDLY2": "RIOI_IDELAY1_IFDLY2", - "INC": "IOI_IDELAY1_INC", - "LD": "IOI_IDELAY1_LD", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "REGRST": "IOI_IDELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY1_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_REGRST" + } }, "type": "IDELAYE2_FINEDELAY", "x_coord": 0, @@ -3535,29 +12953,236 @@ "name": "X0Y1", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "IFDLY0": "RIOI_IDELAY0_IFDLY0", - "IFDLY1": "RIOI_IDELAY0_IFDLY1", - "IFDLY2": "RIOI_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2_FINEDELAY", "x_coord": 0, @@ -3565,750 +13190,750 @@ } ], "tile_type": "RIOI", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS0_1", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS1_1", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS2_1", - "IOI_BLOCK_OUTS3_0", - "IOI_BLOCK_OUTS3_1", - "IOI_BYP0_0", - "IOI_BYP0_1", - "IOI_BYP1_0", - "IOI_BYP1_1", - "IOI_BYP2_0", - "IOI_BYP2_1", - "IOI_BYP3_0", - "IOI_BYP3_1", - "IOI_BYP4_0", - "IOI_BYP4_1", - "IOI_BYP5_0", - "IOI_BYP5_1", - "IOI_BYP6_0", - "IOI_BYP6_1", - "IOI_BYP7_0", - "IOI_BYP7_1", - "IOI_CLK0_0", - "IOI_CLK0_1", - "IOI_CLK1_0", - "IOI_CLK1_1", - "IOI_CTRL0_0", - "IOI_CTRL0_1", - "IOI_CTRL1_0", - "IOI_CTRL1_1", - "IOI_DCI_DCIDONE", - "IOI_DCI_TSTCLK", - "IOI_DCI_TSTHLN", - "IOI_DCI_TSTHLP", - "IOI_DCI_TSTRST", - "IOI_DCI_TSTRST0", - "IOI_EE2A0_0", - "IOI_EE2A0_1", - "IOI_EE2A1_0", - "IOI_EE2A1_1", - "IOI_EE2A2_0", - "IOI_EE2A2_1", - "IOI_EE2A3_0", - "IOI_EE2A3_1", - "IOI_EE2BEG0_0", - "IOI_EE2BEG0_1", - "IOI_EE2BEG1_0", - "IOI_EE2BEG1_1", - "IOI_EE2BEG2_0", - "IOI_EE2BEG2_1", - "IOI_EE2BEG3_0", - "IOI_EE2BEG3_1", - "IOI_EE4A0_0", - "IOI_EE4A0_1", - "IOI_EE4A1_0", - "IOI_EE4A1_1", - "IOI_EE4A2_0", - "IOI_EE4A2_1", - "IOI_EE4A3_0", - "IOI_EE4A3_1", - "IOI_EE4B0_0", - "IOI_EE4B0_1", - "IOI_EE4B1_0", - "IOI_EE4B1_1", - "IOI_EE4B2_0", - "IOI_EE4B2_1", - "IOI_EE4B3_0", - "IOI_EE4B3_1", - "IOI_EE4BEG0_0", - "IOI_EE4BEG0_1", - "IOI_EE4BEG1_0", - "IOI_EE4BEG1_1", - "IOI_EE4BEG2_0", - "IOI_EE4BEG2_1", - "IOI_EE4BEG3_0", - "IOI_EE4BEG3_1", - "IOI_EE4C0_0", - "IOI_EE4C0_1", - "IOI_EE4C1_0", - "IOI_EE4C1_1", - "IOI_EE4C2_0", - "IOI_EE4C2_1", - "IOI_EE4C3_0", - "IOI_EE4C3_1", - "IOI_EL1BEG0_0", - "IOI_EL1BEG0_1", - "IOI_EL1BEG1_0", - "IOI_EL1BEG1_1", - "IOI_EL1BEG2_0", - "IOI_EL1BEG2_1", - "IOI_EL1BEG3_0", - "IOI_EL1BEG3_1", - "IOI_ER1BEG0_0", - "IOI_ER1BEG0_1", - "IOI_ER1BEG1_0", - "IOI_ER1BEG1_1", - "IOI_ER1BEG2_0", - "IOI_ER1BEG2_1", - "IOI_ER1BEG3_0", - "IOI_ER1BEG3_1", - "IOI_FAN0_0", - "IOI_FAN0_1", - "IOI_FAN1_0", - "IOI_FAN1_1", - "IOI_FAN2_0", - "IOI_FAN2_1", - "IOI_FAN3_0", - "IOI_FAN3_1", - "IOI_FAN4_0", - "IOI_FAN4_1", - "IOI_FAN5_0", - "IOI_FAN5_1", - "IOI_FAN6_0", - "IOI_FAN6_1", - "IOI_FAN7_0", - "IOI_FAN7_1", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY1_C", - "IOI_IDELAY1_CE", - "IOI_IDELAY1_CINVCTRL", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT0", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_IDELAY1_DATAIN", - "IOI_IDELAY1_INC", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_LDPIPEEN", - "IOI_IDELAY1_REGRST", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC1_BITSLIP", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC1_CE2", - "IOI_ILOGIC1_CLK", - "IOI_ILOGIC1_CLKB", - "IOI_ILOGIC1_CLKDIV", - "IOI_ILOGIC1_CLKDIVP", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_ILOGIC1_O", - "IOI_ILOGIC1_OCLK", - "IOI_ILOGIC1_OCLKB", - "IOI_ILOGIC1_Q1", - "IOI_ILOGIC1_Q2", - "IOI_ILOGIC1_Q3", - "IOI_ILOGIC1_Q4", - "IOI_ILOGIC1_Q5", - "IOI_ILOGIC1_Q6", - "IOI_ILOGIC1_Q7", - "IOI_ILOGIC1_Q8", - "IOI_ILOGIC1_REV", - "IOI_ILOGIC1_SR", - "IOI_IMUX0_0", - "IOI_IMUX0_1", - "IOI_IMUX10_0", - "IOI_IMUX10_1", - "IOI_IMUX11_0", - "IOI_IMUX11_1", - "IOI_IMUX12_0", - "IOI_IMUX12_1", - "IOI_IMUX13_0", - "IOI_IMUX13_1", - "IOI_IMUX14_0", - "IOI_IMUX14_1", - "IOI_IMUX15_0", - "IOI_IMUX15_1", - "IOI_IMUX16_0", - "IOI_IMUX16_1", - "IOI_IMUX17_0", - "IOI_IMUX17_1", - "IOI_IMUX18_0", - "IOI_IMUX18_1", - "IOI_IMUX19_0", - "IOI_IMUX19_1", - "IOI_IMUX1_0", - "IOI_IMUX1_1", - "IOI_IMUX20_0", - "IOI_IMUX20_1", - "IOI_IMUX21_0", - "IOI_IMUX21_1", - "IOI_IMUX22_0", - "IOI_IMUX22_1", - "IOI_IMUX23_0", - "IOI_IMUX23_1", - "IOI_IMUX24_0", - "IOI_IMUX24_1", - "IOI_IMUX25_0", - "IOI_IMUX25_1", - "IOI_IMUX26_0", - "IOI_IMUX26_1", - "IOI_IMUX27_0", - "IOI_IMUX27_1", - "IOI_IMUX28_0", - "IOI_IMUX28_1", - "IOI_IMUX29_0", - "IOI_IMUX29_1", - "IOI_IMUX2_0", - "IOI_IMUX2_1", - "IOI_IMUX30_0", - "IOI_IMUX30_1", - "IOI_IMUX31_0", - "IOI_IMUX31_1", - "IOI_IMUX32_0", - "IOI_IMUX32_1", - "IOI_IMUX33_0", - "IOI_IMUX33_1", - "IOI_IMUX34_0", - "IOI_IMUX34_1", - "IOI_IMUX35_0", - "IOI_IMUX35_1", - "IOI_IMUX36_0", - "IOI_IMUX36_1", - "IOI_IMUX37_0", - "IOI_IMUX37_1", - "IOI_IMUX38_0", - "IOI_IMUX38_1", - "IOI_IMUX39_0", - "IOI_IMUX39_1", - "IOI_IMUX3_0", - "IOI_IMUX3_1", - "IOI_IMUX40_0", - "IOI_IMUX40_1", - "IOI_IMUX41_0", - "IOI_IMUX41_1", - "IOI_IMUX42_0", - "IOI_IMUX42_1", - "IOI_IMUX43_0", - "IOI_IMUX43_1", - "IOI_IMUX44_0", - "IOI_IMUX44_1", - "IOI_IMUX45_0", - "IOI_IMUX45_1", - "IOI_IMUX46_0", - "IOI_IMUX46_1", - "IOI_IMUX47_0", - "IOI_IMUX47_1", - "IOI_IMUX4_0", - "IOI_IMUX4_1", - "IOI_IMUX5_0", - "IOI_IMUX5_1", - "IOI_IMUX6_0", - "IOI_IMUX6_1", - "IOI_IMUX7_0", - "IOI_IMUX7_1", - "IOI_IMUX8_0", - "IOI_IMUX8_1", - "IOI_IMUX9_0", - "IOI_IMUX9_1", - "IOI_IMUX_RC0", - "IOI_IMUX_RC1", - "IOI_IMUX_RC2", - "IOI_IMUX_RC3", - "IOI_INT_DCI_EN", - "IOI_IOCLK0", - "IOI_IOCLK1", - "IOI_IOCLK2", - "IOI_IOCLK3", - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK5", - "IOI_LH10_0", - "IOI_LH10_1", - "IOI_LH11_0", - "IOI_LH11_1", - "IOI_LH12_0", - "IOI_LH12_1", - "IOI_LH1_0", - "IOI_LH1_1", - "IOI_LH2_0", - "IOI_LH2_1", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_LH4_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_LH5_1", - "IOI_LH6_0", - "IOI_LH6_1", - "IOI_LH7_0", - "IOI_LH7_1", - "IOI_LH8_0", - "IOI_LH8_1", - "IOI_LH9_0", - "IOI_LH9_1", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS10_1", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS11_1", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS12_1", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS13_1", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS14_1", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS15_1", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS16_1", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS17_1", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS18_1", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS1_1", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS20_1", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS21_1", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS22_1", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS23_1", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS2_1", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS3_1", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS4_1", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS5_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS6_1", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS7_1", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS9_0", - "IOI_LOGIC_OUTS9_1", - "IOI_MONITOR_N", - "IOI_MONITOR_P", - "IOI_NE2A0_0", - "IOI_NE2A0_1", - "IOI_NE2A1_0", - "IOI_NE2A1_1", - "IOI_NE2A2_0", - "IOI_NE2A2_1", - "IOI_NE2A3_0", - "IOI_NE2A3_1", - "IOI_NE4BEG0_0", - "IOI_NE4BEG0_1", - "IOI_NE4BEG1_0", - "IOI_NE4BEG1_1", - "IOI_NE4BEG2_0", - "IOI_NE4BEG2_1", - "IOI_NE4BEG3_0", - "IOI_NE4BEG3_1", - "IOI_NE4C0_0", - "IOI_NE4C0_1", - "IOI_NE4C1_0", - "IOI_NE4C1_1", - "IOI_NE4C2_0", - "IOI_NE4C2_1", - "IOI_NE4C3_0", - "IOI_NE4C3_1", - "IOI_NW2A0_0", - "IOI_NW2A0_1", - "IOI_NW2A1_0", - "IOI_NW2A1_1", - "IOI_NW2A2_0", - "IOI_NW2A2_1", - "IOI_NW2A3_0", - "IOI_NW2A3_1", - "IOI_NW4A0_0", - "IOI_NW4A0_1", - "IOI_NW4A1_0", - "IOI_NW4A1_1", - "IOI_NW4A2_0", - "IOI_NW4A2_1", - "IOI_NW4A3_0", - "IOI_NW4A3_1", - "IOI_NW4END0_0", - "IOI_NW4END0_1", - "IOI_NW4END1_0", - "IOI_NW4END1_1", - "IOI_NW4END2_0", - "IOI_NW4END2_1", - "IOI_NW4END3_0", - "IOI_NW4END3_1", - "IOI_OCLKM_0", - "IOI_OCLKM_1", - "IOI_OCLK_0", - "IOI_OCLK_1", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_ODELAY1_C", - "IOI_ODELAY1_CE", - "IOI_ODELAY1_CINVCTRL", - "IOI_ODELAY1_CLKIN", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_ODELAY1_INC", - "IOI_ODELAY1_LD", - "IOI_ODELAY1_LDPIPEEN", - "IOI_ODELAY1_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_CLK", - "IOI_OLOGIC1_CLKB", - "IOI_OLOGIC1_CLKDIV", - "IOI_OLOGIC1_CLKDIVB", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_OLOGIC1_D1", - "IOI_OLOGIC1_D2", - "IOI_OLOGIC1_D3", - "IOI_OLOGIC1_D4", - "IOI_OLOGIC1_D5", - "IOI_OLOGIC1_D6", - "IOI_OLOGIC1_D7", - "IOI_OLOGIC1_D8", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_OLOGIC1_OCE", - "IOI_OLOGIC1_REV", - "IOI_OLOGIC1_SR", - "IOI_OLOGIC1_T1", - "IOI_OLOGIC1_T2", - "IOI_OLOGIC1_T3", - "IOI_OLOGIC1_T4", - "IOI_OLOGIC1_TBYTEIN", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_OLOGIC1_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR3", - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO3", - "IOI_SE2A0_0", - "IOI_SE2A0_1", - "IOI_SE2A1_0", - "IOI_SE2A1_1", - "IOI_SE2A2_0", - "IOI_SE2A2_1", - "IOI_SE2A3_0", - "IOI_SE2A3_1", - "IOI_SE4BEG0_0", - "IOI_SE4BEG0_1", - "IOI_SE4BEG1_0", - "IOI_SE4BEG1_1", - "IOI_SE4BEG2_0", - "IOI_SE4BEG2_1", - "IOI_SE4BEG3_0", - "IOI_SE4BEG3_1", - "IOI_SE4C0_0", - "IOI_SE4C0_1", - "IOI_SE4C1_0", - "IOI_SE4C1_1", - "IOI_SE4C2_0", - "IOI_SE4C2_1", - "IOI_SE4C3_0", - "IOI_SE4C3_1", - "IOI_SW2A0_0", - "IOI_SW2A0_1", - "IOI_SW2A1_0", - "IOI_SW2A1_1", - "IOI_SW2A2_0", - "IOI_SW2A2_1", - "IOI_SW2A3_0", - "IOI_SW2A3_1", - "IOI_SW4A0_0", - "IOI_SW4A0_1", - "IOI_SW4A1_0", - "IOI_SW4A1_1", - "IOI_SW4A2_0", - "IOI_SW4A2_1", - "IOI_SW4A3_0", - "IOI_SW4A3_1", - "IOI_SW4END0_0", - "IOI_SW4END0_1", - "IOI_SW4END1_0", - "IOI_SW4END1_1", - "IOI_SW4END2_0", - "IOI_SW4END2_1", - "IOI_SW4END3_0", - "IOI_SW4END3_1", - "IOI_TBYTEIN", - "IOI_WL1END0_0", - "IOI_WL1END0_1", - "IOI_WL1END1_0", - "IOI_WL1END1_1", - "IOI_WL1END2_0", - "IOI_WL1END2_1", - "IOI_WL1END3_0", - "IOI_WL1END3_1", - "IOI_WR1END0_0", - "IOI_WR1END0_1", - "IOI_WR1END1_0", - "IOI_WR1END1_1", - "IOI_WR1END2_0", - "IOI_WR1END2_1", - "IOI_WR1END3_0", - "IOI_WR1END3_1", - "IOI_WW2A0_0", - "IOI_WW2A0_1", - "IOI_WW2A1_0", - "IOI_WW2A1_1", - "IOI_WW2A2_0", - "IOI_WW2A2_1", - "IOI_WW2A3_0", - "IOI_WW2A3_1", - "IOI_WW2END0_0", - "IOI_WW2END0_1", - "IOI_WW2END1_0", - "IOI_WW2END1_1", - "IOI_WW2END2_0", - "IOI_WW2END2_1", - "IOI_WW2END3_0", - "IOI_WW2END3_1", - "IOI_WW4A0_0", - "IOI_WW4A0_1", - "IOI_WW4A1_0", - "IOI_WW4A1_1", - "IOI_WW4A2_0", - "IOI_WW4A2_1", - "IOI_WW4A3_0", - "IOI_WW4A3_1", - "IOI_WW4B0_0", - "IOI_WW4B0_1", - "IOI_WW4B1_0", - "IOI_WW4B1_1", - "IOI_WW4B2_0", - "IOI_WW4B2_1", - "IOI_WW4B3_0", - "IOI_WW4B3_1", - "IOI_WW4C0_0", - "IOI_WW4C0_1", - "IOI_WW4C1_0", - "IOI_WW4C1_1", - "IOI_WW4C2_0", - "IOI_WW4C2_1", - "IOI_WW4C3_0", - "IOI_WW4C3_1", - "IOI_WW4END0_0", - "IOI_WW4END0_1", - "IOI_WW4END1_0", - "IOI_WW4END1_1", - "IOI_WW4END2_0", - "IOI_WW4END2_1", - "IOI_WW4END3_0", - "IOI_WW4END3_1", - "RIOI_DCI_T_TERM0", - "RIOI_DCI_T_TERM1", - "RIOI_DIFF_TERM_INT_EN", - "RIOI_I0", - "RIOI_I1", - "RIOI_I2GCLK_BOT1", - "RIOI_I2GCLK_TOP0", - "RIOI_I2GCLK_TOP1", - "RIOI_IBUF0", - "RIOI_IBUF1", - "RIOI_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE1", - "RIOI_IDELAY0_DATAOUT", - "RIOI_IDELAY0_IDATAIN", - "RIOI_IDELAY0_IFDLY0", - "RIOI_IDELAY0_IFDLY1", - "RIOI_IDELAY0_IFDLY2", - "RIOI_IDELAY1_DATAOUT", - "RIOI_IDELAY1_IDATAIN", - "RIOI_IDELAY1_IFDLY0", - "RIOI_IDELAY1_IFDLY1", - "RIOI_IDELAY1_IFDLY2", - "RIOI_ILOGIC0_D", - "RIOI_ILOGIC0_DDLY", - "RIOI_ILOGIC0_OFB", - "RIOI_ILOGIC0_TFB", - "RIOI_ILOGIC1_D", - "RIOI_ILOGIC1_DDLY", - "RIOI_ILOGIC1_OFB", - "RIOI_ILOGIC1_TFB", - "RIOI_ISIN10", - "RIOI_ISIN11", - "RIOI_ISIN20", - "RIOI_ISIN21", - "RIOI_ISOUT10", - "RIOI_ISOUT11", - "RIOI_ISOUT20", - "RIOI_ISOUT21", - "RIOI_KEEPER_INT_EN_0", - "RIOI_KEEPER_INT_EN_1", - "RIOI_O0", - "RIOI_O1", - "RIOI_ODELAY0_DATAOUT", - "RIOI_ODELAY0_ODATAIN", - "RIOI_ODELAY0_OFDLY0", - "RIOI_ODELAY0_OFDLY1", - "RIOI_ODELAY0_OFDLY2", - "RIOI_ODELAY1_DATAOUT", - "RIOI_ODELAY1_ODATAIN", - "RIOI_ODELAY1_OFDLY0", - "RIOI_ODELAY1_OFDLY1", - "RIOI_ODELAY1_OFDLY2", - "RIOI_OLOGIC0_CLKDIVF", - "RIOI_OLOGIC0_OFB", - "RIOI_OLOGIC0_OQ", - "RIOI_OLOGIC0_TFB", - "RIOI_OLOGIC0_TFB_LOCAL", - "RIOI_OLOGIC0_TQ", - "RIOI_OLOGIC1_CLKDIVF", - "RIOI_OLOGIC1_OFB", - "RIOI_OLOGIC1_OQ", - "RIOI_OLOGIC1_TFB", - "RIOI_OLOGIC1_TFB_LOCAL", - "RIOI_OLOGIC1_TQ", - "RIOI_OSIN10", - "RIOI_OSIN11", - "RIOI_OSIN20", - "RIOI_OSIN21", - "RIOI_OSOUT10", - "RIOI_OSOUT11", - "RIOI_OSOUT20", - "RIOI_OSOUT21", - "RIOI_PD_INT_EN_0", - "RIOI_PD_INT_EN_1", - "RIOI_PU_INT_EN_0", - "RIOI_PU_INT_EN_1", - "RIOI_T0", - "RIOI_T1" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS0_1": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS1_1": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS2_1": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BLOCK_OUTS3_1": null, + "IOI_BYP0_0": null, + "IOI_BYP0_1": null, + "IOI_BYP1_0": null, + "IOI_BYP1_1": null, + "IOI_BYP2_0": null, + "IOI_BYP2_1": null, + "IOI_BYP3_0": null, + "IOI_BYP3_1": null, + "IOI_BYP4_0": null, + "IOI_BYP4_1": null, + "IOI_BYP5_0": null, + "IOI_BYP5_1": null, + "IOI_BYP6_0": null, + "IOI_BYP6_1": null, + "IOI_BYP7_0": null, + "IOI_BYP7_1": null, + "IOI_CLK0_0": null, + "IOI_CLK0_1": null, + "IOI_CLK1_0": null, + "IOI_CLK1_1": null, + "IOI_CTRL0_0": null, + "IOI_CTRL0_1": null, + "IOI_CTRL1_0": null, + "IOI_CTRL1_1": null, + "IOI_DCI_DCIDONE": null, + "IOI_DCI_TSTCLK": null, + "IOI_DCI_TSTHLN": null, + "IOI_DCI_TSTHLP": null, + "IOI_DCI_TSTRST": null, + "IOI_DCI_TSTRST0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A0_1": null, + "IOI_EE2A1_0": null, + "IOI_EE2A1_1": null, + "IOI_EE2A2_0": null, + "IOI_EE2A2_1": null, + "IOI_EE2A3_0": null, + "IOI_EE2A3_1": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG0_1": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG1_1": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG2_1": null, + "IOI_EE2BEG3_0": null, + "IOI_EE2BEG3_1": null, + "IOI_EE4A0_0": null, + "IOI_EE4A0_1": null, + "IOI_EE4A1_0": null, + "IOI_EE4A1_1": null, + "IOI_EE4A2_0": null, + "IOI_EE4A2_1": null, + "IOI_EE4A3_0": null, + "IOI_EE4A3_1": null, + "IOI_EE4B0_0": null, + "IOI_EE4B0_1": null, + "IOI_EE4B1_0": null, + "IOI_EE4B1_1": null, + "IOI_EE4B2_0": null, + "IOI_EE4B2_1": null, + "IOI_EE4B3_0": null, + "IOI_EE4B3_1": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG0_1": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG1_1": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG2_1": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4BEG3_1": null, + "IOI_EE4C0_0": null, + "IOI_EE4C0_1": null, + "IOI_EE4C1_0": null, + "IOI_EE4C1_1": null, + "IOI_EE4C2_0": null, + "IOI_EE4C2_1": null, + "IOI_EE4C3_0": null, + "IOI_EE4C3_1": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG0_1": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG1_1": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG2_1": null, + "IOI_EL1BEG3_0": null, + "IOI_EL1BEG3_1": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG0_1": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG1_1": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG2_1": null, + "IOI_ER1BEG3_0": null, + "IOI_ER1BEG3_1": null, + "IOI_FAN0_0": null, + "IOI_FAN0_1": null, + "IOI_FAN1_0": null, + "IOI_FAN1_1": null, + "IOI_FAN2_0": null, + "IOI_FAN2_1": null, + "IOI_FAN3_0": null, + "IOI_FAN3_1": null, + "IOI_FAN4_0": null, + "IOI_FAN4_1": null, + "IOI_FAN5_0": null, + "IOI_FAN5_1": null, + "IOI_FAN6_0": null, + "IOI_FAN6_1": null, + "IOI_FAN7_0": null, + "IOI_FAN7_1": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_IDELAY1_C": null, + "IOI_IDELAY1_CE": null, + "IOI_IDELAY1_CINVCTRL": null, + "IOI_IDELAY1_CNTVALUEIN0": null, + "IOI_IDELAY1_CNTVALUEIN1": null, + "IOI_IDELAY1_CNTVALUEIN2": null, + "IOI_IDELAY1_CNTVALUEIN3": null, + "IOI_IDELAY1_CNTVALUEIN4": null, + "IOI_IDELAY1_CNTVALUEOUT0": null, + "IOI_IDELAY1_CNTVALUEOUT1": null, + "IOI_IDELAY1_CNTVALUEOUT2": null, + "IOI_IDELAY1_CNTVALUEOUT3": null, + "IOI_IDELAY1_CNTVALUEOUT4": null, + "IOI_IDELAY1_DATAIN": null, + "IOI_IDELAY1_INC": null, + "IOI_IDELAY1_LD": null, + "IOI_IDELAY1_LDPIPEEN": null, + "IOI_IDELAY1_REGRST": null, + "IOI_IDELAYCTRL_DNPULSEOUT": null, + "IOI_IDELAYCTRL_OUTN1": null, + "IOI_IDELAYCTRL_OUTN65": null, + "IOI_IDELAYCTRL_RDY": null, + "IOI_IDELAYCTRL_RST": null, + "IOI_IDELAYCTRL_UPPULSEOUT": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_ILOGIC1_BITSLIP": null, + "IOI_ILOGIC1_CE1": null, + "IOI_ILOGIC1_CE2": null, + "IOI_ILOGIC1_CLK": null, + "IOI_ILOGIC1_CLKB": null, + "IOI_ILOGIC1_CLKDIV": null, + "IOI_ILOGIC1_CLKDIVP": null, + "IOI_ILOGIC1_DYNCLKDIVPSEL": null, + "IOI_ILOGIC1_DYNCLKDIVSEL": null, + "IOI_ILOGIC1_DYNCLKSEL": null, + "IOI_ILOGIC1_O": null, + "IOI_ILOGIC1_OCLK": null, + "IOI_ILOGIC1_OCLKB": null, + "IOI_ILOGIC1_Q1": null, + "IOI_ILOGIC1_Q2": null, + "IOI_ILOGIC1_Q3": null, + "IOI_ILOGIC1_Q4": null, + "IOI_ILOGIC1_Q5": null, + "IOI_ILOGIC1_Q6": null, + "IOI_ILOGIC1_Q7": null, + "IOI_ILOGIC1_Q8": null, + "IOI_ILOGIC1_REV": null, + "IOI_ILOGIC1_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX0_1": null, + "IOI_IMUX10_0": null, + "IOI_IMUX10_1": null, + "IOI_IMUX11_0": null, + "IOI_IMUX11_1": null, + "IOI_IMUX12_0": null, + "IOI_IMUX12_1": null, + "IOI_IMUX13_0": null, + "IOI_IMUX13_1": null, + "IOI_IMUX14_0": null, + "IOI_IMUX14_1": null, + "IOI_IMUX15_0": null, + "IOI_IMUX15_1": null, + "IOI_IMUX16_0": null, + "IOI_IMUX16_1": null, + "IOI_IMUX17_0": null, + "IOI_IMUX17_1": null, + "IOI_IMUX18_0": null, + "IOI_IMUX18_1": null, + "IOI_IMUX19_0": null, + "IOI_IMUX19_1": null, + "IOI_IMUX1_0": null, + "IOI_IMUX1_1": null, + "IOI_IMUX20_0": null, + "IOI_IMUX20_1": null, + "IOI_IMUX21_0": null, + "IOI_IMUX21_1": null, + "IOI_IMUX22_0": null, + "IOI_IMUX22_1": null, + "IOI_IMUX23_0": null, + "IOI_IMUX23_1": null, + "IOI_IMUX24_0": null, + "IOI_IMUX24_1": null, + "IOI_IMUX25_0": null, + "IOI_IMUX25_1": null, + "IOI_IMUX26_0": null, + "IOI_IMUX26_1": null, + "IOI_IMUX27_0": null, + "IOI_IMUX27_1": null, + "IOI_IMUX28_0": null, + "IOI_IMUX28_1": null, + "IOI_IMUX29_0": null, + "IOI_IMUX29_1": null, + "IOI_IMUX2_0": null, + "IOI_IMUX2_1": null, + "IOI_IMUX30_0": null, + "IOI_IMUX30_1": null, + "IOI_IMUX31_0": null, + "IOI_IMUX31_1": null, + "IOI_IMUX32_0": null, + "IOI_IMUX32_1": null, + "IOI_IMUX33_0": null, + "IOI_IMUX33_1": null, + "IOI_IMUX34_0": null, + "IOI_IMUX34_1": null, + "IOI_IMUX35_0": null, + "IOI_IMUX35_1": null, + "IOI_IMUX36_0": null, + "IOI_IMUX36_1": null, + "IOI_IMUX37_0": null, + "IOI_IMUX37_1": null, + "IOI_IMUX38_0": null, + "IOI_IMUX38_1": null, + "IOI_IMUX39_0": null, + "IOI_IMUX39_1": null, + "IOI_IMUX3_0": null, + "IOI_IMUX3_1": null, + "IOI_IMUX40_0": null, + "IOI_IMUX40_1": null, + "IOI_IMUX41_0": null, + "IOI_IMUX41_1": null, + "IOI_IMUX42_0": null, + "IOI_IMUX42_1": null, + "IOI_IMUX43_0": null, + "IOI_IMUX43_1": null, + "IOI_IMUX44_0": null, + "IOI_IMUX44_1": null, + "IOI_IMUX45_0": null, + "IOI_IMUX45_1": null, + "IOI_IMUX46_0": null, + "IOI_IMUX46_1": null, + "IOI_IMUX47_0": null, + "IOI_IMUX47_1": null, + "IOI_IMUX4_0": null, + "IOI_IMUX4_1": null, + "IOI_IMUX5_0": null, + "IOI_IMUX5_1": null, + "IOI_IMUX6_0": null, + "IOI_IMUX6_1": null, + "IOI_IMUX7_0": null, + "IOI_IMUX7_1": null, + "IOI_IMUX8_0": null, + "IOI_IMUX8_1": null, + "IOI_IMUX9_0": null, + "IOI_IMUX9_1": null, + "IOI_IMUX_RC0": null, + "IOI_IMUX_RC1": null, + "IOI_IMUX_RC2": null, + "IOI_IMUX_RC3": null, + "IOI_INT_DCI_EN": null, + "IOI_IOCLK0": null, + "IOI_IOCLK1": null, + "IOI_IOCLK2": null, + "IOI_IOCLK3": null, + "IOI_LEAF_GCLK0": null, + "IOI_LEAF_GCLK1": null, + "IOI_LEAF_GCLK2": null, + "IOI_LEAF_GCLK3": null, + "IOI_LEAF_GCLK4": null, + "IOI_LEAF_GCLK5": null, + "IOI_LH10_0": null, + "IOI_LH10_1": null, + "IOI_LH11_0": null, + "IOI_LH11_1": null, + "IOI_LH12_0": null, + "IOI_LH12_1": null, + "IOI_LH1_0": null, + "IOI_LH1_1": null, + "IOI_LH2_0": null, + "IOI_LH2_1": null, + "IOI_LH3_0": null, + "IOI_LH3_1": null, + "IOI_LH4_0": null, + "IOI_LH4_1": null, + "IOI_LH5_0": null, + "IOI_LH5_1": null, + "IOI_LH6_0": null, + "IOI_LH6_1": null, + "IOI_LH7_0": null, + "IOI_LH7_1": null, + "IOI_LH8_0": null, + "IOI_LH8_1": null, + "IOI_LH9_0": null, + "IOI_LH9_1": null, + "IOI_LOGIC_OUTS0_0": null, + "IOI_LOGIC_OUTS0_1": null, + "IOI_LOGIC_OUTS10_0": null, + "IOI_LOGIC_OUTS10_1": null, + "IOI_LOGIC_OUTS11_0": null, + "IOI_LOGIC_OUTS11_1": null, + "IOI_LOGIC_OUTS12_0": null, + "IOI_LOGIC_OUTS12_1": null, + "IOI_LOGIC_OUTS13_0": null, + "IOI_LOGIC_OUTS13_1": null, + "IOI_LOGIC_OUTS14_0": null, + "IOI_LOGIC_OUTS14_1": null, + "IOI_LOGIC_OUTS15_0": null, + "IOI_LOGIC_OUTS15_1": null, + "IOI_LOGIC_OUTS16_0": null, + "IOI_LOGIC_OUTS16_1": null, + "IOI_LOGIC_OUTS17_0": null, + "IOI_LOGIC_OUTS17_1": null, + "IOI_LOGIC_OUTS18_0": null, + "IOI_LOGIC_OUTS18_1": null, + "IOI_LOGIC_OUTS19_0": null, + "IOI_LOGIC_OUTS19_1": null, + "IOI_LOGIC_OUTS1_0": null, + "IOI_LOGIC_OUTS1_1": null, + "IOI_LOGIC_OUTS20_0": null, + "IOI_LOGIC_OUTS20_1": null, + "IOI_LOGIC_OUTS21_0": null, + "IOI_LOGIC_OUTS21_1": null, + "IOI_LOGIC_OUTS22_0": null, + "IOI_LOGIC_OUTS22_1": null, + "IOI_LOGIC_OUTS23_0": null, + "IOI_LOGIC_OUTS23_1": null, + "IOI_LOGIC_OUTS2_0": null, + "IOI_LOGIC_OUTS2_1": null, + "IOI_LOGIC_OUTS3_0": null, + "IOI_LOGIC_OUTS3_1": null, + "IOI_LOGIC_OUTS4_0": null, + "IOI_LOGIC_OUTS4_1": null, + "IOI_LOGIC_OUTS5_0": null, + "IOI_LOGIC_OUTS5_1": null, + "IOI_LOGIC_OUTS6_0": null, + "IOI_LOGIC_OUTS6_1": null, + "IOI_LOGIC_OUTS7_0": null, + "IOI_LOGIC_OUTS7_1": null, + "IOI_LOGIC_OUTS8_0": null, + "IOI_LOGIC_OUTS8_1": null, + "IOI_LOGIC_OUTS9_0": null, + "IOI_LOGIC_OUTS9_1": null, + "IOI_MONITOR_N": null, + "IOI_MONITOR_P": null, + "IOI_NE2A0_0": null, + "IOI_NE2A0_1": null, + "IOI_NE2A1_0": null, + "IOI_NE2A1_1": null, + "IOI_NE2A2_0": null, + "IOI_NE2A2_1": null, + "IOI_NE2A3_0": null, + "IOI_NE2A3_1": null, + "IOI_NE4BEG0_0": null, + "IOI_NE4BEG0_1": null, + "IOI_NE4BEG1_0": null, + "IOI_NE4BEG1_1": null, + "IOI_NE4BEG2_0": null, + "IOI_NE4BEG2_1": null, + "IOI_NE4BEG3_0": null, + "IOI_NE4BEG3_1": null, + "IOI_NE4C0_0": null, + "IOI_NE4C0_1": null, + "IOI_NE4C1_0": null, + "IOI_NE4C1_1": null, + "IOI_NE4C2_0": null, + "IOI_NE4C2_1": null, + "IOI_NE4C3_0": null, + "IOI_NE4C3_1": null, + "IOI_NW2A0_0": null, + "IOI_NW2A0_1": null, + "IOI_NW2A1_0": null, + "IOI_NW2A1_1": null, + "IOI_NW2A2_0": null, + "IOI_NW2A2_1": null, + "IOI_NW2A3_0": null, + "IOI_NW2A3_1": null, + "IOI_NW4A0_0": null, + "IOI_NW4A0_1": null, + "IOI_NW4A1_0": null, + "IOI_NW4A1_1": null, + "IOI_NW4A2_0": null, + "IOI_NW4A2_1": null, + "IOI_NW4A3_0": null, + "IOI_NW4A3_1": null, + "IOI_NW4END0_0": null, + "IOI_NW4END0_1": null, + "IOI_NW4END1_0": null, + "IOI_NW4END1_1": null, + "IOI_NW4END2_0": null, + "IOI_NW4END2_1": null, + "IOI_NW4END3_0": null, + "IOI_NW4END3_1": null, + "IOI_OCLKM_0": null, + "IOI_OCLKM_1": null, + "IOI_OCLK_0": null, + "IOI_OCLK_1": null, + "IOI_ODELAY0_C": null, + "IOI_ODELAY0_CE": null, + "IOI_ODELAY0_CINVCTRL": null, + "IOI_ODELAY0_CLKIN": null, + "IOI_ODELAY0_CNTVALUEIN0": null, + "IOI_ODELAY0_CNTVALUEIN1": null, + "IOI_ODELAY0_CNTVALUEIN2": null, + "IOI_ODELAY0_CNTVALUEIN3": null, + "IOI_ODELAY0_CNTVALUEIN4": null, + "IOI_ODELAY0_CNTVALUEOUT0": null, + "IOI_ODELAY0_CNTVALUEOUT1": null, + "IOI_ODELAY0_CNTVALUEOUT2": null, + "IOI_ODELAY0_CNTVALUEOUT3": null, + "IOI_ODELAY0_CNTVALUEOUT4": null, + "IOI_ODELAY0_INC": null, + "IOI_ODELAY0_LD": null, + "IOI_ODELAY0_LDPIPEEN": null, + "IOI_ODELAY0_REGRST": null, + "IOI_ODELAY1_C": null, + "IOI_ODELAY1_CE": null, + "IOI_ODELAY1_CINVCTRL": null, + "IOI_ODELAY1_CLKIN": null, + "IOI_ODELAY1_CNTVALUEIN0": null, + "IOI_ODELAY1_CNTVALUEIN1": null, + "IOI_ODELAY1_CNTVALUEIN2": null, + "IOI_ODELAY1_CNTVALUEIN3": null, + "IOI_ODELAY1_CNTVALUEIN4": null, + "IOI_ODELAY1_CNTVALUEOUT0": null, + "IOI_ODELAY1_CNTVALUEOUT1": null, + "IOI_ODELAY1_CNTVALUEOUT2": null, + "IOI_ODELAY1_CNTVALUEOUT3": null, + "IOI_ODELAY1_CNTVALUEOUT4": null, + "IOI_ODELAY1_INC": null, + "IOI_ODELAY1_LD": null, + "IOI_ODELAY1_LDPIPEEN": null, + "IOI_ODELAY1_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_OLOGIC1_CLK": null, + "IOI_OLOGIC1_CLKB": null, + "IOI_OLOGIC1_CLKDIV": null, + "IOI_OLOGIC1_CLKDIVB": null, + "IOI_OLOGIC1_CLKDIVFB": null, + "IOI_OLOGIC1_D1": null, + "IOI_OLOGIC1_D2": null, + "IOI_OLOGIC1_D3": null, + "IOI_OLOGIC1_D4": null, + "IOI_OLOGIC1_D5": null, + "IOI_OLOGIC1_D6": null, + "IOI_OLOGIC1_D7": null, + "IOI_OLOGIC1_D8": null, + "IOI_OLOGIC1_IOCLKGLITCH": null, + "IOI_OLOGIC1_OCE": null, + "IOI_OLOGIC1_REV": null, + "IOI_OLOGIC1_SR": null, + "IOI_OLOGIC1_T1": null, + "IOI_OLOGIC1_T2": null, + "IOI_OLOGIC1_T3": null, + "IOI_OLOGIC1_T4": null, + "IOI_OLOGIC1_TBYTEIN": null, + "IOI_OLOGIC1_TBYTEOUT": null, + "IOI_OLOGIC1_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_ICLKDIV_0": null, + "IOI_PHASER_TO_IO_ICLK_0": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLK1X_90_0": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_PHASER_TO_IO_OCLKDIV_0": null, + "IOI_PHASER_TO_IO_OCLK_0": null, + "IOI_RCLK_DIV_CE0": null, + "IOI_RCLK_DIV_CE1": null, + "IOI_RCLK_DIV_CE2": null, + "IOI_RCLK_DIV_CE2_1": null, + "IOI_RCLK_DIV_CE3": null, + "IOI_RCLK_DIV_CE3_1": null, + "IOI_RCLK_DIV_CLR0": null, + "IOI_RCLK_DIV_CLR0_1": null, + "IOI_RCLK_DIV_CLR1": null, + "IOI_RCLK_DIV_CLR1_1": null, + "IOI_RCLK_DIV_CLR2": null, + "IOI_RCLK_DIV_CLR3": null, + "IOI_RCLK_FORIO0": null, + "IOI_RCLK_FORIO1": null, + "IOI_RCLK_FORIO2": null, + "IOI_RCLK_FORIO3": null, + "IOI_SE2A0_0": null, + "IOI_SE2A0_1": null, + "IOI_SE2A1_0": null, + "IOI_SE2A1_1": null, + "IOI_SE2A2_0": null, + "IOI_SE2A2_1": null, + "IOI_SE2A3_0": null, + "IOI_SE2A3_1": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG0_1": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG1_1": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG2_1": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4BEG3_1": null, + "IOI_SE4C0_0": null, + "IOI_SE4C0_1": null, + "IOI_SE4C1_0": null, + "IOI_SE4C1_1": null, + "IOI_SE4C2_0": null, + "IOI_SE4C2_1": null, + "IOI_SE4C3_0": null, + "IOI_SE4C3_1": null, + "IOI_SW2A0_0": null, + "IOI_SW2A0_1": null, + "IOI_SW2A1_0": null, + "IOI_SW2A1_1": null, + "IOI_SW2A2_0": null, + "IOI_SW2A2_1": null, + "IOI_SW2A3_0": null, + "IOI_SW2A3_1": null, + "IOI_SW4A0_0": null, + "IOI_SW4A0_1": null, + "IOI_SW4A1_0": null, + "IOI_SW4A1_1": null, + "IOI_SW4A2_0": null, + "IOI_SW4A2_1": null, + "IOI_SW4A3_0": null, + "IOI_SW4A3_1": null, + "IOI_SW4END0_0": null, + "IOI_SW4END0_1": null, + "IOI_SW4END1_0": null, + "IOI_SW4END1_1": null, + "IOI_SW4END2_0": null, + "IOI_SW4END2_1": null, + "IOI_SW4END3_0": null, + "IOI_SW4END3_1": null, + "IOI_TBYTEIN": null, + "IOI_WL1END0_0": null, + "IOI_WL1END0_1": null, + "IOI_WL1END1_0": null, + "IOI_WL1END1_1": null, + "IOI_WL1END2_0": null, + "IOI_WL1END2_1": null, + "IOI_WL1END3_0": null, + "IOI_WL1END3_1": null, + "IOI_WR1END0_0": null, + "IOI_WR1END0_1": null, + "IOI_WR1END1_0": null, + "IOI_WR1END1_1": null, + "IOI_WR1END2_0": null, + "IOI_WR1END2_1": null, + "IOI_WR1END3_0": null, + "IOI_WR1END3_1": null, + "IOI_WW2A0_0": null, + "IOI_WW2A0_1": null, + "IOI_WW2A1_0": null, + "IOI_WW2A1_1": null, + "IOI_WW2A2_0": null, + "IOI_WW2A2_1": null, + "IOI_WW2A3_0": null, + "IOI_WW2A3_1": null, + "IOI_WW2END0_0": null, + "IOI_WW2END0_1": null, + "IOI_WW2END1_0": null, + "IOI_WW2END1_1": null, + "IOI_WW2END2_0": null, + "IOI_WW2END2_1": null, + "IOI_WW2END3_0": null, + "IOI_WW2END3_1": null, + "IOI_WW4A0_0": null, + "IOI_WW4A0_1": null, + "IOI_WW4A1_0": null, + "IOI_WW4A1_1": null, + "IOI_WW4A2_0": null, + "IOI_WW4A2_1": null, + "IOI_WW4A3_0": null, + "IOI_WW4A3_1": null, + "IOI_WW4B0_0": null, + "IOI_WW4B0_1": null, + "IOI_WW4B1_0": null, + "IOI_WW4B1_1": null, + "IOI_WW4B2_0": null, + "IOI_WW4B2_1": null, + "IOI_WW4B3_0": null, + "IOI_WW4B3_1": null, + "IOI_WW4C0_0": null, + "IOI_WW4C0_1": null, + "IOI_WW4C1_0": null, + "IOI_WW4C1_1": null, + "IOI_WW4C2_0": null, + "IOI_WW4C2_1": null, + "IOI_WW4C3_0": null, + "IOI_WW4C3_1": null, + "IOI_WW4END0_0": null, + "IOI_WW4END0_1": null, + "IOI_WW4END1_0": null, + "IOI_WW4END1_1": null, + "IOI_WW4END2_0": null, + "IOI_WW4END2_1": null, + "IOI_WW4END3_0": null, + "IOI_WW4END3_1": null, + "RIOI_DCI_T_TERM0": null, + "RIOI_DCI_T_TERM1": null, + "RIOI_DIFF_TERM_INT_EN": null, + "RIOI_I0": null, + "RIOI_I1": null, + "RIOI_I2GCLK_BOT1": null, + "RIOI_I2GCLK_TOP0": null, + "RIOI_I2GCLK_TOP1": null, + "RIOI_IBUF0": null, + "RIOI_IBUF1": null, + "RIOI_IBUF_DISABLE0": null, + "RIOI_IBUF_DISABLE1": null, + "RIOI_IDELAY0_DATAOUT": null, + "RIOI_IDELAY0_IDATAIN": null, + "RIOI_IDELAY0_IFDLY0": null, + "RIOI_IDELAY0_IFDLY1": null, + "RIOI_IDELAY0_IFDLY2": null, + "RIOI_IDELAY1_DATAOUT": null, + "RIOI_IDELAY1_IDATAIN": null, + "RIOI_IDELAY1_IFDLY0": null, + "RIOI_IDELAY1_IFDLY1": null, + "RIOI_IDELAY1_IFDLY2": null, + "RIOI_ILOGIC0_D": null, + "RIOI_ILOGIC0_DDLY": null, + "RIOI_ILOGIC0_OFB": null, + "RIOI_ILOGIC0_TFB": null, + "RIOI_ILOGIC1_D": null, + "RIOI_ILOGIC1_DDLY": null, + "RIOI_ILOGIC1_OFB": null, + "RIOI_ILOGIC1_TFB": null, + "RIOI_ISIN10": null, + "RIOI_ISIN11": null, + "RIOI_ISIN20": null, + "RIOI_ISIN21": null, + "RIOI_ISOUT10": null, + "RIOI_ISOUT11": null, + "RIOI_ISOUT20": null, + "RIOI_ISOUT21": null, + "RIOI_KEEPER_INT_EN_0": null, + "RIOI_KEEPER_INT_EN_1": null, + "RIOI_O0": null, + "RIOI_O1": null, + "RIOI_ODELAY0_DATAOUT": null, + "RIOI_ODELAY0_ODATAIN": null, + "RIOI_ODELAY0_OFDLY0": null, + "RIOI_ODELAY0_OFDLY1": null, + "RIOI_ODELAY0_OFDLY2": null, + "RIOI_ODELAY1_DATAOUT": null, + "RIOI_ODELAY1_ODATAIN": null, + "RIOI_ODELAY1_OFDLY0": null, + "RIOI_ODELAY1_OFDLY1": null, + "RIOI_ODELAY1_OFDLY2": null, + "RIOI_OLOGIC0_CLKDIVF": null, + "RIOI_OLOGIC0_OFB": null, + "RIOI_OLOGIC0_OQ": null, + "RIOI_OLOGIC0_TFB": null, + "RIOI_OLOGIC0_TFB_LOCAL": null, + "RIOI_OLOGIC0_TQ": null, + "RIOI_OLOGIC1_CLKDIVF": null, + "RIOI_OLOGIC1_OFB": null, + "RIOI_OLOGIC1_OQ": null, + "RIOI_OLOGIC1_TFB": null, + "RIOI_OLOGIC1_TFB_LOCAL": null, + "RIOI_OLOGIC1_TQ": null, + "RIOI_OSIN10": null, + "RIOI_OSIN11": null, + "RIOI_OSIN20": null, + "RIOI_OSIN21": null, + "RIOI_OSOUT10": null, + "RIOI_OSOUT11": null, + "RIOI_OSOUT20": null, + "RIOI_OSOUT21": null, + "RIOI_PD_INT_EN_0": null, + "RIOI_PD_INT_EN_1": null, + "RIOI_PU_INT_EN_0": null, + "RIOI_PU_INT_EN_1": null, + "RIOI_T0": null, + "RIOI_T1": null + } } diff --git a/kintex7/tile_type_RIOI_SING.json b/kintex7/tile_type_RIOI_SING.json index 5879c17..210cdf7 100644 --- a/kintex7/tile_type_RIOI_SING.json +++ b/kintex7/tile_type_RIOI_SING.json @@ -2,1556 +2,5268 @@ "pips": { "RIOI_SING.IOI_BYP0_0->RIOI_ODELAY0_OFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP0_0" }, "RIOI_SING.IOI_BYP1_0->RIOI_ODELAY0_OFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP1_0" }, "RIOI_SING.IOI_BYP2_0->IOI_ODELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP2_0" }, "RIOI_SING.IOI_BYP5_0->RIOI_ODELAY0_OFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP5_0" }, "RIOI_SING.IOI_BYP6_0->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "RIOI_SING.IOI_BYP7_0->RIOI_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "RIOI_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI_SING.IOI_CLK0_0->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI_SING.IOI_CLK1_0->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI_SING.IOI_CLK1_0->IOI_ODELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI_SING.IOI_CTRL0_0->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "RIOI_SING.IOI_CTRL1_0->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "RIOI_SING.IOI_FAN4_0->RIOI_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "RIOI_SING.IOI_FAN5_0->RIOI_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "RIOI_SING.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "RIOI_SING.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI_SING.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "RIOI_SING.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "RIOI_SING.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "RIOI_SING.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "RIOI_SING.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "RIOI_SING.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "RIOI_SING.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "RIOI_SING.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "RIOI_SING.IOI_IMUX0_0->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "RIOI_SING.IOI_IMUX10_0->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "RIOI_SING.IOI_IMUX11_0->IOI_ODELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX11_0" }, "RIOI_SING.IOI_IMUX12_0->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "RIOI_SING.IOI_IMUX13_0->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "RIOI_SING.IOI_IMUX14_0->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "RIOI_SING.IOI_IMUX15_0->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "RIOI_SING.IOI_IMUX16_0->IOI_ODELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX16_0" }, "RIOI_SING.IOI_IMUX17_0->IOI_ODELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX17_0" }, "RIOI_SING.IOI_IMUX18_0->IOI_ODELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX18_0" }, "RIOI_SING.IOI_IMUX19_0->IOI_ODELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX19_0" }, "RIOI_SING.IOI_IMUX1_0->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "RIOI_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI_SING.IOI_IMUX20_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI_SING.IOI_IMUX21_0->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "RIOI_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI_SING.IOI_IMUX22_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI_SING.IOI_IMUX23_0->IOI_ODELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX23_0" }, "RIOI_SING.IOI_IMUX25_0->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "RIOI_SING.IOI_IMUX26_0->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "RIOI_SING.IOI_IMUX27_0->IOI_ODELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX27_0" }, "RIOI_SING.IOI_IMUX28_0->IOI_ODELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX28_0" }, "RIOI_SING.IOI_IMUX29_0->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "RIOI_SING.IOI_IMUX2_0->IOI_ODELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX2_0" }, "RIOI_SING.IOI_IMUX30_0->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "RIOI_SING.IOI_IMUX31_0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI_SING.IOI_IMUX31_0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI_SING.IOI_IMUX32_0->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "RIOI_SING.IOI_IMUX33_0->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "RIOI_SING.IOI_IMUX34_0->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "RIOI_SING.IOI_IMUX35_0->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "RIOI_SING.IOI_IMUX36_0->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "RIOI_SING.IOI_IMUX37_0->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "RIOI_SING.IOI_IMUX38_0->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "RIOI_SING.IOI_IMUX39_0->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "RIOI_SING.IOI_IMUX3_0->IOI_ODELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX3_0" }, "RIOI_SING.IOI_IMUX40_0->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "RIOI_SING.IOI_IMUX41_0->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "RIOI_SING.IOI_IMUX42_0->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "RIOI_SING.IOI_IMUX43_0->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "RIOI_SING.IOI_IMUX44_0->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "RIOI_SING.IOI_IMUX45_0->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "RIOI_SING.IOI_IMUX46_0->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "RIOI_SING.IOI_IMUX47_0->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "RIOI_SING.IOI_IMUX4_0->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "RIOI_SING.IOI_IMUX5_0->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "RIOI_SING.IOI_IMUX6_0->RIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "RIOI_SING.IOI_IMUX7_0->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "RIOI_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_SING.IOI_IMUX8_0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_SING.IOI_IMUX8_0->IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_SING.IOI_IMUX8_0->RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_SING.IOI_IMUX9_0->RIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "RIOI_SING.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI_SING.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_SING.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_SING.IOI_OCLK_0->IOI_ODELAY0_CLKIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CLKIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_SING.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_SING.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT0" }, "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT1" }, "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT2" }, "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT3" }, "RIOI_SING.IOI_ODELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT4" }, "RIOI_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI_SING.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI_SING.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" }, "RIOI_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI_SING.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI_SING.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI_SING.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "RIOI_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI_SING.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI_SING.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI_SING.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90" }, "RIOI_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "RIOI_SING.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" }, "RIOI_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "RIOI_SING.IOI_SING_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "RIOI_SING.IOI_SING_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "RIOI_SING.IOI_SING_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK0" }, "RIOI_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "RIOI_SING.IOI_SING_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "RIOI_SING.IOI_SING_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "RIOI_SING.IOI_SING_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK1" }, "RIOI_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "RIOI_SING.IOI_SING_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "RIOI_SING.IOI_SING_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "RIOI_SING.IOI_SING_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK2" }, "RIOI_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "RIOI_SING.IOI_SING_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "RIOI_SING.IOI_SING_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "RIOI_SING.IOI_SING_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_IOCLK3" }, "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI_SING.IOI_SING_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI_SING.IOI_SING_LEAF_GCLK0->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK0" }, "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI_SING.IOI_SING_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI_SING.IOI_SING_LEAF_GCLK1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK1" }, "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI_SING.IOI_SING_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI_SING.IOI_SING_LEAF_GCLK2->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK2" }, "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI_SING.IOI_SING_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI_SING.IOI_SING_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK3" }, "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI_SING.IOI_SING_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI_SING.IOI_SING_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK4" }, "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI_SING.IOI_SING_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI_SING.IOI_SING_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_LEAF_GCLK5" }, "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "RIOI_SING.IOI_SING_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "RIOI_SING.IOI_SING_RCLK_FORIO0->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO0" }, "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "RIOI_SING.IOI_SING_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "RIOI_SING.IOI_SING_RCLK_FORIO1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO1" }, "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI_SING.IOI_SING_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI_SING.IOI_SING_RCLK_FORIO2->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO2" }, "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI_SING.IOI_SING_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI_SING.IOI_SING_RCLK_FORIO3->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_RCLK_FORIO3" }, "RIOI_SING.IOI_SING_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_SING_TBYTEIN" }, "RIOI_SING.RIOI_I0->RIOI_IDELAY0_IDATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IDATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_I0" }, "RIOI_SING.RIOI_I0->RIOI_ILOGIC0_D": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_D", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_I0" }, "RIOI_SING.RIOI_IBUF0->RIOI_I0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IBUF0" }, "RIOI_SING.RIOI_IDELAY0_DATAOUT->RIOI_ILOGIC0_DDLY": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_DDLY", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_IDELAY0_DATAOUT" }, "RIOI_SING.RIOI_IDELAY0_IDATAIN->>RIOI_IDELAY0_DATAOUT": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.264", + "0.331", + "0.575", + "0.666" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_IDELAY0_DATAOUT", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.264", + "0.331", + "0.575", + "0.666" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_IDELAY0_IDATAIN" }, "RIOI_SING.RIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.050", + "0.058", + "0.084", + "0.096" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC0_D" }, "RIOI_SING.RIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC0_DDLY" }, "RIOI_SING.RIOI_ODELAY0_DATAOUT->RIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_O0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ODELAY0_DATAOUT" }, "RIOI_SING.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_OFB" }, "RIOI_SING.RIOI_OLOGIC0_OFB->RIOI_ODELAY0_ODATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_ODATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_OFB" }, "RIOI_SING.RIOI_OLOGIC0_OQ->>RIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI_SING.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI_SING.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB" }, "RIOI_SING.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI_SING.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI_SING.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI_SING.RIOI_OLOGIC0_TQ->>RIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" } }, @@ -1560,39 +5272,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "RIOI_OLOGIC0_OFB", - "OQ": "RIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_OSOUT10", - "SHIFTOUT2": "RIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "RIOI_OLOGIC0_TFB", - "TQ": "RIOI_OLOGIC0_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE2", "x_coord": 0, @@ -1602,29 +5584,236 @@ "name": "X0Y0", "prefix": "ODELAY", "site_pins": { - "C": "IOI_ODELAY0_C", - "CE": "IOI_ODELAY0_CE", - "CINVCTRL": "IOI_ODELAY0_CINVCTRL", - "CLKIN": "IOI_ODELAY0_CLKIN", - "CNTVALUEIN0": "IOI_ODELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_ODELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_ODELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_ODELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_ODELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_ODELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_ODELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_ODELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_ODELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_ODELAY0_CNTVALUEOUT4", - "DATAOUT": "RIOI_ODELAY0_DATAOUT", - "INC": "IOI_ODELAY0_INC", - "LD": "IOI_ODELAY0_LD", - "LDPIPEEN": "IOI_ODELAY0_LDPIPEEN", - "ODATAIN": "RIOI_ODELAY0_ODATAIN", - "OFDLY0": "RIOI_ODELAY0_OFDLY0", - "OFDLY1": "RIOI_ODELAY0_OFDLY1", - "OFDLY2": "RIOI_ODELAY0_OFDLY2", - "REGRST": "IOI_ODELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CINVCTRL" + }, + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CLKIN" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT4" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_ODELAY0_DATAOUT" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_LDPIPEEN" + }, + "ODATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_ODATAIN" + }, + "OFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY0" + }, + "OFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY1" + }, + "OFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY2" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_REGRST" + } }, "type": "ODELAYE2", "x_coord": 0, @@ -1634,37 +5823,289 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "RIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "RIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE2", "x_coord": 0, @@ -1674,29 +6115,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "IFDLY0": "RIOI_IDELAY0_IFDLY0", - "IFDLY1": "RIOI_IDELAY0_IFDLY1", - "IFDLY2": "RIOI_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2_FINEDELAY", "x_coord": 0, @@ -1704,368 +6352,368 @@ } ], "tile_type": "RIOI_SING", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS3_0", - "IOI_BYP0_0", - "IOI_BYP1_0", - "IOI_BYP2_0", - "IOI_BYP3_0", - "IOI_BYP4_0", - "IOI_BYP5_0", - "IOI_BYP6_0", - "IOI_BYP7_0", - "IOI_CLK0_0", - "IOI_CLK1_0", - "IOI_CTRL0_0", - "IOI_CTRL1_0", - "IOI_EE2A0_0", - "IOI_EE2A1_0", - "IOI_EE2A2_0", - "IOI_EE2A3_0", - "IOI_EE2BEG0_0", - "IOI_EE2BEG1_0", - "IOI_EE2BEG2_0", - "IOI_EE2BEG3_0", - "IOI_EE4A0_0", - "IOI_EE4A1_0", - "IOI_EE4A2_0", - "IOI_EE4A3_0", - "IOI_EE4B0_0", - "IOI_EE4B1_0", - "IOI_EE4B2_0", - "IOI_EE4B3_0", - "IOI_EE4BEG0_0", - "IOI_EE4BEG1_0", - "IOI_EE4BEG2_0", - "IOI_EE4BEG3_0", - "IOI_EE4C0_0", - "IOI_EE4C1_0", - "IOI_EE4C2_0", - "IOI_EE4C3_0", - "IOI_EL1BEG0_0", - "IOI_EL1BEG1_0", - "IOI_EL1BEG2_0", - "IOI_EL1BEG3_0", - "IOI_ER1BEG0_0", - "IOI_ER1BEG1_0", - "IOI_ER1BEG2_0", - "IOI_ER1BEG3_0", - "IOI_FAN0_0", - "IOI_FAN1_0", - "IOI_FAN2_0", - "IOI_FAN3_0", - "IOI_FAN4_0", - "IOI_FAN5_0", - "IOI_FAN6_0", - "IOI_FAN7_0", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_IMUX0_0", - "IOI_IMUX10_0", - "IOI_IMUX11_0", - "IOI_IMUX12_0", - "IOI_IMUX13_0", - "IOI_IMUX14_0", - "IOI_IMUX15_0", - "IOI_IMUX16_0", - "IOI_IMUX17_0", - "IOI_IMUX18_0", - "IOI_IMUX19_0", - "IOI_IMUX1_0", - "IOI_IMUX20_0", - "IOI_IMUX21_0", - "IOI_IMUX22_0", - "IOI_IMUX23_0", - "IOI_IMUX24_0", - "IOI_IMUX25_0", - "IOI_IMUX26_0", - "IOI_IMUX27_0", - "IOI_IMUX28_0", - "IOI_IMUX29_0", - "IOI_IMUX2_0", - "IOI_IMUX30_0", - "IOI_IMUX31_0", - "IOI_IMUX32_0", - "IOI_IMUX33_0", - "IOI_IMUX34_0", - "IOI_IMUX35_0", - "IOI_IMUX36_0", - "IOI_IMUX37_0", - "IOI_IMUX38_0", - "IOI_IMUX39_0", - "IOI_IMUX3_0", - "IOI_IMUX40_0", - "IOI_IMUX41_0", - "IOI_IMUX42_0", - "IOI_IMUX43_0", - "IOI_IMUX44_0", - "IOI_IMUX45_0", - "IOI_IMUX46_0", - "IOI_IMUX47_0", - "IOI_IMUX4_0", - "IOI_IMUX5_0", - "IOI_IMUX6_0", - "IOI_IMUX7_0", - "IOI_IMUX8_0", - "IOI_IMUX9_0", - "IOI_LH10_0", - "IOI_LH11_0", - "IOI_LH12_0", - "IOI_LH1_0", - "IOI_LH2_0", - "IOI_LH3_0", - "IOI_LH4_0", - "IOI_LH5_0", - "IOI_LH6_0", - "IOI_LH7_0", - "IOI_LH8_0", - "IOI_LH9_0", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS9_0", - "IOI_NE2A0_0", - "IOI_NE2A1_0", - "IOI_NE2A2_0", - "IOI_NE2A3_0", - "IOI_NE4BEG0_0", - "IOI_NE4BEG1_0", - "IOI_NE4BEG2_0", - "IOI_NE4BEG3_0", - "IOI_NE4C0_0", - "IOI_NE4C1_0", - "IOI_NE4C2_0", - "IOI_NE4C3_0", - "IOI_NW2A0_0", - "IOI_NW2A1_0", - "IOI_NW2A2_0", - "IOI_NW2A3_0", - "IOI_NW4A0_0", - "IOI_NW4A1_0", - "IOI_NW4A2_0", - "IOI_NW4A3_0", - "IOI_NW4END0_0", - "IOI_NW4END1_0", - "IOI_NW4END2_0", - "IOI_NW4END3_0", - "IOI_OCLKM_0", - "IOI_OCLK_0", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_SE2A0_0", - "IOI_SE2A1_0", - "IOI_SE2A2_0", - "IOI_SE2A3_0", - "IOI_SE4BEG0_0", - "IOI_SE4BEG1_0", - "IOI_SE4BEG2_0", - "IOI_SE4BEG3_0", - "IOI_SE4C0_0", - "IOI_SE4C1_0", - "IOI_SE4C2_0", - "IOI_SE4C3_0", - "IOI_SING_IOCLK0", - "IOI_SING_IOCLK1", - "IOI_SING_IOCLK2", - "IOI_SING_IOCLK3", - "IOI_SING_LEAF_GCLK0", - "IOI_SING_LEAF_GCLK1", - "IOI_SING_LEAF_GCLK2", - "IOI_SING_LEAF_GCLK3", - "IOI_SING_LEAF_GCLK4", - "IOI_SING_LEAF_GCLK5", - "IOI_SING_RCLK_FORIO0", - "IOI_SING_RCLK_FORIO1", - "IOI_SING_RCLK_FORIO2", - "IOI_SING_RCLK_FORIO3", - "IOI_SING_TBYTEIN", - "IOI_SW2A0_0", - "IOI_SW2A1_0", - "IOI_SW2A2_0", - "IOI_SW2A3_0", - "IOI_SW4A0_0", - "IOI_SW4A1_0", - "IOI_SW4A2_0", - "IOI_SW4A3_0", - "IOI_SW4END0_0", - "IOI_SW4END1_0", - "IOI_SW4END2_0", - "IOI_SW4END3_0", - "IOI_WL1END0_0", - "IOI_WL1END1_0", - "IOI_WL1END2_0", - "IOI_WL1END3_0", - "IOI_WR1END0_0", - "IOI_WR1END1_0", - "IOI_WR1END2_0", - "IOI_WR1END3_0", - "IOI_WW2A0_0", - "IOI_WW2A1_0", - "IOI_WW2A2_0", - "IOI_WW2A3_0", - "IOI_WW2END0_0", - "IOI_WW2END1_0", - "IOI_WW2END2_0", - "IOI_WW2END3_0", - "IOI_WW4A0_0", - "IOI_WW4A1_0", - "IOI_WW4A2_0", - "IOI_WW4A3_0", - "IOI_WW4B0_0", - "IOI_WW4B1_0", - "IOI_WW4B2_0", - "IOI_WW4B3_0", - "IOI_WW4C0_0", - "IOI_WW4C1_0", - "IOI_WW4C2_0", - "IOI_WW4C3_0", - "IOI_WW4END0_0", - "IOI_WW4END1_0", - "IOI_WW4END2_0", - "IOI_WW4END3_0", - "RIOI_DCI_T_TERM0", - "RIOI_I0", - "RIOI_IBUF0", - "RIOI_IBUF_DISABLE0", - "RIOI_IDELAY0_DATAOUT", - "RIOI_IDELAY0_IDATAIN", - "RIOI_IDELAY0_IFDLY0", - "RIOI_IDELAY0_IFDLY1", - "RIOI_IDELAY0_IFDLY2", - "RIOI_ILOGIC0_D", - "RIOI_ILOGIC0_DDLY", - "RIOI_ILOGIC0_OFB", - "RIOI_ILOGIC0_TFB", - "RIOI_ISIN10", - "RIOI_ISIN20", - "RIOI_ISOUT10", - "RIOI_ISOUT20", - "RIOI_KEEPER_INT_EN_1", - "RIOI_O0", - "RIOI_ODELAY0_DATAOUT", - "RIOI_ODELAY0_ODATAIN", - "RIOI_ODELAY0_OFDLY0", - "RIOI_ODELAY0_OFDLY1", - "RIOI_ODELAY0_OFDLY2", - "RIOI_OLOGIC0_CLKDIVF", - "RIOI_OLOGIC0_OFB", - "RIOI_OLOGIC0_OQ", - "RIOI_OLOGIC0_TFB", - "RIOI_OLOGIC0_TFB_LOCAL", - "RIOI_OLOGIC0_TQ", - "RIOI_OSIN10", - "RIOI_OSIN20", - "RIOI_OSOUT10", - "RIOI_OSOUT20", - "RIOI_PD_INT_EN_1", - "RIOI_PU_INT_EN_1", - "RIOI_T0" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BYP0_0": null, + "IOI_BYP1_0": null, + "IOI_BYP2_0": null, + "IOI_BYP3_0": null, + "IOI_BYP4_0": null, + "IOI_BYP5_0": null, + "IOI_BYP6_0": null, + "IOI_BYP7_0": null, + "IOI_CLK0_0": null, + "IOI_CLK1_0": null, + "IOI_CTRL0_0": null, + "IOI_CTRL1_0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A1_0": null, + "IOI_EE2A2_0": null, + "IOI_EE2A3_0": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG3_0": null, + "IOI_EE4A0_0": null, + "IOI_EE4A1_0": null, + "IOI_EE4A2_0": null, + "IOI_EE4A3_0": null, + "IOI_EE4B0_0": null, + "IOI_EE4B1_0": null, + "IOI_EE4B2_0": null, + "IOI_EE4B3_0": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4C0_0": null, + "IOI_EE4C1_0": null, + "IOI_EE4C2_0": null, + "IOI_EE4C3_0": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG3_0": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG3_0": null, + "IOI_FAN0_0": null, + "IOI_FAN1_0": null, + "IOI_FAN2_0": null, + "IOI_FAN3_0": null, + "IOI_FAN4_0": null, + "IOI_FAN5_0": null, + "IOI_FAN6_0": null, + "IOI_FAN7_0": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX10_0": null, + "IOI_IMUX11_0": null, + "IOI_IMUX12_0": null, + "IOI_IMUX13_0": null, + "IOI_IMUX14_0": null, + "IOI_IMUX15_0": null, + "IOI_IMUX16_0": null, + "IOI_IMUX17_0": null, + "IOI_IMUX18_0": null, + "IOI_IMUX19_0": null, + "IOI_IMUX1_0": null, + "IOI_IMUX20_0": null, + "IOI_IMUX21_0": null, + "IOI_IMUX22_0": null, + "IOI_IMUX23_0": null, + "IOI_IMUX24_0": null, + "IOI_IMUX25_0": null, + "IOI_IMUX26_0": null, + "IOI_IMUX27_0": null, + "IOI_IMUX28_0": null, + "IOI_IMUX29_0": null, + "IOI_IMUX2_0": null, + "IOI_IMUX30_0": null, + "IOI_IMUX31_0": null, + "IOI_IMUX32_0": null, + "IOI_IMUX33_0": null, + "IOI_IMUX34_0": null, + "IOI_IMUX35_0": null, + "IOI_IMUX36_0": null, + "IOI_IMUX37_0": null, + "IOI_IMUX38_0": null, + "IOI_IMUX39_0": null, + "IOI_IMUX3_0": null, + "IOI_IMUX40_0": null, + "IOI_IMUX41_0": null, + "IOI_IMUX42_0": null, + "IOI_IMUX43_0": null, + "IOI_IMUX44_0": null, + "IOI_IMUX45_0": null, + "IOI_IMUX46_0": null, + "IOI_IMUX47_0": null, + "IOI_IMUX4_0": null, + "IOI_IMUX5_0": null, + "IOI_IMUX6_0": null, + "IOI_IMUX7_0": null, + "IOI_IMUX8_0": null, + "IOI_IMUX9_0": null, + "IOI_LH10_0": null, + "IOI_LH11_0": null, + "IOI_LH12_0": null, + "IOI_LH1_0": null, + "IOI_LH2_0": null, + "IOI_LH3_0": null, + "IOI_LH4_0": null, + "IOI_LH5_0": null, + "IOI_LH6_0": null, + "IOI_LH7_0": null, + "IOI_LH8_0": null, + "IOI_LH9_0": null, + "IOI_LOGIC_OUTS0_0": null, + "IOI_LOGIC_OUTS10_0": null, + "IOI_LOGIC_OUTS11_0": null, + "IOI_LOGIC_OUTS12_0": null, + "IOI_LOGIC_OUTS13_0": null, + "IOI_LOGIC_OUTS14_0": null, + "IOI_LOGIC_OUTS15_0": null, + "IOI_LOGIC_OUTS16_0": null, + "IOI_LOGIC_OUTS17_0": null, + "IOI_LOGIC_OUTS18_0": null, + "IOI_LOGIC_OUTS19_0": null, + "IOI_LOGIC_OUTS1_0": null, + "IOI_LOGIC_OUTS20_0": null, + "IOI_LOGIC_OUTS21_0": null, + "IOI_LOGIC_OUTS22_0": null, + "IOI_LOGIC_OUTS23_0": null, + "IOI_LOGIC_OUTS2_0": null, + "IOI_LOGIC_OUTS3_0": null, + "IOI_LOGIC_OUTS4_0": null, + "IOI_LOGIC_OUTS5_0": null, + "IOI_LOGIC_OUTS6_0": null, + "IOI_LOGIC_OUTS7_0": null, + "IOI_LOGIC_OUTS8_0": null, + "IOI_LOGIC_OUTS9_0": null, + "IOI_NE2A0_0": null, + "IOI_NE2A1_0": null, + "IOI_NE2A2_0": null, + "IOI_NE2A3_0": null, + "IOI_NE4BEG0_0": null, + "IOI_NE4BEG1_0": null, + "IOI_NE4BEG2_0": null, + "IOI_NE4BEG3_0": null, + "IOI_NE4C0_0": null, + "IOI_NE4C1_0": null, + "IOI_NE4C2_0": null, + "IOI_NE4C3_0": null, + "IOI_NW2A0_0": null, + "IOI_NW2A1_0": null, + "IOI_NW2A2_0": null, + "IOI_NW2A3_0": null, + "IOI_NW4A0_0": null, + "IOI_NW4A1_0": null, + "IOI_NW4A2_0": null, + "IOI_NW4A3_0": null, + "IOI_NW4END0_0": null, + "IOI_NW4END1_0": null, + "IOI_NW4END2_0": null, + "IOI_NW4END3_0": null, + "IOI_OCLKM_0": null, + "IOI_OCLK_0": null, + "IOI_ODELAY0_C": null, + "IOI_ODELAY0_CE": null, + "IOI_ODELAY0_CINVCTRL": null, + "IOI_ODELAY0_CLKIN": null, + "IOI_ODELAY0_CNTVALUEIN0": null, + "IOI_ODELAY0_CNTVALUEIN1": null, + "IOI_ODELAY0_CNTVALUEIN2": null, + "IOI_ODELAY0_CNTVALUEIN3": null, + "IOI_ODELAY0_CNTVALUEIN4": null, + "IOI_ODELAY0_CNTVALUEOUT0": null, + "IOI_ODELAY0_CNTVALUEOUT1": null, + "IOI_ODELAY0_CNTVALUEOUT2": null, + "IOI_ODELAY0_CNTVALUEOUT3": null, + "IOI_ODELAY0_CNTVALUEOUT4": null, + "IOI_ODELAY0_INC": null, + "IOI_ODELAY0_LD": null, + "IOI_ODELAY0_LDPIPEEN": null, + "IOI_ODELAY0_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_SE2A0_0": null, + "IOI_SE2A1_0": null, + "IOI_SE2A2_0": null, + "IOI_SE2A3_0": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4C0_0": null, + "IOI_SE4C1_0": null, + "IOI_SE4C2_0": null, + "IOI_SE4C3_0": null, + "IOI_SING_IOCLK0": null, + "IOI_SING_IOCLK1": null, + "IOI_SING_IOCLK2": null, + "IOI_SING_IOCLK3": null, + "IOI_SING_LEAF_GCLK0": null, + "IOI_SING_LEAF_GCLK1": null, + "IOI_SING_LEAF_GCLK2": null, + "IOI_SING_LEAF_GCLK3": null, + "IOI_SING_LEAF_GCLK4": null, + "IOI_SING_LEAF_GCLK5": null, + "IOI_SING_RCLK_FORIO0": null, + "IOI_SING_RCLK_FORIO1": null, + "IOI_SING_RCLK_FORIO2": null, + "IOI_SING_RCLK_FORIO3": null, + "IOI_SING_TBYTEIN": null, + "IOI_SW2A0_0": null, + "IOI_SW2A1_0": null, + "IOI_SW2A2_0": null, + "IOI_SW2A3_0": null, + "IOI_SW4A0_0": null, + "IOI_SW4A1_0": null, + "IOI_SW4A2_0": null, + "IOI_SW4A3_0": null, + "IOI_SW4END0_0": null, + "IOI_SW4END1_0": null, + "IOI_SW4END2_0": null, + "IOI_SW4END3_0": null, + "IOI_WL1END0_0": null, + "IOI_WL1END1_0": null, + "IOI_WL1END2_0": null, + "IOI_WL1END3_0": null, + "IOI_WR1END0_0": null, + "IOI_WR1END1_0": null, + "IOI_WR1END2_0": null, + "IOI_WR1END3_0": null, + "IOI_WW2A0_0": null, + "IOI_WW2A1_0": null, + "IOI_WW2A2_0": null, + "IOI_WW2A3_0": null, + "IOI_WW2END0_0": null, + "IOI_WW2END1_0": null, + "IOI_WW2END2_0": null, + "IOI_WW2END3_0": null, + "IOI_WW4A0_0": null, + "IOI_WW4A1_0": null, + "IOI_WW4A2_0": null, + "IOI_WW4A3_0": null, + "IOI_WW4B0_0": null, + "IOI_WW4B1_0": null, + "IOI_WW4B2_0": null, + "IOI_WW4B3_0": null, + "IOI_WW4C0_0": null, + "IOI_WW4C1_0": null, + "IOI_WW4C2_0": null, + "IOI_WW4C3_0": null, + "IOI_WW4END0_0": null, + "IOI_WW4END1_0": null, + "IOI_WW4END2_0": null, + "IOI_WW4END3_0": null, + "RIOI_DCI_T_TERM0": null, + "RIOI_I0": null, + "RIOI_IBUF0": null, + "RIOI_IBUF_DISABLE0": null, + "RIOI_IDELAY0_DATAOUT": null, + "RIOI_IDELAY0_IDATAIN": null, + "RIOI_IDELAY0_IFDLY0": null, + "RIOI_IDELAY0_IFDLY1": null, + "RIOI_IDELAY0_IFDLY2": null, + "RIOI_ILOGIC0_D": null, + "RIOI_ILOGIC0_DDLY": null, + "RIOI_ILOGIC0_OFB": null, + "RIOI_ILOGIC0_TFB": null, + "RIOI_ISIN10": null, + "RIOI_ISIN20": null, + "RIOI_ISOUT10": null, + "RIOI_ISOUT20": null, + "RIOI_KEEPER_INT_EN_1": null, + "RIOI_O0": null, + "RIOI_ODELAY0_DATAOUT": null, + "RIOI_ODELAY0_ODATAIN": null, + "RIOI_ODELAY0_OFDLY0": null, + "RIOI_ODELAY0_OFDLY1": null, + "RIOI_ODELAY0_OFDLY2": null, + "RIOI_OLOGIC0_CLKDIVF": null, + "RIOI_OLOGIC0_OFB": null, + "RIOI_OLOGIC0_OQ": null, + "RIOI_OLOGIC0_TFB": null, + "RIOI_OLOGIC0_TFB_LOCAL": null, + "RIOI_OLOGIC0_TQ": null, + "RIOI_OSIN10": null, + "RIOI_OSIN20": null, + "RIOI_OSOUT10": null, + "RIOI_OSOUT20": null, + "RIOI_PD_INT_EN_1": null, + "RIOI_PU_INT_EN_1": null, + "RIOI_T0": null + } } diff --git a/kintex7/tile_type_RIOI_TBYTESRC.json b/kintex7/tile_type_RIOI_TBYTESRC.json index 92a4c17..6d9dacb 100644 --- a/kintex7/tile_type_RIOI_TBYTESRC.json +++ b/kintex7/tile_type_RIOI_TBYTESRC.json @@ -2,3236 +2,10908 @@ "pips": { "RIOI_TBYTESRC.IOI_BYP0_0->RIOI_ODELAY1_OFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_OFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP0_0" }, "RIOI_TBYTESRC.IOI_BYP0_1->RIOI_ODELAY0_OFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP0_1" }, "RIOI_TBYTESRC.IOI_BYP1_0->RIOI_ODELAY1_OFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_OFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP1_0" }, "RIOI_TBYTESRC.IOI_BYP1_1->RIOI_ODELAY0_OFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP1_1" }, "RIOI_TBYTESRC.IOI_BYP2_0->IOI_ODELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP2_0" }, "RIOI_TBYTESRC.IOI_BYP2_1->IOI_ODELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP2_1" }, "RIOI_TBYTESRC.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI_TBYTESRC.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI_TBYTESRC.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI_TBYTESRC.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI_TBYTESRC.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI_TBYTESRC.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI_TBYTESRC.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI_TBYTESRC.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI_TBYTESRC.IOI_BYP5_0->RIOI_ODELAY1_OFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_OFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP5_0" }, "RIOI_TBYTESRC.IOI_BYP5_1->RIOI_ODELAY0_OFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP5_1" }, "RIOI_TBYTESRC.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "RIOI_TBYTESRC.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_1" }, "RIOI_TBYTESRC.IOI_BYP7_0->RIOI_IDELAY1_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "RIOI_TBYTESRC.IOI_BYP7_1->RIOI_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_1" }, "RIOI_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI_TBYTESRC.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI_TBYTESRC.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI_TBYTESRC.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI_TBYTESRC.IOI_CLK1_0->IOI_ODELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI_TBYTESRC.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "RIOI_TBYTESRC.IOI_CLK1_1->IOI_ODELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "RIOI_TBYTESRC.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "RIOI_TBYTESRC.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_1" }, "RIOI_TBYTESRC.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "RIOI_TBYTESRC.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_1" }, "RIOI_TBYTESRC.IOI_FAN4_0->RIOI_IDELAY1_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "RIOI_TBYTESRC.IOI_FAN4_1->RIOI_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_1" }, "RIOI_TBYTESRC.IOI_FAN5_0->RIOI_IDELAY1_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "RIOI_TBYTESRC.IOI_FAN5_1->RIOI_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_1" }, "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "RIOI_TBYTESRC.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "RIOI_TBYTESRC.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "RIOI_TBYTESRC.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI_TBYTESRC.IOI_ILOGIC0_O->RIOI_I2GCLK_TOP0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_I2GCLK_TOP0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI_TBYTESRC.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "RIOI_TBYTESRC.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "RIOI_TBYTESRC.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "RIOI_TBYTESRC.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "RIOI_TBYTESRC.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "RIOI_TBYTESRC.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "RIOI_TBYTESRC.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "RIOI_TBYTESRC.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "RIOI_TBYTESRC.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC1_O" }, "RIOI_TBYTESRC.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q1" }, "RIOI_TBYTESRC.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q2" }, "RIOI_TBYTESRC.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q3" }, "RIOI_TBYTESRC.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q4" }, "RIOI_TBYTESRC.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q5" }, "RIOI_TBYTESRC.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q6" }, "RIOI_TBYTESRC.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q7" }, "RIOI_TBYTESRC.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q8" }, "RIOI_TBYTESRC.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "RIOI_TBYTESRC.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_1" }, "RIOI_TBYTESRC.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "RIOI_TBYTESRC.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_1" }, "RIOI_TBYTESRC.IOI_IMUX11_0->IOI_ODELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX11_0" }, "RIOI_TBYTESRC.IOI_IMUX11_1->IOI_ODELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX11_1" }, "RIOI_TBYTESRC.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "RIOI_TBYTESRC.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_1" }, "RIOI_TBYTESRC.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "RIOI_TBYTESRC.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_1" }, "RIOI_TBYTESRC.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "RIOI_TBYTESRC.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_1" }, "RIOI_TBYTESRC.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "RIOI_TBYTESRC.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_1" }, "RIOI_TBYTESRC.IOI_IMUX16_0->IOI_ODELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX16_0" }, "RIOI_TBYTESRC.IOI_IMUX16_1->IOI_ODELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX16_1" }, "RIOI_TBYTESRC.IOI_IMUX17_0->IOI_ODELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX17_0" }, "RIOI_TBYTESRC.IOI_IMUX17_1->IOI_ODELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX17_1" }, "RIOI_TBYTESRC.IOI_IMUX18_0->IOI_ODELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX18_0" }, "RIOI_TBYTESRC.IOI_IMUX18_1->IOI_ODELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX18_1" }, "RIOI_TBYTESRC.IOI_IMUX19_0->IOI_ODELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX19_0" }, "RIOI_TBYTESRC.IOI_IMUX19_1->IOI_ODELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX19_1" }, "RIOI_TBYTESRC.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "RIOI_TBYTESRC.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_1" }, "RIOI_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI_TBYTESRC.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI_TBYTESRC.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI_TBYTESRC.IOI_IMUX21_0->IOI_OLOGIC1_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "RIOI_TBYTESRC.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_1" }, "RIOI_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI_TBYTESRC.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI_TBYTESRC.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI_TBYTESRC.IOI_IMUX23_0->IOI_ODELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX23_0" }, "RIOI_TBYTESRC.IOI_IMUX23_1->IOI_ODELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX23_1" }, "RIOI_TBYTESRC.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "RIOI_TBYTESRC.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_1" }, "RIOI_TBYTESRC.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "RIOI_TBYTESRC.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_1" }, "RIOI_TBYTESRC.IOI_IMUX27_0->IOI_ODELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX27_0" }, "RIOI_TBYTESRC.IOI_IMUX27_1->IOI_ODELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX27_1" }, "RIOI_TBYTESRC.IOI_IMUX28_0->IOI_ODELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX28_0" }, "RIOI_TBYTESRC.IOI_IMUX28_1->IOI_ODELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX28_1" }, "RIOI_TBYTESRC.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "RIOI_TBYTESRC.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_1" }, "RIOI_TBYTESRC.IOI_IMUX2_0->IOI_ODELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX2_0" }, "RIOI_TBYTESRC.IOI_IMUX2_1->IOI_ODELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX2_1" }, "RIOI_TBYTESRC.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "RIOI_TBYTESRC.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_1" }, "RIOI_TBYTESRC.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI_TBYTESRC.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI_TBYTESRC.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI_TBYTESRC.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI_TBYTESRC.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "RIOI_TBYTESRC.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_1" }, "RIOI_TBYTESRC.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "RIOI_TBYTESRC.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_1" }, "RIOI_TBYTESRC.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "RIOI_TBYTESRC.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_1" }, "RIOI_TBYTESRC.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "RIOI_TBYTESRC.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_1" }, "RIOI_TBYTESRC.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "RIOI_TBYTESRC.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_1" }, "RIOI_TBYTESRC.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "RIOI_TBYTESRC.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_1" }, "RIOI_TBYTESRC.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "RIOI_TBYTESRC.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_1" }, "RIOI_TBYTESRC.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "RIOI_TBYTESRC.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_1" }, "RIOI_TBYTESRC.IOI_IMUX3_0->IOI_ODELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX3_0" }, "RIOI_TBYTESRC.IOI_IMUX3_1->IOI_ODELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX3_1" }, "RIOI_TBYTESRC.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "RIOI_TBYTESRC.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_1" }, "RIOI_TBYTESRC.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "RIOI_TBYTESRC.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_1" }, "RIOI_TBYTESRC.IOI_IMUX42_0->IOI_OLOGIC1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "RIOI_TBYTESRC.IOI_IMUX42_1->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_1" }, "RIOI_TBYTESRC.IOI_IMUX43_0->IOI_OLOGIC1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "RIOI_TBYTESRC.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_1" }, "RIOI_TBYTESRC.IOI_IMUX44_0->IOI_OLOGIC1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "RIOI_TBYTESRC.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_1" }, "RIOI_TBYTESRC.IOI_IMUX45_0->IOI_OLOGIC1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "RIOI_TBYTESRC.IOI_IMUX45_1->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_1" }, "RIOI_TBYTESRC.IOI_IMUX46_0->IOI_OLOGIC1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "RIOI_TBYTESRC.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_1" }, "RIOI_TBYTESRC.IOI_IMUX47_0->IOI_OLOGIC1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "RIOI_TBYTESRC.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_1" }, "RIOI_TBYTESRC.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "RIOI_TBYTESRC.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_1" }, "RIOI_TBYTESRC.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "RIOI_TBYTESRC.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_1" }, "RIOI_TBYTESRC.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "RIOI_TBYTESRC.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_1" }, "RIOI_TBYTESRC.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "RIOI_TBYTESRC.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_1" }, "RIOI_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_TBYTESRC.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_TBYTESRC.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI_TBYTESRC.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI_TBYTESRC.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI_TBYTESRC.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "RIOI_TBYTESRC.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_1" }, "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTESRC.IOI_IOCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTESRC.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, 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"IOI_IOCLK1" }, "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTESRC.IOI_IOCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": 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"is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTESRC.IOI_IOCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, 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"0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK2" }, 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"IOI_LEAF_GCLK3" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", 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"src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK3->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK4->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK4" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTESRC.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI_TBYTESRC.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI_TBYTESRC.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI_TBYTESRC.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTESRC.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTESRC.IOI_OCLK_0->IOI_ODELAY0_CLKIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CLKIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTESRC.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTESRC.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTESRC.IOI_OCLK_1->IOI_ODELAY1_CLKIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CLKIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTESRC.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT0" }, "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT1" }, "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT2" }, "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT3" }, "RIOI_TBYTESRC.IOI_ODELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT4" }, "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT0" }, "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT1" }, "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT2" }, "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT3" }, "RIOI_TBYTESRC.IOI_ODELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT4" }, "RIOI_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI_TBYTESRC.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": 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"1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI_TBYTESRC.IOI_OLOGIC0_T1->>RIOI_OLOGIC0_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_T1" }, "RIOI_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI_TBYTESRC.IOI_OLOGIC1_D1->>RIOI_OLOGIC1_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_D1" }, "RIOI_TBYTESRC.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OLOGIC1_IOCLKGLITCH" }, "RIOI_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI_TBYTESRC.IOI_OLOGIC1_T1->>RIOI_OLOGIC1_TQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.381", + "0.438", + "0.699", + "0.804" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC1_T1" }, "RIOI_TBYTESRC.IOI_OLOGIC1_TBYTEOUT->>IOI_TBYTEIN": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "dst_wire": "IOI_TBYTEIN", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": null, + "res": null + }, "src_wire": "IOI_OLOGIC1_TBYTEOUT" }, "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK" }, "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" }, "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0" }, "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, "RIOI_TBYTESRC.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_ICLK_0" }, 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"dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_PHASER_TO_IO_OCLK" }, "RIOI_TBYTESRC.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.031", + "0.035", + "0.058", + "0.066" + ], + "in_cap": "0.000", + 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"in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC1_D" }, "RIOI_TBYTESRC.RIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_O", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.051", + "0.059", + "0.090", + "0.104" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_ILOGIC1_DDLY" }, "RIOI_TBYTESRC.RIOI_ISOUT10->RIOI_ISIN11": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ISIN11", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ISOUT10" }, "RIOI_TBYTESRC.RIOI_ISOUT20->RIOI_ISIN21": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ISIN21", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ISOUT20" }, "RIOI_TBYTESRC.RIOI_ODELAY0_DATAOUT->RIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_O0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ODELAY0_DATAOUT" }, "RIOI_TBYTESRC.RIOI_ODELAY1_DATAOUT->RIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_O1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_ODELAY1_DATAOUT" }, "RIOI_TBYTESRC.RIOI_OLOGIC0_OFB->RIOI_ILOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_OFB" }, "RIOI_TBYTESRC.RIOI_OLOGIC0_OFB->RIOI_ODELAY0_ODATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_ODATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_OFB" }, "RIOI_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_O0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI_TBYTESRC.RIOI_OLOGIC0_OQ->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_OQ" }, "RIOI_TBYTESRC.RIOI_OLOGIC0_TFB->RIOI_OLOGIC0_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC0_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB" }, "RIOI_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI_TBYTESRC.RIOI_OLOGIC0_TFB_LOCAL->RIOI_ILOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC0_TFB_LOCAL" }, "RIOI_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_OLOGIC0_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI_TBYTESRC.RIOI_OLOGIC0_TQ->>RIOI_T0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC0_TQ" }, "RIOI_TBYTESRC.RIOI_OLOGIC1_OFB->RIOI_ILOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_OFB" }, "RIOI_TBYTESRC.RIOI_OLOGIC1_OFB->RIOI_ODELAY1_ODATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_ODATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_OFB" }, "RIOI_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI_TBYTESRC.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI_TBYTESRC.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB" }, "RIOI_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI_TBYTESRC.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI_TBYTESRC.RIOI_OLOGIC1_TQ->>RIOI_T1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI_TBYTESRC.RIOI_OSOUT11->RIOI_OSIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT11" }, "RIOI_TBYTESRC.RIOI_OSOUT21->RIOI_OSIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT21" } }, @@ -3240,39 +10912,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC1_CLK", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "D1": "IOI_OLOGIC1_D1", - "D2": "IOI_OLOGIC1_D2", - "D3": "IOI_OLOGIC1_D3", - "D4": "IOI_OLOGIC1_D4", - "D5": "IOI_OLOGIC1_D5", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "OCE": "IOI_OLOGIC1_OCE", - "OFB": "RIOI_OLOGIC1_OFB", - "OQ": "RIOI_OLOGIC1_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_OSOUT11", - "SHIFTOUT2": "RIOI_OSOUT21", - "SR": "IOI_OLOGIC1_SR", - "T1": "IOI_OLOGIC1_T1", - "T2": "IOI_OLOGIC1_T2", - "T3": "IOI_OLOGIC1_T3", - "T4": "IOI_OLOGIC1_T4", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TCE": "IOI_OLOGIC1_TCE", - "TFB": "RIOI_OLOGIC1_TFB", - "TQ": "RIOI_OLOGIC1_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TQ" + } }, "type": "OLOGICE2", "x_coord": 0, @@ -3282,29 +11224,236 @@ "name": "X0Y0", "prefix": "ODELAY", "site_pins": { - "C": "IOI_ODELAY1_C", - "CE": "IOI_ODELAY1_CE", - "CINVCTRL": "IOI_ODELAY1_CINVCTRL", - "CLKIN": "IOI_ODELAY1_CLKIN", - "CNTVALUEIN0": "IOI_ODELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_ODELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_ODELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_ODELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_ODELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_ODELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_ODELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_ODELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_ODELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_ODELAY1_CNTVALUEOUT4", - "DATAOUT": "RIOI_ODELAY1_DATAOUT", - "INC": "IOI_ODELAY1_INC", - "LD": "IOI_ODELAY1_LD", - "LDPIPEEN": "IOI_ODELAY1_LDPIPEEN", - "ODATAIN": "RIOI_ODELAY1_ODATAIN", - "OFDLY0": "RIOI_ODELAY1_OFDLY0", - "OFDLY1": "RIOI_ODELAY1_OFDLY1", - "OFDLY2": "RIOI_ODELAY1_OFDLY2", - "REGRST": "IOI_ODELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CINVCTRL" + }, + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CLKIN" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT4" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_ODELAY1_DATAOUT" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_LDPIPEEN" + }, + "ODATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_ODATAIN" + }, + "OFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_OFDLY0" + }, + "OFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_OFDLY1" + }, + "OFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_OFDLY2" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_REGRST" + } }, "type": "ODELAYE2", "x_coord": 0, @@ -3314,37 +11463,307 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "CE1": "IOI_ILOGIC1_CE1", - "CE2": "IOI_ILOGIC1_CE2", - "CLK": "IOI_ILOGIC1_CLK", - "CLKB": "IOI_ILOGIC1_CLKB", - "CLKDIV": "IOI_ILOGIC1_CLKDIV", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "D": "RIOI_ILOGIC1_D", - "DDLY": "RIOI_ILOGIC1_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "O": "IOI_ILOGIC1_O", - "OCLK": "IOI_ILOGIC1_OCLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "OFB": "RIOI_ILOGIC1_OFB", - "Q1": "IOI_ILOGIC1_Q1", - "Q2": "IOI_ILOGIC1_Q2", - "Q3": "IOI_ILOGIC1_Q3", - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q6": "IOI_ILOGIC1_Q6", - "Q7": "IOI_ILOGIC1_Q7", - "Q8": "IOI_ILOGIC1_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC1_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q8" + }, "REV": null, - "SHIFTIN1": "RIOI_ISIN11", - "SHIFTIN2": "RIOI_ISIN21", - "SHIFTOUT1": "RIOI_ISOUT11", - "SHIFTOUT2": "RIOI_ISOUT21", - "SR": "IOI_ILOGIC1_SR", - "TFB": "RIOI_ILOGIC1_TFB" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN11" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN21" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_TFB" + } }, "type": "ILOGICE2", "x_coord": 0, @@ -3354,39 +11773,327 @@ "name": "X0Y1", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "RIOI_OLOGIC0_OFB", - "OQ": "RIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OQ" + }, "REV": null, - "SHIFTIN1": "RIOI_OSIN10", - "SHIFTIN2": "RIOI_OSIN20", - "SHIFTOUT1": "RIOI_OSOUT10", - "SHIFTOUT2": "RIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "RIOI_OLOGIC0_TFB", - "TQ": "RIOI_OLOGIC0_TQ" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN10" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN20" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE2", "x_coord": 0, @@ -3396,29 +12103,236 @@ "name": "X0Y1", "prefix": "ODELAY", "site_pins": { - "C": "IOI_ODELAY0_C", - "CE": "IOI_ODELAY0_CE", - "CINVCTRL": "IOI_ODELAY0_CINVCTRL", - "CLKIN": "IOI_ODELAY0_CLKIN", - "CNTVALUEIN0": "IOI_ODELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_ODELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_ODELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_ODELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_ODELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_ODELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_ODELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_ODELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_ODELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_ODELAY0_CNTVALUEOUT4", - "DATAOUT": "RIOI_ODELAY0_DATAOUT", - "INC": "IOI_ODELAY0_INC", - "LD": "IOI_ODELAY0_LD", - "LDPIPEEN": "IOI_ODELAY0_LDPIPEEN", - "ODATAIN": "RIOI_ODELAY0_ODATAIN", - "OFDLY0": "RIOI_ODELAY0_OFDLY0", - "OFDLY1": "RIOI_ODELAY0_OFDLY1", - "OFDLY2": "RIOI_ODELAY0_OFDLY2", - "REGRST": "IOI_ODELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CINVCTRL" + }, + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CLKIN" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT4" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_ODELAY0_DATAOUT" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_LDPIPEEN" + }, + "ODATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_ODATAIN" + }, + "OFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY0" + }, + "OFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY1" + }, + "OFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY2" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_REGRST" + } }, "type": "ODELAYE2", "x_coord": 0, @@ -3428,37 +12342,289 @@ "name": "X0Y1", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "RIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "RIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE2", "x_coord": 0, @@ -3468,29 +12634,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY1_C", - "CE": "IOI_IDELAY1_CE", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY1_DATAIN", - "DATAOUT": "RIOI_IDELAY1_DATAOUT", - "IDATAIN": "RIOI_IDELAY1_IDATAIN", - "IFDLY0": "RIOI_IDELAY1_IFDLY0", - "IFDLY1": "RIOI_IDELAY1_IFDLY1", - "IFDLY2": "RIOI_IDELAY1_IFDLY2", - "INC": "IOI_IDELAY1_INC", - "LD": "IOI_IDELAY1_LD", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "REGRST": "IOI_IDELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY1_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_REGRST" + } }, "type": "IDELAYE2_FINEDELAY", "x_coord": 0, @@ -3500,29 +12873,236 @@ "name": "X0Y1", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "IFDLY0": "RIOI_IDELAY0_IFDLY0", - "IFDLY1": "RIOI_IDELAY0_IFDLY1", - "IFDLY2": "RIOI_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2_FINEDELAY", "x_coord": 0, @@ -3530,750 +13110,750 @@ } ], "tile_type": "RIOI_TBYTESRC", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS0_1", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS1_1", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS2_1", - "IOI_BLOCK_OUTS3_0", - "IOI_BLOCK_OUTS3_1", - "IOI_BYP0_0", - "IOI_BYP0_1", - "IOI_BYP1_0", - "IOI_BYP1_1", - "IOI_BYP2_0", - "IOI_BYP2_1", - "IOI_BYP3_0", - "IOI_BYP3_1", - "IOI_BYP4_0", - "IOI_BYP4_1", - "IOI_BYP5_0", - "IOI_BYP5_1", - "IOI_BYP6_0", - "IOI_BYP6_1", - "IOI_BYP7_0", - "IOI_BYP7_1", - "IOI_CLK0_0", - "IOI_CLK0_1", - "IOI_CLK1_0", - "IOI_CLK1_1", - "IOI_CTRL0_0", - "IOI_CTRL0_1", - "IOI_CTRL1_0", - "IOI_CTRL1_1", - "IOI_DCI_DCIDONE", - "IOI_DCI_TSTCLK", - "IOI_DCI_TSTHLN", - "IOI_DCI_TSTHLP", - "IOI_DCI_TSTRST", - "IOI_DCI_TSTRST0", - "IOI_EE2A0_0", - "IOI_EE2A0_1", - "IOI_EE2A1_0", - "IOI_EE2A1_1", - "IOI_EE2A2_0", - "IOI_EE2A2_1", - "IOI_EE2A3_0", - "IOI_EE2A3_1", - "IOI_EE2BEG0_0", - "IOI_EE2BEG0_1", - "IOI_EE2BEG1_0", - "IOI_EE2BEG1_1", - "IOI_EE2BEG2_0", - "IOI_EE2BEG2_1", - "IOI_EE2BEG3_0", - "IOI_EE2BEG3_1", - "IOI_EE4A0_0", - "IOI_EE4A0_1", - "IOI_EE4A1_0", - "IOI_EE4A1_1", - "IOI_EE4A2_0", - "IOI_EE4A2_1", - "IOI_EE4A3_0", - "IOI_EE4A3_1", - "IOI_EE4B0_0", - "IOI_EE4B0_1", - "IOI_EE4B1_0", - "IOI_EE4B1_1", - "IOI_EE4B2_0", - "IOI_EE4B2_1", - "IOI_EE4B3_0", - "IOI_EE4B3_1", - "IOI_EE4BEG0_0", - "IOI_EE4BEG0_1", - "IOI_EE4BEG1_0", - "IOI_EE4BEG1_1", - "IOI_EE4BEG2_0", - "IOI_EE4BEG2_1", - "IOI_EE4BEG3_0", - "IOI_EE4BEG3_1", - "IOI_EE4C0_0", - "IOI_EE4C0_1", - "IOI_EE4C1_0", - "IOI_EE4C1_1", - "IOI_EE4C2_0", - "IOI_EE4C2_1", - "IOI_EE4C3_0", - "IOI_EE4C3_1", - "IOI_EL1BEG0_0", - "IOI_EL1BEG0_1", - "IOI_EL1BEG1_0", - "IOI_EL1BEG1_1", - "IOI_EL1BEG2_0", - "IOI_EL1BEG2_1", - "IOI_EL1BEG3_0", - "IOI_EL1BEG3_1", - "IOI_ER1BEG0_0", - "IOI_ER1BEG0_1", - "IOI_ER1BEG1_0", - "IOI_ER1BEG1_1", - "IOI_ER1BEG2_0", - "IOI_ER1BEG2_1", - "IOI_ER1BEG3_0", - "IOI_ER1BEG3_1", - "IOI_FAN0_0", - "IOI_FAN0_1", - "IOI_FAN1_0", - "IOI_FAN1_1", - "IOI_FAN2_0", - "IOI_FAN2_1", - "IOI_FAN3_0", - "IOI_FAN3_1", - "IOI_FAN4_0", - "IOI_FAN4_1", - "IOI_FAN5_0", - "IOI_FAN5_1", - "IOI_FAN6_0", - "IOI_FAN6_1", - "IOI_FAN7_0", - "IOI_FAN7_1", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY1_C", - "IOI_IDELAY1_CE", - "IOI_IDELAY1_CINVCTRL", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT0", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_IDELAY1_DATAIN", - "IOI_IDELAY1_INC", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_LDPIPEEN", - "IOI_IDELAY1_REGRST", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC1_BITSLIP", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC1_CE2", - "IOI_ILOGIC1_CLK", - "IOI_ILOGIC1_CLKB", - "IOI_ILOGIC1_CLKDIV", - "IOI_ILOGIC1_CLKDIVP", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_ILOGIC1_O", - "IOI_ILOGIC1_OCLK", - "IOI_ILOGIC1_OCLKB", - "IOI_ILOGIC1_Q1", - "IOI_ILOGIC1_Q2", - "IOI_ILOGIC1_Q3", - "IOI_ILOGIC1_Q4", - "IOI_ILOGIC1_Q5", - "IOI_ILOGIC1_Q6", - "IOI_ILOGIC1_Q7", - "IOI_ILOGIC1_Q8", - "IOI_ILOGIC1_REV", - "IOI_ILOGIC1_SR", - "IOI_IMUX0_0", - "IOI_IMUX0_1", - "IOI_IMUX10_0", - "IOI_IMUX10_1", - "IOI_IMUX11_0", - "IOI_IMUX11_1", - "IOI_IMUX12_0", - "IOI_IMUX12_1", - "IOI_IMUX13_0", - "IOI_IMUX13_1", - "IOI_IMUX14_0", - "IOI_IMUX14_1", - "IOI_IMUX15_0", - "IOI_IMUX15_1", - "IOI_IMUX16_0", - "IOI_IMUX16_1", - "IOI_IMUX17_0", - "IOI_IMUX17_1", - "IOI_IMUX18_0", - "IOI_IMUX18_1", - "IOI_IMUX19_0", - "IOI_IMUX19_1", - "IOI_IMUX1_0", - "IOI_IMUX1_1", - "IOI_IMUX20_0", - "IOI_IMUX20_1", - "IOI_IMUX21_0", - "IOI_IMUX21_1", - "IOI_IMUX22_0", - "IOI_IMUX22_1", - "IOI_IMUX23_0", - "IOI_IMUX23_1", - "IOI_IMUX24_0", - "IOI_IMUX24_1", - "IOI_IMUX25_0", - "IOI_IMUX25_1", - "IOI_IMUX26_0", - "IOI_IMUX26_1", - "IOI_IMUX27_0", - "IOI_IMUX27_1", - "IOI_IMUX28_0", - "IOI_IMUX28_1", - "IOI_IMUX29_0", - "IOI_IMUX29_1", - "IOI_IMUX2_0", - "IOI_IMUX2_1", - "IOI_IMUX30_0", - "IOI_IMUX30_1", - "IOI_IMUX31_0", - "IOI_IMUX31_1", - "IOI_IMUX32_0", - "IOI_IMUX32_1", - "IOI_IMUX33_0", - "IOI_IMUX33_1", - "IOI_IMUX34_0", - "IOI_IMUX34_1", - "IOI_IMUX35_0", - "IOI_IMUX35_1", - "IOI_IMUX36_0", - "IOI_IMUX36_1", - "IOI_IMUX37_0", - "IOI_IMUX37_1", - "IOI_IMUX38_0", - "IOI_IMUX38_1", - "IOI_IMUX39_0", - "IOI_IMUX39_1", - "IOI_IMUX3_0", - "IOI_IMUX3_1", - "IOI_IMUX40_0", - "IOI_IMUX40_1", - "IOI_IMUX41_0", - "IOI_IMUX41_1", - "IOI_IMUX42_0", - "IOI_IMUX42_1", - "IOI_IMUX43_0", - "IOI_IMUX43_1", - "IOI_IMUX44_0", - "IOI_IMUX44_1", - "IOI_IMUX45_0", - "IOI_IMUX45_1", - "IOI_IMUX46_0", - "IOI_IMUX46_1", - "IOI_IMUX47_0", - "IOI_IMUX47_1", - "IOI_IMUX4_0", - "IOI_IMUX4_1", - "IOI_IMUX5_0", - "IOI_IMUX5_1", - "IOI_IMUX6_0", - "IOI_IMUX6_1", - "IOI_IMUX7_0", - "IOI_IMUX7_1", - "IOI_IMUX8_0", - "IOI_IMUX8_1", - "IOI_IMUX9_0", - "IOI_IMUX9_1", - "IOI_IMUX_RC0", - "IOI_IMUX_RC1", - "IOI_IMUX_RC2", - "IOI_IMUX_RC3", - "IOI_INT_DCI_EN", - "IOI_IOCLK0", - "IOI_IOCLK1", - "IOI_IOCLK2", - "IOI_IOCLK3", - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK5", - "IOI_LH10_0", - "IOI_LH10_1", - "IOI_LH11_0", - "IOI_LH11_1", - "IOI_LH12_0", - "IOI_LH12_1", - "IOI_LH1_0", - "IOI_LH1_1", - "IOI_LH2_0", - "IOI_LH2_1", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_LH4_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_LH5_1", - "IOI_LH6_0", - "IOI_LH6_1", - "IOI_LH7_0", - "IOI_LH7_1", - "IOI_LH8_0", - "IOI_LH8_1", - "IOI_LH9_0", - "IOI_LH9_1", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS10_1", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS11_1", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS12_1", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS13_1", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS14_1", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS15_1", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS16_1", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS17_1", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS18_1", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS1_1", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS20_1", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS21_1", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS22_1", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS23_1", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS2_1", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS3_1", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS4_1", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS5_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS6_1", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS7_1", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS9_0", - "IOI_LOGIC_OUTS9_1", - "IOI_MONITOR_N", - "IOI_MONITOR_P", - "IOI_NE2A0_0", - "IOI_NE2A0_1", - "IOI_NE2A1_0", - "IOI_NE2A1_1", - "IOI_NE2A2_0", - "IOI_NE2A2_1", - "IOI_NE2A3_0", - "IOI_NE2A3_1", - "IOI_NE4BEG0_0", - "IOI_NE4BEG0_1", - "IOI_NE4BEG1_0", - "IOI_NE4BEG1_1", - "IOI_NE4BEG2_0", - "IOI_NE4BEG2_1", - "IOI_NE4BEG3_0", - "IOI_NE4BEG3_1", - "IOI_NE4C0_0", - "IOI_NE4C0_1", - "IOI_NE4C1_0", - "IOI_NE4C1_1", - "IOI_NE4C2_0", - "IOI_NE4C2_1", - "IOI_NE4C3_0", - "IOI_NE4C3_1", - "IOI_NW2A0_0", - "IOI_NW2A0_1", - "IOI_NW2A1_0", - "IOI_NW2A1_1", - "IOI_NW2A2_0", - "IOI_NW2A2_1", - "IOI_NW2A3_0", - "IOI_NW2A3_1", - "IOI_NW4A0_0", - "IOI_NW4A0_1", - "IOI_NW4A1_0", - "IOI_NW4A1_1", - "IOI_NW4A2_0", - "IOI_NW4A2_1", - "IOI_NW4A3_0", - "IOI_NW4A3_1", - "IOI_NW4END0_0", - "IOI_NW4END0_1", - "IOI_NW4END1_0", - "IOI_NW4END1_1", - "IOI_NW4END2_0", - "IOI_NW4END2_1", - "IOI_NW4END3_0", - "IOI_NW4END3_1", - "IOI_OCLKM_0", - "IOI_OCLKM_1", - "IOI_OCLK_0", - "IOI_OCLK_1", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_ODELAY1_C", - "IOI_ODELAY1_CE", - "IOI_ODELAY1_CINVCTRL", - "IOI_ODELAY1_CLKIN", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_ODELAY1_INC", - "IOI_ODELAY1_LD", - "IOI_ODELAY1_LDPIPEEN", - "IOI_ODELAY1_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_CLK", - "IOI_OLOGIC1_CLKB", - "IOI_OLOGIC1_CLKDIV", - "IOI_OLOGIC1_CLKDIVB", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_OLOGIC1_D1", - "IOI_OLOGIC1_D2", - "IOI_OLOGIC1_D3", - "IOI_OLOGIC1_D4", - "IOI_OLOGIC1_D5", - "IOI_OLOGIC1_D6", - "IOI_OLOGIC1_D7", - "IOI_OLOGIC1_D8", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_OLOGIC1_OCE", - "IOI_OLOGIC1_REV", - "IOI_OLOGIC1_SR", - "IOI_OLOGIC1_T1", - "IOI_OLOGIC1_T2", - "IOI_OLOGIC1_T3", - "IOI_OLOGIC1_T4", - "IOI_OLOGIC1_TBYTEIN", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_OLOGIC1_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR3", - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO3", - "IOI_SE2A0_0", - "IOI_SE2A0_1", - "IOI_SE2A1_0", - "IOI_SE2A1_1", - "IOI_SE2A2_0", - "IOI_SE2A2_1", - "IOI_SE2A3_0", - "IOI_SE2A3_1", - "IOI_SE4BEG0_0", - "IOI_SE4BEG0_1", - "IOI_SE4BEG1_0", - "IOI_SE4BEG1_1", - "IOI_SE4BEG2_0", - "IOI_SE4BEG2_1", - "IOI_SE4BEG3_0", - "IOI_SE4BEG3_1", - "IOI_SE4C0_0", - "IOI_SE4C0_1", - "IOI_SE4C1_0", - "IOI_SE4C1_1", - "IOI_SE4C2_0", - "IOI_SE4C2_1", - "IOI_SE4C3_0", - "IOI_SE4C3_1", - "IOI_SW2A0_0", - "IOI_SW2A0_1", - "IOI_SW2A1_0", - "IOI_SW2A1_1", - "IOI_SW2A2_0", - "IOI_SW2A2_1", - "IOI_SW2A3_0", - "IOI_SW2A3_1", - "IOI_SW4A0_0", - "IOI_SW4A0_1", - "IOI_SW4A1_0", - "IOI_SW4A1_1", - "IOI_SW4A2_0", - "IOI_SW4A2_1", - "IOI_SW4A3_0", - "IOI_SW4A3_1", - "IOI_SW4END0_0", - "IOI_SW4END0_1", - "IOI_SW4END1_0", - "IOI_SW4END1_1", - "IOI_SW4END2_0", - "IOI_SW4END2_1", - "IOI_SW4END3_0", - "IOI_SW4END3_1", - "IOI_TBYTEIN", - "IOI_WL1END0_0", - "IOI_WL1END0_1", - "IOI_WL1END1_0", - "IOI_WL1END1_1", - "IOI_WL1END2_0", - "IOI_WL1END2_1", - "IOI_WL1END3_0", - "IOI_WL1END3_1", - "IOI_WR1END0_0", - "IOI_WR1END0_1", - "IOI_WR1END1_0", - "IOI_WR1END1_1", - "IOI_WR1END2_0", - "IOI_WR1END2_1", - "IOI_WR1END3_0", - "IOI_WR1END3_1", - "IOI_WW2A0_0", - "IOI_WW2A0_1", - "IOI_WW2A1_0", - "IOI_WW2A1_1", - "IOI_WW2A2_0", - "IOI_WW2A2_1", - "IOI_WW2A3_0", - "IOI_WW2A3_1", - "IOI_WW2END0_0", - "IOI_WW2END0_1", - "IOI_WW2END1_0", - "IOI_WW2END1_1", - "IOI_WW2END2_0", - "IOI_WW2END2_1", - "IOI_WW2END3_0", - "IOI_WW2END3_1", - "IOI_WW4A0_0", - "IOI_WW4A0_1", - "IOI_WW4A1_0", - "IOI_WW4A1_1", - "IOI_WW4A2_0", - "IOI_WW4A2_1", - "IOI_WW4A3_0", - "IOI_WW4A3_1", - "IOI_WW4B0_0", - "IOI_WW4B0_1", - "IOI_WW4B1_0", - "IOI_WW4B1_1", - "IOI_WW4B2_0", - "IOI_WW4B2_1", - "IOI_WW4B3_0", - "IOI_WW4B3_1", - "IOI_WW4C0_0", - "IOI_WW4C0_1", - "IOI_WW4C1_0", - "IOI_WW4C1_1", - "IOI_WW4C2_0", - "IOI_WW4C2_1", - "IOI_WW4C3_0", - "IOI_WW4C3_1", - "IOI_WW4END0_0", - "IOI_WW4END0_1", - "IOI_WW4END1_0", - "IOI_WW4END1_1", - "IOI_WW4END2_0", - "IOI_WW4END2_1", - "IOI_WW4END3_0", - "IOI_WW4END3_1", - "RIOI_DCI_T_TERM0", - "RIOI_DCI_T_TERM1", - "RIOI_DIFF_TERM_INT_EN", - "RIOI_I0", - "RIOI_I1", - "RIOI_I2GCLK_BOT1", - "RIOI_I2GCLK_TOP0", - "RIOI_I2GCLK_TOP1", - "RIOI_IBUF0", - "RIOI_IBUF1", - "RIOI_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE1", - "RIOI_IDELAY0_DATAOUT", - "RIOI_IDELAY0_IDATAIN", - "RIOI_IDELAY0_IFDLY0", - "RIOI_IDELAY0_IFDLY1", - "RIOI_IDELAY0_IFDLY2", - "RIOI_IDELAY1_DATAOUT", - "RIOI_IDELAY1_IDATAIN", - "RIOI_IDELAY1_IFDLY0", - "RIOI_IDELAY1_IFDLY1", - "RIOI_IDELAY1_IFDLY2", - "RIOI_ILOGIC0_D", - "RIOI_ILOGIC0_DDLY", - "RIOI_ILOGIC0_OFB", - "RIOI_ILOGIC0_TFB", - "RIOI_ILOGIC1_D", - "RIOI_ILOGIC1_DDLY", - "RIOI_ILOGIC1_OFB", - "RIOI_ILOGIC1_TFB", - "RIOI_ISIN10", - "RIOI_ISIN11", - "RIOI_ISIN20", - "RIOI_ISIN21", - "RIOI_ISOUT10", - "RIOI_ISOUT11", - "RIOI_ISOUT20", - "RIOI_ISOUT21", - "RIOI_KEEPER_INT_EN_0", - "RIOI_KEEPER_INT_EN_1", - "RIOI_O0", - "RIOI_O1", - "RIOI_ODELAY0_DATAOUT", - "RIOI_ODELAY0_ODATAIN", - "RIOI_ODELAY0_OFDLY0", - "RIOI_ODELAY0_OFDLY1", - "RIOI_ODELAY0_OFDLY2", - "RIOI_ODELAY1_DATAOUT", - "RIOI_ODELAY1_ODATAIN", - "RIOI_ODELAY1_OFDLY0", - "RIOI_ODELAY1_OFDLY1", - "RIOI_ODELAY1_OFDLY2", - "RIOI_OLOGIC0_CLKDIVF", - "RIOI_OLOGIC0_OFB", - "RIOI_OLOGIC0_OQ", - "RIOI_OLOGIC0_TFB", - "RIOI_OLOGIC0_TFB_LOCAL", - "RIOI_OLOGIC0_TQ", - "RIOI_OLOGIC1_CLKDIVF", - "RIOI_OLOGIC1_OFB", - "RIOI_OLOGIC1_OQ", - "RIOI_OLOGIC1_TFB", - "RIOI_OLOGIC1_TFB_LOCAL", - "RIOI_OLOGIC1_TQ", - "RIOI_OSIN10", - "RIOI_OSIN11", - "RIOI_OSIN20", - "RIOI_OSIN21", - "RIOI_OSOUT10", - "RIOI_OSOUT11", - "RIOI_OSOUT20", - "RIOI_OSOUT21", - "RIOI_PD_INT_EN_0", - "RIOI_PD_INT_EN_1", - "RIOI_PU_INT_EN_0", - "RIOI_PU_INT_EN_1", - "RIOI_T0", - "RIOI_T1" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS0_1": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS1_1": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS2_1": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BLOCK_OUTS3_1": null, + "IOI_BYP0_0": null, + "IOI_BYP0_1": null, + "IOI_BYP1_0": null, + "IOI_BYP1_1": null, + "IOI_BYP2_0": null, + "IOI_BYP2_1": null, + "IOI_BYP3_0": null, + "IOI_BYP3_1": null, + "IOI_BYP4_0": null, + "IOI_BYP4_1": null, + "IOI_BYP5_0": null, + "IOI_BYP5_1": null, + "IOI_BYP6_0": null, + "IOI_BYP6_1": null, + "IOI_BYP7_0": null, + "IOI_BYP7_1": null, + "IOI_CLK0_0": null, + "IOI_CLK0_1": null, + "IOI_CLK1_0": null, + "IOI_CLK1_1": null, + "IOI_CTRL0_0": null, + "IOI_CTRL0_1": null, + "IOI_CTRL1_0": null, + "IOI_CTRL1_1": null, + "IOI_DCI_DCIDONE": null, + "IOI_DCI_TSTCLK": null, + "IOI_DCI_TSTHLN": null, + "IOI_DCI_TSTHLP": null, + "IOI_DCI_TSTRST": null, + "IOI_DCI_TSTRST0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A0_1": null, + "IOI_EE2A1_0": null, + "IOI_EE2A1_1": null, + "IOI_EE2A2_0": null, + "IOI_EE2A2_1": null, + "IOI_EE2A3_0": null, + "IOI_EE2A3_1": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG0_1": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG1_1": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG2_1": null, + "IOI_EE2BEG3_0": null, + "IOI_EE2BEG3_1": null, + "IOI_EE4A0_0": null, + "IOI_EE4A0_1": null, + "IOI_EE4A1_0": null, + "IOI_EE4A1_1": null, + "IOI_EE4A2_0": null, + "IOI_EE4A2_1": null, + "IOI_EE4A3_0": null, + "IOI_EE4A3_1": null, + "IOI_EE4B0_0": null, + "IOI_EE4B0_1": null, + "IOI_EE4B1_0": null, + "IOI_EE4B1_1": null, + "IOI_EE4B2_0": null, + "IOI_EE4B2_1": null, + "IOI_EE4B3_0": null, + "IOI_EE4B3_1": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG0_1": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG1_1": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG2_1": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4BEG3_1": null, + "IOI_EE4C0_0": null, + "IOI_EE4C0_1": null, + "IOI_EE4C1_0": null, + "IOI_EE4C1_1": null, + "IOI_EE4C2_0": null, + "IOI_EE4C2_1": null, + "IOI_EE4C3_0": null, + "IOI_EE4C3_1": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG0_1": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG1_1": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG2_1": null, + "IOI_EL1BEG3_0": null, + "IOI_EL1BEG3_1": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG0_1": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG1_1": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG2_1": null, + "IOI_ER1BEG3_0": null, + "IOI_ER1BEG3_1": null, + "IOI_FAN0_0": null, + "IOI_FAN0_1": null, + "IOI_FAN1_0": null, + "IOI_FAN1_1": null, + "IOI_FAN2_0": null, + "IOI_FAN2_1": null, + "IOI_FAN3_0": null, + "IOI_FAN3_1": null, + "IOI_FAN4_0": null, + "IOI_FAN4_1": null, + "IOI_FAN5_0": null, + "IOI_FAN5_1": null, + "IOI_FAN6_0": null, + "IOI_FAN6_1": null, + "IOI_FAN7_0": null, + "IOI_FAN7_1": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_IDELAY1_C": null, + "IOI_IDELAY1_CE": null, + "IOI_IDELAY1_CINVCTRL": null, + "IOI_IDELAY1_CNTVALUEIN0": null, + "IOI_IDELAY1_CNTVALUEIN1": null, + "IOI_IDELAY1_CNTVALUEIN2": null, + "IOI_IDELAY1_CNTVALUEIN3": null, + "IOI_IDELAY1_CNTVALUEIN4": null, + "IOI_IDELAY1_CNTVALUEOUT0": null, + "IOI_IDELAY1_CNTVALUEOUT1": null, + "IOI_IDELAY1_CNTVALUEOUT2": null, + "IOI_IDELAY1_CNTVALUEOUT3": null, + "IOI_IDELAY1_CNTVALUEOUT4": null, + "IOI_IDELAY1_DATAIN": null, + "IOI_IDELAY1_INC": null, + "IOI_IDELAY1_LD": null, + "IOI_IDELAY1_LDPIPEEN": null, + "IOI_IDELAY1_REGRST": null, + "IOI_IDELAYCTRL_DNPULSEOUT": null, + "IOI_IDELAYCTRL_OUTN1": null, + "IOI_IDELAYCTRL_OUTN65": null, + "IOI_IDELAYCTRL_RDY": null, + "IOI_IDELAYCTRL_RST": null, + "IOI_IDELAYCTRL_UPPULSEOUT": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_ILOGIC1_BITSLIP": null, + "IOI_ILOGIC1_CE1": null, + "IOI_ILOGIC1_CE2": null, + "IOI_ILOGIC1_CLK": null, + "IOI_ILOGIC1_CLKB": null, + "IOI_ILOGIC1_CLKDIV": null, + "IOI_ILOGIC1_CLKDIVP": null, + "IOI_ILOGIC1_DYNCLKDIVPSEL": null, + "IOI_ILOGIC1_DYNCLKDIVSEL": null, + "IOI_ILOGIC1_DYNCLKSEL": null, + "IOI_ILOGIC1_O": null, + "IOI_ILOGIC1_OCLK": null, + "IOI_ILOGIC1_OCLKB": null, + "IOI_ILOGIC1_Q1": null, + "IOI_ILOGIC1_Q2": null, + "IOI_ILOGIC1_Q3": null, + "IOI_ILOGIC1_Q4": null, + "IOI_ILOGIC1_Q5": null, + "IOI_ILOGIC1_Q6": null, + "IOI_ILOGIC1_Q7": null, + "IOI_ILOGIC1_Q8": null, + "IOI_ILOGIC1_REV": null, + "IOI_ILOGIC1_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX0_1": null, + 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"IOI_SW4A1_0": null, + "IOI_SW4A1_1": null, + "IOI_SW4A2_0": null, + "IOI_SW4A2_1": null, + "IOI_SW4A3_0": null, + "IOI_SW4A3_1": null, + "IOI_SW4END0_0": null, + "IOI_SW4END0_1": null, + "IOI_SW4END1_0": null, + "IOI_SW4END1_1": null, + "IOI_SW4END2_0": null, + "IOI_SW4END2_1": null, + "IOI_SW4END3_0": null, + "IOI_SW4END3_1": null, + "IOI_TBYTEIN": null, + "IOI_WL1END0_0": null, + "IOI_WL1END0_1": null, + "IOI_WL1END1_0": null, + "IOI_WL1END1_1": null, + "IOI_WL1END2_0": null, + "IOI_WL1END2_1": null, + "IOI_WL1END3_0": null, + "IOI_WL1END3_1": null, + "IOI_WR1END0_0": null, + "IOI_WR1END0_1": null, + "IOI_WR1END1_0": null, + "IOI_WR1END1_1": null, + "IOI_WR1END2_0": null, + "IOI_WR1END2_1": null, + "IOI_WR1END3_0": null, + "IOI_WR1END3_1": null, + "IOI_WW2A0_0": null, + "IOI_WW2A0_1": null, + "IOI_WW2A1_0": null, + "IOI_WW2A1_1": null, + "IOI_WW2A2_0": null, + "IOI_WW2A2_1": null, + "IOI_WW2A3_0": null, + "IOI_WW2A3_1": null, + "IOI_WW2END0_0": null, + "IOI_WW2END0_1": null, + "IOI_WW2END1_0": null, + "IOI_WW2END1_1": null, + "IOI_WW2END2_0": null, + "IOI_WW2END2_1": null, + "IOI_WW2END3_0": null, + "IOI_WW2END3_1": null, + "IOI_WW4A0_0": null, + "IOI_WW4A0_1": null, + "IOI_WW4A1_0": null, + "IOI_WW4A1_1": null, + "IOI_WW4A2_0": null, + "IOI_WW4A2_1": null, + "IOI_WW4A3_0": null, + "IOI_WW4A3_1": null, + "IOI_WW4B0_0": null, + "IOI_WW4B0_1": null, + "IOI_WW4B1_0": null, + "IOI_WW4B1_1": null, + "IOI_WW4B2_0": null, + "IOI_WW4B2_1": null, + "IOI_WW4B3_0": null, + "IOI_WW4B3_1": null, + "IOI_WW4C0_0": null, + "IOI_WW4C0_1": null, + "IOI_WW4C1_0": null, + "IOI_WW4C1_1": null, + "IOI_WW4C2_0": null, + "IOI_WW4C2_1": null, + "IOI_WW4C3_0": null, + "IOI_WW4C3_1": null, + "IOI_WW4END0_0": null, + "IOI_WW4END0_1": null, + "IOI_WW4END1_0": null, + "IOI_WW4END1_1": null, + "IOI_WW4END2_0": null, + "IOI_WW4END2_1": null, + "IOI_WW4END3_0": null, + "IOI_WW4END3_1": null, + "RIOI_DCI_T_TERM0": null, + "RIOI_DCI_T_TERM1": null, + "RIOI_DIFF_TERM_INT_EN": null, + "RIOI_I0": null, + "RIOI_I1": null, + "RIOI_I2GCLK_BOT1": null, + "RIOI_I2GCLK_TOP0": null, + "RIOI_I2GCLK_TOP1": null, + "RIOI_IBUF0": null, + "RIOI_IBUF1": null, + "RIOI_IBUF_DISABLE0": null, + "RIOI_IBUF_DISABLE1": null, + "RIOI_IDELAY0_DATAOUT": null, + "RIOI_IDELAY0_IDATAIN": null, + "RIOI_IDELAY0_IFDLY0": null, + "RIOI_IDELAY0_IFDLY1": null, + "RIOI_IDELAY0_IFDLY2": null, + "RIOI_IDELAY1_DATAOUT": null, + "RIOI_IDELAY1_IDATAIN": null, + "RIOI_IDELAY1_IFDLY0": null, + "RIOI_IDELAY1_IFDLY1": null, + "RIOI_IDELAY1_IFDLY2": null, + "RIOI_ILOGIC0_D": null, + "RIOI_ILOGIC0_DDLY": null, + "RIOI_ILOGIC0_OFB": null, + "RIOI_ILOGIC0_TFB": null, + "RIOI_ILOGIC1_D": null, + "RIOI_ILOGIC1_DDLY": null, + "RIOI_ILOGIC1_OFB": null, + "RIOI_ILOGIC1_TFB": null, + "RIOI_ISIN10": null, + "RIOI_ISIN11": null, + "RIOI_ISIN20": null, + "RIOI_ISIN21": null, + "RIOI_ISOUT10": null, + "RIOI_ISOUT11": null, + "RIOI_ISOUT20": null, + "RIOI_ISOUT21": null, + "RIOI_KEEPER_INT_EN_0": null, + "RIOI_KEEPER_INT_EN_1": null, + "RIOI_O0": null, + "RIOI_O1": null, + "RIOI_ODELAY0_DATAOUT": null, + "RIOI_ODELAY0_ODATAIN": null, + "RIOI_ODELAY0_OFDLY0": null, + "RIOI_ODELAY0_OFDLY1": null, + "RIOI_ODELAY0_OFDLY2": null, + "RIOI_ODELAY1_DATAOUT": null, + "RIOI_ODELAY1_ODATAIN": null, + "RIOI_ODELAY1_OFDLY0": null, + "RIOI_ODELAY1_OFDLY1": null, + "RIOI_ODELAY1_OFDLY2": null, + "RIOI_OLOGIC0_CLKDIVF": null, + "RIOI_OLOGIC0_OFB": null, + "RIOI_OLOGIC0_OQ": null, + "RIOI_OLOGIC0_TFB": null, + "RIOI_OLOGIC0_TFB_LOCAL": null, + "RIOI_OLOGIC0_TQ": null, + "RIOI_OLOGIC1_CLKDIVF": null, + "RIOI_OLOGIC1_OFB": null, + "RIOI_OLOGIC1_OQ": null, + "RIOI_OLOGIC1_TFB": null, + "RIOI_OLOGIC1_TFB_LOCAL": null, + "RIOI_OLOGIC1_TQ": null, + "RIOI_OSIN10": null, + "RIOI_OSIN11": null, + "RIOI_OSIN20": null, + "RIOI_OSIN21": null, + "RIOI_OSOUT10": null, + "RIOI_OSOUT11": null, + "RIOI_OSOUT20": null, + "RIOI_OSOUT21": null, + "RIOI_PD_INT_EN_0": null, + "RIOI_PD_INT_EN_1": null, + "RIOI_PU_INT_EN_0": null, + "RIOI_PU_INT_EN_1": null, + "RIOI_T0": null, + "RIOI_T1": null + } } diff --git a/kintex7/tile_type_RIOI_TBYTETERM.json b/kintex7/tile_type_RIOI_TBYTETERM.json index d0e1d4d..959a93a 100644 --- a/kintex7/tile_type_RIOI_TBYTETERM.json +++ b/kintex7/tile_type_RIOI_TBYTETERM.json @@ -2,3222 +2,10862 @@ "pips": { "RIOI_TBYTETERM.IOI_BYP0_0->RIOI_ODELAY1_OFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_OFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP0_0" }, "RIOI_TBYTETERM.IOI_BYP0_1->RIOI_ODELAY0_OFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP0_1" }, "RIOI_TBYTETERM.IOI_BYP1_0->RIOI_ODELAY1_OFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_OFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP1_0" }, "RIOI_TBYTETERM.IOI_BYP1_1->RIOI_ODELAY0_OFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP1_1" }, "RIOI_TBYTETERM.IOI_BYP2_0->IOI_ODELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP2_0" }, "RIOI_TBYTETERM.IOI_BYP2_1->IOI_ODELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP2_1" }, "RIOI_TBYTETERM.IOI_BYP3_0->IOI_IMUX_RC0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI_TBYTETERM.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_0" }, "RIOI_TBYTETERM.IOI_BYP3_1->IOI_IMUX_RC3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI_TBYTETERM.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP3_1" }, "RIOI_TBYTETERM.IOI_BYP4_0->IOI_IMUX_RC1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI_TBYTETERM.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CLR2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_0" }, "RIOI_TBYTETERM.IOI_BYP4_1->IOI_IMUX_RC2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IMUX_RC2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI_TBYTETERM.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_RCLK_DIV_CE2_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP4_1" }, "RIOI_TBYTETERM.IOI_BYP5_0->RIOI_ODELAY1_OFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_OFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP5_0" }, "RIOI_TBYTETERM.IOI_BYP5_1->RIOI_ODELAY0_OFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY0_OFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP5_1" }, "RIOI_TBYTETERM.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_0" }, "RIOI_TBYTETERM.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CINVCTRL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP6_1" }, "RIOI_TBYTETERM.IOI_BYP7_0->RIOI_IDELAY1_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_0" }, "RIOI_TBYTETERM.IOI_BYP7_1->RIOI_IDELAY0_IFDLY2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_BYP7_1" }, "RIOI_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI_TBYTETERM.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_0" }, "RIOI_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI_TBYTETERM.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CLKDIVP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK0_1" }, "RIOI_TBYTETERM.IOI_CLK1_0->IOI_IDELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI_TBYTETERM.IOI_CLK1_0->IOI_ODELAY1_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_0" }, "RIOI_TBYTETERM.IOI_CLK1_1->IOI_IDELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "RIOI_TBYTETERM.IOI_CLK1_1->IOI_ODELAY0_C": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_C", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CLK1_1" }, "RIOI_TBYTETERM.IOI_CTRL0_0->IOI_OLOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_0" }, "RIOI_TBYTETERM.IOI_CTRL0_1->IOI_OLOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL0_1" }, "RIOI_TBYTETERM.IOI_CTRL1_0->IOI_ILOGIC1_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_0" }, "RIOI_TBYTETERM.IOI_CTRL1_1->IOI_ILOGIC0_SR": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_SR", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_CTRL1_1" }, "RIOI_TBYTETERM.IOI_FAN4_0->RIOI_IDELAY1_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_0" }, "RIOI_TBYTETERM.IOI_FAN4_1->RIOI_IDELAY0_IFDLY0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN4_1" }, "RIOI_TBYTETERM.IOI_FAN5_0->RIOI_IDELAY1_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY1_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_0" }, "RIOI_TBYTETERM.IOI_FAN5_1->RIOI_IDELAY0_IFDLY1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IDELAY0_IFDLY1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_FAN5_1" }, "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" }, "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" }, "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" }, "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" }, "RIOI_TBYTETERM.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" }, "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS20_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" }, "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS1_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" }, "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS19_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" }, "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS15_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" }, "RIOI_TBYTETERM.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS11_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" }, "RIOI_TBYTETERM.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC0_O" }, "RIOI_TBYTETERM.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q1" }, "RIOI_TBYTETERM.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q2" }, "RIOI_TBYTETERM.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q3" }, "RIOI_TBYTETERM.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q4" }, "RIOI_TBYTETERM.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q5" }, "RIOI_TBYTETERM.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q6" }, "RIOI_TBYTETERM.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q7" }, "RIOI_TBYTETERM.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC0_Q8" }, "RIOI_TBYTETERM.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_LOGIC_OUTS18_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.033", + "0.039", + "0.060", + "0.089" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_ILOGIC1_O" }, "RIOI_TBYTETERM.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS0_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q1" }, "RIOI_TBYTETERM.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS23_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q2" }, "RIOI_TBYTETERM.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS9_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q3" }, "RIOI_TBYTETERM.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS10_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q4" }, "RIOI_TBYTETERM.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS14_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q5" }, "RIOI_TBYTETERM.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS3_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q6" }, "RIOI_TBYTETERM.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS7_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q7" }, "RIOI_TBYTETERM.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS8_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ILOGIC1_Q8" }, "RIOI_TBYTETERM.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_0" }, "RIOI_TBYTETERM.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_BITSLIP", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX0_1" }, "RIOI_TBYTETERM.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_0" }, "RIOI_TBYTETERM.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX10_1" }, "RIOI_TBYTETERM.IOI_IMUX11_0->IOI_ODELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX11_0" }, "RIOI_TBYTETERM.IOI_IMUX11_1->IOI_ODELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX11_1" }, "RIOI_TBYTETERM.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_0" }, "RIOI_TBYTETERM.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_REGRST", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX12_1" }, "RIOI_TBYTETERM.IOI_IMUX13_0->IOI_OLOGIC1_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_0" }, "RIOI_TBYTETERM.IOI_IMUX13_1->IOI_OLOGIC0_T3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX13_1" }, "RIOI_TBYTETERM.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_0" }, "RIOI_TBYTETERM.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX14_1" }, "RIOI_TBYTETERM.IOI_IMUX15_0->IOI_OLOGIC1_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_0" }, "RIOI_TBYTETERM.IOI_IMUX15_1->IOI_OLOGIC0_T1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX15_1" }, "RIOI_TBYTETERM.IOI_IMUX16_0->IOI_ODELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX16_0" }, "RIOI_TBYTETERM.IOI_IMUX16_1->IOI_ODELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX16_1" }, "RIOI_TBYTETERM.IOI_IMUX17_0->IOI_ODELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX17_0" }, "RIOI_TBYTETERM.IOI_IMUX17_1->IOI_ODELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX17_1" }, "RIOI_TBYTETERM.IOI_IMUX18_0->IOI_ODELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX18_0" }, "RIOI_TBYTETERM.IOI_IMUX18_1->IOI_ODELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX18_1" }, "RIOI_TBYTETERM.IOI_IMUX19_0->IOI_ODELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX19_0" }, "RIOI_TBYTETERM.IOI_IMUX19_1->IOI_ODELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX19_1" }, "RIOI_TBYTETERM.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_0" }, "RIOI_TBYTETERM.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_TCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX1_1" }, "RIOI_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI_TBYTETERM.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_0" }, "RIOI_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI_TBYTETERM.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX20_1" }, "RIOI_TBYTETERM.IOI_IMUX21_0->IOI_OLOGIC1_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_0" }, "RIOI_TBYTETERM.IOI_IMUX21_1->IOI_OLOGIC0_T4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX21_1" }, "RIOI_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI_TBYTETERM.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_0" }, "RIOI_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI_TBYTETERM.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX22_1" }, "RIOI_TBYTETERM.IOI_IMUX23_0->IOI_ODELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX23_0" }, "RIOI_TBYTETERM.IOI_IMUX23_1->IOI_ODELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX23_1" }, "RIOI_TBYTETERM.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_0" }, "RIOI_TBYTETERM.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_DATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX25_1" }, "RIOI_TBYTETERM.IOI_IMUX26_0->IOI_IDELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_0" }, "RIOI_TBYTETERM.IOI_IMUX26_1->IOI_IDELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX26_1" }, "RIOI_TBYTETERM.IOI_IMUX27_0->IOI_ODELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX27_0" }, "RIOI_TBYTETERM.IOI_IMUX27_1->IOI_ODELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX27_1" }, "RIOI_TBYTETERM.IOI_IMUX28_0->IOI_ODELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX28_0" }, "RIOI_TBYTETERM.IOI_IMUX28_1->IOI_ODELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX28_1" }, "RIOI_TBYTETERM.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_0" }, "RIOI_TBYTETERM.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_OCE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX29_1" }, "RIOI_TBYTETERM.IOI_IMUX2_0->IOI_ODELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX2_0" }, "RIOI_TBYTETERM.IOI_IMUX2_1->IOI_ODELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX2_1" }, "RIOI_TBYTETERM.IOI_IMUX30_0->IOI_IDELAY1_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_0" }, "RIOI_TBYTETERM.IOI_IMUX30_1->IOI_IDELAY0_LD": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LD", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX30_1" }, "RIOI_TBYTETERM.IOI_IMUX31_0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI_TBYTETERM.IOI_IMUX31_0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_0" }, "RIOI_TBYTETERM.IOI_IMUX31_1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI_TBYTETERM.IOI_IMUX31_1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX31_1" }, "RIOI_TBYTETERM.IOI_IMUX32_0->IOI_IDELAY1_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_0" }, "RIOI_TBYTETERM.IOI_IMUX32_1->IOI_IDELAY0_CE": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CE", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX32_1" }, "RIOI_TBYTETERM.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_0" }, "RIOI_TBYTETERM.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_LDPIPEEN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX33_1" }, "RIOI_TBYTETERM.IOI_IMUX34_0->IOI_OLOGIC1_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_0" }, "RIOI_TBYTETERM.IOI_IMUX34_1->IOI_OLOGIC0_D1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX34_1" }, "RIOI_TBYTETERM.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_0" }, "RIOI_TBYTETERM.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX35_1" }, "RIOI_TBYTETERM.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_0" }, "RIOI_TBYTETERM.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX36_1" }, "RIOI_TBYTETERM.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_0" }, "RIOI_TBYTETERM.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX37_1" }, "RIOI_TBYTETERM.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_0" }, "RIOI_TBYTETERM.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX38_1" }, "RIOI_TBYTETERM.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_0" }, "RIOI_TBYTETERM.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX39_1" }, "RIOI_TBYTETERM.IOI_IMUX3_0->IOI_ODELAY1_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX3_0" }, "RIOI_TBYTETERM.IOI_IMUX3_1->IOI_ODELAY0_INC": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_INC", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX3_1" }, "RIOI_TBYTETERM.IOI_IMUX40_0->IOI_OLOGIC1_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_0" }, "RIOI_TBYTETERM.IOI_IMUX40_1->IOI_OLOGIC0_D2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX40_1" }, "RIOI_TBYTETERM.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_0" }, "RIOI_TBYTETERM.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX41_1" }, "RIOI_TBYTETERM.IOI_IMUX42_0->IOI_OLOGIC1_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_0" }, "RIOI_TBYTETERM.IOI_IMUX42_1->IOI_OLOGIC0_D4": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D4", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX42_1" }, "RIOI_TBYTETERM.IOI_IMUX43_0->IOI_OLOGIC1_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_0" }, "RIOI_TBYTETERM.IOI_IMUX43_1->IOI_OLOGIC0_D5": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D5", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX43_1" }, "RIOI_TBYTETERM.IOI_IMUX44_0->IOI_OLOGIC1_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_0" }, "RIOI_TBYTETERM.IOI_IMUX44_1->IOI_OLOGIC0_D3": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D3", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX44_1" }, "RIOI_TBYTETERM.IOI_IMUX45_0->IOI_OLOGIC1_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_0" }, "RIOI_TBYTETERM.IOI_IMUX45_1->IOI_OLOGIC0_D6": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D6", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX45_1" }, "RIOI_TBYTETERM.IOI_IMUX46_0->IOI_OLOGIC1_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_0" }, "RIOI_TBYTETERM.IOI_IMUX46_1->IOI_OLOGIC0_D7": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D7", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX46_1" }, "RIOI_TBYTETERM.IOI_IMUX47_0->IOI_OLOGIC1_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_0" }, "RIOI_TBYTETERM.IOI_IMUX47_1->IOI_OLOGIC0_D8": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_D8", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX47_1" }, "RIOI_TBYTETERM.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_0" }, "RIOI_TBYTETERM.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX4_1" }, "RIOI_TBYTETERM.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_0" }, "RIOI_TBYTETERM.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_CE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX5_1" }, "RIOI_TBYTETERM.IOI_IMUX6_0->RIOI_DCI_T_TERM1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_0" }, "RIOI_TBYTETERM.IOI_IMUX6_1->RIOI_DCI_T_TERM0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_DCI_T_TERM0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX6_1" }, "RIOI_TBYTETERM.IOI_IMUX7_0->IOI_OLOGIC1_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_0" }, "RIOI_TBYTETERM.IOI_IMUX7_1->IOI_OLOGIC0_T2": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_T2", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX7_1" }, "RIOI_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_TBYTETERM.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_TBYTETERM.IOI_IMUX8_0->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_0" }, "RIOI_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI_TBYTETERM.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI_TBYTETERM.IOI_IMUX8_1->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.134", + "0.154", + "0.247", + "0.284" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IMUX8_1" }, "RIOI_TBYTETERM.IOI_IMUX9_0->RIOI_IBUF_DISABLE1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_0" }, "RIOI_TBYTETERM.IOI_IMUX9_1->RIOI_IBUF_DISABLE0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_IBUF_DISABLE0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_IMUX9_1" }, "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTETERM.IOI_IOCLK0->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK0" }, "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTETERM.IOI_IOCLK1->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK1" }, "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTETERM.IOI_IOCLK2->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK2" }, "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_OCLKM_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_IOCLK3" }, "RIOI_TBYTETERM.IOI_IOCLK3->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + 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}, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK0" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { "can_invert": "0", + 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"res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_ILOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLKM_0", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK3" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { "can_invert": "0", + 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"0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OCLK_1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OCLK_1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC0_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIV", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "IOI_OLOGIC1_CLKDIVFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC0_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_LEAF_GCLK5->>RIOI_OLOGIC1_CLKDIVF": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_CLKDIVF", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.021", + "0.022", + "0.130", + "0.162" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "IOI_LEAF_GCLK5" }, "RIOI_TBYTETERM.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI_TBYTETERM.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_0" }, "RIOI_TBYTETERM.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI_TBYTETERM.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLKM_1" }, "RIOI_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTETERM.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC0_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTETERM.IOI_OCLK_0->IOI_ODELAY0_CLKIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY0_CLKIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTETERM.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC0_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_0" }, "RIOI_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTETERM.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ILOGIC1_OCLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTETERM.IOI_OCLK_1->IOI_ODELAY1_CLKIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_ODELAY1_CLKIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLK": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLK", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTETERM.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_OLOGIC1_CLKB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_OCLK_1" }, "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS12_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS12_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT0" }, "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS4_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS4_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT1" }, "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS6_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS6_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT2" }, "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS17_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS17_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT3" }, "RIOI_TBYTETERM.IOI_ODELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS21_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS21_1", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY0_CNTVALUEOUT4" }, "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS12_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS12_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT0" }, "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS4_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS4_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT1" }, "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS6_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS6_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT2" }, "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS17_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS17_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT3" }, "RIOI_TBYTETERM.IOI_ODELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS21_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS21_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "IOI_ODELAY1_CNTVALUEOUT4" }, "RIOI_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI_TBYTETERM.IOI_OLOGIC0_D1->>RIOI_OLOGIC0_OQ": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC0_OQ", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.128", + "0.277", + "0.731", + "0.801" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "IOI_OLOGIC0_D1" }, "RIOI_TBYTETERM.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS5_1", "is_directional": "1", + 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"RIOI_TBYTETERM.RIOI_OLOGIC1_OFB->RIOI_ODELAY1_ODATAIN": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ODELAY1_ODATAIN", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_OFB" }, "RIOI_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_O1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_O1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI_TBYTETERM.RIOI_OLOGIC1_OQ->>RIOI_OLOGIC1_OFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_OFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_OQ" }, "RIOI_TBYTETERM.RIOI_OLOGIC1_TFB->RIOI_OLOGIC1_TFB_LOCAL": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OLOGIC1_TFB_LOCAL", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB" }, "RIOI_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "IOI_LOGIC_OUTS2_0", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI_TBYTETERM.RIOI_OLOGIC1_TFB_LOCAL->RIOI_ILOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_ILOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OLOGIC1_TFB_LOCAL" }, "RIOI_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_OLOGIC1_TFB": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "dst_wire": "RIOI_OLOGIC1_TFB", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "1", + "src_to_dst": { + "delay": [ + "0.060", + "0.069", + "0.126", + "0.145" + ], + "in_cap": null, + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI_TBYTETERM.RIOI_OLOGIC1_TQ->>RIOI_T1": { "can_invert": "0", + "dst_to_src": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "dst_wire": "RIOI_T1", "is_directional": "1", + "is_pass_transistor": 0, "is_pseudo": "0", + "src_to_dst": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "in_cap": "0.000", + "res": "0.0" + }, "src_wire": "RIOI_OLOGIC1_TQ" }, "RIOI_TBYTETERM.RIOI_OSOUT11->RIOI_OSIN10": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN10", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT11" }, "RIOI_TBYTETERM.RIOI_OSOUT21->RIOI_OSIN20": { "can_invert": "0", + "dst_to_src": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "dst_wire": "RIOI_OSIN20", "is_directional": "1", + "is_pass_transistor": 1, "is_pseudo": "0", + "src_to_dst": { + "delay": null, + "in_cap": null, + "res": "0.000" + }, "src_wire": "RIOI_OSOUT21" } }, @@ -3226,39 +10866,309 @@ "name": "X0Y0", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC1_CLK", - "CLKB": "IOI_OLOGIC1_CLKB", - "CLKDIV": "IOI_OLOGIC1_CLKDIV", - "CLKDIVB": "IOI_OLOGIC1_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC1_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC1_CLKDIVFB", - "D1": "IOI_OLOGIC1_D1", - "D2": "IOI_OLOGIC1_D2", - "D3": "IOI_OLOGIC1_D3", - "D4": "IOI_OLOGIC1_D4", - "D5": "IOI_OLOGIC1_D5", - "D6": "IOI_OLOGIC1_D6", - "D7": "IOI_OLOGIC1_D7", - "D8": "IOI_OLOGIC1_D8", - "IOCLKGLITCH": "IOI_OLOGIC1_IOCLKGLITCH", - "OCE": "IOI_OLOGIC1_OCE", - "OFB": "RIOI_OLOGIC1_OFB", - "OQ": "RIOI_OLOGIC1_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC1_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_OQ" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_OSOUT11", - "SHIFTOUT2": "RIOI_OSOUT21", - "SR": "IOI_OLOGIC1_SR", - "T1": "IOI_OLOGIC1_T1", - "T2": "IOI_OLOGIC1_T2", - "T3": "IOI_OLOGIC1_T3", - "T4": "IOI_OLOGIC1_T4", - "TBYTEIN": "IOI_OLOGIC1_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC1_TBYTEOUT", - "TCE": "IOI_OLOGIC1_TCE", - "TFB": "RIOI_OLOGIC1_TFB", - "TQ": "RIOI_OLOGIC1_TQ" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC1_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC1_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC1_TQ" + } }, "type": "OLOGICE2", "x_coord": 0, @@ -3268,29 +11178,236 @@ "name": "X0Y0", "prefix": "ODELAY", "site_pins": { - "C": "IOI_ODELAY1_C", - "CE": "IOI_ODELAY1_CE", - "CINVCTRL": "IOI_ODELAY1_CINVCTRL", - "CLKIN": "IOI_ODELAY1_CLKIN", - "CNTVALUEIN0": "IOI_ODELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_ODELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_ODELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_ODELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_ODELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_ODELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_ODELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_ODELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_ODELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_ODELAY1_CNTVALUEOUT4", - "DATAOUT": "RIOI_ODELAY1_DATAOUT", - "INC": "IOI_ODELAY1_INC", - "LD": "IOI_ODELAY1_LD", - "LDPIPEEN": "IOI_ODELAY1_LDPIPEEN", - "ODATAIN": "RIOI_ODELAY1_ODATAIN", - "OFDLY0": "RIOI_ODELAY1_OFDLY0", - "OFDLY1": "RIOI_ODELAY1_OFDLY1", - "OFDLY2": "RIOI_ODELAY1_OFDLY2", - "REGRST": "IOI_ODELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CINVCTRL" + }, + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CLKIN" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY1_CNTVALUEOUT4" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_ODELAY1_DATAOUT" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_LDPIPEEN" + }, + "ODATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_ODATAIN" + }, + "OFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_OFDLY0" + }, + "OFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_OFDLY1" + }, + "OFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY1_OFDLY2" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY1_REGRST" + } }, "type": "ODELAYE2", "x_coord": 0, @@ -3300,37 +11417,307 @@ "name": "X0Y0", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC1_BITSLIP", - "CE1": "IOI_ILOGIC1_CE1", - "CE2": "IOI_ILOGIC1_CE2", - "CLK": "IOI_ILOGIC1_CLK", - "CLKB": "IOI_ILOGIC1_CLKB", - "CLKDIV": "IOI_ILOGIC1_CLKDIV", - "CLKDIVP": "IOI_ILOGIC1_CLKDIVP", - "D": "RIOI_ILOGIC1_D", - "DDLY": "RIOI_ILOGIC1_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC1_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC1_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC1_DYNCLKSEL", - "O": "IOI_ILOGIC1_O", - "OCLK": "IOI_ILOGIC1_OCLK", - "OCLKB": "IOI_ILOGIC1_OCLKB", - "OFB": "RIOI_ILOGIC1_OFB", - "Q1": "IOI_ILOGIC1_Q1", - "Q2": "IOI_ILOGIC1_Q2", - "Q3": "IOI_ILOGIC1_Q3", - "Q4": "IOI_ILOGIC1_Q4", - "Q5": "IOI_ILOGIC1_Q5", - "Q6": "IOI_ILOGIC1_Q6", - "Q7": "IOI_ILOGIC1_Q7", - "Q8": "IOI_ILOGIC1_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC1_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC1_Q8" + }, "REV": null, - "SHIFTIN1": "RIOI_ISIN11", - "SHIFTIN2": "RIOI_ISIN21", - "SHIFTOUT1": "RIOI_ISOUT11", - "SHIFTOUT2": "RIOI_ISOUT21", - "SR": "IOI_ILOGIC1_SR", - "TFB": "RIOI_ILOGIC1_TFB" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN11" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ISIN21" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT11" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT21" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC1_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC1_TFB" + } }, "type": "ILOGICE2", "x_coord": 0, @@ -3340,39 +11727,327 @@ "name": "X0Y1", "prefix": "OLOGIC", "site_pins": { - "CLK": "IOI_OLOGIC0_CLK", - "CLKB": "IOI_OLOGIC0_CLKB", - "CLKDIV": "IOI_OLOGIC0_CLKDIV", - "CLKDIVB": "IOI_OLOGIC0_CLKDIVB", - "CLKDIVF": "RIOI_OLOGIC0_CLKDIVF", - "CLKDIVFB": "IOI_OLOGIC0_CLKDIVFB", - "D1": "IOI_OLOGIC0_D1", - "D2": "IOI_OLOGIC0_D2", - "D3": "IOI_OLOGIC0_D3", - "D4": "IOI_OLOGIC0_D4", - "D5": "IOI_OLOGIC0_D5", - "D6": "IOI_OLOGIC0_D6", - "D7": "IOI_OLOGIC0_D7", - "D8": "IOI_OLOGIC0_D8", - "IOCLKGLITCH": "IOI_OLOGIC0_IOCLKGLITCH", - "OCE": "IOI_OLOGIC0_OCE", - "OFB": "RIOI_OLOGIC0_OFB", - "OQ": "RIOI_OLOGIC0_OQ", + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIV" + }, + "CLKDIVB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVB" + }, + "CLKDIVF": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OLOGIC0_CLKDIVF" + }, + "CLKDIVFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_CLKDIVFB" + }, + "D1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D1" + }, + "D2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D2" + }, + "D3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D3" + }, + "D4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D4" + }, + "D5": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D5" + }, + "D6": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D6" + }, + "D7": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D7" + }, + "D8": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_D8" + }, + "IOCLKGLITCH": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_IOCLKGLITCH" + }, + "OCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_OCE" + }, + "OFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OFB" + }, + "OQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_OQ" + }, "REV": null, - "SHIFTIN1": "RIOI_OSIN10", - "SHIFTIN2": "RIOI_OSIN20", - "SHIFTOUT1": "RIOI_OSOUT10", - "SHIFTOUT2": "RIOI_OSOUT20", - "SR": "IOI_OLOGIC0_SR", - "T1": "IOI_OLOGIC0_T1", - "T2": "IOI_OLOGIC0_T2", - "T3": "IOI_OLOGIC0_T3", - "T4": "IOI_OLOGIC0_T4", - "TBYTEIN": "IOI_OLOGIC0_TBYTEIN", - "TBYTEOUT": "IOI_OLOGIC0_TBYTEOUT", - "TCE": "IOI_OLOGIC0_TCE", - "TFB": "RIOI_OLOGIC0_TFB", - "TQ": "RIOI_OLOGIC0_TQ" + "SHIFTIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN10" + }, + "SHIFTIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_OSIN20" + }, + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_OSOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_SR" + }, + "T1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T1" + }, + "T2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T2" + }, + "T3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T3" + }, + "T4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_T4" + }, + "TBYTEIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TBYTEIN" + }, + "TBYTEOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_OLOGIC0_TBYTEOUT" + }, + "TCE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_OLOGIC0_TCE" + }, + "TFB": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TFB" + }, + "TQ": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_OLOGIC0_TQ" + } }, "type": "OLOGICE2", "x_coord": 0, @@ -3382,29 +12057,236 @@ "name": "X0Y1", "prefix": "ODELAY", "site_pins": { - "C": "IOI_ODELAY0_C", - "CE": "IOI_ODELAY0_CE", - "CINVCTRL": "IOI_ODELAY0_CINVCTRL", - "CLKIN": "IOI_ODELAY0_CLKIN", - "CNTVALUEIN0": "IOI_ODELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_ODELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_ODELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_ODELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_ODELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_ODELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_ODELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_ODELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_ODELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_ODELAY0_CNTVALUEOUT4", - "DATAOUT": "RIOI_ODELAY0_DATAOUT", - "INC": "IOI_ODELAY0_INC", - "LD": "IOI_ODELAY0_LD", - "LDPIPEEN": "IOI_ODELAY0_LDPIPEEN", - "ODATAIN": "RIOI_ODELAY0_ODATAIN", - "OFDLY0": "RIOI_ODELAY0_OFDLY0", - "OFDLY1": "RIOI_ODELAY0_OFDLY1", - "OFDLY2": "RIOI_ODELAY0_OFDLY2", - "REGRST": "IOI_ODELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CINVCTRL" + }, + "CLKIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CLKIN" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ODELAY0_CNTVALUEOUT4" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_ODELAY0_DATAOUT" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_LDPIPEEN" + }, + "ODATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_ODATAIN" + }, + "OFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY0" + }, + "OFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY1" + }, + "OFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ODELAY0_OFDLY2" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ODELAY0_REGRST" + } }, "type": "ODELAYE2", "x_coord": 0, @@ -3414,37 +12296,289 @@ "name": "X0Y1", "prefix": "ILOGIC", "site_pins": { - "BITSLIP": "IOI_ILOGIC0_BITSLIP", - "CE1": "IOI_ILOGIC0_CE1", - "CE2": "IOI_ILOGIC0_CE2", - "CLK": "IOI_ILOGIC0_CLK", - "CLKB": "IOI_ILOGIC0_CLKB", - "CLKDIV": "IOI_ILOGIC0_CLKDIV", - "CLKDIVP": "IOI_ILOGIC0_CLKDIVP", - "D": "RIOI_ILOGIC0_D", - "DDLY": "RIOI_ILOGIC0_DDLY", - "DYNCLKDIVPSEL": "IOI_ILOGIC0_DYNCLKDIVPSEL", - "DYNCLKDIVSEL": "IOI_ILOGIC0_DYNCLKDIVSEL", - "DYNCLKSEL": "IOI_ILOGIC0_DYNCLKSEL", - "O": "IOI_ILOGIC0_O", - "OCLK": "IOI_ILOGIC0_OCLK", - "OCLKB": "IOI_ILOGIC0_OCLKB", - "OFB": "RIOI_ILOGIC0_OFB", - "Q1": "IOI_ILOGIC0_Q1", - "Q2": "IOI_ILOGIC0_Q2", - "Q3": "IOI_ILOGIC0_Q3", - "Q4": "IOI_ILOGIC0_Q4", - "Q5": "IOI_ILOGIC0_Q5", - "Q6": "IOI_ILOGIC0_Q6", - "Q7": "IOI_ILOGIC0_Q7", - "Q8": "IOI_ILOGIC0_Q8", + "BITSLIP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_BITSLIP" + }, + "CE1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE1" + }, + "CE2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CE2" + }, + "CLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLK" + }, + "CLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKB" + }, + "CLKDIV": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIV" + }, + "CLKDIVP": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_CLKDIVP" + }, + "D": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_D" + }, + "DDLY": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_DDLY" + }, + "DYNCLKDIVPSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVPSEL" + }, + "DYNCLKDIVSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKDIVSEL" + }, + "DYNCLKSEL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_DYNCLKSEL" + }, + "O": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_ILOGIC0_O" + }, + "OCLK": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLK" + }, + "OCLKB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_OCLKB" + }, + "OFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_OFB" + }, + "Q1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q1" + }, + "Q2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q2" + }, + "Q3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q3" + }, + "Q4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q4" + }, + "Q5": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q5" + }, + "Q6": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q6" + }, + "Q7": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q7" + }, + "Q8": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "IOI_ILOGIC0_Q8" + }, "REV": null, "SHIFTIN1": null, "SHIFTIN2": null, - "SHIFTOUT1": "RIOI_ISOUT10", - "SHIFTOUT2": "RIOI_ISOUT20", - "SR": "IOI_ILOGIC0_SR", - "TFB": "RIOI_ILOGIC0_TFB" + "SHIFTOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT10" + }, + "SHIFTOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "687.5", + "wire": "RIOI_ISOUT20" + }, + "SR": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_ILOGIC0_SR" + }, + "TFB": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_ILOGIC0_TFB" + } }, "type": "ILOGICE2", "x_coord": 0, @@ -3454,29 +12588,236 @@ "name": "X0Y0", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY1_C", - "CE": "IOI_IDELAY1_CE", - "CINVCTRL": "IOI_IDELAY1_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY1_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY1_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY1_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY1_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY1_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY1_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY1_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY1_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY1_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY1_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY1_DATAIN", - "DATAOUT": "RIOI_IDELAY1_DATAOUT", - "IDATAIN": "RIOI_IDELAY1_IDATAIN", - "IFDLY0": "RIOI_IDELAY1_IFDLY0", - "IFDLY1": "RIOI_IDELAY1_IFDLY1", - "IFDLY2": "RIOI_IDELAY1_IFDLY2", - "INC": "IOI_IDELAY1_INC", - "LD": "IOI_IDELAY1_LD", - "LDPIPEEN": "IOI_IDELAY1_LDPIPEEN", - "REGRST": "IOI_IDELAY1_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY1_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY1_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY1_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY1_REGRST" + } }, "type": "IDELAYE2_FINEDELAY", "x_coord": 0, @@ -3486,29 +12827,236 @@ "name": "X0Y1", "prefix": "IDELAY", "site_pins": { - "C": "IOI_IDELAY0_C", - "CE": "IOI_IDELAY0_CE", - "CINVCTRL": "IOI_IDELAY0_CINVCTRL", - "CNTVALUEIN0": "IOI_IDELAY0_CNTVALUEIN0", - "CNTVALUEIN1": "IOI_IDELAY0_CNTVALUEIN1", - "CNTVALUEIN2": "IOI_IDELAY0_CNTVALUEIN2", - "CNTVALUEIN3": "IOI_IDELAY0_CNTVALUEIN3", - "CNTVALUEIN4": "IOI_IDELAY0_CNTVALUEIN4", - "CNTVALUEOUT0": "IOI_IDELAY0_CNTVALUEOUT0", - "CNTVALUEOUT1": "IOI_IDELAY0_CNTVALUEOUT1", - "CNTVALUEOUT2": "IOI_IDELAY0_CNTVALUEOUT2", - "CNTVALUEOUT3": "IOI_IDELAY0_CNTVALUEOUT3", - "CNTVALUEOUT4": "IOI_IDELAY0_CNTVALUEOUT4", - "DATAIN": "IOI_IDELAY0_DATAIN", - "DATAOUT": "RIOI_IDELAY0_DATAOUT", - "IDATAIN": "RIOI_IDELAY0_IDATAIN", - "IFDLY0": "RIOI_IDELAY0_IFDLY0", - "IFDLY1": "RIOI_IDELAY0_IFDLY1", - "IFDLY2": "RIOI_IDELAY0_IFDLY2", - "INC": "IOI_IDELAY0_INC", - "LD": "IOI_IDELAY0_LD", - "LDPIPEEN": "IOI_IDELAY0_LDPIPEEN", - "REGRST": "IOI_IDELAY0_REGRST" + "C": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_C" + }, + "CE": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CE" + }, + "CINVCTRL": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CINVCTRL" + }, + "CNTVALUEIN0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN0" + }, + "CNTVALUEIN1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN1" + }, + "CNTVALUEIN2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN2" + }, + "CNTVALUEIN3": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN3" + }, + "CNTVALUEIN4": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_CNTVALUEIN4" + }, + "CNTVALUEOUT0": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT0" + }, + "CNTVALUEOUT1": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT1" + }, + "CNTVALUEOUT2": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT2" + }, + "CNTVALUEOUT3": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT3" + }, + "CNTVALUEOUT4": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "IOI_IDELAY0_CNTVALUEOUT4" + }, + "DATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_DATAIN" + }, + "DATAOUT": { + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "res": "0.0", + "wire": "RIOI_IDELAY0_DATAOUT" + }, + "IDATAIN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IDATAIN" + }, + "IFDLY0": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY0" + }, + "IFDLY1": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY1" + }, + "IFDLY2": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "RIOI_IDELAY0_IFDLY2" + }, + "INC": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_INC" + }, + "LD": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LD" + }, + "LDPIPEEN": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_LDPIPEEN" + }, + "REGRST": { + "cap": "0.000", + "delay": [ + "0.000", + "0.000", + "0.000", + "0.000" + ], + "wire": "IOI_IDELAY0_REGRST" + } }, "type": "IDELAYE2_FINEDELAY", "x_coord": 0, @@ -3516,750 +13064,750 @@ } ], "tile_type": "RIOI_TBYTETERM", - "wires": [ - "IOI_BLOCK_OUTS0_0", - "IOI_BLOCK_OUTS0_1", - "IOI_BLOCK_OUTS1_0", - "IOI_BLOCK_OUTS1_1", - "IOI_BLOCK_OUTS2_0", - "IOI_BLOCK_OUTS2_1", - "IOI_BLOCK_OUTS3_0", - "IOI_BLOCK_OUTS3_1", - "IOI_BYP0_0", - "IOI_BYP0_1", - "IOI_BYP1_0", - "IOI_BYP1_1", - "IOI_BYP2_0", - "IOI_BYP2_1", - "IOI_BYP3_0", - "IOI_BYP3_1", - "IOI_BYP4_0", - "IOI_BYP4_1", - "IOI_BYP5_0", - "IOI_BYP5_1", - "IOI_BYP6_0", - "IOI_BYP6_1", - "IOI_BYP7_0", - "IOI_BYP7_1", - "IOI_CLK0_0", - "IOI_CLK0_1", - "IOI_CLK1_0", - "IOI_CLK1_1", - "IOI_CTRL0_0", - "IOI_CTRL0_1", - "IOI_CTRL1_0", - "IOI_CTRL1_1", - "IOI_DCI_DCIDONE", - "IOI_DCI_TSTCLK", - "IOI_DCI_TSTHLN", - "IOI_DCI_TSTHLP", - "IOI_DCI_TSTRST", - "IOI_DCI_TSTRST0", - "IOI_EE2A0_0", - "IOI_EE2A0_1", - "IOI_EE2A1_0", - "IOI_EE2A1_1", - "IOI_EE2A2_0", - "IOI_EE2A2_1", - "IOI_EE2A3_0", - "IOI_EE2A3_1", - "IOI_EE2BEG0_0", - "IOI_EE2BEG0_1", - "IOI_EE2BEG1_0", - "IOI_EE2BEG1_1", - "IOI_EE2BEG2_0", - "IOI_EE2BEG2_1", - "IOI_EE2BEG3_0", - "IOI_EE2BEG3_1", - "IOI_EE4A0_0", - "IOI_EE4A0_1", - "IOI_EE4A1_0", - "IOI_EE4A1_1", - "IOI_EE4A2_0", - "IOI_EE4A2_1", - "IOI_EE4A3_0", - "IOI_EE4A3_1", - "IOI_EE4B0_0", - "IOI_EE4B0_1", - "IOI_EE4B1_0", - "IOI_EE4B1_1", - "IOI_EE4B2_0", - "IOI_EE4B2_1", - "IOI_EE4B3_0", - "IOI_EE4B3_1", - "IOI_EE4BEG0_0", - "IOI_EE4BEG0_1", - "IOI_EE4BEG1_0", - "IOI_EE4BEG1_1", - "IOI_EE4BEG2_0", - "IOI_EE4BEG2_1", - "IOI_EE4BEG3_0", - "IOI_EE4BEG3_1", - "IOI_EE4C0_0", - "IOI_EE4C0_1", - "IOI_EE4C1_0", - "IOI_EE4C1_1", - "IOI_EE4C2_0", - "IOI_EE4C2_1", - "IOI_EE4C3_0", - "IOI_EE4C3_1", - "IOI_EL1BEG0_0", - "IOI_EL1BEG0_1", - "IOI_EL1BEG1_0", - "IOI_EL1BEG1_1", - "IOI_EL1BEG2_0", - "IOI_EL1BEG2_1", - "IOI_EL1BEG3_0", - "IOI_EL1BEG3_1", - "IOI_ER1BEG0_0", - "IOI_ER1BEG0_1", - "IOI_ER1BEG1_0", - "IOI_ER1BEG1_1", - "IOI_ER1BEG2_0", - "IOI_ER1BEG2_1", - "IOI_ER1BEG3_0", - "IOI_ER1BEG3_1", - "IOI_FAN0_0", - "IOI_FAN0_1", - "IOI_FAN1_0", - "IOI_FAN1_1", - "IOI_FAN2_0", - "IOI_FAN2_1", - "IOI_FAN3_0", - "IOI_FAN3_1", - "IOI_FAN4_0", - "IOI_FAN4_1", - "IOI_FAN5_0", - "IOI_FAN5_1", - "IOI_FAN6_0", - "IOI_FAN6_1", - "IOI_FAN7_0", - "IOI_FAN7_1", - "IOI_IDELAY0_C", - "IOI_IDELAY0_CE", - "IOI_IDELAY0_CINVCTRL", - "IOI_IDELAY0_CNTVALUEIN0", - "IOI_IDELAY0_CNTVALUEIN1", - "IOI_IDELAY0_CNTVALUEIN2", - "IOI_IDELAY0_CNTVALUEIN3", - "IOI_IDELAY0_CNTVALUEIN4", - "IOI_IDELAY0_CNTVALUEOUT0", - "IOI_IDELAY0_CNTVALUEOUT1", - "IOI_IDELAY0_CNTVALUEOUT2", - "IOI_IDELAY0_CNTVALUEOUT3", - "IOI_IDELAY0_CNTVALUEOUT4", - "IOI_IDELAY0_DATAIN", - "IOI_IDELAY0_INC", - "IOI_IDELAY0_LD", - "IOI_IDELAY0_LDPIPEEN", - "IOI_IDELAY0_REGRST", - "IOI_IDELAY1_C", - "IOI_IDELAY1_CE", - "IOI_IDELAY1_CINVCTRL", - "IOI_IDELAY1_CNTVALUEIN0", - "IOI_IDELAY1_CNTVALUEIN1", - "IOI_IDELAY1_CNTVALUEIN2", - "IOI_IDELAY1_CNTVALUEIN3", - "IOI_IDELAY1_CNTVALUEIN4", - "IOI_IDELAY1_CNTVALUEOUT0", - "IOI_IDELAY1_CNTVALUEOUT1", - "IOI_IDELAY1_CNTVALUEOUT2", - "IOI_IDELAY1_CNTVALUEOUT3", - "IOI_IDELAY1_CNTVALUEOUT4", - "IOI_IDELAY1_DATAIN", - "IOI_IDELAY1_INC", - "IOI_IDELAY1_LD", - "IOI_IDELAY1_LDPIPEEN", - "IOI_IDELAY1_REGRST", - "IOI_IDELAYCTRL_DNPULSEOUT", - "IOI_IDELAYCTRL_OUTN1", - "IOI_IDELAYCTRL_OUTN65", - "IOI_IDELAYCTRL_RDY", - "IOI_IDELAYCTRL_RST", - "IOI_IDELAYCTRL_UPPULSEOUT", - "IOI_ILOGIC0_BITSLIP", - "IOI_ILOGIC0_CE1", - "IOI_ILOGIC0_CE2", - "IOI_ILOGIC0_CLK", - "IOI_ILOGIC0_CLKB", - "IOI_ILOGIC0_CLKDIV", - "IOI_ILOGIC0_CLKDIVP", - "IOI_ILOGIC0_DYNCLKDIVPSEL", - "IOI_ILOGIC0_DYNCLKDIVSEL", - "IOI_ILOGIC0_DYNCLKSEL", - "IOI_ILOGIC0_O", - "IOI_ILOGIC0_OCLK", - "IOI_ILOGIC0_OCLKB", - "IOI_ILOGIC0_Q1", - "IOI_ILOGIC0_Q2", - "IOI_ILOGIC0_Q3", - "IOI_ILOGIC0_Q4", - "IOI_ILOGIC0_Q5", - "IOI_ILOGIC0_Q6", - "IOI_ILOGIC0_Q7", - "IOI_ILOGIC0_Q8", - "IOI_ILOGIC0_REV", - "IOI_ILOGIC0_SR", - "IOI_ILOGIC1_BITSLIP", - "IOI_ILOGIC1_CE1", - "IOI_ILOGIC1_CE2", - "IOI_ILOGIC1_CLK", - "IOI_ILOGIC1_CLKB", - "IOI_ILOGIC1_CLKDIV", - "IOI_ILOGIC1_CLKDIVP", - "IOI_ILOGIC1_DYNCLKDIVPSEL", - "IOI_ILOGIC1_DYNCLKDIVSEL", - "IOI_ILOGIC1_DYNCLKSEL", - "IOI_ILOGIC1_O", - "IOI_ILOGIC1_OCLK", - "IOI_ILOGIC1_OCLKB", - "IOI_ILOGIC1_Q1", - "IOI_ILOGIC1_Q2", - "IOI_ILOGIC1_Q3", - "IOI_ILOGIC1_Q4", - "IOI_ILOGIC1_Q5", - "IOI_ILOGIC1_Q6", - "IOI_ILOGIC1_Q7", - "IOI_ILOGIC1_Q8", - "IOI_ILOGIC1_REV", - "IOI_ILOGIC1_SR", - "IOI_IMUX0_0", - "IOI_IMUX0_1", - "IOI_IMUX10_0", - "IOI_IMUX10_1", - "IOI_IMUX11_0", - "IOI_IMUX11_1", - "IOI_IMUX12_0", - "IOI_IMUX12_1", - "IOI_IMUX13_0", - "IOI_IMUX13_1", - "IOI_IMUX14_0", - "IOI_IMUX14_1", - "IOI_IMUX15_0", - "IOI_IMUX15_1", - "IOI_IMUX16_0", - "IOI_IMUX16_1", - "IOI_IMUX17_0", - "IOI_IMUX17_1", - "IOI_IMUX18_0", - "IOI_IMUX18_1", - "IOI_IMUX19_0", - "IOI_IMUX19_1", - "IOI_IMUX1_0", - "IOI_IMUX1_1", - "IOI_IMUX20_0", - "IOI_IMUX20_1", - "IOI_IMUX21_0", - "IOI_IMUX21_1", - "IOI_IMUX22_0", - "IOI_IMUX22_1", - "IOI_IMUX23_0", - "IOI_IMUX23_1", - "IOI_IMUX24_0", - "IOI_IMUX24_1", - "IOI_IMUX25_0", - "IOI_IMUX25_1", - "IOI_IMUX26_0", - "IOI_IMUX26_1", - "IOI_IMUX27_0", - "IOI_IMUX27_1", - "IOI_IMUX28_0", - "IOI_IMUX28_1", - "IOI_IMUX29_0", - "IOI_IMUX29_1", - "IOI_IMUX2_0", - "IOI_IMUX2_1", - "IOI_IMUX30_0", - "IOI_IMUX30_1", - "IOI_IMUX31_0", - "IOI_IMUX31_1", - "IOI_IMUX32_0", - "IOI_IMUX32_1", - "IOI_IMUX33_0", - "IOI_IMUX33_1", - "IOI_IMUX34_0", - "IOI_IMUX34_1", - "IOI_IMUX35_0", - "IOI_IMUX35_1", - "IOI_IMUX36_0", - "IOI_IMUX36_1", - "IOI_IMUX37_0", - "IOI_IMUX37_1", - "IOI_IMUX38_0", - "IOI_IMUX38_1", - "IOI_IMUX39_0", - "IOI_IMUX39_1", - "IOI_IMUX3_0", - "IOI_IMUX3_1", - "IOI_IMUX40_0", - "IOI_IMUX40_1", - "IOI_IMUX41_0", - "IOI_IMUX41_1", - "IOI_IMUX42_0", - "IOI_IMUX42_1", - "IOI_IMUX43_0", - "IOI_IMUX43_1", - "IOI_IMUX44_0", - "IOI_IMUX44_1", - "IOI_IMUX45_0", - "IOI_IMUX45_1", - "IOI_IMUX46_0", - "IOI_IMUX46_1", - "IOI_IMUX47_0", - "IOI_IMUX47_1", - "IOI_IMUX4_0", - "IOI_IMUX4_1", - "IOI_IMUX5_0", - "IOI_IMUX5_1", - "IOI_IMUX6_0", - "IOI_IMUX6_1", - "IOI_IMUX7_0", - "IOI_IMUX7_1", - "IOI_IMUX8_0", - "IOI_IMUX8_1", - "IOI_IMUX9_0", - "IOI_IMUX9_1", - "IOI_IMUX_RC0", - "IOI_IMUX_RC1", - "IOI_IMUX_RC2", - "IOI_IMUX_RC3", - "IOI_INT_DCI_EN", - "IOI_IOCLK0", - "IOI_IOCLK1", - "IOI_IOCLK2", - "IOI_IOCLK3", - "IOI_LEAF_GCLK0", - "IOI_LEAF_GCLK1", - "IOI_LEAF_GCLK2", - "IOI_LEAF_GCLK3", - "IOI_LEAF_GCLK4", - "IOI_LEAF_GCLK5", - "IOI_LH10_0", - "IOI_LH10_1", - "IOI_LH11_0", - "IOI_LH11_1", - "IOI_LH12_0", - "IOI_LH12_1", - "IOI_LH1_0", - "IOI_LH1_1", - "IOI_LH2_0", - "IOI_LH2_1", - "IOI_LH3_0", - "IOI_LH3_1", - "IOI_LH4_0", - "IOI_LH4_1", - "IOI_LH5_0", - "IOI_LH5_1", - "IOI_LH6_0", - "IOI_LH6_1", - "IOI_LH7_0", - "IOI_LH7_1", - "IOI_LH8_0", - "IOI_LH8_1", - "IOI_LH9_0", - "IOI_LH9_1", - "IOI_LOGIC_OUTS0_0", - "IOI_LOGIC_OUTS0_1", - "IOI_LOGIC_OUTS10_0", - "IOI_LOGIC_OUTS10_1", - "IOI_LOGIC_OUTS11_0", - "IOI_LOGIC_OUTS11_1", - "IOI_LOGIC_OUTS12_0", - "IOI_LOGIC_OUTS12_1", - "IOI_LOGIC_OUTS13_0", - "IOI_LOGIC_OUTS13_1", - "IOI_LOGIC_OUTS14_0", - "IOI_LOGIC_OUTS14_1", - "IOI_LOGIC_OUTS15_0", - "IOI_LOGIC_OUTS15_1", - "IOI_LOGIC_OUTS16_0", - "IOI_LOGIC_OUTS16_1", - "IOI_LOGIC_OUTS17_0", - "IOI_LOGIC_OUTS17_1", - "IOI_LOGIC_OUTS18_0", - "IOI_LOGIC_OUTS18_1", - "IOI_LOGIC_OUTS19_0", - "IOI_LOGIC_OUTS19_1", - "IOI_LOGIC_OUTS1_0", - "IOI_LOGIC_OUTS1_1", - "IOI_LOGIC_OUTS20_0", - "IOI_LOGIC_OUTS20_1", - "IOI_LOGIC_OUTS21_0", - "IOI_LOGIC_OUTS21_1", - "IOI_LOGIC_OUTS22_0", - "IOI_LOGIC_OUTS22_1", - "IOI_LOGIC_OUTS23_0", - "IOI_LOGIC_OUTS23_1", - "IOI_LOGIC_OUTS2_0", - "IOI_LOGIC_OUTS2_1", - "IOI_LOGIC_OUTS3_0", - "IOI_LOGIC_OUTS3_1", - "IOI_LOGIC_OUTS4_0", - "IOI_LOGIC_OUTS4_1", - "IOI_LOGIC_OUTS5_0", - "IOI_LOGIC_OUTS5_1", - "IOI_LOGIC_OUTS6_0", - "IOI_LOGIC_OUTS6_1", - "IOI_LOGIC_OUTS7_0", - "IOI_LOGIC_OUTS7_1", - "IOI_LOGIC_OUTS8_0", - "IOI_LOGIC_OUTS8_1", - "IOI_LOGIC_OUTS9_0", - "IOI_LOGIC_OUTS9_1", - "IOI_MONITOR_N", - "IOI_MONITOR_P", - "IOI_NE2A0_0", - "IOI_NE2A0_1", - "IOI_NE2A1_0", - "IOI_NE2A1_1", - "IOI_NE2A2_0", - "IOI_NE2A2_1", - "IOI_NE2A3_0", - "IOI_NE2A3_1", - "IOI_NE4BEG0_0", - "IOI_NE4BEG0_1", - "IOI_NE4BEG1_0", - "IOI_NE4BEG1_1", - "IOI_NE4BEG2_0", - "IOI_NE4BEG2_1", - "IOI_NE4BEG3_0", - "IOI_NE4BEG3_1", - "IOI_NE4C0_0", - "IOI_NE4C0_1", - "IOI_NE4C1_0", - "IOI_NE4C1_1", - "IOI_NE4C2_0", - "IOI_NE4C2_1", - "IOI_NE4C3_0", - "IOI_NE4C3_1", - "IOI_NW2A0_0", - "IOI_NW2A0_1", - "IOI_NW2A1_0", - "IOI_NW2A1_1", - "IOI_NW2A2_0", - "IOI_NW2A2_1", - "IOI_NW2A3_0", - "IOI_NW2A3_1", - "IOI_NW4A0_0", - "IOI_NW4A0_1", - "IOI_NW4A1_0", - "IOI_NW4A1_1", - "IOI_NW4A2_0", - "IOI_NW4A2_1", - "IOI_NW4A3_0", - "IOI_NW4A3_1", - "IOI_NW4END0_0", - "IOI_NW4END0_1", - "IOI_NW4END1_0", - "IOI_NW4END1_1", - "IOI_NW4END2_0", - "IOI_NW4END2_1", - "IOI_NW4END3_0", - "IOI_NW4END3_1", - "IOI_OCLKM_0", - "IOI_OCLKM_1", - "IOI_OCLK_0", - "IOI_OCLK_1", - "IOI_ODELAY0_C", - "IOI_ODELAY0_CE", - "IOI_ODELAY0_CINVCTRL", - "IOI_ODELAY0_CLKIN", - "IOI_ODELAY0_CNTVALUEIN0", - "IOI_ODELAY0_CNTVALUEIN1", - "IOI_ODELAY0_CNTVALUEIN2", - "IOI_ODELAY0_CNTVALUEIN3", - "IOI_ODELAY0_CNTVALUEIN4", - "IOI_ODELAY0_CNTVALUEOUT0", - "IOI_ODELAY0_CNTVALUEOUT1", - "IOI_ODELAY0_CNTVALUEOUT2", - "IOI_ODELAY0_CNTVALUEOUT3", - "IOI_ODELAY0_CNTVALUEOUT4", - "IOI_ODELAY0_INC", - "IOI_ODELAY0_LD", - "IOI_ODELAY0_LDPIPEEN", - "IOI_ODELAY0_REGRST", - "IOI_ODELAY1_C", - "IOI_ODELAY1_CE", - "IOI_ODELAY1_CINVCTRL", - "IOI_ODELAY1_CLKIN", - "IOI_ODELAY1_CNTVALUEIN0", - "IOI_ODELAY1_CNTVALUEIN1", - "IOI_ODELAY1_CNTVALUEIN2", - "IOI_ODELAY1_CNTVALUEIN3", - "IOI_ODELAY1_CNTVALUEIN4", - "IOI_ODELAY1_CNTVALUEOUT0", - "IOI_ODELAY1_CNTVALUEOUT1", - "IOI_ODELAY1_CNTVALUEOUT2", - "IOI_ODELAY1_CNTVALUEOUT3", - "IOI_ODELAY1_CNTVALUEOUT4", - "IOI_ODELAY1_INC", - "IOI_ODELAY1_LD", - "IOI_ODELAY1_LDPIPEEN", - "IOI_ODELAY1_REGRST", - "IOI_OLOGIC0_CLK", - "IOI_OLOGIC0_CLKB", - "IOI_OLOGIC0_CLKDIV", - "IOI_OLOGIC0_CLKDIVB", - "IOI_OLOGIC0_CLKDIVFB", - "IOI_OLOGIC0_D1", - "IOI_OLOGIC0_D2", - "IOI_OLOGIC0_D3", - "IOI_OLOGIC0_D4", - "IOI_OLOGIC0_D5", - "IOI_OLOGIC0_D6", - "IOI_OLOGIC0_D7", - "IOI_OLOGIC0_D8", - "IOI_OLOGIC0_IOCLKGLITCH", - "IOI_OLOGIC0_OCE", - "IOI_OLOGIC0_REV", - "IOI_OLOGIC0_SR", - "IOI_OLOGIC0_T1", - "IOI_OLOGIC0_T2", - "IOI_OLOGIC0_T3", - "IOI_OLOGIC0_T4", - "IOI_OLOGIC0_TBYTEIN", - "IOI_OLOGIC0_TBYTEOUT", - "IOI_OLOGIC0_TCE", - "IOI_OLOGIC1_CLK", - "IOI_OLOGIC1_CLKB", - "IOI_OLOGIC1_CLKDIV", - "IOI_OLOGIC1_CLKDIVB", - "IOI_OLOGIC1_CLKDIVFB", - "IOI_OLOGIC1_D1", - "IOI_OLOGIC1_D2", - "IOI_OLOGIC1_D3", - "IOI_OLOGIC1_D4", - "IOI_OLOGIC1_D5", - "IOI_OLOGIC1_D6", - "IOI_OLOGIC1_D7", - "IOI_OLOGIC1_D8", - "IOI_OLOGIC1_IOCLKGLITCH", - "IOI_OLOGIC1_OCE", - "IOI_OLOGIC1_REV", - "IOI_OLOGIC1_SR", - "IOI_OLOGIC1_T1", - "IOI_OLOGIC1_T2", - "IOI_OLOGIC1_T3", - "IOI_OLOGIC1_T4", - "IOI_OLOGIC1_TBYTEIN", - "IOI_OLOGIC1_TBYTEOUT", - "IOI_OLOGIC1_TCE", - "IOI_PHASER_TO_IO_ICLK", - "IOI_PHASER_TO_IO_ICLKDIV", - "IOI_PHASER_TO_IO_ICLKDIV_0", - "IOI_PHASER_TO_IO_ICLK_0", - "IOI_PHASER_TO_IO_OCLK", - "IOI_PHASER_TO_IO_OCLK1X_90", - "IOI_PHASER_TO_IO_OCLK1X_90_0", - "IOI_PHASER_TO_IO_OCLKDIV", - "IOI_PHASER_TO_IO_OCLKDIV_0", - "IOI_PHASER_TO_IO_OCLK_0", - "IOI_RCLK_DIV_CE0", - "IOI_RCLK_DIV_CE1", - "IOI_RCLK_DIV_CE2", - "IOI_RCLK_DIV_CE2_1", - "IOI_RCLK_DIV_CE3", - "IOI_RCLK_DIV_CE3_1", - "IOI_RCLK_DIV_CLR0", - "IOI_RCLK_DIV_CLR0_1", - "IOI_RCLK_DIV_CLR1", - "IOI_RCLK_DIV_CLR1_1", - "IOI_RCLK_DIV_CLR2", - "IOI_RCLK_DIV_CLR3", - "IOI_RCLK_FORIO0", - "IOI_RCLK_FORIO1", - "IOI_RCLK_FORIO2", - "IOI_RCLK_FORIO3", - "IOI_SE2A0_0", - "IOI_SE2A0_1", - "IOI_SE2A1_0", - "IOI_SE2A1_1", - "IOI_SE2A2_0", - "IOI_SE2A2_1", - "IOI_SE2A3_0", - "IOI_SE2A3_1", - "IOI_SE4BEG0_0", - "IOI_SE4BEG0_1", - "IOI_SE4BEG1_0", - "IOI_SE4BEG1_1", - "IOI_SE4BEG2_0", - "IOI_SE4BEG2_1", - "IOI_SE4BEG3_0", - "IOI_SE4BEG3_1", - "IOI_SE4C0_0", - "IOI_SE4C0_1", - "IOI_SE4C1_0", - "IOI_SE4C1_1", - "IOI_SE4C2_0", - "IOI_SE4C2_1", - "IOI_SE4C3_0", - "IOI_SE4C3_1", - "IOI_SW2A0_0", - "IOI_SW2A0_1", - "IOI_SW2A1_0", - "IOI_SW2A1_1", - "IOI_SW2A2_0", - "IOI_SW2A2_1", - "IOI_SW2A3_0", - "IOI_SW2A3_1", - "IOI_SW4A0_0", - "IOI_SW4A0_1", - "IOI_SW4A1_0", - "IOI_SW4A1_1", - "IOI_SW4A2_0", - "IOI_SW4A2_1", - "IOI_SW4A3_0", - "IOI_SW4A3_1", - "IOI_SW4END0_0", - "IOI_SW4END0_1", - "IOI_SW4END1_0", - "IOI_SW4END1_1", - "IOI_SW4END2_0", - "IOI_SW4END2_1", - "IOI_SW4END3_0", - "IOI_SW4END3_1", - "IOI_TBYTEIN_TERM", - "IOI_WL1END0_0", - "IOI_WL1END0_1", - "IOI_WL1END1_0", - "IOI_WL1END1_1", - "IOI_WL1END2_0", - "IOI_WL1END2_1", - "IOI_WL1END3_0", - "IOI_WL1END3_1", - "IOI_WR1END0_0", - "IOI_WR1END0_1", - "IOI_WR1END1_0", - "IOI_WR1END1_1", - "IOI_WR1END2_0", - "IOI_WR1END2_1", - "IOI_WR1END3_0", - "IOI_WR1END3_1", - "IOI_WW2A0_0", - "IOI_WW2A0_1", - "IOI_WW2A1_0", - "IOI_WW2A1_1", - "IOI_WW2A2_0", - "IOI_WW2A2_1", - "IOI_WW2A3_0", - "IOI_WW2A3_1", - "IOI_WW2END0_0", - "IOI_WW2END0_1", - "IOI_WW2END1_0", - "IOI_WW2END1_1", - "IOI_WW2END2_0", - "IOI_WW2END2_1", - "IOI_WW2END3_0", - "IOI_WW2END3_1", - "IOI_WW4A0_0", - "IOI_WW4A0_1", - "IOI_WW4A1_0", - "IOI_WW4A1_1", - "IOI_WW4A2_0", - "IOI_WW4A2_1", - "IOI_WW4A3_0", - "IOI_WW4A3_1", - "IOI_WW4B0_0", - "IOI_WW4B0_1", - "IOI_WW4B1_0", - "IOI_WW4B1_1", - "IOI_WW4B2_0", - "IOI_WW4B2_1", - "IOI_WW4B3_0", - "IOI_WW4B3_1", - "IOI_WW4C0_0", - "IOI_WW4C0_1", - "IOI_WW4C1_0", - "IOI_WW4C1_1", - "IOI_WW4C2_0", - "IOI_WW4C2_1", - "IOI_WW4C3_0", - "IOI_WW4C3_1", - "IOI_WW4END0_0", - "IOI_WW4END0_1", - "IOI_WW4END1_0", - "IOI_WW4END1_1", - "IOI_WW4END2_0", - "IOI_WW4END2_1", - "IOI_WW4END3_0", - "IOI_WW4END3_1", - "RIOI_DCI_T_TERM0", - "RIOI_DCI_T_TERM1", - "RIOI_DIFF_TERM_INT_EN", - "RIOI_I0", - "RIOI_I1", - "RIOI_I2GCLK_BOT1", - "RIOI_I2GCLK_TOP0", - "RIOI_I2GCLK_TOP1", - "RIOI_IBUF0", - "RIOI_IBUF1", - "RIOI_IBUF_DISABLE0", - "RIOI_IBUF_DISABLE1", - "RIOI_IDELAY0_DATAOUT", - "RIOI_IDELAY0_IDATAIN", - "RIOI_IDELAY0_IFDLY0", - "RIOI_IDELAY0_IFDLY1", - "RIOI_IDELAY0_IFDLY2", - "RIOI_IDELAY1_DATAOUT", - "RIOI_IDELAY1_IDATAIN", - "RIOI_IDELAY1_IFDLY0", - "RIOI_IDELAY1_IFDLY1", - "RIOI_IDELAY1_IFDLY2", - "RIOI_ILOGIC0_D", - "RIOI_ILOGIC0_DDLY", - "RIOI_ILOGIC0_OFB", - "RIOI_ILOGIC0_TFB", - "RIOI_ILOGIC1_D", - "RIOI_ILOGIC1_DDLY", - "RIOI_ILOGIC1_OFB", - "RIOI_ILOGIC1_TFB", - "RIOI_ISIN10", - "RIOI_ISIN11", - "RIOI_ISIN20", - "RIOI_ISIN21", - "RIOI_ISOUT10", - "RIOI_ISOUT11", - "RIOI_ISOUT20", - "RIOI_ISOUT21", - "RIOI_KEEPER_INT_EN_0", - "RIOI_KEEPER_INT_EN_1", - "RIOI_O0", - "RIOI_O1", - "RIOI_ODELAY0_DATAOUT", - "RIOI_ODELAY0_ODATAIN", - "RIOI_ODELAY0_OFDLY0", - "RIOI_ODELAY0_OFDLY1", - "RIOI_ODELAY0_OFDLY2", - "RIOI_ODELAY1_DATAOUT", - "RIOI_ODELAY1_ODATAIN", - "RIOI_ODELAY1_OFDLY0", - "RIOI_ODELAY1_OFDLY1", - "RIOI_ODELAY1_OFDLY2", - "RIOI_OLOGIC0_CLKDIVF", - "RIOI_OLOGIC0_OFB", - "RIOI_OLOGIC0_OQ", - "RIOI_OLOGIC0_TFB", - "RIOI_OLOGIC0_TFB_LOCAL", - "RIOI_OLOGIC0_TQ", - "RIOI_OLOGIC1_CLKDIVF", - "RIOI_OLOGIC1_OFB", - "RIOI_OLOGIC1_OQ", - "RIOI_OLOGIC1_TFB", - "RIOI_OLOGIC1_TFB_LOCAL", - "RIOI_OLOGIC1_TQ", - "RIOI_OSIN10", - "RIOI_OSIN11", - "RIOI_OSIN20", - "RIOI_OSIN21", - "RIOI_OSOUT10", - "RIOI_OSOUT11", - "RIOI_OSOUT20", - "RIOI_OSOUT21", - "RIOI_PD_INT_EN_0", - "RIOI_PD_INT_EN_1", - "RIOI_PU_INT_EN_0", - "RIOI_PU_INT_EN_1", - "RIOI_T0", - "RIOI_T1" - ] + "wires": { + "IOI_BLOCK_OUTS0_0": null, + "IOI_BLOCK_OUTS0_1": null, + "IOI_BLOCK_OUTS1_0": null, + "IOI_BLOCK_OUTS1_1": null, + "IOI_BLOCK_OUTS2_0": null, + "IOI_BLOCK_OUTS2_1": null, + "IOI_BLOCK_OUTS3_0": null, + "IOI_BLOCK_OUTS3_1": null, + "IOI_BYP0_0": null, + "IOI_BYP0_1": null, + "IOI_BYP1_0": null, + "IOI_BYP1_1": null, + "IOI_BYP2_0": null, + "IOI_BYP2_1": null, + "IOI_BYP3_0": null, + "IOI_BYP3_1": null, + "IOI_BYP4_0": null, + "IOI_BYP4_1": null, + "IOI_BYP5_0": null, + "IOI_BYP5_1": null, + "IOI_BYP6_0": null, + "IOI_BYP6_1": null, + "IOI_BYP7_0": null, + "IOI_BYP7_1": null, + "IOI_CLK0_0": null, + "IOI_CLK0_1": null, + "IOI_CLK1_0": null, + "IOI_CLK1_1": null, + "IOI_CTRL0_0": null, + "IOI_CTRL0_1": null, + "IOI_CTRL1_0": null, + "IOI_CTRL1_1": null, + "IOI_DCI_DCIDONE": null, + "IOI_DCI_TSTCLK": null, + "IOI_DCI_TSTHLN": null, + "IOI_DCI_TSTHLP": null, + "IOI_DCI_TSTRST": null, + "IOI_DCI_TSTRST0": null, + "IOI_EE2A0_0": null, + "IOI_EE2A0_1": null, + "IOI_EE2A1_0": null, + "IOI_EE2A1_1": null, + "IOI_EE2A2_0": null, + "IOI_EE2A2_1": null, + "IOI_EE2A3_0": null, + "IOI_EE2A3_1": null, + "IOI_EE2BEG0_0": null, + "IOI_EE2BEG0_1": null, + "IOI_EE2BEG1_0": null, + "IOI_EE2BEG1_1": null, + "IOI_EE2BEG2_0": null, + "IOI_EE2BEG2_1": null, + "IOI_EE2BEG3_0": null, + "IOI_EE2BEG3_1": null, + "IOI_EE4A0_0": null, + "IOI_EE4A0_1": null, + "IOI_EE4A1_0": null, + "IOI_EE4A1_1": null, + "IOI_EE4A2_0": null, + "IOI_EE4A2_1": null, + "IOI_EE4A3_0": null, + "IOI_EE4A3_1": null, + "IOI_EE4B0_0": null, + "IOI_EE4B0_1": null, + "IOI_EE4B1_0": null, + "IOI_EE4B1_1": null, + "IOI_EE4B2_0": null, + "IOI_EE4B2_1": null, + "IOI_EE4B3_0": null, + "IOI_EE4B3_1": null, + "IOI_EE4BEG0_0": null, + "IOI_EE4BEG0_1": null, + "IOI_EE4BEG1_0": null, + "IOI_EE4BEG1_1": null, + "IOI_EE4BEG2_0": null, + "IOI_EE4BEG2_1": null, + "IOI_EE4BEG3_0": null, + "IOI_EE4BEG3_1": null, + "IOI_EE4C0_0": null, + "IOI_EE4C0_1": null, + "IOI_EE4C1_0": null, + "IOI_EE4C1_1": null, + "IOI_EE4C2_0": null, + "IOI_EE4C2_1": null, + "IOI_EE4C3_0": null, + "IOI_EE4C3_1": null, + "IOI_EL1BEG0_0": null, + "IOI_EL1BEG0_1": null, + "IOI_EL1BEG1_0": null, + "IOI_EL1BEG1_1": null, + "IOI_EL1BEG2_0": null, + "IOI_EL1BEG2_1": null, + "IOI_EL1BEG3_0": null, + "IOI_EL1BEG3_1": null, + "IOI_ER1BEG0_0": null, + "IOI_ER1BEG0_1": null, + "IOI_ER1BEG1_0": null, + "IOI_ER1BEG1_1": null, + "IOI_ER1BEG2_0": null, + "IOI_ER1BEG2_1": null, + "IOI_ER1BEG3_0": null, + "IOI_ER1BEG3_1": null, + "IOI_FAN0_0": null, + "IOI_FAN0_1": null, + "IOI_FAN1_0": null, + "IOI_FAN1_1": null, + "IOI_FAN2_0": null, + "IOI_FAN2_1": null, + "IOI_FAN3_0": null, + "IOI_FAN3_1": null, + "IOI_FAN4_0": null, + "IOI_FAN4_1": null, + "IOI_FAN5_0": null, + "IOI_FAN5_1": null, + "IOI_FAN6_0": null, + "IOI_FAN6_1": null, + "IOI_FAN7_0": null, + "IOI_FAN7_1": null, + "IOI_IDELAY0_C": null, + "IOI_IDELAY0_CE": null, + "IOI_IDELAY0_CINVCTRL": null, + "IOI_IDELAY0_CNTVALUEIN0": null, + "IOI_IDELAY0_CNTVALUEIN1": null, + "IOI_IDELAY0_CNTVALUEIN2": null, + "IOI_IDELAY0_CNTVALUEIN3": null, + "IOI_IDELAY0_CNTVALUEIN4": null, + "IOI_IDELAY0_CNTVALUEOUT0": null, + "IOI_IDELAY0_CNTVALUEOUT1": null, + "IOI_IDELAY0_CNTVALUEOUT2": null, + "IOI_IDELAY0_CNTVALUEOUT3": null, + "IOI_IDELAY0_CNTVALUEOUT4": null, + "IOI_IDELAY0_DATAIN": null, + "IOI_IDELAY0_INC": null, + "IOI_IDELAY0_LD": null, + "IOI_IDELAY0_LDPIPEEN": null, + "IOI_IDELAY0_REGRST": null, + "IOI_IDELAY1_C": null, + "IOI_IDELAY1_CE": null, + "IOI_IDELAY1_CINVCTRL": null, + "IOI_IDELAY1_CNTVALUEIN0": null, + "IOI_IDELAY1_CNTVALUEIN1": null, + "IOI_IDELAY1_CNTVALUEIN2": null, + "IOI_IDELAY1_CNTVALUEIN3": null, + "IOI_IDELAY1_CNTVALUEIN4": null, + "IOI_IDELAY1_CNTVALUEOUT0": null, + "IOI_IDELAY1_CNTVALUEOUT1": null, + "IOI_IDELAY1_CNTVALUEOUT2": null, + "IOI_IDELAY1_CNTVALUEOUT3": null, + "IOI_IDELAY1_CNTVALUEOUT4": null, + "IOI_IDELAY1_DATAIN": null, + "IOI_IDELAY1_INC": null, + "IOI_IDELAY1_LD": null, + "IOI_IDELAY1_LDPIPEEN": null, + "IOI_IDELAY1_REGRST": null, + "IOI_IDELAYCTRL_DNPULSEOUT": null, + "IOI_IDELAYCTRL_OUTN1": null, + "IOI_IDELAYCTRL_OUTN65": null, + "IOI_IDELAYCTRL_RDY": null, + "IOI_IDELAYCTRL_RST": null, + "IOI_IDELAYCTRL_UPPULSEOUT": null, + "IOI_ILOGIC0_BITSLIP": null, + "IOI_ILOGIC0_CE1": null, + "IOI_ILOGIC0_CE2": null, + "IOI_ILOGIC0_CLK": null, + "IOI_ILOGIC0_CLKB": null, + "IOI_ILOGIC0_CLKDIV": null, + "IOI_ILOGIC0_CLKDIVP": null, + "IOI_ILOGIC0_DYNCLKDIVPSEL": null, + "IOI_ILOGIC0_DYNCLKDIVSEL": null, + "IOI_ILOGIC0_DYNCLKSEL": null, + "IOI_ILOGIC0_O": null, + "IOI_ILOGIC0_OCLK": null, + "IOI_ILOGIC0_OCLKB": null, + "IOI_ILOGIC0_Q1": null, + "IOI_ILOGIC0_Q2": null, + "IOI_ILOGIC0_Q3": null, + "IOI_ILOGIC0_Q4": null, + "IOI_ILOGIC0_Q5": null, + "IOI_ILOGIC0_Q6": null, + "IOI_ILOGIC0_Q7": null, + "IOI_ILOGIC0_Q8": null, + "IOI_ILOGIC0_REV": null, + "IOI_ILOGIC0_SR": null, + "IOI_ILOGIC1_BITSLIP": null, + "IOI_ILOGIC1_CE1": null, + "IOI_ILOGIC1_CE2": null, + "IOI_ILOGIC1_CLK": null, + "IOI_ILOGIC1_CLKB": null, + "IOI_ILOGIC1_CLKDIV": null, + "IOI_ILOGIC1_CLKDIVP": null, + "IOI_ILOGIC1_DYNCLKDIVPSEL": null, + "IOI_ILOGIC1_DYNCLKDIVSEL": null, + "IOI_ILOGIC1_DYNCLKSEL": null, + "IOI_ILOGIC1_O": null, + "IOI_ILOGIC1_OCLK": null, + "IOI_ILOGIC1_OCLKB": null, + "IOI_ILOGIC1_Q1": null, + "IOI_ILOGIC1_Q2": null, + "IOI_ILOGIC1_Q3": null, + "IOI_ILOGIC1_Q4": null, + "IOI_ILOGIC1_Q5": null, + "IOI_ILOGIC1_Q6": null, + "IOI_ILOGIC1_Q7": null, + "IOI_ILOGIC1_Q8": null, + "IOI_ILOGIC1_REV": null, + "IOI_ILOGIC1_SR": null, + "IOI_IMUX0_0": null, + "IOI_IMUX0_1": null, + "IOI_IMUX10_0": null, + "IOI_IMUX10_1": null, + "IOI_IMUX11_0": null, + "IOI_IMUX11_1": null, + "IOI_IMUX12_0": null, + "IOI_IMUX12_1": null, + "IOI_IMUX13_0": null, + "IOI_IMUX13_1": null, + "IOI_IMUX14_0": null, + "IOI_IMUX14_1": null, + "IOI_IMUX15_0": null, + "IOI_IMUX15_1": null, + "IOI_IMUX16_0": null, + "IOI_IMUX16_1": null, + "IOI_IMUX17_0": null, + "IOI_IMUX17_1": null, + "IOI_IMUX18_0": null, + "IOI_IMUX18_1": null, + "IOI_IMUX19_0": null, + "IOI_IMUX19_1": null, + "IOI_IMUX1_0": null, + "IOI_IMUX1_1": null, + "IOI_IMUX20_0": null, + "IOI_IMUX20_1": null, + "IOI_IMUX21_0": null, + "IOI_IMUX21_1": null, + "IOI_IMUX22_0": null, + "IOI_IMUX22_1": null, + "IOI_IMUX23_0": null, + "IOI_IMUX23_1": null, + "IOI_IMUX24_0": null, + "IOI_IMUX24_1": null, + "IOI_IMUX25_0": null, + "IOI_IMUX25_1": null, + "IOI_IMUX26_0": null, + "IOI_IMUX26_1": null, + "IOI_IMUX27_0": null, + "IOI_IMUX27_1": null, + "IOI_IMUX28_0": null, + "IOI_IMUX28_1": null, + "IOI_IMUX29_0": null, + "IOI_IMUX29_1": null, + "IOI_IMUX2_0": null, + "IOI_IMUX2_1": null, + "IOI_IMUX30_0": null, + "IOI_IMUX30_1": null, + "IOI_IMUX31_0": null, + "IOI_IMUX31_1": null, + "IOI_IMUX32_0": null, + "IOI_IMUX32_1": null, + "IOI_IMUX33_0": null, + "IOI_IMUX33_1": null, + "IOI_IMUX34_0": null, + "IOI_IMUX34_1": null, + "IOI_IMUX35_0": null, + "IOI_IMUX35_1": null, + "IOI_IMUX36_0": null, + "IOI_IMUX36_1": null, + "IOI_IMUX37_0": null, + "IOI_IMUX37_1": null, + "IOI_IMUX38_0": null, + "IOI_IMUX38_1": null, + "IOI_IMUX39_0": null, + "IOI_IMUX39_1": null, + "IOI_IMUX3_0": null, + "IOI_IMUX3_1": null, + "IOI_IMUX40_0": null, + "IOI_IMUX40_1": null, + "IOI_IMUX41_0": null, + "IOI_IMUX41_1": null, + "IOI_IMUX42_0": null, + "IOI_IMUX42_1": null, + "IOI_IMUX43_0": null, + "IOI_IMUX43_1": null, + "IOI_IMUX44_0": null, + "IOI_IMUX44_1": null, + "IOI_IMUX45_0": null, + "IOI_IMUX45_1": null, + "IOI_IMUX46_0": null, + "IOI_IMUX46_1": null, + "IOI_IMUX47_0": null, + "IOI_IMUX47_1": null, + "IOI_IMUX4_0": null, + "IOI_IMUX4_1": null, + "IOI_IMUX5_0": null, + "IOI_IMUX5_1": null, + "IOI_IMUX6_0": null, + "IOI_IMUX6_1": null, + "IOI_IMUX7_0": null, + "IOI_IMUX7_1": null, + "IOI_IMUX8_0": null, + "IOI_IMUX8_1": null, + "IOI_IMUX9_0": null, + "IOI_IMUX9_1": null, + "IOI_IMUX_RC0": null, + "IOI_IMUX_RC1": null, + "IOI_IMUX_RC2": null, + "IOI_IMUX_RC3": null, + "IOI_INT_DCI_EN": null, + "IOI_IOCLK0": null, + "IOI_IOCLK1": null, + "IOI_IOCLK2": null, + "IOI_IOCLK3": null, + "IOI_LEAF_GCLK0": null, + "IOI_LEAF_GCLK1": null, + "IOI_LEAF_GCLK2": null, + "IOI_LEAF_GCLK3": null, + "IOI_LEAF_GCLK4": null, + "IOI_LEAF_GCLK5": null, + "IOI_LH10_0": null, + "IOI_LH10_1": null, + "IOI_LH11_0": null, + "IOI_LH11_1": null, + "IOI_LH12_0": null, + "IOI_LH12_1": null, + "IOI_LH1_0": null, + "IOI_LH1_1": null, + "IOI_LH2_0": null, + "IOI_LH2_1": null, + "IOI_LH3_0": null, + "IOI_LH3_1": null, + "IOI_LH4_0": null, + "IOI_LH4_1": null, + "IOI_LH5_0": null, + "IOI_LH5_1": null, + "IOI_LH6_0": null, + "IOI_LH6_1": null, + "IOI_LH7_0": null, + "IOI_LH7_1": null, + "IOI_LH8_0": null, + "IOI_LH8_1": null, + "IOI_LH9_0": null, + "IOI_LH9_1": null, + "IOI_LOGIC_OUTS0_0": null, + "IOI_LOGIC_OUTS0_1": null, + "IOI_LOGIC_OUTS10_0": null, + "IOI_LOGIC_OUTS10_1": null, + "IOI_LOGIC_OUTS11_0": null, + "IOI_LOGIC_OUTS11_1": null, + "IOI_LOGIC_OUTS12_0": null, + "IOI_LOGIC_OUTS12_1": null, + "IOI_LOGIC_OUTS13_0": null, + "IOI_LOGIC_OUTS13_1": null, + "IOI_LOGIC_OUTS14_0": null, + "IOI_LOGIC_OUTS14_1": null, + "IOI_LOGIC_OUTS15_0": null, + "IOI_LOGIC_OUTS15_1": null, + "IOI_LOGIC_OUTS16_0": null, + "IOI_LOGIC_OUTS16_1": null, + "IOI_LOGIC_OUTS17_0": null, + "IOI_LOGIC_OUTS17_1": null, + "IOI_LOGIC_OUTS18_0": null, + "IOI_LOGIC_OUTS18_1": null, + "IOI_LOGIC_OUTS19_0": null, + "IOI_LOGIC_OUTS19_1": null, + "IOI_LOGIC_OUTS1_0": null, + "IOI_LOGIC_OUTS1_1": null, + "IOI_LOGIC_OUTS20_0": null, + "IOI_LOGIC_OUTS20_1": null, + "IOI_LOGIC_OUTS21_0": null, + "IOI_LOGIC_OUTS21_1": null, + "IOI_LOGIC_OUTS22_0": null, + "IOI_LOGIC_OUTS22_1": null, + "IOI_LOGIC_OUTS23_0": null, + "IOI_LOGIC_OUTS23_1": null, + "IOI_LOGIC_OUTS2_0": null, + "IOI_LOGIC_OUTS2_1": null, + "IOI_LOGIC_OUTS3_0": null, + "IOI_LOGIC_OUTS3_1": null, + "IOI_LOGIC_OUTS4_0": null, + "IOI_LOGIC_OUTS4_1": null, + "IOI_LOGIC_OUTS5_0": null, + "IOI_LOGIC_OUTS5_1": null, + "IOI_LOGIC_OUTS6_0": null, + "IOI_LOGIC_OUTS6_1": null, + "IOI_LOGIC_OUTS7_0": null, + "IOI_LOGIC_OUTS7_1": null, + "IOI_LOGIC_OUTS8_0": null, + "IOI_LOGIC_OUTS8_1": null, + "IOI_LOGIC_OUTS9_0": null, + "IOI_LOGIC_OUTS9_1": null, + "IOI_MONITOR_N": null, + "IOI_MONITOR_P": null, + "IOI_NE2A0_0": null, + "IOI_NE2A0_1": null, + "IOI_NE2A1_0": null, + "IOI_NE2A1_1": null, + "IOI_NE2A2_0": null, + "IOI_NE2A2_1": null, + "IOI_NE2A3_0": null, + "IOI_NE2A3_1": null, + "IOI_NE4BEG0_0": null, + "IOI_NE4BEG0_1": null, + "IOI_NE4BEG1_0": null, + "IOI_NE4BEG1_1": null, + "IOI_NE4BEG2_0": null, + "IOI_NE4BEG2_1": null, + "IOI_NE4BEG3_0": null, + "IOI_NE4BEG3_1": null, + "IOI_NE4C0_0": null, + "IOI_NE4C0_1": null, + "IOI_NE4C1_0": null, + "IOI_NE4C1_1": null, + "IOI_NE4C2_0": null, + "IOI_NE4C2_1": null, + "IOI_NE4C3_0": null, + "IOI_NE4C3_1": null, + "IOI_NW2A0_0": null, + "IOI_NW2A0_1": null, + "IOI_NW2A1_0": null, + "IOI_NW2A1_1": null, + "IOI_NW2A2_0": null, + "IOI_NW2A2_1": null, + "IOI_NW2A3_0": null, + "IOI_NW2A3_1": null, + "IOI_NW4A0_0": null, + "IOI_NW4A0_1": null, + "IOI_NW4A1_0": null, + "IOI_NW4A1_1": null, + "IOI_NW4A2_0": null, + "IOI_NW4A2_1": null, + "IOI_NW4A3_0": null, + "IOI_NW4A3_1": null, + "IOI_NW4END0_0": null, + "IOI_NW4END0_1": null, + "IOI_NW4END1_0": null, + "IOI_NW4END1_1": null, + "IOI_NW4END2_0": null, + "IOI_NW4END2_1": null, + "IOI_NW4END3_0": null, + "IOI_NW4END3_1": null, + "IOI_OCLKM_0": null, + "IOI_OCLKM_1": null, + "IOI_OCLK_0": null, + "IOI_OCLK_1": null, + "IOI_ODELAY0_C": null, + "IOI_ODELAY0_CE": null, + "IOI_ODELAY0_CINVCTRL": null, + "IOI_ODELAY0_CLKIN": null, + "IOI_ODELAY0_CNTVALUEIN0": null, + "IOI_ODELAY0_CNTVALUEIN1": null, + "IOI_ODELAY0_CNTVALUEIN2": null, + "IOI_ODELAY0_CNTVALUEIN3": null, + "IOI_ODELAY0_CNTVALUEIN4": null, + "IOI_ODELAY0_CNTVALUEOUT0": null, + "IOI_ODELAY0_CNTVALUEOUT1": null, + "IOI_ODELAY0_CNTVALUEOUT2": null, + "IOI_ODELAY0_CNTVALUEOUT3": null, + "IOI_ODELAY0_CNTVALUEOUT4": null, + "IOI_ODELAY0_INC": null, + "IOI_ODELAY0_LD": null, + "IOI_ODELAY0_LDPIPEEN": null, + "IOI_ODELAY0_REGRST": null, + "IOI_ODELAY1_C": null, + "IOI_ODELAY1_CE": null, + "IOI_ODELAY1_CINVCTRL": null, + "IOI_ODELAY1_CLKIN": null, + "IOI_ODELAY1_CNTVALUEIN0": null, + "IOI_ODELAY1_CNTVALUEIN1": null, + "IOI_ODELAY1_CNTVALUEIN2": null, + "IOI_ODELAY1_CNTVALUEIN3": null, + "IOI_ODELAY1_CNTVALUEIN4": null, + "IOI_ODELAY1_CNTVALUEOUT0": null, + "IOI_ODELAY1_CNTVALUEOUT1": null, + "IOI_ODELAY1_CNTVALUEOUT2": null, + "IOI_ODELAY1_CNTVALUEOUT3": null, + "IOI_ODELAY1_CNTVALUEOUT4": null, + "IOI_ODELAY1_INC": null, + "IOI_ODELAY1_LD": null, + "IOI_ODELAY1_LDPIPEEN": null, + "IOI_ODELAY1_REGRST": null, + "IOI_OLOGIC0_CLK": null, + "IOI_OLOGIC0_CLKB": null, + "IOI_OLOGIC0_CLKDIV": null, + "IOI_OLOGIC0_CLKDIVB": null, + "IOI_OLOGIC0_CLKDIVFB": null, + "IOI_OLOGIC0_D1": null, + "IOI_OLOGIC0_D2": null, + "IOI_OLOGIC0_D3": null, + "IOI_OLOGIC0_D4": null, + "IOI_OLOGIC0_D5": null, + "IOI_OLOGIC0_D6": null, + "IOI_OLOGIC0_D7": null, + "IOI_OLOGIC0_D8": null, + "IOI_OLOGIC0_IOCLKGLITCH": null, + "IOI_OLOGIC0_OCE": null, + "IOI_OLOGIC0_REV": null, + "IOI_OLOGIC0_SR": null, + "IOI_OLOGIC0_T1": null, + "IOI_OLOGIC0_T2": null, + "IOI_OLOGIC0_T3": null, + "IOI_OLOGIC0_T4": null, + "IOI_OLOGIC0_TBYTEIN": null, + "IOI_OLOGIC0_TBYTEOUT": null, + "IOI_OLOGIC0_TCE": null, + "IOI_OLOGIC1_CLK": null, + "IOI_OLOGIC1_CLKB": null, + "IOI_OLOGIC1_CLKDIV": null, + "IOI_OLOGIC1_CLKDIVB": null, + "IOI_OLOGIC1_CLKDIVFB": null, + "IOI_OLOGIC1_D1": null, + "IOI_OLOGIC1_D2": null, + "IOI_OLOGIC1_D3": null, + "IOI_OLOGIC1_D4": null, + "IOI_OLOGIC1_D5": null, + "IOI_OLOGIC1_D6": null, + "IOI_OLOGIC1_D7": null, + "IOI_OLOGIC1_D8": null, + "IOI_OLOGIC1_IOCLKGLITCH": null, + "IOI_OLOGIC1_OCE": null, + "IOI_OLOGIC1_REV": null, + "IOI_OLOGIC1_SR": null, + "IOI_OLOGIC1_T1": null, + "IOI_OLOGIC1_T2": null, + "IOI_OLOGIC1_T3": null, + "IOI_OLOGIC1_T4": null, + "IOI_OLOGIC1_TBYTEIN": null, + "IOI_OLOGIC1_TBYTEOUT": null, + "IOI_OLOGIC1_TCE": null, + "IOI_PHASER_TO_IO_ICLK": null, + "IOI_PHASER_TO_IO_ICLKDIV": null, + "IOI_PHASER_TO_IO_ICLKDIV_0": null, + "IOI_PHASER_TO_IO_ICLK_0": null, + "IOI_PHASER_TO_IO_OCLK": null, + "IOI_PHASER_TO_IO_OCLK1X_90": null, + "IOI_PHASER_TO_IO_OCLK1X_90_0": null, + "IOI_PHASER_TO_IO_OCLKDIV": null, + "IOI_PHASER_TO_IO_OCLKDIV_0": null, + "IOI_PHASER_TO_IO_OCLK_0": null, + "IOI_RCLK_DIV_CE0": null, + "IOI_RCLK_DIV_CE1": null, + "IOI_RCLK_DIV_CE2": null, + "IOI_RCLK_DIV_CE2_1": null, + "IOI_RCLK_DIV_CE3": null, + "IOI_RCLK_DIV_CE3_1": null, + "IOI_RCLK_DIV_CLR0": null, + "IOI_RCLK_DIV_CLR0_1": null, + "IOI_RCLK_DIV_CLR1": null, + "IOI_RCLK_DIV_CLR1_1": null, + "IOI_RCLK_DIV_CLR2": null, + "IOI_RCLK_DIV_CLR3": null, + "IOI_RCLK_FORIO0": null, + "IOI_RCLK_FORIO1": null, + "IOI_RCLK_FORIO2": null, + "IOI_RCLK_FORIO3": null, + "IOI_SE2A0_0": null, + "IOI_SE2A0_1": null, + "IOI_SE2A1_0": null, + "IOI_SE2A1_1": null, + "IOI_SE2A2_0": null, + "IOI_SE2A2_1": null, + "IOI_SE2A3_0": null, + "IOI_SE2A3_1": null, + "IOI_SE4BEG0_0": null, + "IOI_SE4BEG0_1": null, + "IOI_SE4BEG1_0": null, + "IOI_SE4BEG1_1": null, + "IOI_SE4BEG2_0": null, + "IOI_SE4BEG2_1": null, + "IOI_SE4BEG3_0": null, + "IOI_SE4BEG3_1": null, + "IOI_SE4C0_0": null, + "IOI_SE4C0_1": null, + "IOI_SE4C1_0": null, + "IOI_SE4C1_1": null, + "IOI_SE4C2_0": null, + "IOI_SE4C2_1": null, + "IOI_SE4C3_0": null, + "IOI_SE4C3_1": null, + "IOI_SW2A0_0": null, + "IOI_SW2A0_1": null, + "IOI_SW2A1_0": null, + "IOI_SW2A1_1": null, + "IOI_SW2A2_0": null, + "IOI_SW2A2_1": null, + "IOI_SW2A3_0": null, + "IOI_SW2A3_1": null, + "IOI_SW4A0_0": null, + "IOI_SW4A0_1": null, + "IOI_SW4A1_0": null, + "IOI_SW4A1_1": null, + "IOI_SW4A2_0": null, + "IOI_SW4A2_1": null, + "IOI_SW4A3_0": null, + "IOI_SW4A3_1": null, + "IOI_SW4END0_0": null, + "IOI_SW4END0_1": null, + "IOI_SW4END1_0": null, + "IOI_SW4END1_1": null, + "IOI_SW4END2_0": null, + "IOI_SW4END2_1": null, + "IOI_SW4END3_0": null, + "IOI_SW4END3_1": null, + "IOI_TBYTEIN_TERM": null, + "IOI_WL1END0_0": null, + "IOI_WL1END0_1": null, + "IOI_WL1END1_0": null, + "IOI_WL1END1_1": null, + "IOI_WL1END2_0": null, + "IOI_WL1END2_1": null, + "IOI_WL1END3_0": null, + "IOI_WL1END3_1": null, + "IOI_WR1END0_0": null, + "IOI_WR1END0_1": null, + "IOI_WR1END1_0": null, + "IOI_WR1END1_1": null, + "IOI_WR1END2_0": null, + "IOI_WR1END2_1": null, + "IOI_WR1END3_0": null, + "IOI_WR1END3_1": null, + "IOI_WW2A0_0": null, + "IOI_WW2A0_1": null, + "IOI_WW2A1_0": null, + "IOI_WW2A1_1": null, + "IOI_WW2A2_0": null, + "IOI_WW2A2_1": null, + "IOI_WW2A3_0": null, + "IOI_WW2A3_1": null, + "IOI_WW2END0_0": null, + "IOI_WW2END0_1": null, + "IOI_WW2END1_0": null, + "IOI_WW2END1_1": null, + "IOI_WW2END2_0": null, + "IOI_WW2END2_1": null, + "IOI_WW2END3_0": null, + "IOI_WW2END3_1": null, + "IOI_WW4A0_0": null, + "IOI_WW4A0_1": null, + "IOI_WW4A1_0": null, + "IOI_WW4A1_1": null, + "IOI_WW4A2_0": null, + "IOI_WW4A2_1": null, + "IOI_WW4A3_0": null, + "IOI_WW4A3_1": null, + "IOI_WW4B0_0": null, + "IOI_WW4B0_1": null, + "IOI_WW4B1_0": null, + "IOI_WW4B1_1": null, + "IOI_WW4B2_0": null, + "IOI_WW4B2_1": null, + "IOI_WW4B3_0": null, + "IOI_WW4B3_1": null, + "IOI_WW4C0_0": null, + "IOI_WW4C0_1": null, + "IOI_WW4C1_0": null, + "IOI_WW4C1_1": null, + "IOI_WW4C2_0": null, + "IOI_WW4C2_1": null, + "IOI_WW4C3_0": null, + "IOI_WW4C3_1": null, + "IOI_WW4END0_0": null, + "IOI_WW4END0_1": null, + "IOI_WW4END1_0": null, + "IOI_WW4END1_1": null, + "IOI_WW4END2_0": null, + "IOI_WW4END2_1": null, + "IOI_WW4END3_0": null, + "IOI_WW4END3_1": null, + "RIOI_DCI_T_TERM0": null, + "RIOI_DCI_T_TERM1": null, + "RIOI_DIFF_TERM_INT_EN": null, + "RIOI_I0": null, + "RIOI_I1": null, + "RIOI_I2GCLK_BOT1": null, + "RIOI_I2GCLK_TOP0": null, + "RIOI_I2GCLK_TOP1": null, + "RIOI_IBUF0": null, + "RIOI_IBUF1": null, + "RIOI_IBUF_DISABLE0": null, + "RIOI_IBUF_DISABLE1": null, + "RIOI_IDELAY0_DATAOUT": null, + "RIOI_IDELAY0_IDATAIN": null, + "RIOI_IDELAY0_IFDLY0": null, + "RIOI_IDELAY0_IFDLY1": null, + "RIOI_IDELAY0_IFDLY2": null, + "RIOI_IDELAY1_DATAOUT": null, + "RIOI_IDELAY1_IDATAIN": null, + "RIOI_IDELAY1_IFDLY0": null, + "RIOI_IDELAY1_IFDLY1": null, + "RIOI_IDELAY1_IFDLY2": null, + "RIOI_ILOGIC0_D": null, + "RIOI_ILOGIC0_DDLY": null, + "RIOI_ILOGIC0_OFB": null, + "RIOI_ILOGIC0_TFB": null, + "RIOI_ILOGIC1_D": null, + "RIOI_ILOGIC1_DDLY": null, + "RIOI_ILOGIC1_OFB": null, + "RIOI_ILOGIC1_TFB": null, + "RIOI_ISIN10": null, + "RIOI_ISIN11": null, + "RIOI_ISIN20": null, + "RIOI_ISIN21": null, + "RIOI_ISOUT10": null, + "RIOI_ISOUT11": null, + "RIOI_ISOUT20": null, + "RIOI_ISOUT21": null, + "RIOI_KEEPER_INT_EN_0": null, + "RIOI_KEEPER_INT_EN_1": null, + "RIOI_O0": null, + "RIOI_O1": null, + "RIOI_ODELAY0_DATAOUT": null, + "RIOI_ODELAY0_ODATAIN": null, + "RIOI_ODELAY0_OFDLY0": null, + "RIOI_ODELAY0_OFDLY1": null, + "RIOI_ODELAY0_OFDLY2": null, + "RIOI_ODELAY1_DATAOUT": null, + "RIOI_ODELAY1_ODATAIN": null, + "RIOI_ODELAY1_OFDLY0": null, + "RIOI_ODELAY1_OFDLY1": null, + "RIOI_ODELAY1_OFDLY2": null, + "RIOI_OLOGIC0_CLKDIVF": null, + "RIOI_OLOGIC0_OFB": null, + "RIOI_OLOGIC0_OQ": null, + "RIOI_OLOGIC0_TFB": null, + "RIOI_OLOGIC0_TFB_LOCAL": null, + "RIOI_OLOGIC0_TQ": null, + "RIOI_OLOGIC1_CLKDIVF": null, + "RIOI_OLOGIC1_OFB": null, + "RIOI_OLOGIC1_OQ": null, + "RIOI_OLOGIC1_TFB": null, + "RIOI_OLOGIC1_TFB_LOCAL": null, + "RIOI_OLOGIC1_TQ": null, + "RIOI_OSIN10": null, + "RIOI_OSIN11": null, + "RIOI_OSIN20": null, + "RIOI_OSIN21": null, + "RIOI_OSOUT10": null, + "RIOI_OSOUT11": null, + "RIOI_OSOUT20": null, + "RIOI_OSOUT21": null, + "RIOI_PD_INT_EN_0": null, + "RIOI_PD_INT_EN_1": null, + "RIOI_PU_INT_EN_0": null, + "RIOI_PU_INT_EN_1": null, + "RIOI_T0": null, + "RIOI_T1": null + } } diff --git a/kintex7/tile_type_R_TERM_INT.json b/kintex7/tile_type_R_TERM_INT.json index 67209e5..498c25b 100644 --- a/kintex7/tile_type_R_TERM_INT.json +++ b/kintex7/tile_type_R_TERM_INT.json @@ -2,172 +2,358 @@ "pips": {}, "sites": [], "tile_type": "R_TERM_INT", - "wires": [ - "L_TERM_INT_DQS_IOTOPHASER", - "L_TERM_INT_PHASER_TO_IO_ICLK", - "L_TERM_INT_PHASER_TO_IO_ICLKDIV", - "L_TERM_INT_PHASER_TO_IO_OCLK", - "L_TERM_INT_PHASER_TO_IO_OCLK1X_90", - "L_TERM_INT_PHASER_TO_IO_OCLKDIV", - "R_TERM_INT_LH0", - "R_TERM_INT_LH1", - "R_TERM_INT_LH2", - "R_TERM_INT_LH3", - "R_TERM_INT_LH4", - "R_TERM_INT_LH5", - "R_TERM_INT_NW2A0", - "R_TERM_INT_NW2A1", - "R_TERM_INT_NW2A2", - "R_TERM_INT_NW2A3", - "R_TERM_INT_NW4A0", - "R_TERM_INT_NW4A1", - "R_TERM_INT_NW4A2", - "R_TERM_INT_NW4A3", - "R_TERM_INT_NW4END0", - "R_TERM_INT_NW4END1", - "R_TERM_INT_NW4END2", - "R_TERM_INT_NW4END3", - "R_TERM_INT_SW2A0", - "R_TERM_INT_SW2A1", - "R_TERM_INT_SW2A2", - "R_TERM_INT_SW2A3", - "R_TERM_INT_SW4A0", - "R_TERM_INT_SW4A1", - "R_TERM_INT_SW4A2", - "R_TERM_INT_SW4A3", - "R_TERM_INT_SW4END0", - "R_TERM_INT_SW4END1", - "R_TERM_INT_SW4END2", - "R_TERM_INT_SW4END3", - "R_TERM_INT_WL1END0", - "R_TERM_INT_WL1END1", - "R_TERM_INT_WL1END2", - "R_TERM_INT_WL1END3", - "R_TERM_INT_WR1END0", - "R_TERM_INT_WR1END1", - "R_TERM_INT_WR1END2", - "R_TERM_INT_WR1END3", - "R_TERM_INT_WW2A0", - "R_TERM_INT_WW2A1", - "R_TERM_INT_WW2A2", - "R_TERM_INT_WW2A3", - "R_TERM_INT_WW2END0", - "R_TERM_INT_WW2END1", - "R_TERM_INT_WW2END2", - "R_TERM_INT_WW2END3", - "R_TERM_INT_WW4A0", - "R_TERM_INT_WW4A1", - "R_TERM_INT_WW4A2", - "R_TERM_INT_WW4A3", - "R_TERM_INT_WW4B0", - "R_TERM_INT_WW4B1", - "R_TERM_INT_WW4B2", - "R_TERM_INT_WW4B3", - "R_TERM_INT_WW4C0", - "R_TERM_INT_WW4C1", - "R_TERM_INT_WW4C2", - "R_TERM_INT_WW4C3", - "R_TERM_INT_WW4END0", - "R_TERM_INT_WW4END1", - "R_TERM_INT_WW4END2", - "R_TERM_INT_WW4END3", - "TERM_INT_BLOCK_OUTS_L_B0", - "TERM_INT_BLOCK_OUTS_L_B1", - "TERM_INT_BLOCK_OUTS_L_B2", - "TERM_INT_BLOCK_OUTS_L_B3", - "TERM_INT_BYP0", - "TERM_INT_BYP1", - "TERM_INT_BYP2", - "TERM_INT_BYP3", - "TERM_INT_BYP4", - "TERM_INT_BYP5", - "TERM_INT_BYP6", - "TERM_INT_BYP7", - "TERM_INT_CLK0", - "TERM_INT_CLK1", - "TERM_INT_CTRL0", - "TERM_INT_CTRL1", - "TERM_INT_FAN0", - "TERM_INT_FAN1", - "TERM_INT_FAN2", - "TERM_INT_FAN3", - "TERM_INT_FAN4", - "TERM_INT_FAN5", - "TERM_INT_FAN6", - "TERM_INT_FAN7", - "TERM_INT_IMUX0", - "TERM_INT_IMUX1", - "TERM_INT_IMUX10", - "TERM_INT_IMUX11", - "TERM_INT_IMUX12", - "TERM_INT_IMUX13", - "TERM_INT_IMUX14", - "TERM_INT_IMUX15", - "TERM_INT_IMUX16", - "TERM_INT_IMUX17", - "TERM_INT_IMUX18", - "TERM_INT_IMUX19", - "TERM_INT_IMUX2", - "TERM_INT_IMUX20", - "TERM_INT_IMUX21", - "TERM_INT_IMUX22", - "TERM_INT_IMUX23", - "TERM_INT_IMUX24", - "TERM_INT_IMUX25", - "TERM_INT_IMUX26", - "TERM_INT_IMUX27", - "TERM_INT_IMUX28", - "TERM_INT_IMUX29", - "TERM_INT_IMUX3", - "TERM_INT_IMUX30", - "TERM_INT_IMUX31", - "TERM_INT_IMUX32", - "TERM_INT_IMUX33", - "TERM_INT_IMUX34", - "TERM_INT_IMUX35", - "TERM_INT_IMUX36", - "TERM_INT_IMUX37", - "TERM_INT_IMUX38", - "TERM_INT_IMUX39", - "TERM_INT_IMUX4", - "TERM_INT_IMUX40", - "TERM_INT_IMUX41", - "TERM_INT_IMUX42", - "TERM_INT_IMUX43", - "TERM_INT_IMUX44", - "TERM_INT_IMUX45", - "TERM_INT_IMUX46", - "TERM_INT_IMUX47", - "TERM_INT_IMUX5", - "TERM_INT_IMUX6", - "TERM_INT_IMUX7", - "TERM_INT_IMUX8", - "TERM_INT_IMUX9", - "TERM_INT_LOGIC_OUTS_L_B0", - "TERM_INT_LOGIC_OUTS_L_B1", - "TERM_INT_LOGIC_OUTS_L_B10", - "TERM_INT_LOGIC_OUTS_L_B11", - "TERM_INT_LOGIC_OUTS_L_B12", - "TERM_INT_LOGIC_OUTS_L_B13", - "TERM_INT_LOGIC_OUTS_L_B14", - "TERM_INT_LOGIC_OUTS_L_B15", - "TERM_INT_LOGIC_OUTS_L_B16", - "TERM_INT_LOGIC_OUTS_L_B17", - "TERM_INT_LOGIC_OUTS_L_B18", - "TERM_INT_LOGIC_OUTS_L_B19", - "TERM_INT_LOGIC_OUTS_L_B2", - "TERM_INT_LOGIC_OUTS_L_B20", - "TERM_INT_LOGIC_OUTS_L_B21", - "TERM_INT_LOGIC_OUTS_L_B22", - "TERM_INT_LOGIC_OUTS_L_B23", - "TERM_INT_LOGIC_OUTS_L_B3", - "TERM_INT_LOGIC_OUTS_L_B4", - "TERM_INT_LOGIC_OUTS_L_B5", - "TERM_INT_LOGIC_OUTS_L_B6", - "TERM_INT_LOGIC_OUTS_L_B7", - "TERM_INT_LOGIC_OUTS_L_B8", - "TERM_INT_LOGIC_OUTS_L_B9", - "TERM_INT_MONITOR_N", - "TERM_INT_MONITOR_P" - ] + "wires": { + "L_TERM_INT_DQS_IOTOPHASER": null, + "L_TERM_INT_PHASER_TO_IO_ICLK": null, + "L_TERM_INT_PHASER_TO_IO_ICLKDIV": null, + "L_TERM_INT_PHASER_TO_IO_OCLK": null, + "L_TERM_INT_PHASER_TO_IO_OCLK1X_90": null, + "L_TERM_INT_PHASER_TO_IO_OCLKDIV": null, + "R_TERM_INT_LH0": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH1": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH2": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH3": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH4": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH5": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_NW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END3": { + "cap": "4.200", + "res": "87.290" + }, + "TERM_INT_BLOCK_OUTS_L_B0": null, + "TERM_INT_BLOCK_OUTS_L_B1": null, + "TERM_INT_BLOCK_OUTS_L_B2": null, + "TERM_INT_BLOCK_OUTS_L_B3": null, + "TERM_INT_BYP0": null, + "TERM_INT_BYP1": null, + "TERM_INT_BYP2": null, + "TERM_INT_BYP3": null, + "TERM_INT_BYP4": null, + "TERM_INT_BYP5": null, + "TERM_INT_BYP6": null, + "TERM_INT_BYP7": null, + "TERM_INT_CLK0": null, + "TERM_INT_CLK1": null, + "TERM_INT_CTRL0": null, + "TERM_INT_CTRL1": null, + "TERM_INT_FAN0": null, + "TERM_INT_FAN1": null, + "TERM_INT_FAN2": null, + "TERM_INT_FAN3": null, + "TERM_INT_FAN4": null, + "TERM_INT_FAN5": null, + "TERM_INT_FAN6": null, + "TERM_INT_FAN7": null, + "TERM_INT_IMUX0": null, + "TERM_INT_IMUX1": null, + "TERM_INT_IMUX10": null, + "TERM_INT_IMUX11": null, + "TERM_INT_IMUX12": null, + "TERM_INT_IMUX13": null, + "TERM_INT_IMUX14": null, + "TERM_INT_IMUX15": null, + "TERM_INT_IMUX16": null, + "TERM_INT_IMUX17": null, + "TERM_INT_IMUX18": null, + "TERM_INT_IMUX19": null, + "TERM_INT_IMUX2": null, + "TERM_INT_IMUX20": null, + "TERM_INT_IMUX21": null, + "TERM_INT_IMUX22": null, + "TERM_INT_IMUX23": null, + "TERM_INT_IMUX24": null, + "TERM_INT_IMUX25": null, + "TERM_INT_IMUX26": null, + "TERM_INT_IMUX27": null, + "TERM_INT_IMUX28": null, + "TERM_INT_IMUX29": null, + "TERM_INT_IMUX3": null, + "TERM_INT_IMUX30": null, + "TERM_INT_IMUX31": null, + "TERM_INT_IMUX32": null, + "TERM_INT_IMUX33": null, + "TERM_INT_IMUX34": null, + "TERM_INT_IMUX35": null, + "TERM_INT_IMUX36": null, + "TERM_INT_IMUX37": null, + "TERM_INT_IMUX38": null, + "TERM_INT_IMUX39": null, + "TERM_INT_IMUX4": null, + "TERM_INT_IMUX40": null, + "TERM_INT_IMUX41": null, + "TERM_INT_IMUX42": null, + "TERM_INT_IMUX43": null, + "TERM_INT_IMUX44": null, + "TERM_INT_IMUX45": null, + "TERM_INT_IMUX46": null, + "TERM_INT_IMUX47": null, + "TERM_INT_IMUX5": null, + "TERM_INT_IMUX6": null, + "TERM_INT_IMUX7": null, + "TERM_INT_IMUX8": null, + "TERM_INT_IMUX9": null, + "TERM_INT_LOGIC_OUTS_L_B0": null, + "TERM_INT_LOGIC_OUTS_L_B1": null, + "TERM_INT_LOGIC_OUTS_L_B10": null, + "TERM_INT_LOGIC_OUTS_L_B11": null, + "TERM_INT_LOGIC_OUTS_L_B12": null, + "TERM_INT_LOGIC_OUTS_L_B13": null, + "TERM_INT_LOGIC_OUTS_L_B14": null, + "TERM_INT_LOGIC_OUTS_L_B15": null, + "TERM_INT_LOGIC_OUTS_L_B16": null, + "TERM_INT_LOGIC_OUTS_L_B17": null, + "TERM_INT_LOGIC_OUTS_L_B18": null, + "TERM_INT_LOGIC_OUTS_L_B19": null, + "TERM_INT_LOGIC_OUTS_L_B2": null, + "TERM_INT_LOGIC_OUTS_L_B20": null, + "TERM_INT_LOGIC_OUTS_L_B21": null, + "TERM_INT_LOGIC_OUTS_L_B22": null, + "TERM_INT_LOGIC_OUTS_L_B23": null, + "TERM_INT_LOGIC_OUTS_L_B3": null, + "TERM_INT_LOGIC_OUTS_L_B4": null, + "TERM_INT_LOGIC_OUTS_L_B5": null, + "TERM_INT_LOGIC_OUTS_L_B6": null, + "TERM_INT_LOGIC_OUTS_L_B7": null, + "TERM_INT_LOGIC_OUTS_L_B8": null, + "TERM_INT_LOGIC_OUTS_L_B9": null, + "TERM_INT_MONITOR_N": null, + "TERM_INT_MONITOR_P": null + } } diff --git a/kintex7/tile_type_R_TERM_INT_GTX.json b/kintex7/tile_type_R_TERM_INT_GTX.json index 7e99de0..69f9103 100644 --- a/kintex7/tile_type_R_TERM_INT_GTX.json +++ b/kintex7/tile_type_R_TERM_INT_GTX.json @@ -2,160 +2,346 @@ "pips": {}, "sites": [], "tile_type": "R_TERM_INT_GTX", - "wires": [ - "R_TERM_INT_GTX_BYP0", - "R_TERM_INT_GTX_BYP1", - "R_TERM_INT_GTX_BYP2", - "R_TERM_INT_GTX_BYP3", - "R_TERM_INT_GTX_BYP4", - "R_TERM_INT_GTX_BYP5", - "R_TERM_INT_GTX_BYP6", - "R_TERM_INT_GTX_BYP7", - "R_TERM_INT_GTX_CLK0", - "R_TERM_INT_GTX_CLK1", - "R_TERM_INT_GTX_CTRL0", - "R_TERM_INT_GTX_CTRL1", - "R_TERM_INT_GTX_FAN0", - "R_TERM_INT_GTX_FAN1", - "R_TERM_INT_GTX_FAN2", - "R_TERM_INT_GTX_FAN3", - "R_TERM_INT_GTX_FAN4", - "R_TERM_INT_GTX_FAN5", - "R_TERM_INT_GTX_FAN6", - "R_TERM_INT_GTX_FAN7", - "R_TERM_INT_GTX_IMUX0", - "R_TERM_INT_GTX_IMUX1", - "R_TERM_INT_GTX_IMUX10", - "R_TERM_INT_GTX_IMUX11", - "R_TERM_INT_GTX_IMUX12", - "R_TERM_INT_GTX_IMUX13", - "R_TERM_INT_GTX_IMUX14", - "R_TERM_INT_GTX_IMUX15", - "R_TERM_INT_GTX_IMUX16", - "R_TERM_INT_GTX_IMUX17", - "R_TERM_INT_GTX_IMUX18", - "R_TERM_INT_GTX_IMUX19", - "R_TERM_INT_GTX_IMUX2", - "R_TERM_INT_GTX_IMUX20", - "R_TERM_INT_GTX_IMUX21", - "R_TERM_INT_GTX_IMUX22", - "R_TERM_INT_GTX_IMUX23", - "R_TERM_INT_GTX_IMUX24", - "R_TERM_INT_GTX_IMUX25", - "R_TERM_INT_GTX_IMUX26", - "R_TERM_INT_GTX_IMUX27", - "R_TERM_INT_GTX_IMUX28", - "R_TERM_INT_GTX_IMUX29", - "R_TERM_INT_GTX_IMUX3", - "R_TERM_INT_GTX_IMUX30", - "R_TERM_INT_GTX_IMUX31", - "R_TERM_INT_GTX_IMUX32", - "R_TERM_INT_GTX_IMUX33", - "R_TERM_INT_GTX_IMUX34", - "R_TERM_INT_GTX_IMUX35", - "R_TERM_INT_GTX_IMUX36", - "R_TERM_INT_GTX_IMUX37", - "R_TERM_INT_GTX_IMUX38", - "R_TERM_INT_GTX_IMUX39", - "R_TERM_INT_GTX_IMUX4", - "R_TERM_INT_GTX_IMUX40", - "R_TERM_INT_GTX_IMUX41", - "R_TERM_INT_GTX_IMUX42", - "R_TERM_INT_GTX_IMUX43", - "R_TERM_INT_GTX_IMUX44", - "R_TERM_INT_GTX_IMUX45", - "R_TERM_INT_GTX_IMUX46", - "R_TERM_INT_GTX_IMUX47", - "R_TERM_INT_GTX_IMUX5", - "R_TERM_INT_GTX_IMUX6", - "R_TERM_INT_GTX_IMUX7", - "R_TERM_INT_GTX_IMUX8", - "R_TERM_INT_GTX_IMUX9", - "R_TERM_INT_GTX_LOGIC_OUTS_B0", - "R_TERM_INT_GTX_LOGIC_OUTS_B1", - "R_TERM_INT_GTX_LOGIC_OUTS_B10", - "R_TERM_INT_GTX_LOGIC_OUTS_B11", - "R_TERM_INT_GTX_LOGIC_OUTS_B12", - "R_TERM_INT_GTX_LOGIC_OUTS_B13", - "R_TERM_INT_GTX_LOGIC_OUTS_B14", - "R_TERM_INT_GTX_LOGIC_OUTS_B15", - "R_TERM_INT_GTX_LOGIC_OUTS_B16", - "R_TERM_INT_GTX_LOGIC_OUTS_B17", - "R_TERM_INT_GTX_LOGIC_OUTS_B18", - "R_TERM_INT_GTX_LOGIC_OUTS_B19", - "R_TERM_INT_GTX_LOGIC_OUTS_B2", - "R_TERM_INT_GTX_LOGIC_OUTS_B20", - "R_TERM_INT_GTX_LOGIC_OUTS_B21", - "R_TERM_INT_GTX_LOGIC_OUTS_B22", - "R_TERM_INT_GTX_LOGIC_OUTS_B23", - "R_TERM_INT_GTX_LOGIC_OUTS_B3", - "R_TERM_INT_GTX_LOGIC_OUTS_B4", - "R_TERM_INT_GTX_LOGIC_OUTS_B5", - "R_TERM_INT_GTX_LOGIC_OUTS_B6", - "R_TERM_INT_GTX_LOGIC_OUTS_B7", - "R_TERM_INT_GTX_LOGIC_OUTS_B8", - "R_TERM_INT_GTX_LOGIC_OUTS_B9", - "R_TERM_INT_LH0", - "R_TERM_INT_LH1", - "R_TERM_INT_LH2", - "R_TERM_INT_LH3", - "R_TERM_INT_LH4", - "R_TERM_INT_LH5", - "R_TERM_INT_NW2A0", - "R_TERM_INT_NW2A1", - "R_TERM_INT_NW2A2", - "R_TERM_INT_NW2A3", - "R_TERM_INT_NW4A0", - "R_TERM_INT_NW4A1", - "R_TERM_INT_NW4A2", - "R_TERM_INT_NW4A3", - "R_TERM_INT_NW4END0", - "R_TERM_INT_NW4END1", - "R_TERM_INT_NW4END2", - "R_TERM_INT_NW4END3", - "R_TERM_INT_SW2A0", - "R_TERM_INT_SW2A1", - "R_TERM_INT_SW2A2", - "R_TERM_INT_SW2A3", - "R_TERM_INT_SW4A0", - "R_TERM_INT_SW4A1", - "R_TERM_INT_SW4A2", - "R_TERM_INT_SW4A3", - "R_TERM_INT_SW4END0", - "R_TERM_INT_SW4END1", - "R_TERM_INT_SW4END2", - "R_TERM_INT_SW4END3", - "R_TERM_INT_WL1END0", - "R_TERM_INT_WL1END1", - "R_TERM_INT_WL1END2", - "R_TERM_INT_WL1END3", - "R_TERM_INT_WR1END0", - "R_TERM_INT_WR1END1", - "R_TERM_INT_WR1END2", - "R_TERM_INT_WR1END3", - "R_TERM_INT_WW2A0", - "R_TERM_INT_WW2A1", - "R_TERM_INT_WW2A2", - "R_TERM_INT_WW2A3", - "R_TERM_INT_WW2END0", - "R_TERM_INT_WW2END1", - "R_TERM_INT_WW2END2", - "R_TERM_INT_WW2END3", - "R_TERM_INT_WW4A0", - "R_TERM_INT_WW4A1", - "R_TERM_INT_WW4A2", - "R_TERM_INT_WW4A3", - "R_TERM_INT_WW4B0", - "R_TERM_INT_WW4B1", - "R_TERM_INT_WW4B2", - "R_TERM_INT_WW4B3", - "R_TERM_INT_WW4C0", - "R_TERM_INT_WW4C1", - "R_TERM_INT_WW4C2", - "R_TERM_INT_WW4C3", - "R_TERM_INT_WW4END0", - "R_TERM_INT_WW4END1", - "R_TERM_INT_WW4END2", - "R_TERM_INT_WW4END3" - ] + "wires": { + "R_TERM_INT_GTX_BYP0": null, + "R_TERM_INT_GTX_BYP1": null, + "R_TERM_INT_GTX_BYP2": null, + "R_TERM_INT_GTX_BYP3": null, + "R_TERM_INT_GTX_BYP4": null, + "R_TERM_INT_GTX_BYP5": null, + "R_TERM_INT_GTX_BYP6": null, + "R_TERM_INT_GTX_BYP7": null, + "R_TERM_INT_GTX_CLK0": null, + "R_TERM_INT_GTX_CLK1": null, + "R_TERM_INT_GTX_CTRL0": null, + "R_TERM_INT_GTX_CTRL1": null, + "R_TERM_INT_GTX_FAN0": null, + "R_TERM_INT_GTX_FAN1": null, + "R_TERM_INT_GTX_FAN2": null, + "R_TERM_INT_GTX_FAN3": null, + "R_TERM_INT_GTX_FAN4": null, + "R_TERM_INT_GTX_FAN5": null, + "R_TERM_INT_GTX_FAN6": null, + "R_TERM_INT_GTX_FAN7": null, + "R_TERM_INT_GTX_IMUX0": null, + "R_TERM_INT_GTX_IMUX1": null, + "R_TERM_INT_GTX_IMUX10": null, + "R_TERM_INT_GTX_IMUX11": null, + "R_TERM_INT_GTX_IMUX12": null, + "R_TERM_INT_GTX_IMUX13": null, + "R_TERM_INT_GTX_IMUX14": null, + "R_TERM_INT_GTX_IMUX15": null, + "R_TERM_INT_GTX_IMUX16": null, + "R_TERM_INT_GTX_IMUX17": null, + "R_TERM_INT_GTX_IMUX18": null, + "R_TERM_INT_GTX_IMUX19": null, + "R_TERM_INT_GTX_IMUX2": null, + "R_TERM_INT_GTX_IMUX20": null, + "R_TERM_INT_GTX_IMUX21": null, + "R_TERM_INT_GTX_IMUX22": null, + "R_TERM_INT_GTX_IMUX23": null, + "R_TERM_INT_GTX_IMUX24": null, + "R_TERM_INT_GTX_IMUX25": null, + "R_TERM_INT_GTX_IMUX26": null, + "R_TERM_INT_GTX_IMUX27": null, + "R_TERM_INT_GTX_IMUX28": null, + "R_TERM_INT_GTX_IMUX29": null, + "R_TERM_INT_GTX_IMUX3": null, + "R_TERM_INT_GTX_IMUX30": null, + "R_TERM_INT_GTX_IMUX31": null, + "R_TERM_INT_GTX_IMUX32": null, + "R_TERM_INT_GTX_IMUX33": null, + "R_TERM_INT_GTX_IMUX34": null, + "R_TERM_INT_GTX_IMUX35": null, + "R_TERM_INT_GTX_IMUX36": null, + "R_TERM_INT_GTX_IMUX37": null, + "R_TERM_INT_GTX_IMUX38": null, + "R_TERM_INT_GTX_IMUX39": null, + "R_TERM_INT_GTX_IMUX4": null, + "R_TERM_INT_GTX_IMUX40": null, + "R_TERM_INT_GTX_IMUX41": null, + "R_TERM_INT_GTX_IMUX42": null, + "R_TERM_INT_GTX_IMUX43": null, + "R_TERM_INT_GTX_IMUX44": null, + "R_TERM_INT_GTX_IMUX45": null, + "R_TERM_INT_GTX_IMUX46": null, + "R_TERM_INT_GTX_IMUX47": null, + "R_TERM_INT_GTX_IMUX5": null, + "R_TERM_INT_GTX_IMUX6": null, + "R_TERM_INT_GTX_IMUX7": null, + "R_TERM_INT_GTX_IMUX8": null, + "R_TERM_INT_GTX_IMUX9": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B0": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B1": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B10": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B11": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B12": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B13": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B14": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B15": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B16": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B17": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B18": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B19": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B2": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B20": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B21": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B22": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B23": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B3": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B4": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B5": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B6": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B7": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B8": null, + "R_TERM_INT_GTX_LOGIC_OUTS_B9": null, + "R_TERM_INT_LH0": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH1": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH2": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH3": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH4": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_LH5": { + "cap": "13.120", + "res": "4.520" + }, + "R_TERM_INT_NW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_NW4END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_SW4END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WL1END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WR1END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW2END3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4A3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4B3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4C3": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END0": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END1": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END2": { + "cap": "4.200", + "res": "87.290" + }, + "R_TERM_INT_WW4END3": { + "cap": "4.200", + "res": "87.290" + } + } } diff --git a/kintex7/tile_type_TERM_CMT.json b/kintex7/tile_type_TERM_CMT.json index 3790f7c..c640568 100644 --- a/kintex7/tile_type_TERM_CMT.json +++ b/kintex7/tile_type_TERM_CMT.json @@ -2,10 +2,10 @@ "pips": {}, "sites": [], "tile_type": "TERM_CMT", - "wires": [ - "TERM_CMT_FREQ_REF_NS0", - "TERM_CMT_FREQ_REF_NS1", - "TERM_CMT_FREQ_REF_NS2", - "TERM_CMT_FREQ_REF_NS3" - ] + "wires": { + "TERM_CMT_FREQ_REF_NS0": null, + "TERM_CMT_FREQ_REF_NS1": null, + "TERM_CMT_FREQ_REF_NS2": null, + "TERM_CMT_FREQ_REF_NS3": null + } } diff --git a/kintex7/tile_type_T_TERM_INT.json b/kintex7/tile_type_T_TERM_INT.json index 57ff508..0e326d9 100644 --- a/kintex7/tile_type_T_TERM_INT.json +++ b/kintex7/tile_type_T_TERM_INT.json @@ -2,123 +2,213 @@ "pips": {}, "sites": [], "tile_type": "T_TERM_INT", - "wires": [ - "T_TERM_INT_UTURN_LV_R16", - "T_TERM_INT_UTURN_LV_R17", - "T_TERM_INT_UTURN_LV_R2", - "T_TERM_INT_UTURN_LV_R3", - "T_TERM_INT_UTURN_LV_R4", - "T_TERM_INT_UTURN_LV_R5", - "T_TERM_INT_UTURN_LV_R6", - "T_TERM_INT_UTURN_LV_R7", - "T_TERM_INT_UTURN_LV_R9", - "T_TERM_UTURN_INT_ER1BEG_S0", - "T_TERM_UTURN_INT_ER1END3", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", - "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", - "T_TERM_UTURN_INT_LVB0", - "T_TERM_UTURN_INT_LVB1", - "T_TERM_UTURN_INT_LVB2", - "T_TERM_UTURN_INT_LVB3", - "T_TERM_UTURN_INT_LVB4", - "T_TERM_UTURN_INT_LVB5", - "T_TERM_UTURN_INT_LVB_L0", - "T_TERM_UTURN_INT_LVB_L1", - "T_TERM_UTURN_INT_LVB_L2", - "T_TERM_UTURN_INT_LVB_L3", - "T_TERM_UTURN_INT_LVB_L4", - "T_TERM_UTURN_INT_LVB_L5", - "T_TERM_UTURN_INT_LV_L16", - "T_TERM_UTURN_INT_LV_L17", - "T_TERM_UTURN_INT_LV_L2", - "T_TERM_UTURN_INT_LV_L3", - "T_TERM_UTURN_INT_LV_L4", - "T_TERM_UTURN_INT_LV_L5", - "T_TERM_UTURN_INT_LV_L6", - "T_TERM_UTURN_INT_LV_L7", - "T_TERM_UTURN_INT_LV_L9", - "T_TERM_UTURN_INT_SE2A0", - "T_TERM_UTURN_INT_SE2A1", - "T_TERM_UTURN_INT_SE2A2", - "T_TERM_UTURN_INT_SE2A3", - "T_TERM_UTURN_INT_SE6B0", - "T_TERM_UTURN_INT_SE6B1", - "T_TERM_UTURN_INT_SE6B2", - "T_TERM_UTURN_INT_SE6B3", - "T_TERM_UTURN_INT_SE6C0", - "T_TERM_UTURN_INT_SE6C1", - "T_TERM_UTURN_INT_SE6C2", - "T_TERM_UTURN_INT_SE6C3", - "T_TERM_UTURN_INT_SE6D0", - "T_TERM_UTURN_INT_SE6D1", - "T_TERM_UTURN_INT_SE6D2", - "T_TERM_UTURN_INT_SE6D3", - "T_TERM_UTURN_INT_SE6E0", - "T_TERM_UTURN_INT_SE6E1", - "T_TERM_UTURN_INT_SE6E2", - "T_TERM_UTURN_INT_SE6E3", - "T_TERM_UTURN_INT_SL1END0", - "T_TERM_UTURN_INT_SL1END1", - "T_TERM_UTURN_INT_SL1END2", - "T_TERM_UTURN_INT_SL1END3", - "T_TERM_UTURN_INT_SR1END1", - "T_TERM_UTURN_INT_SR1END2", - "T_TERM_UTURN_INT_SR1END3", - "T_TERM_UTURN_INT_SS2A0", - "T_TERM_UTURN_INT_SS2A1", - "T_TERM_UTURN_INT_SS2A2", - "T_TERM_UTURN_INT_SS2A3", - "T_TERM_UTURN_INT_SS2END0", - "T_TERM_UTURN_INT_SS2END1", - "T_TERM_UTURN_INT_SS2END2", - "T_TERM_UTURN_INT_SS2END3", - "T_TERM_UTURN_INT_SS6A0", - "T_TERM_UTURN_INT_SS6A1", - "T_TERM_UTURN_INT_SS6A2", - "T_TERM_UTURN_INT_SS6A3", - "T_TERM_UTURN_INT_SS6B0", - "T_TERM_UTURN_INT_SS6B1", - "T_TERM_UTURN_INT_SS6B2", - "T_TERM_UTURN_INT_SS6B3", - "T_TERM_UTURN_INT_SS6C0", - "T_TERM_UTURN_INT_SS6C1", - "T_TERM_UTURN_INT_SS6C2", - "T_TERM_UTURN_INT_SS6C3", - "T_TERM_UTURN_INT_SS6D0", - "T_TERM_UTURN_INT_SS6D1", - "T_TERM_UTURN_INT_SS6D2", - "T_TERM_UTURN_INT_SS6D3", - "T_TERM_UTURN_INT_SS6E0", - "T_TERM_UTURN_INT_SS6E1", - "T_TERM_UTURN_INT_SS6E2", - "T_TERM_UTURN_INT_SS6E3", - "T_TERM_UTURN_INT_SS6END0", - "T_TERM_UTURN_INT_SS6END1", - "T_TERM_UTURN_INT_SS6END2", - "T_TERM_UTURN_INT_SS6END3", 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b/kintex7/tile_type_VBRK.json @@ -2,132 +2,495 @@ "pips": {}, "sites": [], "tile_type": "VBRK", - "wires": [ - "VBRK_EE2A0", - "VBRK_EE2A1", - "VBRK_EE2A2", - "VBRK_EE2A3", - "VBRK_EE2BEG0", - "VBRK_EE2BEG1", - "VBRK_EE2BEG2", - "VBRK_EE2BEG3", - "VBRK_EE4A0", - "VBRK_EE4A1", - "VBRK_EE4A2", - "VBRK_EE4A3", - "VBRK_EE4B0", - "VBRK_EE4B1", - "VBRK_EE4B2", - "VBRK_EE4B3", - "VBRK_EE4BEG0", - "VBRK_EE4BEG1", - "VBRK_EE4BEG2", - "VBRK_EE4BEG3", - "VBRK_EE4C0", - "VBRK_EE4C1", - "VBRK_EE4C2", - "VBRK_EE4C3", - "VBRK_EL1BEG0", - "VBRK_EL1BEG1", - "VBRK_EL1BEG2", - "VBRK_EL1BEG3", - "VBRK_ER1BEG0", - "VBRK_ER1BEG1", - "VBRK_ER1BEG2", - "VBRK_ER1BEG3", - "VBRK_LH1", - "VBRK_LH10", - "VBRK_LH11", - "VBRK_LH12", - "VBRK_LH2", - "VBRK_LH3", - "VBRK_LH4", - "VBRK_LH5", - "VBRK_LH6", - "VBRK_LH7", - "VBRK_LH8", - "VBRK_LH9", - "VBRK_MONITOR_N", - "VBRK_MONITOR_P", - "VBRK_NE2A0", - "VBRK_NE2A1", - "VBRK_NE2A2", - "VBRK_NE2A3", - "VBRK_NE4BEG0", - "VBRK_NE4BEG1", - "VBRK_NE4BEG2", - "VBRK_NE4BEG3", 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"1.620", + "res": "12.110" + }, + "VBRK_ER1BEG2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_ER1BEG3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_LH1": { + "cap": "2.300", + "res": "0.580" + }, + "VBRK_LH10": null, + "VBRK_LH11": null, + "VBRK_LH12": null, + "VBRK_LH2": { + "cap": "2.300", + "res": "0.580" + }, + "VBRK_LH3": { + "cap": "2.300", + "res": "0.580" + }, + "VBRK_LH4": { + "cap": "2.300", + "res": "0.580" + }, + "VBRK_LH5": { + "cap": "2.300", + "res": "0.580" + }, + "VBRK_LH6": { + "cap": "2.300", + "res": "0.580" + }, + "VBRK_LH7": { + "cap": "2.300", + "res": "0.580" + }, + "VBRK_LH8": { + "cap": "2.300", + "res": "0.580" + }, + "VBRK_LH9": { + "cap": "2.300", + "res": "0.580" + }, + "VBRK_MONITOR_N": null, + "VBRK_MONITOR_P": null, + "VBRK_NE2A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE2A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE2A2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NE2A3": { + "cap": "1.620", + "res": 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"1.620", + "res": "12.110" + }, + "VBRK_NW4END1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NW4END2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_NW4END3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE2A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE2A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE2A2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE2A3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE4BEG0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE4BEG1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE4BEG2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE4BEG3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE4C0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE4C1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE4C2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SE4C3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW2A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW2A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW2A2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW2A3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW4A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW4A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW4A2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW4A3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW4END0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW4END1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW4END2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_SW4END3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WL1END0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WL1END1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WL1END2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WL1END3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WR1END0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WR1END1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WR1END2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WR1END3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW2A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW2A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW2A2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW2A3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW2END0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW2END1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW2END2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW2END3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4A0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4A1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4A2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4A3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4B0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4B1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4B2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4B3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4C0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4C1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4C2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4C3": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4END0": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4END1": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4END2": { + "cap": "1.620", + "res": "12.110" + }, + "VBRK_WW4END3": { + "cap": "1.620", + "res": "12.110" + } + } } diff --git a/kintex7/tile_type_VBRK_EXT.json b/kintex7/tile_type_VBRK_EXT.json index 3a4ab8d..660010a 100644 --- a/kintex7/tile_type_VBRK_EXT.json +++ b/kintex7/tile_type_VBRK_EXT.json @@ -2,98 +2,98 @@ "pips": {}, "sites": [], "tile_type": "VBRK_EXT", - "wires": [ - "VBRK_EXT_BYP0", - "VBRK_EXT_BYP1", - "VBRK_EXT_BYP2", - "VBRK_EXT_BYP3", - "VBRK_EXT_BYP4", - "VBRK_EXT_BYP5", - "VBRK_EXT_BYP6", - "VBRK_EXT_BYP7", - "VBRK_EXT_CLK0", - "VBRK_EXT_CLK1", - "VBRK_EXT_CTRL0", - "VBRK_EXT_CTRL1", - "VBRK_EXT_FAN0", - "VBRK_EXT_FAN1", - "VBRK_EXT_FAN2", - "VBRK_EXT_FAN3", - "VBRK_EXT_FAN4", - "VBRK_EXT_FAN5", - "VBRK_EXT_FAN6", - "VBRK_EXT_FAN7", - "VBRK_EXT_IMUX0", - "VBRK_EXT_IMUX1", - "VBRK_EXT_IMUX10", - "VBRK_EXT_IMUX11", - "VBRK_EXT_IMUX12", - "VBRK_EXT_IMUX13", - "VBRK_EXT_IMUX14", - "VBRK_EXT_IMUX15", - "VBRK_EXT_IMUX16", - "VBRK_EXT_IMUX17", - "VBRK_EXT_IMUX18", - "VBRK_EXT_IMUX19", - "VBRK_EXT_IMUX2", - "VBRK_EXT_IMUX20", - "VBRK_EXT_IMUX21", - "VBRK_EXT_IMUX22", - "VBRK_EXT_IMUX23", - "VBRK_EXT_IMUX24", - "VBRK_EXT_IMUX25", - "VBRK_EXT_IMUX26", - "VBRK_EXT_IMUX27", - "VBRK_EXT_IMUX28", - "VBRK_EXT_IMUX29", - "VBRK_EXT_IMUX3", - "VBRK_EXT_IMUX30", - "VBRK_EXT_IMUX31", - "VBRK_EXT_IMUX32", - "VBRK_EXT_IMUX33", - "VBRK_EXT_IMUX34", - "VBRK_EXT_IMUX35", - "VBRK_EXT_IMUX36", - "VBRK_EXT_IMUX37", - "VBRK_EXT_IMUX38", - "VBRK_EXT_IMUX39", - "VBRK_EXT_IMUX4", - "VBRK_EXT_IMUX40", - "VBRK_EXT_IMUX41", - "VBRK_EXT_IMUX42", - "VBRK_EXT_IMUX43", - "VBRK_EXT_IMUX44", - "VBRK_EXT_IMUX45", - "VBRK_EXT_IMUX46", - "VBRK_EXT_IMUX47", - "VBRK_EXT_IMUX5", - "VBRK_EXT_IMUX6", - "VBRK_EXT_IMUX7", - "VBRK_EXT_IMUX8", - "VBRK_EXT_IMUX9", - "VBRK_EXT_LOGIC_OUTS_B0", - "VBRK_EXT_LOGIC_OUTS_B1", - "VBRK_EXT_LOGIC_OUTS_B10", - "VBRK_EXT_LOGIC_OUTS_B11", - "VBRK_EXT_LOGIC_OUTS_B12", - "VBRK_EXT_LOGIC_OUTS_B13", - "VBRK_EXT_LOGIC_OUTS_B14", - "VBRK_EXT_LOGIC_OUTS_B15", - "VBRK_EXT_LOGIC_OUTS_B16", - "VBRK_EXT_LOGIC_OUTS_B17", - "VBRK_EXT_LOGIC_OUTS_B18", - "VBRK_EXT_LOGIC_OUTS_B19", - "VBRK_EXT_LOGIC_OUTS_B2", - "VBRK_EXT_LOGIC_OUTS_B20", - "VBRK_EXT_LOGIC_OUTS_B21", - "VBRK_EXT_LOGIC_OUTS_B22", - "VBRK_EXT_LOGIC_OUTS_B23", - "VBRK_EXT_LOGIC_OUTS_B3", - "VBRK_EXT_LOGIC_OUTS_B4", - "VBRK_EXT_LOGIC_OUTS_B5", - "VBRK_EXT_LOGIC_OUTS_B6", - "VBRK_EXT_LOGIC_OUTS_B7", - "VBRK_EXT_LOGIC_OUTS_B8", - "VBRK_EXT_LOGIC_OUTS_B9" - ] + "wires": { + "VBRK_EXT_BYP0": null, + "VBRK_EXT_BYP1": null, + "VBRK_EXT_BYP2": null, + "VBRK_EXT_BYP3": null, + "VBRK_EXT_BYP4": null, + "VBRK_EXT_BYP5": null, + "VBRK_EXT_BYP6": null, + "VBRK_EXT_BYP7": null, + "VBRK_EXT_CLK0": null, + "VBRK_EXT_CLK1": null, + "VBRK_EXT_CTRL0": null, + "VBRK_EXT_CTRL1": null, + "VBRK_EXT_FAN0": null, + "VBRK_EXT_FAN1": null, + "VBRK_EXT_FAN2": null, + "VBRK_EXT_FAN3": null, + "VBRK_EXT_FAN4": null, + "VBRK_EXT_FAN5": null, + "VBRK_EXT_FAN6": null, + "VBRK_EXT_FAN7": null, + "VBRK_EXT_IMUX0": null, + "VBRK_EXT_IMUX1": null, + "VBRK_EXT_IMUX10": null, + "VBRK_EXT_IMUX11": null, + "VBRK_EXT_IMUX12": null, + "VBRK_EXT_IMUX13": null, + "VBRK_EXT_IMUX14": null, + "VBRK_EXT_IMUX15": null, + "VBRK_EXT_IMUX16": null, + "VBRK_EXT_IMUX17": null, + "VBRK_EXT_IMUX18": null, + "VBRK_EXT_IMUX19": null, + "VBRK_EXT_IMUX2": null, + "VBRK_EXT_IMUX20": null, + "VBRK_EXT_IMUX21": null, + "VBRK_EXT_IMUX22": null, + "VBRK_EXT_IMUX23": null, + "VBRK_EXT_IMUX24": null, + "VBRK_EXT_IMUX25": null, + "VBRK_EXT_IMUX26": null, + "VBRK_EXT_IMUX27": null, + "VBRK_EXT_IMUX28": null, + "VBRK_EXT_IMUX29": null, + "VBRK_EXT_IMUX3": null, + "VBRK_EXT_IMUX30": null, + "VBRK_EXT_IMUX31": null, + "VBRK_EXT_IMUX32": null, + "VBRK_EXT_IMUX33": null, + "VBRK_EXT_IMUX34": null, + "VBRK_EXT_IMUX35": null, + "VBRK_EXT_IMUX36": null, + "VBRK_EXT_IMUX37": null, + "VBRK_EXT_IMUX38": null, + "VBRK_EXT_IMUX39": null, + "VBRK_EXT_IMUX4": null, + "VBRK_EXT_IMUX40": null, + "VBRK_EXT_IMUX41": null, + "VBRK_EXT_IMUX42": null, + "VBRK_EXT_IMUX43": null, + "VBRK_EXT_IMUX44": null, + "VBRK_EXT_IMUX45": null, + "VBRK_EXT_IMUX46": null, + "VBRK_EXT_IMUX47": null, + "VBRK_EXT_IMUX5": null, + "VBRK_EXT_IMUX6": null, + "VBRK_EXT_IMUX7": null, + "VBRK_EXT_IMUX8": null, + "VBRK_EXT_IMUX9": null, + "VBRK_EXT_LOGIC_OUTS_B0": null, + "VBRK_EXT_LOGIC_OUTS_B1": null, + "VBRK_EXT_LOGIC_OUTS_B10": null, + "VBRK_EXT_LOGIC_OUTS_B11": null, + "VBRK_EXT_LOGIC_OUTS_B12": null, + "VBRK_EXT_LOGIC_OUTS_B13": null, + "VBRK_EXT_LOGIC_OUTS_B14": null, + "VBRK_EXT_LOGIC_OUTS_B15": null, + "VBRK_EXT_LOGIC_OUTS_B16": null, + "VBRK_EXT_LOGIC_OUTS_B17": null, + "VBRK_EXT_LOGIC_OUTS_B18": null, + "VBRK_EXT_LOGIC_OUTS_B19": null, + "VBRK_EXT_LOGIC_OUTS_B2": null, + "VBRK_EXT_LOGIC_OUTS_B20": null, + "VBRK_EXT_LOGIC_OUTS_B21": null, + "VBRK_EXT_LOGIC_OUTS_B22": null, + "VBRK_EXT_LOGIC_OUTS_B23": null, + "VBRK_EXT_LOGIC_OUTS_B3": null, + "VBRK_EXT_LOGIC_OUTS_B4": null, + "VBRK_EXT_LOGIC_OUTS_B5": null, + "VBRK_EXT_LOGIC_OUTS_B6": null, + "VBRK_EXT_LOGIC_OUTS_B7": null, + "VBRK_EXT_LOGIC_OUTS_B8": null, + "VBRK_EXT_LOGIC_OUTS_B9": null + } } diff --git a/kintex7/tile_type_VFRAME.json b/kintex7/tile_type_VFRAME.json index 393a2f7..34affe1 100644 --- a/kintex7/tile_type_VFRAME.json +++ b/kintex7/tile_type_VFRAME.json @@ -2,228 +2,600 @@ "pips": {}, "sites": [], "tile_type": "VFRAME", - "wires": [ - "VFRAME_BLOCK_OUTS_B0", - "VFRAME_BLOCK_OUTS_B1", - "VFRAME_BLOCK_OUTS_B2", - "VFRAME_BLOCK_OUTS_B3", - "VFRAME_BYP0", - "VFRAME_BYP1", - "VFRAME_BYP2", - "VFRAME_BYP3", - "VFRAME_BYP4", - "VFRAME_BYP5", - "VFRAME_BYP6", - "VFRAME_BYP7", - "VFRAME_CLK0", - "VFRAME_CLK1", - "VFRAME_CTRL0", - "VFRAME_CTRL1", - "VFRAME_EE2A0", - "VFRAME_EE2A1", - "VFRAME_EE2A2", - "VFRAME_EE2A3", - "VFRAME_EE2BEG0", - "VFRAME_EE2BEG1", - "VFRAME_EE2BEG2", - "VFRAME_EE2BEG3", - "VFRAME_EE4A0", - "VFRAME_EE4A1", - "VFRAME_EE4A2", - "VFRAME_EE4A3", - "VFRAME_EE4B0", - "VFRAME_EE4B1", - "VFRAME_EE4B2", - "VFRAME_EE4B3", - "VFRAME_EE4BEG0", - "VFRAME_EE4BEG1", - "VFRAME_EE4BEG2", - "VFRAME_EE4BEG3", - "VFRAME_EE4C0", - "VFRAME_EE4C1", - "VFRAME_EE4C2", - "VFRAME_EE4C3", - "VFRAME_EL1BEG0", - "VFRAME_EL1BEG1", - "VFRAME_EL1BEG2", - "VFRAME_EL1BEG3", - "VFRAME_ER1BEG0", - "VFRAME_ER1BEG1", - "VFRAME_ER1BEG2", - "VFRAME_ER1BEG3", - "VFRAME_FAN0", - "VFRAME_FAN1", - "VFRAME_FAN2", - "VFRAME_FAN3", - "VFRAME_FAN4", - "VFRAME_FAN5", - "VFRAME_FAN6", - "VFRAME_FAN7", - "VFRAME_IMUX0", - "VFRAME_IMUX1", - "VFRAME_IMUX10", - "VFRAME_IMUX11", - "VFRAME_IMUX12", - "VFRAME_IMUX13", - "VFRAME_IMUX14", - "VFRAME_IMUX15", - "VFRAME_IMUX16", - "VFRAME_IMUX17", - "VFRAME_IMUX18", - "VFRAME_IMUX19", - "VFRAME_IMUX2", - "VFRAME_IMUX20", - "VFRAME_IMUX21", - "VFRAME_IMUX22", - "VFRAME_IMUX23", - "VFRAME_IMUX24", - "VFRAME_IMUX25", - "VFRAME_IMUX26", - "VFRAME_IMUX27", - "VFRAME_IMUX28", - "VFRAME_IMUX29", - "VFRAME_IMUX3", - "VFRAME_IMUX30", - "VFRAME_IMUX31", - "VFRAME_IMUX32", - "VFRAME_IMUX33", - "VFRAME_IMUX34", - "VFRAME_IMUX35", - "VFRAME_IMUX36", - "VFRAME_IMUX37", - "VFRAME_IMUX38", - "VFRAME_IMUX39", - "VFRAME_IMUX4", - "VFRAME_IMUX40", - "VFRAME_IMUX41", - "VFRAME_IMUX42", - "VFRAME_IMUX43", - "VFRAME_IMUX44", - "VFRAME_IMUX45", - "VFRAME_IMUX46", - "VFRAME_IMUX47", - "VFRAME_IMUX5", - "VFRAME_IMUX6", - "VFRAME_IMUX7", - "VFRAME_IMUX8", - "VFRAME_IMUX9", - "VFRAME_LH1", - "VFRAME_LH10", - "VFRAME_LH11", - "VFRAME_LH12", - "VFRAME_LH2", - "VFRAME_LH3", - "VFRAME_LH4", - "VFRAME_LH5", - "VFRAME_LH6", - "VFRAME_LH7", - "VFRAME_LH8", - "VFRAME_LH9", - "VFRAME_LOGIC_OUTS_B0", - "VFRAME_LOGIC_OUTS_B1", - "VFRAME_LOGIC_OUTS_B10", - "VFRAME_LOGIC_OUTS_B11", - "VFRAME_LOGIC_OUTS_B12", - "VFRAME_LOGIC_OUTS_B13", - "VFRAME_LOGIC_OUTS_B14", - "VFRAME_LOGIC_OUTS_B15", - "VFRAME_LOGIC_OUTS_B16", - "VFRAME_LOGIC_OUTS_B17", - "VFRAME_LOGIC_OUTS_B18", - "VFRAME_LOGIC_OUTS_B19", - "VFRAME_LOGIC_OUTS_B2", - "VFRAME_LOGIC_OUTS_B20", - "VFRAME_LOGIC_OUTS_B21", - "VFRAME_LOGIC_OUTS_B22", - "VFRAME_LOGIC_OUTS_B23", - "VFRAME_LOGIC_OUTS_B3", - "VFRAME_LOGIC_OUTS_B4", - "VFRAME_LOGIC_OUTS_B5", - "VFRAME_LOGIC_OUTS_B6", - "VFRAME_LOGIC_OUTS_B7", - "VFRAME_LOGIC_OUTS_B8", - "VFRAME_LOGIC_OUTS_B9", - "VFRAME_MONITOR_N", - "VFRAME_MONITOR_P", - "VFRAME_NE2A0", - "VFRAME_NE2A1", - "VFRAME_NE2A2", - "VFRAME_NE2A3", - "VFRAME_NE4BEG0", - "VFRAME_NE4BEG1", - "VFRAME_NE4BEG2", - "VFRAME_NE4BEG3", - "VFRAME_NE4C0", - "VFRAME_NE4C1", - "VFRAME_NE4C2", - "VFRAME_NE4C3", - "VFRAME_NW2A0", - "VFRAME_NW2A1", - "VFRAME_NW2A2", - "VFRAME_NW2A3", - "VFRAME_NW4A0", - "VFRAME_NW4A1", - "VFRAME_NW4A2", - "VFRAME_NW4A3", - "VFRAME_NW4END0", - "VFRAME_NW4END1", - "VFRAME_NW4END2", - "VFRAME_NW4END3", - "VFRAME_SE2A0", - "VFRAME_SE2A1", - "VFRAME_SE2A2", - "VFRAME_SE2A3", - "VFRAME_SE4BEG0", - "VFRAME_SE4BEG1", - "VFRAME_SE4BEG2", - "VFRAME_SE4BEG3", - "VFRAME_SE4C0", - "VFRAME_SE4C1", - "VFRAME_SE4C2", - "VFRAME_SE4C3", - "VFRAME_SW2A0", - "VFRAME_SW2A1", - "VFRAME_SW2A2", - "VFRAME_SW2A3", - "VFRAME_SW4A0", - "VFRAME_SW4A1", - "VFRAME_SW4A2", - "VFRAME_SW4A3", - "VFRAME_SW4END0", - "VFRAME_SW4END1", - "VFRAME_SW4END2", - "VFRAME_SW4END3", - "VFRAME_WL1END0", - "VFRAME_WL1END1", - "VFRAME_WL1END2", - "VFRAME_WL1END3", - "VFRAME_WR1END0", - "VFRAME_WR1END1", - "VFRAME_WR1END2", - "VFRAME_WR1END3", - "VFRAME_WW2A0", - "VFRAME_WW2A1", - "VFRAME_WW2A2", - "VFRAME_WW2A3", - "VFRAME_WW2END0", - "VFRAME_WW2END1", - "VFRAME_WW2END2", - "VFRAME_WW2END3", - "VFRAME_WW4A0", - "VFRAME_WW4A1", - "VFRAME_WW4A2", - "VFRAME_WW4A3", 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